[PATCH v2 0/3] Add R5F nodes on TI K3 AM64x SoCs

[PATCH v2 0/3] Add R5F nodes on TI K3 AM64x SoCs

[Suman Anna]

Hi Nishanth,

This is a rebased version of the K3 AM64x R5F node series posted previously.
Please see the v1 cover-letter for all the functional details [1]. I have
dropped Patch 4 [2] from the previous series as per the discussion and agreed
upon in [2] until we align on the longer-term memory utilization of OCM RAM.

Patches are on top of your latest staged ti-k3-dts-next branch commit
d65f069e50a3 (arm64: dts: ti: Drop reg-io-width/reg-shift from UART nodes")
+ Aswath's [PATCH v4 0/3] AM64: Update the locations of various elements in SRAM
series (can't see the links on lakml patchworks).

Bjorn has staged a tag from remoteproc tree with just the bindings [3]
that you can use for merging this series for v5.14. The driver support
will come through remoteproc tree.

I have validated the IPC functionality using System Firmware v2021.01a
with appropriate U-Boot that goes along with Aswath's series and corresponding
legacy PDK IPC example firmwares.

regards
Suman

[1] https://patchwork.kernel.org/project/linux-arm-kernel/cover/20210528144718.25132-1-s-anna@ti.com/
[2] https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210528144718.25132-5-s-anna@ti.com/
[3] https://git.kernel.org/pub/scm/linux/kernel/git/andersson/remoteproc.git/log/?h=20210327143117.1840-2-s-anna@ti.com 

Suman Anna (3):
  arm64: dts: ti: k3-am64-main: Add MAIN domain R5F cluster nodes
  arm64: dts: ti: k3-am642-evm/sk: Add mailboxes to R5Fs
  arm64: dts: ti: k3-am642-evm/sk: Add DDR carveout memory nodes for
    R5Fs

 arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 84 ++++++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am642-evm.dts  | 78 ++++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am642-sk.dts   | 78 ++++++++++++++++++++++
 3 files changed, 240 insertions(+)

-- 
2.30.1

[PATCH v2 0/3] Add R5F nodes on TI K3 AM64x SoCs

[Suman Anna]

Hi Nishanth,

This is a rebased version of the K3 AM64x R5F node series posted previously.
Please see the v1 cover-letter for all the functional details [1]. I have
dropped Patch 4 [2] from the previous series as per the discussion and agreed
upon in [2] until we align on the longer-term memory utilization of OCM RAM.

Patches are on top of your latest staged ti-k3-dts-next branch commit
d65f069e50a3 (arm64: dts: ti: Drop reg-io-width/reg-shift from UART nodes")
+ Aswath's [PATCH v4 0/3] AM64: Update the locations of various elements in SRAM
series (can't see the links on lakml patchworks).

Bjorn has staged a tag from remoteproc tree with just the bindings [3]
that you can use for merging this series for v5.14. The driver support
will come through remoteproc tree.

I have validated the IPC functionality using System Firmware v2021.01a
with appropriate U-Boot that goes along with Aswath's series and corresponding
legacy PDK IPC example firmwares.

regards
Suman

[1] https://patchwork.kernel.org/project/linux-arm-kernel/cover/20210528144718.25132-1-s-anna@ti.com/
[2] https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210528144718.25132-5-s-anna@ti.com/
[3] https://git.kernel.org/pub/scm/linux/kernel/git/andersson/remoteproc.git/log/?h=20210327143117.1840-2-s-anna@ti.com 

Suman Anna (3):
  arm64: dts: ti: k3-am64-main: Add MAIN domain R5F cluster nodes
  arm64: dts: ti: k3-am642-evm/sk: Add mailboxes to R5Fs
  arm64: dts: ti: k3-am642-evm/sk: Add DDR carveout memory nodes for
    R5Fs

 arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 84 ++++++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am642-evm.dts  | 78 ++++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am642-sk.dts   | 78 ++++++++++++++++++++++
 3 files changed, 240 insertions(+)

-- 
2.30.1


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 1/3] arm64: dts: ti: k3-am64-main: Add MAIN domain R5F cluster nodes

[Suman Anna]

The AM64x SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. Both the R5F clusters are present within the
MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be
configured at boot time to be either run in a new "Single-CPU" mode
or in an Asymmetric Multi Processing (AMP) fashion in Split-mode.
The mode is restricted to "Single-CPU" on some devices with the
appropriate eFuse bit set, but the most common devices support both
modes. These subsystems have 64 KB each Tightly-Coupled Memory (TCM)
internal memories for each core split between two banks - ATCM and
BTCM (further interleaved into two banks). The TCMs of both Cores
are combined in Single-CPU mode to provide a larger 128 KB of memory.
The other notable difference is that the TCMs are spaced 1 MB apart
on these SoCs unlike the existing SoCs.

Add the DT nodes for both these MAIN domain R5F cluster/subsystems,
the two R5F cores are added as child nodes to each of the corresponding
R5F cluster node. Both the clusters are configured to run in Split mode
by default, with the ATCMs enabled to allow the R5 cores to execute
code from DDR with boot-strapping code from ATCM. The inter-processor
communication between the main A72 cores and these processors is
achieved through shared memory and Mailboxes.

The following firmware names are used by default for these cores, and
can be overridden in a board dts file if desired:
  MAIN R5FSS0 Core0: am64-main-r5f0_0-fw (both in Single-CPU & Split modes)
  MAIN R5FSS0 Core1: am64-main-r5f0_1-fw (needed only in Split mode)
  MAIN R5FSS1 Core0: am64-main-r5f1_0-fw (both in Single-CPU & Split modes)
  MAIN R5FSS1 Core1: am64-main-r5f1_1-fw (needed only in Split mode)

NOTE:
A R5FSS cluster can be configured in "Single-CPU" mode by using a
value of 2 for the "ti,cluster-mode" property. Value of 1 is not
permitted (fails the dtbs_check).

Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2:
No code changes, rebased and retained the presence after the mailbox nodes

 arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 84 ++++++++++++++++++++++++
 1 file changed, 84 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 7ab3652dfdfb..73e6b0f10879 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -694,6 +694,90 @@ mailbox0_cluster7: mailbox@29070000 {
 		ti,mbox-num-fifos = <16>;
 	};
 
+	main_r5fss0: r5fss@78000000 {
+		compatible = "ti,am64-r5fss";
+		ti,cluster-mode = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x78000000 0x00 0x78000000 0x10000>,
+			 <0x78100000 0x00 0x78100000 0x10000>,
+			 <0x78200000 0x00 0x78200000 0x08000>,
+			 <0x78300000 0x00 0x78300000 0x08000>;
+		power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
+
+		main_r5fss0_core0: r5f@78000000 {
+			compatible = "ti,am64-r5f";
+			reg = <0x78000000 0x00010000>,
+			      <0x78100000 0x00010000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <121>;
+			ti,sci-proc-ids = <0x01 0xff>;
+			resets = <&k3_reset 121 1>;
+			firmware-name = "am64-main-r5f0_0-fw";
+			ti,atcm-enable = <1>;
+			ti,btcm-enable = <1>;
+			ti,loczrama = <1>;
+		};
+
+		main_r5fss0_core1: r5f@78200000 {
+			compatible = "ti,am64-r5f";
+			reg = <0x78200000 0x00008000>,
+			      <0x78300000 0x00008000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <122>;
+			ti,sci-proc-ids = <0x02 0xff>;
+			resets = <&k3_reset 122 1>;
+			firmware-name = "am64-main-r5f0_1-fw";
+			ti,atcm-enable = <1>;
+			ti,btcm-enable = <1>;
+			ti,loczrama = <1>;
+		};
+	};
+
+	main_r5fss1: r5fss@78400000 {
+		compatible = "ti,am64-r5fss";
+		ti,cluster-mode = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x78400000 0x00 0x78400000 0x10000>,
+			 <0x78500000 0x00 0x78500000 0x10000>,
+			 <0x78600000 0x00 0x78600000 0x08000>,
+			 <0x78700000 0x00 0x78700000 0x08000>;
+		power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
+
+		main_r5fss1_core0: r5f@78400000 {
+			compatible = "ti,am64-r5f";
+			reg = <0x78400000 0x00010000>,
+			      <0x78500000 0x00010000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <123>;
+			ti,sci-proc-ids = <0x06 0xff>;
+			resets = <&k3_reset 123 1>;
+			firmware-name = "am64-main-r5f1_0-fw";
+			ti,atcm-enable = <1>;
+			ti,btcm-enable = <1>;
+			ti,loczrama = <1>;
+		};
+
+		main_r5fss1_core1: r5f@78600000 {
+			compatible = "ti,am64-r5f";
+			reg = <0x78600000 0x00008000>,
+			      <0x78700000 0x00008000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <124>;
+			ti,sci-proc-ids = <0x07 0xff>;
+			resets = <&k3_reset 124 1>;
+			firmware-name = "am64-main-r5f1_1-fw";
+			ti,atcm-enable = <1>;
+			ti,btcm-enable = <1>;
+			ti,loczrama = <1>;
+		};
+	};
+
 	serdes_wiz0: wiz@f000000 {
 		compatible = "ti,am64-wiz-10g";
 		#address-cells = <1>;
-- 
2.30.1

[PATCH v2 1/3] arm64: dts: ti: k3-am64-main: Add MAIN domain R5F cluster nodes

[Suman Anna]

The AM64x SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. Both the R5F clusters are present within the
MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be
configured at boot time to be either run in a new "Single-CPU" mode
or in an Asymmetric Multi Processing (AMP) fashion in Split-mode.
The mode is restricted to "Single-CPU" on some devices with the
appropriate eFuse bit set, but the most common devices support both
modes. These subsystems have 64 KB each Tightly-Coupled Memory (TCM)
internal memories for each core split between two banks - ATCM and
BTCM (further interleaved into two banks). The TCMs of both Cores
are combined in Single-CPU mode to provide a larger 128 KB of memory.
The other notable difference is that the TCMs are spaced 1 MB apart
on these SoCs unlike the existing SoCs.

Add the DT nodes for both these MAIN domain R5F cluster/subsystems,
the two R5F cores are added as child nodes to each of the corresponding
R5F cluster node. Both the clusters are configured to run in Split mode
by default, with the ATCMs enabled to allow the R5 cores to execute
code from DDR with boot-strapping code from ATCM. The inter-processor
communication between the main A72 cores and these processors is
achieved through shared memory and Mailboxes.

The following firmware names are used by default for these cores, and
can be overridden in a board dts file if desired:
  MAIN R5FSS0 Core0: am64-main-r5f0_0-fw (both in Single-CPU & Split modes)
  MAIN R5FSS0 Core1: am64-main-r5f0_1-fw (needed only in Split mode)
  MAIN R5FSS1 Core0: am64-main-r5f1_0-fw (both in Single-CPU & Split modes)
  MAIN R5FSS1 Core1: am64-main-r5f1_1-fw (needed only in Split mode)

NOTE:
A R5FSS cluster can be configured in "Single-CPU" mode by using a
value of 2 for the "ti,cluster-mode" property. Value of 1 is not
permitted (fails the dtbs_check).

Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2:
No code changes, rebased and retained the presence after the mailbox nodes

 arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 84 ++++++++++++++++++++++++
 1 file changed, 84 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 7ab3652dfdfb..73e6b0f10879 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -694,6 +694,90 @@ mailbox0_cluster7: mailbox@29070000 {
 		ti,mbox-num-fifos = <16>;
 	};
 
+	main_r5fss0: r5fss@78000000 {
+		compatible = "ti,am64-r5fss";
+		ti,cluster-mode = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x78000000 0x00 0x78000000 0x10000>,
+			 <0x78100000 0x00 0x78100000 0x10000>,
+			 <0x78200000 0x00 0x78200000 0x08000>,
+			 <0x78300000 0x00 0x78300000 0x08000>;
+		power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
+
+		main_r5fss0_core0: r5f@78000000 {
+			compatible = "ti,am64-r5f";
+			reg = <0x78000000 0x00010000>,
+			      <0x78100000 0x00010000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <121>;
+			ti,sci-proc-ids = <0x01 0xff>;
+			resets = <&k3_reset 121 1>;
+			firmware-name = "am64-main-r5f0_0-fw";
+			ti,atcm-enable = <1>;
+			ti,btcm-enable = <1>;
+			ti,loczrama = <1>;
+		};
+
+		main_r5fss0_core1: r5f@78200000 {
+			compatible = "ti,am64-r5f";
+			reg = <0x78200000 0x00008000>,
+			      <0x78300000 0x00008000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <122>;
+			ti,sci-proc-ids = <0x02 0xff>;
+			resets = <&k3_reset 122 1>;
+			firmware-name = "am64-main-r5f0_1-fw";
+			ti,atcm-enable = <1>;
+			ti,btcm-enable = <1>;
+			ti,loczrama = <1>;
+		};
+	};
+
+	main_r5fss1: r5fss@78400000 {
+		compatible = "ti,am64-r5fss";
+		ti,cluster-mode = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x78400000 0x00 0x78400000 0x10000>,
+			 <0x78500000 0x00 0x78500000 0x10000>,
+			 <0x78600000 0x00 0x78600000 0x08000>,
+			 <0x78700000 0x00 0x78700000 0x08000>;
+		power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
+
+		main_r5fss1_core0: r5f@78400000 {
+			compatible = "ti,am64-r5f";
+			reg = <0x78400000 0x00010000>,
+			      <0x78500000 0x00010000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <123>;
+			ti,sci-proc-ids = <0x06 0xff>;
+			resets = <&k3_reset 123 1>;
+			firmware-name = "am64-main-r5f1_0-fw";
+			ti,atcm-enable = <1>;
+			ti,btcm-enable = <1>;
+			ti,loczrama = <1>;
+		};
+
+		main_r5fss1_core1: r5f@78600000 {
+			compatible = "ti,am64-r5f";
+			reg = <0x78600000 0x00008000>,
+			      <0x78700000 0x00008000>;
+			reg-names = "atcm", "btcm";
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <124>;
+			ti,sci-proc-ids = <0x07 0xff>;
+			resets = <&k3_reset 124 1>;
+			firmware-name = "am64-main-r5f1_1-fw";
+			ti,atcm-enable = <1>;
+			ti,btcm-enable = <1>;
+			ti,loczrama = <1>;
+		};
+	};
+
 	serdes_wiz0: wiz@f000000 {
 		compatible = "ti,am64-wiz-10g";
 		#address-cells = <1>;
-- 
2.30.1


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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 2/3] arm64: dts: ti: k3-am642-evm/sk: Add mailboxes to R5Fs

[Suman Anna]

Add the required 'mboxes' property to all the R5F processors for the
TI AM642 EVM and SK boards. The mailboxes and some shared memory are
required for running the Remote Processor Messaging (RPMsg) stack
between the host processor and each of the R5Fs.

The chosen sub-mailboxes match the values used in the current firmware
images. This can be changed, if needed, as per the system integration
needs after making appropriate changes on the firmware side as well.

Note that any R5F Core1 resources are needed and used only when that
R5F cluster is configured for Split-mode.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2:
No code changes, rebased and retained the presence after the mailbox nodes

 arch/arm64/boot/dts/ti/k3-am642-evm.dts | 16 ++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am642-sk.dts  | 16 ++++++++++++++++
 2 files changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index dc69db2d10c3..2e75cd68f8b7 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -469,6 +469,22 @@ &mailbox0_cluster7 {
 	status = "disabled";
 };
 
+&main_r5fss0_core0 {
+	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+};
+
+&main_r5fss0_core1 {
+	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+};
+
+&main_r5fss1_core0 {
+	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+};
+
+&main_r5fss1_core1 {
+	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+};
+
 &serdes_ln_ctrl {
 	idle-states = <AM64_SERDES0_LANE0_PCIE0>;
 };
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index 40124007259d..4abddea92cf5 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -368,6 +368,22 @@ &mailbox0_cluster7 {
 	status = "disabled";
 };
 
+&main_r5fss0_core0 {
+	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+};
+
+&main_r5fss0_core1 {
+	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+};
+
+&main_r5fss1_core0 {
+	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+};
+
+&main_r5fss1_core1 {
+	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+};
+
 &pcie0_rc {
 	status = "disabled";
 };
-- 
2.30.1

[PATCH v2 2/3] arm64: dts: ti: k3-am642-evm/sk: Add mailboxes to R5Fs

[Suman Anna]

Add the required 'mboxes' property to all the R5F processors for the
TI AM642 EVM and SK boards. The mailboxes and some shared memory are
required for running the Remote Processor Messaging (RPMsg) stack
between the host processor and each of the R5Fs.

The chosen sub-mailboxes match the values used in the current firmware
images. This can be changed, if needed, as per the system integration
needs after making appropriate changes on the firmware side as well.

Note that any R5F Core1 resources are needed and used only when that
R5F cluster is configured for Split-mode.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2:
No code changes, rebased and retained the presence after the mailbox nodes

 arch/arm64/boot/dts/ti/k3-am642-evm.dts | 16 ++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am642-sk.dts  | 16 ++++++++++++++++
 2 files changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index dc69db2d10c3..2e75cd68f8b7 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -469,6 +469,22 @@ &mailbox0_cluster7 {
 	status = "disabled";
 };
 
+&main_r5fss0_core0 {
+	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+};
+
+&main_r5fss0_core1 {
+	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+};
+
+&main_r5fss1_core0 {
+	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+};
+
+&main_r5fss1_core1 {
+	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+};
+
 &serdes_ln_ctrl {
 	idle-states = <AM64_SERDES0_LANE0_PCIE0>;
 };
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index 40124007259d..4abddea92cf5 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -368,6 +368,22 @@ &mailbox0_cluster7 {
 	status = "disabled";
 };
 
+&main_r5fss0_core0 {
+	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+};
+
+&main_r5fss0_core1 {
+	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+};
+
+&main_r5fss1_core0 {
+	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+};
+
+&main_r5fss1_core1 {
+	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+};
+
 &pcie0_rc {
 	status = "disabled";
 };
-- 
2.30.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 3/3] arm64: dts: ti: k3-am642-evm/sk: Add DDR carveout memory nodes for R5Fs

[Suman Anna]

Two carveout reserved memory nodes each have been added for each of the
R5F remote processor devices within the MAIN domain on the TI AM642 EVM
and SK boards. These nodes are assigned to the respective rproc device
nodes as well. The first region will be used as the DMA pool for the rproc
devices, and the second region will furnish the static carveout regions
for the firmware memory.

An additional reserved memory node is also added to reserve a portion of
the DDR memory to be used for performing inter-processor communication
between all the remote processors running RTOS or baremetal firmwares.
8 MB of memory is reserved for this purpose, and this accounts for all
the vrings and vring buffers between all the possible pairs of remote
processors.

The current carveout addresses and sizes are defined statically for each
rproc device. The R5F processors do not have an MMU, and as such require
the exact memory used by the firmwares to be set-aside. The firmware
images do not require any RSC_CARVEOUT entries in their resource tables
to allocate the memory for firmware memory segments.

NOTE:
1. The R5F1 carveouts are needed only if the R5F cluster is running in
   Split (non Single-CPU) mode. The reserved memory nodes can be disabled
   later on if there is no use-case defined to use the corresponding
   remote processor.
2. The AM64x SoCs do not have any DSPs and one less R5F cluster compared
   to J721E SoCs. So, while the carveout memories reserved for the R5F
   clusters present on the SoC match to those on J721E, the overall
   memory map reserved for firmwares is quite different. The number of
   R5F clusters on AM64x SoCs are same as on J7200 SoCs, but the AM64x
   SoCs also have an additional M4F core, so the RTOS IPC memory region
   is 1 MB higher than on J7200 SoCs.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2:
No code changes, rebased and retained the presence after the mailbox nodes

 arch/arm64/boot/dts/ti/k3-am642-evm.dts | 62 +++++++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am642-sk.dts  | 62 +++++++++++++++++++++++++
 2 files changed, 124 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index 2e75cd68f8b7..030712221188 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -38,6 +38,60 @@ secure_ddr: optee@9e800000 {
 			alignment = <0x1000>;
 			no-map;
 		};
+
+		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa0000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa0100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa1000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa1100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa2000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa2100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa3000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa3100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		rtos_ipc_memory_region: ipc-memories@a5000000 {
+			reg = <0x00 0xa5000000 0x00 0x00800000>;
+			alignment = <0x1000>;
+			no-map;
+		};
 	};
 
 	evm_12v0: fixedregulator-evm12v0 {
@@ -471,18 +525,26 @@ &mailbox0_cluster7 {
 
 &main_r5fss0_core0 {
 	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+	memory-region = <&main_r5fss0_core0_dma_memory_region>,
+			<&main_r5fss0_core0_memory_region>;
 };
 
 &main_r5fss0_core1 {
 	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+	memory-region = <&main_r5fss0_core1_dma_memory_region>,
+			<&main_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss1_core0 {
 	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+	memory-region = <&main_r5fss1_core0_dma_memory_region>,
+			<&main_r5fss1_core0_memory_region>;
 };
 
 &main_r5fss1_core1 {
 	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+	memory-region = <&main_r5fss1_core1_dma_memory_region>,
+			<&main_r5fss1_core1_memory_region>;
 };
 
 &serdes_ln_ctrl {
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index 4abddea92cf5..d3aa2901e6fd 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -37,6 +37,60 @@ secure_ddr: optee@9e800000 {
 			alignment = <0x1000>;
 			no-map;
 		};
+
+		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa0000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa0100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa1000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa1100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa2000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa2100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa3000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa3100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		rtos_ipc_memory_region: ipc-memories@a5000000 {
+			reg = <0x00 0xa5000000 0x00 0x00800000>;
+			alignment = <0x1000>;
+			no-map;
+		};
 	};
 
 	vusb_main: fixed-regulator-vusb-main5v0 {
@@ -370,18 +424,26 @@ &mailbox0_cluster7 {
 
 &main_r5fss0_core0 {
 	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+	memory-region = <&main_r5fss0_core0_dma_memory_region>,
+			<&main_r5fss0_core0_memory_region>;
 };
 
 &main_r5fss0_core1 {
 	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+	memory-region = <&main_r5fss0_core1_dma_memory_region>,
+			<&main_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss1_core0 {
 	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+	memory-region = <&main_r5fss1_core0_dma_memory_region>,
+			<&main_r5fss1_core0_memory_region>;
 };
 
 &main_r5fss1_core1 {
 	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+	memory-region = <&main_r5fss1_core1_dma_memory_region>,
+			<&main_r5fss1_core1_memory_region>;
 };
 
 &pcie0_rc {
-- 
2.30.1

[PATCH v2 3/3] arm64: dts: ti: k3-am642-evm/sk: Add DDR carveout memory nodes for R5Fs

[Suman Anna]

Two carveout reserved memory nodes each have been added for each of the
R5F remote processor devices within the MAIN domain on the TI AM642 EVM
and SK boards. These nodes are assigned to the respective rproc device
nodes as well. The first region will be used as the DMA pool for the rproc
devices, and the second region will furnish the static carveout regions
for the firmware memory.

An additional reserved memory node is also added to reserve a portion of
the DDR memory to be used for performing inter-processor communication
between all the remote processors running RTOS or baremetal firmwares.
8 MB of memory is reserved for this purpose, and this accounts for all
the vrings and vring buffers between all the possible pairs of remote
processors.

The current carveout addresses and sizes are defined statically for each
rproc device. The R5F processors do not have an MMU, and as such require
the exact memory used by the firmwares to be set-aside. The firmware
images do not require any RSC_CARVEOUT entries in their resource tables
to allocate the memory for firmware memory segments.

NOTE:
1. The R5F1 carveouts are needed only if the R5F cluster is running in
   Split (non Single-CPU) mode. The reserved memory nodes can be disabled
   later on if there is no use-case defined to use the corresponding
   remote processor.
2. The AM64x SoCs do not have any DSPs and one less R5F cluster compared
   to J721E SoCs. So, while the carveout memories reserved for the R5F
   clusters present on the SoC match to those on J721E, the overall
   memory map reserved for firmwares is quite different. The number of
   R5F clusters on AM64x SoCs are same as on J7200 SoCs, but the AM64x
   SoCs also have an additional M4F core, so the RTOS IPC memory region
   is 1 MB higher than on J7200 SoCs.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
v2:
No code changes, rebased and retained the presence after the mailbox nodes

 arch/arm64/boot/dts/ti/k3-am642-evm.dts | 62 +++++++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am642-sk.dts  | 62 +++++++++++++++++++++++++
 2 files changed, 124 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index 2e75cd68f8b7..030712221188 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -38,6 +38,60 @@ secure_ddr: optee@9e800000 {
 			alignment = <0x1000>;
 			no-map;
 		};
+
+		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa0000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa0100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa1000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa1100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa2000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa2100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa3000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa3100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		rtos_ipc_memory_region: ipc-memories@a5000000 {
+			reg = <0x00 0xa5000000 0x00 0x00800000>;
+			alignment = <0x1000>;
+			no-map;
+		};
 	};
 
 	evm_12v0: fixedregulator-evm12v0 {
@@ -471,18 +525,26 @@ &mailbox0_cluster7 {
 
 &main_r5fss0_core0 {
 	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+	memory-region = <&main_r5fss0_core0_dma_memory_region>,
+			<&main_r5fss0_core0_memory_region>;
 };
 
 &main_r5fss0_core1 {
 	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+	memory-region = <&main_r5fss0_core1_dma_memory_region>,
+			<&main_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss1_core0 {
 	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+	memory-region = <&main_r5fss1_core0_dma_memory_region>,
+			<&main_r5fss1_core0_memory_region>;
 };
 
 &main_r5fss1_core1 {
 	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+	memory-region = <&main_r5fss1_core1_dma_memory_region>,
+			<&main_r5fss1_core1_memory_region>;
 };
 
 &serdes_ln_ctrl {
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index 4abddea92cf5..d3aa2901e6fd 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -37,6 +37,60 @@ secure_ddr: optee@9e800000 {
 			alignment = <0x1000>;
 			no-map;
 		};
+
+		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa0000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa0100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa1000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa1100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa2000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa2100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa3000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa3100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		rtos_ipc_memory_region: ipc-memories@a5000000 {
+			reg = <0x00 0xa5000000 0x00 0x00800000>;
+			alignment = <0x1000>;
+			no-map;
+		};
 	};
 
 	vusb_main: fixed-regulator-vusb-main5v0 {
@@ -370,18 +424,26 @@ &mailbox0_cluster7 {
 
 &main_r5fss0_core0 {
 	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+	memory-region = <&main_r5fss0_core0_dma_memory_region>,
+			<&main_r5fss0_core0_memory_region>;
 };
 
 &main_r5fss0_core1 {
 	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+	memory-region = <&main_r5fss0_core1_dma_memory_region>,
+			<&main_r5fss0_core1_memory_region>;
 };
 
 &main_r5fss1_core0 {
 	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+	memory-region = <&main_r5fss1_core0_dma_memory_region>,
+			<&main_r5fss1_core0_memory_region>;
 };
 
 &main_r5fss1_core1 {
 	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+	memory-region = <&main_r5fss1_core1_dma_memory_region>,
+			<&main_r5fss1_core1_memory_region>;
 };
 
 &pcie0_rc {
-- 
2.30.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v2 0/3] Add R5F nodes on TI K3 AM64x SoCs

[Bajjuri, Praneeth]

On 6/15/2021 2:57 PM, Suman Anna wrote:
> Hi Nishanth,
> 
> This is a rebased version of the K3 AM64x R5F node series posted previously.
> Please see the v1 cover-letter for all the functional details [1]. I have
> dropped Patch 4 [2] from the previous series as per the discussion and agreed
> upon in [2] until we align on the longer-term memory utilization of OCM RAM.
> 
> Patches are on top of your latest staged ti-k3-dts-next branch commit
> d65f069e50a3 (arm64: dts: ti: Drop reg-io-width/reg-shift from UART nodes")
> + Aswath's [PATCH v4 0/3] AM64: Update the locations of various elements in SRAM
> series (can't see the links on lakml patchworks).
> 
> Bjorn has staged a tag from remoteproc tree with just the bindings [3]
> that you can use for merging this series for v5.14. The driver support
> will come through remoteproc tree.
> 
> I have validated the IPC functionality using System Firmware v2021.01a
> with appropriate U-Boot that goes along with Aswath's series and corresponding
> legacy PDK IPC example firmwares.
> 
> regards
> Suman
> 
> [1] https://patchwork.kernel.org/project/linux-arm-kernel/cover/20210528144718.25132-1-s-anna@ti.com/
> [2] https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210528144718.25132-5-s-anna@ti.com/
> [3] https://git.kernel.org/pub/scm/linux/kernel/git/andersson/remoteproc.git/log/?h=20210327143117.1840-2-s-anna@ti.com
> 
> Suman Anna (3):
>    arm64: dts: ti: k3-am64-main: Add MAIN domain R5F cluster nodes
>    arm64: dts: ti: k3-am642-evm/sk: Add mailboxes to R5Fs
>    arm64: dts: ti: k3-am642-evm/sk: Add DDR carveout memory nodes for
>      R5Fs

For the series.

Reviewed-by: Praneeth Bajjuri <praneeth@ti.com>

> 
>   arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 84 ++++++++++++++++++++++++
>   arch/arm64/boot/dts/ti/k3-am642-evm.dts  | 78 ++++++++++++++++++++++
>   arch/arm64/boot/dts/ti/k3-am642-sk.dts   | 78 ++++++++++++++++++++++
>   3 files changed, 240 insertions(+)
> 

Re: [PATCH v2 0/3] Add R5F nodes on TI K3 AM64x SoCs

[Bajjuri, Praneeth]

On 6/15/2021 2:57 PM, Suman Anna wrote:
> Hi Nishanth,
> 
> This is a rebased version of the K3 AM64x R5F node series posted previously.
> Please see the v1 cover-letter for all the functional details [1]. I have
> dropped Patch 4 [2] from the previous series as per the discussion and agreed
> upon in [2] until we align on the longer-term memory utilization of OCM RAM.
> 
> Patches are on top of your latest staged ti-k3-dts-next branch commit
> d65f069e50a3 (arm64: dts: ti: Drop reg-io-width/reg-shift from UART nodes")
> + Aswath's [PATCH v4 0/3] AM64: Update the locations of various elements in SRAM
> series (can't see the links on lakml patchworks).
> 
> Bjorn has staged a tag from remoteproc tree with just the bindings [3]
> that you can use for merging this series for v5.14. The driver support
> will come through remoteproc tree.
> 
> I have validated the IPC functionality using System Firmware v2021.01a
> with appropriate U-Boot that goes along with Aswath's series and corresponding
> legacy PDK IPC example firmwares.
> 
> regards
> Suman
> 
> [1] https://patchwork.kernel.org/project/linux-arm-kernel/cover/20210528144718.25132-1-s-anna@ti.com/
> [2] https://patchwork.kernel.org/project/linux-arm-kernel/patch/20210528144718.25132-5-s-anna@ti.com/
> [3] https://git.kernel.org/pub/scm/linux/kernel/git/andersson/remoteproc.git/log/?h=20210327143117.1840-2-s-anna@ti.com
> 
> Suman Anna (3):
>    arm64: dts: ti: k3-am64-main: Add MAIN domain R5F cluster nodes
>    arm64: dts: ti: k3-am642-evm/sk: Add mailboxes to R5Fs
>    arm64: dts: ti: k3-am642-evm/sk: Add DDR carveout memory nodes for
>      R5Fs

For the series.

Reviewed-by: Praneeth Bajjuri <praneeth@ti.com>

> 
>   arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 84 ++++++++++++++++++++++++
>   arch/arm64/boot/dts/ti/k3-am642-evm.dts  | 78 ++++++++++++++++++++++
>   arch/arm64/boot/dts/ti/k3-am642-sk.dts   | 78 ++++++++++++++++++++++
>   3 files changed, 240 insertions(+)
> 

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Re: [PATCH v2 3/3] arm64: dts: ti: k3-am642-evm/sk: Add DDR carveout memory nodes for R5Fs

[Nishanth Menon]

On 14:57-20210615, Suman Anna wrote:
[...]
> 
>  arch/arm64/boot/dts/ti/k3-am642-evm.dts | 62 +++++++++++++++++++++++++
>  arch/arm64/boot/dts/ti/k3-am642-sk.dts  | 62 +++++++++++++++++++++++++
>  2 files changed, 124 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> index 2e75cd68f8b7..030712221188 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> @@ -38,6 +38,60 @@ secure_ddr: optee@9e800000 {
>  			alignment = <0x1000>;
>  			no-map;
>  		};
> +
[...]
> +		main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
> +			compatible = "shared-dma-pool";
> +			reg = <0x00 0xa3100000 0x00 0xf00000>;
> +			no-map;
> +		};
arch/arm64/boot/dts/ti/k3-am642-evm.dt.yaml:0:0: /reserved-memory/r5f-dma-memory@a0000000: failed to match any schema with compatible: ['shared-dma-pool']
arch/arm64/boot/dts/ti/k3-am642-evm.dt.yaml:0:0: /reserved-memory/r5f-memory@a0100000: failed to match any schema with compatible: ['shared-dma-pool']
arch/arm64/boot/dts/ti/k3-am642-evm.dt.yaml:0:0: /reserved-memory/r5f-dma-memory@a1000000: failed to match any schema with compatible: ['shared-dma-pool']
arch/arm64/boot/dts/ti/k3-am642-evm.dt.yaml:0:0: /reserved-memory/r5f-memory@a1100000: failed to match any schema with compatible: ['shared-dma-pool']
arch/arm64/boot/dts/ti/k3-am642-evm.dt.yaml:0:0: /reserved-memory/r5f-dma-memory@a2000000: failed to match any schema with compatible: ['shared-dma-pool']
arch/arm64/boot/dts/ti/k3-am642-evm.dt.yaml:0:0: /reserved-memory/r5f-memory@a2100000: failed to match any schema with compatible: ['shared-dma-pool']
arch/arm64/boot/dts/ti/k3-am642-evm.dt.yaml:0:0: /reserved-memory/r5f-dma-memory@a3000000: failed to match any schema with compatible: ['shared-dma-pool']
arch/arm64/boot/dts/ti/k3-am642-evm.dt.yaml:0:0: /reserved-memory/r5f-memory@a3100000: failed to match any schema with compatible: ['shared-dma-pool']

ughh..

Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt is
not converted to yaml.

Rob, Arnd,

I am considering to pick this series up this friday given the scale
of other platforms that are using the same property and since I see
for example commit 0fe0fbc867115659bbd9a0ab107d1fe9bcc432e8 (MIPS)
in next-20210616. Unfortunately [1] does'nt give me much precedence
either in immediate recent history.

Let me know if you think we should wait on this.

[1] https://lore.kernel.org/linux-arm-kernel/?q=shared-dma-pool
-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH v2 3/3] arm64: dts: ti: k3-am642-evm/sk: Add DDR carveout memory nodes for R5Fs

[Nishanth Menon]

On 14:57-20210615, Suman Anna wrote:
[...]
> 
>  arch/arm64/boot/dts/ti/k3-am642-evm.dts | 62 +++++++++++++++++++++++++
>  arch/arm64/boot/dts/ti/k3-am642-sk.dts  | 62 +++++++++++++++++++++++++
>  2 files changed, 124 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> index 2e75cd68f8b7..030712221188 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> @@ -38,6 +38,60 @@ secure_ddr: optee@9e800000 {
>  			alignment = <0x1000>;
>  			no-map;
>  		};
> +
[...]
> +		main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
> +			compatible = "shared-dma-pool";
> +			reg = <0x00 0xa3100000 0x00 0xf00000>;
> +			no-map;
> +		};
arch/arm64/boot/dts/ti/k3-am642-evm.dt.yaml:0:0: /reserved-memory/r5f-dma-memory@a0000000: failed to match any schema with compatible: ['shared-dma-pool']
arch/arm64/boot/dts/ti/k3-am642-evm.dt.yaml:0:0: /reserved-memory/r5f-memory@a0100000: failed to match any schema with compatible: ['shared-dma-pool']
arch/arm64/boot/dts/ti/k3-am642-evm.dt.yaml:0:0: /reserved-memory/r5f-dma-memory@a1000000: failed to match any schema with compatible: ['shared-dma-pool']
arch/arm64/boot/dts/ti/k3-am642-evm.dt.yaml:0:0: /reserved-memory/r5f-memory@a1100000: failed to match any schema with compatible: ['shared-dma-pool']
arch/arm64/boot/dts/ti/k3-am642-evm.dt.yaml:0:0: /reserved-memory/r5f-dma-memory@a2000000: failed to match any schema with compatible: ['shared-dma-pool']
arch/arm64/boot/dts/ti/k3-am642-evm.dt.yaml:0:0: /reserved-memory/r5f-memory@a2100000: failed to match any schema with compatible: ['shared-dma-pool']
arch/arm64/boot/dts/ti/k3-am642-evm.dt.yaml:0:0: /reserved-memory/r5f-dma-memory@a3000000: failed to match any schema with compatible: ['shared-dma-pool']
arch/arm64/boot/dts/ti/k3-am642-evm.dt.yaml:0:0: /reserved-memory/r5f-memory@a3100000: failed to match any schema with compatible: ['shared-dma-pool']

ughh..

Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt is
not converted to yaml.

Rob, Arnd,

I am considering to pick this series up this friday given the scale
of other platforms that are using the same property and since I see
for example commit 0fe0fbc867115659bbd9a0ab107d1fe9bcc432e8 (MIPS)
in next-20210616. Unfortunately [1] does'nt give me much precedence
either in immediate recent history.

Let me know if you think we should wait on this.

[1] https://lore.kernel.org/linux-arm-kernel/?q=shared-dma-pool
-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

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Re: [PATCH v2 0/3] Add R5F nodes on TI K3 AM64x SoCs

[Nishanth Menon]

On Tue, 15 Jun 2021 14:57:15 -0500, Suman Anna wrote:
> This is a rebased version of the K3 AM64x R5F node series posted previously.
> Please see the v1 cover-letter for all the functional details [1]. I have
> dropped Patch 4 [2] from the previous series as per the discussion and agreed
> upon in [2] until we align on the longer-term memory utilization of OCM RAM.
> 
> Patches are on top of your latest staged ti-k3-dts-next branch commit
> d65f069e50a3 (arm64: dts: ti: Drop reg-io-width/reg-shift from UART nodes")
> + Aswath's [PATCH v4 0/3] AM64: Update the locations of various elements in SRAM
> series (can't see the links on lakml patchworks).
> 
> [...]

Hi Suman Anna,

I have applied the following to branch ti-k3-dts-next on [1].
Thank you!

NOTE:
* I have pulled in yaml tag from Bjorn[2] prior to your patches. (cced him as
  well FYI - Thanks Bjorn for facilitating this)
* As discussed in [3], the shared-dma-pool dtbs_check warnings - I am merging
  since there is at least one precedence in this merge window, but as we have
  been discussing in prior threads as well, we will not do this in the 5.15
  window. In the future, please give a headsup in patch if such issues are
  introduced.

[1/3] arm64: dts: ti: k3-am64-main: Add MAIN domain R5F cluster nodes
      commit: a4f221cd68b306d6311237e47b531d21fab8dfa4
[2/3] arm64: dts: ti: k3-am642-evm/sk: Add mailboxes to R5Fs
      commit: 0afadba435892c8d330e3238b9cc7f9ee8b20e90
[3/3] arm64: dts: ti: k3-am642-evm/sk: Add DDR carveout memory nodes for R5Fs
      commit: d71abfcc6c050b72ba735b74f3e3848ce07ddd15


All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

[1] git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux.git
[2] https://git.kernel.org/pub/scm/linux/kernel/git/andersson/remoteproc.git/tag/?h=20210327143117.1840-2-s-anna@ti.com
[3] https://lore.kernel.org/linux-devicetree/20210617004448.aozqtxu5smg57vr5@exterior/

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH v2 0/3] Add R5F nodes on TI K3 AM64x SoCs

[Nishanth Menon]

On Tue, 15 Jun 2021 14:57:15 -0500, Suman Anna wrote:
> This is a rebased version of the K3 AM64x R5F node series posted previously.
> Please see the v1 cover-letter for all the functional details [1]. I have
> dropped Patch 4 [2] from the previous series as per the discussion and agreed
> upon in [2] until we align on the longer-term memory utilization of OCM RAM.
> 
> Patches are on top of your latest staged ti-k3-dts-next branch commit
> d65f069e50a3 (arm64: dts: ti: Drop reg-io-width/reg-shift from UART nodes")
> + Aswath's [PATCH v4 0/3] AM64: Update the locations of various elements in SRAM
> series (can't see the links on lakml patchworks).
> 
> [...]

Hi Suman Anna,

I have applied the following to branch ti-k3-dts-next on [1].
Thank you!

NOTE:
* I have pulled in yaml tag from Bjorn[2] prior to your patches. (cced him as
  well FYI - Thanks Bjorn for facilitating this)
* As discussed in [3], the shared-dma-pool dtbs_check warnings - I am merging
  since there is at least one precedence in this merge window, but as we have
  been discussing in prior threads as well, we will not do this in the 5.15
  window. In the future, please give a headsup in patch if such issues are
  introduced.

[1/3] arm64: dts: ti: k3-am64-main: Add MAIN domain R5F cluster nodes
      commit: a4f221cd68b306d6311237e47b531d21fab8dfa4
[2/3] arm64: dts: ti: k3-am642-evm/sk: Add mailboxes to R5Fs
      commit: 0afadba435892c8d330e3238b9cc7f9ee8b20e90
[3/3] arm64: dts: ti: k3-am642-evm/sk: Add DDR carveout memory nodes for R5Fs
      commit: d71abfcc6c050b72ba735b74f3e3848ce07ddd15


All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

[1] git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux.git
[2] https://git.kernel.org/pub/scm/linux/kernel/git/andersson/remoteproc.git/tag/?h=20210327143117.1840-2-s-anna@ti.com
[3] https://lore.kernel.org/linux-devicetree/20210617004448.aozqtxu5smg57vr5@exterior/

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D


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