From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Subject: [Qemu-devel] [RFC v1 02/23] target/riscv: Add the Hypervisor extension Date: Fri, 24 May 2019 16:45:40 -0700 [thread overview] Message-ID: <668f55005ffe96a231306ba4d8022e43142b25f5.1558741334.git.alistair.francis@wdc.com> (raw) In-Reply-To: <cover.1558741334.git.alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8937bda918..3337d1aef3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -81,6 +81,7 @@ #define RVC RV('C') #define RVS RV('S') #define RVU RV('U') +#define RVH RV('H') /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there -- 2.21.0
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@sifive.com, alistair.francis@wdc.com, alistair23@gmail.com Subject: [Qemu-riscv] [RFC v1 02/23] target/riscv: Add the Hypervisor extension Date: Fri, 24 May 2019 16:45:40 -0700 [thread overview] Message-ID: <668f55005ffe96a231306ba4d8022e43142b25f5.1558741334.git.alistair.francis@wdc.com> (raw) In-Reply-To: <cover.1558741334.git.alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8937bda918..3337d1aef3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -81,6 +81,7 @@ #define RVC RV('C') #define RVS RV('S') #define RVU RV('U') +#define RVH RV('H') /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there -- 2.21.0
next prev parent reply other threads:[~2019-05-25 0:13 UTC|newest] Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-05-24 23:45 [Qemu-devel] [RFC v1 00/23] Add RISC-V Hypervisor Extension Alistair Francis 2019-05-24 23:45 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:45 ` [Qemu-devel] [RFC v1 01/23] target/riscv: Don't set write permissions on dirty PTEs Alistair Francis 2019-05-24 23:45 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:45 ` Alistair Francis [this message] 2019-05-24 23:45 ` [Qemu-riscv] [RFC v1 02/23] target/riscv: Add the Hypervisor extension Alistair Francis 2019-05-24 23:45 ` [Qemu-devel] [RFC v1 03/23] target/riscv: Add the virtulisation mode Alistair Francis 2019-05-24 23:45 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:45 ` [Qemu-devel] [RFC v1 04/23] target/riscv: Add the force HS exception mode Alistair Francis 2019-05-24 23:45 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:45 ` [Qemu-devel] [RFC v1 05/23] target/riscv: Add the Hypervisor CSRs to CPUState Alistair Francis 2019-05-24 23:45 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:45 ` [Qemu-devel] [RFC v1 06/23] target/riscv: Dump Hypervisor registers if enabled Alistair Francis 2019-05-24 23:45 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:45 ` [Qemu-devel] [RFC v1 07/23] target/riscv: Remove strict perm checking for CSR R/W Alistair Francis 2019-05-24 23:45 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:45 ` [Qemu-devel] [RFC v1 08/23] target/riscv: Add support for background interrupt setting Alistair Francis 2019-05-24 23:45 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:45 ` [Qemu-devel] [RFC v1 09/23] target/riscv: Add Hypervisor CSR access functions Alistair Francis 2019-05-24 23:45 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 10/23] target/riscv: Add background CSRs accesses Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 11/23] target/riscv: Add background register swapping function Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 12/23] target/ricsv: Flush the TLB on virtulisation mode changes Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 13/23] target/riscv: Generate illegal instruction on WFI when V=1 Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 14/23] riscv: plic: Remove unused interrupt functions Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 15/23] riscv: plic: Always set sip.SEIP bit for HS Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 16/23] target/riscv: Add hypvervisor trap support Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 17/23] target/riscv: Add Hypervisor trap return support Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 18/23] target/riscv: Add hfence instructions Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 19/23] target/riscv: Allow specifying MMU stage Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 20/23] target/riscv: Allow specifying number of MMU stages Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 21/23] target/riscv: Implement second stage MMU Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 22/23] target/riscv: Call the second stage MMU in virtualisation mode Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 23/23] target/riscv: Allow enabling the Hypervisor extension Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:50 ` [Qemu-devel] [RFC v1 00/23] Add RISC-V Hypervisor Extension Alistair Francis 2019-05-24 23:50 ` [Qemu-riscv] " Alistair Francis
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