From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Subject: [Qemu-devel] [RFC v1 22/23] target/riscv: Call the second stage MMU in virtualisation mode Date: Fri, 24 May 2019 16:46:33 -0700 [thread overview] Message-ID: <a52e30a4be4bc83aa0d29685b6f2c80fb466ab39.1558741334.git.alistair.francis@wdc.com> (raw) In-Reply-To: <cover.1558741334.git.alistair.francis@wdc.com> The qemu_log_mask(CPU_LOG_MMU,... calls trigger false positive checkpatch errors which are being ignored. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu_helper.c | 118 ++++++++++++++++++++++++++++++++------ 1 file changed, 99 insertions(+), 19 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 387c12547b..99091ed0fd 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -569,15 +569,23 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address, hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; hwaddr phys_addr; int prot; int mmu_idx = cpu_mmu_index(&cpu->env, false); - if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx, - true, false)) { + if (get_physical_address(env, &phys_addr, &prot, addr, 0, mmu_idx, + true, riscv_cpu_virt_enabled(env))) { return -1; } + if (riscv_cpu_virt_enabled(env)) { + if (get_physical_address(env, &phys_addr, &prot, phys_addr, + 0, mmu_idx, false, true)) { + return -1; + } + } + return phys_addr; } @@ -628,34 +636,106 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, #ifndef CONFIG_USER_ONLY RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; + vaddr im_address; hwaddr pa = 0; int prot; + bool m_mode_two_stage = false; + bool hs_mode_two_stage = false; int ret = TRANSLATE_FAIL; qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, address, access_type, mmu_idx); - ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx, - true, false); + /* + * Determine if we are in M mode and MPRV is set or in HS mode and SPRV is + * set and we want to access a virtulisation address. + */ + if (riscv_has_ext(env, RVH)) { + m_mode_two_stage = env->priv == PRV_M && + access_type != MMU_INST_FETCH && + get_field(env->mstatus, MSTATUS_MPRV) && + get_field(env->mstatus, MSTATUS_MPV); + + hs_mode_two_stage = env->priv == PRV_S && + !riscv_cpu_virt_enabled(env) && + access_type != MMU_INST_FETCH && + get_field(env->hstatus, HSTATUS_SPRV) && + get_field(env->hstatus, HSTATUS_SPV); + } + + if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_stage) { + /* Two stage lookup */ + ret = get_physical_address(env, &pa, &prot, address, access_type, + mmu_idx, true, true); - qemu_log_mask(CPU_LOG_MMU, - "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx - " prot %d\n", __func__, address, ret, pa, prot); + qemu_log_mask(CPU_LOG_MMU, + "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " + TARGET_FMT_plx " prot %d\n", + __func__, address, ret, pa, prot); - if (riscv_feature(env, RISCV_FEATURE_PMP) && - !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) { - ret = TRANSLATE_FAIL; - } - if (ret == TRANSLATE_SUCCESS) { - tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, - prot, mmu_idx, TARGET_PAGE_SIZE); - return true; - } else if (probe) { - return false; + if (ret == TRANSLATE_FAIL) { + if (!probe) { + raise_mmu_exception(env, address, access_type, true); + riscv_raise_exception(env, cs->exception_index, retaddr); + } + return ret; + } + + /* Second stage lookup */ + im_address = pa; + + ret = get_physical_address(env, &pa, &prot, im_address, access_type, mmu_idx, + false, true); + + qemu_log_mask(CPU_LOG_MMU, + "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " + TARGET_FMT_plx " prot %d\n", + __func__, im_address, ret, pa, prot); + + if (riscv_feature(env, RISCV_FEATURE_PMP) && + !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) { + ret = TRANSLATE_FAIL; + } + + if (ret == TRANSLATE_FAIL) { + /* + * Guest physical address translation failed, this is a HS + * level exception + */ + if (!probe) { + raise_mmu_exception(env, im_address | (address & (TARGET_PAGE_SIZE - 1)), access_type, false); + riscv_raise_exception(env, cs->exception_index, retaddr); + } + return ret; + } } else { - raise_mmu_exception(env, address, access_type, true); - riscv_raise_exception(env, cs->exception_index, retaddr); + /* Single stage lookup */ + ret = get_physical_address(env, &pa, &prot, address, access_type, + mmu_idx, true, false); + + qemu_log_mask(CPU_LOG_MMU, + "%s address=%" VADDR_PRIx " ret %d physical " + TARGET_FMT_plx " prot %d\n", + __func__, address, ret, pa, prot); + + if (riscv_feature(env, RISCV_FEATURE_PMP) && + !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) { + ret = TRANSLATE_FAIL; + } + + if (ret == TRANSLATE_FAIL) { + if (!probe) { + raise_mmu_exception(env, address, access_type, true); + riscv_raise_exception(env, cs->exception_index, retaddr); + } + return ret; + } } + + tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, + prot, mmu_idx, TARGET_PAGE_SIZE); + return true; + #else switch (access_type) { case MMU_INST_FETCH: -- 2.21.0
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@sifive.com, alistair.francis@wdc.com, alistair23@gmail.com Subject: [Qemu-riscv] [RFC v1 22/23] target/riscv: Call the second stage MMU in virtualisation mode Date: Fri, 24 May 2019 16:46:33 -0700 [thread overview] Message-ID: <a52e30a4be4bc83aa0d29685b6f2c80fb466ab39.1558741334.git.alistair.francis@wdc.com> (raw) In-Reply-To: <cover.1558741334.git.alistair.francis@wdc.com> The qemu_log_mask(CPU_LOG_MMU,... calls trigger false positive checkpatch errors which are being ignored. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu_helper.c | 118 ++++++++++++++++++++++++++++++++------ 1 file changed, 99 insertions(+), 19 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 387c12547b..99091ed0fd 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -569,15 +569,23 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address, hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; hwaddr phys_addr; int prot; int mmu_idx = cpu_mmu_index(&cpu->env, false); - if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx, - true, false)) { + if (get_physical_address(env, &phys_addr, &prot, addr, 0, mmu_idx, + true, riscv_cpu_virt_enabled(env))) { return -1; } + if (riscv_cpu_virt_enabled(env)) { + if (get_physical_address(env, &phys_addr, &prot, phys_addr, + 0, mmu_idx, false, true)) { + return -1; + } + } + return phys_addr; } @@ -628,34 +636,106 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, #ifndef CONFIG_USER_ONLY RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; + vaddr im_address; hwaddr pa = 0; int prot; + bool m_mode_two_stage = false; + bool hs_mode_two_stage = false; int ret = TRANSLATE_FAIL; qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, address, access_type, mmu_idx); - ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx, - true, false); + /* + * Determine if we are in M mode and MPRV is set or in HS mode and SPRV is + * set and we want to access a virtulisation address. + */ + if (riscv_has_ext(env, RVH)) { + m_mode_two_stage = env->priv == PRV_M && + access_type != MMU_INST_FETCH && + get_field(env->mstatus, MSTATUS_MPRV) && + get_field(env->mstatus, MSTATUS_MPV); + + hs_mode_two_stage = env->priv == PRV_S && + !riscv_cpu_virt_enabled(env) && + access_type != MMU_INST_FETCH && + get_field(env->hstatus, HSTATUS_SPRV) && + get_field(env->hstatus, HSTATUS_SPV); + } + + if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_stage) { + /* Two stage lookup */ + ret = get_physical_address(env, &pa, &prot, address, access_type, + mmu_idx, true, true); - qemu_log_mask(CPU_LOG_MMU, - "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx - " prot %d\n", __func__, address, ret, pa, prot); + qemu_log_mask(CPU_LOG_MMU, + "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " + TARGET_FMT_plx " prot %d\n", + __func__, address, ret, pa, prot); - if (riscv_feature(env, RISCV_FEATURE_PMP) && - !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) { - ret = TRANSLATE_FAIL; - } - if (ret == TRANSLATE_SUCCESS) { - tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, - prot, mmu_idx, TARGET_PAGE_SIZE); - return true; - } else if (probe) { - return false; + if (ret == TRANSLATE_FAIL) { + if (!probe) { + raise_mmu_exception(env, address, access_type, true); + riscv_raise_exception(env, cs->exception_index, retaddr); + } + return ret; + } + + /* Second stage lookup */ + im_address = pa; + + ret = get_physical_address(env, &pa, &prot, im_address, access_type, mmu_idx, + false, true); + + qemu_log_mask(CPU_LOG_MMU, + "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " + TARGET_FMT_plx " prot %d\n", + __func__, im_address, ret, pa, prot); + + if (riscv_feature(env, RISCV_FEATURE_PMP) && + !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) { + ret = TRANSLATE_FAIL; + } + + if (ret == TRANSLATE_FAIL) { + /* + * Guest physical address translation failed, this is a HS + * level exception + */ + if (!probe) { + raise_mmu_exception(env, im_address | (address & (TARGET_PAGE_SIZE - 1)), access_type, false); + riscv_raise_exception(env, cs->exception_index, retaddr); + } + return ret; + } } else { - raise_mmu_exception(env, address, access_type, true); - riscv_raise_exception(env, cs->exception_index, retaddr); + /* Single stage lookup */ + ret = get_physical_address(env, &pa, &prot, address, access_type, + mmu_idx, true, false); + + qemu_log_mask(CPU_LOG_MMU, + "%s address=%" VADDR_PRIx " ret %d physical " + TARGET_FMT_plx " prot %d\n", + __func__, address, ret, pa, prot); + + if (riscv_feature(env, RISCV_FEATURE_PMP) && + !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) { + ret = TRANSLATE_FAIL; + } + + if (ret == TRANSLATE_FAIL) { + if (!probe) { + raise_mmu_exception(env, address, access_type, true); + riscv_raise_exception(env, cs->exception_index, retaddr); + } + return ret; + } } + + tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, + prot, mmu_idx, TARGET_PAGE_SIZE); + return true; + #else switch (access_type) { case MMU_INST_FETCH: -- 2.21.0
next prev parent reply other threads:[~2019-05-25 0:01 UTC|newest] Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-05-24 23:45 [Qemu-devel] [RFC v1 00/23] Add RISC-V Hypervisor Extension Alistair Francis 2019-05-24 23:45 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:45 ` [Qemu-devel] [RFC v1 01/23] target/riscv: Don't set write permissions on dirty PTEs Alistair Francis 2019-05-24 23:45 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:45 ` [Qemu-devel] [RFC v1 02/23] target/riscv: Add the Hypervisor extension Alistair Francis 2019-05-24 23:45 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:45 ` [Qemu-devel] [RFC v1 03/23] target/riscv: Add the virtulisation mode Alistair Francis 2019-05-24 23:45 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:45 ` [Qemu-devel] [RFC v1 04/23] target/riscv: Add the force HS exception mode Alistair Francis 2019-05-24 23:45 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:45 ` [Qemu-devel] [RFC v1 05/23] target/riscv: Add the Hypervisor CSRs to CPUState Alistair Francis 2019-05-24 23:45 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:45 ` [Qemu-devel] [RFC v1 06/23] target/riscv: Dump Hypervisor registers if enabled Alistair Francis 2019-05-24 23:45 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:45 ` [Qemu-devel] [RFC v1 07/23] target/riscv: Remove strict perm checking for CSR R/W Alistair Francis 2019-05-24 23:45 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:45 ` [Qemu-devel] [RFC v1 08/23] target/riscv: Add support for background interrupt setting Alistair Francis 2019-05-24 23:45 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:45 ` [Qemu-devel] [RFC v1 09/23] target/riscv: Add Hypervisor CSR access functions Alistair Francis 2019-05-24 23:45 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 10/23] target/riscv: Add background CSRs accesses Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 11/23] target/riscv: Add background register swapping function Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 12/23] target/ricsv: Flush the TLB on virtulisation mode changes Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 13/23] target/riscv: Generate illegal instruction on WFI when V=1 Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 14/23] riscv: plic: Remove unused interrupt functions Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 15/23] riscv: plic: Always set sip.SEIP bit for HS Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 16/23] target/riscv: Add hypvervisor trap support Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 17/23] target/riscv: Add Hypervisor trap return support Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 18/23] target/riscv: Add hfence instructions Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 19/23] target/riscv: Allow specifying MMU stage Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 20/23] target/riscv: Allow specifying number of MMU stages Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 21/23] target/riscv: Implement second stage MMU Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:46 ` Alistair Francis [this message] 2019-05-24 23:46 ` [Qemu-riscv] [RFC v1 22/23] target/riscv: Call the second stage MMU in virtualisation mode Alistair Francis 2019-05-24 23:46 ` [Qemu-devel] [RFC v1 23/23] target/riscv: Allow enabling the Hypervisor extension Alistair Francis 2019-05-24 23:46 ` [Qemu-riscv] " Alistair Francis 2019-05-24 23:50 ` [Qemu-devel] [RFC v1 00/23] Add RISC-V Hypervisor Extension Alistair Francis 2019-05-24 23:50 ` [Qemu-riscv] " Alistair Francis
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