From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com
Subject: Re: [PATCH v3 13/20] target/riscv: Fix RESERVED field length in VTYPE
Date: Thu, 11 Nov 2021 12:33:41 +0100 [thread overview]
Message-ID: <6b23e7f0-43ff-8782-f193-e5e6394f1ffc@linaro.org> (raw)
In-Reply-To: <8f43db00-bd51-cadc-4c57-0db699a96aa0@linaro.org>
On 11/11/21 12:33 PM, Richard Henderson wrote:
> On 11/11/21 6:57 AM, LIU Zhiwei wrote:
>> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
>> ---
>> target/riscv/cpu.h | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index 52ce670cbe..b48c7c346c 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -105,7 +105,7 @@ typedef struct CPURISCVState CPURISCVState;
>> FIELD(VTYPE, VLMUL, 0, 2)
>> FIELD(VTYPE, VSEW, 2, 3)
>> FIELD(VTYPE, VEDIV, 5, 2)
>> -FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
>> +FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 8)
>
> Or better, remove it in the next patch.
Bah, nevermind.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com
Subject: Re: [PATCH v3 13/20] target/riscv: Fix RESERVED field length in VTYPE
Date: Thu, 11 Nov 2021 12:33:41 +0100 [thread overview]
Message-ID: <6b23e7f0-43ff-8782-f193-e5e6394f1ffc@linaro.org> (raw)
In-Reply-To: <8f43db00-bd51-cadc-4c57-0db699a96aa0@linaro.org>
On 11/11/21 12:33 PM, Richard Henderson wrote:
> On 11/11/21 6:57 AM, LIU Zhiwei wrote:
>> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
>> ---
>> target/riscv/cpu.h | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index 52ce670cbe..b48c7c346c 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -105,7 +105,7 @@ typedef struct CPURISCVState CPURISCVState;
>> FIELD(VTYPE, VLMUL, 0, 2)
>> FIELD(VTYPE, VSEW, 2, 3)
>> FIELD(VTYPE, VEDIV, 5, 2)
>> -FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
>> +FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 8)
>
> Or better, remove it in the next patch.
Bah, nevermind.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2021-11-11 11:35 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-11 5:57 [PATCH v3 00/20] Support UXL filed in xstatus LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 01/20] target/riscv: Don't save pc when exception return LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 02/20] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 03/20] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 04/20] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 11:19 ` Richard Henderson
2021-11-11 11:19 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 05/20] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 06/20] target/riscv: Relax debug check for pm write LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 07/20] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 11:21 ` Richard Henderson
2021-11-11 11:21 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 08/20] target/riscv: Create current pm fields in env LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 11:26 ` Richard Henderson
2021-11-11 11:26 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 10/20] target/riscv: Calculate address according to XLEN LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 11:28 ` Richard Henderson
2021-11-11 11:28 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 11/20] target/riscv: Split pm_enabled into mask and base LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 11:29 ` Richard Henderson
2021-11-11 11:29 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 12/20] target/riscv: Split out the vill from vtype LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 11:31 ` Richard Henderson
2021-11-11 11:31 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 13/20] target/riscv: Fix RESERVED field length in VTYPE LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 11:33 ` Richard Henderson
2021-11-11 11:33 ` Richard Henderson
2021-11-11 11:33 ` Richard Henderson [this message]
2021-11-11 11:33 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 14/20] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 11:35 ` Richard Henderson
2021-11-11 11:35 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 15/20] target/riscv: Remove VILL field in VTYPE LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 11:38 ` Richard Henderson
2021-11-11 11:38 ` Richard Henderson
2021-11-11 5:57 ` [PATCH v3 16/20] target/riscv: Ajdust vector atomic check with XLEN LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 17/20] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 18/20] target/riscv: Adjust vector address with mask LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 5:57 ` [PATCH v3 19/20] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2021-11-11 5:57 ` LIU Zhiwei
2021-11-11 11:46 ` Richard Henderson
2021-11-11 11:46 ` Richard Henderson
2021-11-11 14:43 ` LIU Zhiwei
2021-11-11 14:43 ` LIU Zhiwei
2021-11-11 5:58 ` [PATCH v3 20/20] target/riscv: Enable uxl field write LIU Zhiwei
2021-11-11 5:58 ` LIU Zhiwei
2021-11-11 11:49 ` Richard Henderson
2021-11-11 11:49 ` Richard Henderson
2021-11-11 15:18 ` Frédéric Pétrot
2021-11-11 15:18 ` Frédéric Pétrot
2021-11-11 18:20 ` Richard Henderson
2021-11-11 18:20 ` Richard Henderson
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