From: "Ramuthevar, Vadivel MuruganX" <vadivel.muruganx.ramuthevar@linux.intel.com>
To: Boris Brezillon <boris.brezillon@collabora.com>
Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org,
devicetree@vger.kernel.org, miquel.raynal@bootlin.com,
richard@nod.at, vigneshr@ti.com, arnd@arndb.de,
brendanhiggins@google.com, tglx@linutronix.de,
anders.roxell@linaro.org, masonccyang@mxic.com.tw,
robh+dt@kernel.org, linux-mips@vger.kernel.org,
hauke.mehrtens@intel.com, andriy.shevchenko@intel.com,
qi-ming.wu@intel.com, cheol.yong.kim@intel.com
Subject: Re: [PATCH v4 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC
Date: Wed, 29 Apr 2020 22:26:25 +0800 [thread overview]
Message-ID: <6b3ad9f3-2a3c-b44c-3c3f-24f2178dd3fa@linux.intel.com> (raw)
In-Reply-To: <20200429153205.09c498cd@collabora.com>
Hi Boris,
Thank you very much for the review comments and your time...
On 29/4/2020 9:32 pm, Boris Brezillon wrote:
> On Wed, 29 Apr 2020 21:29:40 +0800
> "Ramuthevar, Vadivel MuruganX"
> <vadivel.muruganx.ramuthevar@linux.intel.com> wrote:
>
>> Hi Boris,
>>
>> Thank you very much for the review comments and your time..
>>
>> On 29/4/2020 7:33 pm, Boris Brezillon wrote:
>>> On Wed, 29 Apr 2020 18:42:05 +0800
>>> "Ramuthevar,Vadivel MuruganX"
>>> <vadivel.muruganx.ramuthevar@linux.intel.com> wrote:
>>>
>>>> +#define NAND_WRITE_CMD (EBU_CON_CS_P_LOW | HSNAND_CLE_OFFS)
>>>> +#define NAND_WRITE_ADDR (EBU_CON_CS_P_LOW | HSNAND_ALE_OFFS)
>>>> +
>>>
>>> I thought we agreed on dropping those definitions.
>>
>> Yes , we agreed upon it, due to assertion/de-assertion of CS kept it.
>
> And I keep thinking we don't need that, just pass
> 'HSNAND_CLE_OFFS | HSNAND_CS_OFFS' directly.
Agreed!, will update in the next-patch version, Thanks!
Regards
Vadivel
>
WARNING: multiple messages have this Message-ID (diff)
From: "Ramuthevar, Vadivel MuruganX" <vadivel.muruganx.ramuthevar@linux.intel.com>
To: Boris Brezillon <boris.brezillon@collabora.com>
Cc: cheol.yong.kim@intel.com, devicetree@vger.kernel.org,
qi-ming.wu@intel.com, anders.roxell@linaro.org, vigneshr@ti.com,
arnd@arndb.de, hauke.mehrtens@intel.com, richard@nod.at,
brendanhiggins@google.com, linux-kernel@vger.kernel.org,
linux-mips@vger.kernel.org, robh+dt@kernel.org,
linux-mtd@lists.infradead.org, miquel.raynal@bootlin.com,
tglx@linutronix.de, masonccyang@mxic.com.tw,
andriy.shevchenko@intel.com
Subject: Re: [PATCH v4 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC
Date: Wed, 29 Apr 2020 22:26:25 +0800 [thread overview]
Message-ID: <6b3ad9f3-2a3c-b44c-3c3f-24f2178dd3fa@linux.intel.com> (raw)
In-Reply-To: <20200429153205.09c498cd@collabora.com>
Hi Boris,
Thank you very much for the review comments and your time...
On 29/4/2020 9:32 pm, Boris Brezillon wrote:
> On Wed, 29 Apr 2020 21:29:40 +0800
> "Ramuthevar, Vadivel MuruganX"
> <vadivel.muruganx.ramuthevar@linux.intel.com> wrote:
>
>> Hi Boris,
>>
>> Thank you very much for the review comments and your time..
>>
>> On 29/4/2020 7:33 pm, Boris Brezillon wrote:
>>> On Wed, 29 Apr 2020 18:42:05 +0800
>>> "Ramuthevar,Vadivel MuruganX"
>>> <vadivel.muruganx.ramuthevar@linux.intel.com> wrote:
>>>
>>>> +#define NAND_WRITE_CMD (EBU_CON_CS_P_LOW | HSNAND_CLE_OFFS)
>>>> +#define NAND_WRITE_ADDR (EBU_CON_CS_P_LOW | HSNAND_ALE_OFFS)
>>>> +
>>>
>>> I thought we agreed on dropping those definitions.
>>
>> Yes , we agreed upon it, due to assertion/de-assertion of CS kept it.
>
> And I keep thinking we don't need that, just pass
> 'HSNAND_CLE_OFFS | HSNAND_CS_OFFS' directly.
Agreed!, will update in the next-patch version, Thanks!
Regards
Vadivel
>
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Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2020-04-29 14:26 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-29 10:42 [PATCH v4 0/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC Ramuthevar,Vadivel MuruganX
2020-04-29 10:42 ` Ramuthevar, Vadivel MuruganX
2020-04-29 10:42 ` [PATCH v4 1/2] dt-bindings: mtd: Add YAML for Nand Flash Controller support Ramuthevar,Vadivel MuruganX
2020-04-29 10:42 ` Ramuthevar, Vadivel MuruganX
2020-04-29 15:34 ` Boris Brezillon
2020-04-29 15:34 ` Boris Brezillon
2020-04-30 1:07 ` Ramuthevar, Vadivel MuruganX
2020-04-30 1:07 ` Ramuthevar, Vadivel MuruganX
2020-04-29 10:42 ` [PATCH v4 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC Ramuthevar,Vadivel MuruganX
2020-04-29 10:42 ` Ramuthevar, Vadivel MuruganX
2020-04-29 11:33 ` Boris Brezillon
2020-04-29 11:33 ` Boris Brezillon
2020-04-29 13:29 ` Ramuthevar, Vadivel MuruganX
2020-04-29 13:29 ` Ramuthevar, Vadivel MuruganX
2020-04-29 13:32 ` Boris Brezillon
2020-04-29 13:32 ` Boris Brezillon
2020-04-29 14:26 ` Ramuthevar, Vadivel MuruganX [this message]
2020-04-29 14:26 ` Ramuthevar, Vadivel MuruganX
2020-04-29 14:22 ` Boris Brezillon
2020-04-29 14:22 ` Boris Brezillon
2020-04-29 14:33 ` Ramuthevar, Vadivel MuruganX
2020-04-29 14:33 ` Ramuthevar, Vadivel MuruganX
2020-04-29 14:48 ` Boris Brezillon
2020-04-29 14:48 ` Boris Brezillon
2020-04-29 15:18 ` Ramuthevar, Vadivel MuruganX
2020-04-29 15:18 ` Ramuthevar, Vadivel MuruganX
2020-04-29 15:29 ` Ramuthevar, Vadivel MuruganX
2020-04-29 15:29 ` Ramuthevar, Vadivel MuruganX
2020-04-29 15:31 ` Boris Brezillon
2020-04-29 15:31 ` Boris Brezillon
2020-04-30 7:50 ` Ramuthevar, Vadivel MuruganX
2020-04-30 7:50 ` Ramuthevar, Vadivel MuruganX
2020-04-30 8:21 ` Boris Brezillon
2020-04-30 8:21 ` Boris Brezillon
2020-04-30 8:30 ` Ramuthevar, Vadivel MuruganX
2020-04-30 8:30 ` Ramuthevar, Vadivel MuruganX
2020-04-30 8:36 ` Boris Brezillon
2020-04-30 8:36 ` Boris Brezillon
2020-04-30 9:07 ` Ramuthevar, Vadivel MuruganX
2020-04-30 9:07 ` Ramuthevar, Vadivel MuruganX
2020-04-30 12:36 ` Boris Brezillon
2020-04-30 12:36 ` Boris Brezillon
2020-04-30 13:01 ` Boris Brezillon
2020-04-30 13:01 ` Boris Brezillon
2020-05-04 1:58 ` Ramuthevar, Vadivel MuruganX
2020-05-04 1:58 ` Ramuthevar, Vadivel MuruganX
2020-05-04 2:02 ` Ramuthevar, Vadivel MuruganX
2020-05-04 2:02 ` Ramuthevar, Vadivel MuruganX
2020-05-04 7:08 ` Boris Brezillon
2020-05-04 7:08 ` Boris Brezillon
2020-05-04 7:15 ` Ramuthevar, Vadivel MuruganX
2020-05-04 7:15 ` Ramuthevar, Vadivel MuruganX
2020-05-04 7:17 ` Boris Brezillon
2020-05-04 7:17 ` Boris Brezillon
2020-05-04 8:50 ` Ramuthevar, Vadivel MuruganX
2020-05-04 8:50 ` Ramuthevar, Vadivel MuruganX
2020-05-04 8:58 ` Boris Brezillon
2020-05-04 8:58 ` Boris Brezillon
2020-05-04 9:17 ` Ramuthevar, Vadivel MuruganX
2020-05-04 9:17 ` Ramuthevar, Vadivel MuruganX
2020-05-05 5:28 ` Ramuthevar, Vadivel MuruganX
2020-05-05 5:28 ` Ramuthevar, Vadivel MuruganX
2020-05-05 7:00 ` Boris Brezillon
2020-05-05 7:00 ` Boris Brezillon
2020-05-05 7:17 ` Ramuthevar, Vadivel MuruganX
2020-05-05 7:17 ` Ramuthevar, Vadivel MuruganX
2020-05-04 1:54 ` Ramuthevar, Vadivel MuruganX
2020-05-04 1:54 ` Ramuthevar, Vadivel MuruganX
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