From: "Ramuthevar, Vadivel MuruganX" <vadivel.muruganx.ramuthevar@linux.intel.com> To: Boris Brezillon <boris.brezillon@collabora.com> Cc: cheol.yong.kim@intel.com, devicetree@vger.kernel.org, masonccyang@mxic.com.tw, anders.roxell@linaro.org, vigneshr@ti.com, arnd@arndb.de, hauke.mehrtens@intel.com, richard@nod.at, brendanhiggins@google.com, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, robh+dt@kernel.org, linux-mtd@lists.infradead.org, miquel.raynal@bootlin.com, tglx@linutronix.de, qi-ming.wu@intel.com, andriy.shevchenko@intel.com Subject: Re: [PATCH v4 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC Date: Mon, 4 May 2020 10:02:35 +0800 [thread overview] Message-ID: <df7c1952-bc9b-bad7-bf31-d09707a0829e@linux.intel.com> (raw) In-Reply-To: <20200430150124.7856d112@collabora.com> Hi Boris, On 30/4/2020 9:01 pm, Boris Brezillon wrote: > On Thu, 30 Apr 2020 14:36:00 +0200 > Boris Brezillon <boris.brezillon@collabora.com> wrote: > >> On Thu, 30 Apr 2020 17:07:03 +0800 >> "Ramuthevar, Vadivel MuruganX" >> <vadivel.muruganx.ramuthevar@linux.intel.com> wrote: >> >>>>>> The question is, is it the same value we have in nand_pa or it is >>>>>> different? >>>>>> >>>>> Different address which is 0xE1400000 NAND_BASE_PHY address. >>>> >>>> Then why didn't you tell me they didn't match when I suggested to pass >>> >>> sorry, because you keep asking nand_pa after that only I realized that. >>> >>>> nand_pa? So now the question is, what does this address represent? >>> >>> EBU-MODULE >>> _________ _______________________ >>> | | | |NAND CTRL | >>> | FPI BUS |==>| CS0(0x174) | 0xE100 ( 0xE14/0xE1C) NAND_PHY_BASE >>> |_________| |_CS1(0x17C)_|__________ | >>> >>> EBU_CONRTROLLER_BASE : 0xE0F0_0000 >>> HSNAND_BASE: 0xE100_0000 >>> NAND_CS0: 0xE140_0000 >>> NAND_CS1: 0xE1C0_0000 >>> >>> MEM_REGION_BASE_CS0: 0x17400 (internal to ebu controller ) >>> MEM_REGION_BASE_CS1: 0x17C00 >>> >> >> Hm, I wonder if we shouldn't use a 'ranges' property to describe this >> address translation. Something like >> >> ebu@xxx { >> ranges = <0x17400000 0xe1400000 0x1000>, >> <0x17c00000 0xe1c00000 0x1000>; >> reg = <0x17400000>, <0x17c00000>; >> reg-names = "cs-0", "cs-1"; >> } >> >> The translated address (0xE1X00000) will be available in res->start, >> and the non-translated one (0x17X00000) can be retrieved with >> of_get_address(). All you'd have to do then would be calculate the >> mask: >> >> mask = (translated_address & original_address) >> 22; >> num_comp_bits = fls(mask); >> WARN_ON(mask != GENMASK(num_comp_bits - 1, 0)); >> >> Which allows you to properly set the ADDR_SEL() register without >> relying on some hardcoded values: >> >> writel(original_address | EBU_ADDR_SEL_REGEN | >> EBU_ADDR_COMP_BITS(num_comp_bits), >> ebu_host->ebu + EBU_ADDR_SEL(csid)); >> >> That's quite important if we want to merge the xway NAND driver with >> this one. > > Looks like the translation is done at the FPI bus declaration level (see > [1]). We really need to see the big picture to take a wise decision > about the bindings. Would you mind pasting your dsti/dts files > somewhere? It feels like the NAND controller is a sub-part of a more > generic 'memory' controller, in which case the NAND controller should be > declared as a child of this generic memory bus (called localbus in [1], > but maybe EBU is more accurate). > > [1]https://github.com/xieyaxiongfly/Atheros_CSI_tool_OpenWRT_src/blob/master/target/linux/lantiq/files-4.14/arch/mips/boot/dts/vr9.dtsi#L162 ebu_nand: ebu_nand@e0f00000 { compatible = "intel,lgm-ebu-nand"; reg = <0xe0f00000 0x100 0xe1000000 0x300 0xe1400000 0x80000 0xe1c00000 0x10000>; reg-names = "ebunand", "hsnand", "nand_cs0", nand_cs1"; dmas = <&dma0 8>, <&dma0 9>; dma-names = "ebu_rx", "ebu_tx"; clocks = <&cgu0 LGM_GCLK_EBU>; }; &ebu_nand { status = "disabled"; nand,cs = <1>; nand-ecc-mode = "hw"; pinctrl-names = "default"; pinctrl-0 = <&ebu_nand_base &ebu_cs1>; }; >
WARNING: multiple messages have this Message-ID (diff)
From: "Ramuthevar, Vadivel MuruganX" <vadivel.muruganx.ramuthevar@linux.intel.com> To: Boris Brezillon <boris.brezillon@collabora.com> Cc: cheol.yong.kim@intel.com, devicetree@vger.kernel.org, qi-ming.wu@intel.com, anders.roxell@linaro.org, vigneshr@ti.com, arnd@arndb.de, hauke.mehrtens@intel.com, richard@nod.at, brendanhiggins@google.com, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, robh+dt@kernel.org, linux-mtd@lists.infradead.org, miquel.raynal@bootlin.com, tglx@linutronix.de, masonccyang@mxic.com.tw, andriy.shevchenko@intel.com Subject: Re: [PATCH v4 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC Date: Mon, 4 May 2020 10:02:35 +0800 [thread overview] Message-ID: <df7c1952-bc9b-bad7-bf31-d09707a0829e@linux.intel.com> (raw) In-Reply-To: <20200430150124.7856d112@collabora.com> Hi Boris, On 30/4/2020 9:01 pm, Boris Brezillon wrote: > On Thu, 30 Apr 2020 14:36:00 +0200 > Boris Brezillon <boris.brezillon@collabora.com> wrote: > >> On Thu, 30 Apr 2020 17:07:03 +0800 >> "Ramuthevar, Vadivel MuruganX" >> <vadivel.muruganx.ramuthevar@linux.intel.com> wrote: >> >>>>>> The question is, is it the same value we have in nand_pa or it is >>>>>> different? >>>>>> >>>>> Different address which is 0xE1400000 NAND_BASE_PHY address. >>>> >>>> Then why didn't you tell me they didn't match when I suggested to pass >>> >>> sorry, because you keep asking nand_pa after that only I realized that. >>> >>>> nand_pa? So now the question is, what does this address represent? >>> >>> EBU-MODULE >>> _________ _______________________ >>> | | | |NAND CTRL | >>> | FPI BUS |==>| CS0(0x174) | 0xE100 ( 0xE14/0xE1C) NAND_PHY_BASE >>> |_________| |_CS1(0x17C)_|__________ | >>> >>> EBU_CONRTROLLER_BASE : 0xE0F0_0000 >>> HSNAND_BASE: 0xE100_0000 >>> NAND_CS0: 0xE140_0000 >>> NAND_CS1: 0xE1C0_0000 >>> >>> MEM_REGION_BASE_CS0: 0x17400 (internal to ebu controller ) >>> MEM_REGION_BASE_CS1: 0x17C00 >>> >> >> Hm, I wonder if we shouldn't use a 'ranges' property to describe this >> address translation. Something like >> >> ebu@xxx { >> ranges = <0x17400000 0xe1400000 0x1000>, >> <0x17c00000 0xe1c00000 0x1000>; >> reg = <0x17400000>, <0x17c00000>; >> reg-names = "cs-0", "cs-1"; >> } >> >> The translated address (0xE1X00000) will be available in res->start, >> and the non-translated one (0x17X00000) can be retrieved with >> of_get_address(). All you'd have to do then would be calculate the >> mask: >> >> mask = (translated_address & original_address) >> 22; >> num_comp_bits = fls(mask); >> WARN_ON(mask != GENMASK(num_comp_bits - 1, 0)); >> >> Which allows you to properly set the ADDR_SEL() register without >> relying on some hardcoded values: >> >> writel(original_address | EBU_ADDR_SEL_REGEN | >> EBU_ADDR_COMP_BITS(num_comp_bits), >> ebu_host->ebu + EBU_ADDR_SEL(csid)); >> >> That's quite important if we want to merge the xway NAND driver with >> this one. > > Looks like the translation is done at the FPI bus declaration level (see > [1]). We really need to see the big picture to take a wise decision > about the bindings. Would you mind pasting your dsti/dts files > somewhere? It feels like the NAND controller is a sub-part of a more > generic 'memory' controller, in which case the NAND controller should be > declared as a child of this generic memory bus (called localbus in [1], > but maybe EBU is more accurate). > > [1]https://github.com/xieyaxiongfly/Atheros_CSI_tool_OpenWRT_src/blob/master/target/linux/lantiq/files-4.14/arch/mips/boot/dts/vr9.dtsi#L162 ebu_nand: ebu_nand@e0f00000 { compatible = "intel,lgm-ebu-nand"; reg = <0xe0f00000 0x100 0xe1000000 0x300 0xe1400000 0x80000 0xe1c00000 0x10000>; reg-names = "ebunand", "hsnand", "nand_cs0", nand_cs1"; dmas = <&dma0 8>, <&dma0 9>; dma-names = "ebu_rx", "ebu_tx"; clocks = <&cgu0 LGM_GCLK_EBU>; }; &ebu_nand { status = "disabled"; nand,cs = <1>; nand-ecc-mode = "hw"; pinctrl-names = "default"; pinctrl-0 = <&ebu_nand_base &ebu_cs1>; }; > ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2020-05-04 2:02 UTC|newest] Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-04-29 10:42 [PATCH v4 0/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC Ramuthevar,Vadivel MuruganX 2020-04-29 10:42 ` Ramuthevar, Vadivel MuruganX 2020-04-29 10:42 ` [PATCH v4 1/2] dt-bindings: mtd: Add YAML for Nand Flash Controller support Ramuthevar,Vadivel MuruganX 2020-04-29 10:42 ` Ramuthevar, Vadivel MuruganX 2020-04-29 15:34 ` Boris Brezillon 2020-04-29 15:34 ` Boris Brezillon 2020-04-30 1:07 ` Ramuthevar, Vadivel MuruganX 2020-04-30 1:07 ` Ramuthevar, Vadivel MuruganX 2020-04-29 10:42 ` [PATCH v4 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC Ramuthevar,Vadivel MuruganX 2020-04-29 10:42 ` Ramuthevar, Vadivel MuruganX 2020-04-29 11:33 ` Boris Brezillon 2020-04-29 11:33 ` Boris Brezillon 2020-04-29 13:29 ` Ramuthevar, Vadivel MuruganX 2020-04-29 13:29 ` Ramuthevar, Vadivel MuruganX 2020-04-29 13:32 ` Boris Brezillon 2020-04-29 13:32 ` Boris Brezillon 2020-04-29 14:26 ` Ramuthevar, Vadivel MuruganX 2020-04-29 14:26 ` Ramuthevar, Vadivel MuruganX 2020-04-29 14:22 ` Boris Brezillon 2020-04-29 14:22 ` Boris Brezillon 2020-04-29 14:33 ` Ramuthevar, Vadivel MuruganX 2020-04-29 14:33 ` Ramuthevar, Vadivel MuruganX 2020-04-29 14:48 ` Boris Brezillon 2020-04-29 14:48 ` Boris Brezillon 2020-04-29 15:18 ` Ramuthevar, Vadivel MuruganX 2020-04-29 15:18 ` Ramuthevar, Vadivel MuruganX 2020-04-29 15:29 ` Ramuthevar, Vadivel MuruganX 2020-04-29 15:29 ` Ramuthevar, Vadivel MuruganX 2020-04-29 15:31 ` Boris Brezillon 2020-04-29 15:31 ` Boris Brezillon 2020-04-30 7:50 ` Ramuthevar, Vadivel MuruganX 2020-04-30 7:50 ` Ramuthevar, Vadivel MuruganX 2020-04-30 8:21 ` Boris Brezillon 2020-04-30 8:21 ` Boris Brezillon 2020-04-30 8:30 ` Ramuthevar, Vadivel MuruganX 2020-04-30 8:30 ` Ramuthevar, Vadivel MuruganX 2020-04-30 8:36 ` Boris Brezillon 2020-04-30 8:36 ` Boris Brezillon 2020-04-30 9:07 ` Ramuthevar, Vadivel MuruganX 2020-04-30 9:07 ` Ramuthevar, Vadivel MuruganX 2020-04-30 12:36 ` Boris Brezillon 2020-04-30 12:36 ` Boris Brezillon 2020-04-30 13:01 ` Boris Brezillon 2020-04-30 13:01 ` Boris Brezillon 2020-05-04 1:58 ` Ramuthevar, Vadivel MuruganX 2020-05-04 1:58 ` Ramuthevar, Vadivel MuruganX 2020-05-04 2:02 ` Ramuthevar, Vadivel MuruganX [this message] 2020-05-04 2:02 ` Ramuthevar, Vadivel MuruganX 2020-05-04 7:08 ` Boris Brezillon 2020-05-04 7:08 ` Boris Brezillon 2020-05-04 7:15 ` Ramuthevar, Vadivel MuruganX 2020-05-04 7:15 ` Ramuthevar, Vadivel MuruganX 2020-05-04 7:17 ` Boris Brezillon 2020-05-04 7:17 ` Boris Brezillon 2020-05-04 8:50 ` Ramuthevar, Vadivel MuruganX 2020-05-04 8:50 ` Ramuthevar, Vadivel MuruganX 2020-05-04 8:58 ` Boris Brezillon 2020-05-04 8:58 ` Boris Brezillon 2020-05-04 9:17 ` Ramuthevar, Vadivel MuruganX 2020-05-04 9:17 ` Ramuthevar, Vadivel MuruganX 2020-05-05 5:28 ` Ramuthevar, Vadivel MuruganX 2020-05-05 5:28 ` Ramuthevar, Vadivel MuruganX 2020-05-05 7:00 ` Boris Brezillon 2020-05-05 7:00 ` Boris Brezillon 2020-05-05 7:17 ` Ramuthevar, Vadivel MuruganX 2020-05-05 7:17 ` Ramuthevar, Vadivel MuruganX 2020-05-04 1:54 ` Ramuthevar, Vadivel MuruganX 2020-05-04 1:54 ` Ramuthevar, Vadivel MuruganX
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