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From: "Thomas Hellström (Intel)" <thomas_os@shipmail.org>
To: "Christian König" <christian.koenig@amd.com>,
	"Daniel Vetter" <daniel@ffwll.ch>
Cc: DRI Development <dri-devel@lists.freedesktop.org>,
	Daniel Stone <daniels@collabora.com>,
	linux-rdma <linux-rdma@vger.kernel.org>,
	Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	amd-gfx list <amd-gfx@lists.freedesktop.org>,
	"moderated list:DMA BUFFER SHARING FRAMEWORK" 
	<linaro-mm-sig@lists.linaro.org>,
	Steve Pronovost <spronovo@microsoft.com>,
	Daniel Vetter <daniel.vetter@intel.com>,
	Jason Ekstrand <jason@jlekstrand.net>,
	Jesse Natalie <jenatali@microsoft.com>,
	Felix Kuehling <Felix.Kuehling@amd.com>,
	Thomas Hellstrom <thomas.hellstrom@intel.com>,
	"open list:DMA BUFFER SHARING FRAMEWORK" 
	<linux-media@vger.kernel.org>,
	Mika Kuoppala <mika.kuoppala@intel.com>
Subject: Re: [Linaro-mm-sig] [PATCH 1/2] dma-buf.rst: Document why indefinite fences are a bad idea
Date: Tue, 21 Jul 2020 19:46:25 +0200	[thread overview]
Message-ID: <6ed364c9-893b-8974-501a-418585eb4def@shipmail.org> (raw)
In-Reply-To: <f8f73b9f-ce8d-ea02-7caa-d50b75b72809@amd.com>


On 2020-07-21 15:59, Christian König wrote:
> Am 21.07.20 um 12:47 schrieb Thomas Hellström (Intel):
...
>> Yes, we can't do magic. As soon as an indefinite batch makes it to 
>> such hardware we've lost. But since we can break out while the batch 
>> is stuck in the scheduler waiting, what I believe we *can* do with 
>> this approach is to avoid deadlocks due to locally unknown 
>> dependencies, which has some bearing on this documentation patch, and 
>> also to allow memory allocation in dma-fence (not memory-fence) 
>> critical sections, like gpu fault- and error handlers without 
>> resorting to using memory pools.
>
> Avoiding deadlocks is only the tip of the iceberg here.
>
> When you allow the kernel to depend on user space to proceed with some 
> operation there are a lot more things which need consideration.
>
> E.g. what happens when an userspace process which has submitted stuff 
> to the kernel is killed? Are the prepared commands send to the 
> hardware or aborted as well? What do we do with other processes 
> waiting for that stuff?
>
> How to we do resource accounting? When processes need to block when 
> submitting to the hardware stuff which is not ready we have a process 
> we can punish for blocking resources. But how is kernel memory used 
> for a submission accounted? How do we avoid deny of service attacks 
> here were somebody eats up all memory by doing submissions which can't 
> finish?
>
Hmm. Are these problems really unique to user-space controlled 
dependencies? Couldn't you hit the same or similar problems with 
mis-behaving shaders blocking timeline progress?

/Thomas




WARNING: multiple messages have this Message-ID (diff)
From: "Thomas Hellström (Intel)" <thomas_os@shipmail.org>
To: "Christian König" <christian.koenig@amd.com>,
	"Daniel Vetter" <daniel@ffwll.ch>
Cc: Daniel Stone <daniels@collabora.com>,
	linux-rdma <linux-rdma@vger.kernel.org>,
	Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
	amd-gfx list <amd-gfx@lists.freedesktop.org>,
	"moderated list:DMA BUFFER SHARING FRAMEWORK"
	<linaro-mm-sig@lists.linaro.org>,
	Steve Pronovost <spronovo@microsoft.com>,
	DRI Development <dri-devel@lists.freedesktop.org>,
	Jason Ekstrand <jason@jlekstrand.net>,
	Jesse Natalie <jenatali@microsoft.com>,
	Daniel Vetter <daniel.vetter@intel.com>,
	Thomas Hellstrom <thomas.hellstrom@intel.com>,
	Mika Kuoppala <mika.kuoppala@intel.com>,
	Felix Kuehling <Felix.Kuehling@amd.com>,
	"open list:DMA BUFFER SHARING FRAMEWORK"
	<linux-media@vger.kernel.org>
Subject: Re: [Linaro-mm-sig] [PATCH 1/2] dma-buf.rst: Document why indefinite fences are a bad idea
Date: Tue, 21 Jul 2020 19:46:25 +0200	[thread overview]
Message-ID: <6ed364c9-893b-8974-501a-418585eb4def@shipmail.org> (raw)
In-Reply-To: <f8f73b9f-ce8d-ea02-7caa-d50b75b72809@amd.com>


On 2020-07-21 15:59, Christian König wrote:
> Am 21.07.20 um 12:47 schrieb Thomas Hellström (Intel):
...
>> Yes, we can't do magic. As soon as an indefinite batch makes it to 
>> such hardware we've lost. But since we can break out while the batch 
>> is stuck in the scheduler waiting, what I believe we *can* do with 
>> this approach is to avoid deadlocks due to locally unknown 
>> dependencies, which has some bearing on this documentation patch, and 
>> also to allow memory allocation in dma-fence (not memory-fence) 
>> critical sections, like gpu fault- and error handlers without 
>> resorting to using memory pools.
>
> Avoiding deadlocks is only the tip of the iceberg here.
>
> When you allow the kernel to depend on user space to proceed with some 
> operation there are a lot more things which need consideration.
>
> E.g. what happens when an userspace process which has submitted stuff 
> to the kernel is killed? Are the prepared commands send to the 
> hardware or aborted as well? What do we do with other processes 
> waiting for that stuff?
>
> How to we do resource accounting? When processes need to block when 
> submitting to the hardware stuff which is not ready we have a process 
> we can punish for blocking resources. But how is kernel memory used 
> for a submission accounted? How do we avoid deny of service attacks 
> here were somebody eats up all memory by doing submissions which can't 
> finish?
>
Hmm. Are these problems really unique to user-space controlled 
dependencies? Couldn't you hit the same or similar problems with 
mis-behaving shaders blocking timeline progress?

/Thomas



_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

WARNING: multiple messages have this Message-ID (diff)
From: "Thomas Hellström (Intel)" <thomas_os@shipmail.org>
To: "Christian König" <christian.koenig@amd.com>,
	"Daniel Vetter" <daniel@ffwll.ch>
Cc: Daniel Stone <daniels@collabora.com>,
	linux-rdma <linux-rdma@vger.kernel.org>,
	Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
	amd-gfx list <amd-gfx@lists.freedesktop.org>,
	"moderated list:DMA BUFFER SHARING FRAMEWORK"
	<linaro-mm-sig@lists.linaro.org>,
	Steve Pronovost <spronovo@microsoft.com>,
	DRI Development <dri-devel@lists.freedesktop.org>,
	Jesse Natalie <jenatali@microsoft.com>,
	Daniel Vetter <daniel.vetter@intel.com>,
	Thomas Hellstrom <thomas.hellstrom@intel.com>,
	Mika Kuoppala <mika.kuoppala@intel.com>,
	Felix Kuehling <Felix.Kuehling@amd.com>,
	"open list:DMA BUFFER SHARING FRAMEWORK"
	<linux-media@vger.kernel.org>
Subject: Re: [Intel-gfx] [Linaro-mm-sig] [PATCH 1/2] dma-buf.rst: Document why indefinite fences are a bad idea
Date: Tue, 21 Jul 2020 19:46:25 +0200	[thread overview]
Message-ID: <6ed364c9-893b-8974-501a-418585eb4def@shipmail.org> (raw)
In-Reply-To: <f8f73b9f-ce8d-ea02-7caa-d50b75b72809@amd.com>


On 2020-07-21 15:59, Christian König wrote:
> Am 21.07.20 um 12:47 schrieb Thomas Hellström (Intel):
...
>> Yes, we can't do magic. As soon as an indefinite batch makes it to 
>> such hardware we've lost. But since we can break out while the batch 
>> is stuck in the scheduler waiting, what I believe we *can* do with 
>> this approach is to avoid deadlocks due to locally unknown 
>> dependencies, which has some bearing on this documentation patch, and 
>> also to allow memory allocation in dma-fence (not memory-fence) 
>> critical sections, like gpu fault- and error handlers without 
>> resorting to using memory pools.
>
> Avoiding deadlocks is only the tip of the iceberg here.
>
> When you allow the kernel to depend on user space to proceed with some 
> operation there are a lot more things which need consideration.
>
> E.g. what happens when an userspace process which has submitted stuff 
> to the kernel is killed? Are the prepared commands send to the 
> hardware or aborted as well? What do we do with other processes 
> waiting for that stuff?
>
> How to we do resource accounting? When processes need to block when 
> submitting to the hardware stuff which is not ready we have a process 
> we can punish for blocking resources. But how is kernel memory used 
> for a submission accounted? How do we avoid deny of service attacks 
> here were somebody eats up all memory by doing submissions which can't 
> finish?
>
Hmm. Are these problems really unique to user-space controlled 
dependencies? Couldn't you hit the same or similar problems with 
mis-behaving shaders blocking timeline progress?

/Thomas



_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: "Thomas Hellström (Intel)" <thomas_os@shipmail.org>
To: "Christian König" <christian.koenig@amd.com>,
	"Daniel Vetter" <daniel@ffwll.ch>
Cc: Daniel Stone <daniels@collabora.com>,
	linux-rdma <linux-rdma@vger.kernel.org>,
	Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	amd-gfx list <amd-gfx@lists.freedesktop.org>,
	"moderated list:DMA BUFFER SHARING FRAMEWORK"
	<linaro-mm-sig@lists.linaro.org>,
	Steve Pronovost <spronovo@microsoft.com>,
	DRI Development <dri-devel@lists.freedesktop.org>,
	Jason Ekstrand <jason@jlekstrand.net>,
	Jesse Natalie <jenatali@microsoft.com>,
	Daniel Vetter <daniel.vetter@intel.com>,
	Thomas Hellstrom <thomas.hellstrom@intel.com>,
	Mika Kuoppala <mika.kuoppala@intel.com>,
	Felix Kuehling <Felix.Kuehling@amd.com>,
	"open list:DMA BUFFER SHARING FRAMEWORK"
	<linux-media@vger.kernel.org>
Subject: Re: [Linaro-mm-sig] [PATCH 1/2] dma-buf.rst: Document why indefinite fences are a bad idea
Date: Tue, 21 Jul 2020 19:46:25 +0200	[thread overview]
Message-ID: <6ed364c9-893b-8974-501a-418585eb4def@shipmail.org> (raw)
In-Reply-To: <f8f73b9f-ce8d-ea02-7caa-d50b75b72809@amd.com>


On 2020-07-21 15:59, Christian König wrote:
> Am 21.07.20 um 12:47 schrieb Thomas Hellström (Intel):
...
>> Yes, we can't do magic. As soon as an indefinite batch makes it to 
>> such hardware we've lost. But since we can break out while the batch 
>> is stuck in the scheduler waiting, what I believe we *can* do with 
>> this approach is to avoid deadlocks due to locally unknown 
>> dependencies, which has some bearing on this documentation patch, and 
>> also to allow memory allocation in dma-fence (not memory-fence) 
>> critical sections, like gpu fault- and error handlers without 
>> resorting to using memory pools.
>
> Avoiding deadlocks is only the tip of the iceberg here.
>
> When you allow the kernel to depend on user space to proceed with some 
> operation there are a lot more things which need consideration.
>
> E.g. what happens when an userspace process which has submitted stuff 
> to the kernel is killed? Are the prepared commands send to the 
> hardware or aborted as well? What do we do with other processes 
> waiting for that stuff?
>
> How to we do resource accounting? When processes need to block when 
> submitting to the hardware stuff which is not ready we have a process 
> we can punish for blocking resources. But how is kernel memory used 
> for a submission accounted? How do we avoid deny of service attacks 
> here were somebody eats up all memory by doing submissions which can't 
> finish?
>
Hmm. Are these problems really unique to user-space controlled 
dependencies? Couldn't you hit the same or similar problems with 
mis-behaving shaders blocking timeline progress?

/Thomas



_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

  reply	other threads:[~2020-07-21 17:46 UTC|newest]

Thread overview: 467+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-07 20:12 [PATCH 00/25] dma-fence annotations, round 3 Daniel Vetter
2020-07-07 20:12 ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12 ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 01/25] dma-fence: basic lockdep annotations Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-08 14:57   ` Christian König
2020-07-08 14:57     ` Christian König
2020-07-08 14:57     ` [Intel-gfx] " Christian König
2020-07-08 14:57     ` Christian König
2020-07-08 15:12     ` Daniel Vetter
2020-07-08 15:12       ` Daniel Vetter
2020-07-08 15:12       ` [Intel-gfx] " Daniel Vetter
2020-07-08 15:12       ` Daniel Vetter
2020-07-08 15:19       ` Alex Deucher
2020-07-08 15:19         ` Alex Deucher
2020-07-08 15:19         ` [Intel-gfx] " Alex Deucher
2020-07-08 15:19         ` Alex Deucher
2020-07-08 15:37         ` Daniel Vetter
2020-07-08 15:37           ` Daniel Vetter
2020-07-08 15:37           ` [Intel-gfx] " Daniel Vetter
2020-07-08 15:37           ` Daniel Vetter
2020-07-14 11:09           ` Daniel Vetter
2020-07-14 11:09             ` Daniel Vetter
2020-07-14 11:09             ` [Intel-gfx] " Daniel Vetter
2020-07-14 11:09             ` Daniel Vetter
2020-07-09  7:32       ` [Intel-gfx] " Daniel Stone
2020-07-09  7:32         ` Daniel Stone
2020-07-09  7:32         ` Daniel Stone
2020-07-09  7:32         ` Daniel Stone
2020-07-09  7:52         ` Daniel Vetter
2020-07-09  7:52           ` Daniel Vetter
2020-07-09  7:52           ` Daniel Vetter
2020-07-09  7:52           ` Daniel Vetter
2020-07-13 16:26     ` Daniel Vetter
2020-07-13 16:26       ` Daniel Vetter
2020-07-13 16:26       ` [Intel-gfx] " Daniel Vetter
2020-07-13 16:26       ` Daniel Vetter
2020-07-13 16:39       ` Christian König
2020-07-13 16:39         ` Christian König
2020-07-13 16:39         ` [Intel-gfx] " Christian König
2020-07-13 16:39         ` Christian König
2020-07-13 20:31         ` Dave Airlie
2020-07-13 20:31           ` Dave Airlie
2020-07-13 20:31           ` [Intel-gfx] " Dave Airlie
2020-07-13 20:31           ` Dave Airlie
2020-07-07 20:12 ` [PATCH 02/25] dma-fence: prime " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-09  8:09   ` Daniel Vetter
2020-07-09  8:09     ` Daniel Vetter
2020-07-09  8:09     ` [Intel-gfx] " Daniel Vetter
2020-07-09  8:09     ` Daniel Vetter
2020-07-10 12:43     ` Jason Gunthorpe
2020-07-10 12:43       ` Jason Gunthorpe
2020-07-10 12:43       ` [Intel-gfx] " Jason Gunthorpe
2020-07-10 12:43       ` Jason Gunthorpe
2020-07-10 12:48       ` Christian König
2020-07-10 12:48         ` Christian König
2020-07-10 12:48         ` [Intel-gfx] " Christian König
2020-07-10 12:48         ` Christian König
2020-07-10 12:54         ` Jason Gunthorpe
2020-07-10 12:54           ` Jason Gunthorpe
2020-07-10 12:54           ` [Intel-gfx] " Jason Gunthorpe
2020-07-10 12:54           ` Jason Gunthorpe
2020-07-10 13:01           ` Christian König
2020-07-10 13:01             ` Christian König
2020-07-10 13:01             ` [Intel-gfx] " Christian König
2020-07-10 13:01             ` Christian König
2020-07-10 13:48             ` Jason Gunthorpe
2020-07-10 13:48               ` Jason Gunthorpe
2020-07-10 13:48               ` [Intel-gfx] " Jason Gunthorpe
2020-07-10 13:48               ` Jason Gunthorpe
2020-07-10 14:02               ` Daniel Vetter
2020-07-10 14:02                 ` Daniel Vetter
2020-07-10 14:02                 ` [Intel-gfx] " Daniel Vetter
2020-07-10 14:02                 ` Daniel Vetter
2020-07-10 14:23                 ` Jason Gunthorpe
2020-07-10 14:23                   ` Jason Gunthorpe
2020-07-10 14:23                   ` [Intel-gfx] " Jason Gunthorpe
2020-07-10 14:23                   ` Jason Gunthorpe
2020-07-10 20:02                   ` Daniel Vetter
2020-07-10 20:02                     ` Daniel Vetter
2020-07-10 20:02                     ` [Intel-gfx] " Daniel Vetter
2020-07-10 20:02                     ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 03/25] dma-buf.rst: Document why idenfinite fences are a bad idea Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-09  7:36   ` [Intel-gfx] " Daniel Stone
2020-07-09  7:36     ` Daniel Stone
2020-07-09  7:36     ` Daniel Stone
2020-07-09  7:36     ` Daniel Stone
2020-07-09  8:04     ` Daniel Vetter
2020-07-09  8:04       ` Daniel Vetter
2020-07-09  8:04       ` Daniel Vetter
2020-07-09  8:04       ` Daniel Vetter
2020-07-09 12:11       ` Daniel Stone
2020-07-09 12:11         ` Daniel Stone
2020-07-09 12:11         ` Daniel Stone
2020-07-09 12:11         ` Daniel Stone
2020-07-09 12:31         ` Daniel Vetter
2020-07-09 12:31           ` Daniel Vetter
2020-07-09 12:31           ` Daniel Vetter
2020-07-09 12:31           ` Daniel Vetter
2020-07-09 14:28           ` Christian König
2020-07-09 14:28             ` Christian König
2020-07-09 14:28             ` Christian König
2020-07-09 14:28             ` Christian König
2020-07-09 11:53   ` Christian König
2020-07-09 11:53     ` Christian König
2020-07-09 11:53     ` [Intel-gfx] " Christian König
2020-07-09 11:53     ` Christian König
2020-07-09 12:33   ` [PATCH 1/2] dma-buf.rst: Document why indefinite " Daniel Vetter
2020-07-09 12:33     ` Daniel Vetter
2020-07-09 12:33     ` [Intel-gfx] " Daniel Vetter
2020-07-09 12:33     ` Daniel Vetter
2020-07-09 12:33     ` [PATCH 2/2] drm/virtio: Remove open-coded commit-tail function Daniel Vetter
2020-07-09 12:33       ` [Intel-gfx] " Daniel Vetter
2020-07-09 12:33       ` Daniel Vetter
2020-07-09 12:33       ` Daniel Vetter
2020-07-09 12:48       ` Gerd Hoffmann
2020-07-09 12:48         ` [Intel-gfx] " Gerd Hoffmann
2020-07-09 12:48         ` Gerd Hoffmann
2020-07-09 12:48         ` Gerd Hoffmann
2020-07-09 14:05       ` Sam Ravnborg
2020-07-09 14:05         ` [Intel-gfx] " Sam Ravnborg
2020-07-09 14:05         ` Sam Ravnborg
2020-07-09 14:05         ` Sam Ravnborg
2020-07-14  9:13         ` Daniel Vetter
2020-07-14  9:13           ` [Intel-gfx] " Daniel Vetter
2020-07-14  9:13           ` Daniel Vetter
2020-07-14  9:13           ` Daniel Vetter
2020-08-19 12:43       ` Jiri Slaby
2020-08-19 12:43         ` [Intel-gfx] " Jiri Slaby
2020-08-19 12:43         ` Jiri Slaby
2020-08-19 12:47         ` Jiri Slaby
2020-08-19 12:47           ` [Intel-gfx] " Jiri Slaby
2020-08-19 12:47           ` Jiri Slaby
2020-08-19 13:24         ` Gerd Hoffmann
2020-08-19 13:24           ` [Intel-gfx] " Gerd Hoffmann
2020-08-19 13:24           ` Gerd Hoffmann
2020-08-19 13:24           ` Gerd Hoffmann
2020-08-20  6:32           ` Jiri Slaby
2020-08-20  6:32             ` [Intel-gfx] " Jiri Slaby
2020-08-20  6:32             ` Jiri Slaby
2020-08-21  7:01             ` Gerd Hoffmann
2020-08-21  7:01               ` [Intel-gfx] " Gerd Hoffmann
2020-08-21  7:01               ` Gerd Hoffmann
2020-08-21  7:01               ` Gerd Hoffmann
2020-07-10 12:30     ` [PATCH 1/2] dma-buf.rst: Document why indefinite fences are a bad idea Maarten Lankhorst
2020-07-10 12:30       ` Maarten Lankhorst
2020-07-10 12:30       ` [Intel-gfx] " Maarten Lankhorst
2020-07-10 12:30       ` Maarten Lankhorst
2020-07-14 17:46     ` Jason Ekstrand
2020-07-14 17:46       ` Jason Ekstrand
2020-07-14 17:46       ` [Intel-gfx] " Jason Ekstrand
2020-07-14 17:46       ` Jason Ekstrand
2020-07-20 11:15     ` [Linaro-mm-sig] " Thomas Hellström (Intel)
2020-07-20 11:15       ` Thomas Hellström (Intel)
2020-07-20 11:15       ` [Intel-gfx] " Thomas Hellström (Intel)
2020-07-20 11:15       ` Thomas Hellström (Intel)
2020-07-21  7:41       ` Daniel Vetter
2020-07-21  7:41         ` Daniel Vetter
2020-07-21  7:41         ` [Intel-gfx] " Daniel Vetter
2020-07-21  7:41         ` Daniel Vetter
2020-07-21  7:45         ` Christian König
2020-07-21  7:45           ` Christian König
2020-07-21  7:45           ` [Intel-gfx] " Christian König
2020-07-21  7:45           ` Christian König
2020-07-21  8:47           ` Thomas Hellström (Intel)
2020-07-21  8:47             ` Thomas Hellström (Intel)
2020-07-21  8:47             ` [Intel-gfx] " Thomas Hellström (Intel)
2020-07-21  8:47             ` Thomas Hellström (Intel)
2020-07-21  8:55             ` Christian König
2020-07-21  8:55               ` Christian König
2020-07-21  8:55               ` [Intel-gfx] " Christian König
2020-07-21  8:55               ` Christian König
2020-07-21  9:16               ` Daniel Vetter
2020-07-21  9:16                 ` Daniel Vetter
2020-07-21  9:16                 ` [Intel-gfx] " Daniel Vetter
2020-07-21  9:16                 ` Daniel Vetter
2020-07-21  9:24                 ` Daniel Vetter
2020-07-21  9:24                   ` Daniel Vetter
2020-07-21  9:24                   ` [Intel-gfx] " Daniel Vetter
2020-07-21  9:24                   ` Daniel Vetter
2020-07-21  9:37               ` Thomas Hellström (Intel)
2020-07-21  9:37                 ` Thomas Hellström (Intel)
2020-07-21  9:37                 ` [Intel-gfx] " Thomas Hellström (Intel)
2020-07-21  9:37                 ` Thomas Hellström (Intel)
2020-07-21  9:50                 ` Daniel Vetter
2020-07-21  9:50                   ` Daniel Vetter
2020-07-21  9:50                   ` [Intel-gfx] " Daniel Vetter
2020-07-21  9:50                   ` Daniel Vetter
2020-07-21 10:47                   ` Thomas Hellström (Intel)
2020-07-21 10:47                     ` Thomas Hellström (Intel)
2020-07-21 10:47                     ` [Intel-gfx] " Thomas Hellström (Intel)
2020-07-21 10:47                     ` Thomas Hellström (Intel)
2020-07-21 13:59                     ` Christian König
2020-07-21 13:59                       ` Christian König
2020-07-21 13:59                       ` [Intel-gfx] " Christian König
2020-07-21 13:59                       ` Christian König
2020-07-21 17:46                       ` Thomas Hellström (Intel) [this message]
2020-07-21 17:46                         ` Thomas Hellström (Intel)
2020-07-21 17:46                         ` [Intel-gfx] " Thomas Hellström (Intel)
2020-07-21 17:46                         ` Thomas Hellström (Intel)
2020-07-21 18:18                         ` Daniel Vetter
2020-07-21 18:18                           ` Daniel Vetter
2020-07-21 18:18                           ` [Intel-gfx] " Daniel Vetter
2020-07-21 18:18                           ` Daniel Vetter
2020-07-21 21:42                       ` Dave Airlie
2020-07-21 21:42                         ` Dave Airlie
2020-07-21 21:42                         ` [Intel-gfx] " Dave Airlie
2020-07-21 21:42                         ` Dave Airlie
2020-07-21 22:45             ` Dave Airlie
2020-07-21 22:45               ` Dave Airlie
2020-07-21 22:45               ` [Intel-gfx] " Dave Airlie
2020-07-21 22:45               ` Dave Airlie
2020-07-22  6:45               ` Thomas Hellström (Intel)
2020-07-22  6:45                 ` Thomas Hellström (Intel)
2020-07-22  6:45                 ` [Intel-gfx] " Thomas Hellström (Intel)
2020-07-22  6:45                 ` Thomas Hellström (Intel)
2020-07-22  7:11                 ` Daniel Vetter
2020-07-22  7:11                   ` Daniel Vetter
2020-07-22  7:11                   ` [Intel-gfx] " Daniel Vetter
2020-07-22  7:11                   ` Daniel Vetter
2020-07-22  8:05                   ` Thomas Hellström (Intel)
2020-07-22  8:05                     ` Thomas Hellström (Intel)
2020-07-22  8:05                     ` [Intel-gfx] " Thomas Hellström (Intel)
2020-07-22  8:05                     ` Thomas Hellström (Intel)
2020-07-22  9:45                     ` Daniel Vetter
2020-07-22  9:45                       ` Daniel Vetter
2020-07-22  9:45                       ` [Intel-gfx] " Daniel Vetter
2020-07-22  9:45                       ` Daniel Vetter
2020-07-22 10:31                       ` Thomas Hellström (Intel)
2020-07-22 10:31                         ` Thomas Hellström (Intel)
2020-07-22 10:31                         ` [Intel-gfx] " Thomas Hellström (Intel)
2020-07-22 10:31                         ` Thomas Hellström (Intel)
2020-07-22 11:39                         ` Daniel Vetter
2020-07-22 11:39                           ` Daniel Vetter
2020-07-22 11:39                           ` [Intel-gfx] " Daniel Vetter
2020-07-22 11:39                           ` Daniel Vetter
2020-07-22 12:22                           ` Thomas Hellström (Intel)
2020-07-22 12:22                             ` Thomas Hellström (Intel)
2020-07-22 12:22                             ` [Intel-gfx] " Thomas Hellström (Intel)
2020-07-22 12:22                             ` Thomas Hellström (Intel)
2020-07-22 12:41                             ` Daniel Vetter
2020-07-22 12:41                               ` Daniel Vetter
2020-07-22 12:41                               ` [Intel-gfx] " Daniel Vetter
2020-07-22 12:41                               ` Daniel Vetter
2020-07-22 13:12                               ` Thomas Hellström (Intel)
2020-07-22 13:12                                 ` Thomas Hellström (Intel)
2020-07-22 13:12                                 ` [Intel-gfx] " Thomas Hellström (Intel)
2020-07-22 13:12                                 ` Thomas Hellström (Intel)
2020-07-22 14:07                                 ` Daniel Vetter
2020-07-22 14:07                                   ` Daniel Vetter
2020-07-22 14:07                                   ` [Intel-gfx] " Daniel Vetter
2020-07-22 14:07                                   ` Daniel Vetter
2020-07-22 14:23                                   ` Christian König
2020-07-22 14:23                                     ` Christian König
2020-07-22 14:23                                     ` [Intel-gfx] " Christian König
2020-07-22 14:23                                     ` Christian König
2020-07-22 14:30                                     ` Thomas Hellström (Intel)
2020-07-22 14:30                                       ` Thomas Hellström (Intel)
2020-07-22 14:30                                       ` [Intel-gfx] " Thomas Hellström (Intel)
2020-07-22 14:30                                       ` Thomas Hellström (Intel)
2020-07-22 14:35                                       ` Christian König
2020-07-22 14:35                                         ` Christian König
2020-07-22 14:35                                         ` [Intel-gfx] " Christian König
2020-07-22 14:35                                         ` Christian König
2020-07-07 20:12 ` [PATCH 04/25] drm/vkms: Annotate vblank timer Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-12 22:27   ` Rodrigo Siqueira
2020-07-12 22:27     ` Rodrigo Siqueira
2020-07-12 22:27     ` [Intel-gfx] " Rodrigo Siqueira
2020-07-12 22:27     ` Rodrigo Siqueira
2020-07-14  9:57     ` Melissa Wen
2020-07-14  9:57       ` Melissa Wen
2020-07-14  9:57       ` [Intel-gfx] " Melissa Wen
2020-07-14  9:57       ` Melissa Wen
2020-07-14  9:59       ` Daniel Vetter
2020-07-14  9:59         ` Daniel Vetter
2020-07-14  9:59         ` [Intel-gfx] " Daniel Vetter
2020-07-14  9:59         ` Daniel Vetter
2020-07-14 14:55         ` Melissa Wen
2020-07-14 14:55           ` Melissa Wen
2020-07-14 14:55           ` [Intel-gfx] " Melissa Wen
2020-07-14 14:55           ` Melissa Wen
2020-07-14 15:23           ` Daniel Vetter
2020-07-14 15:23             ` Daniel Vetter
2020-07-14 15:23             ` [Intel-gfx] " Daniel Vetter
2020-07-14 15:23             ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 05/25] drm/vblank: Annotate with dma-fence signalling section Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 06/25] drm/amdgpu: add dma-fence annotations to atomic commit path Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 07/25] drm/komdea: Annotate dma-fence critical section in " Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-08  5:17   ` james qian wang (Arm Technology China)
2020-07-08  5:17     ` [Intel-gfx] " james qian wang (Arm Technology China)
2020-07-08  5:17     ` james qian wang (Arm Technology China)
2020-07-14  8:34     ` Daniel Vetter
2020-07-14  8:34       ` [Intel-gfx] " Daniel Vetter
2020-07-14  8:34       ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 08/25] drm/malidp: " Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-15 12:53   ` Liviu Dudau
2020-07-15 12:53     ` [Intel-gfx] " Liviu Dudau
2020-07-15 12:53     ` Liviu Dudau
2020-07-15 13:51     ` Daniel Vetter
2020-07-15 13:51       ` [Intel-gfx] " Daniel Vetter
2020-07-15 13:51       ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 09/25] drm/atmel: Use drm_atomic_helper_commit Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:37   ` Sam Ravnborg
2020-07-07 20:37     ` [Intel-gfx] " Sam Ravnborg
2020-07-07 20:37     ` Sam Ravnborg
2020-07-07 20:37     ` Sam Ravnborg
2020-07-07 21:31   ` [PATCH] " Daniel Vetter
2020-07-07 21:31     ` [Intel-gfx] " Daniel Vetter
2020-07-07 21:31     ` Daniel Vetter
2020-07-07 21:31     ` Daniel Vetter
2020-07-14  9:55     ` Sam Ravnborg
2020-07-14  9:55       ` [Intel-gfx] " Sam Ravnborg
2020-07-14  9:55       ` Sam Ravnborg
2020-07-14  9:55       ` Sam Ravnborg
2020-07-07 20:12 ` [PATCH 10/25] drm/imx: Annotate dma-fence critical section in commit path Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 11/25] drm/omapdrm: " Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 12/25] drm/rcar-du: " Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 23:32   ` Laurent Pinchart
2020-07-07 23:32     ` [Intel-gfx] " Laurent Pinchart
2020-07-07 23:32     ` Laurent Pinchart
2020-07-14  8:39     ` Daniel Vetter
2020-07-14  8:39       ` [Intel-gfx] " Daniel Vetter
2020-07-14  8:39       ` Daniel Vetter
     [not found] ` <20200707201229.472834-1-daniel.vetter-/w4YWyX8dFk@public.gmane.org>
2020-07-07 20:12   ` [PATCH 13/25] drm/tegra: " Daniel Vetter
2020-07-07 20:12     ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12     ` Daniel Vetter
2020-07-07 20:12     ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 14/25] drm/tidss: " Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-08  9:01   ` Jyri Sarha
2020-07-08  9:01     ` [Intel-gfx] " Jyri Sarha
2020-07-08  9:01     ` Jyri Sarha
2020-07-07 20:12 ` [PATCH 15/25] drm/tilcdc: Use standard drm_atomic_helper_commit Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-08  9:17   ` Jyri Sarha
2020-07-08  9:17     ` [Intel-gfx] " Jyri Sarha
2020-07-08  9:17     ` Jyri Sarha
2020-07-08  9:27     ` Daniel Vetter
2020-07-08  9:27       ` [Intel-gfx] " Daniel Vetter
2020-07-08  9:27       ` Daniel Vetter
2020-07-08  9:44   ` [PATCH] " Daniel Vetter
2020-07-08  9:44     ` [Intel-gfx] " Daniel Vetter
2020-07-08  9:44     ` Daniel Vetter
2020-07-08 10:21     ` Jyri Sarha
2020-07-08 10:21       ` [Intel-gfx] " Jyri Sarha
2020-07-08 10:21       ` Jyri Sarha
2020-07-08 14:20   ` Daniel Vetter
2020-07-08 14:20     ` [Intel-gfx] " Daniel Vetter
2020-07-08 14:20     ` Daniel Vetter
2020-07-10 11:16     ` Jyri Sarha
2020-07-10 11:16       ` [Intel-gfx] " Jyri Sarha
2020-07-10 11:16       ` Jyri Sarha
2020-07-14  8:32       ` Daniel Vetter
2020-07-14  8:32         ` [Intel-gfx] " Daniel Vetter
2020-07-14  8:32         ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 16/25] drm/atomic-helper: Add dma-fence annotations Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 17/25] drm/scheduler: use dma-fence annotations in main thread Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 18/25] drm/amdgpu: use dma-fence annotations in cs_submit() Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 19/25] drm/amdgpu: s/GFP_KERNEL/GFP_ATOMIC in scheduler code Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-14 10:49   ` Daniel Vetter
2020-07-14 10:49     ` Daniel Vetter
2020-07-14 10:49     ` [Intel-gfx] " Daniel Vetter
2020-07-14 10:49     ` Daniel Vetter
2020-07-14 11:40     ` Christian König
2020-07-14 11:40       ` Christian König
2020-07-14 11:40       ` [Intel-gfx] " Christian König
2020-07-14 11:40       ` Christian König
2020-07-14 14:31       ` Daniel Vetter
2020-07-14 14:31         ` Daniel Vetter
2020-07-14 14:31         ` [Intel-gfx] " Daniel Vetter
2020-07-14 14:31         ` Daniel Vetter
2020-07-15  9:17         ` Christian König
2020-07-15  9:17           ` Christian König
2020-07-15  9:17           ` [Intel-gfx] " Christian König
2020-07-15  9:17           ` Christian König
2020-07-15 11:53           ` Daniel Vetter
2020-07-15 11:53             ` Daniel Vetter
2020-07-15 11:53             ` [Intel-gfx] " Daniel Vetter
2020-07-15 11:53             ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 20/25] drm/amdgpu: DC also loves to allocate stuff where it shouldn't Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-14 11:12   ` Daniel Vetter
2020-07-14 11:12     ` Daniel Vetter
2020-07-14 11:12     ` [Intel-gfx] " Daniel Vetter
2020-07-14 11:12     ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 21/25] drm/amdgpu/dc: Stop dma_resv_lock inversion in commit_tail Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 22/25] drm/scheduler: use dma-fence annotations in tdr work Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 23/25] drm/amdgpu: use dma-fence annotations for gpu reset code Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 24/25] Revert "drm/amdgpu: add fbdev suspend/resume on gpu reset" Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 25/25] drm/amdgpu: gpu recovery does full modesets Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 22:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for dma-fence annotations, round 3 (rev2) Patchwork
2020-07-07 22:12 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-07-07 22:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-08  0:59 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-07-08 11:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for dma-fence annotations, round 3 (rev3) Patchwork
2020-07-08 11:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-07-08 11:37 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-07-08 14:53 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for dma-fence annotations, round 3 (rev4) Patchwork
2020-07-08 14:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-07-08 15:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-08 18:46 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-07-09 13:05 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for dma-fence annotations, round 3 (rev6) Patchwork
2020-07-09 13:06 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-07-09 13:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-09 15:38 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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