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From: "Christian König" <christian.koenig@amd.com>
To: "Thomas Hellström (Intel)" <thomas_os@shipmail.org>,
	"Daniel Vetter" <daniel.vetter@ffwll.ch>
Cc: Felix Kuehling <Felix.Kuehling@amd.com>,
	Daniel Stone <daniels@collabora.com>,
	linux-rdma <linux-rdma@vger.kernel.org>,
	Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	DRI Development <dri-devel@lists.freedesktop.org>,
	"moderated list:DMA BUFFER SHARING FRAMEWORK" 
	<linaro-mm-sig@lists.linaro.org>,
	Steve Pronovost <spronovo@microsoft.com>,
	amd-gfx mailing list <amd-gfx@lists.freedesktop.org>,
	Jason Ekstrand <jason@jlekstrand.net>,
	Jesse Natalie <jenatali@microsoft.com>,
	Daniel Vetter <daniel.vetter@intel.com>,
	Thomas Hellstrom <thomas.hellstrom@intel.com>,
	Linux Media Mailing List <linux-media@vger.kernel.org>,
	Dave Airlie <airlied@gmail.com>,
	Mika Kuoppala <mika.kuoppala@intel.com>
Subject: Re: [Linaro-mm-sig] [PATCH 1/2] dma-buf.rst: Document why indefinite fences are a bad idea
Date: Wed, 22 Jul 2020 16:35:44 +0200	[thread overview]
Message-ID: <e3112430-9533-ef75-cbd8-31814893210c@amd.com> (raw)
In-Reply-To: <a046ea93-b303-17d4-add4-efd0a709cfd2@shipmail.org>

Am 22.07.20 um 16:30 schrieb Thomas Hellström (Intel):
>
> On 2020-07-22 16:23, Christian König wrote:
>> Am 22.07.20 um 16:07 schrieb Daniel Vetter:
>>> On Wed, Jul 22, 2020 at 3:12 PM Thomas Hellström (Intel)
>>> <thomas_os@shipmail.org> wrote:
>>>> On 2020-07-22 14:41, Daniel Vetter wrote:
>>>>> I'm pretty sure there's more bugs, I just haven't heard from them 
>>>>> yet.
>>>>> Also due to the opt-in nature of dma-fence we can limit the scope of
>>>>> what we fix fairly naturally, just don't put them where no one cares
>>>>> :-) Of course that also hides general locking issues in dma_fence
>>>>> signalling code, but well *shrug*.
>>>> Hmm, yes. Another potential big problem would be drivers that want to
>>>> use gpu page faults in the dma-fence critical sections with the
>>>> batch-based programming model.
>>> Yeah that's a massive can of worms. But luckily there's no such driver
>>> merged in upstream, so hopefully we can think about all the
>>> constraints and how to best annotate&enforce this before we land any
>>> code and have big regrets.
>>
>> Do you want a bad news? I once made a prototype for that when Vega10 
>> came out.
>>
>> But we abandoned this approach for the the batch based approach 
>> because of the horrible performance.
>
> In context of the previous discussion I'd consider the fact that it's 
> not performant in the batch-based model good news :)

Well the Vega10 had such a horrible page fault performance because it 
was the first generation which enabled it.

Later hardware versions are much better, but we just didn't push for 
this feature on them any more.

But yeah, now you mentioned it we did discuss this locking problem on 
tons of team calls as well.

Our solution at that time was to just not allow waiting if we do any 
allocation in the page fault handler. But this is of course not 
practical for a production environment.

Christian.

>
> Thomas
>
>
>>
>> KFD is going to see that, but this is only with user queues and no 
>> dma_fence involved whatsoever.
>>
>> Christian.
>>
>>> -Daniel
>>>
>>>
>>>
>>> -- 
>>> Daniel Vetter
>>> Software Engineer, Intel Corporation
>>> https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fblog.ffwll.ch%2F&amp;data=02%7C01%7Cchristian.koenig%40amd.com%7C65836d463c6a43425a0b08d82e4bc09e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637310250203344946&amp;sdata=F8LZEnsMOJLeC3Sr%2BPn2HjGHlttdkVUiOzW7mYeijys%3D&amp;reserved=0 
>>>
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7Cchristian.koenig%40amd.com%7C65836d463c6a43425a0b08d82e4bc09e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637310250203344946&amp;sdata=V3FsfahK6344%2FXujtLA%2BazWV0XjKWDXFWObRWc1JUKs%3D&amp;reserved=0 
>>>


WARNING: multiple messages have this Message-ID (diff)
From: "Christian König" <christian.koenig@amd.com>
To: "Thomas Hellström (Intel)" <thomas_os@shipmail.org>,
	"Daniel Vetter" <daniel.vetter@ffwll.ch>
Cc: Daniel Stone <daniels@collabora.com>,
	linux-rdma <linux-rdma@vger.kernel.org>,
	Felix Kuehling <Felix.Kuehling@amd.com>,
	DRI Development <dri-devel@lists.freedesktop.org>,
	"moderated list:DMA BUFFER SHARING FRAMEWORK"
	<linaro-mm-sig@lists.linaro.org>,
	Steve Pronovost <spronovo@microsoft.com>,
	amd-gfx mailing list <amd-gfx@lists.freedesktop.org>,
	Jason Ekstrand <jason@jlekstrand.net>,
	Jesse Natalie <jenatali@microsoft.com>,
	Daniel Vetter <daniel.vetter@intel.com>,
	Thomas Hellstrom <thomas.hellstrom@intel.com>,
	Mika Kuoppala <mika.kuoppala@intel.com>,
	Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
	Linux Media Mailing List <linux-media@vger.kernel.org>
Subject: Re: [Linaro-mm-sig] [PATCH 1/2] dma-buf.rst: Document why indefinite fences are a bad idea
Date: Wed, 22 Jul 2020 16:35:44 +0200	[thread overview]
Message-ID: <e3112430-9533-ef75-cbd8-31814893210c@amd.com> (raw)
In-Reply-To: <a046ea93-b303-17d4-add4-efd0a709cfd2@shipmail.org>

Am 22.07.20 um 16:30 schrieb Thomas Hellström (Intel):
>
> On 2020-07-22 16:23, Christian König wrote:
>> Am 22.07.20 um 16:07 schrieb Daniel Vetter:
>>> On Wed, Jul 22, 2020 at 3:12 PM Thomas Hellström (Intel)
>>> <thomas_os@shipmail.org> wrote:
>>>> On 2020-07-22 14:41, Daniel Vetter wrote:
>>>>> I'm pretty sure there's more bugs, I just haven't heard from them 
>>>>> yet.
>>>>> Also due to the opt-in nature of dma-fence we can limit the scope of
>>>>> what we fix fairly naturally, just don't put them where no one cares
>>>>> :-) Of course that also hides general locking issues in dma_fence
>>>>> signalling code, but well *shrug*.
>>>> Hmm, yes. Another potential big problem would be drivers that want to
>>>> use gpu page faults in the dma-fence critical sections with the
>>>> batch-based programming model.
>>> Yeah that's a massive can of worms. But luckily there's no such driver
>>> merged in upstream, so hopefully we can think about all the
>>> constraints and how to best annotate&enforce this before we land any
>>> code and have big regrets.
>>
>> Do you want a bad news? I once made a prototype for that when Vega10 
>> came out.
>>
>> But we abandoned this approach for the the batch based approach 
>> because of the horrible performance.
>
> In context of the previous discussion I'd consider the fact that it's 
> not performant in the batch-based model good news :)

Well the Vega10 had such a horrible page fault performance because it 
was the first generation which enabled it.

Later hardware versions are much better, but we just didn't push for 
this feature on them any more.

But yeah, now you mentioned it we did discuss this locking problem on 
tons of team calls as well.

Our solution at that time was to just not allow waiting if we do any 
allocation in the page fault handler. But this is of course not 
practical for a production environment.

Christian.

>
> Thomas
>
>
>>
>> KFD is going to see that, but this is only with user queues and no 
>> dma_fence involved whatsoever.
>>
>> Christian.
>>
>>> -Daniel
>>>
>>>
>>>
>>> -- 
>>> Daniel Vetter
>>> Software Engineer, Intel Corporation
>>> https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fblog.ffwll.ch%2F&amp;data=02%7C01%7Cchristian.koenig%40amd.com%7C65836d463c6a43425a0b08d82e4bc09e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637310250203344946&amp;sdata=F8LZEnsMOJLeC3Sr%2BPn2HjGHlttdkVUiOzW7mYeijys%3D&amp;reserved=0 
>>>
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7Cchristian.koenig%40amd.com%7C65836d463c6a43425a0b08d82e4bc09e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637310250203344946&amp;sdata=V3FsfahK6344%2FXujtLA%2BazWV0XjKWDXFWObRWc1JUKs%3D&amp;reserved=0 
>>>

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

WARNING: multiple messages have this Message-ID (diff)
From: "Christian König" <christian.koenig@amd.com>
To: "Thomas Hellström (Intel)" <thomas_os@shipmail.org>,
	"Daniel Vetter" <daniel.vetter@ffwll.ch>
Cc: Daniel Stone <daniels@collabora.com>,
	linux-rdma <linux-rdma@vger.kernel.org>,
	Felix Kuehling <Felix.Kuehling@amd.com>,
	DRI Development <dri-devel@lists.freedesktop.org>,
	"moderated list:DMA BUFFER SHARING FRAMEWORK"
	<linaro-mm-sig@lists.linaro.org>,
	Steve Pronovost <spronovo@microsoft.com>,
	amd-gfx mailing list <amd-gfx@lists.freedesktop.org>,
	Jesse Natalie <jenatali@microsoft.com>,
	Daniel Vetter <daniel.vetter@intel.com>,
	Thomas Hellstrom <thomas.hellstrom@intel.com>,
	Mika Kuoppala <mika.kuoppala@intel.com>,
	Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
	Linux Media Mailing List <linux-media@vger.kernel.org>
Subject: Re: [Intel-gfx] [Linaro-mm-sig] [PATCH 1/2] dma-buf.rst: Document why indefinite fences are a bad idea
Date: Wed, 22 Jul 2020 16:35:44 +0200	[thread overview]
Message-ID: <e3112430-9533-ef75-cbd8-31814893210c@amd.com> (raw)
In-Reply-To: <a046ea93-b303-17d4-add4-efd0a709cfd2@shipmail.org>

Am 22.07.20 um 16:30 schrieb Thomas Hellström (Intel):
>
> On 2020-07-22 16:23, Christian König wrote:
>> Am 22.07.20 um 16:07 schrieb Daniel Vetter:
>>> On Wed, Jul 22, 2020 at 3:12 PM Thomas Hellström (Intel)
>>> <thomas_os@shipmail.org> wrote:
>>>> On 2020-07-22 14:41, Daniel Vetter wrote:
>>>>> I'm pretty sure there's more bugs, I just haven't heard from them 
>>>>> yet.
>>>>> Also due to the opt-in nature of dma-fence we can limit the scope of
>>>>> what we fix fairly naturally, just don't put them where no one cares
>>>>> :-) Of course that also hides general locking issues in dma_fence
>>>>> signalling code, but well *shrug*.
>>>> Hmm, yes. Another potential big problem would be drivers that want to
>>>> use gpu page faults in the dma-fence critical sections with the
>>>> batch-based programming model.
>>> Yeah that's a massive can of worms. But luckily there's no such driver
>>> merged in upstream, so hopefully we can think about all the
>>> constraints and how to best annotate&enforce this before we land any
>>> code and have big regrets.
>>
>> Do you want a bad news? I once made a prototype for that when Vega10 
>> came out.
>>
>> But we abandoned this approach for the the batch based approach 
>> because of the horrible performance.
>
> In context of the previous discussion I'd consider the fact that it's 
> not performant in the batch-based model good news :)

Well the Vega10 had such a horrible page fault performance because it 
was the first generation which enabled it.

Later hardware versions are much better, but we just didn't push for 
this feature on them any more.

But yeah, now you mentioned it we did discuss this locking problem on 
tons of team calls as well.

Our solution at that time was to just not allow waiting if we do any 
allocation in the page fault handler. But this is of course not 
practical for a production environment.

Christian.

>
> Thomas
>
>
>>
>> KFD is going to see that, but this is only with user queues and no 
>> dma_fence involved whatsoever.
>>
>> Christian.
>>
>>> -Daniel
>>>
>>>
>>>
>>> -- 
>>> Daniel Vetter
>>> Software Engineer, Intel Corporation
>>> https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fblog.ffwll.ch%2F&amp;data=02%7C01%7Cchristian.koenig%40amd.com%7C65836d463c6a43425a0b08d82e4bc09e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637310250203344946&amp;sdata=F8LZEnsMOJLeC3Sr%2BPn2HjGHlttdkVUiOzW7mYeijys%3D&amp;reserved=0 
>>>
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7Cchristian.koenig%40amd.com%7C65836d463c6a43425a0b08d82e4bc09e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637310250203344946&amp;sdata=V3FsfahK6344%2FXujtLA%2BazWV0XjKWDXFWObRWc1JUKs%3D&amp;reserved=0 
>>>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: "Christian König" <christian.koenig@amd.com>
To: "Thomas Hellström (Intel)" <thomas_os@shipmail.org>,
	"Daniel Vetter" <daniel.vetter@ffwll.ch>
Cc: Daniel Stone <daniels@collabora.com>,
	linux-rdma <linux-rdma@vger.kernel.org>,
	Felix Kuehling <Felix.Kuehling@amd.com>,
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	DRI Development <dri-devel@lists.freedesktop.org>,
	"moderated list:DMA BUFFER SHARING FRAMEWORK"
	<linaro-mm-sig@lists.linaro.org>,
	Steve Pronovost <spronovo@microsoft.com>,
	amd-gfx mailing list <amd-gfx@lists.freedesktop.org>,
	Jason Ekstrand <jason@jlekstrand.net>,
	Jesse Natalie <jenatali@microsoft.com>,
	Daniel Vetter <daniel.vetter@intel.com>,
	Thomas Hellstrom <thomas.hellstrom@intel.com>,
	Mika Kuoppala <mika.kuoppala@intel.com>,
	Dave Airlie <airlied@gmail.com>,
	Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
	Linux Media Mailing List <linux-media@vger.kernel.org>
Subject: Re: [Linaro-mm-sig] [PATCH 1/2] dma-buf.rst: Document why indefinite fences are a bad idea
Date: Wed, 22 Jul 2020 16:35:44 +0200	[thread overview]
Message-ID: <e3112430-9533-ef75-cbd8-31814893210c@amd.com> (raw)
In-Reply-To: <a046ea93-b303-17d4-add4-efd0a709cfd2@shipmail.org>

Am 22.07.20 um 16:30 schrieb Thomas Hellström (Intel):
>
> On 2020-07-22 16:23, Christian König wrote:
>> Am 22.07.20 um 16:07 schrieb Daniel Vetter:
>>> On Wed, Jul 22, 2020 at 3:12 PM Thomas Hellström (Intel)
>>> <thomas_os@shipmail.org> wrote:
>>>> On 2020-07-22 14:41, Daniel Vetter wrote:
>>>>> I'm pretty sure there's more bugs, I just haven't heard from them 
>>>>> yet.
>>>>> Also due to the opt-in nature of dma-fence we can limit the scope of
>>>>> what we fix fairly naturally, just don't put them where no one cares
>>>>> :-) Of course that also hides general locking issues in dma_fence
>>>>> signalling code, but well *shrug*.
>>>> Hmm, yes. Another potential big problem would be drivers that want to
>>>> use gpu page faults in the dma-fence critical sections with the
>>>> batch-based programming model.
>>> Yeah that's a massive can of worms. But luckily there's no such driver
>>> merged in upstream, so hopefully we can think about all the
>>> constraints and how to best annotate&enforce this before we land any
>>> code and have big regrets.
>>
>> Do you want a bad news? I once made a prototype for that when Vega10 
>> came out.
>>
>> But we abandoned this approach for the the batch based approach 
>> because of the horrible performance.
>
> In context of the previous discussion I'd consider the fact that it's 
> not performant in the batch-based model good news :)

Well the Vega10 had such a horrible page fault performance because it 
was the first generation which enabled it.

Later hardware versions are much better, but we just didn't push for 
this feature on them any more.

But yeah, now you mentioned it we did discuss this locking problem on 
tons of team calls as well.

Our solution at that time was to just not allow waiting if we do any 
allocation in the page fault handler. But this is of course not 
practical for a production environment.

Christian.

>
> Thomas
>
>
>>
>> KFD is going to see that, but this is only with user queues and no 
>> dma_fence involved whatsoever.
>>
>> Christian.
>>
>>> -Daniel
>>>
>>>
>>>
>>> -- 
>>> Daniel Vetter
>>> Software Engineer, Intel Corporation
>>> https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fblog.ffwll.ch%2F&amp;data=02%7C01%7Cchristian.koenig%40amd.com%7C65836d463c6a43425a0b08d82e4bc09e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637310250203344946&amp;sdata=F8LZEnsMOJLeC3Sr%2BPn2HjGHlttdkVUiOzW7mYeijys%3D&amp;reserved=0 
>>>
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7Cchristian.koenig%40amd.com%7C65836d463c6a43425a0b08d82e4bc09e%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637310250203344946&amp;sdata=V3FsfahK6344%2FXujtLA%2BazWV0XjKWDXFWObRWc1JUKs%3D&amp;reserved=0 
>>>

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

  reply	other threads:[~2020-07-22 14:35 UTC|newest]

Thread overview: 467+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-07 20:12 [PATCH 00/25] dma-fence annotations, round 3 Daniel Vetter
2020-07-07 20:12 ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12 ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 01/25] dma-fence: basic lockdep annotations Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-08 14:57   ` Christian König
2020-07-08 14:57     ` Christian König
2020-07-08 14:57     ` [Intel-gfx] " Christian König
2020-07-08 14:57     ` Christian König
2020-07-08 15:12     ` Daniel Vetter
2020-07-08 15:12       ` Daniel Vetter
2020-07-08 15:12       ` [Intel-gfx] " Daniel Vetter
2020-07-08 15:12       ` Daniel Vetter
2020-07-08 15:19       ` Alex Deucher
2020-07-08 15:19         ` Alex Deucher
2020-07-08 15:19         ` [Intel-gfx] " Alex Deucher
2020-07-08 15:19         ` Alex Deucher
2020-07-08 15:37         ` Daniel Vetter
2020-07-08 15:37           ` Daniel Vetter
2020-07-08 15:37           ` [Intel-gfx] " Daniel Vetter
2020-07-08 15:37           ` Daniel Vetter
2020-07-14 11:09           ` Daniel Vetter
2020-07-14 11:09             ` Daniel Vetter
2020-07-14 11:09             ` [Intel-gfx] " Daniel Vetter
2020-07-14 11:09             ` Daniel Vetter
2020-07-09  7:32       ` [Intel-gfx] " Daniel Stone
2020-07-09  7:32         ` Daniel Stone
2020-07-09  7:32         ` Daniel Stone
2020-07-09  7:32         ` Daniel Stone
2020-07-09  7:52         ` Daniel Vetter
2020-07-09  7:52           ` Daniel Vetter
2020-07-09  7:52           ` Daniel Vetter
2020-07-09  7:52           ` Daniel Vetter
2020-07-13 16:26     ` Daniel Vetter
2020-07-13 16:26       ` Daniel Vetter
2020-07-13 16:26       ` [Intel-gfx] " Daniel Vetter
2020-07-13 16:26       ` Daniel Vetter
2020-07-13 16:39       ` Christian König
2020-07-13 16:39         ` Christian König
2020-07-13 16:39         ` [Intel-gfx] " Christian König
2020-07-13 16:39         ` Christian König
2020-07-13 20:31         ` Dave Airlie
2020-07-13 20:31           ` Dave Airlie
2020-07-13 20:31           ` [Intel-gfx] " Dave Airlie
2020-07-13 20:31           ` Dave Airlie
2020-07-07 20:12 ` [PATCH 02/25] dma-fence: prime " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-09  8:09   ` Daniel Vetter
2020-07-09  8:09     ` Daniel Vetter
2020-07-09  8:09     ` [Intel-gfx] " Daniel Vetter
2020-07-09  8:09     ` Daniel Vetter
2020-07-10 12:43     ` Jason Gunthorpe
2020-07-10 12:43       ` Jason Gunthorpe
2020-07-10 12:43       ` [Intel-gfx] " Jason Gunthorpe
2020-07-10 12:43       ` Jason Gunthorpe
2020-07-10 12:48       ` Christian König
2020-07-10 12:48         ` Christian König
2020-07-10 12:48         ` [Intel-gfx] " Christian König
2020-07-10 12:48         ` Christian König
2020-07-10 12:54         ` Jason Gunthorpe
2020-07-10 12:54           ` Jason Gunthorpe
2020-07-10 12:54           ` [Intel-gfx] " Jason Gunthorpe
2020-07-10 12:54           ` Jason Gunthorpe
2020-07-10 13:01           ` Christian König
2020-07-10 13:01             ` Christian König
2020-07-10 13:01             ` [Intel-gfx] " Christian König
2020-07-10 13:01             ` Christian König
2020-07-10 13:48             ` Jason Gunthorpe
2020-07-10 13:48               ` Jason Gunthorpe
2020-07-10 13:48               ` [Intel-gfx] " Jason Gunthorpe
2020-07-10 13:48               ` Jason Gunthorpe
2020-07-10 14:02               ` Daniel Vetter
2020-07-10 14:02                 ` Daniel Vetter
2020-07-10 14:02                 ` [Intel-gfx] " Daniel Vetter
2020-07-10 14:02                 ` Daniel Vetter
2020-07-10 14:23                 ` Jason Gunthorpe
2020-07-10 14:23                   ` Jason Gunthorpe
2020-07-10 14:23                   ` [Intel-gfx] " Jason Gunthorpe
2020-07-10 14:23                   ` Jason Gunthorpe
2020-07-10 20:02                   ` Daniel Vetter
2020-07-10 20:02                     ` Daniel Vetter
2020-07-10 20:02                     ` [Intel-gfx] " Daniel Vetter
2020-07-10 20:02                     ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 03/25] dma-buf.rst: Document why idenfinite fences are a bad idea Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-09  7:36   ` [Intel-gfx] " Daniel Stone
2020-07-09  7:36     ` Daniel Stone
2020-07-09  7:36     ` Daniel Stone
2020-07-09  7:36     ` Daniel Stone
2020-07-09  8:04     ` Daniel Vetter
2020-07-09  8:04       ` Daniel Vetter
2020-07-09  8:04       ` Daniel Vetter
2020-07-09  8:04       ` Daniel Vetter
2020-07-09 12:11       ` Daniel Stone
2020-07-09 12:11         ` Daniel Stone
2020-07-09 12:11         ` Daniel Stone
2020-07-09 12:11         ` Daniel Stone
2020-07-09 12:31         ` Daniel Vetter
2020-07-09 12:31           ` Daniel Vetter
2020-07-09 12:31           ` Daniel Vetter
2020-07-09 12:31           ` Daniel Vetter
2020-07-09 14:28           ` Christian König
2020-07-09 14:28             ` Christian König
2020-07-09 14:28             ` Christian König
2020-07-09 14:28             ` Christian König
2020-07-09 11:53   ` Christian König
2020-07-09 11:53     ` Christian König
2020-07-09 11:53     ` [Intel-gfx] " Christian König
2020-07-09 11:53     ` Christian König
2020-07-09 12:33   ` [PATCH 1/2] dma-buf.rst: Document why indefinite " Daniel Vetter
2020-07-09 12:33     ` Daniel Vetter
2020-07-09 12:33     ` [Intel-gfx] " Daniel Vetter
2020-07-09 12:33     ` Daniel Vetter
2020-07-09 12:33     ` [PATCH 2/2] drm/virtio: Remove open-coded commit-tail function Daniel Vetter
2020-07-09 12:33       ` [Intel-gfx] " Daniel Vetter
2020-07-09 12:33       ` Daniel Vetter
2020-07-09 12:33       ` Daniel Vetter
2020-07-09 12:48       ` Gerd Hoffmann
2020-07-09 12:48         ` [Intel-gfx] " Gerd Hoffmann
2020-07-09 12:48         ` Gerd Hoffmann
2020-07-09 12:48         ` Gerd Hoffmann
2020-07-09 14:05       ` Sam Ravnborg
2020-07-09 14:05         ` [Intel-gfx] " Sam Ravnborg
2020-07-09 14:05         ` Sam Ravnborg
2020-07-09 14:05         ` Sam Ravnborg
2020-07-14  9:13         ` Daniel Vetter
2020-07-14  9:13           ` [Intel-gfx] " Daniel Vetter
2020-07-14  9:13           ` Daniel Vetter
2020-07-14  9:13           ` Daniel Vetter
2020-08-19 12:43       ` Jiri Slaby
2020-08-19 12:43         ` [Intel-gfx] " Jiri Slaby
2020-08-19 12:43         ` Jiri Slaby
2020-08-19 12:47         ` Jiri Slaby
2020-08-19 12:47           ` [Intel-gfx] " Jiri Slaby
2020-08-19 12:47           ` Jiri Slaby
2020-08-19 13:24         ` Gerd Hoffmann
2020-08-19 13:24           ` [Intel-gfx] " Gerd Hoffmann
2020-08-19 13:24           ` Gerd Hoffmann
2020-08-19 13:24           ` Gerd Hoffmann
2020-08-20  6:32           ` Jiri Slaby
2020-08-20  6:32             ` [Intel-gfx] " Jiri Slaby
2020-08-20  6:32             ` Jiri Slaby
2020-08-21  7:01             ` Gerd Hoffmann
2020-08-21  7:01               ` [Intel-gfx] " Gerd Hoffmann
2020-08-21  7:01               ` Gerd Hoffmann
2020-08-21  7:01               ` Gerd Hoffmann
2020-07-10 12:30     ` [PATCH 1/2] dma-buf.rst: Document why indefinite fences are a bad idea Maarten Lankhorst
2020-07-10 12:30       ` Maarten Lankhorst
2020-07-10 12:30       ` [Intel-gfx] " Maarten Lankhorst
2020-07-10 12:30       ` Maarten Lankhorst
2020-07-14 17:46     ` Jason Ekstrand
2020-07-14 17:46       ` Jason Ekstrand
2020-07-14 17:46       ` [Intel-gfx] " Jason Ekstrand
2020-07-14 17:46       ` Jason Ekstrand
2020-07-20 11:15     ` [Linaro-mm-sig] " Thomas Hellström (Intel)
2020-07-20 11:15       ` Thomas Hellström (Intel)
2020-07-20 11:15       ` [Intel-gfx] " Thomas Hellström (Intel)
2020-07-20 11:15       ` Thomas Hellström (Intel)
2020-07-21  7:41       ` Daniel Vetter
2020-07-21  7:41         ` Daniel Vetter
2020-07-21  7:41         ` [Intel-gfx] " Daniel Vetter
2020-07-21  7:41         ` Daniel Vetter
2020-07-21  7:45         ` Christian König
2020-07-21  7:45           ` Christian König
2020-07-21  7:45           ` [Intel-gfx] " Christian König
2020-07-21  7:45           ` Christian König
2020-07-21  8:47           ` Thomas Hellström (Intel)
2020-07-21  8:47             ` Thomas Hellström (Intel)
2020-07-21  8:47             ` [Intel-gfx] " Thomas Hellström (Intel)
2020-07-21  8:47             ` Thomas Hellström (Intel)
2020-07-21  8:55             ` Christian König
2020-07-21  8:55               ` Christian König
2020-07-21  8:55               ` [Intel-gfx] " Christian König
2020-07-21  8:55               ` Christian König
2020-07-21  9:16               ` Daniel Vetter
2020-07-21  9:16                 ` Daniel Vetter
2020-07-21  9:16                 ` [Intel-gfx] " Daniel Vetter
2020-07-21  9:16                 ` Daniel Vetter
2020-07-21  9:24                 ` Daniel Vetter
2020-07-21  9:24                   ` Daniel Vetter
2020-07-21  9:24                   ` [Intel-gfx] " Daniel Vetter
2020-07-21  9:24                   ` Daniel Vetter
2020-07-21  9:37               ` Thomas Hellström (Intel)
2020-07-21  9:37                 ` Thomas Hellström (Intel)
2020-07-21  9:37                 ` [Intel-gfx] " Thomas Hellström (Intel)
2020-07-21  9:37                 ` Thomas Hellström (Intel)
2020-07-21  9:50                 ` Daniel Vetter
2020-07-21  9:50                   ` Daniel Vetter
2020-07-21  9:50                   ` [Intel-gfx] " Daniel Vetter
2020-07-21  9:50                   ` Daniel Vetter
2020-07-21 10:47                   ` Thomas Hellström (Intel)
2020-07-21 10:47                     ` Thomas Hellström (Intel)
2020-07-21 10:47                     ` [Intel-gfx] " Thomas Hellström (Intel)
2020-07-21 10:47                     ` Thomas Hellström (Intel)
2020-07-21 13:59                     ` Christian König
2020-07-21 13:59                       ` Christian König
2020-07-21 13:59                       ` [Intel-gfx] " Christian König
2020-07-21 13:59                       ` Christian König
2020-07-21 17:46                       ` Thomas Hellström (Intel)
2020-07-21 17:46                         ` Thomas Hellström (Intel)
2020-07-21 17:46                         ` [Intel-gfx] " Thomas Hellström (Intel)
2020-07-21 17:46                         ` Thomas Hellström (Intel)
2020-07-21 18:18                         ` Daniel Vetter
2020-07-21 18:18                           ` Daniel Vetter
2020-07-21 18:18                           ` [Intel-gfx] " Daniel Vetter
2020-07-21 18:18                           ` Daniel Vetter
2020-07-21 21:42                       ` Dave Airlie
2020-07-21 21:42                         ` Dave Airlie
2020-07-21 21:42                         ` [Intel-gfx] " Dave Airlie
2020-07-21 21:42                         ` Dave Airlie
2020-07-21 22:45             ` Dave Airlie
2020-07-21 22:45               ` Dave Airlie
2020-07-21 22:45               ` [Intel-gfx] " Dave Airlie
2020-07-21 22:45               ` Dave Airlie
2020-07-22  6:45               ` Thomas Hellström (Intel)
2020-07-22  6:45                 ` Thomas Hellström (Intel)
2020-07-22  6:45                 ` [Intel-gfx] " Thomas Hellström (Intel)
2020-07-22  6:45                 ` Thomas Hellström (Intel)
2020-07-22  7:11                 ` Daniel Vetter
2020-07-22  7:11                   ` Daniel Vetter
2020-07-22  7:11                   ` [Intel-gfx] " Daniel Vetter
2020-07-22  7:11                   ` Daniel Vetter
2020-07-22  8:05                   ` Thomas Hellström (Intel)
2020-07-22  8:05                     ` Thomas Hellström (Intel)
2020-07-22  8:05                     ` [Intel-gfx] " Thomas Hellström (Intel)
2020-07-22  8:05                     ` Thomas Hellström (Intel)
2020-07-22  9:45                     ` Daniel Vetter
2020-07-22  9:45                       ` Daniel Vetter
2020-07-22  9:45                       ` [Intel-gfx] " Daniel Vetter
2020-07-22  9:45                       ` Daniel Vetter
2020-07-22 10:31                       ` Thomas Hellström (Intel)
2020-07-22 10:31                         ` Thomas Hellström (Intel)
2020-07-22 10:31                         ` [Intel-gfx] " Thomas Hellström (Intel)
2020-07-22 10:31                         ` Thomas Hellström (Intel)
2020-07-22 11:39                         ` Daniel Vetter
2020-07-22 11:39                           ` Daniel Vetter
2020-07-22 11:39                           ` [Intel-gfx] " Daniel Vetter
2020-07-22 11:39                           ` Daniel Vetter
2020-07-22 12:22                           ` Thomas Hellström (Intel)
2020-07-22 12:22                             ` Thomas Hellström (Intel)
2020-07-22 12:22                             ` [Intel-gfx] " Thomas Hellström (Intel)
2020-07-22 12:22                             ` Thomas Hellström (Intel)
2020-07-22 12:41                             ` Daniel Vetter
2020-07-22 12:41                               ` Daniel Vetter
2020-07-22 12:41                               ` [Intel-gfx] " Daniel Vetter
2020-07-22 12:41                               ` Daniel Vetter
2020-07-22 13:12                               ` Thomas Hellström (Intel)
2020-07-22 13:12                                 ` Thomas Hellström (Intel)
2020-07-22 13:12                                 ` [Intel-gfx] " Thomas Hellström (Intel)
2020-07-22 13:12                                 ` Thomas Hellström (Intel)
2020-07-22 14:07                                 ` Daniel Vetter
2020-07-22 14:07                                   ` Daniel Vetter
2020-07-22 14:07                                   ` [Intel-gfx] " Daniel Vetter
2020-07-22 14:07                                   ` Daniel Vetter
2020-07-22 14:23                                   ` Christian König
2020-07-22 14:23                                     ` Christian König
2020-07-22 14:23                                     ` [Intel-gfx] " Christian König
2020-07-22 14:23                                     ` Christian König
2020-07-22 14:30                                     ` Thomas Hellström (Intel)
2020-07-22 14:30                                       ` Thomas Hellström (Intel)
2020-07-22 14:30                                       ` [Intel-gfx] " Thomas Hellström (Intel)
2020-07-22 14:30                                       ` Thomas Hellström (Intel)
2020-07-22 14:35                                       ` Christian König [this message]
2020-07-22 14:35                                         ` Christian König
2020-07-22 14:35                                         ` [Intel-gfx] " Christian König
2020-07-22 14:35                                         ` Christian König
2020-07-07 20:12 ` [PATCH 04/25] drm/vkms: Annotate vblank timer Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-12 22:27   ` Rodrigo Siqueira
2020-07-12 22:27     ` Rodrigo Siqueira
2020-07-12 22:27     ` [Intel-gfx] " Rodrigo Siqueira
2020-07-12 22:27     ` Rodrigo Siqueira
2020-07-14  9:57     ` Melissa Wen
2020-07-14  9:57       ` Melissa Wen
2020-07-14  9:57       ` [Intel-gfx] " Melissa Wen
2020-07-14  9:57       ` Melissa Wen
2020-07-14  9:59       ` Daniel Vetter
2020-07-14  9:59         ` Daniel Vetter
2020-07-14  9:59         ` [Intel-gfx] " Daniel Vetter
2020-07-14  9:59         ` Daniel Vetter
2020-07-14 14:55         ` Melissa Wen
2020-07-14 14:55           ` Melissa Wen
2020-07-14 14:55           ` [Intel-gfx] " Melissa Wen
2020-07-14 14:55           ` Melissa Wen
2020-07-14 15:23           ` Daniel Vetter
2020-07-14 15:23             ` Daniel Vetter
2020-07-14 15:23             ` [Intel-gfx] " Daniel Vetter
2020-07-14 15:23             ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 05/25] drm/vblank: Annotate with dma-fence signalling section Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 06/25] drm/amdgpu: add dma-fence annotations to atomic commit path Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 07/25] drm/komdea: Annotate dma-fence critical section in " Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-08  5:17   ` james qian wang (Arm Technology China)
2020-07-08  5:17     ` [Intel-gfx] " james qian wang (Arm Technology China)
2020-07-08  5:17     ` james qian wang (Arm Technology China)
2020-07-14  8:34     ` Daniel Vetter
2020-07-14  8:34       ` [Intel-gfx] " Daniel Vetter
2020-07-14  8:34       ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 08/25] drm/malidp: " Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-15 12:53   ` Liviu Dudau
2020-07-15 12:53     ` [Intel-gfx] " Liviu Dudau
2020-07-15 12:53     ` Liviu Dudau
2020-07-15 13:51     ` Daniel Vetter
2020-07-15 13:51       ` [Intel-gfx] " Daniel Vetter
2020-07-15 13:51       ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 09/25] drm/atmel: Use drm_atomic_helper_commit Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:37   ` Sam Ravnborg
2020-07-07 20:37     ` [Intel-gfx] " Sam Ravnborg
2020-07-07 20:37     ` Sam Ravnborg
2020-07-07 20:37     ` Sam Ravnborg
2020-07-07 21:31   ` [PATCH] " Daniel Vetter
2020-07-07 21:31     ` [Intel-gfx] " Daniel Vetter
2020-07-07 21:31     ` Daniel Vetter
2020-07-07 21:31     ` Daniel Vetter
2020-07-14  9:55     ` Sam Ravnborg
2020-07-14  9:55       ` [Intel-gfx] " Sam Ravnborg
2020-07-14  9:55       ` Sam Ravnborg
2020-07-14  9:55       ` Sam Ravnborg
2020-07-07 20:12 ` [PATCH 10/25] drm/imx: Annotate dma-fence critical section in commit path Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 11/25] drm/omapdrm: " Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 12/25] drm/rcar-du: " Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 23:32   ` Laurent Pinchart
2020-07-07 23:32     ` [Intel-gfx] " Laurent Pinchart
2020-07-07 23:32     ` Laurent Pinchart
2020-07-14  8:39     ` Daniel Vetter
2020-07-14  8:39       ` [Intel-gfx] " Daniel Vetter
2020-07-14  8:39       ` Daniel Vetter
     [not found] ` <20200707201229.472834-1-daniel.vetter-/w4YWyX8dFk@public.gmane.org>
2020-07-07 20:12   ` [PATCH 13/25] drm/tegra: " Daniel Vetter
2020-07-07 20:12     ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12     ` Daniel Vetter
2020-07-07 20:12     ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 14/25] drm/tidss: " Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-08  9:01   ` Jyri Sarha
2020-07-08  9:01     ` [Intel-gfx] " Jyri Sarha
2020-07-08  9:01     ` Jyri Sarha
2020-07-07 20:12 ` [PATCH 15/25] drm/tilcdc: Use standard drm_atomic_helper_commit Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-08  9:17   ` Jyri Sarha
2020-07-08  9:17     ` [Intel-gfx] " Jyri Sarha
2020-07-08  9:17     ` Jyri Sarha
2020-07-08  9:27     ` Daniel Vetter
2020-07-08  9:27       ` [Intel-gfx] " Daniel Vetter
2020-07-08  9:27       ` Daniel Vetter
2020-07-08  9:44   ` [PATCH] " Daniel Vetter
2020-07-08  9:44     ` [Intel-gfx] " Daniel Vetter
2020-07-08  9:44     ` Daniel Vetter
2020-07-08 10:21     ` Jyri Sarha
2020-07-08 10:21       ` [Intel-gfx] " Jyri Sarha
2020-07-08 10:21       ` Jyri Sarha
2020-07-08 14:20   ` Daniel Vetter
2020-07-08 14:20     ` [Intel-gfx] " Daniel Vetter
2020-07-08 14:20     ` Daniel Vetter
2020-07-10 11:16     ` Jyri Sarha
2020-07-10 11:16       ` [Intel-gfx] " Jyri Sarha
2020-07-10 11:16       ` Jyri Sarha
2020-07-14  8:32       ` Daniel Vetter
2020-07-14  8:32         ` [Intel-gfx] " Daniel Vetter
2020-07-14  8:32         ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 16/25] drm/atomic-helper: Add dma-fence annotations Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 17/25] drm/scheduler: use dma-fence annotations in main thread Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 18/25] drm/amdgpu: use dma-fence annotations in cs_submit() Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 19/25] drm/amdgpu: s/GFP_KERNEL/GFP_ATOMIC in scheduler code Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-14 10:49   ` Daniel Vetter
2020-07-14 10:49     ` Daniel Vetter
2020-07-14 10:49     ` [Intel-gfx] " Daniel Vetter
2020-07-14 10:49     ` Daniel Vetter
2020-07-14 11:40     ` Christian König
2020-07-14 11:40       ` Christian König
2020-07-14 11:40       ` [Intel-gfx] " Christian König
2020-07-14 11:40       ` Christian König
2020-07-14 14:31       ` Daniel Vetter
2020-07-14 14:31         ` Daniel Vetter
2020-07-14 14:31         ` [Intel-gfx] " Daniel Vetter
2020-07-14 14:31         ` Daniel Vetter
2020-07-15  9:17         ` Christian König
2020-07-15  9:17           ` Christian König
2020-07-15  9:17           ` [Intel-gfx] " Christian König
2020-07-15  9:17           ` Christian König
2020-07-15 11:53           ` Daniel Vetter
2020-07-15 11:53             ` Daniel Vetter
2020-07-15 11:53             ` [Intel-gfx] " Daniel Vetter
2020-07-15 11:53             ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 20/25] drm/amdgpu: DC also loves to allocate stuff where it shouldn't Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-14 11:12   ` Daniel Vetter
2020-07-14 11:12     ` Daniel Vetter
2020-07-14 11:12     ` [Intel-gfx] " Daniel Vetter
2020-07-14 11:12     ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 21/25] drm/amdgpu/dc: Stop dma_resv_lock inversion in commit_tail Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 22/25] drm/scheduler: use dma-fence annotations in tdr work Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 23/25] drm/amdgpu: use dma-fence annotations for gpu reset code Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 24/25] Revert "drm/amdgpu: add fbdev suspend/resume on gpu reset" Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12 ` [PATCH 25/25] drm/amdgpu: gpu recovery does full modesets Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 20:12   ` [Intel-gfx] " Daniel Vetter
2020-07-07 20:12   ` Daniel Vetter
2020-07-07 22:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for dma-fence annotations, round 3 (rev2) Patchwork
2020-07-07 22:12 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-07-07 22:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-08  0:59 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-07-08 11:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for dma-fence annotations, round 3 (rev3) Patchwork
2020-07-08 11:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-07-08 11:37 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-07-08 14:53 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for dma-fence annotations, round 3 (rev4) Patchwork
2020-07-08 14:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-07-08 15:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-08 18:46 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-07-09 13:05 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for dma-fence annotations, round 3 (rev6) Patchwork
2020-07-09 13:06 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-07-09 13:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-09 15:38 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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all data and code used by this external index.