[PATCH 0/5] Fix some bugs

[PATCH 0/5] Fix some bugs

[Song Gao]

hi,

This series fix some bugs find from RISU test.

Thanks.
Song Gao

Song Gao (5):
  target/loongarch: ftint_xxx insns set the result high 32bit 0xffffffff
  target/loongarch: bstrins.w need set dest register EXT_SIGN
  target/loongarch: Fix fnm{sub/add}_{s/d} set wrong flags
  target/loongarch: flogb_{s/d} add set float_flag_divbyzero
  target/loongarch: div if x/0 set dividend to 0

 target/loongarch/fpu_helper.c                 | 32 ++++++++++++-----
 target/loongarch/insn_trans/trans_arith.c.inc | 34 +++++++++++++++----
 target/loongarch/insn_trans/trans_bit.c.inc   |  4 +--
 .../loongarch/insn_trans/trans_farith.c.inc   | 12 +++----
 4 files changed, 58 insertions(+), 24 deletions(-)

-- 
2.31.1

[PATCH 1/5] target/loongarch: ftint_xxx insns set the result high 32bit 0xffffffff

[Song Gao]

we just set high 32bit 0xffffffff as the other float instructions do.

Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 target/loongarch/fpu_helper.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/target/loongarch/fpu_helper.c b/target/loongarch/fpu_helper.c
index 4b9637210a..1a24667eaf 100644
--- a/target/loongarch/fpu_helper.c
+++ b/target/loongarch/fpu_helper.c
@@ -518,7 +518,7 @@ uint64_t helper_frint_s(CPULoongArchState *env, uint64_t fj)
 {
     uint64_t fd;
 
-    fd = (uint64_t)(float32_round_to_int((uint32_t)fj, &env->fp_status));
+    fd = nanbox_s(float32_round_to_int((uint32_t)fj, &env->fp_status));
     update_fcsr0(env, GETPC());
     return fd;
 }
@@ -574,7 +574,7 @@ uint64_t helper_ftintrm_w_d(CPULoongArchState *env, uint64_t fj)
     FloatRoundMode old_mode = get_float_rounding_mode(&env->fp_status);
 
     set_float_rounding_mode(float_round_down, &env->fp_status);
-    fd = (uint64_t)float64_to_int32(fj, &env->fp_status);
+    fd = nanbox_s(float64_to_int32(fj, &env->fp_status));
     set_float_rounding_mode(old_mode, &env->fp_status);
 
     if (get_float_exception_flags(&env->fp_status) & (float_flag_invalid)) {
@@ -592,7 +592,7 @@ uint64_t helper_ftintrm_w_s(CPULoongArchState *env, uint64_t fj)
     FloatRoundMode old_mode = get_float_rounding_mode(&env->fp_status);
 
     set_float_rounding_mode(float_round_down, &env->fp_status);
-    fd = (uint64_t)float32_to_int32((uint32_t)fj, &env->fp_status);
+    fd = nanbox_s(float32_to_int32((uint32_t)fj, &env->fp_status));
     set_float_rounding_mode(old_mode, &env->fp_status);
 
     if (get_float_exception_flags(&env->fp_status) & (float_flag_invalid)) {
@@ -646,7 +646,7 @@ uint64_t helper_ftintrp_w_d(CPULoongArchState *env, uint64_t fj)
     FloatRoundMode old_mode = get_float_rounding_mode(&env->fp_status);
 
     set_float_rounding_mode(float_round_up, &env->fp_status);
-    fd = (uint64_t)float64_to_int32(fj, &env->fp_status);
+    fd = nanbox_s(float64_to_int32(fj, &env->fp_status));
     set_float_rounding_mode(old_mode, &env->fp_status);
 
     if (get_float_exception_flags(&env->fp_status) & (float_flag_invalid)) {
@@ -664,7 +664,7 @@ uint64_t helper_ftintrp_w_s(CPULoongArchState *env, uint64_t fj)
     FloatRoundMode old_mode = get_float_rounding_mode(&env->fp_status);
 
     set_float_rounding_mode(float_round_up, &env->fp_status);
-    fd = (uint64_t)float32_to_int32((uint32_t)fj, &env->fp_status);
+    fd = nanbox_s(float32_to_int32((uint32_t)fj, &env->fp_status));
     set_float_rounding_mode(old_mode, &env->fp_status);
 
     if (get_float_exception_flags(&env->fp_status) & (float_flag_invalid)) {
@@ -715,7 +715,7 @@ uint64_t helper_ftintrz_w_d(CPULoongArchState *env, uint64_t fj)
     uint64_t fd;
     FloatRoundMode old_mode = get_float_rounding_mode(&env->fp_status);
 
-    fd = (uint64_t)float64_to_int32_round_to_zero(fj, &env->fp_status);
+    fd = nanbox_s(float64_to_int32_round_to_zero(fj, &env->fp_status));
     set_float_rounding_mode(old_mode, &env->fp_status);
 
     if (get_float_exception_flags(&env->fp_status) & (float_flag_invalid)) {
@@ -786,7 +786,7 @@ uint64_t helper_ftintrne_w_d(CPULoongArchState *env, uint64_t fj)
     FloatRoundMode old_mode = get_float_rounding_mode(&env->fp_status);
 
     set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
-    fd = (uint64_t)float64_to_int32(fj, &env->fp_status);
+    fd = nanbox_s(float64_to_int32(fj, &env->fp_status));
     set_float_rounding_mode(old_mode, &env->fp_status);
 
     if (get_float_exception_flags(&env->fp_status) & (float_flag_invalid)) {
@@ -848,7 +848,7 @@ uint64_t helper_ftint_w_s(CPULoongArchState *env, uint64_t fj)
 {
     uint64_t fd;
 
-    fd = (uint64_t)float32_to_int32((uint32_t)fj, &env->fp_status);
+    fd = nanbox_s(float32_to_int32((uint32_t)fj, &env->fp_status));
     if (get_float_exception_flags(&env->fp_status) & (float_flag_invalid)) {
         if (float32_is_any_nan((uint32_t)fj)) {
             fd = 0;
@@ -862,7 +862,7 @@ uint64_t helper_ftint_w_d(CPULoongArchState *env, uint64_t fj)
 {
     uint64_t fd;
 
-    fd = (uint64_t)float64_to_int32(fj, &env->fp_status);
+    fd = nanbox_s(float64_to_int32(fj, &env->fp_status));
     if (get_float_exception_flags(&env->fp_status) & (float_flag_invalid)) {
         if (float64_is_any_nan(fj)) {
             fd = 0;
-- 
2.31.1

[PATCH 2/5] target/loongarch: bstrins.w need set dest register EXT_SIGN

[Song Gao]

Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 target/loongarch/insn_trans/trans_bit.c.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/loongarch/insn_trans/trans_bit.c.inc b/target/loongarch/insn_trans/trans_bit.c.inc
index 9337714ec4..33e94878fd 100644
--- a/target/loongarch/insn_trans/trans_bit.c.inc
+++ b/target/loongarch/insn_trans/trans_bit.c.inc
@@ -37,7 +37,7 @@ static bool gen_rr_ms_ls(DisasContext *ctx, arg_rr_ms_ls *a,
                          DisasExtend src_ext, DisasExtend dst_ext,
                          void (*func)(TCGv, TCGv, unsigned int, unsigned int))
 {
-    TCGv dest = gpr_dst(ctx, a->rd, dst_ext);
+    TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
     TCGv src1 = gpr_src(ctx, a->rj, src_ext);
 
     if (a->ls > a->ms) {
@@ -206,7 +206,7 @@ TRANS(maskeqz, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_maskeqz)
 TRANS(masknez, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_masknez)
 TRANS(bytepick_w, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_w)
 TRANS(bytepick_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)
-TRANS(bstrins_w, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
+TRANS(bstrins_w, gen_rr_ms_ls, EXT_NONE, EXT_SIGN, gen_bstrins)
 TRANS(bstrins_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
 TRANS(bstrpick_w, gen_rr_ms_ls, EXT_NONE, EXT_SIGN, tcg_gen_extract_tl)
 TRANS(bstrpick_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, tcg_gen_extract_tl)
-- 
2.31.1

Re: [PATCH 2/5] target/loongarch: bstrins.w need set dest register EXT_SIGN

[Qi Hu]

On 2022/9/17 15:59, Song Gao wrote:
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> ---
>   target/loongarch/insn_trans/trans_bit.c.inc | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/loongarch/insn_trans/trans_bit.c.inc b/target/loongarch/insn_trans/trans_bit.c.inc
> index 9337714ec4..33e94878fd 100644
> --- a/target/loongarch/insn_trans/trans_bit.c.inc
> +++ b/target/loongarch/insn_trans/trans_bit.c.inc
> @@ -37,7 +37,7 @@ static bool gen_rr_ms_ls(DisasContext *ctx, arg_rr_ms_ls *a,
>                            DisasExtend src_ext, DisasExtend dst_ext,
>                            void (*func)(TCGv, TCGv, unsigned int, unsigned int))
>   {
> -    TCGv dest = gpr_dst(ctx, a->rd, dst_ext);
> +    TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
I think this may not be correct. Maybe the code was used for debugging 
but forgot to modify?
>       TCGv src1 = gpr_src(ctx, a->rj, src_ext);
>   
>       if (a->ls > a->ms) {
> @@ -206,7 +206,7 @@ TRANS(maskeqz, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_maskeqz)
>   TRANS(masknez, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_masknez)
>   TRANS(bytepick_w, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_w)
>   TRANS(bytepick_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)
> -TRANS(bstrins_w, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
> +TRANS(bstrins_w, gen_rr_ms_ls, EXT_NONE, EXT_SIGN, gen_bstrins)
>   TRANS(bstrins_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
>   TRANS(bstrpick_w, gen_rr_ms_ls, EXT_NONE, EXT_SIGN, tcg_gen_extract_tl)
>   TRANS(bstrpick_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, tcg_gen_extract_tl)

Re: [PATCH 2/5] target/loongarch: bstrins.w need set dest register EXT_SIGN

[gaosong]

在 2022/9/17 下午4:41, Qi Hu 写道:
>
> On 2022/9/17 15:59, Song Gao wrote:
>> Signed-off-by: Song Gao <gaosong@loongson.cn>
>> ---
>>   target/loongarch/insn_trans/trans_bit.c.inc | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/loongarch/insn_trans/trans_bit.c.inc 
>> b/target/loongarch/insn_trans/trans_bit.c.inc
>> index 9337714ec4..33e94878fd 100644
>> --- a/target/loongarch/insn_trans/trans_bit.c.inc
>> +++ b/target/loongarch/insn_trans/trans_bit.c.inc
>> @@ -37,7 +37,7 @@ static bool gen_rr_ms_ls(DisasContext *ctx, 
>> arg_rr_ms_ls *a,
>>                            DisasExtend src_ext, DisasExtend dst_ext,
>>                            void (*func)(TCGv, TCGv, unsigned int, 
>> unsigned int))
>>   {
>> -    TCGv dest = gpr_dst(ctx, a->rd, dst_ext);
>> +    TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
> I think this may not be correct. Maybe the code was used for debugging 
> but forgot to modify?
We just need EXT_SIGN  the result.
>>       TCGv src1 = gpr_src(ctx, a->rj, src_ext);
>>         if (a->ls > a->ms) {
>> @@ -206,7 +206,7 @@ TRANS(maskeqz, gen_rrr, EXT_NONE, EXT_NONE, 
>> EXT_NONE, gen_maskeqz)
>>   TRANS(masknez, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_masknez)
>>   TRANS(bytepick_w, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_w)
>>   TRANS(bytepick_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)
>> -TRANS(bstrins_w, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
>> +TRANS(bstrins_w, gen_rr_ms_ls, EXT_NONE, EXT_SIGN, gen_bstrins)
>>   TRANS(bstrins_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
>>   TRANS(bstrpick_w, gen_rr_ms_ls, EXT_NONE, EXT_SIGN, 
>> tcg_gen_extract_tl)
>>   TRANS(bstrpick_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, 
>> tcg_gen_extract_tl)
>

Re: [PATCH 2/5] target/loongarch: bstrins.w need set dest register EXT_SIGN

[Qi Hu]

On 2022/9/17 17:16, gaosong wrote:
>
> 在 2022/9/17 下午4:41, Qi Hu 写道:
>>
>> On 2022/9/17 15:59, Song Gao wrote:
>>> Signed-off-by: Song Gao <gaosong@loongson.cn>
>>> ---
>>>   target/loongarch/insn_trans/trans_bit.c.inc | 4 ++--
>>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/target/loongarch/insn_trans/trans_bit.c.inc 
>>> b/target/loongarch/insn_trans/trans_bit.c.inc
>>> index 9337714ec4..33e94878fd 100644
>>> --- a/target/loongarch/insn_trans/trans_bit.c.inc
>>> +++ b/target/loongarch/insn_trans/trans_bit.c.inc
>>> @@ -37,7 +37,7 @@ static bool gen_rr_ms_ls(DisasContext *ctx, 
>>> arg_rr_ms_ls *a,
>>>                            DisasExtend src_ext, DisasExtend dst_ext,
>>>                            void (*func)(TCGv, TCGv, unsigned int, 
>>> unsigned int))
>>>   {
>>> -    TCGv dest = gpr_dst(ctx, a->rd, dst_ext);
>>> +    TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
>> I think this may not be correct. Maybe the code was used for 
>> debugging but forgot to modify?
> We just need EXT_SIGN  the result.

Got it. Thanks.

Qi

>>>       TCGv src1 = gpr_src(ctx, a->rj, src_ext);
>>>         if (a->ls > a->ms) {
>>> @@ -206,7 +206,7 @@ TRANS(maskeqz, gen_rrr, EXT_NONE, EXT_NONE, 
>>> EXT_NONE, gen_maskeqz)
>>>   TRANS(masknez, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_masknez)
>>>   TRANS(bytepick_w, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_w)
>>>   TRANS(bytepick_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)
>>> -TRANS(bstrins_w, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
>>> +TRANS(bstrins_w, gen_rr_ms_ls, EXT_NONE, EXT_SIGN, gen_bstrins)
>>>   TRANS(bstrins_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, gen_bstrins)
>>>   TRANS(bstrpick_w, gen_rr_ms_ls, EXT_NONE, EXT_SIGN, 
>>> tcg_gen_extract_tl)
>>>   TRANS(bstrpick_d, gen_rr_ms_ls, EXT_NONE, EXT_NONE, 
>>> tcg_gen_extract_tl)
>>
>

[PATCH 3/5] target/loongarch: Fix fnm{sub/add}_{s/d} set wrong flags

[Song Gao]

Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 target/loongarch/insn_trans/trans_farith.c.inc | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/loongarch/insn_trans/trans_farith.c.inc b/target/loongarch/insn_trans/trans_farith.c.inc
index 65ad2ffab8..7bb3f41aee 100644
--- a/target/loongarch/insn_trans/trans_farith.c.inc
+++ b/target/loongarch/insn_trans/trans_farith.c.inc
@@ -97,9 +97,9 @@ TRANS(fmadd_s, gen_muladd, gen_helper_fmuladd_s, 0)
 TRANS(fmadd_d, gen_muladd, gen_helper_fmuladd_d, 0)
 TRANS(fmsub_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_c)
 TRANS(fmsub_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_c)
-TRANS(fnmadd_s, gen_muladd, gen_helper_fmuladd_s,
-      float_muladd_negate_product | float_muladd_negate_c)
-TRANS(fnmadd_d, gen_muladd, gen_helper_fmuladd_d,
-      float_muladd_negate_product | float_muladd_negate_c)
-TRANS(fnmsub_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_product)
-TRANS(fnmsub_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_product)
+TRANS(fnmadd_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_result)
+TRANS(fnmadd_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_result)
+TRANS(fnmsub_s, gen_muladd, gen_helper_fmuladd_s,
+      float_muladd_negate_c | float_muladd_negate_result)
+TRANS(fnmsub_d, gen_muladd, gen_helper_fmuladd_d,
+      float_muladd_negate_c | float_muladd_negate_result)
-- 
2.31.1

[PATCH 4/5] target/loongarch: flogb_{s/d} add set float_flag_divbyzero

[Song Gao]

if fj ==0 or fj == INT32_MIN/INT64_MIN, LoongArch host set fcsr cause exception FP_DIV0,
So we need set exception flags float_flagdivbyzero if fj ==0.

Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 target/loongarch/fpu_helper.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/target/loongarch/fpu_helper.c b/target/loongarch/fpu_helper.c
index 1a24667eaf..8ddfbd1abd 100644
--- a/target/loongarch/fpu_helper.c
+++ b/target/loongarch/fpu_helper.c
@@ -322,6 +322,13 @@ uint64_t helper_flogb_s(CPULoongArchState *env, uint64_t fj)
     fp = float32_log2((uint32_t)fj, status);
     fd = nanbox_s(float32_round_to_int(fp, status));
     set_float_rounding_mode(old_mode, status);
+    /*
+     * LoongArch host if fj == 0 or INT32_MIN , set the fcsr cause FP_DIV0
+     * so we need set exception flags float_flag_divbyzero.
+     */
+    if (((uint32_t)fj == 0) | ((uint32_t)fj == INT32_MIN )) {
+        set_float_exception_flags(float_flag_divbyzero, status);
+    }
     update_fcsr0_mask(env, GETPC(), float_flag_inexact);
     return fd;
 }
@@ -336,6 +343,13 @@ uint64_t helper_flogb_d(CPULoongArchState *env, uint64_t fj)
     fd = float64_log2(fj, status);
     fd = float64_round_to_int(fd, status);
     set_float_rounding_mode(old_mode, status);
+    /*
+     * LoongArch host if fj == 0 or INT64_MIN , set the fcsr cause FP_DIV0
+     * so we need set exception flags float_flag_divbyzero.
+     */
+    if ( (fj == 0) | (fj == INT64_MIN)) {
+        set_float_exception_flags(float_flag_divbyzero, status);
+    }
     update_fcsr0_mask(env, GETPC(), float_flag_inexact);
     return fd;
 }
-- 
2.31.1

[PATCH 5/5] target/loongarch: div if x/0 set dividend to 0

[Song Gao]

div.d, div.du, div,w, div.wu, the LoongArch host if x/0  the result is 0.
So we set the divisor to 1 and the dividend to 0.

Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 target/loongarch/insn_trans/trans_arith.c.inc | 34 +++++++++++++++----
 1 file changed, 27 insertions(+), 7 deletions(-)

diff --git a/target/loongarch/insn_trans/trans_arith.c.inc b/target/loongarch/insn_trans/trans_arith.c.inc
index 8e45eadbc8..c97afb16f9 100644
--- a/target/loongarch/insn_trans/trans_arith.c.inc
+++ b/target/loongarch/insn_trans/trans_arith.c.inc
@@ -147,12 +147,28 @@ static void prep_divisor_du(TCGv ret, TCGv src2)
     tcg_gen_movcond_tl(TCG_COND_EQ, ret, src2, zero, one, src2);
 }
 
+static void prep_div(TCGv divisor, TCGv dividend, TCGv src1, TCGv src2)
+{
+    TCGv zero = tcg_constant_tl(0);
+    TCGv one = tcg_constant_tl(1);
+
+    /*
+     * If x / 0, set the diviend to 0 set the divisor to 1
+     * this is the same with LoongArch host.
+     */
+    tcg_gen_movcond_tl(TCG_COND_EQ, dividend, src2, zero, zero, src1);
+    tcg_gen_movcond_tl(TCG_COND_EQ, divisor, src2, zero, one, src2);
+}
+
 static void gen_div_d(TCGv dest, TCGv src1, TCGv src2)
 {
     TCGv t0 = tcg_temp_new();
-    prep_divisor_d(t0, src1, src2);
-    tcg_gen_div_tl(dest, src1, t0);
+    TCGv t1 = tcg_temp_new();
+
+    prep_div(t0, t1, src1, src2);
+    tcg_gen_div_tl(dest, t1, t0);
     tcg_temp_free(t0);
+    tcg_temp_free(t1);
 }
 
 static void gen_rem_d(TCGv dest, TCGv src1, TCGv src2)
@@ -166,9 +182,11 @@ static void gen_rem_d(TCGv dest, TCGv src1, TCGv src2)
 static void gen_div_du(TCGv dest, TCGv src1, TCGv src2)
 {
     TCGv t0 = tcg_temp_new();
-    prep_divisor_du(t0, src2);
-    tcg_gen_divu_tl(dest, src1, t0);
+    TCGv t1 = tcg_temp_new();
+    prep_div(t0, t1, src1, src2);
+    tcg_gen_divu_tl(dest, t1, t0);
     tcg_temp_free(t0);
+    tcg_temp_free(t1);
 }
 
 static void gen_rem_du(TCGv dest, TCGv src1, TCGv src2)
@@ -182,10 +200,12 @@ static void gen_rem_du(TCGv dest, TCGv src1, TCGv src2)
 static void gen_div_w(TCGv dest, TCGv src1, TCGv src2)
 {
     TCGv t0 = tcg_temp_new();
-    /* We need not check for integer overflow for div_w. */
-    prep_divisor_du(t0, src2);
-    tcg_gen_div_tl(dest, src1, t0);
+    TCGv t1 = tcg_temp_new();
+
+    prep_div(t0, t1, src1, src2);
+    tcg_gen_div_tl(dest, t1, t0);
     tcg_temp_free(t0);
+    tcg_temp_free(t1);
 }
 
 static void gen_rem_w(TCGv dest, TCGv src1, TCGv src2)
-- 
2.31.1

Re: [PATCH 5/5] target/loongarch: div if x/0 set dividend to 0

[Qi Hu]

On 2022/9/17 15:59, Song Gao wrote:
> div.d, div.du, div,w, div.wu, the LoongArch host if x/0  the result is 0.

The message has a typo: "div,w" => "div.w"

Also I don't know why we need to do this, since the manual say: "When 
the divisor is 0, the result can be any value".

> So we set the divisor to 1 and the dividend to 0.
>
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> ---
>   target/loongarch/insn_trans/trans_arith.c.inc | 34 +++++++++++++++----
>   1 file changed, 27 insertions(+), 7 deletions(-)
>
> diff --git a/target/loongarch/insn_trans/trans_arith.c.inc b/target/loongarch/insn_trans/trans_arith.c.inc
> index 8e45eadbc8..c97afb16f9 100644
> --- a/target/loongarch/insn_trans/trans_arith.c.inc
> +++ b/target/loongarch/insn_trans/trans_arith.c.inc
> @@ -147,12 +147,28 @@ static void prep_divisor_du(TCGv ret, TCGv src2)
>       tcg_gen_movcond_tl(TCG_COND_EQ, ret, src2, zero, one, src2);
>   }
>   
> +static void prep_div(TCGv divisor, TCGv dividend, TCGv src1, TCGv src2)
> +{
> +    TCGv zero = tcg_constant_tl(0);
> +    TCGv one = tcg_constant_tl(1);
> +
> +    /*
> +     * If x / 0, set the diviend to 0 set the divisor to 1
> +     * this is the same with LoongArch host.
> +     */
> +    tcg_gen_movcond_tl(TCG_COND_EQ, dividend, src2, zero, zero, src1);
> +    tcg_gen_movcond_tl(TCG_COND_EQ, divisor, src2, zero, one, src2);
> +}
> +
>   static void gen_div_d(TCGv dest, TCGv src1, TCGv src2)
>   {
>       TCGv t0 = tcg_temp_new();
> -    prep_divisor_d(t0, src1, src2);
> -    tcg_gen_div_tl(dest, src1, t0);
> +    TCGv t1 = tcg_temp_new();
> +
> +    prep_div(t0, t1, src1, src2);
> +    tcg_gen_div_tl(dest, t1, t0);
>       tcg_temp_free(t0);
> +    tcg_temp_free(t1);
>   }
>   
>   static void gen_rem_d(TCGv dest, TCGv src1, TCGv src2)
> @@ -166,9 +182,11 @@ static void gen_rem_d(TCGv dest, TCGv src1, TCGv src2)
>   static void gen_div_du(TCGv dest, TCGv src1, TCGv src2)
>   {
>       TCGv t0 = tcg_temp_new();
> -    prep_divisor_du(t0, src2);
> -    tcg_gen_divu_tl(dest, src1, t0);
> +    TCGv t1 = tcg_temp_new();
> +    prep_div(t0, t1, src1, src2);
> +    tcg_gen_divu_tl(dest, t1, t0);
>       tcg_temp_free(t0);
> +    tcg_temp_free(t1);
>   }
>   
>   static void gen_rem_du(TCGv dest, TCGv src1, TCGv src2)
> @@ -182,10 +200,12 @@ static void gen_rem_du(TCGv dest, TCGv src1, TCGv src2)
>   static void gen_div_w(TCGv dest, TCGv src1, TCGv src2)
>   {
>       TCGv t0 = tcg_temp_new();
> -    /* We need not check for integer overflow for div_w. */
> -    prep_divisor_du(t0, src2);
> -    tcg_gen_div_tl(dest, src1, t0);
> +    TCGv t1 = tcg_temp_new();
> +
> +    prep_div(t0, t1, src1, src2);
> +    tcg_gen_div_tl(dest, t1, t0);
>       tcg_temp_free(t0);
> +    tcg_temp_free(t1);
>   }
>   
>   static void gen_rem_w(TCGv dest, TCGv src1, TCGv src2)

Re: [PATCH 5/5] target/loongarch: div if x/0 set dividend to 0

[gaosong]

在 2022/9/17 下午4:59, Qi Hu 写道:
>
> On 2022/9/17 15:59, Song Gao wrote:
>> div.d, div.du, div,w, div.wu, the LoongArch host if x/0  the result 
>> is 0.
>
> The message has a typo: "div,w" => "div.w"
>
> Also I don't know why we need to do this, since the manual say: "When 
> the divisor is 0, the result can be any value".
>
I tested on LoongArch host,   the result is always 0.

>> So we set the divisor to 1 and the dividend to 0.
>>
>> Signed-off-by: Song Gao <gaosong@loongson.cn>
>> ---
>>   target/loongarch/insn_trans/trans_arith.c.inc | 34 +++++++++++++++----
>>   1 file changed, 27 insertions(+), 7 deletions(-)
>>
>> diff --git a/target/loongarch/insn_trans/trans_arith.c.inc 
>> b/target/loongarch/insn_trans/trans_arith.c.inc
>> index 8e45eadbc8..c97afb16f9 100644
>> --- a/target/loongarch/insn_trans/trans_arith.c.inc
>> +++ b/target/loongarch/insn_trans/trans_arith.c.inc
>> @@ -147,12 +147,28 @@ static void prep_divisor_du(TCGv ret, TCGv src2)
>>       tcg_gen_movcond_tl(TCG_COND_EQ, ret, src2, zero, one, src2);
>>   }
>>   +static void prep_div(TCGv divisor, TCGv dividend, TCGv src1, TCGv 
>> src2)
>> +{
>> +    TCGv zero = tcg_constant_tl(0);
>> +    TCGv one = tcg_constant_tl(1);
>> +
>> +    /*
>> +     * If x / 0, set the diviend to 0 set the divisor to 1
>> +     * this is the same with LoongArch host.
>> +     */
>> +    tcg_gen_movcond_tl(TCG_COND_EQ, dividend, src2, zero, zero, src1);
>> +    tcg_gen_movcond_tl(TCG_COND_EQ, divisor, src2, zero, one, src2);
>> +}
>> +
>>   static void gen_div_d(TCGv dest, TCGv src1, TCGv src2)
>>   {
>>       TCGv t0 = tcg_temp_new();
>> -    prep_divisor_d(t0, src1, src2);
>> -    tcg_gen_div_tl(dest, src1, t0);
>> +    TCGv t1 = tcg_temp_new();
>> +
>> +    prep_div(t0, t1, src1, src2);
>> +    tcg_gen_div_tl(dest, t1, t0);
>>       tcg_temp_free(t0);
>> +    tcg_temp_free(t1);
>>   }
>>     static void gen_rem_d(TCGv dest, TCGv src1, TCGv src2)
>> @@ -166,9 +182,11 @@ static void gen_rem_d(TCGv dest, TCGv src1, TCGv 
>> src2)
>>   static void gen_div_du(TCGv dest, TCGv src1, TCGv src2)
>>   {
>>       TCGv t0 = tcg_temp_new();
>> -    prep_divisor_du(t0, src2);
>> -    tcg_gen_divu_tl(dest, src1, t0);
>> +    TCGv t1 = tcg_temp_new();
>> +    prep_div(t0, t1, src1, src2);
>> +    tcg_gen_divu_tl(dest, t1, t0);
>>       tcg_temp_free(t0);
>> +    tcg_temp_free(t1);
>>   }
>>     static void gen_rem_du(TCGv dest, TCGv src1, TCGv src2)
>> @@ -182,10 +200,12 @@ static void gen_rem_du(TCGv dest, TCGv src1, 
>> TCGv src2)
>>   static void gen_div_w(TCGv dest, TCGv src1, TCGv src2)
>>   {
>>       TCGv t0 = tcg_temp_new();
>> -    /* We need not check for integer overflow for div_w. */
>> -    prep_divisor_du(t0, src2);
>> -    tcg_gen_div_tl(dest, src1, t0);
>> +    TCGv t1 = tcg_temp_new();
>> +
>> +    prep_div(t0, t1, src1, src2);
>> +    tcg_gen_div_tl(dest, t1, t0);
>>       tcg_temp_free(t0);
>> +    tcg_temp_free(t1);
>>   }
>>     static void gen_rem_w(TCGv dest, TCGv src1, TCGv src2)
>

Re: [PATCH 5/5] target/loongarch: div if x/0 set dividend to 0

[Richard Henderson]

On 9/17/22 11:12, gaosong wrote:
> 
> 在 2022/9/17 下午4:59, Qi Hu 写道:
>>
>> On 2022/9/17 15:59, Song Gao wrote:
>>> div.d, div.du, div,w, div.wu, the LoongArch host if x/0  the result is 0.
>>
>> The message has a typo: "div,w" => "div.w"
>>
>> Also I don't know why we need to do this, since the manual say: "When the divisor is 0, 
>> the result can be any value".
>>
> I tested on LoongArch host,   the result is always 0.

But it is legal for a different loongarch host implementation to return some other value. 
  Therefore the test itself is not correct.


r~

Re: [PATCH 5/5] target/loongarch: div if x/0 set dividend to 0

[gaosong]

在 2022/9/17 下午6:12, Richard Henderson 写道:
> On 9/17/22 11:12, gaosong wrote:
>>
>> 在 2022/9/17 下午4:59, Qi Hu 写道:
>>>
>>> On 2022/9/17 15:59, Song Gao wrote:
>>>> div.d, div.du, div,w, div.wu, the LoongArch host if x/0  the result 
>>>> is 0.
>>>
>>> The message has a typo: "div,w" => "div.w"
>>>
>>> Also I don't know why we need to do this, since the manual say: 
>>> "When the divisor is 0, the result can be any value".
>>>
>> I tested on LoongArch host,   the result is always 0.
>
> But it is legal for a different loongarch host implementation to 
> return some other value.  Therefore the test itself is not correct.
>
I think the manual maybe not correct,  the hardware engineer said that 
they need to comfirm  whether the result is always 0.

Thanks.
Song Gao
> r~

Re: [PATCH 5/5] target/loongarch: div if x/0 set dividend to 0

[Qi Hu]

On 2022/9/19 19:45, gaosong wrote:
>
> 在 2022/9/17 下午6:12, Richard Henderson 写道:
>> On 9/17/22 11:12, gaosong wrote:
>>>
>>> 在 2022/9/17 下午4:59, Qi Hu 写道:
>>>>
>>>> On 2022/9/17 15:59, Song Gao wrote:
>>>>> div.d, div.du, div,w, div.wu, the LoongArch host if x/0  the 
>>>>> result is 0.
>>>>
>>>> The message has a typo: "div,w" => "div.w"
>>>>
>>>> Also I don't know why we need to do this, since the manual say: 
>>>> "When the divisor is 0, the result can be any value".
>>>>
>>> I tested on LoongArch host,   the result is always 0.
>>
>> But it is legal for a different loongarch host implementation to 
>> return some other value.  Therefore the test itself is not correct.
>>
> I think the manual maybe not correct,  the hardware engineer said that 
> they need to comfirm  whether the result is always 0.
>
> Thanks.
> Song Gao

Hi,

The hardware designers suggested that 0 should not be used as the 
default value when "div 0" occurs. The behavior is not guaranteed in 
future processors.

So I think there are some ways to solve this:

- Remove this case("div 0") from risu test.

- Keep this patch by yourself. If you want to do risu test, patch it. :-)


regards,

Qi

>> r~
>