All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section
@ 2019-07-16 22:03 Dhinakaran Pandiyan
  2019-07-16 22:10 ` Pandiyan, Dhinakaran
                   ` (3 more replies)
  0 siblings, 4 replies; 9+ messages in thread
From: Dhinakaran Pandiyan @ 2019-07-16 22:03 UTC (permalink / raw)
  To: intel-gfx; +Cc: Dhinakaran Pandiyan

A single 32-bit PSR2 training pattern field follows the sixteen element
array of PSR table entries in the VBT spec. But, we incorrectly define
this PSR2 field for each of the PSR table entries. As a result, the PSR1
training pattern duration for any panel_type != 0 will be parsed
incorrectly. Secondly, PSR2 training pattern durations for VBTs with bdb
version >= 226 will also be wrong.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time")
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 2 +-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 21501d565327..b416b394b641 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -766,7 +766,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
 	}
 
 	if (bdb->version >= 226) {
-		u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
+		u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
 
 		wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
 		switch (wakeup_time) {
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 93f5c9d204d6..09cd37fb0b1c 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -481,13 +481,13 @@ struct psr_table {
 	/* TP wake up time in multiple of 100 */
 	u16 tp1_wakeup_time;
 	u16 tp2_tp3_wakeup_time;
-
-	/* PSR2 TP2/TP3 wakeup time for 16 panels */
-	u32 psr2_tp2_tp3_wakeup_time;
 } __packed;
 
 struct bdb_psr {
 	struct psr_table psr_table[16];
+
+	/* PSR2 TP2/TP3 wakeup time for 16 panels */
+	u32 psr2_tp2_tp3_wakeup_time;
 } __packed;
 
 /*
-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section
  2019-07-16 22:03 [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section Dhinakaran Pandiyan
@ 2019-07-16 22:10 ` Pandiyan, Dhinakaran
  2019-07-17 16:41   ` Souza, Jose
  2019-07-17 19:49   ` François Guerraz
  2019-07-17 11:35 ` [PATCH] " Ville Syrjälä
                   ` (2 subsequent siblings)
  3 siblings, 2 replies; 9+ messages in thread
From: Pandiyan, Dhinakaran @ 2019-07-16 22:10 UTC (permalink / raw)
  To: intel-gfx

On Tue, 2019-07-16 at 15:03 -0700, Dhinakaran Pandiyan wrote:
> A single 32-bit PSR2 training pattern field follows the sixteen element
> array of PSR table entries in the VBT spec. But, we incorrectly define
> this PSR2 field for each of the PSR table entries. As a result, the PSR1
> training pattern duration for any panel_type != 0 will be parsed
> incorrectly. Secondly, PSR2 training pattern durations for VBTs with bdb
> version >= 226 will also be wrong.

This was reported and bisected by 
Aliaksei Urbanski here - https://bugzilla.kernel.org/show_bug.cgi?id=204183

I'll add Bugzilla after the fix is confirmed.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time")z
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 2 +-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 21501d565327..b416b394b641 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -766,7 +766,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
 	}
 
 	if (bdb->version >= 226) {
-		u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
+		u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
 
 		wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
 		switch (wakeup_time) {
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 93f5c9d204d6..09cd37fb0b1c 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -481,13 +481,13 @@ struct psr_table {
 	/* TP wake up time in multiple of 100 */
 	u16 tp1_wakeup_time;
 	u16 tp2_tp3_wakeup_time;
-
-	/* PSR2 TP2/TP3 wakeup time for 16 panels */
-	u32 psr2_tp2_tp3_wakeup_time;
 } __packed;
 
 struct bdb_psr {
 	struct psr_table psr_table[16];
+
+	/* PSR2 TP2/TP3 wakeup time for 16 panels */
+	u32 psr2_tp2_tp3_wakeup_time;
 } __packed;
 
 /*
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section
  2019-07-16 22:03 [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section Dhinakaran Pandiyan
  2019-07-16 22:10 ` Pandiyan, Dhinakaran
@ 2019-07-17 11:35 ` Ville Syrjälä
  2019-07-17 23:45   ` Pandiyan, Dhinakaran
  2019-07-17 19:34 ` François Guerraz
  2019-07-17 19:36 ` François Guerraz
  3 siblings, 1 reply; 9+ messages in thread
From: Ville Syrjälä @ 2019-07-17 11:35 UTC (permalink / raw)
  To: Dhinakaran Pandiyan; +Cc: intel-gfx

On Tue, Jul 16, 2019 at 03:03:21PM -0700, Dhinakaran Pandiyan wrote:
> A single 32-bit PSR2 training pattern field follows the sixteen element
> array of PSR table entries in the VBT spec. But, we incorrectly define
> this PSR2 field for each of the PSR table entries. As a result, the PSR1
> training pattern duration for any panel_type != 0 will be parsed
> incorrectly. Secondly, PSR2 training pattern durations for VBTs with bdb
> version >= 226 will also be wrong.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time")
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Please sync the igt copy after landing this.

> ---
>  drivers/gpu/drm/i915/display/intel_bios.c     | 2 +-
>  drivers/gpu/drm/i915/display/intel_vbt_defs.h | 6 +++---
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 21501d565327..b416b394b641 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -766,7 +766,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
>  	}
>  
>  	if (bdb->version >= 226) {
> -		u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
> +		u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
>  
>  		wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
>  		switch (wakeup_time) {
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 93f5c9d204d6..09cd37fb0b1c 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -481,13 +481,13 @@ struct psr_table {
>  	/* TP wake up time in multiple of 100 */
>  	u16 tp1_wakeup_time;
>  	u16 tp2_tp3_wakeup_time;
> -
> -	/* PSR2 TP2/TP3 wakeup time for 16 panels */
> -	u32 psr2_tp2_tp3_wakeup_time;
>  } __packed;
>  
>  struct bdb_psr {
>  	struct psr_table psr_table[16];
> +
> +	/* PSR2 TP2/TP3 wakeup time for 16 panels */
> +	u32 psr2_tp2_tp3_wakeup_time;
>  } __packed;
>  
>  /*
> -- 
> 2.17.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section
  2019-07-16 22:10 ` Pandiyan, Dhinakaran
@ 2019-07-17 16:41   ` Souza, Jose
  2019-07-17 16:56     ` Rodrigo Vivi
  2019-07-17 19:49   ` François Guerraz
  1 sibling, 1 reply; 9+ messages in thread
From: Souza, Jose @ 2019-07-17 16:41 UTC (permalink / raw)
  To: intel-gfx, Pandiyan, Dhinakaran

On Tue, 2019-07-16 at 15:10 -0700, Pandiyan, Dhinakaran wrote:
> On Tue, 2019-07-16 at 15:03 -0700, Dhinakaran Pandiyan wrote:
> > A single 32-bit PSR2 training pattern field follows the sixteen
> > element
> > array of PSR table entries in the VBT spec. But, we incorrectly
> > define
> > this PSR2 field for each of the PSR table entries. As a result, the
> > PSR1
> > training pattern duration for any panel_type != 0 will be parsed
> > incorrectly. Secondly, PSR2 training pattern durations for VBTs
> > with bdb
> > version >= 226 will also be wrong.
> 
> This was reported and bisected by 
> Aliaksei Urbanski here - 
> https://bugzilla.kernel.org/show_bug.cgi?id=204183
> 
> I'll add Bugzilla after the fix is confirmed.
> 

Oohh it makes sense, thanks for spotting it.

And 2 users reported that it works:
https://bugzilla.kernel.org/show_bug.cgi?id=204183
https://bugs.freedesktop.org/show_bug.cgi?id=111088

Can you also CC kernel stable so the fix is cherry-picked?

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>


> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field with
> PSR2 TP2/3 wakeup time")z
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bios.c     | 2 +-
>  drivers/gpu/drm/i915/display/intel_vbt_defs.h | 6 +++---
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 21501d565327..b416b394b641 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -766,7 +766,7 @@ parse_psr(struct drm_i915_private *dev_priv,
> const struct bdb_header *bdb)
>  	}
>  
>  	if (bdb->version >= 226) {
> -		u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
> +		u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
>  
>  		wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
>  		switch (wakeup_time) {
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 93f5c9d204d6..09cd37fb0b1c 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -481,13 +481,13 @@ struct psr_table {
>  	/* TP wake up time in multiple of 100 */
>  	u16 tp1_wakeup_time;
>  	u16 tp2_tp3_wakeup_time;
> -
> -	/* PSR2 TP2/TP3 wakeup time for 16 panels */
> -	u32 psr2_tp2_tp3_wakeup_time;
>  } __packed;
>  
>  struct bdb_psr {
>  	struct psr_table psr_table[16];
> +
> +	/* PSR2 TP2/TP3 wakeup time for 16 panels */
> +	u32 psr2_tp2_tp3_wakeup_time;
>  } __packed;
>  
>  /*
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section
  2019-07-17 16:41   ` Souza, Jose
@ 2019-07-17 16:56     ` Rodrigo Vivi
  0 siblings, 0 replies; 9+ messages in thread
From: Rodrigo Vivi @ 2019-07-17 16:56 UTC (permalink / raw)
  To: Souza, Jose; +Cc: intel-gfx, Pandiyan, Dhinakaran

On Wed, Jul 17, 2019 at 09:41:13AM -0700, Souza, Jose wrote:
> On Tue, 2019-07-16 at 15:10 -0700, Pandiyan, Dhinakaran wrote:
> > On Tue, 2019-07-16 at 15:03 -0700, Dhinakaran Pandiyan wrote:
> > > A single 32-bit PSR2 training pattern field follows the sixteen
> > > element
> > > array of PSR table entries in the VBT spec. But, we incorrectly
> > > define
> > > this PSR2 field for each of the PSR table entries. As a result, the
> > > PSR1
> > > training pattern duration for any panel_type != 0 will be parsed
> > > incorrectly. Secondly, PSR2 training pattern durations for VBTs
> > > with bdb
> > > version >= 226 will also be wrong.
> > 
> > This was reported and bisected by 
> > Aliaksei Urbanski here - 
> > https://bugzilla.kernel.org/show_bug.cgi?id=204183
> > 
> > I'll add Bugzilla after the fix is confirmed.
> > 
> 
> Oohh it makes sense, thanks for spotting it.
> 
> And 2 users reported that it works:
> https://bugzilla.kernel.org/show_bug.cgi?id=204183
> https://bugs.freedesktop.org/show_bug.cgi?id=111088

Please add this before merging:

Reference: https://bugzilla.kernel.org/show_bug.cgi?id=204183
Reference: https://bugs.freedesktop.org/show_bug.cgi?id=111088

> 
> Can you also CC kernel stable so the fix is cherry-picked?

and this:

Cc: stable@vger.kernel.org #v5.2

> 
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> 
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field with
> > PSR2 TP2/3 wakeup time")z
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_bios.c     | 2 +-
> >  drivers/gpu/drm/i915/display/intel_vbt_defs.h | 6 +++---
> >  2 files changed, 4 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> > b/drivers/gpu/drm/i915/display/intel_bios.c
> > index 21501d565327..b416b394b641 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > @@ -766,7 +766,7 @@ parse_psr(struct drm_i915_private *dev_priv,
> > const struct bdb_header *bdb)
> >  	}
> >  
> >  	if (bdb->version >= 226) {
> > -		u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
> > +		u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
> >  
> >  		wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
> >  		switch (wakeup_time) {
> > diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > index 93f5c9d204d6..09cd37fb0b1c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > @@ -481,13 +481,13 @@ struct psr_table {
> >  	/* TP wake up time in multiple of 100 */
> >  	u16 tp1_wakeup_time;
> >  	u16 tp2_tp3_wakeup_time;
> > -
> > -	/* PSR2 TP2/TP3 wakeup time for 16 panels */
> > -	u32 psr2_tp2_tp3_wakeup_time;
> >  } __packed;
> >  
> >  struct bdb_psr {
> >  	struct psr_table psr_table[16];
> > +
> > +	/* PSR2 TP2/TP3 wakeup time for 16 panels */
> > +	u32 psr2_tp2_tp3_wakeup_time;
> >  } __packed;
> >  
> >  /*
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: drm/i915/vbt: Fix VBT parsing for the PSR section
  2019-07-16 22:03 [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section Dhinakaran Pandiyan
  2019-07-16 22:10 ` Pandiyan, Dhinakaran
  2019-07-17 11:35 ` [PATCH] " Ville Syrjälä
@ 2019-07-17 19:34 ` François Guerraz
  2019-07-17 19:36 ` François Guerraz
  3 siblings, 0 replies; 9+ messages in thread
From: François Guerraz @ 2019-07-17 19:34 UTC (permalink / raw)
  To: intel-gfx

Tested-by: François Guerraz <kubrick@fgv6.net>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: drm/i915/vbt: Fix VBT parsing for the PSR section
  2019-07-16 22:03 [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section Dhinakaran Pandiyan
                   ` (2 preceding siblings ...)
  2019-07-17 19:34 ` François Guerraz
@ 2019-07-17 19:36 ` François Guerraz
  3 siblings, 0 replies; 9+ messages in thread
From: François Guerraz @ 2019-07-17 19:36 UTC (permalink / raw)
  To: intel-gfx

Tested-by: François Guerraz <kubrick@fgv6.net>

On Dell XPS 9350

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: drm/i915/vbt: Fix VBT parsing for the PSR section
  2019-07-16 22:10 ` Pandiyan, Dhinakaran
  2019-07-17 16:41   ` Souza, Jose
@ 2019-07-17 19:49   ` François Guerraz
  1 sibling, 0 replies; 9+ messages in thread
From: François Guerraz @ 2019-07-17 19:49 UTC (permalink / raw)
  To: Pandiyan, Dhinakaran, intel-gfx

Tested-by: François Guerraz <kubrick@fgv6.net>

On Dell XPS 9350

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section
  2019-07-17 11:35 ` [PATCH] " Ville Syrjälä
@ 2019-07-17 23:45   ` Pandiyan, Dhinakaran
  0 siblings, 0 replies; 9+ messages in thread
From: Pandiyan, Dhinakaran @ 2019-07-17 23:45 UTC (permalink / raw)
  To: ville.syrjala; +Cc: intel-gfx

On Wed, 2019-07-17 at 14:35 +0300, Ville Syrjälä wrote:
> On Tue, Jul 16, 2019 at 03:03:21PM -0700, Dhinakaran Pandiyan wrote:
> > A single 32-bit PSR2 training pattern field follows the sixteen element
> > array of PSR table entries in the VBT spec. But, we incorrectly define
> > this PSR2 field for each of the PSR table entries. As a result, the PSR1
> > training pattern duration for any panel_type != 0 will be parsed
> > incorrectly. Secondly, PSR2 training pattern durations for VBTs with bdb
> > version >= 226 will also be wrong.
> > 
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time")
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Please sync the igt copy after landing this.

Will do, thanks!

-DK
> 
> > ---
> >  drivers/gpu/drm/i915/display/intel_bios.c     | 2 +-
> >  drivers/gpu/drm/i915/display/intel_vbt_defs.h | 6 +++---
> >  2 files changed, 4 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> > b/drivers/gpu/drm/i915/display/intel_bios.c
> > index 21501d565327..b416b394b641 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > @@ -766,7 +766,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
> >  	}
> >  
> >  	if (bdb->version >= 226) {
> > -		u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
> > +		u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
> >  
> >  		wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
> >  		switch (wakeup_time) {
> > diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > index 93f5c9d204d6..09cd37fb0b1c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > @@ -481,13 +481,13 @@ struct psr_table {
> >  	/* TP wake up time in multiple of 100 */
> >  	u16 tp1_wakeup_time;
> >  	u16 tp2_tp3_wakeup_time;
> > -
> > -	/* PSR2 TP2/TP3 wakeup time for 16 panels */
> > -	u32 psr2_tp2_tp3_wakeup_time;
> >  } __packed;
> >  
> >  struct bdb_psr {
> >  	struct psr_table psr_table[16];
> > +
> > +	/* PSR2 TP2/TP3 wakeup time for 16 panels */
> > +	u32 psr2_tp2_tp3_wakeup_time;
> >  } __packed;
> >  
> >  /*
> > -- 
> > 2.17.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
end of thread, other threads:[~2019-07-17 23:45 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-07-16 22:03 [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section Dhinakaran Pandiyan
2019-07-16 22:10 ` Pandiyan, Dhinakaran
2019-07-17 16:41   ` Souza, Jose
2019-07-17 16:56     ` Rodrigo Vivi
2019-07-17 19:49   ` François Guerraz
2019-07-17 11:35 ` [PATCH] " Ville Syrjälä
2019-07-17 23:45   ` Pandiyan, Dhinakaran
2019-07-17 19:34 ` François Guerraz
2019-07-17 19:36 ` François Guerraz

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.