[PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section

[PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section

[Dhinakaran Pandiyan]

A single 32-bit PSR2 training pattern field follows the sixteen element
array of PSR table entries in the VBT spec. But, we incorrectly define
this PSR2 field for each of the PSR table entries. As a result, the PSR1
training pattern duration for any panel_type != 0 will be parsed
incorrectly. Secondly, PSR2 training pattern durations for VBTs with bdb
version >= 226 will also be wrong.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time")
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 2 +-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 21501d565327..b416b394b641 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -766,7 +766,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
 	}
 
 	if (bdb->version >= 226) {
-		u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
+		u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
 
 		wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
 		switch (wakeup_time) {
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 93f5c9d204d6..09cd37fb0b1c 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -481,13 +481,13 @@ struct psr_table {
 	/* TP wake up time in multiple of 100 */
 	u16 tp1_wakeup_time;
 	u16 tp2_tp3_wakeup_time;
-
-	/* PSR2 TP2/TP3 wakeup time for 16 panels */
-	u32 psr2_tp2_tp3_wakeup_time;
 } __packed;
 
 struct bdb_psr {
 	struct psr_table psr_table[16];
+
+	/* PSR2 TP2/TP3 wakeup time for 16 panels */
+	u32 psr2_tp2_tp3_wakeup_time;
 } __packed;
 
 /*
-- 
2.17.1

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Re: [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section

[Pandiyan, Dhinakaran]

On Tue, 2019-07-16 at 15:03 -0700, Dhinakaran Pandiyan wrote:
> A single 32-bit PSR2 training pattern field follows the sixteen element
> array of PSR table entries in the VBT spec. But, we incorrectly define
> this PSR2 field for each of the PSR table entries. As a result, the PSR1
> training pattern duration for any panel_type != 0 will be parsed
> incorrectly. Secondly, PSR2 training pattern durations for VBTs with bdb
> version >= 226 will also be wrong.

This was reported and bisected by 
Aliaksei Urbanski here - https://bugzilla.kernel.org/show_bug.cgi?id=204183

I'll add Bugzilla after the fix is confirmed.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time")z
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 2 +-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 21501d565327..b416b394b641 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -766,7 +766,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
 	}
 
 	if (bdb->version >= 226) {
-		u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
+		u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
 
 		wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
 		switch (wakeup_time) {
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 93f5c9d204d6..09cd37fb0b1c 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -481,13 +481,13 @@ struct psr_table {
 	/* TP wake up time in multiple of 100 */
 	u16 tp1_wakeup_time;
 	u16 tp2_tp3_wakeup_time;
-
-	/* PSR2 TP2/TP3 wakeup time for 16 panels */
-	u32 psr2_tp2_tp3_wakeup_time;
 } __packed;
 
 struct bdb_psr {
 	struct psr_table psr_table[16];
+
+	/* PSR2 TP2/TP3 wakeup time for 16 panels */
+	u32 psr2_tp2_tp3_wakeup_time;
 } __packed;
 
 /*
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Re: [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section

[Ville Syrjälä]

On Tue, Jul 16, 2019 at 03:03:21PM -0700, Dhinakaran Pandiyan wrote:
> A single 32-bit PSR2 training pattern field follows the sixteen element
> array of PSR table entries in the VBT spec. But, we incorrectly define
> this PSR2 field for each of the PSR table entries. As a result, the PSR1
> training pattern duration for any panel_type != 0 will be parsed
> incorrectly. Secondly, PSR2 training pattern durations for VBTs with bdb
> version >= 226 will also be wrong.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time")
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Please sync the igt copy after landing this.

> ---
>  drivers/gpu/drm/i915/display/intel_bios.c     | 2 +-
>  drivers/gpu/drm/i915/display/intel_vbt_defs.h | 6 +++---
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 21501d565327..b416b394b641 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -766,7 +766,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
>  	}
>  
>  	if (bdb->version >= 226) {
> -		u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
> +		u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
>  
>  		wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
>  		switch (wakeup_time) {
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 93f5c9d204d6..09cd37fb0b1c 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -481,13 +481,13 @@ struct psr_table {
>  	/* TP wake up time in multiple of 100 */
>  	u16 tp1_wakeup_time;
>  	u16 tp2_tp3_wakeup_time;
> -
> -	/* PSR2 TP2/TP3 wakeup time for 16 panels */
> -	u32 psr2_tp2_tp3_wakeup_time;
>  } __packed;
>  
>  struct bdb_psr {
>  	struct psr_table psr_table[16];
> +
> +	/* PSR2 TP2/TP3 wakeup time for 16 panels */
> +	u32 psr2_tp2_tp3_wakeup_time;
>  } __packed;
>  
>  /*
> -- 
> 2.17.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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Re: [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section

[Souza, Jose]

On Tue, 2019-07-16 at 15:10 -0700, Pandiyan, Dhinakaran wrote:
> On Tue, 2019-07-16 at 15:03 -0700, Dhinakaran Pandiyan wrote:
> > A single 32-bit PSR2 training pattern field follows the sixteen
> > element
> > array of PSR table entries in the VBT spec. But, we incorrectly
> > define
> > this PSR2 field for each of the PSR table entries. As a result, the
> > PSR1
> > training pattern duration for any panel_type != 0 will be parsed
> > incorrectly. Secondly, PSR2 training pattern durations for VBTs
> > with bdb
> > version >= 226 will also be wrong.
> 
> This was reported and bisected by 
> Aliaksei Urbanski here - 
> https://bugzilla.kernel.org/show_bug.cgi?id=204183
> 
> I'll add Bugzilla after the fix is confirmed.
> 

Oohh it makes sense, thanks for spotting it.

And 2 users reported that it works:
https://bugzilla.kernel.org/show_bug.cgi?id=204183
https://bugs.freedesktop.org/show_bug.cgi?id=111088

Can you also CC kernel stable so the fix is cherry-picked?

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>


> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field with
> PSR2 TP2/3 wakeup time")z
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bios.c     | 2 +-
>  drivers/gpu/drm/i915/display/intel_vbt_defs.h | 6 +++---
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 21501d565327..b416b394b641 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -766,7 +766,7 @@ parse_psr(struct drm_i915_private *dev_priv,
> const struct bdb_header *bdb)
>  	}
>  
>  	if (bdb->version >= 226) {
> -		u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
> +		u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
>  
>  		wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
>  		switch (wakeup_time) {
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 93f5c9d204d6..09cd37fb0b1c 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -481,13 +481,13 @@ struct psr_table {
>  	/* TP wake up time in multiple of 100 */
>  	u16 tp1_wakeup_time;
>  	u16 tp2_tp3_wakeup_time;
> -
> -	/* PSR2 TP2/TP3 wakeup time for 16 panels */
> -	u32 psr2_tp2_tp3_wakeup_time;
>  } __packed;
>  
>  struct bdb_psr {
>  	struct psr_table psr_table[16];
> +
> +	/* PSR2 TP2/TP3 wakeup time for 16 panels */
> +	u32 psr2_tp2_tp3_wakeup_time;
>  } __packed;
>  
>  /*
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Re: [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section

[Rodrigo Vivi]

On Wed, Jul 17, 2019 at 09:41:13AM -0700, Souza, Jose wrote:
> On Tue, 2019-07-16 at 15:10 -0700, Pandiyan, Dhinakaran wrote:
> > On Tue, 2019-07-16 at 15:03 -0700, Dhinakaran Pandiyan wrote:
> > > A single 32-bit PSR2 training pattern field follows the sixteen
> > > element
> > > array of PSR table entries in the VBT spec. But, we incorrectly
> > > define
> > > this PSR2 field for each of the PSR table entries. As a result, the
> > > PSR1
> > > training pattern duration for any panel_type != 0 will be parsed
> > > incorrectly. Secondly, PSR2 training pattern durations for VBTs
> > > with bdb
> > > version >= 226 will also be wrong.
> > 
> > This was reported and bisected by 
> > Aliaksei Urbanski here - 
> > https://bugzilla.kernel.org/show_bug.cgi?id=204183
> > 
> > I'll add Bugzilla after the fix is confirmed.
> > 
> 
> Oohh it makes sense, thanks for spotting it.
> 
> And 2 users reported that it works:
> https://bugzilla.kernel.org/show_bug.cgi?id=204183
> https://bugs.freedesktop.org/show_bug.cgi?id=111088

Please add this before merging:

Reference: https://bugzilla.kernel.org/show_bug.cgi?id=204183
Reference: https://bugs.freedesktop.org/show_bug.cgi?id=111088

> 
> Can you also CC kernel stable so the fix is cherry-picked?

and this:

Cc: stable@vger.kernel.org #v5.2

> 
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> 
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field with
> > PSR2 TP2/3 wakeup time")z
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_bios.c     | 2 +-
> >  drivers/gpu/drm/i915/display/intel_vbt_defs.h | 6 +++---
> >  2 files changed, 4 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> > b/drivers/gpu/drm/i915/display/intel_bios.c
> > index 21501d565327..b416b394b641 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > @@ -766,7 +766,7 @@ parse_psr(struct drm_i915_private *dev_priv,
> > const struct bdb_header *bdb)
> >  	}
> >  
> >  	if (bdb->version >= 226) {
> > -		u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
> > +		u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
> >  
> >  		wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
> >  		switch (wakeup_time) {
> > diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > index 93f5c9d204d6..09cd37fb0b1c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > @@ -481,13 +481,13 @@ struct psr_table {
> >  	/* TP wake up time in multiple of 100 */
> >  	u16 tp1_wakeup_time;
> >  	u16 tp2_tp3_wakeup_time;
> > -
> > -	/* PSR2 TP2/TP3 wakeup time for 16 panels */
> > -	u32 psr2_tp2_tp3_wakeup_time;
> >  } __packed;
> >  
> >  struct bdb_psr {
> >  	struct psr_table psr_table[16];
> > +
> > +	/* PSR2 TP2/TP3 wakeup time for 16 panels */
> > +	u32 psr2_tp2_tp3_wakeup_time;
> >  } __packed;
> >  
> >  /*
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Re: drm/i915/vbt: Fix VBT parsing for the PSR section

[François Guerraz]

Tested-by: François Guerraz <kubrick@fgv6.net>

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Re: drm/i915/vbt: Fix VBT parsing for the PSR section

[François Guerraz]

Tested-by: François Guerraz <kubrick@fgv6.net>

On Dell XPS 9350

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Re: drm/i915/vbt: Fix VBT parsing for the PSR section

[François Guerraz]

Tested-by: François Guerraz <kubrick@fgv6.net>

On Dell XPS 9350

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Re: [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section

[Pandiyan, Dhinakaran]

On Wed, 2019-07-17 at 14:35 +0300, Ville Syrjälä wrote:
> On Tue, Jul 16, 2019 at 03:03:21PM -0700, Dhinakaran Pandiyan wrote:
> > A single 32-bit PSR2 training pattern field follows the sixteen element
> > array of PSR table entries in the VBT spec. But, we incorrectly define
> > this PSR2 field for each of the PSR table entries. As a result, the PSR1
> > training pattern duration for any panel_type != 0 will be parsed
> > incorrectly. Secondly, PSR2 training pattern durations for VBTs with bdb
> > version >= 226 will also be wrong.
> > 
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time")
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Please sync the igt copy after landing this.

Will do, thanks!

-DK
> 
> > ---
> >  drivers/gpu/drm/i915/display/intel_bios.c     | 2 +-
> >  drivers/gpu/drm/i915/display/intel_vbt_defs.h | 6 +++---
> >  2 files changed, 4 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> > b/drivers/gpu/drm/i915/display/intel_bios.c
> > index 21501d565327..b416b394b641 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > @@ -766,7 +766,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
> >  	}
> >  
> >  	if (bdb->version >= 226) {
> > -		u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
> > +		u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
> >  
> >  		wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
> >  		switch (wakeup_time) {
> > diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > index 93f5c9d204d6..09cd37fb0b1c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > @@ -481,13 +481,13 @@ struct psr_table {
> >  	/* TP wake up time in multiple of 100 */
> >  	u16 tp1_wakeup_time;
> >  	u16 tp2_tp3_wakeup_time;
> > -
> > -	/* PSR2 TP2/TP3 wakeup time for 16 panels */
> > -	u32 psr2_tp2_tp3_wakeup_time;
> >  } __packed;
> >  
> >  struct bdb_psr {
> >  	struct psr_table psr_table[16];
> > +
> > +	/* PSR2 TP2/TP3 wakeup time for 16 panels */
> > +	u32 psr2_tp2_tp3_wakeup_time;
> >  } __packed;
> >  
> >  /*
> > -- 
> > 2.17.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
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Re: [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section

[Greg KH]

On Tue, Aug 06, 2019 at 10:44:33AM +0300, Jani Nikula wrote:
> On Mon, 05 Aug 2019, José Roberto de Souza <jose.souza@intel.com> wrote:
> > From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> >
> 
> commit 6d61f716a01ec0e134de38ae97e71d6fec5a6ff6 upstream.

Now queued up, thanks.

greg k-h

Re: [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section

[gregkh]

On Wed, Aug 07, 2019 at 07:37:13PM +0000, Souza, Jose wrote:
> Hi Greg
> 
> Anything is missing to have this merged for 5.2.8?

Patience :)

The queue is long and you only sent this 2 days ago...

Re: [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section

[Souza, Jose]

Hi Greg

Anything is missing to have this merged for 5.2.8?


On Tue, 2019-08-06 at 10:44 +0300, Jani Nikula wrote:
> On Mon, 05 Aug 2019, José Roberto de Souza <jose.souza@intel.com>
> wrote:
> > From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > 
> 
> commit 6d61f716a01ec0e134de38ae97e71d6fec5a6ff6 upstream.
> 
> > A single 32-bit PSR2 training pattern field follows the sixteen
> > element
> > array of PSR table entries in the VBT spec. But, we incorrectly
> > define
> > this PSR2 field for each of the PSR table entries. As a result, the
> > PSR1
> > training pattern duration for any panel_type != 0 will be parsed
> > incorrectly. Secondly, PSR2 training pattern durations for VBTs
> > with bdb
> > version >= 226 will also be wrong.
> > 
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Cc: stable@vger.kernel.org
> > Cc: stable@vger.kernel.org #v5.2
> > Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field
> > with PSR2 TP2/3 wakeup time")
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111088
> > Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204183
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> > Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Tested-by: François Guerraz <kubrick@fgv6.net>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Link: 
> > https://patchwork.freedesktop.org/patch/msgid/20190717223451.2595-1-dhinakaran.pandiyan@intel.com
> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> > (cherry picked from commit
> > 6d61f716a01ec0e134de38ae97e71d6fec5a6ff6)
> > ---
> > 
> > Sending it for Dhinakaran, let me know if something is wrong.
> > 
> >  drivers/gpu/drm/i915/intel_bios.c     | 2 +-
> >  drivers/gpu/drm/i915/intel_vbt_defs.h | 6 +++---
> >  2 files changed, 4 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_bios.c
> > b/drivers/gpu/drm/i915/intel_bios.c
> > index 1dc8d03ff127..ee6fa75d65a2 100644
> > --- a/drivers/gpu/drm/i915/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/intel_bios.c
> > @@ -762,7 +762,7 @@ parse_psr(struct drm_i915_private *dev_priv,
> > const struct bdb_header *bdb)
> >  	}
> >  
> >  	if (bdb->version >= 226) {
> > -		u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
> > +		u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
> >  
> >  		wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
> >  		switch (wakeup_time) {
> > diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h
> > b/drivers/gpu/drm/i915/intel_vbt_defs.h
> > index fdbbb9a53804..796c070bbe6f 100644
> > --- a/drivers/gpu/drm/i915/intel_vbt_defs.h
> > +++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
> > @@ -772,13 +772,13 @@ struct psr_table {
> >  	/* TP wake up time in multiple of 100 */
> >  	u16 tp1_wakeup_time;
> >  	u16 tp2_tp3_wakeup_time;
> > -
> > -	/* PSR2 TP2/TP3 wakeup time for 16 panels */
> > -	u32 psr2_tp2_tp3_wakeup_time;
> >  } __packed;
> >  
> >  struct bdb_psr {
> >  	struct psr_table psr_table[16];
> > +
> > +	/* PSR2 TP2/TP3 wakeup time for 16 panels */
> > +	u32 psr2_tp2_tp3_wakeup_time;
> >  } __packed;
> >  
> >  /*

Re: [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section

[Jani Nikula]

On Mon, 05 Aug 2019, José Roberto de Souza <jose.souza@intel.com> wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>

commit 6d61f716a01ec0e134de38ae97e71d6fec5a6ff6 upstream.

> A single 32-bit PSR2 training pattern field follows the sixteen element
> array of PSR table entries in the VBT spec. But, we incorrectly define
> this PSR2 field for each of the PSR table entries. As a result, the PSR1
> training pattern duration for any panel_type != 0 will be parsed
> incorrectly. Secondly, PSR2 training pattern durations for VBTs with bdb
> version >= 226 will also be wrong.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: stable@vger.kernel.org
> Cc: stable@vger.kernel.org #v5.2
> Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111088
> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204183
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Tested-by: François Guerraz <kubrick@fgv6.net>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Link: https://patchwork.freedesktop.org/patch/msgid/20190717223451.2595-1-dhinakaran.pandiyan@intel.com
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> (cherry picked from commit 6d61f716a01ec0e134de38ae97e71d6fec5a6ff6)
> ---
>
> Sending it for Dhinakaran, let me know if something is wrong.
>
>  drivers/gpu/drm/i915/intel_bios.c     | 2 +-
>  drivers/gpu/drm/i915/intel_vbt_defs.h | 6 +++---
>  2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 1dc8d03ff127..ee6fa75d65a2 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -762,7 +762,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
>  	}
>  
>  	if (bdb->version >= 226) {
> -		u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
> +		u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
>  
>  		wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
>  		switch (wakeup_time) {
> diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
> index fdbbb9a53804..796c070bbe6f 100644
> --- a/drivers/gpu/drm/i915/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
> @@ -772,13 +772,13 @@ struct psr_table {
>  	/* TP wake up time in multiple of 100 */
>  	u16 tp1_wakeup_time;
>  	u16 tp2_tp3_wakeup_time;
> -
> -	/* PSR2 TP2/TP3 wakeup time for 16 panels */
> -	u32 psr2_tp2_tp3_wakeup_time;
>  } __packed;
>  
>  struct bdb_psr {
>  	struct psr_table psr_table[16];
> +
> +	/* PSR2 TP2/TP3 wakeup time for 16 panels */
> +	u32 psr2_tp2_tp3_wakeup_time;
>  } __packed;
>  
>  /*

-- 
Jani Nikula, Intel Open Source Graphics Center

[PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section

[José Roberto de Souza]

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

A single 32-bit PSR2 training pattern field follows the sixteen element
array of PSR table entries in the VBT spec. But, we incorrectly define
this PSR2 field for each of the PSR table entries. As a result, the PSR1
training pattern duration for any panel_type != 0 will be parsed
incorrectly. Secondly, PSR2 training pattern durations for VBTs with bdb
version >= 226 will also be wrong.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: stable@vger.kernel.org
Cc: stable@vger.kernel.org #v5.2
Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111088
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204183
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Tested-by: François Guerraz <kubrick@fgv6.net>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190717223451.2595-1-dhinakaran.pandiyan@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
(cherry picked from commit 6d61f716a01ec0e134de38ae97e71d6fec5a6ff6)
---

Sending it for Dhinakaran, let me know if something is wrong.

 drivers/gpu/drm/i915/intel_bios.c     | 2 +-
 drivers/gpu/drm/i915/intel_vbt_defs.h | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 1dc8d03ff127..ee6fa75d65a2 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -762,7 +762,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
 	}
 
 	if (bdb->version >= 226) {
-		u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
+		u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
 
 		wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
 		switch (wakeup_time) {
diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
index fdbbb9a53804..796c070bbe6f 100644
--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
@@ -772,13 +772,13 @@ struct psr_table {
 	/* TP wake up time in multiple of 100 */
 	u16 tp1_wakeup_time;
 	u16 tp2_tp3_wakeup_time;
-
-	/* PSR2 TP2/TP3 wakeup time for 16 panels */
-	u32 psr2_tp2_tp3_wakeup_time;
 } __packed;
 
 struct bdb_psr {
 	struct psr_table psr_table[16];
+
+	/* PSR2 TP2/TP3 wakeup time for 16 panels */
+	u32 psr2_tp2_tp3_wakeup_time;
 } __packed;
 
 /*
-- 
2.22.0

Re: [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section

[Vivi, Rodrigo]

> On Jul 30, 2019, at 2:48 PM, Sasha Levin <sashal@kernel.org> wrote:
> 
> On Tue, Jul 30, 2019 at 01:42:45PM -0700, Rodrigo Vivi wrote:
>> Hi Sasha,
> 
> Hello!
> 
>> On Thu, Jul 18, 2019 at 5:45 PM Sasha Levin <sashal@kernel.org> wrote:
>>> 
>>> Hi,
>>> 
>>> [This is an automated email]
>> 
>> Where did you get this patch from? Since stable needs patches merged
> 
> This bot grabs them from various mailing lists.
> 
>> on Linus tree,
>> shouldn't your scripts run to try backporting only patches from there?
> 
> There's a note a few lines down that says:
> 
>   "NOTE: The patch will not be queued to stable trees until it is upstream."
> 
> Otherwise, no, there's no rule that says we can't look at patches before
> they are upstream. We can't queue them up, but we sure can poke them.
> 
> The reasoning behind this is that it's easier to get replies (and
> backports) from folks who are actively working on the patch now,


This is a very good reason indeed...

> rather
> than a few weeks later when Greg sends his "FAILED:" mails and gets
> ignored because said folks have moved on.

however this could potentially cause extra work and confusion like we can see on this
thread where the developer immediately responded to your email and sent the
backported patch to the stable mailing list.

Maybe it is just because we are used to Greg's failed to apply email or maybe
it was just a matter of education... 

But I wonder if there isn't something that could be improved on the automated
message here. Some message clearly stating:

- No action required at this point
- you can work to prepare the backport in advance
-  don't send it to stable before requested by Greg

Anyway, just few ideas. I just reached you to understand the flow and I'm already
happy to understand what happened here.

Thanks a lot for that,
Rodrigo.


> 
> --
> Thanks,
> Sasha
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section

[Sasha Levin]

On Tue, Jul 30, 2019 at 01:42:45PM -0700, Rodrigo Vivi wrote:
>Hi Sasha,

Hello!

>On Thu, Jul 18, 2019 at 5:45 PM Sasha Levin <sashal@kernel.org> wrote:
>>
>> Hi,
>>
>> [This is an automated email]
>
>Where did you get this patch from? Since stable needs patches merged

This bot grabs them from various mailing lists.

>on Linus tree,
>shouldn't your scripts run to try backporting only patches from there?

There's a note a few lines down that says:

    "NOTE: The patch will not be queued to stable trees until it is upstream."

Otherwise, no, there's no rule that says we can't look at patches before
they are upstream. We can't queue them up, but we sure can poke them.

The reasoning behind this is that it's easier to get replies (and
backports) from folks who are actively working on the patch now, rather
than a few weeks later when Greg sends his "FAILED:" mails and gets
ignored because said folks have moved on.

--
Thanks,
Sasha
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section

[Sasha Levin]

Hi,

[This is an automated email]

This commit has been processed because it contains a "Fixes:" tag,
fixing commit: 88a0d9606aff drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time.

The bot has tested the following trees: v5.2.1.

v5.2.1: Failed to apply! Possible dependencies:
    231dcffc234f ("drm/i915/bios: add BDB block comments before definitions")
    843444ed1301 ("drm/i915/bios: sort BDB block definitions using block ID")
    f87f6599c843 ("drm/i915/bios: reserve struct bdb_ prefix for BDB blocks")


NOTE: The patch will not be queued to stable trees until it is upstream.

How should we proceed with this patch?

--
Thanks,
Sasha
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section

[Dhinakaran Pandiyan]

A single 32-bit PSR2 training pattern field follows the sixteen element
array of PSR table entries in the VBT spec. But, we incorrectly define
this PSR2 field for each of the PSR table entries. As a result, the PSR1
training pattern duration for any panel_type != 0 will be parsed
incorrectly. Secondly, PSR2 training pattern durations for VBTs with bdb
version >= 226 will also be wrong.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: stable@vger.kernel.org
Cc: stable@vger.kernel.org #v5.2
Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111088
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204183
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Tested-by: François Guerraz <kubrick@fgv6.net>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 2 +-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 21501d565327..b416b394b641 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -766,7 +766,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
 	}
 
 	if (bdb->version >= 226) {
-		u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
+		u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
 
 		wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
 		switch (wakeup_time) {
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 93f5c9d204d6..09cd37fb0b1c 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -481,13 +481,13 @@ struct psr_table {
 	/* TP wake up time in multiple of 100 */
 	u16 tp1_wakeup_time;
 	u16 tp2_tp3_wakeup_time;
-
-	/* PSR2 TP2/TP3 wakeup time for 16 panels */
-	u32 psr2_tp2_tp3_wakeup_time;
 } __packed;
 
 struct bdb_psr {
 	struct psr_table psr_table[16];
+
+	/* PSR2 TP2/TP3 wakeup time for 16 panels */
+	u32 psr2_tp2_tp3_wakeup_time;
 } __packed;
 
 /*
-- 
2.17.1

[PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section

[Dhinakaran Pandiyan]

A single 32-bit PSR2 training pattern field follows the sixteen element
array of PSR table entries in the VBT spec. But, we incorrectly define
this PSR2 field for each of the PSR table entries. As a result, the PSR1
training pattern duration for any panel_type != 0 will be parsed
incorrectly. Secondly, PSR2 training pattern durations for VBTs with bdb
version >= 226 will also be wrong.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: stable@vger.kernel.org
Cc: stable@vger.kernel.org #v5.2
Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111088
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204183
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Tested-by: François Guerraz <kubrick@fgv6.net>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 2 +-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 21501d565327..b416b394b641 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -766,7 +766,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
 	}
 
 	if (bdb->version >= 226) {
-		u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
+		u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
 
 		wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
 		switch (wakeup_time) {
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 93f5c9d204d6..09cd37fb0b1c 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -481,13 +481,13 @@ struct psr_table {
 	/* TP wake up time in multiple of 100 */
 	u16 tp1_wakeup_time;
 	u16 tp2_tp3_wakeup_time;
-
-	/* PSR2 TP2/TP3 wakeup time for 16 panels */
-	u32 psr2_tp2_tp3_wakeup_time;
 } __packed;
 
 struct bdb_psr {
 	struct psr_table psr_table[16];
+
+	/* PSR2 TP2/TP3 wakeup time for 16 panels */
+	u32 psr2_tp2_tp3_wakeup_time;
 } __packed;
 
 /*
-- 
2.17.1

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