[igt-dev] [PATCH i-g-t 0/3] intel/gem: test the partial whitelisting of the INSTPM register

[igt-dev] [PATCH i-g-t 0/3] intel/gem: test the partial whitelisting of the INSTPM register

[Lionel Landwerlin]

Hi,

On Haswell, We would like to support the same feature that is already
supported on Gen8 of configuring the RCS to turn some
3DPRIMITIVE/GPU_WALKER into NOOPs.

This series verify the changes made to the kernel command parser.

Cheers,

Lionel Landwerlin (3):
  tests/gem_exec_parse: add a register write mask
  tests/gem_exec_parse: verify that we allow LRI on INSTPM
  test/gem_ctx_isolation: verify INSTPM isolation on Gen7+

 tests/gem_ctx_isolation.c |  1 +
 tests/gem_exec_parse.c    | 33 ++++++++++++++++++++++++++-------
 2 files changed, 27 insertions(+), 7 deletions(-)

--
2.17.0
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[igt-dev] [PATCH i-g-t 1/3] tests/gem_exec_parse: add a register write mask

[Lionel Landwerlin]

Some register are masked (meaning the 16bits are dedicated to identify
which of the other 16bits have to be taken into account by the
hardware). This change adds the mask to the write but doesn't take it
into account in the value comparison assert.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 tests/gem_exec_parse.c | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index b653b1bd..c37c056e 100644
--- a/tests/gem_exec_parse.c
+++ b/tests/gem_exec_parse.c
@@ -261,6 +261,7 @@ struct test_lri {
 	const char *name; /* register name for debug info */
 	uint32_t reg; /* address to test */
 	uint32_t read_mask; /* ignore things like HW status bits */
+	uint32_t write_mask; /* mask to write the register with */
 	uint32_t init_val; /* initial identifiable value to set without LRI */
 	uint32_t test_val; /* value to attempt loading via LRI command */
 	bool whitelisted; /* expect to become NOOP / fail if not whitelisted */
@@ -273,7 +274,7 @@ test_lri(int fd, uint32_t handle, struct test_lri *test)
 	uint32_t lri[] = {
 		MI_LOAD_REGISTER_IMM,
 		test->reg,
-		test->test_val,
+		test->test_val | test->write_mask,
 		MI_BATCH_BUFFER_END,
 	};
 	int bad_lri_errno = parser_version >= 8 ? 0 : -EINVAL;
@@ -284,7 +285,8 @@ test_lri(int fd, uint32_t handle, struct test_lri *test)
 		  test->name, test->reg, test->test_val,
 		  expected_errno, expect);
 
-	intel_register_write(test->reg, test->init_val);
+	intel_register_write(test->reg,
+			     test->init_val | test->write_mask);
 
 	igt_assert_eq_u32((intel_register_read(test->reg) &
 			   test->read_mask),
@@ -498,14 +500,16 @@ igt_main
 	}
 
 	igt_subtest_group {
-#define REG(R, MSK, INI, V, OK, MIN_V) { #R, R, MSK, INI, V, OK, MIN_V }
+#define REG(R, RMSK, WMSK, INI, V, OK, MIN_V) { #R, R, RMSK, WMSK, INI, V, OK, MIN_V }
 		struct test_lri lris[] = {
 			/* dummy head pointer */
 			REG(OASTATUS2,
-			    0xffffff80, 0xdeadf000, 0xbeeff000, false, 0),
+			    0xffffff80, 0x00000000,
+			    0xdeadf000, 0xbeeff000, false, 0),
 			/* NB: [1:0] MBZ */
 			REG(SO_WRITE_OFFSET_0,
-			    0xfffffffc, 0xabcdabc0, 0xbeefbee0, true, 0),
+			    0xfffffffc, 0x00000000,
+			    0xabcdabc0, 0xbeefbee0, true, 0),
 
 			/* It's really important for us to check that
 			 * an LRI to OACONTROL doesn't result in an
@@ -521,7 +525,8 @@ igt_main
 			 * while leaving the OA unit disabled
 			 */
 			REG(OACONTROL,
-			    0xfffff000, 0xfeed0000, 0x31337000, false, 9)
+			    0xfffff000, 0x00000000,
+			    0xfeed0000, 0x31337000, false, 9),
 		};
 #undef REG
 
-- 
2.17.0

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[igt-dev] [PATCH i-g-t 2/3] tests/gem_exec_parse: verify that we allow LRI on INSTPM

[Lionel Landwerlin]

INSTPM will be used by Mesa. It's allowed by default on Gen8+.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 tests/gem_exec_parse.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index c37c056e..0818a6a5 100644
--- a/tests/gem_exec_parse.c
+++ b/tests/gem_exec_parse.c
@@ -38,6 +38,7 @@
 #define OASTATUS2 0x2368
 #define OACONTROL 0x2360
 #define SO_WRITE_OFFSET_0 0x5280
+#define INSTPM 0x20c0
 
 #define HSW_CS_GPR(n) (0x2600 + 8*(n))
 #define HSW_CS_GPR0 HSW_CS_GPR(0)
@@ -369,6 +370,7 @@ static void hsw_load_register_reg(void)
 		OACONTROL, /* filtered */
 		DERRMR, /* master only */
 		0x2038, /* RING_START: invalid */
+		INSTPM, /* filtered */
 	};
 	int fd;
 	uint32_t handle;
@@ -378,7 +380,7 @@ static void hsw_load_register_reg(void)
 	fd = drm_open_driver(DRIVER_INTEL);
 
 	igt_require(IS_HASWELL(intel_get_drm_devid(fd)));
-	igt_require(parser_version >= 7);
+	igt_require(parser_version >= 10);
 
 	handle = gem_create(fd, 4096);
 
@@ -501,6 +503,7 @@ igt_main
 
 	igt_subtest_group {
 #define REG(R, RMSK, WMSK, INI, V, OK, MIN_V) { #R, R, RMSK, WMSK, INI, V, OK, MIN_V }
+#define REGN(N, R, RMSK, WMSK, INI, V, OK, MIN_V) { N, R, RMSK, WMSK, INI, V, OK, MIN_V }
 		struct test_lri lris[] = {
 			/* dummy head pointer */
 			REG(OASTATUS2,
@@ -527,8 +530,19 @@ igt_main
 			REG(OACONTROL,
 			    0xfffff000, 0x00000000,
 			    0xfeed0000, 0x31337000, false, 9),
+			/*
+			 * INSTPM is masked and only has 3bits
+			 * allowed.
+			*/
+			REGN("INSTPM-allowed", INSTPM,
+			     0x0000000e, 0x000e0000,
+			     0x00000000, 0x0000000e, true, 10),
+			REGN("INSTPM-disallowed", INSTPM,
+			     0x0000000e, 0x000e0000,
+			     0x00000000, 0x100e100e, false, 10)
 		};
 #undef REG
+#undef REGN
 
 		igt_fixture {
 			intel_register_access_init(intel_get_pci_device(), 0, fd);
-- 
2.17.0

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[igt-dev] [PATCH i-g-t 3/3] test/gem_ctx_isolation: verify INSTPM isolation on Gen7+

[Lionel Landwerlin]

This register should leak between contexts. Documentation says it's
context saved/restored.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 tests/gem_ctx_isolation.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tests/gem_ctx_isolation.c b/tests/gem_ctx_isolation.c
index 4968e367..48291547 100644
--- a/tests/gem_ctx_isolation.c
+++ b/tests/gem_ctx_isolation.c
@@ -122,6 +122,7 @@ static const struct named_register {
 	{ "OA_CONTROL", NOCTX, RCS0, 0x2b00 },
 	{ "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 },
 	{ "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 },
+	{ "INSTPM", GEN7, RCS0, 0x20c0 },
 
 	/* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
 	{ "CTX_PREEMPT", NOCTX /* GEN_RANGE(9, 10) */, RCS0, 0x2248 },
-- 
2.17.0

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Re: [igt-dev] [PATCH i-g-t 3/3] test/gem_ctx_isolation: verify INSTPM isolation on Gen7+

[Chris Wilson]

Quoting Lionel Landwerlin (2018-05-18 18:10:43)
> This register should leak between contexts. Documentation says it's
> context saved/restored.
> 
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
>  tests/gem_ctx_isolation.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/tests/gem_ctx_isolation.c b/tests/gem_ctx_isolation.c
> index 4968e367..48291547 100644
> --- a/tests/gem_ctx_isolation.c
> +++ b/tests/gem_ctx_isolation.c
> @@ -122,6 +122,7 @@ static const struct named_register {
>         { "OA_CONTROL", NOCTX, RCS0, 0x2b00 },
>         { "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 },
>         { "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 },
> +       { "INSTPM", GEN7, RCS0, 0x20c0 },

It's already in the list, just marked as GEN9+. Let's fix that one :)
-Chris
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Re: [igt-dev] [PATCH i-g-t 1/3] tests/gem_exec_parse: add a register write mask

[Chris Wilson]

Quoting Lionel Landwerlin (2018-05-18 18:10:41)
> Some register are masked (meaning the 16bits are dedicated to identify
> which of the other 16bits have to be taken into account by the
> hardware). This change adds the mask to the write but doesn't take it
> into account in the value comparison assert.
> 
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [igt-dev] [PATCH i-g-t 3/3] test/gem_ctx_isolation: verify INSTPM isolation on Gen7+

[Lionel Landwerlin]

On 18/05/18 18:14, Chris Wilson wrote:
> Quoting Lionel Landwerlin (2018-05-18 18:10:43)
>> This register should leak between contexts. Documentation says it's
>> context saved/restored.
>>
>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>> ---
>>   tests/gem_ctx_isolation.c | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/tests/gem_ctx_isolation.c b/tests/gem_ctx_isolation.c
>> index 4968e367..48291547 100644
>> --- a/tests/gem_ctx_isolation.c
>> +++ b/tests/gem_ctx_isolation.c
>> @@ -122,6 +122,7 @@ static const struct named_register {
>>          { "OA_CONTROL", NOCTX, RCS0, 0x2b00 },
>>          { "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 },
>>          { "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 },
>> +       { "INSTPM", GEN7, RCS0, 0x20c0 },
> It's already in the list, just marked as GEN9+. Let's fix that one :)
> -Chris
>
Duh!

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Re: [igt-dev] [PATCH i-g-t 2/3] tests/gem_exec_parse: verify that we allow LRI on INSTPM

[Chris Wilson]

Quoting Lionel Landwerlin (2018-05-18 18:10:42)
> INSTPM will be used by Mesa. It's allowed by default on Gen8+.
> 
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
>  tests/gem_exec_parse.c | 16 +++++++++++++++-
>  1 file changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
> index c37c056e..0818a6a5 100644
> --- a/tests/gem_exec_parse.c
> +++ b/tests/gem_exec_parse.c
> @@ -38,6 +38,7 @@
>  #define OASTATUS2 0x2368
>  #define OACONTROL 0x2360
>  #define SO_WRITE_OFFSET_0 0x5280
> +#define INSTPM 0x20c0
>  
>  #define HSW_CS_GPR(n) (0x2600 + 8*(n))
>  #define HSW_CS_GPR0 HSW_CS_GPR(0)
> @@ -369,6 +370,7 @@ static void hsw_load_register_reg(void)
>                 OACONTROL, /* filtered */
>                 DERRMR, /* master only */
>                 0x2038, /* RING_START: invalid */
> +               INSTPM, /* filtered */
>         };
>         int fd;
>         uint32_t handle;
> @@ -378,7 +380,7 @@ static void hsw_load_register_reg(void)
>         fd = drm_open_driver(DRIVER_INTEL);
>  
>         igt_require(IS_HASWELL(intel_get_drm_devid(fd)));
> -       igt_require(parser_version >= 7);
> +       igt_require(parser_version >= 10);

Oh, that's painful. We should just filter out individual tests.

>  
> @@ -501,6 +503,7 @@ igt_main
>  
>         igt_subtest_group {
>  #define REG(R, RMSK, WMSK, INI, V, OK, MIN_V) { #R, R, RMSK, WMSK, INI, V, OK, MIN_V }
> +#define REGN(N, R, RMSK, WMSK, INI, V, OK, MIN_V) { N, R, RMSK, WMSK, INI, V, OK, MIN_V }
>                 struct test_lri lris[] = {
>                         /* dummy head pointer */
>                         REG(OASTATUS2,
> @@ -527,8 +530,19 @@ igt_main
>                         REG(OACONTROL,
>                             0xfffff000, 0x00000000,
>                             0xfeed0000, 0x31337000, false, 9),
> +                       /*
> +                        * INSTPM is masked and only has 3bits
> +                        * allowed.
> +                       */
> +                       REGN("INSTPM-allowed", INSTPM,

0x000e, 0x000e << 16

> +                            0x0000000e, 0x000e0000,
> +                            0x00000000, 0x0000000e, true, 10),
> +                       REGN("INSTPM-disallowed", INSTPM,
> +                            0x0000000e, 0x000e0000,
> +                            0x00000000, 0x100e100e, false, 10)

So many negative values to test :) At least do
	0xffff | 0xffff << 16
	0x0000 | 0xffff << 16
for set-all and clear-all
-Chris
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[igt-dev] ✓ Fi.CI.BAT: success for intel/gem: test the partial whitelisting of the INSTPM register

[Patchwork]

== Series Details ==

Series: intel/gem: test the partial whitelisting of the INSTPM register
URL   : https://patchwork.freedesktop.org/series/43436/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4193 -> IGTPW_1376 =

== Summary - WARNING ==

  Minor unknown changes coming with IGTPW_1376 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_1376, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/43436/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in IGTPW_1376:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_exec_gttfill@basic:
      fi-pnv-d510:        SKIP -> PASS

    
== Known issues ==

  Here are the changes found in IGTPW_1376 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-snb-2520m:       NOTRUN -> INCOMPLETE (fdo#103713)

    
    ==== Possible fixes ====

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
      fi-cfl-s3:          FAIL (fdo#103481) -> PASS +1

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      fi-cnl-psr:         DMESG-WARN (fdo#104951) -> PASS

    
  fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951


== Participating hosts (41 -> 38) ==

  Additional (3): fi-kbl-guc fi-cfl-guc fi-snb-2520m 
  Missing    (6): fi-ilk-m540 fi-bxt-dsi fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-skl-6700hq 


== Build changes ==

    * IGT: IGT_4485 -> IGTPW_1376
    * Piglit: piglit_4485 -> piglit_4487

  CI_DRM_4193: 9322e3903ce6c89bde0c24877fe730b808427caf @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_1376: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1376/
  IGT_4485: eccae1360d6d01e73c6af2bd97122cef708207ef @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4485: 62ef6b0db8967e7021fd3e0b57d03ff164b984fe @ git://anongit.freedesktop.org/piglit
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ git://anongit.freedesktop.org/piglit



== Testlist changes ==

+igt@gem_exec_parse@test-lri-instpm-allowed
+igt@gem_exec_parse@test-lri-instpm-disallowed

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1376/issues.html
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[igt-dev] ✓ Fi.CI.IGT: success for intel/gem: test the partial whitelisting of the INSTPM register

[Patchwork]

== Series Details ==

Series: intel/gem: test the partial whitelisting of the INSTPM register
URL   : https://patchwork.freedesktop.org/series/43436/
State : success

== Summary ==

= CI Bug Log - changes from IGT_4485_full -> IGTPW_1376_full =

== Summary - WARNING ==

  Minor unknown changes coming with IGTPW_1376_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_1376_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/43436/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in IGTPW_1376_full:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_exec_parse@load-register-reg:
      shard-hsw:          PASS -> SKIP

    igt@gem_exec_schedule@deep-bsd2:
      shard-kbl:          SKIP -> PASS

    igt@gem_mocs_settings@mocs-rc6-bsd2:
      shard-kbl:          PASS -> SKIP

    igt@gem_pwrite@big-gtt-fbr:
      shard-glk:          PASS -> SKIP

    igt@kms_chv_cursor_fail@pipe-a-64x64-top-edge:
      shard-apl:          PASS -> SKIP +36

    igt@kms_cursor_crc@cursor-128x128-random:
      shard-snb:          SKIP -> PASS

    
== Known issues ==

  Here are the changes found in IGTPW_1376_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_eio@execbuf:
      shard-glk:          PASS -> DMESG-WARN (fdo#106523) +3
      shard-hsw:          PASS -> DMESG-WARN (fdo#106523) +3

    igt@gem_eio@in-flight-contexts-1us:
      shard-snb:          PASS -> DMESG-WARN (fdo#106523) +3

    igt@gem_eio@in-flight-contexts-immediate:
      shard-apl:          PASS -> DMESG-WARN (fdo#106523) +2

    igt@gem_eio@in-flight-external:
      shard-kbl:          PASS -> DMESG-WARN (fdo#106523)

    igt@kms_cursor_crc@cursor-128x42-offscreen:
      shard-apl:          PASS -> DMESG-WARN (fdo#105602, fdo#103558) +17

    igt@kms_fbcon_fbt@fbc-suspend:
      shard-kbl:          PASS -> INCOMPLETE (fdo#103665)

    igt@kms_flip@2x-flip-vs-expired-vblank:
      shard-glk:          PASS -> FAIL (fdo#105363)

    igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
      shard-glk:          PASS -> FAIL (fdo#100368)

    igt@kms_flip@flip-vs-expired-vblank-interruptible:
      shard-hsw:          PASS -> FAIL (fdo#105707)

    igt@kms_flip@modeset-vs-vblank-race:
      shard-hsw:          PASS -> FAIL (fdo#103060) +1

    igt@kms_flip_tiling@flip-y-tiled:
      shard-glk:          PASS -> FAIL (fdo#104724, fdo#103822)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      shard-apl:          PASS -> DMESG-WARN (fdo#103558) +1

    igt@kms_setmode@basic:
      shard-apl:          PASS -> FAIL (fdo#99912)

    igt@pm_rpm@fences-dpms:
      shard-kbl:          PASS -> DMESG-WARN (fdo#105602, fdo#103558) +15

    
    ==== Possible fixes ====

    igt@gem_ctx_isolation@vecs0-s3:
      shard-kbl:          INCOMPLETE (fdo#103665) -> PASS +1

    igt@gem_eio@hibernate:
      shard-hsw:          DMESG-WARN (fdo#106523) -> PASS +3

    igt@gem_eio@in-flight-immediate:
      shard-apl:          DMESG-WARN (fdo#106523) -> PASS +3
      shard-snb:          DMESG-WARN (fdo#106523) -> PASS +4

    igt@gem_eio@in-flight-internal-immediate:
      shard-glk:          DMESG-WARN (fdo#106523) -> PASS +4

    igt@gem_eio@wait-wedge-10ms:
      shard-kbl:          DMESG-WARN (fdo#106523) -> PASS +2

    igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
      shard-glk:          FAIL (fdo#105703) -> PASS

    igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
      shard-glk:          FAIL (fdo#106509) -> PASS

    igt@kms_flip@2x-plain-flip-ts-check-interruptible:
      shard-glk:          FAIL (fdo#100368) -> PASS

    igt@kms_flip@flip-vs-expired-vblank-interruptible:
      shard-glk:          FAIL (fdo#105707) -> PASS +1

    igt@kms_flip_tiling@flip-to-y-tiled:
      shard-glk:          FAIL (fdo#104724, fdo#103822) -> PASS

    igt@perf_pmu@idle-vcs0:
      shard-glk:          INCOMPLETE (k.org#198133, fdo#103359) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
  fdo#105707 https://bugs.freedesktop.org/show_bug.cgi?id=105707
  fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
  fdo#106523 https://bugs.freedesktop.org/show_bug.cgi?id=106523
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

    * IGT: IGT_4485 -> IGTPW_1376
    * Linux: CI_DRM_4191 -> CI_DRM_4193
    * Piglit: piglit_4485 -> piglit_4487

  CI_DRM_4191: 70daebf1a83c2ed6eff118d2a2806086c0c89027 @ git://anongit.freedesktop.org/gfx-ci/linux
  CI_DRM_4193: 9322e3903ce6c89bde0c24877fe730b808427caf @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_1376: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1376/
  IGT_4485: eccae1360d6d01e73c6af2bd97122cef708207ef @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4485: 62ef6b0db8967e7021fd3e0b57d03ff164b984fe @ git://anongit.freedesktop.org/piglit
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1376/shards.html
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