[PATCH 00/11] Skylake display NV12 feature addition

[PATCH 00/11] Skylake display NV12 feature addition

[Chandra Konduru]

This patch series adding NV12 support for Skylake display.
Feature is tested with igt/kms_nv12 testcase.
I will be sending the igt patches shortly.

Feature is unit tested for linear/X/Y/Yf formats in 0 and 180
orientations with combinations of 1, 2 or 3 planes enabled along
with scaling. Also negatively tested for enabling NV12 on unsupported
plane.

Chandra Konduru (11):
  drm/i915: Add register definitions for NV12 support
  drm/i915: Set scaler mode for NV12
  drm/i915: Stage scaler request for NV12 as src format
  drm/i915: Update format_is_yuv() to include NV12
  drm/i915: Upscale scaler max scale for NV12.
  drm/i915: Add NV12 as supported format for primary plane
  drm/i915: Add NV12 as supported format for sprite plane
  drm/i915: Add NV12 support to intel_framebuffer_init
  drm/i915: Update compute_baseline_bpp for NV12.
  drm/i915: Add NV12 to primary plane programming.
  drm/i915: Add NV12 to sprite plane programming.

 drivers/gpu/drm/i915/i915_reg.h           |   27 +++++++
 drivers/gpu/drm/i915/intel_atomic.c       |    5 +-
 drivers/gpu/drm/i915/intel_atomic_plane.c |    2 +
 drivers/gpu/drm/i915/intel_display.c      |  120 +++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_drv.h          |    4 +-
 drivers/gpu/drm/i915/intel_sprite.c       |   59 ++++++++++++--
 6 files changed, 201 insertions(+), 16 deletions(-)

-- 
1.7.9.5

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[PATCH 01/11] drm/i915: Add register definitions for NV12 support

[Chandra Konduru]

This patch adds register definitions for skylake
display NV12 support.

Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |   27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index aa2a0de..504d967 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5121,6 +5121,7 @@ enum skl_disp_power_wells {
 #define PS_SCALER_MODE_MASK (3 << 28)
 #define PS_SCALER_MODE_DYN  (0 << 28)
 #define PS_SCALER_MODE_HQ  (1 << 28)
+#define PS_SCALER_MODE_NV12 (2 << 28)
 #define PS_PLANE_SEL_MASK  (7 << 25)
 #define PS_PLANE_SEL(plane) ((plane + 1) << 25)
 #define PS_FILTER_MASK         (3 << 23)
@@ -5224,6 +5225,32 @@ enum skl_disp_power_wells {
 			_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
 			_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)
 
+
+/*
+ * Skylake  NV12 Register
+ */
+#define PLANE_AUX_DIST_1_A		0x701c0
+#define PLANE_AUX_DIST_2_A		0x702c0
+#define PLANE_AUX_DIST_1_B		0x711c0
+#define PLANE_AUX_DIST_2_B		0x712c0
+#define _PLANE_AUX_DIST_1(pipe)	\
+   _PIPE(pipe, PLANE_AUX_DIST_1_A, PLANE_AUX_DIST_1_B)
+#define _PLANE_AUX_DIST_2(pipe)	\
+   _PIPE(pipe, PLANE_AUX_DIST_2_A, PLANE_AUX_DIST_2_B)
+#define PLANE_AUX_DIST(pipe, plane)	\
+	_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
+
+#define PLANE_AUX_OFFSET_1_A		0x701c4
+#define PLANE_AUX_OFFSET_2_A		0x702c4
+#define PLANE_AUX_OFFSET_1_B		0x711c4
+#define PLANE_AUX_OFFSET_2_B		0x712c4
+#define _PLANE_AUX_OFFSET_1(pipe)	\
+   _PIPE(pipe, PLANE_AUX_OFFSET_1_A, PLANE_AUX_OFFSET_1_B)
+#define _PLANE_AUX_OFFSET_2(pipe)	\
+   _PIPE(pipe, PLANE_AUX_OFFSET_2_A, PLANE_AUX_OFFSET_2_B)
+#define PLANE_AUX_OFFSET(pipe, plane)	\
+	_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
+
 /* legacy palette */
 #define _LGC_PALETTE_A           0x4a000
 #define _LGC_PALETTE_B           0x4a800
-- 
1.7.9.5

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[PATCH 02/11] drm/i915: Set scaler mode for NV12

[Chandra Konduru]

This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling.

Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
---
 drivers/gpu/drm/i915/intel_atomic.c |    5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index cb6d5f2..fe10f22 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -400,7 +400,10 @@ int intel_atomic_setup_scalers(struct drm_device *dev,
 		}
 
 		/* set scaler mode */
-		if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
+		if (plane_state && plane_state->base.fb &&
+			plane_state->base.fb->pixel_format == DRM_FORMAT_NV12) {
+			scaler_state->scalers[*scaler_id].mode = PS_SCALER_MODE_NV12;
+		} else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
 			/*
 			 * when only 1 scaler is in use on either pipe A or B,
 			 * scaler 0 operates in high quality (HQ) mode.
-- 
1.7.9.5

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[PATCH 03/11] drm/i915: Stage scaler request for NV12 as src format

[Chandra Konduru]

This patch stages a scaler request when input format
is NV12. The same scaler does both chroma-upsampling
and resolution scaling as needed.

Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 22799fb..9d413a6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4444,9 +4444,11 @@ skl_update_scaler_users(
 		rotation = DRM_ROTATE_0;
 	}
 
-	need_scaling = intel_rotation_90_or_270(rotation) ?
-		(src_h != dst_w || src_w != dst_h):
-		(src_w != dst_w || src_h != dst_h);
+	/* scaling is required when src dst sizes doesn't match or format is NV12 */
+	need_scaling = (src_w != dst_w || src_h != dst_h ||
+		(intel_rotation_90_or_270(rotation) &&
+			(src_h != dst_w || src_w != dst_h)) ||
+		(fb && fb->pixel_format == DRM_FORMAT_NV12));
 
 	/*
 	 * if plane is being disabled or scaler is no more required or force detach
@@ -4512,6 +4514,7 @@ skl_update_scaler_users(
 		case DRM_FORMAT_YVYU:
 		case DRM_FORMAT_UYVY:
 		case DRM_FORMAT_VYUY:
+		case DRM_FORMAT_NV12:
 			break;
 		default:
 			DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
-- 
1.7.9.5

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[PATCH 04/11] drm/i915: Update format_is_yuv() to include NV12

[Chandra Konduru]

This patch adds NV12 to format_is_yuv() function
and made it available for both primary and sprite
planes.

Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h    |    1 +
 drivers/gpu/drm/i915/intel_sprite.c |    3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8079865..ccf89f8 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1376,6 +1376,7 @@ bool intel_pipe_update_start(struct intel_crtc *crtc,
 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
 void intel_post_enable_primary(struct drm_crtc *crtc);
 void intel_pre_disable_primary(struct drm_crtc *crtc);
+bool format_is_yuv(uint32_t format);
 
 /* intel_tv.c */
 void intel_tv_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 68de97c..5698a07 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -39,7 +39,7 @@
 #include <drm/i915_drm.h>
 #include "i915_drv.h"
 
-static bool
+bool
 format_is_yuv(uint32_t format)
 {
 	switch (format) {
@@ -47,6 +47,7 @@ format_is_yuv(uint32_t format)
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
 	case DRM_FORMAT_YVYU:
+	case DRM_FORMAT_NV12:
 		return true;
 	default:
 		return false;
-- 
1.7.9.5

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[PATCH 05/11] drm/i915: Upscale scaler max scale for NV12.

[Chandra Konduru]

This patch updates max supported scaler limits for NV12.

Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   12 ++++++++----
 drivers/gpu/drm/i915/intel_drv.h     |    3 ++-
 drivers/gpu/drm/i915/intel_sprite.c  |    2 +-
 3 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9d413a6..c235a66 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12893,7 +12893,8 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
 }
 
 int
-skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
+skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
+	uint32_t pixel_format)
 {
 	int max_scale;
 	struct drm_device *dev;
@@ -12913,11 +12914,13 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state
 
 	/*
 	 * skl max scale is lower of:
-	 *    close to 3 but not 3, -1 is for that purpose
+	 *    close to 2 or 3 (NV12: 2, other formats: 3) but not equal,
+	 *          -1 is for that purpose
 	 *            or
 	 *    cdclk/crtc_clock
 	 */
-	max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
+	max_scale = min((1 << 16) * (pixel_format == DRM_FORMAT_NV12 ? 2 : 3) - 1,
+		(1 << 8) * ((cdclk << 8) / crtc_clock));
 
 	return max_scale;
 }
@@ -12947,7 +12950,8 @@ intel_check_primary_plane(struct drm_plane *plane,
 
 	if (INTEL_INFO(dev)->gen >= 9) {
 		min_scale = 1;
-		max_scale = skl_max_scale(intel_crtc, crtc_state);
+		max_scale = skl_max_scale(intel_crtc, crtc_state,
+			fb ? fb->pixel_format :0);
 		can_position = true;
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ccf89f8..fdd667d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1139,7 +1139,8 @@ void skl_detach_scalers(struct intel_crtc *intel_crtc);
 int skl_update_scaler_users(struct intel_crtc *intel_crtc,
 	struct intel_crtc_state *crtc_state, struct intel_plane *intel_plane,
 	struct intel_plane_state *plane_state, int force_detach);
-int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
+int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
+	uint32_t pixel_format);
 
 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
 				     struct drm_i915_gem_object *obj);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 5698a07..59846f8 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -901,7 +901,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
 
 	if (INTEL_INFO(dev)->gen >= 9) {
 		min_scale = 1;
-		max_scale = skl_max_scale(intel_crtc, crtc_state);
+		max_scale = skl_max_scale(intel_crtc, crtc_state, fb->pixel_format);
 	}
 
 	drm_rect_rotate(src, fb->width << 16, fb->height << 16,
-- 
1.7.9.5

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[PATCH 06/11] drm/i915: Add NV12 as supported format for primary plane

[Chandra Konduru]

This patch adds NV12 to list of supported formats for
primary plane.

Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Testcase: igt/kms_nv12
---
 drivers/gpu/drm/i915/intel_display.c |   32 +++++++++++++++++++++++++++++++-
 1 file changed, 31 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c235a66..d3773d2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -59,7 +59,7 @@ static const uint32_t intel_primary_formats_gen2[] = {
 	DRM_FORMAT_ARGB1555,
 };
 
-/* Primary plane formats for gen >= 4 */
+/* Primary plane formats for gen 4 to 8 */
 static const uint32_t intel_primary_formats_gen4[] = {
 	COMMON_PRIMARY_FORMATS, \
 	DRM_FORMAT_XBGR8888,
@@ -70,6 +70,28 @@ static const uint32_t intel_primary_formats_gen4[] = {
 	DRM_FORMAT_ABGR2101010,
 };
 
+/* Primary plane formats for gen >= 9 */
+static const uint32_t intel_primary_formats_gen9[] = {
+	COMMON_PRIMARY_FORMATS, \
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_XRGB2101010,
+	DRM_FORMAT_ARGB2101010,
+	DRM_FORMAT_XBGR2101010,
+	DRM_FORMAT_ABGR2101010,
+};
+
+static const uint32_t intel_primary_formats_with_nv12_gen9[] = {
+	COMMON_PRIMARY_FORMATS, \
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_XRGB2101010,
+	DRM_FORMAT_ARGB2101010,
+	DRM_FORMAT_XBGR2101010,
+	DRM_FORMAT_ABGR2101010,
+	DRM_FORMAT_NV12,
+};
+
 /* Cursor formats */
 static const uint32_t intel_cursor_formats[] = {
 	DRM_FORMAT_ARGB8888,
@@ -13204,6 +13226,14 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
 	if (INTEL_INFO(dev)->gen <= 3) {
 		intel_primary_formats = intel_primary_formats_gen2;
 		num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
+	} else if (INTEL_INFO(dev)->gen >= 9) {
+		if (pipe == PIPE_A || pipe == PIPE_B) {
+			intel_primary_formats = intel_primary_formats_with_nv12_gen9;
+			num_formats = ARRAY_SIZE(intel_primary_formats_with_nv12_gen9);
+		} else {
+			intel_primary_formats = intel_primary_formats_gen9;
+			num_formats = ARRAY_SIZE(intel_primary_formats_gen9);
+		}
 	} else {
 		intel_primary_formats = intel_primary_formats_gen4;
 		num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
-- 
1.7.9.5

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[PATCH 07/11] drm/i915: Add NV12 as supported format for sprite plane

[Chandra Konduru]

This patch adds NV12 to list of supported formats for
sprite plane.

Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Testcase: igt/kms_nv12
---
 drivers/gpu/drm/i915/intel_sprite.c |   23 +++++++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 59846f8..aa2998f 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1207,6 +1207,19 @@ static uint32_t skl_plane_formats[] = {
 	DRM_FORMAT_VYUY,
 };
 
+static uint32_t skl_plane_formats_with_nv12[] = {
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+	DRM_FORMAT_NV12,
+};
+
 int
 intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
 {
@@ -1278,8 +1291,14 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
 		intel_plane->disable_plane = skl_disable_plane;
 		state->scaler_id = -1;
 
-		plane_formats = skl_plane_formats;
-		num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+		if ((pipe == PIPE_A || pipe == PIPE_B) && (plane == 0)) {
+			plane_formats = skl_plane_formats_with_nv12;
+			num_plane_formats = ARRAY_SIZE(skl_plane_formats_with_nv12);
+		} else {
+			plane_formats = skl_plane_formats;
+			num_plane_formats = ARRAY_SIZE(skl_plane_formats) - 1;
+		}
+
 		break;
 	default:
 		kfree(intel_plane);
-- 
1.7.9.5

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[PATCH 08/11] drm/i915: Add NV12 support to intel_framebuffer_init

[Chandra Konduru]

This patch adds NV12 as supported format to
intel_framebuffer_init and performs various checks.

Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Testcase: igt/kms_nv12
---
 drivers/gpu/drm/i915/intel_display.c |   27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d3773d2..6e693c4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13953,6 +13953,33 @@ static int intel_framebuffer_init(struct drm_device *dev,
 			return -EINVAL;
 		}
 		break;
+	case DRM_FORMAT_NV12:
+		if (INTEL_INFO(dev)->gen < 9) {
+			DRM_DEBUG("unsupported pixel format: %s\n",
+				  drm_get_format_name(mode_cmd->pixel_format));
+			return -EINVAL;
+		}
+		if (!mode_cmd->offsets[1]) {
+			DRM_DEBUG("uv start offset not set\n");
+			return -EINVAL;
+		}
+		if (mode_cmd->pitches[0] != mode_cmd->pitches[1] ||
+			mode_cmd->handles[0] != mode_cmd->handles[1]) {
+			DRM_DEBUG("y and uv subplanes have different parameters\n");
+			return -EINVAL;
+		}
+		if (mode_cmd->modifier[1] == I915_FORMAT_MOD_Yf_TILED &&
+			(mode_cmd->offsets[1] & 0xFFF)) {
+			DRM_DEBUG("tile-Yf uv offset 0x%x isn't starting on new tile-row\n",
+				mode_cmd->offsets[1]);
+			return -EINVAL;
+		}
+		if (mode_cmd->modifier[1] == I915_FORMAT_MOD_Y_TILED &&
+			((mode_cmd->offsets[1] % mode_cmd->pitches[1]) % 4)) {
+			DRM_DEBUG("tile-Y uv offset 0x%x isn't 4-line aligned\n",
+				mode_cmd->offsets[1]);
+		}
+		break;
 	default:
 		DRM_DEBUG("unsupported pixel format: %s\n",
 			  drm_get_format_name(mode_cmd->pixel_format));
-- 
1.7.9.5

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[PATCH 09/11] drm/i915: Update compute_baseline_bpp for NV12.

[Chandra Konduru]

This patch updates baseline bpp when primary plane
is running with NV12. It is same as 8-bpc RGB formats
because NV12 also has 8-bits per channel.

Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6e693c4..e747766 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10845,6 +10845,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
 			return -EINVAL;
 	case DRM_FORMAT_XRGB8888:
 	case DRM_FORMAT_ARGB8888:
+	case DRM_FORMAT_NV12:
 		bpp = 8*3;
 		break;
 	case DRM_FORMAT_XRGB2101010:
-- 
1.7.9.5

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[PATCH 10/11] drm/i915: Add NV12 to primary plane programming.

[Chandra Konduru]

This patch is adding NV12 support to skylake primary plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.

For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. Once GEM adds support
for seperate remappings for two subplanes, 90/270 support
to be added to plane programming.

Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Testcase: igt/kms_nv12
---
 drivers/gpu/drm/i915/intel_atomic_plane.c |    2 ++
 drivers/gpu/drm/i915/intel_display.c      |   39 +++++++++++++++++++++++++++++
 2 files changed, 41 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
index a27ee8c..84cd9fc 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -173,10 +173,12 @@ static int intel_plane_atomic_check(struct drm_plane *plane,
 		 * 90/270 is not allowed with RGB64 16:16:16:16,
 		 * RGB 16-bit 5:6:5, and Indexed 8-bit.
 		 * TBD: Add RGB64 case once its added in supported format list.
+		 * TBD: Remove NV12, once its 90/270 remapping is supported
 		 */
 		switch (state->fb->pixel_format) {
 		case DRM_FORMAT_C8:
 		case DRM_FORMAT_RGB565:
+		case DRM_FORMAT_NV12:
 			DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
 					drm_get_format_name(state->fb->pixel_format));
 			return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e747766..c9d5cc9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3026,6 +3026,9 @@ u32 skl_plane_ctl_format(uint32_t pixel_format)
 	case DRM_FORMAT_VYUY:
 		plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
 		break;
+	case DRM_FORMAT_NV12:
+		plane_ctl_format = PLANE_CTL_FORMAT_NV12;
+		break;
 	default:
 		BUG();
 	}
@@ -3095,6 +3098,8 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
 	int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
 	int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
 	int scaler_id = -1;
+	u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+	u32 tile_row_adjustment = 0;
 
 	plane = crtc->primary;
 	plane_state = to_intel_plane_state(plane->state);
@@ -3152,11 +3157,35 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
 		x_offset = stride * tile_height - y - src_h;
 		y_offset = x;
 		plane_size = (src_w - 1) << 16 | (src_h - 1);
+		/*
+		 * TBD: For NV12 90/270 rotation, Y and UV subplanes should
+		 * be treated as separate surfaces and GTT remapping for
+		 * rotation should be done separately for each subplane.
+		 * Enable support once seperate remappings are available.
+		 */
 	} else {
 		stride = fb->pitches[0] / stride_div;
 		x_offset = x;
 		y_offset = y;
 		plane_size = (src_h - 1) << 16 | (src_w - 1);
+		tile_height = PAGE_SIZE / stride_div;
+
+		if (fb->pixel_format == DRM_FORMAT_NV12) {
+			int height_in_mem = (fb->offsets[1]/fb->pitches[0]);
+			/*
+			 * If UV starts from middle of a page, then UV start should
+			 * be programmed to beginning of that page. And offset into that
+			 * page to be programmed into y-offset
+			 */
+			tile_row_adjustment = height_in_mem % tile_height;
+			aux_dist = fb->pitches[0] * (height_in_mem - tile_row_adjustment);
+			aux_x_offset = DIV_ROUND_UP(plane_state->src.x1, 2);
+			aux_y_offset = DIV_ROUND_UP(plane_state->src.y1, 2) +
+				tile_row_adjustment;
+			/* For tile-Yf, uv-subplane tile width is 2x of Y-subplane */
+			aux_stride = fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED ?
+				stride / 2 : stride;
+		}
 	}
 	plane_offset = y_offset << 16 | x_offset;
 
@@ -3164,11 +3193,14 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
 	I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
 	I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
 	I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
+	I915_WRITE(PLANE_AUX_DIST(pipe, 0), aux_dist | aux_stride);
+	I915_WRITE(PLANE_AUX_OFFSET(pipe, 0), aux_y_offset << 16 | aux_x_offset);
 
 	if (scaler_id >= 0) {
 		uint32_t ps_ctrl = 0;
 
 		WARN_ON(!dst_w || !dst_h);
+
 		ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
 			crtc_state->scaler_state.scalers[scaler_id].mode;
 		I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
@@ -3177,6 +3209,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
 		I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
 		I915_WRITE(PLANE_POS(pipe, 0), 0);
 	} else {
+		WARN_ON(fb->pixel_format == DRM_FORMAT_NV12);
 		I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
 	}
 
@@ -13026,6 +13059,12 @@ intel_check_primary_plane(struct drm_plane *plane,
 			intel_crtc->atomic.update_wm = true;
 	}
 
+	/* Adjust (macro)pixel boundary */
+	if (fb && format_is_yuv(fb->pixel_format)) {
+		src->x1 &= ~0x10000;
+		src->x2 &= ~0x10000;
+	}
+
 	if (INTEL_INFO(dev)->gen >= 9) {
 		ret = skl_update_scaler_users(intel_crtc, crtc_state,
 			to_intel_plane(plane), state, 0);
-- 
1.7.9.5

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[PATCH 11/11] drm/i915: Add NV12 to sprite plane programming.

[Chandra Konduru]

This patch is adding NV12 support to skylake sprite plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.

For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. Once GEM adds support
for seperate remappings for two subplanes, 90/270 support
to be added to plane programming.

Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Testcase: igt/kms_nv12
---
 drivers/gpu/drm/i915/intel_sprite.c |   31 +++++++++++++++++++++++++++++--
 1 file changed, 29 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index aa2998f..2a03905 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -201,6 +201,8 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
 	int x_offset, y_offset;
 	struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config;
 	int scaler_id;
+	u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+	u32 tile_row_adjustment = 0;
 
 	plane_ctl = PLANE_CTL_ENABLE |
 		PLANE_CTL_PIPE_CSC_ENABLE;
@@ -247,24 +249,48 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
 		plane_size = (src_w << 16) | src_h;
 		x_offset = stride * tile_height - y - (src_h + 1);
 		y_offset = x;
+
+		/*
+		 * TBD: For NV12 90/270 rotation, Y and UV subplanes should
+		 * be treated as separate surfaces and GTT remapping for
+		 * rotation should be done separately for each subplane.
+		 * Enable support once seperate remappings are available.
+		 */
 	} else {
 		stride = fb->pitches[0] / stride_div;
 		plane_size = (src_h << 16) | src_w;
 		x_offset = x;
 		y_offset = y;
+		tile_height = PAGE_SIZE / stride_div;
+
+		if (fb->pixel_format == DRM_FORMAT_NV12) {
+			int height_in_mem = (fb->offsets[1]/fb->pitches[0]);
+			/*
+			 * If UV starts from middle of a page, then UV start should
+			 * be programmed to beginning of that page. And offset into that
+			 * page to be programmed into y-offset
+			 */
+			tile_row_adjustment = height_in_mem % tile_height;
+			aux_dist = fb->pitches[0] * (height_in_mem - tile_row_adjustment);
+			aux_x_offset = DIV_ROUND_UP(x, 2);
+			aux_y_offset = DIV_ROUND_UP(y, 2) + tile_row_adjustment;
+			/* For tile-Yf, uv-subplane tile width is 2x of Y-subplane */
+			aux_stride = fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED ?
+				stride / 2 : stride;
+		}
 	}
 	plane_offset = y_offset << 16 | x_offset;
 
 	I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
 	I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
 	I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
+	I915_WRITE(PLANE_AUX_DIST(pipe, plane), aux_dist | aux_stride);
+	I915_WRITE(PLANE_AUX_OFFSET(pipe, plane), aux_y_offset<<16 | aux_x_offset);
 
 	/* program plane scaler */
 	if (scaler_id >= 0) {
 		uint32_t ps_ctrl = 0;
 
-		DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
-			PS_PLANE_SEL(plane));
 		ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) |
 			crtc_state->scaler_state.scalers[scaler_id].mode;
 		I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
@@ -275,6 +301,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
 
 		I915_WRITE(PLANE_POS(pipe, plane), 0);
 	} else {
+		WARN_ON(fb->pixel_format == DRM_FORMAT_NV12);
 		I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
 	}
 
-- 
1.7.9.5

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Re: [PATCH 06/11] drm/i915: Add NV12 as supported format for primary plane

[Daniel Vetter]

On Thu, Apr 30, 2015 at 08:43:10PM -0700, Chandra Konduru wrote:
> This patch adds NV12 to list of supported formats for
> primary plane.
> 
> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> Testcase: igt/kms_nv12
> ---
>  drivers/gpu/drm/i915/intel_display.c |   32 +++++++++++++++++++++++++++++++-
>  1 file changed, 31 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c235a66..d3773d2 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -59,7 +59,7 @@ static const uint32_t intel_primary_formats_gen2[] = {
>  	DRM_FORMAT_ARGB1555,
>  };
>  
> -/* Primary plane formats for gen >= 4 */
> +/* Primary plane formats for gen 4 to 8 */
>  static const uint32_t intel_primary_formats_gen4[] = {
>  	COMMON_PRIMARY_FORMATS, \
>  	DRM_FORMAT_XBGR8888,
> @@ -70,6 +70,28 @@ static const uint32_t intel_primary_formats_gen4[] = {
>  	DRM_FORMAT_ABGR2101010,
>  };
>  
> +/* Primary plane formats for gen >= 9 */
> +static const uint32_t intel_primary_formats_gen9[] = {
> +	COMMON_PRIMARY_FORMATS, \
> +	DRM_FORMAT_XBGR8888,
> +	DRM_FORMAT_ABGR8888,
> +	DRM_FORMAT_XRGB2101010,
> +	DRM_FORMAT_ARGB2101010,
> +	DRM_FORMAT_XBGR2101010,
> +	DRM_FORMAT_ABGR2101010,
> +};
> +
> +static const uint32_t intel_primary_formats_with_nv12_gen9[] = {
> +	COMMON_PRIMARY_FORMATS, \
> +	DRM_FORMAT_XBGR8888,
> +	DRM_FORMAT_ABGR8888,
> +	DRM_FORMAT_XRGB2101010,
> +	DRM_FORMAT_ARGB2101010,
> +	DRM_FORMAT_XBGR2101010,
> +	DRM_FORMAT_ABGR2101010,
> +	DRM_FORMAT_NV12,
> +};

This duplication is a bit unpretty, and we already started to share code
with skl sprites to prep for the great unification of plane code for
gen9+. Can you please do the same with these tables? I also like the names
in intel_sprite.c more. Follow-up patch or squashed in both ok.
-Daniel

> +
>  /* Cursor formats */
>  static const uint32_t intel_cursor_formats[] = {
>  	DRM_FORMAT_ARGB8888,
> @@ -13204,6 +13226,14 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
>  	if (INTEL_INFO(dev)->gen <= 3) {
>  		intel_primary_formats = intel_primary_formats_gen2;
>  		num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
> +	} else if (INTEL_INFO(dev)->gen >= 9) {
> +		if (pipe == PIPE_A || pipe == PIPE_B) {
> +			intel_primary_formats = intel_primary_formats_with_nv12_gen9;
> +			num_formats = ARRAY_SIZE(intel_primary_formats_with_nv12_gen9);
> +		} else {
> +			intel_primary_formats = intel_primary_formats_gen9;
> +			num_formats = ARRAY_SIZE(intel_primary_formats_gen9);
> +		}
>  	} else {
>  		intel_primary_formats = intel_primary_formats_gen4;
>  		num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 09/11] drm/i915: Update compute_baseline_bpp for NV12.

[Daniel Vetter]

On Thu, Apr 30, 2015 at 08:43:13PM -0700, Chandra Konduru wrote:
> This patch updates baseline bpp when primary plane
> is running with NV12. It is same as 8-bpc RGB formats
> because NV12 also has 8-bits per channel.
> 
> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>

This code was removed in

commit d328c9d78d64ca11e744fe227096990430a88477
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Fri Apr 10 16:22:37 2015 +0200

    drm/i915: Select starting pipe bpp irrespective or the primary plane

Please rebase onto latest -nightly before submitting to check for such
things.

Thanks, Daniel
> ---
>  drivers/gpu/drm/i915/intel_display.c |    1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 6e693c4..e747766 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10845,6 +10845,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
>  			return -EINVAL;
>  	case DRM_FORMAT_XRGB8888:
>  	case DRM_FORMAT_ARGB8888:
> +	case DRM_FORMAT_NV12:
>  		bpp = 8*3;
>  		break;
>  	case DRM_FORMAT_XRGB2101010:
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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http://blog.ffwll.ch
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Re: [PATCH 09/11] drm/i915: Update compute_baseline_bpp for NV12.

[Konduru, Chandra]

> -----Original Message-----
> From: Daniel Vetter [mailto:daniel.vetter@ffwll.ch] On Behalf Of Daniel Vetter
> Sent: Wednesday, May 06, 2015 11:59 PM
> To: Konduru, Chandra
> Cc: intel-gfx@lists.freedesktop.org; Vetter, Daniel; Syrjala, Ville
> Subject: Re: [Intel-gfx] [PATCH 09/11] drm/i915: Update compute_baseline_bpp
> for NV12.
> 
> On Thu, Apr 30, 2015 at 08:43:13PM -0700, Chandra Konduru wrote:
> > This patch updates baseline bpp when primary plane is running with
> > NV12. It is same as 8-bpc RGB formats because NV12 also has 8-bits per
> > channel.
> >
> > Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> 
> This code was removed in
> 
> commit d328c9d78d64ca11e744fe227096990430a88477
> Author: Daniel Vetter <daniel.vetter@ffwll.ch>
> Date:   Fri Apr 10 16:22:37 2015 +0200
> 
>     drm/i915: Select starting pipe bpp irrespective or the primary plane
> 
> Please rebase onto latest -nightly before submitting to check for such things.
Will do. This patch (09/11) can be ignored as we are no more setting baseline
bpp based on pixel format.

> 
> Thanks, Daniel
> > ---
> >  drivers/gpu/drm/i915/intel_display.c |    1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 6e693c4..e747766 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -10845,6 +10845,7 @@ compute_baseline_pipe_bpp(struct intel_crtc
> *crtc,
> >  			return -EINVAL;
> >  	case DRM_FORMAT_XRGB8888:
> >  	case DRM_FORMAT_ARGB8888:
> > +	case DRM_FORMAT_NV12:
> >  		bpp = 8*3;
> >  		break;
> >  	case DRM_FORMAT_XRGB2101010:
> > --
> > 1.7.9.5
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
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Re: [PATCH 06/11] drm/i915: Add NV12 as supported format for primary plane

[Konduru, Chandra]

> > +/* Primary plane formats for gen >= 9 */
> > +static const uint32_t intel_primary_formats_gen9[] = {
> > +	COMMON_PRIMARY_FORMATS, \
> > +	DRM_FORMAT_XBGR8888,
> > +	DRM_FORMAT_ABGR8888,
> > +	DRM_FORMAT_XRGB2101010,
> > +	DRM_FORMAT_ARGB2101010,
> > +	DRM_FORMAT_XBGR2101010,
> > +	DRM_FORMAT_ABGR2101010,
> > +};
> > +
> > +static const uint32_t intel_primary_formats_with_nv12_gen9[] = {
> > +	COMMON_PRIMARY_FORMATS, \
> > +	DRM_FORMAT_XBGR8888,
> > +	DRM_FORMAT_ABGR8888,
> > +	DRM_FORMAT_XRGB2101010,
> > +	DRM_FORMAT_ARGB2101010,
> > +	DRM_FORMAT_XBGR2101010,
> > +	DRM_FORMAT_ABGR2101010,
> > +	DRM_FORMAT_NV12,
> > +};
> 
> This duplication is a bit unpretty, and we already started to share code
> with skl sprites to prep for the great unification of plane code for
> gen9+. Can you please do the same with these tables? I also like the names
> in intel_sprite.c more. Follow-up patch or squashed in both ok.
> -Daniel
Hi Daniel,
I planned to have single list with nv12 at the end of the list.
And in plane_init report the list as is for nv12 capable planes and
index-1 for non-nv12 planes.
But the earlier (a while ago) feedback from you is, duplication is
cheaper so duplicated them instead of playing trick with array index.
 
Regarding unification, currently skl_plane_formats[] has different formats 
than intel_primary_formats_gen9[]. To have a unified table for both primary
and sprite planes requires testing delta formats on both primary and sprite
planes respectively with respective i-g-t tests. This is not being planned as 
part of nv12 feature.

> 

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Re: [PATCH 06/11] drm/i915: Add NV12 as supported format for primary plane

[Daniel Vetter]

On Fri, May 08, 2015 at 02:29:30AM +0000, Konduru, Chandra wrote:
> > > +/* Primary plane formats for gen >= 9 */
> > > +static const uint32_t intel_primary_formats_gen9[] = {
> > > +	COMMON_PRIMARY_FORMATS, \
> > > +	DRM_FORMAT_XBGR8888,
> > > +	DRM_FORMAT_ABGR8888,
> > > +	DRM_FORMAT_XRGB2101010,
> > > +	DRM_FORMAT_ARGB2101010,
> > > +	DRM_FORMAT_XBGR2101010,
> > > +	DRM_FORMAT_ABGR2101010,
> > > +};
> > > +
> > > +static const uint32_t intel_primary_formats_with_nv12_gen9[] = {
> > > +	COMMON_PRIMARY_FORMATS, \
> > > +	DRM_FORMAT_XBGR8888,
> > > +	DRM_FORMAT_ABGR8888,
> > > +	DRM_FORMAT_XRGB2101010,
> > > +	DRM_FORMAT_ARGB2101010,
> > > +	DRM_FORMAT_XBGR2101010,
> > > +	DRM_FORMAT_ABGR2101010,
> > > +	DRM_FORMAT_NV12,
> > > +};
> > 
> > This duplication is a bit unpretty, and we already started to share code
> > with skl sprites to prep for the great unification of plane code for
> > gen9+. Can you please do the same with these tables? I also like the names
> > in intel_sprite.c more. Follow-up patch or squashed in both ok.
> > -Daniel
> Hi Daniel,
> I planned to have single list with nv12 at the end of the list.
> And in plane_init report the list as is for nv12 capable planes and
> index-1 for non-nv12 planes.
> But the earlier (a while ago) feedback from you is, duplication is
> cheaper so duplicated them instead of playing trick with array index.
>  
> Regarding unification, currently skl_plane_formats[] has different formats 
> than intel_primary_formats_gen9[]. To have a unified table for both primary
> and sprite planes requires testing delta formats on both primary and sprite
> planes respectively with respective i-g-t tests. This is not being planned as 
> part of nv12 feature.

Well someone eventually needs to do it, I hoped I could sign you up for
that ;-)
-Daniel
-- 
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[PATCH 10/11] drm/i915: Add NV12 to primary plane programming.

[Chandra Konduru]

This patch is adding NV12 support to skylake primary plane
programming. It is covering linear/X/Y/Yf tiling formats
for 0 and 180 rotations.

For 90/270 rotation, Y and UV subplanes should be treated
as separate surfaces and GTT remapping for rotation should
be done separately for each subplane. Once GEM adds support
for seperate remappings for two subplanes, 90/270 support
to be added to plane programming.

v2:
-Use regular int instead of 16.16 in aux_offset calculations (me)

Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Testcase: igt/kms_nv12
---
 drivers/gpu/drm/i915/intel_atomic_plane.c |    2 ++
 drivers/gpu/drm/i915/intel_display.c      |   38 +++++++++++++++++++++++++++++
 2 files changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 86ba4b2..119439d 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -185,10 +185,12 @@ static int intel_plane_atomic_check(struct drm_plane *plane,
 		 * 90/270 is not allowed with RGB64 16:16:16:16,
 		 * RGB 16-bit 5:6:5, and Indexed 8-bit.
 		 * TBD: Add RGB64 case once its added in supported format list.
+		 * TBD: Remove NV12, once its 90/270 remapping is supported
 		 */
 		switch (state->fb->pixel_format) {
 		case DRM_FORMAT_C8:
 		case DRM_FORMAT_RGB565:
+		case DRM_FORMAT_NV12:
 			DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
 					drm_get_format_name(state->fb->pixel_format));
 			return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3ae646e..943a835 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3015,6 +3015,9 @@ u32 skl_plane_ctl_format(uint32_t pixel_format)
 	case DRM_FORMAT_VYUY:
 		plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
 		break;
+	case DRM_FORMAT_NV12:
+		plane_ctl_format = PLANE_CTL_FORMAT_NV12;
+		break;
 	default:
 		BUG();
 	}
@@ -3085,6 +3088,8 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
 	int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
 	int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
 	int scaler_id = -1;
+	u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
+	u32 tile_row_adjustment = 0;
 
 	plane_state = to_intel_plane_state(plane->state);
 
@@ -3141,11 +3146,34 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
 		x_offset = stride * tile_height - y - src_h;
 		y_offset = x;
 		plane_size = (src_w - 1) << 16 | (src_h - 1);
+		/*
+		 * TBD: For NV12 90/270 rotation, Y and UV subplanes should
+		 * be treated as separate surfaces and GTT remapping for
+		 * rotation should be done separately for each subplane.
+		 * Enable support once seperate remappings are available.
+		 */
 	} else {
 		stride = fb->pitches[0] / stride_div;
 		x_offset = x;
 		y_offset = y;
 		plane_size = (src_h - 1) << 16 | (src_w - 1);
+		tile_height = PAGE_SIZE / stride_div;
+
+		if (fb->pixel_format == DRM_FORMAT_NV12) {
+			int height_in_mem = (fb->offsets[1]/fb->pitches[0]);
+			/*
+			 * If UV starts from middle of a page, then UV start should
+			 * be programmed to beginning of that page. And offset into that
+			 * page to be programmed into y-offset
+			 */
+			tile_row_adjustment = height_in_mem % tile_height;
+			aux_dist = fb->pitches[0] * (height_in_mem - tile_row_adjustment);
+			aux_x_offset = DIV_ROUND_UP(x, 2);
+			aux_y_offset = DIV_ROUND_UP(y, 2) + tile_row_adjustment;
+			/* For tile-Yf, uv-subplane tile width is 2x of Y-subplane */
+			aux_stride = fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED ?
+				stride / 2 : stride;
+		}
 	}
 	plane_offset = y_offset << 16 | x_offset;
 
@@ -3153,11 +3181,14 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
 	I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
 	I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
 	I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
+	I915_WRITE(PLANE_AUX_DIST(pipe, 0), aux_dist | aux_stride);
+	I915_WRITE(PLANE_AUX_OFFSET(pipe, 0), aux_y_offset << 16 | aux_x_offset);
 
 	if (scaler_id >= 0) {
 		uint32_t ps_ctrl = 0;
 
 		WARN_ON(!dst_w || !dst_h);
+
 		ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
 			crtc_state->scaler_state.scalers[scaler_id].mode;
 		I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
@@ -3166,6 +3197,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
 		I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
 		I915_WRITE(PLANE_POS(pipe, 0), 0);
 	} else {
+		WARN_ON(fb->pixel_format == DRM_FORMAT_NV12);
 		I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
 	}
 
@@ -13090,6 +13122,12 @@ intel_check_primary_plane(struct drm_plane *plane,
 			intel_crtc->atomic.update_wm = true;
 	}
 
+	/* Adjust (macro)pixel boundary */
+	if (fb && format_is_yuv(fb->pixel_format)) {
+		src->x1 &= ~0x10000;
+		src->x2 &= ~0x10000;
+	}
+
 	if (INTEL_INFO(dev)->gen >= 9) {
 		ret = skl_update_scaler_users(intel_crtc, crtc_state,
 			to_intel_plane(plane), state, 0);
-- 
1.7.9.5

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Re: [PATCH 10/11] drm/i915: Add NV12 to primary plane programming.

[Tvrtko Ursulin]

Hi,

On 05/08/2015 09:40 PM, Chandra Konduru wrote:
> This patch is adding NV12 support to skylake primary plane
> programming. It is covering linear/X/Y/Yf tiling formats
> for 0 and 180 rotations.
> 
> For 90/270 rotation, Y and UV subplanes should be treated
> as separate surfaces and GTT remapping for rotation should
> be done separately for each subplane. Once GEM adds support
> for seperate remappings for two subplanes, 90/270 support
> to be added to plane programming.
> 
> v2:
> -Use regular int instead of 16.16 in aux_offset calculations (me)
> 
> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> Testcase: igt/kms_nv12
> ---
>   drivers/gpu/drm/i915/intel_atomic_plane.c |    2 ++
>   drivers/gpu/drm/i915/intel_display.c      |   38 +++++++++++++++++++++++++++++
>   2 files changed, 40 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index 86ba4b2..119439d 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -185,10 +185,12 @@ static int intel_plane_atomic_check(struct drm_plane *plane,
>   		 * 90/270 is not allowed with RGB64 16:16:16:16,
>   		 * RGB 16-bit 5:6:5, and Indexed 8-bit.
>   		 * TBD: Add RGB64 case once its added in supported format list.
> +		 * TBD: Remove NV12, once its 90/270 remapping is supported
>   		 */
>   		switch (state->fb->pixel_format) {
>   		case DRM_FORMAT_C8:
>   		case DRM_FORMAT_RGB565:
> +		case DRM_FORMAT_NV12:
>   			DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
>   					drm_get_format_name(state->fb->pixel_format));
>   			return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3ae646e..943a835 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3015,6 +3015,9 @@ u32 skl_plane_ctl_format(uint32_t pixel_format)
>   	case DRM_FORMAT_VYUY:
>   		plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
>   		break;
> +	case DRM_FORMAT_NV12:
> +		plane_ctl_format = PLANE_CTL_FORMAT_NV12;
> +		break;
>   	default:
>   		BUG();
>   	}
> @@ -3085,6 +3088,8 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
>   	int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
>   	int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
>   	int scaler_id = -1;
> +	u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0;
> +	u32 tile_row_adjustment = 0;
>   
>   	plane_state = to_intel_plane_state(plane->state);
>   
> @@ -3141,11 +3146,34 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
>   		x_offset = stride * tile_height - y - src_h;
>   		y_offset = x;
>   		plane_size = (src_w - 1) << 16 | (src_h - 1);
> +		/*
> +		 * TBD: For NV12 90/270 rotation, Y and UV subplanes should
> +		 * be treated as separate surfaces and GTT remapping for
> +		 * rotation should be done separately for each subplane.
> +		 * Enable support once seperate remappings are available.
> +		 */
>   	} else {
>   		stride = fb->pitches[0] / stride_div;
>   		x_offset = x;
>   		y_offset = y;
>   		plane_size = (src_h - 1) << 16 | (src_w - 1);
> +		tile_height = PAGE_SIZE / stride_div;
> +
> +		if (fb->pixel_format == DRM_FORMAT_NV12) {
> +			int height_in_mem = (fb->offsets[1]/fb->pitches[0]);
> +			/*
> +			 * If UV starts from middle of a page, then UV start should
> +			 * be programmed to beginning of that page. And offset into that
> +			 * page to be programmed into y-offset
> +			 */
> +			tile_row_adjustment = height_in_mem % tile_height;
> +			aux_dist = fb->pitches[0] * (height_in_mem - tile_row_adjustment);
> +			aux_x_offset = DIV_ROUND_UP(x, 2);
> +			aux_y_offset = DIV_ROUND_UP(y, 2) + tile_row_adjustment;
> +			/* For tile-Yf, uv-subplane tile width is 2x of Y-subplane */
> +			aux_stride = fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED ?
> +				stride / 2 : stride;
> +		}
>   	}
>   	plane_offset = y_offset << 16 | x_offset;
>   
> @@ -3153,11 +3181,14 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
>   	I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
>   	I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
>   	I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
> +	I915_WRITE(PLANE_AUX_DIST(pipe, 0), aux_dist | aux_stride);
> +	I915_WRITE(PLANE_AUX_OFFSET(pipe, 0), aux_y_offset << 16 | aux_x_offset);
>   
>   	if (scaler_id >= 0) {
>   		uint32_t ps_ctrl = 0;
>   
>   		WARN_ON(!dst_w || !dst_h);
> +
>   		ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
>   			crtc_state->scaler_state.scalers[scaler_id].mode;
>   		I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
> @@ -3166,6 +3197,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
>   		I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
>   		I915_WRITE(PLANE_POS(pipe, 0), 0);
>   	} else {
> +		WARN_ON(fb->pixel_format == DRM_FORMAT_NV12);
>   		I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);

I've hit this WARN_ON with kms_rotation_crc by just changing the format of frame buffers
it creates to NV12 (so even before any rotation happens). Small snippet:

[  906.408194] [drm:skl_update_scaler_users] PLANE:17 staged scaling request for 3200x1800->3200x1800 crtc_state = ffff880037348800 scaler_users = 0x1
[  906.436759] ------------[ cut here ]------------
[  906.442107] WARNING: CPU: 0 PID: 1709 at drivers/gpu/drm/i915/intel_display.c:3225 skylake_update_primary_plane+0x678/0x6e0 [i915]()
[  906.455620] WARN_ON(fb->pixel_format == DRM_FORMAT_NV12)
[  906.461451] Modules linked in: coretemp i915 drm_kms_helper drm i2c_algo_bit i2c_hid video pinctrl_sunrisepoint pinctrl_intel acpi_pad nls_iso8859_1 hid_generic usbhid hid e1000e ptp psmouse ahci pps_core libahci
[  906.483472] CPU: 0 PID: 1709 Comm: kms_rotation_cr Tainted: G     U  W       4.1.0-rc3-150511+ #12
[  906.493638] Hardware name: Intel Corporation Skylake Client platform/Skylake Y LPDDR3 RVP3, BIOS SKLSE2R1.86C.X070.R01.1501282110 01/28/2015
[  906.507938]  0000000000000c99 ffff88009bc979a8 ffffffff8161283d 0000000000000007
[  906.516410]  ffff88009bc979f8 ffff88009bc979e8 ffffffff81050062 ffff88009acd0000
[  906.524874]  ffff88009acd0000 ffff8800372356c0 0000000000000000 00000000c1802000
[  906.533341] Call Trace:
[  906.536135]  [<ffffffff8161283d>] dump_stack+0x4c/0x6e
[  906.541979]  [<ffffffff81050062>] warn_slowpath_common+0xb2/0xe0
[  906.548802]  [<ffffffff81050146>] warn_slowpath_fmt+0x46/0x50
[  906.555408]  [<ffffffffa0242cf8>] skylake_update_primary_plane+0x678/0x6e0 [i915]
[  906.563980]  [<ffffffffa023cca3>] intel_commit_primary_plane+0x93/0xb0 [i915]
[  906.572158]  [<ffffffffa025fa49>] intel_plane_atomic_update+0x19/0x20 [i915]
[  906.580180]  [<ffffffffa01b026a>] drm_atomic_helper_commit_planes+0x17a/0x210 [drm_kms_helper]
[  906.590029]  [<ffffffffa0245de3>] __intel_set_mode+0xbf3/0xcd0 [i915]
[  906.597418]  [<ffffffffa024bdae>] intel_crtc_set_config+0x4ee/0x650 [i915]
[  906.605277]  [<ffffffffa014b549>] drm_mode_set_config_internal+0x69/0x120 [drm]
[  906.613618]  [<ffffffffa0150b48>] drm_mode_setcrtc+0x558/0x650 [drm]
[  906.620856]  [<ffffffffa0140f19>] drm_ioctl+0x3f9/0x650 [drm]
[  906.627419]  [<ffffffffa01505f0>] ? drm_mode_setplane+0x200/0x200 [drm]
[  906.634939]  [<ffffffff8116a1f3>] do_vfs_ioctl+0x543/0x5a0
[  906.641170]  [<ffffffff810a8576>] ? rcu_eqs_exit+0x96/0xb0
[  906.647408]  [<ffffffff81095f2d>] ? trace_hardirqs_on+0xd/0x10
[  906.654038]  [<ffffffff81175cd7>] ? __fget_light+0x57/0xa0
[  906.660271]  [<ffffffff8116a29c>] SyS_ioctl+0x4c/0x90
[  906.666031]  [<ffffffff8161aed7>] system_call_fastpath+0x12/0x6f
[  906.672854] ---[ end trace 599568c0e80eee2a ]---
[  906.678235] [drm:intel_pipe_update_end [i915]] *ERROR* Atomic update failure on pipe A (start=10907 end=10921)
[  906.679305] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe A FIFO underrun

Machine even hard hangs in the process. Either way, it is probably bad that userspace can hit
this WARN_ON just by trying to display a NV12 frame buffer.

Regards,

Tvrtko
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Re: [PATCH 08/11] drm/i915: Add NV12 support to intel_framebuffer_init

[Tvrtko Ursulin]

Hi,

On 05/01/2015 04:43 AM, Chandra Konduru wrote:
> This patch adds NV12 as supported format to
> intel_framebuffer_init and performs various checks.
> 
> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> Testcase: igt/kms_nv12
> ---
>   drivers/gpu/drm/i915/intel_display.c |   27 +++++++++++++++++++++++++++
>   1 file changed, 27 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d3773d2..6e693c4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13953,6 +13953,33 @@ static int intel_framebuffer_init(struct drm_device *dev,
>   			return -EINVAL;
>   		}
>   		break;
> +	case DRM_FORMAT_NV12:
> +		if (INTEL_INFO(dev)->gen < 9) {
> +			DRM_DEBUG("unsupported pixel format: %s\n",
> +				  drm_get_format_name(mode_cmd->pixel_format));
> +			return -EINVAL;
> +		}
> +		if (!mode_cmd->offsets[1]) {
> +			DRM_DEBUG("uv start offset not set\n");
> +			return -EINVAL;
> +		}
> +		if (mode_cmd->pitches[0] != mode_cmd->pitches[1] ||
> +			mode_cmd->handles[0] != mode_cmd->handles[1]) {
> +			DRM_DEBUG("y and uv subplanes have different parameters\n");
> +			return -EINVAL;
> +		}
> +		if (mode_cmd->modifier[1] == I915_FORMAT_MOD_Yf_TILED &&
> +			(mode_cmd->offsets[1] & 0xFFF)) {
> +			DRM_DEBUG("tile-Yf uv offset 0x%x isn't starting on new tile-row\n",
> +				mode_cmd->offsets[1]);
> +			return -EINVAL;
> +		}
> +		if (mode_cmd->modifier[1] == I915_FORMAT_MOD_Y_TILED &&
> +			((mode_cmd->offsets[1] % mode_cmd->pitches[1]) % 4)) {
> +			DRM_DEBUG("tile-Y uv offset 0x%x isn't 4-line aligned\n",
> +				mode_cmd->offsets[1]);
> +		}
> +		break;
>   	default:
>   		DRM_DEBUG("unsupported pixel format: %s\n",
>   			  drm_get_format_name(mode_cmd->pixel_format));
> 

I've noticed a bunch of:

[  566.106745] [drm:drm_mode_addfb2] [FB:58]
[  566.111384] [drm:drm_fb_get_bpp_depth] unsupported pixel format NV12 little-endian (0x3231564e)
[  566.121283] [drm:drm_mode_addfb2] [FB:59]
[  566.125912] [drm:drm_fb_get_bpp_depth] unsupported pixel format NV12 little-endian (0x3231564e)

And on investigating, they probably come from drm_helper_mode_fill_fb_struct
in intel_framebuffer_init.

Result is that fb->depth and fb->bits_per_pixel will be zero, which can't be good. :)

Anyway, looks like this needs some additional work to make NV12 really supported.

Regards,

Tvrtko
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Re: [PATCH 08/11] drm/i915: Add NV12 support to intel_framebuffer_init

[Ville Syrjälä]

On Mon, May 11, 2015 at 11:54:11AM +0100, Tvrtko Ursulin wrote:
> 
> Hi,
> 
> On 05/01/2015 04:43 AM, Chandra Konduru wrote:
> > This patch adds NV12 as supported format to
> > intel_framebuffer_init and performs various checks.
> > 
> > Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> > Testcase: igt/kms_nv12
> > ---
> >   drivers/gpu/drm/i915/intel_display.c |   27 +++++++++++++++++++++++++++
> >   1 file changed, 27 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index d3773d2..6e693c4 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -13953,6 +13953,33 @@ static int intel_framebuffer_init(struct drm_device *dev,
> >   			return -EINVAL;
> >   		}
> >   		break;
> > +	case DRM_FORMAT_NV12:
> > +		if (INTEL_INFO(dev)->gen < 9) {
> > +			DRM_DEBUG("unsupported pixel format: %s\n",
> > +				  drm_get_format_name(mode_cmd->pixel_format));
> > +			return -EINVAL;
> > +		}
> > +		if (!mode_cmd->offsets[1]) {
> > +			DRM_DEBUG("uv start offset not set\n");
> > +			return -EINVAL;
> > +		}
> > +		if (mode_cmd->pitches[0] != mode_cmd->pitches[1] ||
> > +			mode_cmd->handles[0] != mode_cmd->handles[1]) {
> > +			DRM_DEBUG("y and uv subplanes have different parameters\n");
> > +			return -EINVAL;
> > +		}
> > +		if (mode_cmd->modifier[1] == I915_FORMAT_MOD_Yf_TILED &&
> > +			(mode_cmd->offsets[1] & 0xFFF)) {
> > +			DRM_DEBUG("tile-Yf uv offset 0x%x isn't starting on new tile-row\n",
> > +				mode_cmd->offsets[1]);
> > +			return -EINVAL;
> > +		}
> > +		if (mode_cmd->modifier[1] == I915_FORMAT_MOD_Y_TILED &&
> > +			((mode_cmd->offsets[1] % mode_cmd->pitches[1]) % 4)) {
> > +			DRM_DEBUG("tile-Y uv offset 0x%x isn't 4-line aligned\n",
> > +				mode_cmd->offsets[1]);
> > +		}
> > +		break;
> >   	default:
> >   		DRM_DEBUG("unsupported pixel format: %s\n",
> >   			  drm_get_format_name(mode_cmd->pixel_format));
> > 
> 
> I've noticed a bunch of:
> 
> [  566.106745] [drm:drm_mode_addfb2] [FB:58]
> [  566.111384] [drm:drm_fb_get_bpp_depth] unsupported pixel format NV12 little-endian (0x3231564e)
> [  566.121283] [drm:drm_mode_addfb2] [FB:59]
> [  566.125912] [drm:drm_fb_get_bpp_depth] unsupported pixel format NV12 little-endian (0x3231564e)
> 
> And on investigating, they probably come from drm_helper_mode_fill_fb_struct
> in intel_framebuffer_init.
> 
> Result is that fb->depth and fb->bits_per_pixel will be zero, which can't be good. :)

Actually it is good. We have the same situation with all YCbCr formats.

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 00/11] Skylake display NV12 feature addition

[Konduru, Chandra]

Hi,
I have seen review comments from you and addressed/responded to them.
Can you please give R-b tag?

-Chandra

> -----Original Message-----
> From: Konduru, Chandra
> Sent: Thursday, April 30, 2015 8:43 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Konduru, Chandra; Vetter, Daniel; Lespiau, Damien; Syrjala, Ville
> Subject: [PATCH 00/11] Skylake display NV12 feature addition
> 
> This patch series adding NV12 support for Skylake display.
> Feature is tested with igt/kms_nv12 testcase.
> I will be sending the igt patches shortly.
> 
> Feature is unit tested for linear/X/Y/Yf formats in 0 and 180 orientations with
> combinations of 1, 2 or 3 planes enabled along with scaling. Also negatively
> tested for enabling NV12 on unsupported plane.
> 
> Chandra Konduru (11):
>   drm/i915: Add register definitions for NV12 support
>   drm/i915: Set scaler mode for NV12
>   drm/i915: Stage scaler request for NV12 as src format
>   drm/i915: Update format_is_yuv() to include NV12
>   drm/i915: Upscale scaler max scale for NV12.
>   drm/i915: Add NV12 as supported format for primary plane
>   drm/i915: Add NV12 as supported format for sprite plane
>   drm/i915: Add NV12 support to intel_framebuffer_init
>   drm/i915: Update compute_baseline_bpp for NV12.
>   drm/i915: Add NV12 to primary plane programming.
>   drm/i915: Add NV12 to sprite plane programming.
> 
>  drivers/gpu/drm/i915/i915_reg.h           |   27 +++++++
>  drivers/gpu/drm/i915/intel_atomic.c       |    5 +-
>  drivers/gpu/drm/i915/intel_atomic_plane.c |    2 +
>  drivers/gpu/drm/i915/intel_display.c      |  120
> +++++++++++++++++++++++++++--
>  drivers/gpu/drm/i915/intel_drv.h          |    4 +-
>  drivers/gpu/drm/i915/intel_sprite.c       |   59 ++++++++++++--
>  6 files changed, 201 insertions(+), 16 deletions(-)
> 
> --
> 1.7.9.5

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Re: [PATCH 00/11] Skylake display NV12 feature addition

[Tvrtko Ursulin]

On 05/14/2015 06:13 AM, Konduru, Chandra wrote:
> Hi,
> I have seen review comments from you and addressed/responded to them.
> Can you please give R-b tag?

What about that WARN_ON(fb->pixel_format == DRM_FORMAT_NV12) I am 
hitting (and subsequent hard hang)? Were you able to repro that?

I did rebase your series on latest nightly but it was very trivial if 
anything so I don't think I did something wrong there.

Regards,

Tvrtko
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Re: [PATCH 00/11] Skylake display NV12 feature addition

[Konduru, Chandra]

> -----Original Message-----
> From: Tvrtko Ursulin [mailto:tvrtko.ursulin@linux.intel.com]
> Sent: Thursday, May 14, 2015 5:47 AM
> To: Konduru, Chandra; Vetter, Daniel; Lespiau, Damien; Syrjala, Ville
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 00/11] Skylake display NV12 feature addition
> 
> 
> On 05/14/2015 06:13 AM, Konduru, Chandra wrote:
> > Hi,
> > I have seen review comments from you and addressed/responded to them.
> > Can you please give R-b tag?
> 
> What about that WARN_ON(fb->pixel_format == DRM_FORMAT_NV12) I am
> hitting (and subsequent hard hang)? Were you able to repro that?
> 
> I did rebase your series on latest nightly but it was very trivial if anything so I
> don't think I did something wrong there.

I was able to reproduce the issue and found the root-cause. 
The required steps to reproduce this issue requires NV12 as primary plane format
via drmModeCrtcSetConfig() and the way you modified kms_rotation_crc is just
doing that. In crtc set config flow the way atomic commit planes called
without atomic commit call. So, it is missing setupscalers required for NV12.
And the WARN_ON I added is catching this scenario.

Though this may be not common, it requires proper handling in i915.
I just send combined NV12 patch series for 0/180 and 90/270 including addressing
this issue.  
Can you please check at your end with updated series?

By the way, you need latest drm-intel-nightly, then apply your GEM remapping
for NV12 patches (2 to 7 of 8, 8th not required. And 1st one is already merged), 
then apply my series (12 of 12).

> 
> Regards,
> 
> Tvrtko
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Re: [PATCH 00/11] Skylake display NV12 feature addition

[Tvrtko Ursulin]

Hi,

On 05/18/2015 06:24 AM, Konduru, Chandra wrote:
>> -----Original Message-----
>> From: Tvrtko Ursulin [mailto:tvrtko.ursulin@linux.intel.com]
>> Sent: Thursday, May 14, 2015 5:47 AM
>> To: Konduru, Chandra; Vetter, Daniel; Lespiau, Damien; Syrjala, Ville
>> Cc: intel-gfx@lists.freedesktop.org
>> Subject: Re: [Intel-gfx] [PATCH 00/11] Skylake display NV12 feature addition
>>
>>
>> On 05/14/2015 06:13 AM, Konduru, Chandra wrote:
>>> Hi,
>>> I have seen review comments from you and addressed/responded to them.
>>> Can you please give R-b tag?
>>
>> What about that WARN_ON(fb->pixel_format == DRM_FORMAT_NV12) I am
>> hitting (and subsequent hard hang)? Were you able to repro that?
>>
>> I did rebase your series on latest nightly but it was very trivial if anything so I
>> don't think I did something wrong there.
>
> I was able to reproduce the issue and found the root-cause.
> The required steps to reproduce this issue requires NV12 as primary plane format
> via drmModeCrtcSetConfig() and the way you modified kms_rotation_crc is just
> doing that. In crtc set config flow the way atomic commit planes called
> without atomic commit call. So, it is missing setupscalers required for NV12.
> And the WARN_ON I added is catching this scenario.
>
> Though this may be not common, it requires proper handling in i915.
> I just send combined NV12 patch series for 0/180 and 90/270 including addressing
> this issue.
> Can you please check at your end with updated series?
>
> By the way, you need latest drm-intel-nightly, then apply your GEM remapping
> for NV12 patches (2 to 7 of 8, 8th not required. And 1st one is already merged),
> then apply my series (12 of 12).

Warn is gone but my box still locks up hard.

I can even reproduce the lockup by running nv12-plane-linear subtest 
from kms_nv12, where it happens perhaps on the second run. May be more 
easily triggerable with drm.debug=0 - but I am not so confident about that.

And also with nv12-plane-linear I see FIFO underruns so perhaps wm 
programming is not fully OK for NV12?

Regards,

Tvrtko
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Re: [PATCH 00/11] Skylake display NV12 feature addition

[Konduru, Chandra]

> -----Original Message-----
> From: Tvrtko Ursulin [mailto:tvrtko.ursulin@linux.intel.com]
> Sent: Monday, May 18, 2015 3:43 AM
> To: Konduru, Chandra; Vetter, Daniel; Lespiau, Damien; Syrjala, Ville
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 00/11] Skylake display NV12 feature addition
> 
> 
> Hi,
> 
> On 05/18/2015 06:24 AM, Konduru, Chandra wrote:
> >> -----Original Message-----
> >> From: Tvrtko Ursulin [mailto:tvrtko.ursulin@linux.intel.com]
> >> Sent: Thursday, May 14, 2015 5:47 AM
> >> To: Konduru, Chandra; Vetter, Daniel; Lespiau, Damien; Syrjala, Ville
> >> Cc: intel-gfx@lists.freedesktop.org
> >> Subject: Re: [Intel-gfx] [PATCH 00/11] Skylake display NV12 feature
> >> addition
> >>
> >>
> >> On 05/14/2015 06:13 AM, Konduru, Chandra wrote:
> >>> Hi,
> >>> I have seen review comments from you and addressed/responded to them.
> >>> Can you please give R-b tag?
> >>
> >> What about that WARN_ON(fb->pixel_format == DRM_FORMAT_NV12) I am
> >> hitting (and subsequent hard hang)? Were you able to repro that?
> >>
> >> I did rebase your series on latest nightly but it was very trivial if
> >> anything so I don't think I did something wrong there.
> >
> > I was able to reproduce the issue and found the root-cause.
> > The required steps to reproduce this issue requires NV12 as primary
> > plane format via drmModeCrtcSetConfig() and the way you modified
> > kms_rotation_crc is just doing that. In crtc set config flow the way
> > atomic commit planes called without atomic commit call. So, it is missing
> setupscalers required for NV12.
> > And the WARN_ON I added is catching this scenario.
> >
> > Though this may be not common, it requires proper handling in i915.
> > I just send combined NV12 patch series for 0/180 and 90/270 including
> > addressing this issue.
> > Can you please check at your end with updated series?
> >
> > By the way, you need latest drm-intel-nightly, then apply your GEM
> > remapping for NV12 patches (2 to 7 of 8, 8th not required. And 1st one
> > is already merged), then apply my series (12 of 12).
> 
> Warn is gone but my box still locks up hard.
Good.
> 
> I can even reproduce the lockup by running nv12-plane-linear subtest from
> kms_nv12, where it happens perhaps on the second run. May be more easily
> triggerable with drm.debug=0 - but I am not so confident about that.

I have been testing on two boards, and on one board (A step), issue never happens
i.e., no lockups. On the other board (C step), issue happens. I tried chicken bit 
workarounds for C, but still seeing issue. Debugging what is causing lockup.

On another note, when I tested earlier with 400rc3 kernel, I didn't see these lockups
but after moving to 410rc2 started seeing them. So combination of NV12 and
whatever happened in kernel upgrade is causing lockup (at least that' how it appears
now). And this only happens on board (C) not on (A).

> 
> And also with nv12-plane-linear I see FIFO underruns so perhaps wm
> programming is not fully OK for NV12?
Looking at wm programming to rule out that is the case.
> 
> Regards,
> 
> Tvrtko
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