* [PATCH v7 3/8] vt82c686: Add VT8231_SUPERIO based on VIA_SUPERIO
2021-03-10 2:58 [PATCH v7 0/8] Pegasos2 emulation BALATON Zoltan
@ 2021-03-10 2:58 ` BALATON Zoltan
2021-03-10 2:58 ` [PATCH v7 2/8] vt82c686: QOM-ify superio related functionality BALATON Zoltan
` (7 subsequent siblings)
8 siblings, 0 replies; 32+ messages in thread
From: BALATON Zoltan @ 2021-03-10 2:58 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Peter Maydell, Paolo Bonzini, f4bug, David Gibson
The VT8231 south bridge is very similar to VT82C686B but there are
some differences in register addresses and functionality, e.g. the
VT8231 only has one serial port. This commit adds VT8231_SUPERIO
subclass based on the abstract VIA_SUPERIO class to emulate the
superio part of VT8231.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/isa/vt82c686.c | 121 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 121 insertions(+)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index e89dbf43da..8131cb42a9 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -491,6 +491,126 @@ static const TypeInfo vt82c686b_superio_info = {
};
+#define TYPE_VT8231_SUPERIO "vt8231-superio"
+
+static void vt8231_superio_cfg_write(void *opaque, hwaddr addr,
+ uint64_t data, unsigned size)
+{
+ ViaSuperIOState *sc = opaque;
+ uint8_t idx = sc->regs[0];
+
+ if (addr == 0) { /* config index register */
+ sc->regs[0] = data;
+ return;
+ }
+
+ /* config data register */
+ trace_via_superio_write(idx, data);
+ switch (idx) {
+ case 0x00 ... 0xdf:
+ case 0xe7 ... 0xef:
+ case 0xf0 ... 0xf1:
+ case 0xf5:
+ case 0xf8:
+ case 0xfd:
+ /* ignore write to read only registers */
+ return;
+ case 0xf2: /* Function select */
+ {
+ data &= 0x17;
+ if (data & BIT(2)) { /* Serial port enable */
+ ISADevice *dev = sc->superio.serial[0];
+ if (!memory_region_is_mapped(sc->serial_io[0])) {
+ memory_region_add_subregion(isa_address_space_io(dev),
+ dev->ioport_id, sc->serial_io[0]);
+ }
+ } else {
+ MemoryRegion *io = isa_address_space_io(sc->superio.serial[0]);
+ if (memory_region_is_mapped(sc->serial_io[0])) {
+ memory_region_del_subregion(io, sc->serial_io[0]);
+ }
+ }
+ break;
+ }
+ case 0xf4: /* Serial port io base address */
+ {
+ data &= 0xfe;
+ sc->superio.serial[0]->ioport_id = data << 2;
+ if (memory_region_is_mapped(sc->serial_io[0])) {
+ memory_region_set_address(sc->serial_io[0], data << 2);
+ }
+ break;
+ }
+ default:
+ qemu_log_mask(LOG_UNIMP,
+ "via_superio_cfg: unimplemented register 0x%x\n", idx);
+ break;
+ }
+ sc->regs[idx] = data;
+}
+
+static const MemoryRegionOps vt8231_superio_cfg_ops = {
+ .read = via_superio_cfg_read,
+ .write = vt8231_superio_cfg_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+};
+
+static void vt8231_superio_reset(DeviceState *dev)
+{
+ ViaSuperIOState *s = VIA_SUPERIO(dev);
+
+ memset(s->regs, 0, sizeof(s->regs));
+ /* Device ID */
+ s->regs[0xf0] = 0x3c;
+ /* Device revision */
+ s->regs[0xf1] = 0x01;
+ /* Function select - all disabled */
+ vt8231_superio_cfg_write(s, 0, 0xf2, 1);
+ vt8231_superio_cfg_write(s, 1, 0x03, 1);
+ /* Serial port base addr */
+ vt8231_superio_cfg_write(s, 0, 0xf4, 1);
+ vt8231_superio_cfg_write(s, 1, 0xfe, 1);
+ /* Parallel port base addr */
+ vt8231_superio_cfg_write(s, 0, 0xf6, 1);
+ vt8231_superio_cfg_write(s, 1, 0xde, 1);
+ /* Floppy ctrl base addr */
+ vt8231_superio_cfg_write(s, 0, 0xf7, 1);
+ vt8231_superio_cfg_write(s, 1, 0xfc, 1);
+
+ vt8231_superio_cfg_write(s, 0, 0, 1);
+}
+
+static void vt8231_superio_init(Object *obj)
+{
+ VIA_SUPERIO(obj)->io_ops = &vt8231_superio_cfg_ops;
+}
+
+static void vt8231_superio_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
+
+ dc->reset = vt8231_superio_reset;
+ sc->serial.count = 1;
+ sc->parallel.count = 1;
+ sc->ide.count = 0; /* emulated by via-ide */
+ sc->floppy.count = 1;
+}
+
+static const TypeInfo vt8231_superio_info = {
+ .name = TYPE_VT8231_SUPERIO,
+ .parent = TYPE_VIA_SUPERIO,
+ .instance_size = sizeof(ViaSuperIOState),
+ .instance_init = vt8231_superio_init,
+ .class_size = sizeof(ISASuperIOClass),
+ .class_init = vt8231_superio_class_init,
+};
+
+
OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA)
struct VT82C686BISAState {
@@ -614,6 +734,7 @@ static void vt82c686b_register_types(void)
type_register_static(&vt8231_pm_info);
type_register_static(&via_superio_info);
type_register_static(&vt82c686b_superio_info);
+ type_register_static(&vt8231_superio_info);
type_register_static(&via_info);
}
--
2.21.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v7 2/8] vt82c686: QOM-ify superio related functionality
2021-03-10 2:58 [PATCH v7 0/8] Pegasos2 emulation BALATON Zoltan
2021-03-10 2:58 ` [PATCH v7 3/8] vt82c686: Add VT8231_SUPERIO based on VIA_SUPERIO BALATON Zoltan
@ 2021-03-10 2:58 ` BALATON Zoltan
2021-03-11 23:50 ` Philippe Mathieu-Daudé
2021-03-10 2:58 ` [PATCH v7 1/8] vt82c686: Implement control of serial port io ranges via config regs BALATON Zoltan
` (6 subsequent siblings)
8 siblings, 1 reply; 32+ messages in thread
From: BALATON Zoltan @ 2021-03-10 2:58 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Peter Maydell, Paolo Bonzini, f4bug, David Gibson
Collect superio functionality and its controlling config registers
handling in an abstract VIA_SUPERIO class that is a subclass of
ISA_SUPERIO and put vt82c686b specific parts in a subclass of this
abstract class.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/isa/vt82c686.c | 242 ++++++++++++++++++++++++--------------
include/hw/isa/vt82c686.h | 1 -
2 files changed, 152 insertions(+), 91 deletions(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index a3353ec5db..e89dbf43da 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -249,12 +249,21 @@ static const TypeInfo vt8231_pm_info = {
};
-typedef struct SuperIOConfig {
+#define TYPE_VIA_SUPERIO "via-superio"
+OBJECT_DECLARE_SIMPLE_TYPE(ViaSuperIOState, VIA_SUPERIO)
+
+struct ViaSuperIOState {
+ ISASuperIODevice superio;
uint8_t regs[0x100];
+ const MemoryRegionOps *io_ops;
MemoryRegion io;
- ISASuperIODevice *superio;
MemoryRegion *serial_io[SUPERIO_MAX_SERIAL_PORTS];
-} SuperIOConfig;
+};
+
+static inline void via_superio_io_enable(ViaSuperIOState *s, bool enable)
+{
+ memory_region_set_enabled(&s->io, enable);
+}
static MemoryRegion *find_subregion(ISADevice *d, MemoryRegion *parent,
int offs)
@@ -270,10 +279,78 @@ static MemoryRegion *find_subregion(ISADevice *d, MemoryRegion *parent,
return mr;
}
-static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
- unsigned size)
+static void via_superio_realize(DeviceState *d, Error **errp)
+{
+ ViaSuperIOState *s = VIA_SUPERIO(d);
+ ISASuperIOClass *ic = ISA_SUPERIO_GET_CLASS(s);
+ Error *local_err = NULL;
+ int i;
+
+ assert(s->io_ops);
+ ic->parent_realize(d, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+ /* Grab io regions of serial devices so we can control them */
+ for (i = 0; i < ic->serial.count; i++) {
+ ISADevice *sd = s->superio.serial[i];
+ MemoryRegion *io = isa_address_space_io(sd);
+ MemoryRegion *mr = find_subregion(sd, io, sd->ioport_id);
+ if (!mr) {
+ error_setg(errp, "Could not get io region for serial %d", i);
+ return;
+ }
+ s->serial_io[i] = mr;
+ }
+
+ memory_region_init_io(&s->io, OBJECT(d), s->io_ops, s, "via-superio", 2);
+ memory_region_set_enabled(&s->io, false);
+ /* The floppy also uses 0x3f0 and 0x3f1 but this seems to work anyway */
+ memory_region_add_subregion(isa_address_space_io(ISA_DEVICE(s)), 0x3f0,
+ &s->io);
+}
+
+static uint64_t via_superio_cfg_read(void *opaque, hwaddr addr, unsigned size)
+{
+ ViaSuperIOState *sc = opaque;
+ uint8_t idx = sc->regs[0];
+ uint8_t val = sc->regs[idx];
+
+ if (addr == 0) {
+ return idx;
+ }
+ if (addr == 1 && idx == 0) {
+ val = 0; /* reading reg 0 where we store index value */
+ }
+ trace_via_superio_read(idx, val);
+ return val;
+}
+
+static void via_superio_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
+
+ sc->parent_realize = dc->realize;
+ dc->realize = via_superio_realize;
+}
+
+static const TypeInfo via_superio_info = {
+ .name = TYPE_VIA_SUPERIO,
+ .parent = TYPE_ISA_SUPERIO,
+ .instance_size = sizeof(ViaSuperIOState),
+ .class_size = sizeof(ISASuperIOClass),
+ .class_init = via_superio_class_init,
+ .abstract = true,
+};
+
+#define TYPE_VT82C686B_SUPERIO "vt82c686b-superio"
+
+static void vt82c686b_superio_cfg_write(void *opaque, hwaddr addr,
+ uint64_t data, unsigned size)
{
- SuperIOConfig *sc = opaque;
+ ViaSuperIOState *sc = opaque;
uint8_t idx = sc->regs[0];
if (addr == 0) { /* config index register */
@@ -295,29 +372,29 @@ static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
case 0xfd ... 0xff:
/* ignore write to read only registers */
return;
- case 0xe2:
+ case 0xe2: /* Function select */
{
data &= 0x1f;
if (data & BIT(2)) { /* Serial port 1 enable */
- ISADevice *dev = sc->superio->serial[0];
+ ISADevice *dev = sc->superio.serial[0];
if (!memory_region_is_mapped(sc->serial_io[0])) {
memory_region_add_subregion(isa_address_space_io(dev),
dev->ioport_id, sc->serial_io[0]);
}
} else {
- MemoryRegion *io = isa_address_space_io(sc->superio->serial[0]);
+ MemoryRegion *io = isa_address_space_io(sc->superio.serial[0]);
if (memory_region_is_mapped(sc->serial_io[0])) {
memory_region_del_subregion(io, sc->serial_io[0]);
}
}
if (data & BIT(3)) { /* Serial port 2 enable */
- ISADevice *dev = sc->superio->serial[1];
+ ISADevice *dev = sc->superio.serial[1];
if (!memory_region_is_mapped(sc->serial_io[1])) {
memory_region_add_subregion(isa_address_space_io(dev),
dev->ioport_id, sc->serial_io[1]);
}
} else {
- MemoryRegion *io = isa_address_space_io(sc->superio->serial[1]);
+ MemoryRegion *io = isa_address_space_io(sc->superio.serial[1]);
if (memory_region_is_mapped(sc->serial_io[1])) {
memory_region_del_subregion(io, sc->serial_io[1]);
}
@@ -327,7 +404,7 @@ static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
case 0xe7: /* Serial port 1 io base address */
{
data &= 0xfe;
- sc->superio->serial[0]->ioport_id = data << 2;
+ sc->superio.serial[0]->ioport_id = data << 2;
if (memory_region_is_mapped(sc->serial_io[0])) {
memory_region_set_address(sc->serial_io[0], data << 2);
}
@@ -336,7 +413,7 @@ static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
case 0xe8: /* Serial port 2 io base address */
{
data &= 0xfe;
- sc->superio->serial[1]->ioport_id = data << 2;
+ sc->superio.serial[1]->ioport_id = data << 2;
if (memory_region_is_mapped(sc->serial_io[1])) {
memory_region_set_address(sc->serial_io[1], data << 2);
}
@@ -350,25 +427,9 @@ static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
sc->regs[idx] = data;
}
-static uint64_t superio_cfg_read(void *opaque, hwaddr addr, unsigned size)
-{
- SuperIOConfig *sc = opaque;
- uint8_t idx = sc->regs[0];
- uint8_t val = sc->regs[idx];
-
- if (addr == 0) {
- return idx;
- }
- if (addr == 1 && idx == 0) {
- val = 0; /* reading reg 0 where we store index value */
- }
- trace_via_superio_read(idx, val);
- return val;
-}
-
-static const MemoryRegionOps superio_cfg_ops = {
- .read = superio_cfg_read,
- .write = superio_cfg_write,
+static const MemoryRegionOps vt82c686b_superio_cfg_ops = {
+ .read = via_superio_cfg_read,
+ .write = vt82c686b_superio_cfg_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.impl = {
.min_access_size = 1,
@@ -376,13 +437,66 @@ static const MemoryRegionOps superio_cfg_ops = {
},
};
+static void vt82c686b_superio_reset(DeviceState *dev)
+{
+ ViaSuperIOState *s = VIA_SUPERIO(dev);
+
+ memset(s->regs, 0, sizeof(s->regs));
+ /* Device ID */
+ vt82c686b_superio_cfg_write(s, 0, 0xe0, 1);
+ vt82c686b_superio_cfg_write(s, 1, 0x3c, 1);
+ /* Function select - all disabled */
+ vt82c686b_superio_cfg_write(s, 0, 0xe2, 1);
+ vt82c686b_superio_cfg_write(s, 1, 0x03, 1);
+ /* Floppy ctrl base addr */
+ vt82c686b_superio_cfg_write(s, 0, 0xe3, 1);
+ vt82c686b_superio_cfg_write(s, 1, 0xfc, 1);
+ /* Parallel port base addr */
+ vt82c686b_superio_cfg_write(s, 0, 0xe6, 1);
+ vt82c686b_superio_cfg_write(s, 1, 0xde, 1);
+ /* Serial port 1 base addr */
+ vt82c686b_superio_cfg_write(s, 0, 0xe7, 1);
+ vt82c686b_superio_cfg_write(s, 1, 0xfe, 1);
+ /* Serial port 2 base addr */
+ vt82c686b_superio_cfg_write(s, 0, 0xe8, 1);
+ vt82c686b_superio_cfg_write(s, 1, 0xbe, 1);
+
+ vt82c686b_superio_cfg_write(s, 0, 0, 1);
+}
+
+static void vt82c686b_superio_init(Object *obj)
+{
+ VIA_SUPERIO(obj)->io_ops = &vt82c686b_superio_cfg_ops;
+}
+
+static void vt82c686b_superio_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
+
+ dc->reset = vt82c686b_superio_reset;
+ sc->serial.count = 2;
+ sc->parallel.count = 1;
+ sc->ide.count = 0; /* emulated by via-ide */
+ sc->floppy.count = 1;
+}
+
+static const TypeInfo vt82c686b_superio_info = {
+ .name = TYPE_VT82C686B_SUPERIO,
+ .parent = TYPE_VIA_SUPERIO,
+ .instance_size = sizeof(ViaSuperIOState),
+ .instance_init = vt82c686b_superio_init,
+ .class_size = sizeof(ISASuperIOClass),
+ .class_init = vt82c686b_superio_class_init,
+};
+
OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA)
struct VT82C686BISAState {
PCIDevice dev;
qemu_irq cpu_intr;
- SuperIOConfig superio_cfg;
+ ViaSuperIOState *via_sio;
};
static void via_isa_request_i8259_irq(void *opaque, int irq, int level)
@@ -400,7 +514,7 @@ static void vt82c686b_write_config(PCIDevice *d, uint32_t addr,
pci_default_write_config(d, addr, val, len);
if (addr == 0x85) {
/* BIT(1): enable or disable superio config io ports */
- memory_region_set_enabled(&s->superio_cfg.io, val & BIT(1));
+ via_superio_io_enable(s->via_sio, val & BIT(1));
}
}
@@ -432,13 +546,6 @@ static void vt82c686b_isa_reset(DeviceState *dev)
pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
pci_conf[0x5f] = 0x04;
pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
-
- s->superio_cfg.regs[0xe0] = 0x3c; /* Device ID */
- s->superio_cfg.regs[0xe2] = 0x03; /* Function select */
- s->superio_cfg.regs[0xe3] = 0xfc; /* Floppy ctrl base addr */
- s->superio_cfg.regs[0xe6] = 0xde; /* Parallel port base addr */
- s->superio_cfg.regs[0xe7] = 0xfe; /* Serial port 1 base addr */
- s->superio_cfg.regs[0xe8] = 0xbe; /* Serial port 2 base addr */
}
static void vt82c686b_realize(PCIDevice *d, Error **errp)
@@ -447,7 +554,6 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
DeviceState *dev = DEVICE(d);
ISABus *isa_bus;
qemu_irq *isa_irq;
- ISASuperIOClass *ic;
int i;
qdev_init_gpio_out(dev, &s->cpu_intr, 1);
@@ -457,9 +563,8 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
isa_bus_irqs(isa_bus, i8259_init(isa_bus, *isa_irq));
i8254_pit_init(isa_bus, 0x40, 0, NULL);
i8257_dma_init(isa_bus, 0);
- s->superio_cfg.superio = ISA_SUPERIO(isa_create_simple(isa_bus,
- TYPE_VT82C686B_SUPERIO));
- ic = ISA_SUPERIO_GET_CLASS(s->superio_cfg.superio);
+ s->via_sio = VIA_SUPERIO(isa_create_simple(isa_bus,
+ TYPE_VT82C686B_SUPERIO));
mc146818_rtc_init(isa_bus, 2000, NULL);
for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) {
@@ -467,31 +572,6 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
d->wmask[i] = 0;
}
}
-
- memory_region_init_io(&s->superio_cfg.io, OBJECT(d), &superio_cfg_ops,
- &s->superio_cfg, "superio_cfg", 2);
- memory_region_set_enabled(&s->superio_cfg.io, false);
- /*
- * The floppy also uses 0x3f0 and 0x3f1.
- * But we do not emulate a floppy, so just set it here.
- */
- memory_region_add_subregion(isa_bus->address_space_io, 0x3f0,
- &s->superio_cfg.io);
-
- /* Grab io regions of serial devices so we can control them */
- for (i = 0; i < ic->serial.count; i++) {
- ISADevice *sd = s->superio_cfg.superio->serial[i];
- MemoryRegion *io = isa_address_space_io(sd);
- MemoryRegion *mr = find_subregion(sd, io, sd->ioport_id);
- if (!mr) {
- error_setg(errp, "Could not get io region for serial %d", i);
- return;
- }
- s->superio_cfg.serial_io[i] = mr;
- if (memory_region_is_mapped(mr)) {
- memory_region_del_subregion(io, mr);
- }
- }
}
static void via_class_init(ObjectClass *klass, void *data)
@@ -527,32 +607,14 @@ static const TypeInfo via_info = {
};
-static void vt82c686b_superio_class_init(ObjectClass *klass, void *data)
-{
- ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
-
- sc->serial.count = 2;
- sc->parallel.count = 1;
- sc->ide.count = 0;
- sc->floppy.count = 1;
-}
-
-static const TypeInfo via_superio_info = {
- .name = TYPE_VT82C686B_SUPERIO,
- .parent = TYPE_ISA_SUPERIO,
- .instance_size = sizeof(ISASuperIODevice),
- .class_size = sizeof(ISASuperIOClass),
- .class_init = vt82c686b_superio_class_init,
-};
-
-
static void vt82c686b_register_types(void)
{
type_register_static(&via_pm_info);
type_register_static(&vt82c686b_pm_info);
type_register_static(&vt8231_pm_info);
- type_register_static(&via_info);
type_register_static(&via_superio_info);
+ type_register_static(&vt82c686b_superio_info);
+ type_register_static(&via_info);
}
type_init(vt82c686b_register_types)
diff --git a/include/hw/isa/vt82c686.h b/include/hw/isa/vt82c686.h
index 9b6d610e83..0692b9a527 100644
--- a/include/hw/isa/vt82c686.h
+++ b/include/hw/isa/vt82c686.h
@@ -2,7 +2,6 @@
#define HW_VT82C686_H
#define TYPE_VT82C686B_ISA "vt82c686b-isa"
-#define TYPE_VT82C686B_SUPERIO "vt82c686b-superio"
#define TYPE_VT82C686B_PM "vt82c686b-pm"
#define TYPE_VT8231_PM "vt8231-pm"
#define TYPE_VIA_AC97 "via-ac97"
--
2.21.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH v7 2/8] vt82c686: QOM-ify superio related functionality
2021-03-10 2:58 ` [PATCH v7 2/8] vt82c686: QOM-ify superio related functionality BALATON Zoltan
@ 2021-03-11 23:50 ` Philippe Mathieu-Daudé
2021-03-12 0:32 ` BALATON Zoltan
0 siblings, 1 reply; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-11 23:50 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc
Cc: Peter Maydell, David Gibson, Paolo Bonzini
On 3/10/21 3:58 AM, BALATON Zoltan wrote:
> Collect superio functionality and its controlling config registers
> handling in an abstract VIA_SUPERIO class that is a subclass of
> ISA_SUPERIO and put vt82c686b specific parts in a subclass of this
> abstract class.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> hw/isa/vt82c686.c | 242 ++++++++++++++++++++++++--------------
> include/hw/isa/vt82c686.h | 1 -
> 2 files changed, 152 insertions(+), 91 deletions(-)
>
> diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
> index a3353ec5db..e89dbf43da 100644
> --- a/hw/isa/vt82c686.c
> +++ b/hw/isa/vt82c686.c
> @@ -249,12 +249,21 @@ static const TypeInfo vt8231_pm_info = {
> };
>
>
> -typedef struct SuperIOConfig {
> +#define TYPE_VIA_SUPERIO "via-superio"
> +OBJECT_DECLARE_SIMPLE_TYPE(ViaSuperIOState, VIA_SUPERIO)
> +
> +struct ViaSuperIOState {
> + ISASuperIODevice superio;
> uint8_t regs[0x100];
> + const MemoryRegionOps *io_ops;
> MemoryRegion io;
> - ISASuperIODevice *superio;
> MemoryRegion *serial_io[SUPERIO_MAX_SERIAL_PORTS];
> -} SuperIOConfig;
> +};
> +
> +static inline void via_superio_io_enable(ViaSuperIOState *s, bool enable)
> +{
> + memory_region_set_enabled(&s->io, enable);
> +}
>
> static MemoryRegion *find_subregion(ISADevice *d, MemoryRegion *parent,
> int offs)
> @@ -270,10 +279,78 @@ static MemoryRegion *find_subregion(ISADevice *d, MemoryRegion *parent,
> return mr;
> }
>
> -static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
> - unsigned size)
> +static void via_superio_realize(DeviceState *d, Error **errp)
> +{
> + ViaSuperIOState *s = VIA_SUPERIO(d);
> + ISASuperIOClass *ic = ISA_SUPERIO_GET_CLASS(s);
> + Error *local_err = NULL;
> + int i;
> +
> + assert(s->io_ops);
> + ic->parent_realize(d, &local_err);
> + if (local_err) {
> + error_propagate(errp, local_err);
> + return;
> + }
> + /* Grab io regions of serial devices so we can control them */
> + for (i = 0; i < ic->serial.count; i++) {
> + ISADevice *sd = s->superio.serial[i];
> + MemoryRegion *io = isa_address_space_io(sd);
> + MemoryRegion *mr = find_subregion(sd, io, sd->ioport_id);
> + if (!mr) {
> + error_setg(errp, "Could not get io region for serial %d", i);
> + return;
> + }
> + s->serial_io[i] = mr;
Don't we need to memory_region_ref(mr) here?
> + }
> +
> + memory_region_init_io(&s->io, OBJECT(d), s->io_ops, s, "via-superio", 2);
> + memory_region_set_enabled(&s->io, false);
> + /* The floppy also uses 0x3f0 and 0x3f1 but this seems to work anyway */
> + memory_region_add_subregion(isa_address_space_io(ISA_DEVICE(s)), 0x3f0,
> + &s->io);
> +}
> +
> +static uint64_t via_superio_cfg_read(void *opaque, hwaddr addr, unsigned size)
> +{
> + ViaSuperIOState *sc = opaque;
> + uint8_t idx = sc->regs[0];
> + uint8_t val = sc->regs[idx];
> +
> + if (addr == 0) {
> + return idx;
> + }
> + if (addr == 1 && idx == 0) {
> + val = 0; /* reading reg 0 where we store index value */
> + }
> + trace_via_superio_read(idx, val);
> + return val;
> +}
> +
> +static void via_superio_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
> +
> + sc->parent_realize = dc->realize;
> + dc->realize = via_superio_realize;
> +}
> +
> +static const TypeInfo via_superio_info = {
> + .name = TYPE_VIA_SUPERIO,
> + .parent = TYPE_ISA_SUPERIO,
> + .instance_size = sizeof(ViaSuperIOState),
> + .class_size = sizeof(ISASuperIOClass),
> + .class_init = via_superio_class_init,
> + .abstract = true,
> +};
> +
> +#define TYPE_VT82C686B_SUPERIO "vt82c686b-superio"
> +
> +static void vt82c686b_superio_cfg_write(void *opaque, hwaddr addr,
> + uint64_t data, unsigned size)
> {
> - SuperIOConfig *sc = opaque;
> + ViaSuperIOState *sc = opaque;
> uint8_t idx = sc->regs[0];
>
> if (addr == 0) { /* config index register */
> @@ -295,29 +372,29 @@ static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
> case 0xfd ... 0xff:
> /* ignore write to read only registers */
> return;
> - case 0xe2:
> + case 0xe2: /* Function select */
> {
> data &= 0x1f;
> if (data & BIT(2)) { /* Serial port 1 enable */
> - ISADevice *dev = sc->superio->serial[0];
> + ISADevice *dev = sc->superio.serial[0];
> if (!memory_region_is_mapped(sc->serial_io[0])) {
> memory_region_add_subregion(isa_address_space_io(dev),
> dev->ioport_id, sc->serial_io[0]);
> }
> } else {
> - MemoryRegion *io = isa_address_space_io(sc->superio->serial[0]);
> + MemoryRegion *io = isa_address_space_io(sc->superio.serial[0]);
> if (memory_region_is_mapped(sc->serial_io[0])) {
> memory_region_del_subregion(io, sc->serial_io[0]);
> }
> }
> if (data & BIT(3)) { /* Serial port 2 enable */
> - ISADevice *dev = sc->superio->serial[1];
> + ISADevice *dev = sc->superio.serial[1];
> if (!memory_region_is_mapped(sc->serial_io[1])) {
> memory_region_add_subregion(isa_address_space_io(dev),
> dev->ioport_id, sc->serial_io[1]);
> }
> } else {
> - MemoryRegion *io = isa_address_space_io(sc->superio->serial[1]);
> + MemoryRegion *io = isa_address_space_io(sc->superio.serial[1]);
> if (memory_region_is_mapped(sc->serial_io[1])) {
> memory_region_del_subregion(io, sc->serial_io[1]);
> }
> @@ -327,7 +404,7 @@ static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
> case 0xe7: /* Serial port 1 io base address */
> {
> data &= 0xfe;
> - sc->superio->serial[0]->ioport_id = data << 2;
> + sc->superio.serial[0]->ioport_id = data << 2;
> if (memory_region_is_mapped(sc->serial_io[0])) {
> memory_region_set_address(sc->serial_io[0], data << 2);
> }
> @@ -336,7 +413,7 @@ static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
> case 0xe8: /* Serial port 2 io base address */
> {
> data &= 0xfe;
> - sc->superio->serial[1]->ioport_id = data << 2;
> + sc->superio.serial[1]->ioport_id = data << 2;
> if (memory_region_is_mapped(sc->serial_io[1])) {
> memory_region_set_address(sc->serial_io[1], data << 2);
> }
> @@ -350,25 +427,9 @@ static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
> sc->regs[idx] = data;
> }
>
> -static uint64_t superio_cfg_read(void *opaque, hwaddr addr, unsigned size)
> -{
> - SuperIOConfig *sc = opaque;
> - uint8_t idx = sc->regs[0];
> - uint8_t val = sc->regs[idx];
> -
> - if (addr == 0) {
> - return idx;
> - }
> - if (addr == 1 && idx == 0) {
> - val = 0; /* reading reg 0 where we store index value */
> - }
> - trace_via_superio_read(idx, val);
> - return val;
> -}
> -
> -static const MemoryRegionOps superio_cfg_ops = {
> - .read = superio_cfg_read,
> - .write = superio_cfg_write,
> +static const MemoryRegionOps vt82c686b_superio_cfg_ops = {
> + .read = via_superio_cfg_read,
> + .write = vt82c686b_superio_cfg_write,
> .endianness = DEVICE_NATIVE_ENDIAN,
> .impl = {
> .min_access_size = 1,
> @@ -376,13 +437,66 @@ static const MemoryRegionOps superio_cfg_ops = {
> },
> };
>
> +static void vt82c686b_superio_reset(DeviceState *dev)
> +{
> + ViaSuperIOState *s = VIA_SUPERIO(dev);
> +
> + memset(s->regs, 0, sizeof(s->regs));
> + /* Device ID */
> + vt82c686b_superio_cfg_write(s, 0, 0xe0, 1);
> + vt82c686b_superio_cfg_write(s, 1, 0x3c, 1);
> + /* Function select - all disabled */
> + vt82c686b_superio_cfg_write(s, 0, 0xe2, 1);
> + vt82c686b_superio_cfg_write(s, 1, 0x03, 1);
> + /* Floppy ctrl base addr */
> + vt82c686b_superio_cfg_write(s, 0, 0xe3, 1);
> + vt82c686b_superio_cfg_write(s, 1, 0xfc, 1);
> + /* Parallel port base addr */
> + vt82c686b_superio_cfg_write(s, 0, 0xe6, 1);
> + vt82c686b_superio_cfg_write(s, 1, 0xde, 1);
> + /* Serial port 1 base addr */
> + vt82c686b_superio_cfg_write(s, 0, 0xe7, 1);
> + vt82c686b_superio_cfg_write(s, 1, 0xfe, 1);
> + /* Serial port 2 base addr */
> + vt82c686b_superio_cfg_write(s, 0, 0xe8, 1);
> + vt82c686b_superio_cfg_write(s, 1, 0xbe, 1);
> +
> + vt82c686b_superio_cfg_write(s, 0, 0, 1);
> +}
> +
> +static void vt82c686b_superio_init(Object *obj)
> +{
> + VIA_SUPERIO(obj)->io_ops = &vt82c686b_superio_cfg_ops;
> +}
> +
> +static void vt82c686b_superio_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
> +
> + dc->reset = vt82c686b_superio_reset;
> + sc->serial.count = 2;
> + sc->parallel.count = 1;
> + sc->ide.count = 0; /* emulated by via-ide */
> + sc->floppy.count = 1;
> +}
> +
> +static const TypeInfo vt82c686b_superio_info = {
> + .name = TYPE_VT82C686B_SUPERIO,
> + .parent = TYPE_VIA_SUPERIO,
> + .instance_size = sizeof(ViaSuperIOState),
> + .instance_init = vt82c686b_superio_init,
> + .class_size = sizeof(ISASuperIOClass),
> + .class_init = vt82c686b_superio_class_init,
> +};
> +
>
> OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA)
>
> struct VT82C686BISAState {
> PCIDevice dev;
> qemu_irq cpu_intr;
> - SuperIOConfig superio_cfg;
> + ViaSuperIOState *via_sio;
> };
>
> static void via_isa_request_i8259_irq(void *opaque, int irq, int level)
> @@ -400,7 +514,7 @@ static void vt82c686b_write_config(PCIDevice *d, uint32_t addr,
> pci_default_write_config(d, addr, val, len);
> if (addr == 0x85) {
> /* BIT(1): enable or disable superio config io ports */
> - memory_region_set_enabled(&s->superio_cfg.io, val & BIT(1));
> + via_superio_io_enable(s->via_sio, val & BIT(1));
> }
> }
>
> @@ -432,13 +546,6 @@ static void vt82c686b_isa_reset(DeviceState *dev)
> pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
> pci_conf[0x5f] = 0x04;
> pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
> -
> - s->superio_cfg.regs[0xe0] = 0x3c; /* Device ID */
> - s->superio_cfg.regs[0xe2] = 0x03; /* Function select */
> - s->superio_cfg.regs[0xe3] = 0xfc; /* Floppy ctrl base addr */
> - s->superio_cfg.regs[0xe6] = 0xde; /* Parallel port base addr */
> - s->superio_cfg.regs[0xe7] = 0xfe; /* Serial port 1 base addr */
> - s->superio_cfg.regs[0xe8] = 0xbe; /* Serial port 2 base addr */
> }
>
> static void vt82c686b_realize(PCIDevice *d, Error **errp)
> @@ -447,7 +554,6 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
> DeviceState *dev = DEVICE(d);
> ISABus *isa_bus;
> qemu_irq *isa_irq;
> - ISASuperIOClass *ic;
> int i;
>
> qdev_init_gpio_out(dev, &s->cpu_intr, 1);
> @@ -457,9 +563,8 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
> isa_bus_irqs(isa_bus, i8259_init(isa_bus, *isa_irq));
> i8254_pit_init(isa_bus, 0x40, 0, NULL);
> i8257_dma_init(isa_bus, 0);
> - s->superio_cfg.superio = ISA_SUPERIO(isa_create_simple(isa_bus,
> - TYPE_VT82C686B_SUPERIO));
> - ic = ISA_SUPERIO_GET_CLASS(s->superio_cfg.superio);
> + s->via_sio = VIA_SUPERIO(isa_create_simple(isa_bus,
> + TYPE_VT82C686B_SUPERIO));
> mc146818_rtc_init(isa_bus, 2000, NULL);
>
> for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) {
> @@ -467,31 +572,6 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
> d->wmask[i] = 0;
> }
> }
> -
> - memory_region_init_io(&s->superio_cfg.io, OBJECT(d), &superio_cfg_ops,
> - &s->superio_cfg, "superio_cfg", 2);
> - memory_region_set_enabled(&s->superio_cfg.io, false);
> - /*
> - * The floppy also uses 0x3f0 and 0x3f1.
> - * But we do not emulate a floppy, so just set it here.
> - */
> - memory_region_add_subregion(isa_bus->address_space_io, 0x3f0,
> - &s->superio_cfg.io);
> -
> - /* Grab io regions of serial devices so we can control them */
> - for (i = 0; i < ic->serial.count; i++) {
> - ISADevice *sd = s->superio_cfg.superio->serial[i];
> - MemoryRegion *io = isa_address_space_io(sd);
> - MemoryRegion *mr = find_subregion(sd, io, sd->ioport_id);
> - if (!mr) {
> - error_setg(errp, "Could not get io region for serial %d", i);
> - return;
> - }
> - s->superio_cfg.serial_io[i] = mr;
> - if (memory_region_is_mapped(mr)) {
> - memory_region_del_subregion(io, mr);
> - }
> - }
> }
>
> static void via_class_init(ObjectClass *klass, void *data)
> @@ -527,32 +607,14 @@ static const TypeInfo via_info = {
> };
>
>
> -static void vt82c686b_superio_class_init(ObjectClass *klass, void *data)
> -{
> - ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
> -
> - sc->serial.count = 2;
> - sc->parallel.count = 1;
> - sc->ide.count = 0;
> - sc->floppy.count = 1;
> -}
> -
> -static const TypeInfo via_superio_info = {
> - .name = TYPE_VT82C686B_SUPERIO,
> - .parent = TYPE_ISA_SUPERIO,
> - .instance_size = sizeof(ISASuperIODevice),
> - .class_size = sizeof(ISASuperIOClass),
> - .class_init = vt82c686b_superio_class_init,
> -};
> -
> -
> static void vt82c686b_register_types(void)
> {
> type_register_static(&via_pm_info);
> type_register_static(&vt82c686b_pm_info);
> type_register_static(&vt8231_pm_info);
> - type_register_static(&via_info);
> type_register_static(&via_superio_info);
> + type_register_static(&vt82c686b_superio_info);
> + type_register_static(&via_info);
> }
>
> type_init(vt82c686b_register_types)
> diff --git a/include/hw/isa/vt82c686.h b/include/hw/isa/vt82c686.h
> index 9b6d610e83..0692b9a527 100644
> --- a/include/hw/isa/vt82c686.h
> +++ b/include/hw/isa/vt82c686.h
> @@ -2,7 +2,6 @@
> #define HW_VT82C686_H
>
> #define TYPE_VT82C686B_ISA "vt82c686b-isa"
> -#define TYPE_VT82C686B_SUPERIO "vt82c686b-superio"
> #define TYPE_VT82C686B_PM "vt82c686b-pm"
> #define TYPE_VT8231_PM "vt8231-pm"
> #define TYPE_VIA_AC97 "via-ac97"
>
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v7 2/8] vt82c686: QOM-ify superio related functionality
2021-03-11 23:50 ` Philippe Mathieu-Daudé
@ 2021-03-12 0:32 ` BALATON Zoltan
0 siblings, 0 replies; 32+ messages in thread
From: BALATON Zoltan @ 2021-03-12 0:32 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, David Gibson, qemu-ppc, qemu-devel, Paolo Bonzini
[-- Attachment #1: Type: text/plain, Size: 16216 bytes --]
On Fri, 12 Mar 2021, Philippe Mathieu-Daudé wrote:
> On 3/10/21 3:58 AM, BALATON Zoltan wrote:
>> Collect superio functionality and its controlling config registers
>> handling in an abstract VIA_SUPERIO class that is a subclass of
>> ISA_SUPERIO and put vt82c686b specific parts in a subclass of this
>> abstract class.
>>
>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>> ---
>> hw/isa/vt82c686.c | 242 ++++++++++++++++++++++++--------------
>> include/hw/isa/vt82c686.h | 1 -
>> 2 files changed, 152 insertions(+), 91 deletions(-)
>>
>> diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
>> index a3353ec5db..e89dbf43da 100644
>> --- a/hw/isa/vt82c686.c
>> +++ b/hw/isa/vt82c686.c
>> @@ -249,12 +249,21 @@ static const TypeInfo vt8231_pm_info = {
>> };
>>
>>
>> -typedef struct SuperIOConfig {
>> +#define TYPE_VIA_SUPERIO "via-superio"
>> +OBJECT_DECLARE_SIMPLE_TYPE(ViaSuperIOState, VIA_SUPERIO)
>> +
>> +struct ViaSuperIOState {
>> + ISASuperIODevice superio;
>> uint8_t regs[0x100];
>> + const MemoryRegionOps *io_ops;
>> MemoryRegion io;
>> - ISASuperIODevice *superio;
>> MemoryRegion *serial_io[SUPERIO_MAX_SERIAL_PORTS];
>> -} SuperIOConfig;
>> +};
>> +
>> +static inline void via_superio_io_enable(ViaSuperIOState *s, bool enable)
>> +{
>> + memory_region_set_enabled(&s->io, enable);
>> +}
>>
>> static MemoryRegion *find_subregion(ISADevice *d, MemoryRegion *parent,
>> int offs)
>> @@ -270,10 +279,78 @@ static MemoryRegion *find_subregion(ISADevice *d, MemoryRegion *parent,
>> return mr;
>> }
>>
>> -static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
>> - unsigned size)
>> +static void via_superio_realize(DeviceState *d, Error **errp)
>> +{
>> + ViaSuperIOState *s = VIA_SUPERIO(d);
>> + ISASuperIOClass *ic = ISA_SUPERIO_GET_CLASS(s);
>> + Error *local_err = NULL;
>> + int i;
>> +
>> + assert(s->io_ops);
>> + ic->parent_realize(d, &local_err);
>> + if (local_err) {
>> + error_propagate(errp, local_err);
>> + return;
>> + }
>> + /* Grab io regions of serial devices so we can control them */
>> + for (i = 0; i < ic->serial.count; i++) {
>> + ISADevice *sd = s->superio.serial[i];
>> + MemoryRegion *io = isa_address_space_io(sd);
>> + MemoryRegion *mr = find_subregion(sd, io, sd->ioport_id);
>> + if (!mr) {
>> + error_setg(errp, "Could not get io region for serial %d", i);
>> + return;
>> + }
>> + s->serial_io[i] = mr;
>
> Don't we need to memory_region_ref(mr) here?
I don't think so. The ISA device still owns the memory region, we just
snatch it to be able to enable/disable and move it around but otherwise
don't take it over from the device. The memory region would be destroyed
with the device and after that we don't want to keep the memory region as
that's not useful without the device. (This is all theoretical though as
in practice the device is created at startup and never destroyed until
exit.) If we increased ref count here we would also have to decrease it
somewhere but since the serial device is child of this south bridge it
should not go away before via-superio so no separate reference should be
needed here. We own ISASuperIO which owns the isa-serial which owns the
memory region so it should stay there during the lifetime of this object
without increasing ref count.
Regards,
BALATON Zoltan
>> + }
>> +
>> + memory_region_init_io(&s->io, OBJECT(d), s->io_ops, s, "via-superio", 2);
>> + memory_region_set_enabled(&s->io, false);
>> + /* The floppy also uses 0x3f0 and 0x3f1 but this seems to work anyway */
>> + memory_region_add_subregion(isa_address_space_io(ISA_DEVICE(s)), 0x3f0,
>> + &s->io);
>> +}
>> +
>> +static uint64_t via_superio_cfg_read(void *opaque, hwaddr addr, unsigned size)
>> +{
>> + ViaSuperIOState *sc = opaque;
>> + uint8_t idx = sc->regs[0];
>> + uint8_t val = sc->regs[idx];
>> +
>> + if (addr == 0) {
>> + return idx;
>> + }
>> + if (addr == 1 && idx == 0) {
>> + val = 0; /* reading reg 0 where we store index value */
>> + }
>> + trace_via_superio_read(idx, val);
>> + return val;
>> +}
>> +
>> +static void via_superio_class_init(ObjectClass *klass, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(klass);
>> + ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
>> +
>> + sc->parent_realize = dc->realize;
>> + dc->realize = via_superio_realize;
>> +}
>> +
>> +static const TypeInfo via_superio_info = {
>> + .name = TYPE_VIA_SUPERIO,
>> + .parent = TYPE_ISA_SUPERIO,
>> + .instance_size = sizeof(ViaSuperIOState),
>> + .class_size = sizeof(ISASuperIOClass),
>> + .class_init = via_superio_class_init,
>> + .abstract = true,
>> +};
>> +
>> +#define TYPE_VT82C686B_SUPERIO "vt82c686b-superio"
>> +
>> +static void vt82c686b_superio_cfg_write(void *opaque, hwaddr addr,
>> + uint64_t data, unsigned size)
>> {
>> - SuperIOConfig *sc = opaque;
>> + ViaSuperIOState *sc = opaque;
>> uint8_t idx = sc->regs[0];
>>
>> if (addr == 0) { /* config index register */
>> @@ -295,29 +372,29 @@ static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
>> case 0xfd ... 0xff:
>> /* ignore write to read only registers */
>> return;
>> - case 0xe2:
>> + case 0xe2: /* Function select */
>> {
>> data &= 0x1f;
>> if (data & BIT(2)) { /* Serial port 1 enable */
>> - ISADevice *dev = sc->superio->serial[0];
>> + ISADevice *dev = sc->superio.serial[0];
>> if (!memory_region_is_mapped(sc->serial_io[0])) {
>> memory_region_add_subregion(isa_address_space_io(dev),
>> dev->ioport_id, sc->serial_io[0]);
>> }
>> } else {
>> - MemoryRegion *io = isa_address_space_io(sc->superio->serial[0]);
>> + MemoryRegion *io = isa_address_space_io(sc->superio.serial[0]);
>> if (memory_region_is_mapped(sc->serial_io[0])) {
>> memory_region_del_subregion(io, sc->serial_io[0]);
>> }
>> }
>> if (data & BIT(3)) { /* Serial port 2 enable */
>> - ISADevice *dev = sc->superio->serial[1];
>> + ISADevice *dev = sc->superio.serial[1];
>> if (!memory_region_is_mapped(sc->serial_io[1])) {
>> memory_region_add_subregion(isa_address_space_io(dev),
>> dev->ioport_id, sc->serial_io[1]);
>> }
>> } else {
>> - MemoryRegion *io = isa_address_space_io(sc->superio->serial[1]);
>> + MemoryRegion *io = isa_address_space_io(sc->superio.serial[1]);
>> if (memory_region_is_mapped(sc->serial_io[1])) {
>> memory_region_del_subregion(io, sc->serial_io[1]);
>> }
>> @@ -327,7 +404,7 @@ static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
>> case 0xe7: /* Serial port 1 io base address */
>> {
>> data &= 0xfe;
>> - sc->superio->serial[0]->ioport_id = data << 2;
>> + sc->superio.serial[0]->ioport_id = data << 2;
>> if (memory_region_is_mapped(sc->serial_io[0])) {
>> memory_region_set_address(sc->serial_io[0], data << 2);
>> }
>> @@ -336,7 +413,7 @@ static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
>> case 0xe8: /* Serial port 2 io base address */
>> {
>> data &= 0xfe;
>> - sc->superio->serial[1]->ioport_id = data << 2;
>> + sc->superio.serial[1]->ioport_id = data << 2;
>> if (memory_region_is_mapped(sc->serial_io[1])) {
>> memory_region_set_address(sc->serial_io[1], data << 2);
>> }
>> @@ -350,25 +427,9 @@ static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
>> sc->regs[idx] = data;
>> }
>>
>> -static uint64_t superio_cfg_read(void *opaque, hwaddr addr, unsigned size)
>> -{
>> - SuperIOConfig *sc = opaque;
>> - uint8_t idx = sc->regs[0];
>> - uint8_t val = sc->regs[idx];
>> -
>> - if (addr == 0) {
>> - return idx;
>> - }
>> - if (addr == 1 && idx == 0) {
>> - val = 0; /* reading reg 0 where we store index value */
>> - }
>> - trace_via_superio_read(idx, val);
>> - return val;
>> -}
>> -
>> -static const MemoryRegionOps superio_cfg_ops = {
>> - .read = superio_cfg_read,
>> - .write = superio_cfg_write,
>> +static const MemoryRegionOps vt82c686b_superio_cfg_ops = {
>> + .read = via_superio_cfg_read,
>> + .write = vt82c686b_superio_cfg_write,
>> .endianness = DEVICE_NATIVE_ENDIAN,
>> .impl = {
>> .min_access_size = 1,
>> @@ -376,13 +437,66 @@ static const MemoryRegionOps superio_cfg_ops = {
>> },
>> };
>>
>> +static void vt82c686b_superio_reset(DeviceState *dev)
>> +{
>> + ViaSuperIOState *s = VIA_SUPERIO(dev);
>> +
>> + memset(s->regs, 0, sizeof(s->regs));
>> + /* Device ID */
>> + vt82c686b_superio_cfg_write(s, 0, 0xe0, 1);
>> + vt82c686b_superio_cfg_write(s, 1, 0x3c, 1);
>> + /* Function select - all disabled */
>> + vt82c686b_superio_cfg_write(s, 0, 0xe2, 1);
>> + vt82c686b_superio_cfg_write(s, 1, 0x03, 1);
>> + /* Floppy ctrl base addr */
>> + vt82c686b_superio_cfg_write(s, 0, 0xe3, 1);
>> + vt82c686b_superio_cfg_write(s, 1, 0xfc, 1);
>> + /* Parallel port base addr */
>> + vt82c686b_superio_cfg_write(s, 0, 0xe6, 1);
>> + vt82c686b_superio_cfg_write(s, 1, 0xde, 1);
>> + /* Serial port 1 base addr */
>> + vt82c686b_superio_cfg_write(s, 0, 0xe7, 1);
>> + vt82c686b_superio_cfg_write(s, 1, 0xfe, 1);
>> + /* Serial port 2 base addr */
>> + vt82c686b_superio_cfg_write(s, 0, 0xe8, 1);
>> + vt82c686b_superio_cfg_write(s, 1, 0xbe, 1);
>> +
>> + vt82c686b_superio_cfg_write(s, 0, 0, 1);
>> +}
>> +
>> +static void vt82c686b_superio_init(Object *obj)
>> +{
>> + VIA_SUPERIO(obj)->io_ops = &vt82c686b_superio_cfg_ops;
>> +}
>> +
>> +static void vt82c686b_superio_class_init(ObjectClass *klass, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(klass);
>> + ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
>> +
>> + dc->reset = vt82c686b_superio_reset;
>> + sc->serial.count = 2;
>> + sc->parallel.count = 1;
>> + sc->ide.count = 0; /* emulated by via-ide */
>> + sc->floppy.count = 1;
>> +}
>> +
>> +static const TypeInfo vt82c686b_superio_info = {
>> + .name = TYPE_VT82C686B_SUPERIO,
>> + .parent = TYPE_VIA_SUPERIO,
>> + .instance_size = sizeof(ViaSuperIOState),
>> + .instance_init = vt82c686b_superio_init,
>> + .class_size = sizeof(ISASuperIOClass),
>> + .class_init = vt82c686b_superio_class_init,
>> +};
>> +
>>
>> OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA)
>>
>> struct VT82C686BISAState {
>> PCIDevice dev;
>> qemu_irq cpu_intr;
>> - SuperIOConfig superio_cfg;
>> + ViaSuperIOState *via_sio;
>> };
>>
>> static void via_isa_request_i8259_irq(void *opaque, int irq, int level)
>> @@ -400,7 +514,7 @@ static void vt82c686b_write_config(PCIDevice *d, uint32_t addr,
>> pci_default_write_config(d, addr, val, len);
>> if (addr == 0x85) {
>> /* BIT(1): enable or disable superio config io ports */
>> - memory_region_set_enabled(&s->superio_cfg.io, val & BIT(1));
>> + via_superio_io_enable(s->via_sio, val & BIT(1));
>> }
>> }
>>
>> @@ -432,13 +546,6 @@ static void vt82c686b_isa_reset(DeviceState *dev)
>> pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
>> pci_conf[0x5f] = 0x04;
>> pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
>> -
>> - s->superio_cfg.regs[0xe0] = 0x3c; /* Device ID */
>> - s->superio_cfg.regs[0xe2] = 0x03; /* Function select */
>> - s->superio_cfg.regs[0xe3] = 0xfc; /* Floppy ctrl base addr */
>> - s->superio_cfg.regs[0xe6] = 0xde; /* Parallel port base addr */
>> - s->superio_cfg.regs[0xe7] = 0xfe; /* Serial port 1 base addr */
>> - s->superio_cfg.regs[0xe8] = 0xbe; /* Serial port 2 base addr */
>> }
>>
>> static void vt82c686b_realize(PCIDevice *d, Error **errp)
>> @@ -447,7 +554,6 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
>> DeviceState *dev = DEVICE(d);
>> ISABus *isa_bus;
>> qemu_irq *isa_irq;
>> - ISASuperIOClass *ic;
>> int i;
>>
>> qdev_init_gpio_out(dev, &s->cpu_intr, 1);
>> @@ -457,9 +563,8 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
>> isa_bus_irqs(isa_bus, i8259_init(isa_bus, *isa_irq));
>> i8254_pit_init(isa_bus, 0x40, 0, NULL);
>> i8257_dma_init(isa_bus, 0);
>> - s->superio_cfg.superio = ISA_SUPERIO(isa_create_simple(isa_bus,
>> - TYPE_VT82C686B_SUPERIO));
>> - ic = ISA_SUPERIO_GET_CLASS(s->superio_cfg.superio);
>> + s->via_sio = VIA_SUPERIO(isa_create_simple(isa_bus,
>> + TYPE_VT82C686B_SUPERIO));
>> mc146818_rtc_init(isa_bus, 2000, NULL);
>>
>> for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) {
>> @@ -467,31 +572,6 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
>> d->wmask[i] = 0;
>> }
>> }
>> -
>> - memory_region_init_io(&s->superio_cfg.io, OBJECT(d), &superio_cfg_ops,
>> - &s->superio_cfg, "superio_cfg", 2);
>> - memory_region_set_enabled(&s->superio_cfg.io, false);
>> - /*
>> - * The floppy also uses 0x3f0 and 0x3f1.
>> - * But we do not emulate a floppy, so just set it here.
>> - */
>> - memory_region_add_subregion(isa_bus->address_space_io, 0x3f0,
>> - &s->superio_cfg.io);
>> -
>> - /* Grab io regions of serial devices so we can control them */
>> - for (i = 0; i < ic->serial.count; i++) {
>> - ISADevice *sd = s->superio_cfg.superio->serial[i];
>> - MemoryRegion *io = isa_address_space_io(sd);
>> - MemoryRegion *mr = find_subregion(sd, io, sd->ioport_id);
>> - if (!mr) {
>> - error_setg(errp, "Could not get io region for serial %d", i);
>> - return;
>> - }
>> - s->superio_cfg.serial_io[i] = mr;
>> - if (memory_region_is_mapped(mr)) {
>> - memory_region_del_subregion(io, mr);
>> - }
>> - }
>> }
>>
>> static void via_class_init(ObjectClass *klass, void *data)
>> @@ -527,32 +607,14 @@ static const TypeInfo via_info = {
>> };
>>
>>
>> -static void vt82c686b_superio_class_init(ObjectClass *klass, void *data)
>> -{
>> - ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
>> -
>> - sc->serial.count = 2;
>> - sc->parallel.count = 1;
>> - sc->ide.count = 0;
>> - sc->floppy.count = 1;
>> -}
>> -
>> -static const TypeInfo via_superio_info = {
>> - .name = TYPE_VT82C686B_SUPERIO,
>> - .parent = TYPE_ISA_SUPERIO,
>> - .instance_size = sizeof(ISASuperIODevice),
>> - .class_size = sizeof(ISASuperIOClass),
>> - .class_init = vt82c686b_superio_class_init,
>> -};
>> -
>> -
>> static void vt82c686b_register_types(void)
>> {
>> type_register_static(&via_pm_info);
>> type_register_static(&vt82c686b_pm_info);
>> type_register_static(&vt8231_pm_info);
>> - type_register_static(&via_info);
>> type_register_static(&via_superio_info);
>> + type_register_static(&vt82c686b_superio_info);
>> + type_register_static(&via_info);
>> }
>>
>> type_init(vt82c686b_register_types)
>> diff --git a/include/hw/isa/vt82c686.h b/include/hw/isa/vt82c686.h
>> index 9b6d610e83..0692b9a527 100644
>> --- a/include/hw/isa/vt82c686.h
>> +++ b/include/hw/isa/vt82c686.h
>> @@ -2,7 +2,6 @@
>> #define HW_VT82C686_H
>>
>> #define TYPE_VT82C686B_ISA "vt82c686b-isa"
>> -#define TYPE_VT82C686B_SUPERIO "vt82c686b-superio"
>> #define TYPE_VT82C686B_PM "vt82c686b-pm"
>> #define TYPE_VT8231_PM "vt8231-pm"
>> #define TYPE_VIA_AC97 "via-ac97"
>>
>
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v7 1/8] vt82c686: Implement control of serial port io ranges via config regs
2021-03-10 2:58 [PATCH v7 0/8] Pegasos2 emulation BALATON Zoltan
2021-03-10 2:58 ` [PATCH v7 3/8] vt82c686: Add VT8231_SUPERIO based on VIA_SUPERIO BALATON Zoltan
2021-03-10 2:58 ` [PATCH v7 2/8] vt82c686: QOM-ify superio related functionality BALATON Zoltan
@ 2021-03-10 2:58 ` BALATON Zoltan
2021-03-11 23:47 ` Philippe Mathieu-Daudé
2021-03-23 12:54 ` BALATON Zoltan
2021-03-10 2:58 ` [PATCH v7 8/8] hw/ppc: Add emulation of Genesi/bPlan Pegasos II BALATON Zoltan
` (5 subsequent siblings)
8 siblings, 2 replies; 32+ messages in thread
From: BALATON Zoltan @ 2021-03-10 2:58 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Peter Maydell, Paolo Bonzini, f4bug, David Gibson
In VIA super south bridge the io ranges of superio components
(parallel and serial ports and FDC) can be controlled by superio
config registers to set their base address and enable/disable them.
This is not easy to implement in QEMU because ISA emulation is only
designed to set io base address once on creating the device and io
ranges are registered at creation and cannot easily be disabled or
moved later.
In this patch we hack around that but only for serial ports because
those have a single io range at port base that's relatively easy to
handle and it's what guests actually use and set address different
than the default.
We do not attempt to handle controlling the parallel and FDC regions
because those have multiple io ranges so handling them would be messy
and guests either don't change their deafult or don't care. We could
even get away with disabling and not emulating them, but since they
are already there, this patch leaves them mapped at their default
address just in case this could be useful for a guest in the future.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/isa/vt82c686.c | 84 +++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 82 insertions(+), 2 deletions(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 05d084f698..a3353ec5db 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -252,8 +252,24 @@ static const TypeInfo vt8231_pm_info = {
typedef struct SuperIOConfig {
uint8_t regs[0x100];
MemoryRegion io;
+ ISASuperIODevice *superio;
+ MemoryRegion *serial_io[SUPERIO_MAX_SERIAL_PORTS];
} SuperIOConfig;
+static MemoryRegion *find_subregion(ISADevice *d, MemoryRegion *parent,
+ int offs)
+{
+ MemoryRegion *subregion, *mr = NULL;
+
+ QTAILQ_FOREACH(subregion, &parent->subregions, subregions_link) {
+ if (subregion->addr == offs) {
+ mr = subregion;
+ break;
+ }
+ }
+ return mr;
+}
+
static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
unsigned size)
{
@@ -279,7 +295,53 @@ static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
case 0xfd ... 0xff:
/* ignore write to read only registers */
return;
- /* case 0xe6 ... 0xe8: Should set base port of parallel and serial */
+ case 0xe2:
+ {
+ data &= 0x1f;
+ if (data & BIT(2)) { /* Serial port 1 enable */
+ ISADevice *dev = sc->superio->serial[0];
+ if (!memory_region_is_mapped(sc->serial_io[0])) {
+ memory_region_add_subregion(isa_address_space_io(dev),
+ dev->ioport_id, sc->serial_io[0]);
+ }
+ } else {
+ MemoryRegion *io = isa_address_space_io(sc->superio->serial[0]);
+ if (memory_region_is_mapped(sc->serial_io[0])) {
+ memory_region_del_subregion(io, sc->serial_io[0]);
+ }
+ }
+ if (data & BIT(3)) { /* Serial port 2 enable */
+ ISADevice *dev = sc->superio->serial[1];
+ if (!memory_region_is_mapped(sc->serial_io[1])) {
+ memory_region_add_subregion(isa_address_space_io(dev),
+ dev->ioport_id, sc->serial_io[1]);
+ }
+ } else {
+ MemoryRegion *io = isa_address_space_io(sc->superio->serial[1]);
+ if (memory_region_is_mapped(sc->serial_io[1])) {
+ memory_region_del_subregion(io, sc->serial_io[1]);
+ }
+ }
+ break;
+ }
+ case 0xe7: /* Serial port 1 io base address */
+ {
+ data &= 0xfe;
+ sc->superio->serial[0]->ioport_id = data << 2;
+ if (memory_region_is_mapped(sc->serial_io[0])) {
+ memory_region_set_address(sc->serial_io[0], data << 2);
+ }
+ break;
+ }
+ case 0xe8: /* Serial port 2 io base address */
+ {
+ data &= 0xfe;
+ sc->superio->serial[1]->ioport_id = data << 2;
+ if (memory_region_is_mapped(sc->serial_io[1])) {
+ memory_region_set_address(sc->serial_io[1], data << 2);
+ }
+ break;
+ }
default:
qemu_log_mask(LOG_UNIMP,
"via_superio_cfg: unimplemented register 0x%x\n", idx);
@@ -385,6 +447,7 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
DeviceState *dev = DEVICE(d);
ISABus *isa_bus;
qemu_irq *isa_irq;
+ ISASuperIOClass *ic;
int i;
qdev_init_gpio_out(dev, &s->cpu_intr, 1);
@@ -394,7 +457,9 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
isa_bus_irqs(isa_bus, i8259_init(isa_bus, *isa_irq));
i8254_pit_init(isa_bus, 0x40, 0, NULL);
i8257_dma_init(isa_bus, 0);
- isa_create_simple(isa_bus, TYPE_VT82C686B_SUPERIO);
+ s->superio_cfg.superio = ISA_SUPERIO(isa_create_simple(isa_bus,
+ TYPE_VT82C686B_SUPERIO));
+ ic = ISA_SUPERIO_GET_CLASS(s->superio_cfg.superio);
mc146818_rtc_init(isa_bus, 2000, NULL);
for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) {
@@ -412,6 +477,21 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
*/
memory_region_add_subregion(isa_bus->address_space_io, 0x3f0,
&s->superio_cfg.io);
+
+ /* Grab io regions of serial devices so we can control them */
+ for (i = 0; i < ic->serial.count; i++) {
+ ISADevice *sd = s->superio_cfg.superio->serial[i];
+ MemoryRegion *io = isa_address_space_io(sd);
+ MemoryRegion *mr = find_subregion(sd, io, sd->ioport_id);
+ if (!mr) {
+ error_setg(errp, "Could not get io region for serial %d", i);
+ return;
+ }
+ s->superio_cfg.serial_io[i] = mr;
+ if (memory_region_is_mapped(mr)) {
+ memory_region_del_subregion(io, mr);
+ }
+ }
}
static void via_class_init(ObjectClass *klass, void *data)
--
2.21.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH v7 1/8] vt82c686: Implement control of serial port io ranges via config regs
2021-03-10 2:58 ` [PATCH v7 1/8] vt82c686: Implement control of serial port io ranges via config regs BALATON Zoltan
@ 2021-03-11 23:47 ` Philippe Mathieu-Daudé
2021-03-12 1:20 ` David Gibson
2021-03-23 12:54 ` BALATON Zoltan
1 sibling, 1 reply; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-11 23:47 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc
Cc: Peter Maydell, David Gibson, Paolo Bonzini
ping for review?
On 3/10/21 3:58 AM, BALATON Zoltan wrote:
> In VIA super south bridge the io ranges of superio components
> (parallel and serial ports and FDC) can be controlled by superio
> config registers to set their base address and enable/disable them.
> This is not easy to implement in QEMU because ISA emulation is only
> designed to set io base address once on creating the device and io
> ranges are registered at creation and cannot easily be disabled or
> moved later.
>
> In this patch we hack around that but only for serial ports because
> those have a single io range at port base that's relatively easy to
> handle and it's what guests actually use and set address different
> than the default.
>
> We do not attempt to handle controlling the parallel and FDC regions
> because those have multiple io ranges so handling them would be messy
> and guests either don't change their deafult or don't care. We could
> even get away with disabling and not emulating them, but since they
> are already there, this patch leaves them mapped at their default
> address just in case this could be useful for a guest in the future.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> hw/isa/vt82c686.c | 84 +++++++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 82 insertions(+), 2 deletions(-)
>
> diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
> index 05d084f698..a3353ec5db 100644
> --- a/hw/isa/vt82c686.c
> +++ b/hw/isa/vt82c686.c
> @@ -252,8 +252,24 @@ static const TypeInfo vt8231_pm_info = {
> typedef struct SuperIOConfig {
> uint8_t regs[0x100];
> MemoryRegion io;
> + ISASuperIODevice *superio;
> + MemoryRegion *serial_io[SUPERIO_MAX_SERIAL_PORTS];
> } SuperIOConfig;
>
> +static MemoryRegion *find_subregion(ISADevice *d, MemoryRegion *parent,
> + int offs)
> +{
> + MemoryRegion *subregion, *mr = NULL;
> +
> + QTAILQ_FOREACH(subregion, &parent->subregions, subregions_link) {
> + if (subregion->addr == offs) {
> + mr = subregion;
> + break;
> + }
> + }
> + return mr;
> +}
> +
> static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
> unsigned size)
> {
> @@ -279,7 +295,53 @@ static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
> case 0xfd ... 0xff:
> /* ignore write to read only registers */
> return;
> - /* case 0xe6 ... 0xe8: Should set base port of parallel and serial */
> + case 0xe2:
> + {
> + data &= 0x1f;
> + if (data & BIT(2)) { /* Serial port 1 enable */
> + ISADevice *dev = sc->superio->serial[0];
> + if (!memory_region_is_mapped(sc->serial_io[0])) {
> + memory_region_add_subregion(isa_address_space_io(dev),
> + dev->ioport_id, sc->serial_io[0]);
> + }
> + } else {
> + MemoryRegion *io = isa_address_space_io(sc->superio->serial[0]);
> + if (memory_region_is_mapped(sc->serial_io[0])) {
> + memory_region_del_subregion(io, sc->serial_io[0]);
> + }
> + }
> + if (data & BIT(3)) { /* Serial port 2 enable */
> + ISADevice *dev = sc->superio->serial[1];
> + if (!memory_region_is_mapped(sc->serial_io[1])) {
> + memory_region_add_subregion(isa_address_space_io(dev),
> + dev->ioport_id, sc->serial_io[1]);
> + }
> + } else {
> + MemoryRegion *io = isa_address_space_io(sc->superio->serial[1]);
> + if (memory_region_is_mapped(sc->serial_io[1])) {
> + memory_region_del_subregion(io, sc->serial_io[1]);
> + }
> + }
> + break;
> + }
> + case 0xe7: /* Serial port 1 io base address */
> + {
> + data &= 0xfe;
> + sc->superio->serial[0]->ioport_id = data << 2;
> + if (memory_region_is_mapped(sc->serial_io[0])) {
> + memory_region_set_address(sc->serial_io[0], data << 2);
> + }
> + break;
> + }
> + case 0xe8: /* Serial port 2 io base address */
> + {
> + data &= 0xfe;
> + sc->superio->serial[1]->ioport_id = data << 2;
> + if (memory_region_is_mapped(sc->serial_io[1])) {
> + memory_region_set_address(sc->serial_io[1], data << 2);
> + }
> + break;
> + }
> default:
> qemu_log_mask(LOG_UNIMP,
> "via_superio_cfg: unimplemented register 0x%x\n", idx);
> @@ -385,6 +447,7 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
> DeviceState *dev = DEVICE(d);
> ISABus *isa_bus;
> qemu_irq *isa_irq;
> + ISASuperIOClass *ic;
> int i;
>
> qdev_init_gpio_out(dev, &s->cpu_intr, 1);
> @@ -394,7 +457,9 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
> isa_bus_irqs(isa_bus, i8259_init(isa_bus, *isa_irq));
> i8254_pit_init(isa_bus, 0x40, 0, NULL);
> i8257_dma_init(isa_bus, 0);
> - isa_create_simple(isa_bus, TYPE_VT82C686B_SUPERIO);
> + s->superio_cfg.superio = ISA_SUPERIO(isa_create_simple(isa_bus,
> + TYPE_VT82C686B_SUPERIO));
> + ic = ISA_SUPERIO_GET_CLASS(s->superio_cfg.superio);
> mc146818_rtc_init(isa_bus, 2000, NULL);
>
> for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) {
> @@ -412,6 +477,21 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
> */
> memory_region_add_subregion(isa_bus->address_space_io, 0x3f0,
> &s->superio_cfg.io);
> +
> + /* Grab io regions of serial devices so we can control them */
> + for (i = 0; i < ic->serial.count; i++) {
> + ISADevice *sd = s->superio_cfg.superio->serial[i];
> + MemoryRegion *io = isa_address_space_io(sd);
> + MemoryRegion *mr = find_subregion(sd, io, sd->ioport_id);
> + if (!mr) {
> + error_setg(errp, "Could not get io region for serial %d", i);
> + return;
> + }
> + s->superio_cfg.serial_io[i] = mr;
> + if (memory_region_is_mapped(mr)) {
> + memory_region_del_subregion(io, mr);
> + }
> + }
> }
>
> static void via_class_init(ObjectClass *klass, void *data)
>
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v7 1/8] vt82c686: Implement control of serial port io ranges via config regs
2021-03-11 23:47 ` Philippe Mathieu-Daudé
@ 2021-03-12 1:20 ` David Gibson
0 siblings, 0 replies; 32+ messages in thread
From: David Gibson @ 2021-03-12 1:20 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, Paolo Bonzini, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 7167 bytes --]
On Fri, Mar 12, 2021 at 12:47:54AM +0100, Philippe Mathieu-Daudé wrote:
> ping for review?
I'm not sure who you're asking for a review from.
>
> On 3/10/21 3:58 AM, BALATON Zoltan wrote:
> > In VIA super south bridge the io ranges of superio components
> > (parallel and serial ports and FDC) can be controlled by superio
> > config registers to set their base address and enable/disable them.
> > This is not easy to implement in QEMU because ISA emulation is only
> > designed to set io base address once on creating the device and io
> > ranges are registered at creation and cannot easily be disabled or
> > moved later.
> >
> > In this patch we hack around that but only for serial ports because
> > those have a single io range at port base that's relatively easy to
> > handle and it's what guests actually use and set address different
> > than the default.
> >
> > We do not attempt to handle controlling the parallel and FDC regions
> > because those have multiple io ranges so handling them would be messy
> > and guests either don't change their deafult or don't care. We could
> > even get away with disabling and not emulating them, but since they
> > are already there, this patch leaves them mapped at their default
> > address just in case this could be useful for a guest in the future.
> >
> > Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> > ---
> > hw/isa/vt82c686.c | 84 +++++++++++++++++++++++++++++++++++++++++++++--
> > 1 file changed, 82 insertions(+), 2 deletions(-)
> >
> > diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
> > index 05d084f698..a3353ec5db 100644
> > --- a/hw/isa/vt82c686.c
> > +++ b/hw/isa/vt82c686.c
> > @@ -252,8 +252,24 @@ static const TypeInfo vt8231_pm_info = {
> > typedef struct SuperIOConfig {
> > uint8_t regs[0x100];
> > MemoryRegion io;
> > + ISASuperIODevice *superio;
> > + MemoryRegion *serial_io[SUPERIO_MAX_SERIAL_PORTS];
> > } SuperIOConfig;
> >
> > +static MemoryRegion *find_subregion(ISADevice *d, MemoryRegion *parent,
> > + int offs)
> > +{
> > + MemoryRegion *subregion, *mr = NULL;
> > +
> > + QTAILQ_FOREACH(subregion, &parent->subregions, subregions_link) {
> > + if (subregion->addr == offs) {
> > + mr = subregion;
> > + break;
> > + }
> > + }
> > + return mr;
> > +}
> > +
> > static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
> > unsigned size)
> > {
> > @@ -279,7 +295,53 @@ static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
> > case 0xfd ... 0xff:
> > /* ignore write to read only registers */
> > return;
> > - /* case 0xe6 ... 0xe8: Should set base port of parallel and serial */
> > + case 0xe2:
> > + {
> > + data &= 0x1f;
> > + if (data & BIT(2)) { /* Serial port 1 enable */
> > + ISADevice *dev = sc->superio->serial[0];
> > + if (!memory_region_is_mapped(sc->serial_io[0])) {
> > + memory_region_add_subregion(isa_address_space_io(dev),
> > + dev->ioport_id, sc->serial_io[0]);
> > + }
> > + } else {
> > + MemoryRegion *io = isa_address_space_io(sc->superio->serial[0]);
> > + if (memory_region_is_mapped(sc->serial_io[0])) {
> > + memory_region_del_subregion(io, sc->serial_io[0]);
> > + }
> > + }
> > + if (data & BIT(3)) { /* Serial port 2 enable */
> > + ISADevice *dev = sc->superio->serial[1];
> > + if (!memory_region_is_mapped(sc->serial_io[1])) {
> > + memory_region_add_subregion(isa_address_space_io(dev),
> > + dev->ioport_id, sc->serial_io[1]);
> > + }
> > + } else {
> > + MemoryRegion *io = isa_address_space_io(sc->superio->serial[1]);
> > + if (memory_region_is_mapped(sc->serial_io[1])) {
> > + memory_region_del_subregion(io, sc->serial_io[1]);
> > + }
> > + }
> > + break;
> > + }
> > + case 0xe7: /* Serial port 1 io base address */
> > + {
> > + data &= 0xfe;
> > + sc->superio->serial[0]->ioport_id = data << 2;
> > + if (memory_region_is_mapped(sc->serial_io[0])) {
> > + memory_region_set_address(sc->serial_io[0], data << 2);
> > + }
> > + break;
> > + }
> > + case 0xe8: /* Serial port 2 io base address */
> > + {
> > + data &= 0xfe;
> > + sc->superio->serial[1]->ioport_id = data << 2;
> > + if (memory_region_is_mapped(sc->serial_io[1])) {
> > + memory_region_set_address(sc->serial_io[1], data << 2);
> > + }
> > + break;
> > + }
> > default:
> > qemu_log_mask(LOG_UNIMP,
> > "via_superio_cfg: unimplemented register 0x%x\n", idx);
> > @@ -385,6 +447,7 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
> > DeviceState *dev = DEVICE(d);
> > ISABus *isa_bus;
> > qemu_irq *isa_irq;
> > + ISASuperIOClass *ic;
> > int i;
> >
> > qdev_init_gpio_out(dev, &s->cpu_intr, 1);
> > @@ -394,7 +457,9 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
> > isa_bus_irqs(isa_bus, i8259_init(isa_bus, *isa_irq));
> > i8254_pit_init(isa_bus, 0x40, 0, NULL);
> > i8257_dma_init(isa_bus, 0);
> > - isa_create_simple(isa_bus, TYPE_VT82C686B_SUPERIO);
> > + s->superio_cfg.superio = ISA_SUPERIO(isa_create_simple(isa_bus,
> > + TYPE_VT82C686B_SUPERIO));
> > + ic = ISA_SUPERIO_GET_CLASS(s->superio_cfg.superio);
> > mc146818_rtc_init(isa_bus, 2000, NULL);
> >
> > for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) {
> > @@ -412,6 +477,21 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
> > */
> > memory_region_add_subregion(isa_bus->address_space_io, 0x3f0,
> > &s->superio_cfg.io);
> > +
> > + /* Grab io regions of serial devices so we can control them */
> > + for (i = 0; i < ic->serial.count; i++) {
> > + ISADevice *sd = s->superio_cfg.superio->serial[i];
> > + MemoryRegion *io = isa_address_space_io(sd);
> > + MemoryRegion *mr = find_subregion(sd, io, sd->ioport_id);
> > + if (!mr) {
> > + error_setg(errp, "Could not get io region for serial %d", i);
> > + return;
> > + }
> > + s->superio_cfg.serial_io[i] = mr;
> > + if (memory_region_is_mapped(mr)) {
> > + memory_region_del_subregion(io, mr);
> > + }
> > + }
> > }
> >
> > static void via_class_init(ObjectClass *klass, void *data)
> >
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 1/8] vt82c686: Implement control of serial port io ranges via config regs
2021-03-10 2:58 ` [PATCH v7 1/8] vt82c686: Implement control of serial port io ranges via config regs BALATON Zoltan
2021-03-11 23:47 ` Philippe Mathieu-Daudé
@ 2021-03-23 12:54 ` BALATON Zoltan
2021-03-23 21:58 ` Mark Cave-Ayland
1 sibling, 1 reply; 32+ messages in thread
From: BALATON Zoltan @ 2021-03-23 12:54 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: Peter Maydell, David Gibson, Mark Cave-Ayland, f4bug, Paolo Bonzini
On Wed, 10 Mar 2021, BALATON Zoltan wrote:
> In VIA super south bridge the io ranges of superio components
> (parallel and serial ports and FDC) can be controlled by superio
> config registers to set their base address and enable/disable them.
> This is not easy to implement in QEMU because ISA emulation is only
> designed to set io base address once on creating the device and io
> ranges are registered at creation and cannot easily be disabled or
> moved later.
>
> In this patch we hack around that but only for serial ports because
> those have a single io range at port base that's relatively easy to
> handle and it's what guests actually use and set address different
> than the default.
>
> We do not attempt to handle controlling the parallel and FDC regions
> because those have multiple io ranges so handling them would be messy
> and guests either don't change their deafult or don't care. We could
> even get away with disabling and not emulating them, but since they
> are already there, this patch leaves them mapped at their default
> address just in case this could be useful for a guest in the future.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Could this patch be reviewed now please? I've dropped it from later
versions to avoid this holding back the series but now that it won't be in
6.0 I'd like to go back to this. This is implementing the behaviour of the
real hardware better than the unsettable default value we have as a
replacement. That approach also works for the guests I've tried (MorphOS
and Linux) but if we can do better than why not do it?
Regards,
BALATON Zoltan
> ---
> hw/isa/vt82c686.c | 84 +++++++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 82 insertions(+), 2 deletions(-)
>
> diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
> index 05d084f698..a3353ec5db 100644
> --- a/hw/isa/vt82c686.c
> +++ b/hw/isa/vt82c686.c
> @@ -252,8 +252,24 @@ static const TypeInfo vt8231_pm_info = {
> typedef struct SuperIOConfig {
> uint8_t regs[0x100];
> MemoryRegion io;
> + ISASuperIODevice *superio;
> + MemoryRegion *serial_io[SUPERIO_MAX_SERIAL_PORTS];
> } SuperIOConfig;
>
> +static MemoryRegion *find_subregion(ISADevice *d, MemoryRegion *parent,
> + int offs)
> +{
> + MemoryRegion *subregion, *mr = NULL;
> +
> + QTAILQ_FOREACH(subregion, &parent->subregions, subregions_link) {
> + if (subregion->addr == offs) {
> + mr = subregion;
> + break;
> + }
> + }
> + return mr;
> +}
> +
> static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
> unsigned size)
> {
> @@ -279,7 +295,53 @@ static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data,
> case 0xfd ... 0xff:
> /* ignore write to read only registers */
> return;
> - /* case 0xe6 ... 0xe8: Should set base port of parallel and serial */
> + case 0xe2:
> + {
> + data &= 0x1f;
> + if (data & BIT(2)) { /* Serial port 1 enable */
> + ISADevice *dev = sc->superio->serial[0];
> + if (!memory_region_is_mapped(sc->serial_io[0])) {
> + memory_region_add_subregion(isa_address_space_io(dev),
> + dev->ioport_id, sc->serial_io[0]);
> + }
> + } else {
> + MemoryRegion *io = isa_address_space_io(sc->superio->serial[0]);
> + if (memory_region_is_mapped(sc->serial_io[0])) {
> + memory_region_del_subregion(io, sc->serial_io[0]);
> + }
> + }
> + if (data & BIT(3)) { /* Serial port 2 enable */
> + ISADevice *dev = sc->superio->serial[1];
> + if (!memory_region_is_mapped(sc->serial_io[1])) {
> + memory_region_add_subregion(isa_address_space_io(dev),
> + dev->ioport_id, sc->serial_io[1]);
> + }
> + } else {
> + MemoryRegion *io = isa_address_space_io(sc->superio->serial[1]);
> + if (memory_region_is_mapped(sc->serial_io[1])) {
> + memory_region_del_subregion(io, sc->serial_io[1]);
> + }
> + }
> + break;
> + }
> + case 0xe7: /* Serial port 1 io base address */
> + {
> + data &= 0xfe;
> + sc->superio->serial[0]->ioport_id = data << 2;
> + if (memory_region_is_mapped(sc->serial_io[0])) {
> + memory_region_set_address(sc->serial_io[0], data << 2);
> + }
> + break;
> + }
> + case 0xe8: /* Serial port 2 io base address */
> + {
> + data &= 0xfe;
> + sc->superio->serial[1]->ioport_id = data << 2;
> + if (memory_region_is_mapped(sc->serial_io[1])) {
> + memory_region_set_address(sc->serial_io[1], data << 2);
> + }
> + break;
> + }
> default:
> qemu_log_mask(LOG_UNIMP,
> "via_superio_cfg: unimplemented register 0x%x\n", idx);
> @@ -385,6 +447,7 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
> DeviceState *dev = DEVICE(d);
> ISABus *isa_bus;
> qemu_irq *isa_irq;
> + ISASuperIOClass *ic;
> int i;
>
> qdev_init_gpio_out(dev, &s->cpu_intr, 1);
> @@ -394,7 +457,9 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
> isa_bus_irqs(isa_bus, i8259_init(isa_bus, *isa_irq));
> i8254_pit_init(isa_bus, 0x40, 0, NULL);
> i8257_dma_init(isa_bus, 0);
> - isa_create_simple(isa_bus, TYPE_VT82C686B_SUPERIO);
> + s->superio_cfg.superio = ISA_SUPERIO(isa_create_simple(isa_bus,
> + TYPE_VT82C686B_SUPERIO));
> + ic = ISA_SUPERIO_GET_CLASS(s->superio_cfg.superio);
> mc146818_rtc_init(isa_bus, 2000, NULL);
>
> for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) {
> @@ -412,6 +477,21 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
> */
> memory_region_add_subregion(isa_bus->address_space_io, 0x3f0,
> &s->superio_cfg.io);
> +
> + /* Grab io regions of serial devices so we can control them */
> + for (i = 0; i < ic->serial.count; i++) {
> + ISADevice *sd = s->superio_cfg.superio->serial[i];
> + MemoryRegion *io = isa_address_space_io(sd);
> + MemoryRegion *mr = find_subregion(sd, io, sd->ioport_id);
> + if (!mr) {
> + error_setg(errp, "Could not get io region for serial %d", i);
> + return;
> + }
> + s->superio_cfg.serial_io[i] = mr;
> + if (memory_region_is_mapped(mr)) {
> + memory_region_del_subregion(io, mr);
> + }
> + }
> }
>
> static void via_class_init(ObjectClass *klass, void *data)
>
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v7 1/8] vt82c686: Implement control of serial port io ranges via config regs
2021-03-23 12:54 ` BALATON Zoltan
@ 2021-03-23 21:58 ` Mark Cave-Ayland
2021-03-23 23:13 ` BALATON Zoltan
0 siblings, 1 reply; 32+ messages in thread
From: Mark Cave-Ayland @ 2021-03-23 21:58 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc
Cc: Peter Maydell, David Gibson, f4bug, Paolo Bonzini
On 23/03/2021 12:54, BALATON Zoltan wrote:
> On Wed, 10 Mar 2021, BALATON Zoltan wrote:
>> In VIA super south bridge the io ranges of superio components
>> (parallel and serial ports and FDC) can be controlled by superio
>> config registers to set their base address and enable/disable them.
>> This is not easy to implement in QEMU because ISA emulation is only
>> designed to set io base address once on creating the device and io
>> ranges are registered at creation and cannot easily be disabled or
>> moved later.
>>
>> In this patch we hack around that but only for serial ports because
>> those have a single io range at port base that's relatively easy to
>> handle and it's what guests actually use and set address different
>> than the default.
>>
>> We do not attempt to handle controlling the parallel and FDC regions
>> because those have multiple io ranges so handling them would be messy
>> and guests either don't change their deafult or don't care. We could
>> even get away with disabling and not emulating them, but since they
>> are already there, this patch leaves them mapped at their default
>> address just in case this could be useful for a guest in the future.
>>
>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>
> Could this patch be reviewed now please? I've dropped it from later versions to avoid
> this holding back the series but now that it won't be in 6.0 I'd like to go back to
> this. This is implementing the behaviour of the real hardware better than the
> unsettable default value we have as a replacement. That approach also works for the
> guests I've tried (MorphOS and Linux) but if we can do better than why not do it?
Do bear in mind that several people have already looked at this patch and haven't
felt comfortable enough to review it, and I've also said in a previous email that
this isn't the right approach. Given that the ISA bus partly uses the ioport address
to reference the device, manually moving the memory regions around for devices on the
bus without the ISA bus seeing those changes is going to cause issues.
IIRC the ability to dynamically change the standard ISA addresses was present in
several motherboards from that era, and given that this functionality hasn't been
implemented in QEMU this already tells us that no firmware is currently is using it.
I don't understand why using the hard-coded addresses in the v10 is a problem here?
The addresses you added in the comments representing the programmed values are the
standard ISA device addresses, so if those are what the firmware is programming then
there will be no change. You also reported that it works fine with both your MorphOS
and Linux test images, indicating that neither of these guest OSs require the feature.
If you find a guest OS that needs the functionality then certainly we can talk about
trying to come up with a solution, but for me the extra complexity of this approach
and the fact that you're overriding the management of the device by the ISA bus is
why I haven't given it a R-B tag (I should add that my R-B for v10 using the
hard-coded ISA addresses still stands).
ATB,
Mark.
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 1/8] vt82c686: Implement control of serial port io ranges via config regs
2021-03-23 21:58 ` Mark Cave-Ayland
@ 2021-03-23 23:13 ` BALATON Zoltan
0 siblings, 0 replies; 32+ messages in thread
From: BALATON Zoltan @ 2021-03-23 23:13 UTC (permalink / raw)
To: Mark Cave-Ayland
Cc: Peter Maydell, f4bug, qemu-devel, qemu-ppc, Paolo Bonzini, David Gibson
On Tue, 23 Mar 2021, Mark Cave-Ayland wrote:
> On 23/03/2021 12:54, BALATON Zoltan wrote:
>> On Wed, 10 Mar 2021, BALATON Zoltan wrote:
>>> In VIA super south bridge the io ranges of superio components
>>> (parallel and serial ports and FDC) can be controlled by superio
>>> config registers to set their base address and enable/disable them.
>>> This is not easy to implement in QEMU because ISA emulation is only
>>> designed to set io base address once on creating the device and io
>>> ranges are registered at creation and cannot easily be disabled or
>>> moved later.
>>>
>>> In this patch we hack around that but only for serial ports because
>>> those have a single io range at port base that's relatively easy to
>>> handle and it's what guests actually use and set address different
>>> than the default.
>>>
>>> We do not attempt to handle controlling the parallel and FDC regions
>>> because those have multiple io ranges so handling them would be messy
>>> and guests either don't change their deafult or don't care. We could
>>> even get away with disabling and not emulating them, but since they
>>> are already there, this patch leaves them mapped at their default
>>> address just in case this could be useful for a guest in the future.
>>>
>>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>>
>> Could this patch be reviewed now please? I've dropped it from later
>> versions to avoid this holding back the series but now that it won't be in
>> 6.0 I'd like to go back to this. This is implementing the behaviour of the
>> real hardware better than the unsettable default value we have as a
>> replacement. That approach also works for the guests I've tried (MorphOS
>> and Linux) but if we can do better than why not do it?
>
> Do bear in mind that several people have already looked at this patch and
> haven't felt comfortable enough to review it, and I've also said in a
I haven't heard back from many people (mostly only Philippe and you and
maybe David looked at it but I did not expect him to review it as it's not
his area) so I had the impression nobody cared or had time to look at it.
That's why I've raised this again to get a clear answer about it. Now that
at least you dislike this patch it's good enough reason to drop it for now
and go with the default value instead until a guest is found to need this
functionality.
> previous email that this isn't the right approach. Given that the ISA bus
> partly uses the ioport address to reference the device, manually moving the
> memory regions around for devices on the bus without the ISA bus seeing those
> changes is going to cause issues.
The ioport_id you refer to is only used to print device name so the only
issue is that the device may be currently mapped to a different address
than its name might suggest when you query it but that should not break
any functionality so maybe only cosmetic. The current ISA bus emulation in
QEMU does not care about ISA devices after they are created, they are just
initialised once and then the bus seems to forget about them. At least
there are no functions to enable/disable or control them afterwards, only
to register them at startup. So it's static and does not allow dynamically
changing devices like we have in these VTxxx chips. (By the way, this is
the same problem via-ide has that required hacks instead of actually
emulating what the chip does because we can't have both ISA IDE and PCI
IDE as the ISA one cannot be moved or disabled once created.) That's what
this patch tried to circumvent at least for serial ports but without
completly changing ISA emulation which might be a better approach but well
beyond the effort I'm willing to put into this.
> IIRC the ability to dynamically change the standard ISA addresses was present
> in several motherboards from that era, and given that this functionality
> hasn't been implemented in QEMU this already tells us that no firmware is
> currently is using it.
QEMU only supports SeaBIOS and on PC the ports are usually at their
default address at startup so it's probably not firmware but guests that
could change it. I don't know what other BIOSes might do as those don't
run on QEMU. But these VTxxx chips are not used on PC machine models. The
fuloong2e PMON and pegasos2 SmartFirtmware seem to poke the regs enabling
and setting port address of these at startup (otherwise the chip seems to
start without these enabled) so I've tried to emulate that. On pegasos2 it
even uses different than usual standard value (as it only has one serial
port) and guests boot with that so we can use that default. It's not
exactly how the real device works but satisfies guests that rely on
firmware to set up these and don't touch it later.
> I don't understand why using the hard-coded addresses in the v10 is a problem
> here? The addresses you added in the comments representing the programmed
> values are the standard ISA device addresses, so if those are what the
> firmware is programming then there will be no change. You also reported that
> it works fine with both your MorphOS and Linux test images, indicating that
> neither of these guest OSs require the feature.
For now the default address will do until a guest is found actually
needing this. I just wanted to salvage this patch before dismissing it
without a good reason.
> If you find a guest OS that needs the functionality then certainly we can
> talk about trying to come up with a solution, but for me the extra complexity
> of this approach and the fact that you're overriding the management of the
> device by the ISA bus is why I haven't given it a R-B tag (I should add that
> my R-B for v10 using the hard-coded ISA addresses still stands).
OK then forget it, at least this is a clear vote against this patch and if
others don't care that means it should be dropped. Thanks for explaining
it again.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v7 8/8] hw/ppc: Add emulation of Genesi/bPlan Pegasos II
2021-03-10 2:58 [PATCH v7 0/8] Pegasos2 emulation BALATON Zoltan
` (2 preceding siblings ...)
2021-03-10 2:58 ` [PATCH v7 1/8] vt82c686: Implement control of serial port io ranges via config regs BALATON Zoltan
@ 2021-03-10 2:58 ` BALATON Zoltan
2021-03-10 2:58 ` [PATCH v7 7/8] hw/pci-host: Add emulation of Marvell MV64361 PPC system controller BALATON Zoltan
` (4 subsequent siblings)
8 siblings, 0 replies; 32+ messages in thread
From: BALATON Zoltan @ 2021-03-10 2:58 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Peter Maydell, Paolo Bonzini, f4bug, David Gibson
Add new machine called pegasos2 emulating the Genesi/bPlan Pegasos II,
a PowerPC board based on the Marvell MV64361 system controller and the
VIA VT8231 integrated south bridge/superio chips. It can run Linux,
AmigaOS and a wide range of MorphOS versions. Currently a firmware ROM
image is needed to boot and only MorphOS has a video driver to produce
graphics output. Linux could work too but distros that supported this
machine don't include usual video drivers so those only run with
serial console for now.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
MAINTAINERS | 10 ++
default-configs/devices/ppc-softmmu.mak | 2 +
hw/ppc/Kconfig | 9 ++
hw/ppc/meson.build | 2 +
hw/ppc/pegasos2.c | 144 ++++++++++++++++++++++++
5 files changed, 167 insertions(+)
create mode 100644 hw/ppc/pegasos2.c
diff --git a/MAINTAINERS b/MAINTAINERS
index f22d83c178..c363b6ad1e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1345,6 +1345,16 @@ F: pc-bios/canyonlands.dt[sb]
F: pc-bios/u-boot-sam460ex-20100605.bin
F: roms/u-boot-sam460ex
+pegasos2
+M: BALATON Zoltan <balaton@eik.bme.hu>
+R: David Gibson <david@gibson.dropbear.id.au>
+L: qemu-ppc@nongnu.org
+S: Maintained
+F: hw/ppc/pegasos2.c
+F: hw/pci-host/mv64361.c
+F: hw/pci-host/mv643xx.h
+F: include/hw/pci-host/mv64361.h
+
RISC-V Machines
---------------
OpenTitan
diff --git a/default-configs/devices/ppc-softmmu.mak b/default-configs/devices/ppc-softmmu.mak
index 61b78b844d..4535993d8d 100644
--- a/default-configs/devices/ppc-softmmu.mak
+++ b/default-configs/devices/ppc-softmmu.mak
@@ -14,5 +14,7 @@ CONFIG_SAM460EX=y
CONFIG_MAC_OLDWORLD=y
CONFIG_MAC_NEWWORLD=y
+CONFIG_PEGASOS2=y
+
# For PReP
CONFIG_PREP=y
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index d11dc30509..e51e0e5e5a 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -68,6 +68,15 @@ config SAM460EX
select USB_OHCI
select FDT_PPC
+config PEGASOS2
+ bool
+ select MV64361
+ select VT82C686
+ select IDE_VIA
+ select SMBUS_EEPROM
+# This should come with VT82C686
+ select ACPI_X86
+
config PREP
bool
imply PCI_DEVICES
diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build
index 218631c883..86d6f379d1 100644
--- a/hw/ppc/meson.build
+++ b/hw/ppc/meson.build
@@ -78,5 +78,7 @@ ppc_ss.add(when: 'CONFIG_E500', if_true: files(
))
# PowerPC 440 Xilinx ML507 reference board.
ppc_ss.add(when: 'CONFIG_VIRTEX', if_true: files('virtex_ml507.c'))
+# Pegasos2
+ppc_ss.add(when: 'CONFIG_PEGASOS2', if_true: files('pegasos2.c'))
hw_arch += {'ppc': ppc_ss}
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
new file mode 100644
index 0000000000..0bfd0928aa
--- /dev/null
+++ b/hw/ppc/pegasos2.c
@@ -0,0 +1,144 @@
+/*
+ * QEMU PowerPC CHRP (Genesi/bPlan Pegasos II) hardware System Emulator
+ *
+ * Copyright (c) 2018-2020 BALATON Zoltan
+ *
+ * This work is licensed under the GNU GPL license version 2 or later.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "qemu/units.h"
+#include "qapi/error.h"
+#include "hw/hw.h"
+#include "hw/ppc/ppc.h"
+#include "hw/sysbus.h"
+#include "hw/pci/pci_host.h"
+#include "hw/irq.h"
+#include "hw/pci-host/mv64361.h"
+#include "hw/isa/vt82c686.h"
+#include "hw/ide/pci.h"
+#include "hw/i2c/smbus_eeprom.h"
+#include "hw/qdev-properties.h"
+#include "sysemu/reset.h"
+#include "hw/boards.h"
+#include "hw/loader.h"
+#include "hw/fw-path-provider.h"
+#include "elf.h"
+#include "qemu/log.h"
+#include "qemu/error-report.h"
+#include "sysemu/kvm.h"
+#include "kvm_ppc.h"
+#include "exec/address-spaces.h"
+#include "trace.h"
+#include "qemu/datadir.h"
+#include "sysemu/device_tree.h"
+
+#define PROM_FILENAME "pegasos2.rom"
+#define PROM_ADDR 0xfff00000
+#define PROM_SIZE 0x80000
+
+#define BUS_FREQ_HZ 133333333
+
+static void pegasos2_cpu_reset(void *opaque)
+{
+ PowerPCCPU *cpu = opaque;
+
+ cpu_reset(CPU(cpu));
+ cpu->env.spr[SPR_HID1] = 7ULL << 28;
+}
+
+static void pegasos2_init(MachineState *machine)
+{
+ PowerPCCPU *cpu = NULL;
+ MemoryRegion *rom = g_new(MemoryRegion, 1);
+ DeviceState *mv;
+ PCIBus *pci_bus;
+ PCIDevice *dev;
+ I2CBus *i2c_bus;
+ const char *fwname = machine->firmware ?: PROM_FILENAME;
+ char *filename;
+ int sz;
+ uint8_t *spd_data;
+
+ /* init CPU */
+ cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
+ if (PPC_INPUT(&cpu->env) != PPC_FLAGS_INPUT_6xx) {
+ error_report("Incompatible CPU, only 6xx bus supported");
+ exit(1);
+ }
+
+ /* Set time-base frequency */
+ cpu_ppc_tb_init(&cpu->env, BUS_FREQ_HZ / 4);
+ qemu_register_reset(pegasos2_cpu_reset, cpu);
+
+ /* RAM */
+ memory_region_add_subregion(get_system_memory(), 0, machine->ram);
+
+ /* allocate and load firmware */
+ filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, fwname);
+ if (!filename) {
+ error_report("Could not find firmware '%s'", fwname);
+ exit(1);
+ }
+ memory_region_init_rom(rom, NULL, "pegasos2.rom", PROM_SIZE, &error_fatal);
+ memory_region_add_subregion(get_system_memory(), PROM_ADDR, rom);
+ sz = load_elf(filename, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 1,
+ PPC_ELF_MACHINE, 0, 0);
+ if (sz <= 0) {
+ sz = load_image_targphys(filename, PROM_ADDR, PROM_SIZE);
+ }
+ if (sz <= 0 || sz > PROM_SIZE) {
+ error_report("Could not load firmware '%s'", filename);
+ exit(1);
+ }
+ g_free(filename);
+
+ /* Marvell Discovery II system controller */
+ mv = DEVICE(sysbus_create_simple(TYPE_MV64361, -1,
+ ((qemu_irq *)cpu->env.irq_inputs)[PPC6xx_INPUT_INT]));
+ pci_bus = mv64361_get_pci_bus(mv, 1);
+
+ /* VIA VT8231 South Bridge (multifunction PCI device) */
+ /* VT8231 function 0: PCI-to-ISA Bridge */
+ dev = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(12, 0), true,
+ TYPE_VT8231_ISA);
+ qdev_connect_gpio_out(DEVICE(dev), 0,
+ qdev_get_gpio_in_named(mv, "gpp", 31));
+
+ /* VT8231 function 1: IDE Controller */
+ dev = pci_create_simple(pci_bus, PCI_DEVFN(12, 1), "via-ide");
+ pci_ide_create_devs(dev);
+
+ /* VT8231 function 2-3: USB Ports */
+ pci_create_simple(pci_bus, PCI_DEVFN(12, 2), "vt82c686b-usb-uhci");
+ pci_create_simple(pci_bus, PCI_DEVFN(12, 3), "vt82c686b-usb-uhci");
+
+ /* VT8231 function 4: Power Management Controller */
+ dev = pci_create_simple(pci_bus, PCI_DEVFN(12, 4), TYPE_VT8231_PM);
+ i2c_bus = I2C_BUS(qdev_get_child_bus(DEVICE(dev), "i2c"));
+ spd_data = spd_data_generate(DDR, machine->ram_size);
+ smbus_eeprom_init_one(i2c_bus, 0x57, spd_data);
+
+ /* VT8231 function 5-6: AC97 Audio & Modem */
+ pci_create_simple(pci_bus, PCI_DEVFN(12, 5), TYPE_VIA_AC97);
+ pci_create_simple(pci_bus, PCI_DEVFN(12, 6), TYPE_VIA_MC97);
+
+ /* other PC hardware */
+ pci_vga_init(pci_bus);
+}
+
+static void pegasos2_machine(MachineClass *mc)
+{
+ mc->desc = "Genesi/bPlan Pegasos II";
+ mc->init = pegasos2_init;
+ mc->block_default_type = IF_IDE;
+ mc->default_boot_order = "cd";
+ mc->default_display = "std";
+ mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9");
+ mc->default_ram_id = "pegasos2.ram";
+ mc->default_ram_size = 512 * MiB;
+}
+
+DEFINE_MACHINE("pegasos2", pegasos2_machine)
--
2.21.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v7 7/8] hw/pci-host: Add emulation of Marvell MV64361 PPC system controller
2021-03-10 2:58 [PATCH v7 0/8] Pegasos2 emulation BALATON Zoltan
` (3 preceding siblings ...)
2021-03-10 2:58 ` [PATCH v7 8/8] hw/ppc: Add emulation of Genesi/bPlan Pegasos II BALATON Zoltan
@ 2021-03-10 2:58 ` BALATON Zoltan
2021-03-10 2:58 ` [PATCH v7 5/8] vt82c686: Add emulation of VT8231 south bridge BALATON Zoltan
` (3 subsequent siblings)
8 siblings, 0 replies; 32+ messages in thread
From: BALATON Zoltan @ 2021-03-10 2:58 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Peter Maydell, Paolo Bonzini, f4bug, David Gibson
The Marvell Discovery II aka. MV64361 is a PowerPC system controller
chip that is used on the pegasos2 PPC board. This adds emulation of it
that models the device enough to boot guests on this board. The
mv643xx.h header with register definitions is taken from Linux 4.15.10
only fixing white space errors, removing not needed parts and changing
formatting for QEMU coding style.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/pci-host/Kconfig | 4 +
hw/pci-host/meson.build | 2 +
hw/pci-host/mv64361.c | 966 ++++++++++++++++++++++++++++++++++
hw/pci-host/mv643xx.h | 918 ++++++++++++++++++++++++++++++++
hw/pci-host/trace-events | 6 +
include/hw/pci-host/mv64361.h | 8 +
include/hw/pci/pci_ids.h | 1 +
7 files changed, 1905 insertions(+)
create mode 100644 hw/pci-host/mv64361.c
create mode 100644 hw/pci-host/mv643xx.h
create mode 100644 include/hw/pci-host/mv64361.h
diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig
index 2ccc96f02c..79c20bf28b 100644
--- a/hw/pci-host/Kconfig
+++ b/hw/pci-host/Kconfig
@@ -72,3 +72,7 @@ config REMOTE_PCIHOST
config SH_PCI
bool
select PCI
+
+config MV64361
+ bool
+ select PCI
diff --git a/hw/pci-host/meson.build b/hw/pci-host/meson.build
index 87a896973e..34b3538beb 100644
--- a/hw/pci-host/meson.build
+++ b/hw/pci-host/meson.build
@@ -19,6 +19,8 @@ pci_ss.add(when: 'CONFIG_GRACKLE_PCI', if_true: files('grackle.c'))
pci_ss.add(when: 'CONFIG_UNIN_PCI', if_true: files('uninorth.c'))
# PowerPC E500 boards
pci_ss.add(when: 'CONFIG_PPCE500_PCI', if_true: files('ppce500.c'))
+# Pegasos2
+pci_ss.add(when: 'CONFIG_MV64361', if_true: files('mv64361.c'))
# ARM devices
pci_ss.add(when: 'CONFIG_VERSATILE_PCI', if_true: files('versatile.c'))
diff --git a/hw/pci-host/mv64361.c b/hw/pci-host/mv64361.c
new file mode 100644
index 0000000000..d71402f8b5
--- /dev/null
+++ b/hw/pci-host/mv64361.c
@@ -0,0 +1,966 @@
+/*
+ * Marvell Discovery II MV64361 System Controller for
+ * QEMU PowerPC CHRP (Genesi/bPlan Pegasos II) hardware System Emulator
+ *
+ * Copyright (c) 2018-2020 BALATON Zoltan
+ *
+ * This work is licensed under the GNU GPL license version 2 or later.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "qemu/units.h"
+#include "qapi/error.h"
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "hw/pci/pci.h"
+#include "hw/pci/pci_host.h"
+#include "hw/irq.h"
+#include "hw/intc/i8259.h"
+#include "hw/qdev-properties.h"
+#include "exec/address-spaces.h"
+#include "qemu/log.h"
+#include "qemu/error-report.h"
+#include "trace.h"
+#include "hw/pci-host/mv64361.h"
+#include "mv643xx.h"
+
+#define TYPE_MV64361_PCI_BRIDGE "mv64361-pcibridge"
+
+static void mv64361_pcibridge_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ k->vendor_id = PCI_VENDOR_ID_MARVELL;
+ k->device_id = PCI_DEVICE_ID_MARVELL_MV6436X;
+ k->class_id = PCI_CLASS_BRIDGE_HOST;
+ /*
+ * PCI-facing part of the host bridge,
+ * not usable without the host-facing part
+ */
+ dc->user_creatable = false;
+}
+
+static const TypeInfo mv64361_pcibridge_info = {
+ .name = TYPE_MV64361_PCI_BRIDGE,
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(PCIDevice),
+ .class_init = mv64361_pcibridge_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { INTERFACE_CONVENTIONAL_PCI_DEVICE },
+ { },
+ },
+};
+
+
+#define TYPE_MV64361_PCI "mv64361-pcihost"
+OBJECT_DECLARE_SIMPLE_TYPE(MV64361PCIState, MV64361_PCI)
+
+struct MV64361PCIState {
+ PCIHostState parent_obj;
+
+ uint8_t index;
+ MemoryRegion io;
+ MemoryRegion mem;
+ qemu_irq irq[PCI_NUM_PINS];
+
+ uint32_t io_base;
+ uint32_t io_size;
+ uint32_t mem_base[4];
+ uint32_t mem_size[4];
+ uint64_t remap[5];
+};
+
+static int mv64361_pcihost_map_irq(PCIDevice *pci_dev, int n)
+{
+ return (n + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
+}
+
+static void mv64361_pcihost_set_irq(void *opaque, int n, int level)
+{
+ MV64361PCIState *s = opaque;
+ qemu_set_irq(s->irq[n], level);
+}
+
+static void mv64361_pcihost_realize(DeviceState *dev, Error **errp)
+{
+ MV64361PCIState *s = MV64361_PCI(dev);
+ PCIHostState *h = PCI_HOST_BRIDGE(dev);
+ char *name;
+
+ name = g_strdup_printf("pci%d-io", s->index);
+ memory_region_init(&s->io, OBJECT(dev), name, 0x10000);
+ g_free(name);
+ name = g_strdup_printf("pci%d-mem", s->index);
+ memory_region_init(&s->mem, OBJECT(dev), name, 1ULL << 32);
+ g_free(name);
+ name = g_strdup_printf("pci.%d", s->index);
+ h->bus = pci_register_root_bus(dev, name, mv64361_pcihost_set_irq,
+ mv64361_pcihost_map_irq, dev,
+ &s->mem, &s->io, 0, 4, TYPE_PCI_BUS);
+ g_free(name);
+ pci_create_simple(h->bus, 0, TYPE_MV64361_PCI_BRIDGE);
+}
+
+static Property mv64361_pcihost_props[] = {
+ DEFINE_PROP_UINT8("index", MV64361PCIState, index, 0),
+ DEFINE_PROP_END_OF_LIST()
+};
+
+static void mv64361_pcihost_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = mv64361_pcihost_realize;
+ device_class_set_props(dc, mv64361_pcihost_props);
+ set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
+}
+
+static const TypeInfo mv64361_pcihost_info = {
+ .name = TYPE_MV64361_PCI,
+ .parent = TYPE_PCI_HOST_BRIDGE,
+ .instance_size = sizeof(MV64361PCIState),
+ .class_init = mv64361_pcihost_class_init,
+};
+
+static void mv64361_pci_register_types(void)
+{
+ type_register_static(&mv64361_pcihost_info);
+ type_register_static(&mv64361_pcibridge_info);
+}
+
+type_init(mv64361_pci_register_types)
+
+
+OBJECT_DECLARE_SIMPLE_TYPE(MV64361State, MV64361)
+
+struct MV64361State {
+ SysBusDevice parent_obj;
+
+ MemoryRegion regs;
+ MV64361PCIState pci[2];
+ MemoryRegion cpu_win[19];
+ qemu_irq cpu_irq;
+
+ /* registers state */
+ uint32_t cpu_conf;
+ uint32_t regs_base;
+ uint32_t base_addr_enable;
+ uint64_t main_int_cr;
+ uint64_t cpu0_int_mask;
+ uint32_t gpp_io;
+ uint32_t gpp_level;
+ uint32_t gpp_value;
+ uint32_t gpp_int_cr;
+ uint32_t gpp_int_mask;
+ bool gpp_int_level;
+};
+
+enum mv64361_irq_cause {
+ MV64361_IRQ_DEVERR = 1,
+ MV64361_IRQ_DMAERR,
+ MV64361_IRQ_CPUERR,
+ MV64361_IRQ_IDMA0,
+ MV64361_IRQ_IDMA1,
+ MV64361_IRQ_IDMA2,
+ MV64361_IRQ_IDMA3,
+ MV64361_IRQ_TIMER0,
+ MV64361_IRQ_TIMER1,
+ MV64361_IRQ_TIMER2,
+ MV64361_IRQ_TIMER3,
+ MV64361_IRQ_PCI0,
+ MV64361_IRQ_SRAMERR,
+ MV64361_IRQ_GBEERR,
+ MV64361_IRQ_CERR,
+ MV64361_IRQ_PCI1,
+ MV64361_IRQ_DRAMERR,
+ MV64361_IRQ_WDNMI,
+ MV64361_IRQ_WDE,
+ MV64361_IRQ_PCI0IN,
+ MV64361_IRQ_PCI0OUT,
+ MV64361_IRQ_PCI1IN,
+ MV64361_IRQ_PCI1OUT,
+ MV64361_IRQ_P1_GPP0_7,
+ MV64361_IRQ_P1_GPP8_15,
+ MV64361_IRQ_P1_GPP16_23,
+ MV64361_IRQ_P1_GPP24_31,
+ MV64361_IRQ_P1_CPU_DB,
+ /* 29-31: reserved */
+ MV64361_IRQ_GBE0 = 32,
+ MV64361_IRQ_GBE1,
+ MV64361_IRQ_GBE2,
+ /* 35: reserved */
+ MV64361_IRQ_SDMA0 = 36,
+ MV64361_IRQ_TWSI,
+ MV64361_IRQ_SDMA1,
+ MV64361_IRQ_BRG,
+ MV64361_IRQ_MPSC0,
+ MV64361_IRQ_MPSC1,
+ MV64361_IRQ_G0RX,
+ MV64361_IRQ_G0TX,
+ MV64361_IRQ_G0MISC,
+ MV64361_IRQ_G1RX,
+ MV64361_IRQ_G1TX,
+ MV64361_IRQ_G1MISC,
+ MV64361_IRQ_G2RX,
+ MV64361_IRQ_G2TX,
+ MV64361_IRQ_G2MISC,
+ /* 51-55: reserved */
+ MV64361_IRQ_P0_GPP0_7 = 56,
+ MV64361_IRQ_P0_GPP8_15,
+ MV64361_IRQ_P0_GPP16_23,
+ MV64361_IRQ_P0_GPP24_31,
+ MV64361_IRQ_P0_CPU_DB,
+ /* 61-63: reserved */
+};
+
+PCIBus *mv64361_get_pci_bus(DeviceState *dev, int n)
+{
+ MV64361State *mv = MV64361(dev);
+ return PCI_HOST_BRIDGE(&mv->pci[n])->bus;
+}
+
+static void unmap_region(MemoryRegion *mr)
+{
+ if (memory_region_is_mapped(mr)) {
+ memory_region_del_subregion(get_system_memory(), mr);
+ object_unparent(OBJECT(mr));
+ }
+}
+
+static void map_pci_region(MemoryRegion *mr, MemoryRegion *parent,
+ struct Object *owner, const char *name,
+ hwaddr poffs, uint64_t size, hwaddr moffs)
+{
+ memory_region_init_alias(mr, owner, name, parent, poffs, size);
+ memory_region_add_subregion(get_system_memory(), moffs, mr);
+ trace_mv64361_region_map(name, poffs, size, moffs);
+}
+
+static void setup_mem_windows(MV64361State *s, uint32_t val)
+{
+ MV64361PCIState *p;
+ MemoryRegion *mr;
+ uint32_t mask;
+ int i;
+
+ val &= 0x1fffff;
+ for (mask = 1, i = 0; i < 21; i++, mask <<= 1) {
+ if ((val & mask) != (s->base_addr_enable & mask)) {
+ trace_mv64361_region_enable(!(val & mask) ? "enable" : "disable", i);
+ switch (i) {
+ /*
+ * 0-3 are SDRAM chip selects but we map all RAM directly
+ * 4-7 are device chip selects (not sure what those are)
+ * 8 is Boot device (ROM) chip select but we map that directly too
+ */
+ case 9:
+ p = &s->pci[0];
+ mr = &s->cpu_win[i];
+ unmap_region(mr);
+ if (!(val & mask)) {
+ map_pci_region(mr, &p->io, OBJECT(s), "pci0-io-win",
+ p->remap[4], (p->io_size + 1) << 16,
+ (p->io_base & 0xfffff) << 16);
+ }
+ break;
+ case 10:
+ p = &s->pci[0];
+ mr = &s->cpu_win[i];
+ unmap_region(mr);
+ if (!(val & mask)) {
+ map_pci_region(mr, &p->mem, OBJECT(s), "pci0-mem0-win",
+ p->remap[0], (p->mem_size[0] + 1) << 16,
+ (p->mem_base[0] & 0xfffff) << 16);
+ }
+ break;
+ case 11:
+ p = &s->pci[0];
+ mr = &s->cpu_win[i];
+ unmap_region(mr);
+ if (!(val & mask)) {
+ map_pci_region(mr, &p->mem, OBJECT(s), "pci0-mem1-win",
+ p->remap[1], (p->mem_size[1] + 1) << 16,
+ (p->mem_base[1] & 0xfffff) << 16);
+ }
+ break;
+ case 12:
+ p = &s->pci[0];
+ mr = &s->cpu_win[i];
+ unmap_region(mr);
+ if (!(val & mask)) {
+ map_pci_region(mr, &p->mem, OBJECT(s), "pci0-mem2-win",
+ p->remap[2], (p->mem_size[2] + 1) << 16,
+ (p->mem_base[2] & 0xfffff) << 16);
+ }
+ break;
+ case 13:
+ p = &s->pci[0];
+ mr = &s->cpu_win[i];
+ unmap_region(mr);
+ if (!(val & mask)) {
+ map_pci_region(mr, &p->mem, OBJECT(s), "pci0-mem3-win",
+ p->remap[3], (p->mem_size[3] + 1) << 16,
+ (p->mem_base[3] & 0xfffff) << 16);
+ }
+ break;
+ case 14:
+ p = &s->pci[1];
+ mr = &s->cpu_win[i];
+ unmap_region(mr);
+ if (!(val & mask)) {
+ map_pci_region(mr, &p->io, OBJECT(s), "pci1-io-win",
+ p->remap[4], (p->io_size + 1) << 16,
+ (p->io_base & 0xfffff) << 16);
+ }
+ break;
+ case 15:
+ p = &s->pci[1];
+ mr = &s->cpu_win[i];
+ unmap_region(mr);
+ if (!(val & mask)) {
+ map_pci_region(mr, &p->mem, OBJECT(s), "pci1-mem0-win",
+ p->remap[0], (p->mem_size[0] + 1) << 16,
+ (p->mem_base[0] & 0xfffff) << 16);
+ }
+ break;
+ case 16:
+ p = &s->pci[1];
+ mr = &s->cpu_win[i];
+ unmap_region(mr);
+ if (!(val & mask)) {
+ map_pci_region(mr, &p->mem, OBJECT(s), "pci1-mem1-win",
+ p->remap[1], (p->mem_size[1] + 1) << 16,
+ (p->mem_base[1] & 0xfffff) << 16);
+ }
+ break;
+ case 17:
+ p = &s->pci[1];
+ mr = &s->cpu_win[i];
+ unmap_region(mr);
+ if (!(val & mask)) {
+ map_pci_region(mr, &p->mem, OBJECT(s), "pci1-mem2-win",
+ p->remap[2], (p->mem_size[2] + 1) << 16,
+ (p->mem_base[2] & 0xfffff) << 16);
+ }
+ break;
+ case 18:
+ p = &s->pci[1];
+ mr = &s->cpu_win[i];
+ unmap_region(mr);
+ if (!(val & mask)) {
+ map_pci_region(mr, &p->mem, OBJECT(s), "pci1-mem3-win",
+ p->remap[3], (p->mem_size[3] + 1) << 16,
+ (p->mem_base[3] & 0xfffff) << 16);
+ }
+ break;
+ /* 19 is integrated SRAM */
+ case 20:
+ mr = &s->regs;
+ unmap_region(mr);
+ if (!(val & mask)) {
+ memory_region_add_subregion(get_system_memory(),
+ (s->regs_base & 0xfffff) << 16, mr);
+ }
+ break;
+ }
+ }
+ }
+}
+
+static void mv64361_update_irq(void *opaque, int n, int level)
+{
+ MV64361State *s = opaque;
+ uint64_t val = s->main_int_cr;
+
+ if (level) {
+ val |= BIT_ULL(n);
+ } else {
+ val &= ~BIT_ULL(n);
+ }
+ if ((s->main_int_cr & s->cpu0_int_mask) != (val & s->cpu0_int_mask)) {
+ qemu_set_irq(s->cpu_irq, level);
+ }
+ s->main_int_cr = val;
+}
+
+static uint64_t mv64361_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ MV64361State *s = MV64361(opaque);
+ uint32_t ret = 0;
+
+ switch (addr) {
+ case MV64340_CPU_CONFIG:
+ ret = s->cpu_conf;
+ break;
+ case MV64340_PCI_0_IO_BASE_ADDR:
+ ret = s->pci[0].io_base;
+ break;
+ case MV64340_PCI_0_IO_SIZE:
+ ret = s->pci[0].io_size;
+ break;
+ case MV64340_PCI_0_IO_ADDR_REMAP:
+ ret = s->pci[0].remap[4] >> 16;
+ break;
+ case MV64340_PCI_0_MEMORY0_BASE_ADDR:
+ ret = s->pci[0].mem_base[0];
+ break;
+ case MV64340_PCI_0_MEMORY0_SIZE:
+ ret = s->pci[0].mem_size[0];
+ break;
+ case MV64340_PCI_0_MEMORY0_LOW_ADDR_REMAP:
+ ret = (s->pci[0].remap[0] & 0xffff0000) >> 16;
+ break;
+ case MV64340_PCI_0_MEMORY0_HIGH_ADDR_REMAP:
+ ret = s->pci[0].remap[0] >> 32;
+ break;
+ case MV64340_PCI_0_MEMORY1_BASE_ADDR:
+ ret = s->pci[0].mem_base[1];
+ break;
+ case MV64340_PCI_0_MEMORY1_SIZE:
+ ret = s->pci[0].mem_size[1];
+ break;
+ case MV64340_PCI_0_MEMORY1_LOW_ADDR_REMAP:
+ ret = (s->pci[0].remap[1] & 0xffff0000) >> 16;
+ break;
+ case MV64340_PCI_0_MEMORY1_HIGH_ADDR_REMAP:
+ ret = s->pci[0].remap[1] >> 32;
+ break;
+ case MV64340_PCI_0_MEMORY2_BASE_ADDR:
+ ret = s->pci[0].mem_base[2];
+ break;
+ case MV64340_PCI_0_MEMORY2_SIZE:
+ ret = s->pci[0].mem_size[2];
+ break;
+ case MV64340_PCI_0_MEMORY2_LOW_ADDR_REMAP:
+ ret = (s->pci[0].remap[2] & 0xffff0000) >> 16;
+ break;
+ case MV64340_PCI_0_MEMORY2_HIGH_ADDR_REMAP:
+ ret = s->pci[0].remap[2] >> 32;
+ break;
+ case MV64340_PCI_0_MEMORY3_BASE_ADDR:
+ ret = s->pci[0].mem_base[3];
+ break;
+ case MV64340_PCI_0_MEMORY3_SIZE:
+ ret = s->pci[0].mem_size[3];
+ break;
+ case MV64340_PCI_0_MEMORY3_LOW_ADDR_REMAP:
+ ret = (s->pci[0].remap[3] & 0xffff0000) >> 16;
+ break;
+ case MV64340_PCI_0_MEMORY3_HIGH_ADDR_REMAP:
+ ret = s->pci[0].remap[3] >> 32;
+ break;
+ case MV64340_PCI_1_IO_BASE_ADDR:
+ ret = s->pci[1].io_base;
+ break;
+ case MV64340_PCI_1_IO_SIZE:
+ ret = s->pci[1].io_size;
+ break;
+ case MV64340_PCI_1_IO_ADDR_REMAP:
+ ret = s->pci[1].remap[4] >> 16;
+ break;
+ case MV64340_PCI_1_MEMORY0_BASE_ADDR:
+ ret = s->pci[1].mem_base[0];
+ break;
+ case MV64340_PCI_1_MEMORY0_SIZE:
+ ret = s->pci[1].mem_size[0];
+ break;
+ case MV64340_PCI_1_MEMORY0_LOW_ADDR_REMAP:
+ ret = (s->pci[1].remap[0] & 0xffff0000) >> 16;
+ break;
+ case MV64340_PCI_1_MEMORY0_HIGH_ADDR_REMAP:
+ ret = s->pci[1].remap[0] >> 32;
+ break;
+ case MV64340_PCI_1_MEMORY1_BASE_ADDR:
+ ret = s->pci[1].mem_base[1];
+ break;
+ case MV64340_PCI_1_MEMORY1_SIZE:
+ ret = s->pci[1].mem_size[1];
+ break;
+ case MV64340_PCI_1_MEMORY1_LOW_ADDR_REMAP:
+ ret = (s->pci[1].remap[1] & 0xffff0000) >> 16;
+ break;
+ case MV64340_PCI_1_MEMORY1_HIGH_ADDR_REMAP:
+ ret = s->pci[1].remap[1] >> 32;
+ break;
+ case MV64340_PCI_1_MEMORY2_BASE_ADDR:
+ ret = s->pci[1].mem_base[2];
+ break;
+ case MV64340_PCI_1_MEMORY2_SIZE:
+ ret = s->pci[1].mem_size[2];
+ break;
+ case MV64340_PCI_1_MEMORY2_LOW_ADDR_REMAP:
+ ret = (s->pci[1].remap[2] & 0xffff0000) >> 16;
+ break;
+ case MV64340_PCI_1_MEMORY2_HIGH_ADDR_REMAP:
+ ret = s->pci[1].remap[2] >> 32;
+ break;
+ case MV64340_PCI_1_MEMORY3_BASE_ADDR:
+ ret = s->pci[1].mem_base[3];
+ break;
+ case MV64340_PCI_1_MEMORY3_SIZE:
+ ret = s->pci[1].mem_size[3];
+ break;
+ case MV64340_PCI_1_MEMORY3_LOW_ADDR_REMAP:
+ ret = (s->pci[1].remap[3] & 0xffff0000) >> 16;
+ break;
+ case MV64340_PCI_1_MEMORY3_HIGH_ADDR_REMAP:
+ ret = s->pci[1].remap[3] >> 32;
+ break;
+ case MV64340_INTERNAL_SPACE_BASE_ADDR:
+ ret = s->regs_base;
+ break;
+ case MV64340_BASE_ADDR_ENABLE:
+ ret = s->base_addr_enable;
+ break;
+ case MV64340_PCI_0_CONFIG_ADDR:
+ ret = pci_host_conf_le_ops.read(PCI_HOST_BRIDGE(&s->pci[0]), 0, size);
+ break;
+ case MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG ...
+ MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG + 3:
+ ret = pci_host_data_le_ops.read(PCI_HOST_BRIDGE(&s->pci[0]),
+ addr - MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG, size);
+ break;
+ case MV64340_PCI_1_CONFIG_ADDR:
+ ret = pci_host_conf_le_ops.read(PCI_HOST_BRIDGE(&s->pci[1]), 0, size);
+ break;
+ case MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG ...
+ MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG + 3:
+ ret = pci_host_data_le_ops.read(PCI_HOST_BRIDGE(&s->pci[1]),
+ addr - MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG, size);
+ break;
+ case MV64340_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG:
+ /* FIXME: Should this be sent via the PCI bus somehow? */
+ if (s->gpp_int_level && (s->gpp_value & BIT(31))) {
+ ret = pic_read_irq(isa_pic);
+ }
+ break;
+ case MV64340_MAIN_INTERRUPT_CAUSE_LOW:
+ ret = s->main_int_cr;
+ break;
+ case MV64340_MAIN_INTERRUPT_CAUSE_HIGH:
+ ret = s->main_int_cr >> 32;
+ break;
+ case MV64340_CPU_INTERRUPT0_MASK_LOW:
+ ret = s->cpu0_int_mask;
+ break;
+ case MV64340_CPU_INTERRUPT0_MASK_HIGH:
+ ret = s->cpu0_int_mask >> 32;
+ break;
+ case MV64340_CPU_INTERRUPT0_SELECT_CAUSE:
+ ret = s->main_int_cr;
+ if (s->main_int_cr & s->cpu0_int_mask) {
+ if (!(s->main_int_cr & s->cpu0_int_mask & 0xffffffff)) {
+ ret = s->main_int_cr >> 32 | BIT(30);
+ } else if ((s->main_int_cr & s->cpu0_int_mask) >> 32) {
+ ret |= BIT(31);
+ }
+ }
+ break;
+ case MV64340_CUNIT_ARBITER_CONTROL_REG:
+ ret = 0x11ff0000 | (s->gpp_int_level << 10);
+ break;
+ case MV64340_GPP_IO_CONTROL:
+ ret = s->gpp_io;
+ break;
+ case MV64340_GPP_LEVEL_CONTROL:
+ ret = s->gpp_level;
+ break;
+ case MV64340_GPP_VALUE:
+ ret = s->gpp_value;
+ break;
+ case MV64340_GPP_VALUE_SET:
+ case MV64340_GPP_VALUE_CLEAR:
+ ret = 0;
+ break;
+ case MV64340_GPP_INTERRUPT_CAUSE:
+ ret = s->gpp_int_cr;
+ break;
+ case MV64340_GPP_INTERRUPT_MASK0:
+ case MV64340_GPP_INTERRUPT_MASK1:
+ ret = s->gpp_int_mask;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register read 0x%"
+ HWADDR_PRIx "\n", __func__, addr);
+ break;
+ }
+ if (addr != MV64340_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG) {
+ trace_mv64361_reg_read(addr, ret);
+ }
+ return ret;
+}
+
+static void warn_swap_bit(uint64_t val)
+{
+ if ((val & 0x3000000ULL) >> 24 != 1) {
+ qemu_log_mask(LOG_UNIMP, "%s: Data swap not implemented", __func__);
+ }
+}
+
+static void mv64361_set_pci_mem_remap(MV64361State *s, int bus, int idx,
+ uint64_t val, bool high)
+{
+ if (high) {
+ s->pci[bus].remap[idx] = val;
+ } else {
+ s->pci[bus].remap[idx] &= 0xffffffff00000000ULL;
+ s->pci[bus].remap[idx] |= (val & 0xffffULL) << 16;
+ }
+}
+
+static void mv64361_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned int size)
+{
+ MV64361State *s = MV64361(opaque);
+
+ trace_mv64361_reg_write(addr, val);
+ switch (addr) {
+ case MV64340_CPU_CONFIG:
+ s->cpu_conf = val & 0xe4e3bffULL;
+ s->cpu_conf |= BIT(23);
+ break;
+ case MV64340_PCI_0_IO_BASE_ADDR:
+ s->pci[0].io_base = val & 0x30fffffULL;
+ warn_swap_bit(val);
+ if (!(s->cpu_conf & BIT(27))) {
+ s->pci[0].remap[4] = (val & 0xffffULL) << 16;
+ }
+ break;
+ case MV64340_PCI_0_IO_SIZE:
+ s->pci[0].io_size = val & 0xffffULL;
+ break;
+ case MV64340_PCI_0_IO_ADDR_REMAP:
+ s->pci[0].remap[4] = (val & 0xffffULL) << 16;
+ break;
+ case MV64340_PCI_0_MEMORY0_BASE_ADDR:
+ s->pci[0].mem_base[0] = val & 0x70fffffULL;
+ warn_swap_bit(val);
+ if (!(s->cpu_conf & BIT(27))) {
+ mv64361_set_pci_mem_remap(s, 0, 0, val, false);
+ }
+ break;
+ case MV64340_PCI_0_MEMORY0_SIZE:
+ s->pci[0].mem_size[0] = val & 0xffffULL;
+ break;
+ case MV64340_PCI_0_MEMORY0_LOW_ADDR_REMAP:
+ case MV64340_PCI_0_MEMORY0_HIGH_ADDR_REMAP:
+ mv64361_set_pci_mem_remap(s, 0, 0, val,
+ (addr == MV64340_PCI_0_MEMORY0_HIGH_ADDR_REMAP));
+ break;
+ case MV64340_PCI_0_MEMORY1_BASE_ADDR:
+ s->pci[0].mem_base[1] = val & 0x70fffffULL;
+ warn_swap_bit(val);
+ if (!(s->cpu_conf & BIT(27))) {
+ mv64361_set_pci_mem_remap(s, 0, 1, val, false);
+ }
+ break;
+ case MV64340_PCI_0_MEMORY1_SIZE:
+ s->pci[0].mem_size[1] = val & 0xffffULL;
+ break;
+ case MV64340_PCI_0_MEMORY1_LOW_ADDR_REMAP:
+ case MV64340_PCI_0_MEMORY1_HIGH_ADDR_REMAP:
+ mv64361_set_pci_mem_remap(s, 0, 1, val,
+ (addr == MV64340_PCI_0_MEMORY1_HIGH_ADDR_REMAP));
+ break;
+ case MV64340_PCI_0_MEMORY2_BASE_ADDR:
+ s->pci[0].mem_base[2] = val & 0x70fffffULL;
+ warn_swap_bit(val);
+ if (!(s->cpu_conf & BIT(27))) {
+ mv64361_set_pci_mem_remap(s, 0, 2, val, false);
+ }
+ break;
+ case MV64340_PCI_0_MEMORY2_SIZE:
+ s->pci[0].mem_size[2] = val & 0xffffULL;
+ break;
+ case MV64340_PCI_0_MEMORY2_LOW_ADDR_REMAP:
+ case MV64340_PCI_0_MEMORY2_HIGH_ADDR_REMAP:
+ mv64361_set_pci_mem_remap(s, 0, 2, val,
+ (addr == MV64340_PCI_0_MEMORY2_HIGH_ADDR_REMAP));
+ break;
+ case MV64340_PCI_0_MEMORY3_BASE_ADDR:
+ s->pci[0].mem_base[3] = val & 0x70fffffULL;
+ warn_swap_bit(val);
+ if (!(s->cpu_conf & BIT(27))) {
+ mv64361_set_pci_mem_remap(s, 0, 3, val, false);
+ }
+ break;
+ case MV64340_PCI_0_MEMORY3_SIZE:
+ s->pci[0].mem_size[3] = val & 0xffffULL;
+ break;
+ case MV64340_PCI_0_MEMORY3_LOW_ADDR_REMAP:
+ case MV64340_PCI_0_MEMORY3_HIGH_ADDR_REMAP:
+ mv64361_set_pci_mem_remap(s, 0, 3, val,
+ (addr == MV64340_PCI_0_MEMORY3_HIGH_ADDR_REMAP));
+ break;
+ case MV64340_PCI_1_IO_BASE_ADDR:
+ s->pci[1].io_base = val & 0x30fffffULL;
+ warn_swap_bit(val);
+ break;
+ if (!(s->cpu_conf & BIT(27))) {
+ s->pci[1].remap[4] = (val & 0xffffULL) << 16;
+ }
+ break;
+ case MV64340_PCI_1_IO_SIZE:
+ s->pci[1].io_size = val & 0xffffULL;
+ break;
+ case MV64340_PCI_1_MEMORY0_BASE_ADDR:
+ s->pci[1].mem_base[0] = val & 0x70fffffULL;
+ warn_swap_bit(val);
+ if (!(s->cpu_conf & BIT(27))) {
+ mv64361_set_pci_mem_remap(s, 1, 0, val, false);
+ }
+ break;
+ case MV64340_PCI_1_MEMORY0_SIZE:
+ s->pci[1].mem_size[0] = val & 0xffffULL;
+ break;
+ case MV64340_PCI_1_MEMORY0_LOW_ADDR_REMAP:
+ case MV64340_PCI_1_MEMORY0_HIGH_ADDR_REMAP:
+ mv64361_set_pci_mem_remap(s, 1, 0, val,
+ (addr == MV64340_PCI_1_MEMORY0_HIGH_ADDR_REMAP));
+ break;
+ case MV64340_PCI_1_MEMORY1_BASE_ADDR:
+ s->pci[1].mem_base[1] = val & 0x70fffffULL;
+ warn_swap_bit(val);
+ if (!(s->cpu_conf & BIT(27))) {
+ mv64361_set_pci_mem_remap(s, 1, 1, val, false);
+ }
+ break;
+ case MV64340_PCI_1_MEMORY1_SIZE:
+ s->pci[1].mem_size[1] = val & 0xffffULL;
+ break;
+ case MV64340_PCI_1_MEMORY1_LOW_ADDR_REMAP:
+ case MV64340_PCI_1_MEMORY1_HIGH_ADDR_REMAP:
+ mv64361_set_pci_mem_remap(s, 1, 1, val,
+ (addr == MV64340_PCI_1_MEMORY1_HIGH_ADDR_REMAP));
+ break;
+ case MV64340_PCI_1_MEMORY2_BASE_ADDR:
+ s->pci[1].mem_base[2] = val & 0x70fffffULL;
+ warn_swap_bit(val);
+ if (!(s->cpu_conf & BIT(27))) {
+ mv64361_set_pci_mem_remap(s, 1, 2, val, false);
+ }
+ break;
+ case MV64340_PCI_1_MEMORY2_SIZE:
+ s->pci[1].mem_size[2] = val & 0xffffULL;
+ break;
+ case MV64340_PCI_1_MEMORY2_LOW_ADDR_REMAP:
+ case MV64340_PCI_1_MEMORY2_HIGH_ADDR_REMAP:
+ mv64361_set_pci_mem_remap(s, 1, 2, val,
+ (addr == MV64340_PCI_1_MEMORY2_HIGH_ADDR_REMAP));
+ break;
+ case MV64340_PCI_1_MEMORY3_BASE_ADDR:
+ s->pci[1].mem_base[3] = val & 0x70fffffULL;
+ warn_swap_bit(val);
+ if (!(s->cpu_conf & BIT(27))) {
+ mv64361_set_pci_mem_remap(s, 1, 3, val, false);
+ }
+ break;
+ case MV64340_PCI_1_MEMORY3_SIZE:
+ s->pci[1].mem_size[3] = val & 0xffffULL;
+ break;
+ case MV64340_PCI_1_MEMORY3_LOW_ADDR_REMAP:
+ case MV64340_PCI_1_MEMORY3_HIGH_ADDR_REMAP:
+ mv64361_set_pci_mem_remap(s, 1, 3, val,
+ (addr == MV64340_PCI_1_MEMORY3_HIGH_ADDR_REMAP));
+ break;
+ case MV64340_INTERNAL_SPACE_BASE_ADDR:
+ s->regs_base = val & 0xfffffULL;
+ break;
+ case MV64340_BASE_ADDR_ENABLE:
+ setup_mem_windows(s, val);
+ s->base_addr_enable = val & 0x1fffffULL;
+ break;
+ case MV64340_PCI_0_CONFIG_ADDR:
+ pci_host_conf_le_ops.write(PCI_HOST_BRIDGE(&s->pci[0]), 0, val, size);
+ break;
+ case MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG ...
+ MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG + 3:
+ pci_host_data_le_ops.write(PCI_HOST_BRIDGE(&s->pci[0]),
+ addr - MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG, val, size);
+ break;
+ case MV64340_PCI_1_CONFIG_ADDR:
+ pci_host_conf_le_ops.write(PCI_HOST_BRIDGE(&s->pci[1]), 0, val, size);
+ break;
+ case MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG ...
+ MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG + 3:
+ pci_host_data_le_ops.write(PCI_HOST_BRIDGE(&s->pci[1]),
+ addr - MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG, val, size);
+ break;
+ case MV64340_CPU_INTERRUPT0_MASK_LOW:
+ s->cpu0_int_mask &= 0xffffffff00000000ULL;
+ s->cpu0_int_mask |= val & 0xffffffffULL;
+ break;
+ case MV64340_CPU_INTERRUPT0_MASK_HIGH:
+ s->cpu0_int_mask &= 0xffffffffULL;
+ s->cpu0_int_mask |= val << 32;
+ break;
+ case MV64340_CUNIT_ARBITER_CONTROL_REG:
+ s->gpp_int_level = !!(val & BIT(10));
+ break;
+ case MV64340_GPP_IO_CONTROL:
+ s->gpp_io = val;
+ break;
+ case MV64340_GPP_LEVEL_CONTROL:
+ s->gpp_level = val;
+ break;
+ case MV64340_GPP_VALUE:
+ s->gpp_value &= ~s->gpp_io;
+ s->gpp_value |= val & s->gpp_io;
+ break;
+ case MV64340_GPP_VALUE_SET:
+ s->gpp_value |= val & s->gpp_io;
+ break;
+ case MV64340_GPP_VALUE_CLEAR:
+ s->gpp_value &= ~(val & s->gpp_io);
+ break;
+ case MV64340_GPP_INTERRUPT_CAUSE:
+ if (!s->gpp_int_level && val != s->gpp_int_cr) {
+ int i;
+ uint32_t ch = s->gpp_int_cr ^ val;
+ s->gpp_int_cr = val;
+ for (i = 0; i < 4; i++) {
+ if ((ch & 0xff << i) && !(val & 0xff << i)) {
+ mv64361_update_irq(opaque, MV64361_IRQ_P0_GPP0_7 + i, 0);
+ }
+ }
+ } else {
+ s->gpp_int_cr = val;
+ }
+ break;
+ case MV64340_GPP_INTERRUPT_MASK0:
+ case MV64340_GPP_INTERRUPT_MASK1:
+ s->gpp_int_mask = val;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register write 0x%"
+ HWADDR_PRIx " = %"PRIx64"\n", __func__, addr, val);
+ break;
+ }
+}
+
+static const MemoryRegionOps mv64361_ops = {
+ .read = mv64361_read,
+ .write = mv64361_write,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 4,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void mv64361_gpp_irq(void *opaque, int n, int level)
+{
+ MV64361State *s = opaque;
+ uint32_t mask = BIT(n);
+ uint32_t val = s->gpp_value & ~mask;
+
+ if (s->gpp_level & mask) {
+ level = !level;
+ }
+ val |= level << n;
+ if (val > s->gpp_value) {
+ s->gpp_value = val;
+ s->gpp_int_cr |= mask;
+ if (s->gpp_int_mask & mask) {
+ mv64361_update_irq(opaque, MV64361_IRQ_P0_GPP0_7 + n / 8, 1);
+ }
+ } else if (val < s->gpp_value) {
+ int b = n / 8;
+ s->gpp_value = val;
+ if (s->gpp_int_level && !(val & 0xff << b)) {
+ mv64361_update_irq(opaque, MV64361_IRQ_P0_GPP0_7 + b, 0);
+ }
+ }
+}
+
+static void mv64361_realize(DeviceState *dev, Error **errp)
+{
+ MV64361State *s = MV64361(dev);
+ int i;
+
+ s->base_addr_enable = 0x1fffff;
+ memory_region_init_io(&s->regs, OBJECT(s), &mv64361_ops, s,
+ TYPE_MV64361, 0x10000);
+ for (i = 0; i < 2; i++) {
+ char *name = g_strdup_printf("pcihost%d", i);
+ object_initialize_child(OBJECT(dev), name, &s->pci[i],
+ TYPE_MV64361_PCI);
+ g_free(name);
+ DeviceState *pci = DEVICE(&s->pci[i]);
+ qdev_prop_set_uint8(pci, "index", i);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(pci), &error_fatal);
+ }
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cpu_irq);
+ qdev_init_gpio_in_named(dev, mv64361_gpp_irq, "gpp", 32);
+ /* FIXME: PCI IRQ connections may be board specific */
+ for (i = 0; i < PCI_NUM_PINS; i++) {
+ s->pci[1].irq[i] = qdev_get_gpio_in_named(dev, "gpp", 12 + i);
+ }
+}
+
+static void mv64361_reset(DeviceState *dev)
+{
+ MV64361State *s = MV64361(dev);
+ int i, j;
+
+ /*
+ * These values may be board specific
+ * Real chip supports init from an eprom but that's not modelled
+ */
+ setup_mem_windows(s, 0x1fffff);
+ s->base_addr_enable = 0x1fffff;
+ s->cpu_conf = 0x28000ff;
+ s->regs_base = 0x100f100;
+ s->pci[0].io_base = 0x100f800;
+ s->pci[0].io_size = 0xff;
+ s->pci[0].mem_base[0] = 0x100c000;
+ s->pci[0].mem_size[0] = 0x1fff;
+ s->pci[0].mem_base[1] = 0x100f900;
+ s->pci[0].mem_size[1] = 0xff;
+ s->pci[0].mem_base[2] = 0x100f400;
+ s->pci[0].mem_size[2] = 0x1ff;
+ s->pci[0].mem_base[3] = 0x100f600;
+ s->pci[0].mem_size[3] = 0x1ff;
+ s->pci[1].io_base = 0x100fe00;
+ s->pci[1].io_size = 0xff;
+ s->pci[1].mem_base[0] = 0x1008000;
+ s->pci[1].mem_size[0] = 0x3fff;
+ s->pci[1].mem_base[1] = 0x100fd00;
+ s->pci[1].mem_size[1] = 0xff;
+ s->pci[1].mem_base[2] = 0x1002600;
+ s->pci[1].mem_size[2] = 0x1ff;
+ s->pci[1].mem_base[3] = 0x100ff80;
+ s->pci[1].mem_size[3] = 0x7f;
+ for (i = 0; i < 2; i++) {
+ for (j = 0; j < 4; j++) {
+ s->pci[i].remap[j] = s->pci[i].mem_base[j] << 16;
+ }
+ }
+ s->pci[0].remap[1] = 0;
+ s->pci[1].remap[1] = 0;
+ setup_mem_windows(s, 0xfbfff);
+ s->base_addr_enable = 0xfbfff;
+}
+
+static void mv64361_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = mv64361_realize;
+ dc->reset = mv64361_reset;
+}
+
+static const TypeInfo mv64361_type_info = {
+ .name = TYPE_MV64361,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MV64361State),
+ .class_init = mv64361_class_init,
+};
+
+static void mv64361_register_types(void)
+{
+ type_register_static(&mv64361_type_info);
+}
+
+type_init(mv64361_register_types)
diff --git a/hw/pci-host/mv643xx.h b/hw/pci-host/mv643xx.h
new file mode 100644
index 0000000000..cd26a43f18
--- /dev/null
+++ b/hw/pci-host/mv643xx.h
@@ -0,0 +1,918 @@
+/*
+ * mv643xx.h - MV-643XX Internal registers definition file.
+ *
+ * Copyright 2002 Momentum Computer, Inc.
+ * Author: Matthew Dharm <mdharm@momenco.com>
+ * Copyright 2002 GALILEO TECHNOLOGY, LTD.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef ASM_MV643XX_H
+#define ASM_MV643XX_H
+
+/****************************************/
+/* Processor Address Space */
+/****************************************/
+
+/* DDR SDRAM BAR and size registers */
+
+#define MV64340_CS_0_BASE_ADDR 0x008
+#define MV64340_CS_0_SIZE 0x010
+#define MV64340_CS_1_BASE_ADDR 0x208
+#define MV64340_CS_1_SIZE 0x210
+#define MV64340_CS_2_BASE_ADDR 0x018
+#define MV64340_CS_2_SIZE 0x020
+#define MV64340_CS_3_BASE_ADDR 0x218
+#define MV64340_CS_3_SIZE 0x220
+
+/* Devices BAR and size registers */
+
+#define MV64340_DEV_CS0_BASE_ADDR 0x028
+#define MV64340_DEV_CS0_SIZE 0x030
+#define MV64340_DEV_CS1_BASE_ADDR 0x228
+#define MV64340_DEV_CS1_SIZE 0x230
+#define MV64340_DEV_CS2_BASE_ADDR 0x248
+#define MV64340_DEV_CS2_SIZE 0x250
+#define MV64340_DEV_CS3_BASE_ADDR 0x038
+#define MV64340_DEV_CS3_SIZE 0x040
+#define MV64340_BOOTCS_BASE_ADDR 0x238
+#define MV64340_BOOTCS_SIZE 0x240
+
+/* PCI 0 BAR and size registers */
+
+#define MV64340_PCI_0_IO_BASE_ADDR 0x048
+#define MV64340_PCI_0_IO_SIZE 0x050
+#define MV64340_PCI_0_MEMORY0_BASE_ADDR 0x058
+#define MV64340_PCI_0_MEMORY0_SIZE 0x060
+#define MV64340_PCI_0_MEMORY1_BASE_ADDR 0x080
+#define MV64340_PCI_0_MEMORY1_SIZE 0x088
+#define MV64340_PCI_0_MEMORY2_BASE_ADDR 0x258
+#define MV64340_PCI_0_MEMORY2_SIZE 0x260
+#define MV64340_PCI_0_MEMORY3_BASE_ADDR 0x280
+#define MV64340_PCI_0_MEMORY3_SIZE 0x288
+
+/* PCI 1 BAR and size registers */
+#define MV64340_PCI_1_IO_BASE_ADDR 0x090
+#define MV64340_PCI_1_IO_SIZE 0x098
+#define MV64340_PCI_1_MEMORY0_BASE_ADDR 0x0a0
+#define MV64340_PCI_1_MEMORY0_SIZE 0x0a8
+#define MV64340_PCI_1_MEMORY1_BASE_ADDR 0x0b0
+#define MV64340_PCI_1_MEMORY1_SIZE 0x0b8
+#define MV64340_PCI_1_MEMORY2_BASE_ADDR 0x2a0
+#define MV64340_PCI_1_MEMORY2_SIZE 0x2a8
+#define MV64340_PCI_1_MEMORY3_BASE_ADDR 0x2b0
+#define MV64340_PCI_1_MEMORY3_SIZE 0x2b8
+
+/* SRAM base address */
+#define MV64340_INTEGRATED_SRAM_BASE_ADDR 0x268
+
+/* internal registers space base address */
+#define MV64340_INTERNAL_SPACE_BASE_ADDR 0x068
+
+/* Enables the CS , DEV_CS , PCI 0 and PCI 1 windows above */
+#define MV64340_BASE_ADDR_ENABLE 0x278
+
+/****************************************/
+/* PCI remap registers */
+/****************************************/
+
+ /* PCI 0 */
+#define MV64340_PCI_0_IO_ADDR_REMAP 0x0f0
+#define MV64340_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8
+#define MV64340_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320
+#define MV64340_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100
+#define MV64340_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328
+#define MV64340_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8
+#define MV64340_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330
+#define MV64340_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300
+#define MV64340_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338
+ /* PCI 1 */
+#define MV64340_PCI_1_IO_ADDR_REMAP 0x108
+#define MV64340_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110
+#define MV64340_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340
+#define MV64340_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118
+#define MV64340_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348
+#define MV64340_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310
+#define MV64340_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350
+#define MV64340_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318
+#define MV64340_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358
+
+#define MV64340_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0
+#define MV64340_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8
+#define MV64340_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0
+#define MV64340_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8
+#define MV64340_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0
+#define MV64340_CPU_GE_HEADERS_RETARGET_BASE 0x3d8
+#define MV64340_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0
+#define MV64340_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8
+
+/****************************************/
+/* CPU Control Registers */
+/****************************************/
+
+#define MV64340_CPU_CONFIG 0x000
+#define MV64340_CPU_MODE 0x120
+#define MV64340_CPU_MASTER_CONTROL 0x160
+#define MV64340_CPU_CROSS_BAR_CONTROL_LOW 0x150
+#define MV64340_CPU_CROSS_BAR_CONTROL_HIGH 0x158
+#define MV64340_CPU_CROSS_BAR_TIMEOUT 0x168
+
+/****************************************/
+/* SMP RegisterS */
+/****************************************/
+
+#define MV64340_SMP_WHO_AM_I 0x200
+#define MV64340_SMP_CPU0_DOORBELL 0x214
+#define MV64340_SMP_CPU0_DOORBELL_CLEAR 0x21C
+#define MV64340_SMP_CPU1_DOORBELL 0x224
+#define MV64340_SMP_CPU1_DOORBELL_CLEAR 0x22C
+#define MV64340_SMP_CPU0_DOORBELL_MASK 0x234
+#define MV64340_SMP_CPU1_DOORBELL_MASK 0x23C
+#define MV64340_SMP_SEMAPHOR0 0x244
+#define MV64340_SMP_SEMAPHOR1 0x24c
+#define MV64340_SMP_SEMAPHOR2 0x254
+#define MV64340_SMP_SEMAPHOR3 0x25c
+#define MV64340_SMP_SEMAPHOR4 0x264
+#define MV64340_SMP_SEMAPHOR5 0x26c
+#define MV64340_SMP_SEMAPHOR6 0x274
+#define MV64340_SMP_SEMAPHOR7 0x27c
+
+/****************************************/
+/* CPU Sync Barrier Register */
+/****************************************/
+
+#define MV64340_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0
+#define MV64340_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8
+#define MV64340_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0
+#define MV64340_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8
+
+/****************************************/
+/* CPU Access Protect */
+/****************************************/
+
+#define MV64340_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180
+#define MV64340_CPU_PROTECT_WINDOW_0_SIZE 0x188
+#define MV64340_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190
+#define MV64340_CPU_PROTECT_WINDOW_1_SIZE 0x198
+#define MV64340_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0
+#define MV64340_CPU_PROTECT_WINDOW_2_SIZE 0x1a8
+#define MV64340_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0
+#define MV64340_CPU_PROTECT_WINDOW_3_SIZE 0x1b8
+
+
+/****************************************/
+/* CPU Error Report */
+/****************************************/
+
+#define MV64340_CPU_ERROR_ADDR_LOW 0x070
+#define MV64340_CPU_ERROR_ADDR_HIGH 0x078
+#define MV64340_CPU_ERROR_DATA_LOW 0x128
+#define MV64340_CPU_ERROR_DATA_HIGH 0x130
+#define MV64340_CPU_ERROR_PARITY 0x138
+#define MV64340_CPU_ERROR_CAUSE 0x140
+#define MV64340_CPU_ERROR_MASK 0x148
+
+/****************************************/
+/* CPU Interface Debug Registers */
+/****************************************/
+
+#define MV64340_PUNIT_SLAVE_DEBUG_LOW 0x360
+#define MV64340_PUNIT_SLAVE_DEBUG_HIGH 0x368
+#define MV64340_PUNIT_MASTER_DEBUG_LOW 0x370
+#define MV64340_PUNIT_MASTER_DEBUG_HIGH 0x378
+#define MV64340_PUNIT_MMASK 0x3e4
+
+/****************************************/
+/* Integrated SRAM Registers */
+/****************************************/
+
+#define MV64340_SRAM_CONFIG 0x380
+#define MV64340_SRAM_TEST_MODE 0X3F4
+#define MV64340_SRAM_ERROR_CAUSE 0x388
+#define MV64340_SRAM_ERROR_ADDR 0x390
+#define MV64340_SRAM_ERROR_ADDR_HIGH 0X3F8
+#define MV64340_SRAM_ERROR_DATA_LOW 0x398
+#define MV64340_SRAM_ERROR_DATA_HIGH 0x3a0
+#define MV64340_SRAM_ERROR_DATA_PARITY 0x3a8
+
+/****************************************/
+/* SDRAM Configuration */
+/****************************************/
+
+#define MV64340_SDRAM_CONFIG 0x1400
+#define MV64340_D_UNIT_CONTROL_LOW 0x1404
+#define MV64340_D_UNIT_CONTROL_HIGH 0x1424
+#define MV64340_SDRAM_TIMING_CONTROL_LOW 0x1408
+#define MV64340_SDRAM_TIMING_CONTROL_HIGH 0x140c
+#define MV64340_SDRAM_ADDR_CONTROL 0x1410
+#define MV64340_SDRAM_OPEN_PAGES_CONTROL 0x1414
+#define MV64340_SDRAM_OPERATION 0x1418
+#define MV64340_SDRAM_MODE 0x141c
+#define MV64340_EXTENDED_DRAM_MODE 0x1420
+#define MV64340_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430
+#define MV64340_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434
+#define MV64340_SDRAM_CROSS_BAR_TIMEOUT 0x1438
+#define MV64340_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0
+#define MV64340_SDRAM_DATA_PADS_CALIBRATION 0x14c4
+
+/****************************************/
+/* SDRAM Error Report */
+/****************************************/
+
+#define MV64340_SDRAM_ERROR_DATA_LOW 0x1444
+#define MV64340_SDRAM_ERROR_DATA_HIGH 0x1440
+#define MV64340_SDRAM_ERROR_ADDR 0x1450
+#define MV64340_SDRAM_RECEIVED_ECC 0x1448
+#define MV64340_SDRAM_CALCULATED_ECC 0x144c
+#define MV64340_SDRAM_ECC_CONTROL 0x1454
+#define MV64340_SDRAM_ECC_ERROR_COUNTER 0x1458
+
+/******************************************/
+/* Controlled Delay Line (CDL) Registers */
+/******************************************/
+
+#define MV64340_DFCDL_CONFIG0 0x1480
+#define MV64340_DFCDL_CONFIG1 0x1484
+#define MV64340_DLL_WRITE 0x1488
+#define MV64340_DLL_READ 0x148c
+#define MV64340_SRAM_ADDR 0x1490
+#define MV64340_SRAM_DATA0 0x1494
+#define MV64340_SRAM_DATA1 0x1498
+#define MV64340_SRAM_DATA2 0x149c
+#define MV64340_DFCL_PROBE 0x14a0
+
+/******************************************/
+/* Debug Registers */
+/******************************************/
+
+#define MV64340_DUNIT_DEBUG_LOW 0x1460
+#define MV64340_DUNIT_DEBUG_HIGH 0x1464
+#define MV64340_DUNIT_MMASK 0X1b40
+
+/****************************************/
+/* Device Parameters */
+/****************************************/
+
+#define MV64340_DEVICE_BANK0_PARAMETERS 0x45c
+#define MV64340_DEVICE_BANK1_PARAMETERS 0x460
+#define MV64340_DEVICE_BANK2_PARAMETERS 0x464
+#define MV64340_DEVICE_BANK3_PARAMETERS 0x468
+#define MV64340_DEVICE_BOOT_BANK_PARAMETERS 0x46c
+#define MV64340_DEVICE_INTERFACE_CONTROL 0x4c0
+#define MV64340_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8
+#define MV64340_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc
+#define MV64340_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4
+
+/****************************************/
+/* Device interrupt registers */
+/****************************************/
+
+#define MV64340_DEVICE_INTERRUPT_CAUSE 0x4d0
+#define MV64340_DEVICE_INTERRUPT_MASK 0x4d4
+#define MV64340_DEVICE_ERROR_ADDR 0x4d8
+#define MV64340_DEVICE_ERROR_DATA 0x4dc
+#define MV64340_DEVICE_ERROR_PARITY 0x4e0
+
+/****************************************/
+/* Device debug registers */
+/****************************************/
+
+#define MV64340_DEVICE_DEBUG_LOW 0x4e4
+#define MV64340_DEVICE_DEBUG_HIGH 0x4e8
+#define MV64340_RUNIT_MMASK 0x4f0
+
+/****************************************/
+/* PCI Slave Address Decoding registers */
+/****************************************/
+
+#define MV64340_PCI_0_CS_0_BANK_SIZE 0xc08
+#define MV64340_PCI_1_CS_0_BANK_SIZE 0xc88
+#define MV64340_PCI_0_CS_1_BANK_SIZE 0xd08
+#define MV64340_PCI_1_CS_1_BANK_SIZE 0xd88
+#define MV64340_PCI_0_CS_2_BANK_SIZE 0xc0c
+#define MV64340_PCI_1_CS_2_BANK_SIZE 0xc8c
+#define MV64340_PCI_0_CS_3_BANK_SIZE 0xd0c
+#define MV64340_PCI_1_CS_3_BANK_SIZE 0xd8c
+#define MV64340_PCI_0_DEVCS_0_BANK_SIZE 0xc10
+#define MV64340_PCI_1_DEVCS_0_BANK_SIZE 0xc90
+#define MV64340_PCI_0_DEVCS_1_BANK_SIZE 0xd10
+#define MV64340_PCI_1_DEVCS_1_BANK_SIZE 0xd90
+#define MV64340_PCI_0_DEVCS_2_BANK_SIZE 0xd18
+#define MV64340_PCI_1_DEVCS_2_BANK_SIZE 0xd98
+#define MV64340_PCI_0_DEVCS_3_BANK_SIZE 0xc14
+#define MV64340_PCI_1_DEVCS_3_BANK_SIZE 0xc94
+#define MV64340_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14
+#define MV64340_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94
+#define MV64340_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c
+#define MV64340_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c
+#define MV64340_PCI_0_P2P_MEM1_BAR_SIZE 0xd20
+#define MV64340_PCI_1_P2P_MEM1_BAR_SIZE 0xda0
+#define MV64340_PCI_0_P2P_I_O_BAR_SIZE 0xd24
+#define MV64340_PCI_1_P2P_I_O_BAR_SIZE 0xda4
+#define MV64340_PCI_0_CPU_BAR_SIZE 0xd28
+#define MV64340_PCI_1_CPU_BAR_SIZE 0xda8
+#define MV64340_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00
+#define MV64340_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80
+#define MV64340_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c
+#define MV64340_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c
+#define MV64340_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c
+#define MV64340_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc
+#define MV64340_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48
+#define MV64340_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8
+#define MV64340_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48
+#define MV64340_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8
+#define MV64340_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c
+#define MV64340_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc
+#define MV64340_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c
+#define MV64340_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc
+#define MV64340_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04
+#define MV64340_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84
+#define MV64340_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08
+#define MV64340_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88
+#define MV64340_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C
+#define MV64340_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C
+#define MV64340_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10
+#define MV64340_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90
+#define MV64340_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50
+#define MV64340_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0
+#define MV64340_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50
+#define MV64340_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0
+#define MV64340_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58
+#define MV64340_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8
+#define MV64340_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54
+#define MV64340_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4
+#define MV64340_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54
+#define MV64340_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4
+#define MV64340_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c
+#define MV64340_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc
+#define MV64340_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60
+#define MV64340_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0
+#define MV64340_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64
+#define MV64340_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4
+#define MV64340_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68
+#define MV64340_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8
+#define MV64340_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c
+#define MV64340_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec
+#define MV64340_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70
+#define MV64340_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0
+#define MV64340_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74
+#define MV64340_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4
+#define MV64340_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00
+#define MV64340_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80
+#define MV64340_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38
+#define MV64340_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8
+#define MV64340_PCI_0_ADDR_DECODE_CONTROL 0xd3c
+#define MV64340_PCI_1_ADDR_DECODE_CONTROL 0xdbc
+#define MV64340_PCI_0_HEADERS_RETARGET_CONTROL 0xF40
+#define MV64340_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0
+#define MV64340_PCI_0_HEADERS_RETARGET_BASE 0xF44
+#define MV64340_PCI_1_HEADERS_RETARGET_BASE 0xFc4
+#define MV64340_PCI_0_HEADERS_RETARGET_HIGH 0xF48
+#define MV64340_PCI_1_HEADERS_RETARGET_HIGH 0xFc8
+
+/***********************************/
+/* PCI Control Register Map */
+/***********************************/
+
+#define MV64340_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20
+#define MV64340_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0
+#define MV64340_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C
+#define MV64340_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C
+#define MV64340_PCI_0_COMMAND 0xc00
+#define MV64340_PCI_1_COMMAND 0xc80
+#define MV64340_PCI_0_MODE 0xd00
+#define MV64340_PCI_1_MODE 0xd80
+#define MV64340_PCI_0_RETRY 0xc04
+#define MV64340_PCI_1_RETRY 0xc84
+#define MV64340_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04
+#define MV64340_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84
+#define MV64340_PCI_0_MSI_TRIGGER_TIMER 0xc38
+#define MV64340_PCI_1_MSI_TRIGGER_TIMER 0xcb8
+#define MV64340_PCI_0_ARBITER_CONTROL 0x1d00
+#define MV64340_PCI_1_ARBITER_CONTROL 0x1d80
+#define MV64340_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08
+#define MV64340_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88
+#define MV64340_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c
+#define MV64340_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c
+#define MV64340_PCI_0_CROSS_BAR_TIMEOUT 0x1d04
+#define MV64340_PCI_1_CROSS_BAR_TIMEOUT 0x1d84
+#define MV64340_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18
+#define MV64340_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98
+#define MV64340_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10
+#define MV64340_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90
+#define MV64340_PCI_0_P2P_CONFIG 0x1d14
+#define MV64340_PCI_1_P2P_CONFIG 0x1d94
+
+#define MV64340_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00
+#define MV64340_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04
+#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08
+#define MV64340_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10
+#define MV64340_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14
+#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18
+#define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20
+#define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24
+#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28
+#define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30
+#define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34
+#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38
+#define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40
+#define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44
+#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48
+#define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50
+#define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54
+#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58
+
+#define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80
+#define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84
+#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88
+#define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90
+#define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94
+#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98
+#define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0
+#define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
+#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8
+#define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0
+#define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
+#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8
+#define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0
+#define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
+#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8
+#define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0
+#define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
+#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8
+
+/****************************************/
+/* PCI Configuration Access Registers */
+/****************************************/
+
+#define MV64340_PCI_0_CONFIG_ADDR 0xcf8
+#define MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc
+#define MV64340_PCI_1_CONFIG_ADDR 0xc78
+#define MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c
+#define MV64340_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34
+#define MV64340_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4
+
+/****************************************/
+/* PCI Error Report Registers */
+/****************************************/
+
+#define MV64340_PCI_0_SERR_MASK 0xc28
+#define MV64340_PCI_1_SERR_MASK 0xca8
+#define MV64340_PCI_0_ERROR_ADDR_LOW 0x1d40
+#define MV64340_PCI_1_ERROR_ADDR_LOW 0x1dc0
+#define MV64340_PCI_0_ERROR_ADDR_HIGH 0x1d44
+#define MV64340_PCI_1_ERROR_ADDR_HIGH 0x1dc4
+#define MV64340_PCI_0_ERROR_ATTRIBUTE 0x1d48
+#define MV64340_PCI_1_ERROR_ATTRIBUTE 0x1dc8
+#define MV64340_PCI_0_ERROR_COMMAND 0x1d50
+#define MV64340_PCI_1_ERROR_COMMAND 0x1dd0
+#define MV64340_PCI_0_ERROR_CAUSE 0x1d58
+#define MV64340_PCI_1_ERROR_CAUSE 0x1dd8
+#define MV64340_PCI_0_ERROR_MASK 0x1d5c
+#define MV64340_PCI_1_ERROR_MASK 0x1ddc
+
+/****************************************/
+/* PCI Debug Registers */
+/****************************************/
+
+#define MV64340_PCI_0_MMASK 0X1D24
+#define MV64340_PCI_1_MMASK 0X1DA4
+
+/*********************************************/
+/* PCI Configuration, Function 0, Registers */
+/*********************************************/
+
+#define MV64340_PCI_DEVICE_AND_VENDOR_ID 0x000
+#define MV64340_PCI_STATUS_AND_COMMAND 0x004
+#define MV64340_PCI_CLASS_CODE_AND_REVISION_ID 0x008
+#define MV64340_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
+
+#define MV64340_PCI_SCS_0_BASE_ADDR_LOW 0x010
+#define MV64340_PCI_SCS_0_BASE_ADDR_HIGH 0x014
+#define MV64340_PCI_SCS_1_BASE_ADDR_LOW 0x018
+#define MV64340_PCI_SCS_1_BASE_ADDR_HIGH 0x01C
+#define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020
+#define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024
+#define MV64340_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c
+#define MV64340_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030
+#define MV64340_PCI_CAPABILTY_LIST_POINTER 0x034
+#define MV64340_PCI_INTERRUPT_PIN_AND_LINE 0x03C
+ /* capability list */
+#define MV64340_PCI_POWER_MANAGEMENT_CAPABILITY 0x040
+#define MV64340_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
+#define MV64340_PCI_VPD_ADDR 0x048
+#define MV64340_PCI_VPD_DATA 0x04c
+#define MV64340_PCI_MSI_MESSAGE_CONTROL 0x050
+#define MV64340_PCI_MSI_MESSAGE_ADDR 0x054
+#define MV64340_PCI_MSI_MESSAGE_UPPER_ADDR 0x058
+#define MV64340_PCI_MSI_MESSAGE_DATA 0x05c
+#define MV64340_PCI_X_COMMAND 0x060
+#define MV64340_PCI_X_STATUS 0x064
+#define MV64340_PCI_COMPACT_PCI_HOT_SWAP 0x068
+
+/***********************************************/
+/* PCI Configuration, Function 1, Registers */
+/***********************************************/
+
+#define MV64340_PCI_SCS_2_BASE_ADDR_LOW 0x110
+#define MV64340_PCI_SCS_2_BASE_ADDR_HIGH 0x114
+#define MV64340_PCI_SCS_3_BASE_ADDR_LOW 0x118
+#define MV64340_PCI_SCS_3_BASE_ADDR_HIGH 0x11c
+#define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120
+#define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124
+
+/***********************************************/
+/* PCI Configuration, Function 2, Registers */
+/***********************************************/
+
+#define MV64340_PCI_DEVCS_0_BASE_ADDR_LOW 0x210
+#define MV64340_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214
+#define MV64340_PCI_DEVCS_1_BASE_ADDR_LOW 0x218
+#define MV64340_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c
+#define MV64340_PCI_DEVCS_2_BASE_ADDR_LOW 0x220
+#define MV64340_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224
+
+/***********************************************/
+/* PCI Configuration, Function 3, Registers */
+/***********************************************/
+
+#define MV64340_PCI_DEVCS_3_BASE_ADDR_LOW 0x310
+#define MV64340_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314
+#define MV64340_PCI_BOOT_CS_BASE_ADDR_LOW 0x318
+#define MV64340_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c
+#define MV64340_PCI_CPU_BASE_ADDR_LOW 0x220
+#define MV64340_PCI_CPU_BASE_ADDR_HIGH 0x224
+
+/***********************************************/
+/* PCI Configuration, Function 4, Registers */
+/***********************************************/
+
+#define MV64340_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410
+#define MV64340_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414
+#define MV64340_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418
+#define MV64340_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c
+#define MV64340_PCI_P2P_I_O_BASE_ADDR 0x420
+#define MV64340_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424
+
+/****************************************/
+/* Messaging Unit Registers (I20) */
+/****************************************/
+
+#define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010
+#define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014
+#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018
+#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C
+#define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020
+#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024
+#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028
+#define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C
+#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030
+#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034
+#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040
+#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044
+#define MV64340_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050
+#define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054
+#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060
+#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064
+#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068
+#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C
+#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070
+#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074
+#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8
+#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC
+
+#define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090
+#define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094
+#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098
+#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C
+#define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0
+#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4
+#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8
+#define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC
+#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0
+#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4
+#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0
+#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4
+#define MV64340_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0
+#define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4
+#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0
+#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4
+#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8
+#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC
+#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0
+#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4
+#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078
+#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C
+
+#define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10
+#define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14
+#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18
+#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C
+#define MV64340_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20
+#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24
+#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28
+#define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C
+#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30
+#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34
+#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40
+#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44
+#define MV64340_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50
+#define MV64340_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54
+#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60
+#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64
+#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68
+#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C
+#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70
+#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74
+#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8
+#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC
+#define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90
+#define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94
+#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98
+#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C
+#define MV64340_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0
+#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4
+#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8
+#define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC
+#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0
+#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4
+#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0
+#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4
+#define MV64340_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0
+#define MV64340_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4
+#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0
+#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4
+#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8
+#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC
+#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0
+#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4
+#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78
+#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C
+
+/****************************************/
+/* Ethernet Unit Registers */
+/****************************************/
+
+/*******************************************/
+/* CUNIT Registers */
+/*******************************************/
+
+ /* Address Decoding Register Map */
+
+#define MV64340_CUNIT_BASE_ADDR_REG0 0xf200
+#define MV64340_CUNIT_BASE_ADDR_REG1 0xf208
+#define MV64340_CUNIT_BASE_ADDR_REG2 0xf210
+#define MV64340_CUNIT_BASE_ADDR_REG3 0xf218
+#define MV64340_CUNIT_SIZE0 0xf204
+#define MV64340_CUNIT_SIZE1 0xf20c
+#define MV64340_CUNIT_SIZE2 0xf214
+#define MV64340_CUNIT_SIZE3 0xf21c
+#define MV64340_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240
+#define MV64340_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244
+#define MV64340_CUNIT_BASE_ADDR_ENABLE_REG 0xf250
+#define MV64340_MPSC0_ACCESS_PROTECTION_REG 0xf254
+#define MV64340_MPSC1_ACCESS_PROTECTION_REG 0xf258
+#define MV64340_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C
+
+ /* Error Report Registers */
+
+#define MV64340_CUNIT_INTERRUPT_CAUSE_REG 0xf310
+#define MV64340_CUNIT_INTERRUPT_MASK_REG 0xf314
+#define MV64340_CUNIT_ERROR_ADDR 0xf318
+
+ /* Cunit Control Registers */
+
+#define MV64340_CUNIT_ARBITER_CONTROL_REG 0xf300
+#define MV64340_CUNIT_CONFIG_REG 0xb40c
+#define MV64340_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304
+
+ /* Cunit Debug Registers */
+
+#define MV64340_CUNIT_DEBUG_LOW 0xf340
+#define MV64340_CUNIT_DEBUG_HIGH 0xf344
+#define MV64340_CUNIT_MMASK 0xf380
+
+ /* MPSCs Clocks Routing Registers */
+
+#define MV64340_MPSC_ROUTING_REG 0xb400
+#define MV64340_MPSC_RX_CLOCK_ROUTING_REG 0xb404
+#define MV64340_MPSC_TX_CLOCK_ROUTING_REG 0xb408
+
+ /* MPSCs Interrupts Registers */
+
+#define MV64340_MPSC_CAUSE_REG(port) (0xb804 + (port << 3))
+#define MV64340_MPSC_MASK_REG(port) (0xb884 + (port << 3))
+
+#define MV64340_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port << 12))
+#define MV64340_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port << 12))
+#define MV64340_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port << 12))
+#define MV64340_MPSC_CHANNEL_REG1(port) (0x800c + (port << 12))
+#define MV64340_MPSC_CHANNEL_REG2(port) (0x8010 + (port << 12))
+#define MV64340_MPSC_CHANNEL_REG3(port) (0x8014 + (port << 12))
+#define MV64340_MPSC_CHANNEL_REG4(port) (0x8018 + (port << 12))
+#define MV64340_MPSC_CHANNEL_REG5(port) (0x801c + (port << 12))
+#define MV64340_MPSC_CHANNEL_REG6(port) (0x8020 + (port << 12))
+#define MV64340_MPSC_CHANNEL_REG7(port) (0x8024 + (port << 12))
+#define MV64340_MPSC_CHANNEL_REG8(port) (0x8028 + (port << 12))
+#define MV64340_MPSC_CHANNEL_REG9(port) (0x802c + (port << 12))
+#define MV64340_MPSC_CHANNEL_REG10(port) (0x8030 + (port << 12))
+
+ /* MPSC0 Registers */
+
+
+/***************************************/
+/* SDMA Registers */
+/***************************************/
+
+#define MV64340_SDMA_CONFIG_REG(channel) (0x4000 + (channel << 13))
+#define MV64340_SDMA_COMMAND_REG(channel) (0x4008 + (channel << 13))
+#define MV64340_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel << 13))
+#define MV64340_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel << 13))
+#define MV64340_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel << 13))
+
+#define MV64340_SDMA_CAUSE_REG 0xb800
+#define MV64340_SDMA_MASK_REG 0xb880
+
+/* BRG Interrupts */
+
+#define MV64340_BRG_CONFIG_REG(brg) (0xb200 + (brg << 3))
+#define MV64340_BRG_BAUDE_TUNING_REG(brg) (0xb208 + (brg << 3))
+#define MV64340_BRG_CAUSE_REG 0xb834
+#define MV64340_BRG_MASK_REG 0xb8b4
+
+/****************************************/
+/* DMA Channel Control */
+/****************************************/
+
+#define MV64340_DMA_CHANNEL0_CONTROL 0x840
+#define MV64340_DMA_CHANNEL0_CONTROL_HIGH 0x880
+#define MV64340_DMA_CHANNEL1_CONTROL 0x844
+#define MV64340_DMA_CHANNEL1_CONTROL_HIGH 0x884
+#define MV64340_DMA_CHANNEL2_CONTROL 0x848
+#define MV64340_DMA_CHANNEL2_CONTROL_HIGH 0x888
+#define MV64340_DMA_CHANNEL3_CONTROL 0x84C
+#define MV64340_DMA_CHANNEL3_CONTROL_HIGH 0x88C
+
+
+/****************************************/
+/* IDMA Registers */
+/****************************************/
+
+#define MV64340_DMA_CHANNEL0_BYTE_COUNT 0x800
+#define MV64340_DMA_CHANNEL1_BYTE_COUNT 0x804
+#define MV64340_DMA_CHANNEL2_BYTE_COUNT 0x808
+#define MV64340_DMA_CHANNEL3_BYTE_COUNT 0x80C
+#define MV64340_DMA_CHANNEL0_SOURCE_ADDR 0x810
+#define MV64340_DMA_CHANNEL1_SOURCE_ADDR 0x814
+#define MV64340_DMA_CHANNEL2_SOURCE_ADDR 0x818
+#define MV64340_DMA_CHANNEL3_SOURCE_ADDR 0x81c
+#define MV64340_DMA_CHANNEL0_DESTINATION_ADDR 0x820
+#define MV64340_DMA_CHANNEL1_DESTINATION_ADDR 0x824
+#define MV64340_DMA_CHANNEL2_DESTINATION_ADDR 0x828
+#define MV64340_DMA_CHANNEL3_DESTINATION_ADDR 0x82C
+#define MV64340_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830
+#define MV64340_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834
+#define MV64340_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838
+#define MV64340_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C
+#define MV64340_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870
+#define MV64340_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874
+#define MV64340_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878
+#define MV64340_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C
+
+ /* IDMA Address Decoding Base Address Registers */
+
+#define MV64340_DMA_BASE_ADDR_REG0 0xa00
+#define MV64340_DMA_BASE_ADDR_REG1 0xa08
+#define MV64340_DMA_BASE_ADDR_REG2 0xa10
+#define MV64340_DMA_BASE_ADDR_REG3 0xa18
+#define MV64340_DMA_BASE_ADDR_REG4 0xa20
+#define MV64340_DMA_BASE_ADDR_REG5 0xa28
+#define MV64340_DMA_BASE_ADDR_REG6 0xa30
+#define MV64340_DMA_BASE_ADDR_REG7 0xa38
+
+ /* IDMA Address Decoding Size Address Register */
+
+#define MV64340_DMA_SIZE_REG0 0xa04
+#define MV64340_DMA_SIZE_REG1 0xa0c
+#define MV64340_DMA_SIZE_REG2 0xa14
+#define MV64340_DMA_SIZE_REG3 0xa1c
+#define MV64340_DMA_SIZE_REG4 0xa24
+#define MV64340_DMA_SIZE_REG5 0xa2c
+#define MV64340_DMA_SIZE_REG6 0xa34
+#define MV64340_DMA_SIZE_REG7 0xa3C
+
+ /* IDMA Address Decoding High Address Remap and Access Protection Registers */
+
+#define MV64340_DMA_HIGH_ADDR_REMAP_REG0 0xa60
+#define MV64340_DMA_HIGH_ADDR_REMAP_REG1 0xa64
+#define MV64340_DMA_HIGH_ADDR_REMAP_REG2 0xa68
+#define MV64340_DMA_HIGH_ADDR_REMAP_REG3 0xa6C
+#define MV64340_DMA_BASE_ADDR_ENABLE_REG 0xa80
+#define MV64340_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70
+#define MV64340_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74
+#define MV64340_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78
+#define MV64340_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c
+#define MV64340_DMA_ARBITER_CONTROL 0x860
+#define MV64340_DMA_CROSS_BAR_TIMEOUT 0x8d0
+
+ /* IDMA Headers Retarget Registers */
+
+#define MV64340_DMA_HEADERS_RETARGET_CONTROL 0xa84
+#define MV64340_DMA_HEADERS_RETARGET_BASE 0xa88
+
+ /* IDMA Interrupt Register */
+
+#define MV64340_DMA_INTERRUPT_CAUSE_REG 0x8c0
+#define MV64340_DMA_INTERRUPT_CAUSE_MASK 0x8c4
+#define MV64340_DMA_ERROR_ADDR 0x8c8
+#define MV64340_DMA_ERROR_SELECT 0x8cc
+
+ /* IDMA Debug Register ( for internal use ) */
+
+#define MV64340_DMA_DEBUG_LOW 0x8e0
+#define MV64340_DMA_DEBUG_HIGH 0x8e4
+#define MV64340_DMA_SPARE 0xA8C
+
+/****************************************/
+/* Timer_Counter */
+/****************************************/
+
+#define MV64340_TIMER_COUNTER0 0x850
+#define MV64340_TIMER_COUNTER1 0x854
+#define MV64340_TIMER_COUNTER2 0x858
+#define MV64340_TIMER_COUNTER3 0x85C
+#define MV64340_TIMER_COUNTER_0_3_CONTROL 0x864
+#define MV64340_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868
+#define MV64340_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c
+
+/****************************************/
+/* Watchdog registers */
+/****************************************/
+
+#define MV64340_WATCHDOG_CONFIG_REG 0xb410
+#define MV64340_WATCHDOG_VALUE_REG 0xb414
+
+/****************************************/
+/* I2C Registers */
+/****************************************/
+
+#define MV64XXX_I2C_OFFSET 0xc000
+#define MV64XXX_I2C_REG_BLOCK_SIZE 0x0020
+
+/****************************************/
+/* GPP Interface Registers */
+/****************************************/
+
+#define MV64340_GPP_IO_CONTROL 0xf100
+#define MV64340_GPP_LEVEL_CONTROL 0xf110
+#define MV64340_GPP_VALUE 0xf104
+#define MV64340_GPP_INTERRUPT_CAUSE 0xf108
+#define MV64340_GPP_INTERRUPT_MASK0 0xf10c
+#define MV64340_GPP_INTERRUPT_MASK1 0xf114
+#define MV64340_GPP_VALUE_SET 0xf118
+#define MV64340_GPP_VALUE_CLEAR 0xf11c
+
+/****************************************/
+/* Interrupt Controller Registers */
+/****************************************/
+
+/****************************************/
+/* Interrupts */
+/****************************************/
+
+#define MV64340_MAIN_INTERRUPT_CAUSE_LOW 0x004
+#define MV64340_MAIN_INTERRUPT_CAUSE_HIGH 0x00c
+#define MV64340_CPU_INTERRUPT0_MASK_LOW 0x014
+#define MV64340_CPU_INTERRUPT0_MASK_HIGH 0x01c
+#define MV64340_CPU_INTERRUPT0_SELECT_CAUSE 0x024
+#define MV64340_CPU_INTERRUPT1_MASK_LOW 0x034
+#define MV64340_CPU_INTERRUPT1_MASK_HIGH 0x03c
+#define MV64340_CPU_INTERRUPT1_SELECT_CAUSE 0x044
+#define MV64340_INTERRUPT0_MASK_0_LOW 0x054
+#define MV64340_INTERRUPT0_MASK_0_HIGH 0x05c
+#define MV64340_INTERRUPT0_SELECT_CAUSE 0x064
+#define MV64340_INTERRUPT1_MASK_0_LOW 0x074
+#define MV64340_INTERRUPT1_MASK_0_HIGH 0x07c
+#define MV64340_INTERRUPT1_SELECT_CAUSE 0x084
+
+/****************************************/
+/* MPP Interface Registers */
+/****************************************/
+
+#define MV64340_MPP_CONTROL0 0xf000
+#define MV64340_MPP_CONTROL1 0xf004
+#define MV64340_MPP_CONTROL2 0xf008
+#define MV64340_MPP_CONTROL3 0xf00c
+
+/****************************************/
+/* Serial Initialization registers */
+/****************************************/
+
+#define MV64340_SERIAL_INIT_LAST_DATA 0xf324
+#define MV64340_SERIAL_INIT_CONTROL 0xf328
+#define MV64340_SERIAL_INIT_STATUS 0xf32c
+
+#endif /* ASM_MV643XX_H */
diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events
index 7d8063ac42..dac86ad3f0 100644
--- a/hw/pci-host/trace-events
+++ b/hw/pci-host/trace-events
@@ -3,6 +3,12 @@
# grackle.c
grackle_set_irq(int irq_num, int level) "set_irq num %d level %d"
+# mv64361.c
+mv64361_region_map(const char *name, uint64_t poffs, uint64_t size, uint64_t moffs) "Mapping %s 0x%"PRIx64"+0x%"PRIx64" @ 0x%"PRIx64
+mv64361_region_enable(const char *op, int num) "Should %s region %d"
+mv64361_reg_read(uint64_t addr, uint32_t val) "0x%"PRIx64" -> 0x%x"
+mv64361_reg_write(uint64_t addr, uint64_t val) "0x%"PRIx64" <- 0x%"PRIx64
+
# sabre.c
sabre_set_request(int irq_num) "request irq %d"
sabre_clear_request(int irq_num) "clear request irq %d"
diff --git a/include/hw/pci-host/mv64361.h b/include/hw/pci-host/mv64361.h
new file mode 100644
index 0000000000..9cdb35cb3c
--- /dev/null
+++ b/include/hw/pci-host/mv64361.h
@@ -0,0 +1,8 @@
+#ifndef MV64361_H
+#define MV64361_H
+
+#define TYPE_MV64361 "mv64361"
+
+PCIBus *mv64361_get_pci_bus(DeviceState *dev, int n);
+
+#endif
diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h
index ac0c23ebc7..5c14681b82 100644
--- a/include/hw/pci/pci_ids.h
+++ b/include/hw/pci/pci_ids.h
@@ -214,6 +214,7 @@
#define PCI_DEVICE_ID_VIA_8231_PM 0x8235
#define PCI_VENDOR_ID_MARVELL 0x11ab
+#define PCI_DEVICE_ID_MARVELL_MV6436X 0x6460
#define PCI_VENDOR_ID_SILICON_MOTION 0x126f
#define PCI_DEVICE_ID_SM501 0x0501
--
2.21.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v7 5/8] vt82c686: Add emulation of VT8231 south bridge
2021-03-10 2:58 [PATCH v7 0/8] Pegasos2 emulation BALATON Zoltan
` (4 preceding siblings ...)
2021-03-10 2:58 ` [PATCH v7 7/8] hw/pci-host: Add emulation of Marvell MV64361 PPC system controller BALATON Zoltan
@ 2021-03-10 2:58 ` BALATON Zoltan
2021-03-10 2:58 ` [PATCH v7 4/8] vt82c686: Introduce abstract TYPE_VIA_ISA and base vt82c686b_isa on it BALATON Zoltan
` (2 subsequent siblings)
8 siblings, 0 replies; 32+ messages in thread
From: BALATON Zoltan @ 2021-03-10 2:58 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Peter Maydell, Paolo Bonzini, f4bug, David Gibson
Add emulation of VT8231 south bridge ISA part based on the similar
VT82C686B but implemented in a separate subclass that holds the
differences while reusing parts that can be shared.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/isa/vt82c686.c | 84 +++++++++++++++++++++++++++++++++++++++
include/hw/isa/vt82c686.h | 1 +
include/hw/pci/pci_ids.h | 1 +
3 files changed, 86 insertions(+)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index fddbc974bd..51d9eff0ff 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -8,6 +8,9 @@
*
* Contributions after 2012-01-13 are licensed under the terms of the
* GNU GPL, version 2 or (at your option) any later version.
+ *
+ * VT8231 south bridge support and general clean up to allow it
+ * Copyright (c) 2018-2020 BALATON Zoltan
*/
#include "qemu/osdep.h"
@@ -733,6 +736,86 @@ static const TypeInfo vt82c686b_isa_info = {
.class_init = vt82c686b_class_init,
};
+/* TYPE_VT8231_ISA */
+
+static void vt8231_write_config(PCIDevice *d, uint32_t addr,
+ uint32_t val, int len)
+{
+ ViaISAState *s = VIA_ISA(d);
+
+ trace_via_isa_write(addr, val, len);
+ pci_default_write_config(d, addr, val, len);
+ if (addr == 0x50) {
+ /* BIT(2): enable or disable superio config io ports */
+ via_superio_io_enable(s->via_sio, val & BIT(2));
+ }
+}
+
+static void vt8231_isa_reset(DeviceState *dev)
+{
+ ViaISAState *s = VIA_ISA(dev);
+ uint8_t *pci_conf = s->dev.config;
+
+ pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
+ pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+ PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
+ pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
+
+ pci_conf[0x58] = 0x40; /* Miscellaneous Control 0 */
+ pci_conf[0x67] = 0x08; /* Fast IR Config */
+ pci_conf[0x6b] = 0x01; /* Fast IR I/O Base */
+}
+
+static void vt8231_realize(PCIDevice *d, Error **errp)
+{
+ ViaISAState *s = VIA_ISA(d);
+ DeviceState *dev = DEVICE(d);
+ ISABus *isa_bus;
+ qemu_irq *isa_irq;
+ int i;
+
+ qdev_init_gpio_out(dev, &s->cpu_intr, 1);
+ isa_irq = qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1);
+ isa_bus = isa_bus_new(dev, get_system_memory(), pci_address_space_io(d),
+ &error_fatal);
+ isa_bus_irqs(isa_bus, i8259_init(isa_bus, *isa_irq));
+ i8254_pit_init(isa_bus, 0x40, 0, NULL);
+ i8257_dma_init(isa_bus, 0);
+ s->via_sio = VIA_SUPERIO(isa_create_simple(isa_bus, TYPE_VT8231_SUPERIO));
+ mc146818_rtc_init(isa_bus, 2000, NULL);
+
+ for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) {
+ if (i < PCI_COMMAND || i >= PCI_REVISION_ID) {
+ d->wmask[i] = 0;
+ }
+ }
+}
+
+static void vt8231_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ k->realize = vt8231_realize;
+ k->config_write = vt8231_write_config;
+ k->vendor_id = PCI_VENDOR_ID_VIA;
+ k->device_id = PCI_DEVICE_ID_VIA_8231_ISA;
+ k->class_id = PCI_CLASS_BRIDGE_ISA;
+ k->revision = 0x10;
+ dc->reset = vt8231_isa_reset;
+ dc->desc = "ISA bridge";
+ dc->vmsd = &vmstate_via;
+ /* Reason: part of VIA VT8231 southbridge, needs to be wired up */
+ dc->user_creatable = false;
+}
+
+static const TypeInfo vt8231_isa_info = {
+ .name = TYPE_VT8231_ISA,
+ .parent = TYPE_VIA_ISA,
+ .instance_size = sizeof(ViaISAState),
+ .class_init = vt8231_class_init,
+};
+
static void vt82c686b_register_types(void)
{
@@ -744,6 +827,7 @@ static void vt82c686b_register_types(void)
type_register_static(&vt8231_superio_info);
type_register_static(&via_isa_info);
type_register_static(&vt82c686b_isa_info);
+ type_register_static(&vt8231_isa_info);
}
type_init(vt82c686b_register_types)
diff --git a/include/hw/isa/vt82c686.h b/include/hw/isa/vt82c686.h
index 0692b9a527..0f01aaa471 100644
--- a/include/hw/isa/vt82c686.h
+++ b/include/hw/isa/vt82c686.h
@@ -3,6 +3,7 @@
#define TYPE_VT82C686B_ISA "vt82c686b-isa"
#define TYPE_VT82C686B_PM "vt82c686b-pm"
+#define TYPE_VT8231_ISA "vt8231-isa"
#define TYPE_VT8231_PM "vt8231-pm"
#define TYPE_VIA_AC97 "via-ac97"
#define TYPE_VIA_MC97 "via-mc97"
diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h
index aa3f67eaa4..ac0c23ebc7 100644
--- a/include/hw/pci/pci_ids.h
+++ b/include/hw/pci/pci_ids.h
@@ -210,6 +210,7 @@
#define PCI_DEVICE_ID_VIA_82C686B_PM 0x3057
#define PCI_DEVICE_ID_VIA_AC97 0x3058
#define PCI_DEVICE_ID_VIA_MC97 0x3068
+#define PCI_DEVICE_ID_VIA_8231_ISA 0x8231
#define PCI_DEVICE_ID_VIA_8231_PM 0x8235
#define PCI_VENDOR_ID_MARVELL 0x11ab
--
2.21.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v7 4/8] vt82c686: Introduce abstract TYPE_VIA_ISA and base vt82c686b_isa on it
2021-03-10 2:58 [PATCH v7 0/8] Pegasos2 emulation BALATON Zoltan
` (5 preceding siblings ...)
2021-03-10 2:58 ` [PATCH v7 5/8] vt82c686: Add emulation of VT8231 south bridge BALATON Zoltan
@ 2021-03-10 2:58 ` BALATON Zoltan
2021-03-10 2:58 ` [PATCH v7 6/8] hw/isa/Kconfig: Add missing dependency VIA VT82C686 -> APM BALATON Zoltan
2021-03-13 13:27 ` [PATCH v7 0/8] Pegasos2 emulation BALATON Zoltan
8 siblings, 0 replies; 32+ messages in thread
From: BALATON Zoltan @ 2021-03-10 2:58 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Peter Maydell, Paolo Bonzini, f4bug, David Gibson
To allow reusing ISA bridge emulation for vt8231_isa move the device
state of vt82c686b_isa emulation in an abstract via_isa class. This
change breaks migration back compatibility but this is not an issue
for Fuloong2E machine which is not versioned or migration supported.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/isa/vt82c686.c | 70 ++++++++++++++++++++++------------------
include/hw/pci/pci_ids.h | 2 +-
2 files changed, 40 insertions(+), 32 deletions(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 8131cb42a9..fddbc974bd 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -611,24 +611,48 @@ static const TypeInfo vt8231_superio_info = {
};
-OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA)
+#define TYPE_VIA_ISA "via-isa"
+OBJECT_DECLARE_SIMPLE_TYPE(ViaISAState, VIA_ISA)
-struct VT82C686BISAState {
+struct ViaISAState {
PCIDevice dev;
qemu_irq cpu_intr;
ViaSuperIOState *via_sio;
};
+static const VMStateDescription vmstate_via = {
+ .name = "via-isa",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_PCI_DEVICE(dev, ViaISAState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const TypeInfo via_isa_info = {
+ .name = TYPE_VIA_ISA,
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(ViaISAState),
+ .abstract = true,
+ .interfaces = (InterfaceInfo[]) {
+ { INTERFACE_CONVENTIONAL_PCI_DEVICE },
+ { },
+ },
+};
+
static void via_isa_request_i8259_irq(void *opaque, int irq, int level)
{
- VT82C686BISAState *s = opaque;
+ ViaISAState *s = opaque;
qemu_set_irq(s->cpu_intr, level);
}
+/* TYPE_VT82C686B_ISA */
+
static void vt82c686b_write_config(PCIDevice *d, uint32_t addr,
uint32_t val, int len)
{
- VT82C686BISAState *s = VT82C686B_ISA(d);
+ ViaISAState *s = VIA_ISA(d);
trace_via_isa_write(addr, val, len);
pci_default_write_config(d, addr, val, len);
@@ -638,19 +662,9 @@ static void vt82c686b_write_config(PCIDevice *d, uint32_t addr,
}
}
-static const VMStateDescription vmstate_via = {
- .name = "vt82c686b",
- .version_id = 1,
- .minimum_version_id = 1,
- .fields = (VMStateField[]) {
- VMSTATE_PCI_DEVICE(dev, VT82C686BISAState),
- VMSTATE_END_OF_LIST()
- }
-};
-
static void vt82c686b_isa_reset(DeviceState *dev)
{
- VT82C686BISAState *s = VT82C686B_ISA(dev);
+ ViaISAState *s = VIA_ISA(dev);
uint8_t *pci_conf = s->dev.config;
pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
@@ -670,7 +684,7 @@ static void vt82c686b_isa_reset(DeviceState *dev)
static void vt82c686b_realize(PCIDevice *d, Error **errp)
{
- VT82C686BISAState *s = VT82C686B_ISA(d);
+ ViaISAState *s = VIA_ISA(d);
DeviceState *dev = DEVICE(d);
ISABus *isa_bus;
qemu_irq *isa_irq;
@@ -694,7 +708,7 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
}
}
-static void via_class_init(ObjectClass *klass, void *data)
+static void vt82c686b_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
@@ -702,28 +716,21 @@ static void via_class_init(ObjectClass *klass, void *data)
k->realize = vt82c686b_realize;
k->config_write = vt82c686b_write_config;
k->vendor_id = PCI_VENDOR_ID_VIA;
- k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE;
+ k->device_id = PCI_DEVICE_ID_VIA_82C686B_ISA;
k->class_id = PCI_CLASS_BRIDGE_ISA;
k->revision = 0x40;
dc->reset = vt82c686b_isa_reset;
dc->desc = "ISA bridge";
dc->vmsd = &vmstate_via;
- /*
- * Reason: part of VIA VT82C686 southbridge, needs to be wired up,
- * e.g. by mips_fuloong2e_init()
- */
+ /* Reason: part of VIA VT82C686 southbridge, needs to be wired up */
dc->user_creatable = false;
}
-static const TypeInfo via_info = {
+static const TypeInfo vt82c686b_isa_info = {
.name = TYPE_VT82C686B_ISA,
- .parent = TYPE_PCI_DEVICE,
- .instance_size = sizeof(VT82C686BISAState),
- .class_init = via_class_init,
- .interfaces = (InterfaceInfo[]) {
- { INTERFACE_CONVENTIONAL_PCI_DEVICE },
- { },
- },
+ .parent = TYPE_VIA_ISA,
+ .instance_size = sizeof(ViaISAState),
+ .class_init = vt82c686b_class_init,
};
@@ -735,7 +742,8 @@ static void vt82c686b_register_types(void)
type_register_static(&via_superio_info);
type_register_static(&vt82c686b_superio_info);
type_register_static(&vt8231_superio_info);
- type_register_static(&via_info);
+ type_register_static(&via_isa_info);
+ type_register_static(&vt82c686b_isa_info);
}
type_init(vt82c686b_register_types)
diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h
index ea28dcc850..aa3f67eaa4 100644
--- a/include/hw/pci/pci_ids.h
+++ b/include/hw/pci/pci_ids.h
@@ -204,7 +204,7 @@
#define PCI_VENDOR_ID_XILINX 0x10ee
#define PCI_VENDOR_ID_VIA 0x1106
-#define PCI_DEVICE_ID_VIA_ISA_BRIDGE 0x0686
+#define PCI_DEVICE_ID_VIA_82C686B_ISA 0x0686
#define PCI_DEVICE_ID_VIA_IDE 0x0571
#define PCI_DEVICE_ID_VIA_UHCI 0x3038
#define PCI_DEVICE_ID_VIA_82C686B_PM 0x3057
--
2.21.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v7 6/8] hw/isa/Kconfig: Add missing dependency VIA VT82C686 -> APM
2021-03-10 2:58 [PATCH v7 0/8] Pegasos2 emulation BALATON Zoltan
` (6 preceding siblings ...)
2021-03-10 2:58 ` [PATCH v7 4/8] vt82c686: Introduce abstract TYPE_VIA_ISA and base vt82c686b_isa on it BALATON Zoltan
@ 2021-03-10 2:58 ` BALATON Zoltan
2021-03-13 13:27 ` [PATCH v7 0/8] Pegasos2 emulation BALATON Zoltan
8 siblings, 0 replies; 32+ messages in thread
From: BALATON Zoltan @ 2021-03-10 2:58 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Peter Maydell, Paolo Bonzini, f4bug, David Gibson
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
TYPE_VIA_PM calls apm_init() in via_pm_realize(), so
requires APM to be selected.
Reported-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/isa/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index c7f07854f7..9c026d0c51 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -47,6 +47,7 @@ config VT82C686
select ACPI_SMBUS
select SERIAL_ISA
select FDC
+ select APM
config SMC37C669
bool
--
2.21.3
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH v7 0/8] Pegasos2 emulation
2021-03-10 2:58 [PATCH v7 0/8] Pegasos2 emulation BALATON Zoltan
` (7 preceding siblings ...)
2021-03-10 2:58 ` [PATCH v7 6/8] hw/isa/Kconfig: Add missing dependency VIA VT82C686 -> APM BALATON Zoltan
@ 2021-03-13 13:27 ` BALATON Zoltan
2021-03-15 12:33 ` BALATON Zoltan
8 siblings, 1 reply; 32+ messages in thread
From: BALATON Zoltan @ 2021-03-13 13:27 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Peter Maydell, David Gibson, f4bug, Paolo Bonzini
[-- Attachment #1: Type: text/plain, Size: 3859 bytes --]
On Wed, 10 Mar 2021, BALATON Zoltan wrote:
> Hello,
I've started posting this series well in advance to get it into 6.0 and
yet it seems like it may be missing it due to organisational issues (no
real complaints were found with patches but Philippe seems to like more
review that does not seem to happen as nobody is interested). Looks like
David is waiting for an ack from Philippe but will be away next week so if
this is not resolved now it may be too late on Monday. To avoid that:
David, could you please send an ack before you leave for the last two
patches so it could get committed via some other tree while you're away?
Philippe, if you can't ack the vt82c686 patches now are you OK with taking
the whole series via your tree before the freeze? That would give you some
more days to review and it could always be reverted during the freeze but
if it's not merged now I'll have to wait until the summer to get it in
again which would be another long delay. I don't think this will get more
reviews unless it's in master and people can start using and testing it
better.
Thank you,
BALATON Zoltan
> This is adding a new PPC board called pegasos2. More info on it can be
> found at:
>
> https://osdn.net/projects/qmiga/wiki/SubprojectPegasos2
>
> Currently it needs a firmware ROM image that I cannot include due to
> original copyright holder (bPlan) did not release it under a free
> licence but I have plans to write a replacement in the future. With
> the original board firmware it can boot MorphOS now as:
>
> qemu-system-ppc -M pegasos2 -cdrom morphos.iso -device ati-vga,romfile="" -serial stdio
>
> then enter "boot cd boot.img" at the firmware "ok" prompt as described
> in the MorphOS.readme. To boot Linux use same command line with e.g.
> -cdrom debian-8.11.0-powerpc-netinst.iso then enter
> "boot cd install/pegasos"
>
> The last patch adds the actual board code after previous patches
> adding VT8231 and MV64361 system controller chip emulation.
>
> Regards,
> BALATON Zoltan
>
> v7: Fix errp usage in patch 2
>
> v6: Rebased on master, updated commit message about migration change
>
> v5: Changes for review comments from David and Philippe
>
> V4: Rename pegasos2_reset to pegasos2_cpu_reset
> Add new files to MAINTAINERS
>
> BALATON Zoltan (7):
> vt82c686: Implement control of serial port io ranges via config regs
> vt82c686: QOM-ify superio related functionality
> vt82c686: Add VT8231_SUPERIO based on VIA_SUPERIO
> vt82c686: Introduce abstract TYPE_VIA_ISA and base vt82c686b_isa on it
> vt82c686: Add emulation of VT8231 south bridge
> hw/pci-host: Add emulation of Marvell MV64361 PPC system controller
> hw/ppc: Add emulation of Genesi/bPlan Pegasos II
>
> Philippe Mathieu-Daudé (1):
> hw/isa/Kconfig: Add missing dependency VIA VT82C686 -> APM
>
> MAINTAINERS | 10 +
> default-configs/devices/ppc-softmmu.mak | 2 +
> hw/isa/Kconfig | 1 +
> hw/isa/vt82c686.c | 517 +++++++++++--
> hw/pci-host/Kconfig | 4 +
> hw/pci-host/meson.build | 2 +
> hw/pci-host/mv64361.c | 966 ++++++++++++++++++++++++
> hw/pci-host/mv643xx.h | 918 ++++++++++++++++++++++
> hw/pci-host/trace-events | 6 +
> hw/ppc/Kconfig | 9 +
> hw/ppc/meson.build | 2 +
> hw/ppc/pegasos2.c | 144 ++++
> include/hw/isa/vt82c686.h | 2 +-
> include/hw/pci-host/mv64361.h | 8 +
> include/hw/pci/pci_ids.h | 4 +-
> 15 files changed, 2512 insertions(+), 83 deletions(-)
> create mode 100644 hw/pci-host/mv64361.c
> create mode 100644 hw/pci-host/mv643xx.h
> create mode 100644 hw/ppc/pegasos2.c
> create mode 100644 include/hw/pci-host/mv64361.h
>
>
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v7 0/8] Pegasos2 emulation
2021-03-13 13:27 ` [PATCH v7 0/8] Pegasos2 emulation BALATON Zoltan
@ 2021-03-15 12:33 ` BALATON Zoltan
2021-03-16 9:01 ` Laurent Vivier
0 siblings, 1 reply; 32+ messages in thread
From: BALATON Zoltan @ 2021-03-15 12:33 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Peter Maydell
Cc: qemu-devel, Paolo Bonzini, qemu-ppc, f4bug, David Gibson
[-- Attachment #1: Type: text/plain, Size: 4801 bytes --]
On Sat, 13 Mar 2021, BALATON Zoltan wrote:
> On Wed, 10 Mar 2021, BALATON Zoltan wrote:
>> Hello,
>
> I've started posting this series well in advance to get it into 6.0 and yet
> it seems like it may be missing it due to organisational issues (no real
> complaints were found with patches but Philippe seems to like more review
> that does not seem to happen as nobody is interested). Looks like David is
> waiting for an ack from Philippe but will be away next week so if this is not
> resolved now it may be too late on Monday. To avoid that:
>
> David, could you please send an ack before you leave for the last two patches
> so it could get committed via some other tree while you're away?
>
> Philippe, if you can't ack the vt82c686 patches now are you OK with taking
> the whole series via your tree before the freeze? That would give you some
> more days to review and it could always be reverted during the freeze but if
> it's not merged now I'll have to wait until the summer to get it in again
> which would be another long delay. I don't think this will get more reviews
> unless it's in master and people can start using and testing it better.
Hello,
Since David seems to be away for this week before seeing my mail asking
for an ack from him, now this can only get in by Philippe or Peter. (David
said before he'd be OK with the series if Philippe acked it so I think
that can count as an implicit ack and it could always be reverted before
the releease.)
Philippe, do you have anything against this to get merged now? If not
please send a pull or ack it so it has a chance to be in 6.0 or tell if
you still intend to do anything about it before the freeze. This series
was on the list since January and the remaining parts you did not take are
here since February 22nd and the version after your first review since two
weeks so it would be nice to sort this out and not block it any further
without a good reason.
Regards,
BALATON Zoltan
>> This is adding a new PPC board called pegasos2. More info on it can be
>> found at:
>>
>> https://osdn.net/projects/qmiga/wiki/SubprojectPegasos2
>>
>> Currently it needs a firmware ROM image that I cannot include due to
>> original copyright holder (bPlan) did not release it under a free
>> licence but I have plans to write a replacement in the future. With
>> the original board firmware it can boot MorphOS now as:
>>
>> qemu-system-ppc -M pegasos2 -cdrom morphos.iso -device ati-vga,romfile=""
>> -serial stdio
>>
>> then enter "boot cd boot.img" at the firmware "ok" prompt as described
>> in the MorphOS.readme. To boot Linux use same command line with e.g.
>> -cdrom debian-8.11.0-powerpc-netinst.iso then enter
>> "boot cd install/pegasos"
>>
>> The last patch adds the actual board code after previous patches
>> adding VT8231 and MV64361 system controller chip emulation.
>>
>> Regards,
>> BALATON Zoltan
>>
>> v7: Fix errp usage in patch 2
>>
>> v6: Rebased on master, updated commit message about migration change
>>
>> v5: Changes for review comments from David and Philippe
>>
>> V4: Rename pegasos2_reset to pegasos2_cpu_reset
>> Add new files to MAINTAINERS
>>
>> BALATON Zoltan (7):
>> vt82c686: Implement control of serial port io ranges via config regs
>> vt82c686: QOM-ify superio related functionality
>> vt82c686: Add VT8231_SUPERIO based on VIA_SUPERIO
>> vt82c686: Introduce abstract TYPE_VIA_ISA and base vt82c686b_isa on it
>> vt82c686: Add emulation of VT8231 south bridge
>> hw/pci-host: Add emulation of Marvell MV64361 PPC system controller
>> hw/ppc: Add emulation of Genesi/bPlan Pegasos II
>>
>> Philippe Mathieu-Daudé (1):
>> hw/isa/Kconfig: Add missing dependency VIA VT82C686 -> APM
>>
>> MAINTAINERS | 10 +
>> default-configs/devices/ppc-softmmu.mak | 2 +
>> hw/isa/Kconfig | 1 +
>> hw/isa/vt82c686.c | 517 +++++++++++--
>> hw/pci-host/Kconfig | 4 +
>> hw/pci-host/meson.build | 2 +
>> hw/pci-host/mv64361.c | 966 ++++++++++++++++++++++++
>> hw/pci-host/mv643xx.h | 918 ++++++++++++++++++++++
>> hw/pci-host/trace-events | 6 +
>> hw/ppc/Kconfig | 9 +
>> hw/ppc/meson.build | 2 +
>> hw/ppc/pegasos2.c | 144 ++++
>> include/hw/isa/vt82c686.h | 2 +-
>> include/hw/pci-host/mv64361.h | 8 +
>> include/hw/pci/pci_ids.h | 4 +-
>> 15 files changed, 2512 insertions(+), 83 deletions(-)
>> create mode 100644 hw/pci-host/mv64361.c
>> create mode 100644 hw/pci-host/mv643xx.h
>> create mode 100644 hw/ppc/pegasos2.c
>> create mode 100644 include/hw/pci-host/mv64361.h
>>
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 0/8] Pegasos2 emulation
2021-03-15 12:33 ` BALATON Zoltan
@ 2021-03-16 9:01 ` Laurent Vivier
2021-03-16 11:49 ` Philippe Mathieu-Daudé
2021-03-16 12:21 ` BALATON Zoltan
0 siblings, 2 replies; 32+ messages in thread
From: Laurent Vivier @ 2021-03-16 9:01 UTC (permalink / raw)
To: BALATON Zoltan, Philippe Mathieu-Daudé, Peter Maydell
Cc: Mark Cave-Ayland, qemu-devel, f4bug, qemu-ppc, Paolo Bonzini,
David Gibson
Le 15/03/2021 à 13:33, BALATON Zoltan a écrit :
> On Sat, 13 Mar 2021, BALATON Zoltan wrote:
>> On Wed, 10 Mar 2021, BALATON Zoltan wrote:
>>> Hello,
>>
>> I've started posting this series well in advance to get it into 6.0 and yet it seems like it may
>> be missing it due to organisational issues (no real complaints were found with patches but
>> Philippe seems to like more review that does not seem to happen as nobody is interested). Looks
>> like David is waiting for an ack from Philippe but will be away next week so if this is not
>> resolved now it may be too late on Monday. To avoid that:
>>
>> David, could you please send an ack before you leave for the last two patches so it could get
>> committed via some other tree while you're away?
>>
>> Philippe, if you can't ack the vt82c686 patches now are you OK with taking the whole series via
>> your tree before the freeze? That would give you some more days to review and it could always be
>> reverted during the freeze but if it's not merged now I'll have to wait until the summer to get it
>> in again which would be another long delay. I don't think this will get more reviews unless it's
>> in master and people can start using and testing it better.
>
> Hello,
>
> Since David seems to be away for this week before seeing my mail asking for an ack from him, now
> this can only get in by Philippe or Peter. (David said before he'd be OK with the series if Philippe
> acked it so I think that can count as an implicit ack and it could always be reverted before the
> releease.)
>
> Philippe, do you have anything against this to get merged now? If not please send a pull or ack it
> so it has a chance to be in 6.0 or tell if you still intend to do anything about it before the
> freeze. This series was on the list since January and the remaining parts you did not take are here
> since February 22nd and the version after your first review since two weeks so it would be nice to
> sort this out and not block it any further without a good reason.
Pegasos looks like a New World PowerMac, so perhaps Mark can help?
Thanks,
Laurent
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 0/8] Pegasos2 emulation
2021-03-16 9:01 ` Laurent Vivier
@ 2021-03-16 11:49 ` Philippe Mathieu-Daudé
2021-03-16 12:11 ` Laurent Vivier
` (2 more replies)
2021-03-16 12:21 ` BALATON Zoltan
1 sibling, 3 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-16 11:49 UTC (permalink / raw)
To: Laurent Vivier, BALATON Zoltan, Peter Maydell
Cc: Mark Cave-Ayland, qemu-devel, f4bug, qemu-ppc, Paolo Bonzini,
David Gibson
On 3/16/21 10:01 AM, Laurent Vivier wrote:
> Le 15/03/2021 à 13:33, BALATON Zoltan a écrit :
>> On Sat, 13 Mar 2021, BALATON Zoltan wrote:
>>> On Wed, 10 Mar 2021, BALATON Zoltan wrote:
>>>> Hello,
>>>
>>> I've started posting this series well in advance to get it into 6.0 and yet it seems like it may
>>> be missing it due to organisational issues (no real complaints were found with patches but
>>> Philippe seems to like more review that does not seem to happen as nobody is interested). Looks
>>> like David is waiting for an ack from Philippe but will be away next week so if this is not
>>> resolved now it may be too late on Monday. To avoid that:
>>>
>>> David, could you please send an ack before you leave for the last two patches so it could get
>>> committed via some other tree while you're away?
>>>
>>> Philippe, if you can't ack the vt82c686 patches now are you OK with taking the whole series via
>>> your tree before the freeze? That would give you some more days to review and it could always be
>>> reverted during the freeze but if it's not merged now I'll have to wait until the summer to get it
>>> in again which would be another long delay. I don't think this will get more reviews unless it's
>>> in master and people can start using and testing it better.
>>
>> Hello,
>>
>> Since David seems to be away for this week before seeing my mail asking for an ack from him, now
>> this can only get in by Philippe or Peter. (David said before he'd be OK with the series if Philippe
>> acked it so I think that can count as an implicit ack and it could always be reverted before the
>> releease.)
>>
>> Philippe, do you have anything against this to get merged now? If not please send a pull or ack it
>> so it has a chance to be in 6.0 or tell if you still intend to do anything about it before the
>> freeze. This series was on the list since January and the remaining parts you did not take are here
>> since February 22nd and the version after your first review since two weeks so it would be nice to
>> sort this out and not block it any further without a good reason.
>
> Pegasos looks like a New World PowerMac, so perhaps Mark can help?
The PPC part is mostly reviewed. The problem is the first patch:
"vt82c686: Implement control of serial port io ranges via config regs".
I don't understand it. Zoltan said Paolo isn't acking it because
he doesn't mind. I prefer to be cautious and think than Paolo is
rather too busy.
Laurent, Peter, can you have a look at it?
Thanks,
Phil.
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v7 0/8] Pegasos2 emulation
2021-03-16 11:49 ` Philippe Mathieu-Daudé
@ 2021-03-16 12:11 ` Laurent Vivier
2021-03-16 12:24 ` BALATON Zoltan
2021-03-16 14:17 ` BALATON Zoltan
2021-03-16 14:48 ` BALATON Zoltan
2 siblings, 1 reply; 32+ messages in thread
From: Laurent Vivier @ 2021-03-16 12:11 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, BALATON Zoltan, Peter Maydell
Cc: Paolo Bonzini, Mark Cave-Ayland, qemu-ppc, qemu-devel, David Gibson
Le 16/03/2021 à 12:49, Philippe Mathieu-Daudé a écrit :
> On 3/16/21 10:01 AM, Laurent Vivier wrote:
>> Le 15/03/2021 à 13:33, BALATON Zoltan a écrit :
>>> On Sat, 13 Mar 2021, BALATON Zoltan wrote:
>>>> On Wed, 10 Mar 2021, BALATON Zoltan wrote:
>>>>> Hello,
>>>>
>>>> I've started posting this series well in advance to get it into 6.0 and yet it seems like it may
>>>> be missing it due to organisational issues (no real complaints were found with patches but
>>>> Philippe seems to like more review that does not seem to happen as nobody is interested). Looks
>>>> like David is waiting for an ack from Philippe but will be away next week so if this is not
>>>> resolved now it may be too late on Monday. To avoid that:
>>>>
>>>> David, could you please send an ack before you leave for the last two patches so it could get
>>>> committed via some other tree while you're away?
>>>>
>>>> Philippe, if you can't ack the vt82c686 patches now are you OK with taking the whole series via
>>>> your tree before the freeze? That would give you some more days to review and it could always be
>>>> reverted during the freeze but if it's not merged now I'll have to wait until the summer to get it
>>>> in again which would be another long delay. I don't think this will get more reviews unless it's
>>>> in master and people can start using and testing it better.
>>>
>>> Hello,
>>>
>>> Since David seems to be away for this week before seeing my mail asking for an ack from him, now
>>> this can only get in by Philippe or Peter. (David said before he'd be OK with the series if Philippe
>>> acked it so I think that can count as an implicit ack and it could always be reverted before the
>>> releease.)
>>>
>>> Philippe, do you have anything against this to get merged now? If not please send a pull or ack it
>>> so it has a chance to be in 6.0 or tell if you still intend to do anything about it before the
>>> freeze. This series was on the list since January and the remaining parts you did not take are here
>>> since February 22nd and the version after your first review since two weeks so it would be nice to
>>> sort this out and not block it any further without a good reason.
>>
>> Pegasos looks like a New World PowerMac, so perhaps Mark can help?
>
> The PPC part is mostly reviewed. The problem is the first patch:
> "vt82c686: Implement control of serial port io ranges via config regs".
vt82c686.c is a Fuloong 2E file, why Fuloong 2E maintainers are not involved in the review?
Thanks,
Laurent
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 0/8] Pegasos2 emulation
2021-03-16 12:11 ` Laurent Vivier
@ 2021-03-16 12:24 ` BALATON Zoltan
2021-03-16 12:55 ` Laurent Vivier
0 siblings, 1 reply; 32+ messages in thread
From: BALATON Zoltan @ 2021-03-16 12:24 UTC (permalink / raw)
To: Laurent Vivier
Cc: Peter Maydell, Mark Cave-Ayland, Philippe Mathieu-Daudé,
qemu-devel, qemu-ppc, Paolo Bonzini, David Gibson
[-- Attachment #1: Type: text/plain, Size: 3317 bytes --]
On Tue, 16 Mar 2021, Laurent Vivier wrote:
> Le 16/03/2021 à 12:49, Philippe Mathieu-Daudé a écrit :
>> On 3/16/21 10:01 AM, Laurent Vivier wrote:
>>> Le 15/03/2021 à 13:33, BALATON Zoltan a écrit :
>>>> On Sat, 13 Mar 2021, BALATON Zoltan wrote:
>>>>> On Wed, 10 Mar 2021, BALATON Zoltan wrote:
>>>>>> Hello,
>>>>>
>>>>> I've started posting this series well in advance to get it into 6.0 and yet it seems like it may
>>>>> be missing it due to organisational issues (no real complaints were found with patches but
>>>>> Philippe seems to like more review that does not seem to happen as nobody is interested). Looks
>>>>> like David is waiting for an ack from Philippe but will be away next week so if this is not
>>>>> resolved now it may be too late on Monday. To avoid that:
>>>>>
>>>>> David, could you please send an ack before you leave for the last two patches so it could get
>>>>> committed via some other tree while you're away?
>>>>>
>>>>> Philippe, if you can't ack the vt82c686 patches now are you OK with taking the whole series via
>>>>> your tree before the freeze? That would give you some more days to review and it could always be
>>>>> reverted during the freeze but if it's not merged now I'll have to wait until the summer to get it
>>>>> in again which would be another long delay. I don't think this will get more reviews unless it's
>>>>> in master and people can start using and testing it better.
>>>>
>>>> Hello,
>>>>
>>>> Since David seems to be away for this week before seeing my mail asking for an ack from him, now
>>>> this can only get in by Philippe or Peter. (David said before he'd be OK with the series if Philippe
>>>> acked it so I think that can count as an implicit ack and it could always be reverted before the
>>>> releease.)
>>>>
>>>> Philippe, do you have anything against this to get merged now? If not please send a pull or ack it
>>>> so it has a chance to be in 6.0 or tell if you still intend to do anything about it before the
>>>> freeze. This series was on the list since January and the remaining parts you did not take are here
>>>> since February 22nd and the version after your first review since two weeks so it would be nice to
>>>> sort this out and not block it any further without a good reason.
>>>
>>> Pegasos looks like a New World PowerMac, so perhaps Mark can help?
>>
>> The PPC part is mostly reviewed. The problem is the first patch:
>> "vt82c686: Implement control of serial port io ranges via config regs".
>
> vt82c686.c is a Fuloong 2E file, why Fuloong 2E maintainers are not involved in the review?
Philippe is MIPS maintainer and he was involved and reviewed most patches.
Huacai did not respond much and Jiaxun's email adress is constantly
stripped by the list so whenrver I add him it will be lost the next time.
He seems to be more interested in Fuloong 3 anyway so did not respond much
either.
All in all I think there's just not enough interest in these
machines/devices so my stance is that if it does not break anything just
take it now and then we'll have enough time for further review, fixing or
reverting during the freeze. Whereas if this is kept pushing back then
nothing will happen with them for the next 2-3 months then we'll be back
to here and miss the next release as well.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 0/8] Pegasos2 emulation
2021-03-16 12:24 ` BALATON Zoltan
@ 2021-03-16 12:55 ` Laurent Vivier
2021-03-16 13:06 ` BALATON Zoltan
0 siblings, 1 reply; 32+ messages in thread
From: Laurent Vivier @ 2021-03-16 12:55 UTC (permalink / raw)
To: BALATON Zoltan
Cc: Peter Maydell, Mark Cave-Ayland, Philippe Mathieu-Daudé,
qemu-devel, qemu-ppc, Paolo Bonzini, David Gibson
Le 16/03/2021 à 13:24, BALATON Zoltan a écrit :
> On Tue, 16 Mar 2021, Laurent Vivier wrote:
>> Le 16/03/2021 à 12:49, Philippe Mathieu-Daudé a écrit :
>>> On 3/16/21 10:01 AM, Laurent Vivier wrote:
>>>> Le 15/03/2021 à 13:33, BALATON Zoltan a écrit :
>>>>> On Sat, 13 Mar 2021, BALATON Zoltan wrote:
>>>>>> On Wed, 10 Mar 2021, BALATON Zoltan wrote:
>>>>>>> Hello,
>>>>>>
>>>>>> I've started posting this series well in advance to get it into 6.0 and yet it seems like it may
>>>>>> be missing it due to organisational issues (no real complaints were found with patches but
>>>>>> Philippe seems to like more review that does not seem to happen as nobody is interested). Looks
>>>>>> like David is waiting for an ack from Philippe but will be away next week so if this is not
>>>>>> resolved now it may be too late on Monday. To avoid that:
>>>>>>
>>>>>> David, could you please send an ack before you leave for the last two patches so it could get
>>>>>> committed via some other tree while you're away?
>>>>>>
>>>>>> Philippe, if you can't ack the vt82c686 patches now are you OK with taking the whole series via
>>>>>> your tree before the freeze? That would give you some more days to review and it could always be
>>>>>> reverted during the freeze but if it's not merged now I'll have to wait until the summer to
>>>>>> get it
>>>>>> in again which would be another long delay. I don't think this will get more reviews unless it's
>>>>>> in master and people can start using and testing it better.
>>>>>
>>>>> Hello,
>>>>>
>>>>> Since David seems to be away for this week before seeing my mail asking for an ack from him, now
>>>>> this can only get in by Philippe or Peter. (David said before he'd be OK with the series if
>>>>> Philippe
>>>>> acked it so I think that can count as an implicit ack and it could always be reverted before the
>>>>> releease.)
>>>>>
>>>>> Philippe, do you have anything against this to get merged now? If not please send a pull or ack it
>>>>> so it has a chance to be in 6.0 or tell if you still intend to do anything about it before the
>>>>> freeze. This series was on the list since January and the remaining parts you did not take are
>>>>> here
>>>>> since February 22nd and the version after your first review since two weeks so it would be nice to
>>>>> sort this out and not block it any further without a good reason.
>>>>
>>>> Pegasos looks like a New World PowerMac, so perhaps Mark can help?
>>>
>>> The PPC part is mostly reviewed. The problem is the first patch:
>>> "vt82c686: Implement control of serial port io ranges via config regs".
>>
>> vt82c686.c is a Fuloong 2E file, why Fuloong 2E maintainers are not involved in the review?
>
> Philippe is MIPS maintainer and he was involved and reviewed most patches. Huacai did not respond
> much and Jiaxun's email adress is constantly stripped by the list so whenrver I add him it will be
> lost the next time. He seems to be more interested in Fuloong 3 anyway so did not respond much either.
>
> All in all I think there's just not enough interest in these machines/devices so my stance is that
> if it does not break anything just take it now and then we'll have enough time for further review,
> fixing or reverting during the freeze. Whereas if this is kept pushing back then nothing will happen
> with them for the next 2-3 months then we'll be back to here and miss the next release as well.
The PATCH 1 doesn't seem to be needed to have a working Pegasos 2 machine, does it?
If the problem is only with the first patch perhaps you can remove it to have it merged and come
back later with a cleaner implementation (it is presented to be a hack)?
I think PATCH 6 can already be merged, and PATCH 2 can be done outside of the series as a pre-requisite.
Then it will be easier to manage a series only adding devices for your new machine.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 0/8] Pegasos2 emulation
2021-03-16 12:55 ` Laurent Vivier
@ 2021-03-16 13:06 ` BALATON Zoltan
2021-03-16 16:21 ` Mark Cave-Ayland
0 siblings, 1 reply; 32+ messages in thread
From: BALATON Zoltan @ 2021-03-16 13:06 UTC (permalink / raw)
To: Laurent Vivier
Cc: Peter Maydell, Philippe Mathieu-Daudé,
qemu-devel, qemu-ppc, Paolo Bonzini, David Gibson
[-- Attachment #1: Type: text/plain, Size: 4800 bytes --]
On Tue, 16 Mar 2021, Laurent Vivier wrote:
> Le 16/03/2021 à 13:24, BALATON Zoltan a écrit :
>> On Tue, 16 Mar 2021, Laurent Vivier wrote:
>>> Le 16/03/2021 à 12:49, Philippe Mathieu-Daudé a écrit :
>>>> On 3/16/21 10:01 AM, Laurent Vivier wrote:
>>>>> Le 15/03/2021 à 13:33, BALATON Zoltan a écrit :
>>>>>> On Sat, 13 Mar 2021, BALATON Zoltan wrote:
>>>>>>> On Wed, 10 Mar 2021, BALATON Zoltan wrote:
>>>>>>>> Hello,
>>>>>>>
>>>>>>> I've started posting this series well in advance to get it into 6.0 and yet it seems like it may
>>>>>>> be missing it due to organisational issues (no real complaints were found with patches but
>>>>>>> Philippe seems to like more review that does not seem to happen as nobody is interested). Looks
>>>>>>> like David is waiting for an ack from Philippe but will be away next week so if this is not
>>>>>>> resolved now it may be too late on Monday. To avoid that:
>>>>>>>
>>>>>>> David, could you please send an ack before you leave for the last two patches so it could get
>>>>>>> committed via some other tree while you're away?
>>>>>>>
>>>>>>> Philippe, if you can't ack the vt82c686 patches now are you OK with taking the whole series via
>>>>>>> your tree before the freeze? That would give you some more days to review and it could always be
>>>>>>> reverted during the freeze but if it's not merged now I'll have to wait until the summer to
>>>>>>> get it
>>>>>>> in again which would be another long delay. I don't think this will get more reviews unless it's
>>>>>>> in master and people can start using and testing it better.
>>>>>>
>>>>>> Hello,
>>>>>>
>>>>>> Since David seems to be away for this week before seeing my mail asking for an ack from him, now
>>>>>> this can only get in by Philippe or Peter. (David said before he'd be OK with the series if
>>>>>> Philippe
>>>>>> acked it so I think that can count as an implicit ack and it could always be reverted before the
>>>>>> releease.)
>>>>>>
>>>>>> Philippe, do you have anything against this to get merged now? If not please send a pull or ack it
>>>>>> so it has a chance to be in 6.0 or tell if you still intend to do anything about it before the
>>>>>> freeze. This series was on the list since January and the remaining parts you did not take are
>>>>>> here
>>>>>> since February 22nd and the version after your first review since two weeks so it would be nice to
>>>>>> sort this out and not block it any further without a good reason.
>>>>>
>>>>> Pegasos looks like a New World PowerMac, so perhaps Mark can help?
>>>>
>>>> The PPC part is mostly reviewed. The problem is the first patch:
>>>> "vt82c686: Implement control of serial port io ranges via config regs".
>>>
>>> vt82c686.c is a Fuloong 2E file, why Fuloong 2E maintainers are not involved in the review?
>>
>> Philippe is MIPS maintainer and he was involved and reviewed most patches. Huacai did not respond
>> much and Jiaxun's email adress is constantly stripped by the list so whenrver I add him it will be
>> lost the next time. He seems to be more interested in Fuloong 3 anyway so did not respond much either.
>>
>> All in all I think there's just not enough interest in these machines/devices so my stance is that
>> if it does not break anything just take it now and then we'll have enough time for further review,
>> fixing or reverting during the freeze. Whereas if this is kept pushing back then nothing will happen
>> with them for the next 2-3 months then we'll be back to here and miss the next release as well.
>
> The PATCH 1 doesn't seem to be needed to have a working Pegasos 2 machine, does it?
It is needed (as well as all other patches in the series). Patch 1 is
needed for getting serial output which is the only way to communicate with
the Pegasos2 firmware so it's really hard to boot anything without it.
> If the problem is only with the first patch perhaps you can remove it to have it merged and come
> back later with a cleaner implementation (it is presented to be a hack)?
I'll try to explain it again in another message but there's no cleaner
solution available without much more work than I want to take up. To do it
a more cleaner way ISA emulation would need to be QOM'ified that I won't
do. This solution is a hack in that it pokes the isa-serial device from a
superclass but there's no easier and cleaner way to do it so this should
be good enough for now and it has the lowest chance to break anything
else.
> I think PATCH 6 can already be merged, and PATCH 2 can be done outside of the series as a pre-requisite.
>
> Then it will be easier to manage a series only adding devices for your new machine.
It's all or nothing I'm afraid as all these pathces are needed for
pegasos2 to work so taking only a few of them won't let users use it in
6.0.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 0/8] Pegasos2 emulation
2021-03-16 13:06 ` BALATON Zoltan
@ 2021-03-16 16:21 ` Mark Cave-Ayland
2021-03-16 17:25 ` BALATON Zoltan
0 siblings, 1 reply; 32+ messages in thread
From: Mark Cave-Ayland @ 2021-03-16 16:21 UTC (permalink / raw)
To: BALATON Zoltan, Laurent Vivier
Cc: Peter Maydell, Philippe Mathieu-Daudé,
qemu-devel, qemu-ppc, Paolo Bonzini, David Gibson
On 16/03/2021 13:06, BALATON Zoltan wrote:
>> The PATCH 1 doesn't seem to be needed to have a working Pegasos 2 machine, does it?
>
> It is needed (as well as all other patches in the series). Patch 1 is needed for
> getting serial output which is the only way to communicate with the Pegasos2 firmware
> so it's really hard to boot anything without it.
Just having a quick look at patch 1: presumably the issue here is that the Pegasos 2
firmware moves the serial ports to a different address on startup. If you know what
that address is, then why not simply change the serial port base address(es) on the
SuperIO device from the default?
ATB,
Mark.
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 0/8] Pegasos2 emulation
2021-03-16 16:21 ` Mark Cave-Ayland
@ 2021-03-16 17:25 ` BALATON Zoltan
2021-03-16 20:00 ` Mark Cave-Ayland
0 siblings, 1 reply; 32+ messages in thread
From: BALATON Zoltan @ 2021-03-16 17:25 UTC (permalink / raw)
To: Mark Cave-Ayland
Cc: Peter Maydell, qemu-devel, Laurent Vivier, qemu-ppc,
Paolo Bonzini, David Gibson, Philippe Mathieu-Daudé
On Tue, 16 Mar 2021, Mark Cave-Ayland wrote:
> On 16/03/2021 13:06, BALATON Zoltan wrote:
>>> The PATCH 1 doesn't seem to be needed to have a working Pegasos 2 machine,
>>> does it?
>>
>> It is needed (as well as all other patches in the series). Patch 1 is
>> needed for getting serial output which is the only way to communicate with
>> the Pegasos2 firmware so it's really hard to boot anything without it.
>
> Just having a quick look at patch 1: presumably the issue here is that the
> Pegasos 2 firmware moves the serial ports to a different address on startup.
> If you know what that address is, then why not simply change the serial port
> base address(es) on the SuperIO device from the default?
I had that as first version but other guests may expect the serial at the
default address or set it up differently and we can emulate the device
more fully this way that works with all guests which is also more like the
device works. So putting it at a default address would be a step back. I
can attempt that if this approach cannot be used but so far nobody said
so.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 0/8] Pegasos2 emulation
2021-03-16 17:25 ` BALATON Zoltan
@ 2021-03-16 20:00 ` Mark Cave-Ayland
2021-03-16 21:49 ` BALATON Zoltan
0 siblings, 1 reply; 32+ messages in thread
From: Mark Cave-Ayland @ 2021-03-16 20:00 UTC (permalink / raw)
To: BALATON Zoltan
Cc: Peter Maydell, Philippe Mathieu-Daudé,
qemu-devel, Laurent Vivier, qemu-ppc, Paolo Bonzini,
David Gibson
On 16/03/2021 17:25, BALATON Zoltan wrote:
> On Tue, 16 Mar 2021, Mark Cave-Ayland wrote:
>> On 16/03/2021 13:06, BALATON Zoltan wrote:
>>>> The PATCH 1 doesn't seem to be needed to have a working Pegasos 2 machine, does it?
>>>
>>> It is needed (as well as all other patches in the series). Patch 1 is needed for
>>> getting serial output which is the only way to communicate with the Pegasos2
>>> firmware so it's really hard to boot anything without it.
>>
>> Just having a quick look at patch 1: presumably the issue here is that the Pegasos
>> 2 firmware moves the serial ports to a different address on startup. If you know
>> what that address is, then why not simply change the serial port base address(es)
>> on the SuperIO device from the default?
>
> I had that as first version but other guests may expect the serial at the default
> address or set it up differently and we can emulate the device more fully this way
> that works with all guests which is also more like the device works. So putting it at
> a default address would be a step back. I can attempt that if this approach cannot be
> used but so far nobody said so.
That would certainly be my first choice, as swapping out the memory regions within
the ISA bus without its knowledge is likely to cause problems (I can see ioport_id
being incorrect for one).
Do the guest OSs actually use this feature at all? I don't think I've ever seen such
registers being used within QEMU, OSs tend to simply relocate the IO space base
address using the BAR if required.
If Linux/MorphOS work with a fixed address then that's good enough for now: the code
should look something like this:
dev = qdev_new(TYPE_SUPER_IO);
serial_dev = object_resolve_path_component(OBJECT(dev), "serial0"));
qdev_prop_set_uint32(dev, "iobase", 0x1234);
qdev_realise_and_unref(dev, &error_fatal);
ATB,
Mark.
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v7 0/8] Pegasos2 emulation
2021-03-16 20:00 ` Mark Cave-Ayland
@ 2021-03-16 21:49 ` BALATON Zoltan
2021-03-16 22:12 ` BALATON Zoltan
0 siblings, 1 reply; 32+ messages in thread
From: BALATON Zoltan @ 2021-03-16 21:49 UTC (permalink / raw)
To: Mark Cave-Ayland
Cc: Peter Maydell, Philippe Mathieu-Daudé,
qemu-devel, Laurent Vivier, qemu-ppc, Paolo Bonzini,
David Gibson
On Tue, 16 Mar 2021, Mark Cave-Ayland wrote:
> On 16/03/2021 17:25, BALATON Zoltan wrote:
>> On Tue, 16 Mar 2021, Mark Cave-Ayland wrote:
>>> On 16/03/2021 13:06, BALATON Zoltan wrote:
>>>>> The PATCH 1 doesn't seem to be needed to have a working Pegasos 2
>>>>> machine, does it?
>>>>
>>>> It is needed (as well as all other patches in the series). Patch 1 is
>>>> needed for getting serial output which is the only way to communicate
>>>> with the Pegasos2 firmware so it's really hard to boot anything without
>>>> it.
>>>
>>> Just having a quick look at patch 1: presumably the issue here is that the
>>> Pegasos 2 firmware moves the serial ports to a different address on
>>> startup. If you know what that address is, then why not simply change the
>>> serial port base address(es) on the SuperIO device from the default?
>>
>> I had that as first version but other guests may expect the serial at the
>> default address or set it up differently and we can emulate the device more
>> fully this way that works with all guests which is also more like the
>> device works. So putting it at a default address would be a step back. I
>> can attempt that if this approach cannot be used but so far nobody said so.
>
> That would certainly be my first choice, as swapping out the memory regions
> within the ISA bus without its knowledge is likely to cause problems (I can
> see ioport_id being incorrect for one).
Did you check what's that used for? Unlikely to cause any problems other
than displaying initial value of port address instead of current address
in device ID but that could be argued about if an ID should change or
stay the same as initially. Easily fixable either way.
> Do the guest OSs actually use this feature at all? I don't think I've ever
> seen such registers being used within QEMU, OSs tend to simply relocate the
> IO space base address using the BAR if required.
The ISA devices don't have io BAR, they are relocatable _within_ ISA IO
space by the config registers of the VIA superio chip. But the two guests
that currently boot (MorphOS and Linux) don't seems to change default set
by the firmware so we can go with the firmware defaults which is less
correct than actually emulating what the chip does but whatever. (AmigaOS
may also boot but has no gfx driver so can't really check at the moment.)
> If Linux/MorphOS work with a fixed address then that's good enough for now:
> the code should look something like this:
>
> dev = qdev_new(TYPE_SUPER_IO);
> serial_dev = object_resolve_path_component(OBJECT(dev), "serial0"));
> qdev_prop_set_uint32(dev, "iobase", 0x1234);
> qdev_realise_and_unref(dev, &error_fatal);
I've sent a v8 dropping patch 1 and setting a default but using the
callback ISA superio has for this for that which is a bit cleaner IMO.
Could this turned into a pull request by somebody now?
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 0/8] Pegasos2 emulation
2021-03-16 21:49 ` BALATON Zoltan
@ 2021-03-16 22:12 ` BALATON Zoltan
0 siblings, 0 replies; 32+ messages in thread
From: BALATON Zoltan @ 2021-03-16 22:12 UTC (permalink / raw)
To: Mark Cave-Ayland
Cc: Peter Maydell, Philippe Mathieu-Daudé,
qemu-devel, qemu-ppc, Paolo Bonzini, David Gibson
On Tue, 16 Mar 2021, BALATON Zoltan wrote:
> On Tue, 16 Mar 2021, Mark Cave-Ayland wrote:
>> On 16/03/2021 17:25, BALATON Zoltan wrote:
>>> On Tue, 16 Mar 2021, Mark Cave-Ayland wrote:
>>>> On 16/03/2021 13:06, BALATON Zoltan wrote:
>>>>>> The PATCH 1 doesn't seem to be needed to have a working Pegasos 2
>>>>>> machine, does it?
>>>>>
>>>>> It is needed (as well as all other patches in the series). Patch 1 is
>>>>> needed for getting serial output which is the only way to communicate
>>>>> with the Pegasos2 firmware so it's really hard to boot anything without
>>>>> it.
>>>>
>>>> Just having a quick look at patch 1: presumably the issue here is that
>>>> the Pegasos 2 firmware moves the serial ports to a different address on
>>>> startup. If you know what that address is, then why not simply change the
>>>> serial port base address(es) on the SuperIO device from the default?
>>>
>>> I had that as first version but other guests may expect the serial at the
>>> default address or set it up differently and we can emulate the device
>>> more fully this way that works with all guests which is also more like the
>>> device works. So putting it at a default address would be a step back. I
>>> can attempt that if this approach cannot be used but so far nobody said
>>> so.
>>
>> That would certainly be my first choice, as swapping out the memory regions
>> within the ISA bus without its knowledge is likely to cause problems (I can
>> see ioport_id being incorrect for one).
>
> Did you check what's that used for? Unlikely to cause any problems other than
> displaying initial value of port address instead of current address in device
> ID but that could be argued about if an ID should change or stay the same as
> initially. Easily fixable either way.
>
>> Do the guest OSs actually use this feature at all? I don't think I've ever
>> seen such registers being used within QEMU, OSs tend to simply relocate the
>> IO space base address using the BAR if required.
>
> The ISA devices don't have io BAR, they are relocatable _within_ ISA IO space
> by the config registers of the VIA superio chip. But the two guests that
> currently boot (MorphOS and Linux) don't seems to change default set by the
> firmware so we can go with the firmware defaults which is less correct than
> actually emulating what the chip does but whatever. (AmigaOS may also boot
> but has no gfx driver so can't really check at the moment.)
>
>> If Linux/MorphOS work with a fixed address then that's good enough for now:
>> the code should look something like this:
>>
>> dev = qdev_new(TYPE_SUPER_IO);
>> serial_dev = object_resolve_path_component(OBJECT(dev), "serial0"));
>> qdev_prop_set_uint32(dev, "iobase", 0x1234);
>> qdev_realise_and_unref(dev, &error_fatal);
>
> I've sent a v8 dropping patch 1 and setting a default but using the callback
And v9 replacing patch 5 with latest that applies on master that has
changed while I was sending the previous version...
> ISA superio has for this for that which is a bit cleaner IMO.
>
> Could this turned into a pull request by somebody now?
>
> Regards,
> BALATON Zoltan
>
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 0/8] Pegasos2 emulation
2021-03-16 11:49 ` Philippe Mathieu-Daudé
2021-03-16 12:11 ` Laurent Vivier
@ 2021-03-16 14:17 ` BALATON Zoltan
2021-03-16 14:48 ` BALATON Zoltan
2 siblings, 0 replies; 32+ messages in thread
From: BALATON Zoltan @ 2021-03-16 14:17 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, Mark Cave-Ayland, Laurent Vivier, qemu-devel,
qemu-ppc, Paolo Bonzini, David Gibson
[-- Attachment #1: Type: text/plain, Size: 4407 bytes --]
On Tue, 16 Mar 2021, Philippe Mathieu-Daudé wrote:
> On 3/16/21 10:01 AM, Laurent Vivier wrote:
>> Le 15/03/2021 à 13:33, BALATON Zoltan a écrit :
>>> On Sat, 13 Mar 2021, BALATON Zoltan wrote:
>>>> On Wed, 10 Mar 2021, BALATON Zoltan wrote:
>>>>> Hello,
>>>>
>>>> I've started posting this series well in advance to get it into 6.0 and yet it seems like it may
>>>> be missing it due to organisational issues (no real complaints were found with patches but
>>>> Philippe seems to like more review that does not seem to happen as nobody is interested). Looks
>>>> like David is waiting for an ack from Philippe but will be away next week so if this is not
>>>> resolved now it may be too late on Monday. To avoid that:
>>>>
>>>> David, could you please send an ack before you leave for the last two patches so it could get
>>>> committed via some other tree while you're away?
>>>>
>>>> Philippe, if you can't ack the vt82c686 patches now are you OK with taking the whole series via
>>>> your tree before the freeze? That would give you some more days to review and it could always be
>>>> reverted during the freeze but if it's not merged now I'll have to wait until the summer to get it
>>>> in again which would be another long delay. I don't think this will get more reviews unless it's
>>>> in master and people can start using and testing it better.
>>>
>>> Hello,
>>>
>>> Since David seems to be away for this week before seeing my mail asking for an ack from him, now
>>> this can only get in by Philippe or Peter. (David said before he'd be OK with the series if Philippe
>>> acked it so I think that can count as an implicit ack and it could always be reverted before the
>>> releease.)
>>>
>>> Philippe, do you have anything against this to get merged now? If not please send a pull or ack it
>>> so it has a chance to be in 6.0 or tell if you still intend to do anything about it before the
>>> freeze. This series was on the list since January and the remaining parts you did not take are here
>>> since February 22nd and the version after your first review since two weeks so it would be nice to
>>> sort this out and not block it any further without a good reason.
>>
>> Pegasos looks like a New World PowerMac, so perhaps Mark can help?
>
> The PPC part is mostly reviewed. The problem is the first patch:
> "vt82c686: Implement control of serial port io ranges via config regs".
>
> I don't understand it. Zoltan said Paolo isn't acking it because
> he doesn't mind. I prefer to be cautious and think than Paolo is
> rather too busy.
Can you just send a pull request then and Paolo could nack it or comment
on that. If he does not, then this should be OK as it does not touch
anything else than vt82c686 so it also should not break anything else.
Basically what the patch does is have a via-superio class that inherits
from TYPE_ISA_SUPERIO that creates the ISA devices, among others
isa-serial ports. Then the device grabs the memory regions for these
serial devices to be able to change their state and address on config
register writes. It only does that for serial devices not for parallel and
floppy because those have more than one memory region and would not be
easy to handle so those are not configurable but left at their default
address. We need configurability for serial port because on pegasos2
there's only one serial port and it's set to a non-standard address by the
firmware. Fuloong2e used to put these at default address and the firmware
did not touch it, we now more properly emulate the chip and allow changing
the address which the firmware leaves at the default but on pegasos that
would not work.
The resulting model is not so bad as we only access memory region owned by
child device (via-superio sets memory region of isa-serial that's created
by its superclass isa superio and this is only needed because there's no
other interface and one cannot be easily added without possibly breaking
something due to other ISA devices that have multiple memory regions). So
I think this is the simplest and least invasive solution that shoul be
enough for now until ISA device emulation is QOM'ified which is a task I
don't want to take up as it's way more work I'd put in and has a
possibility to break stuff I don't have a way or time to test so unless
somebody does that there's no other easy way to solve this problem.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 0/8] Pegasos2 emulation
2021-03-16 11:49 ` Philippe Mathieu-Daudé
2021-03-16 12:11 ` Laurent Vivier
2021-03-16 14:17 ` BALATON Zoltan
@ 2021-03-16 14:48 ` BALATON Zoltan
2 siblings, 0 replies; 32+ messages in thread
From: BALATON Zoltan @ 2021-03-16 14:48 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, Mark Cave-Ayland, Laurent Vivier, qemu-devel,
qemu-ppc, Paolo Bonzini, David Gibson
Another arrempt to explain patch 1. This is the via-superio class that's a
subclass of ISA superio:
https://github.com/patchew-project/qemu/blob/ca5d88d2fee0016f939e91ae8b32c18e682064fa/hw/isa/vt82c686.c#L255
#define TYPE_VIA_SUPERIO "via-superio"
OBJECT_DECLARE_SIMPLE_TYPE(ViaSuperIOState, VIA_SUPERIO)
struct ViaSuperIOState {
ISASuperIODevice superio;
uint8_t regs[0x100];
const MemoryRegionOps *io_ops;
MemoryRegion io;
MemoryRegion *serial_io[SUPERIO_MAX_SERIAL_PORTS];
};
[...]
static void via_superio_realize(DeviceState *d, Error **errp)
{
ViaSuperIOState *s = VIA_SUPERIO(d);
ISASuperIOClass *ic = ISA_SUPERIO_GET_CLASS(s);
Error *local_err = NULL;
int i;
assert(s->io_ops);
ic->parent_realize(d, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
/* Grab io regions of serial devices so we can control them */
for (i = 0; i < ic->serial.count; i++) {
ISADevice *sd = s->superio.serial[i];
MemoryRegion *io = isa_address_space_io(sd);
MemoryRegion *mr = find_subregion(sd, io, sd->ioport_id);
if (!mr) {
error_setg(errp, "Could not get io region for serial %d", i);
return;
}
s->serial_io[i] = mr;
}
memory_region_init_io(&s->io, OBJECT(d), s->io_ops, s, "via-superio", 2);
memory_region_set_enabled(&s->io, false);
/* The floppy also uses 0x3f0 and 0x3f1 but this seems to work anyway */
memory_region_add_subregion(isa_address_space_io(ISA_DEVICE(s)), 0x3f0,
&s->io);
}
In realize we grab pointers to the MemoryRegions of the isa-serial devices
created by the ISA superio class. This is ISA superio:
https://github.com/patchew-project/qemu/blob/ca5d88d2fee0016f939e91ae8b32c18e682064fa/include/hw/isa/superio.h#L23
#define SUPERIO_MAX_SERIAL_PORTS 4
struct ISASuperIODevice {
/*< private >*/
ISADevice parent_obj;
/*< public >*/
ISADevice *parallel[MAX_PARALLEL_PORTS];
ISADevice *serial[SUPERIO_MAX_SERIAL_PORTS];
ISADevice *floppy;
ISADevice *kbc;
ISADevice *ide;
};
The serial members we access are even public so this should be OK (other
models to that too) but we need to get their MemoryRegion as we need to
configure that based on VIA superio registers. ISADevice is defined in:
https://github.com/patchew-project/qemu/blob/patchew/cover.1615345138.git.balaton%40eik.bme.hu/include/hw/isa/isa.h
but it does not store a reference to its memory regions:
struct ISADevice {
/*< private >*/
DeviceState parent_obj;
/*< public >*/
int8_t isairq[2]; /* -1 = unassigned */
int nirqs;
int ioport_id;
};
only an ioport_id which is the address of its first io region so we have
to get the actual MemoryRegion based on that. This works for isa-serial
that has a single mem region but would not for parallel or FDC that have
multiple regions. Those are created with isa_register_portio_list() I
think but we don't care about parallel and FDC only about serial.
This may be possible to clean up but that would need changes to ISA
emulation that I don't want to change so the patch tries to achieve what's
needed without changing how ISA devices are emulated currently. I think
the solution proposed in patch 1 is relatively clean and by not changing
anything than vt82c686 it avoids any possible breakage to other machines
using ISA devices so unless there's a reason not to accept it this should
solve the problem and allow pegasos2 firmware to boot.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v7 0/8] Pegasos2 emulation
2021-03-16 9:01 ` Laurent Vivier
2021-03-16 11:49 ` Philippe Mathieu-Daudé
@ 2021-03-16 12:21 ` BALATON Zoltan
1 sibling, 0 replies; 32+ messages in thread
From: BALATON Zoltan @ 2021-03-16 12:21 UTC (permalink / raw)
To: Laurent Vivier
Cc: Peter Maydell, Mark Cave-Ayland, f4bug, qemu-devel, qemu-ppc,
Paolo Bonzini, Philippe Mathieu-Daudé,
David Gibson
[-- Attachment #1: Type: text/plain, Size: 2715 bytes --]
On Tue, 16 Mar 2021, Laurent Vivier wrote:
> Le 15/03/2021 à 13:33, BALATON Zoltan a écrit :
>> On Sat, 13 Mar 2021, BALATON Zoltan wrote:
>>> On Wed, 10 Mar 2021, BALATON Zoltan wrote:
>>>> Hello,
>>>
>>> I've started posting this series well in advance to get it into 6.0 and yet it seems like it may
>>> be missing it due to organisational issues (no real complaints were found with patches but
>>> Philippe seems to like more review that does not seem to happen as nobody is interested). Looks
>>> like David is waiting for an ack from Philippe but will be away next week so if this is not
>>> resolved now it may be too late on Monday. To avoid that:
>>>
>>> David, could you please send an ack before you leave for the last two patches so it could get
>>> committed via some other tree while you're away?
>>>
>>> Philippe, if you can't ack the vt82c686 patches now are you OK with taking the whole series via
>>> your tree before the freeze? That would give you some more days to review and it could always be
>>> reverted during the freeze but if it's not merged now I'll have to wait until the summer to get it
>>> in again which would be another long delay. I don't think this will get more reviews unless it's
>>> in master and people can start using and testing it better.
>>
>> Hello,
>>
>> Since David seems to be away for this week before seeing my mail asking for an ack from him, now
>> this can only get in by Philippe or Peter. (David said before he'd be OK with the series if Philippe
>> acked it so I think that can count as an implicit ack and it could always be reverted before the
>> releease.)
>>
>> Philippe, do you have anything against this to get merged now? If not please send a pull or ack it
>> so it has a chance to be in 6.0 or tell if you still intend to do anything about it before the
>> freeze. This series was on the list since January and the remaining parts you did not take are here
>> since February 22nd and the version after your first review since two weeks so it would be nice to
>> sort this out and not block it any further without a good reason.
>
> Pegasos looks like a New World PowerMac, so perhaps Mark can help?
The pegasos2 is more like a MIPS machine or a PC with a PPC than a
PowerMac at the hardware level even if it implements similar specs like
PowerMacs so not sure how much knowledge about Macs would help here.
Besides we had a disagreement with Mark about what level of perfectness is
needed for new QEMU devices so he stayed away from these. That said if
anyone has a comment feel free to share, it probably has missed 6.0 now
anyway. But I'll try to do everything needed to squeeze it in if that's
still possible.
Regards,
BALATON Zoltan
^ permalink raw reply [flat|nested] 32+ messages in thread