* [PATCH v3 0/8] drm/msm: add support for SM8450 @ 2022-11-04 13:03 ` Dmitry Baryshkov 0 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-04 13:03 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno This adds support for the MDSS/DPU/DSI on the Qualcomm SM8450 platform. Dependencies for the DT bindings: [1]. [1] https://lore.kernel.org/all/20221024164225.3236654-1-dmitry.baryshkov@linaro.org/ Change since v2: - Rebased onto msm-next-lumag - Cleaned up bindings according to Krzysztof's suggestions Change since v1: - Fixed the regdma pointer in sm8450_dpu_cfg - Rebased onto pending msm-next-lumag - Added DT bindings for corresponding devices Dmitry Baryshkov (8): dt-bindings: display/msm/dsi-controller-main: allow defining opp-table dt-bindings: display/msm: add sm8350 and sm8450 DSI PHYs dt-bindings: display/msm: add support for the display on SM8450 drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450 drm/msm/dsi: add support for DSI 2.6.0 drm/msm/dpu: add support for MDP_TOP blackhole drm/msm/dpu: add support for SM8450 drm/msm: mdss: add support for SM8450 .../display/msm/dsi-controller-main.yaml | 3 + .../bindings/display/msm/dsi-phy-7nm.yaml | 2 + .../bindings/display/msm/qcom,sm8450-dpu.yaml | 132 +++++++ .../display/msm/qcom,sm8450-mdss.yaml | 347 ++++++++++++++++++ drivers/gpu/drm/msm/Kconfig | 6 +- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 224 +++++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 12 +- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 + drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 128 ++++++- drivers/gpu/drm/msm/msm_mdss.c | 5 + 15 files changed, 858 insertions(+), 15 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml -- 2.35.1 ^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v3 0/8] drm/msm: add support for SM8450 @ 2022-11-04 13:03 ` Dmitry Baryshkov 0 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-04 13:03 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, freedreno This adds support for the MDSS/DPU/DSI on the Qualcomm SM8450 platform. Dependencies for the DT bindings: [1]. [1] https://lore.kernel.org/all/20221024164225.3236654-1-dmitry.baryshkov@linaro.org/ Change since v2: - Rebased onto msm-next-lumag - Cleaned up bindings according to Krzysztof's suggestions Change since v1: - Fixed the regdma pointer in sm8450_dpu_cfg - Rebased onto pending msm-next-lumag - Added DT bindings for corresponding devices Dmitry Baryshkov (8): dt-bindings: display/msm/dsi-controller-main: allow defining opp-table dt-bindings: display/msm: add sm8350 and sm8450 DSI PHYs dt-bindings: display/msm: add support for the display on SM8450 drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450 drm/msm/dsi: add support for DSI 2.6.0 drm/msm/dpu: add support for MDP_TOP blackhole drm/msm/dpu: add support for SM8450 drm/msm: mdss: add support for SM8450 .../display/msm/dsi-controller-main.yaml | 3 + .../bindings/display/msm/dsi-phy-7nm.yaml | 2 + .../bindings/display/msm/qcom,sm8450-dpu.yaml | 132 +++++++ .../display/msm/qcom,sm8450-mdss.yaml | 347 ++++++++++++++++++ drivers/gpu/drm/msm/Kconfig | 6 +- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 224 +++++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 12 +- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 + drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 128 ++++++- drivers/gpu/drm/msm/msm_mdss.c | 5 + 15 files changed, 858 insertions(+), 15 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml -- 2.35.1 ^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v3 1/8] dt-bindings: display/msm/dsi-controller-main: allow defining opp-table 2022-11-04 13:03 ` Dmitry Baryshkov @ 2022-11-04 13:03 ` Dmitry Baryshkov -1 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-04 13:03 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Krzysztof Kozlowski Allow defining DSI OPP table inside the DSI controller node. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- .../devicetree/bindings/display/msm/dsi-controller-main.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index 3b609c19e0bc..c37dd9503da0 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -80,6 +80,9 @@ properties: operating-points-v2: true + opp-table: + type: object + ports: $ref: "/schemas/graph.yaml#/properties/ports" description: | -- 2.35.1 ^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 1/8] dt-bindings: display/msm/dsi-controller-main: allow defining opp-table @ 2022-11-04 13:03 ` Dmitry Baryshkov 0 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-04 13:03 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Krzysztof Kozlowski, freedreno Allow defining DSI OPP table inside the DSI controller node. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- .../devicetree/bindings/display/msm/dsi-controller-main.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index 3b609c19e0bc..c37dd9503da0 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -80,6 +80,9 @@ properties: operating-points-v2: true + opp-table: + type: object + ports: $ref: "/schemas/graph.yaml#/properties/ports" description: | -- 2.35.1 ^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 2/8] dt-bindings: display/msm: add sm8350 and sm8450 DSI PHYs 2022-11-04 13:03 ` Dmitry Baryshkov @ 2022-11-04 13:03 ` Dmitry Baryshkov -1 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-04 13:03 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Krzysztof Kozlowski SM8350 and SM8450 platforms use the same driver and same bindings as the existing 7nm DSI PHYs. Add corresponding compatibility strings. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml index c851770bbdf2..bffd161fedfd 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml @@ -15,6 +15,8 @@ allOf: properties: compatible: enum: + - qcom,dsi-phy-5nm-8350 + - qcom,dsi-phy-5nm-8450 - qcom,dsi-phy-7nm - qcom,dsi-phy-7nm-8150 - qcom,sc7280-dsi-phy-7nm -- 2.35.1 ^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 2/8] dt-bindings: display/msm: add sm8350 and sm8450 DSI PHYs @ 2022-11-04 13:03 ` Dmitry Baryshkov 0 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-04 13:03 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Krzysztof Kozlowski, freedreno SM8350 and SM8450 platforms use the same driver and same bindings as the existing 7nm DSI PHYs. Add corresponding compatibility strings. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml index c851770bbdf2..bffd161fedfd 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml @@ -15,6 +15,8 @@ allOf: properties: compatible: enum: + - qcom,dsi-phy-5nm-8350 + - qcom,dsi-phy-5nm-8450 - qcom,dsi-phy-7nm - qcom,dsi-phy-7nm-8150 - qcom,sc7280-dsi-phy-7nm -- 2.35.1 ^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 3/8] dt-bindings: display/msm: add support for the display on SM8450 2022-11-04 13:03 ` Dmitry Baryshkov @ 2022-11-04 13:03 ` Dmitry Baryshkov -1 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-04 13:03 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- .../bindings/display/msm/qcom,sm8450-dpu.yaml | 132 +++++++ .../display/msm/qcom,sm8450-mdss.yaml | 347 ++++++++++++++++++ 2 files changed, 479 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml new file mode 100644 index 000000000000..090a6506c8e9 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8450 Display DPU + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sm8450-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display hf axi + - description: Display sf axi + - description: Display ahb + - description: Display lut + - description: Display core + - description: Display vsync + + clock-names: + items: + - const: bus + - const: nrt_bus + - const: iface + - const: lut + - const: core + - const: vsync + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8450-dispcc.h> + #include <dt-bindings/clock/qcom,gcc-sm8450.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sm8450.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-controller@ae01000 { + compatible = "qcom,sm8450-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-172000000{ + opp-hz = /bits/ 64 <172000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml new file mode 100644 index 000000000000..9b6e1e03dc78 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml @@ -0,0 +1,347 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8450 Display MDSS + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +description: + SM8450 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like + DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sm8450-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display sf AXI + - description: Display core + + clock-names: + items: + - const: iface + - const: bus + - const: nrt_bus + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm8450-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,dsi-phy-5nm-8450 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8450-dispcc.h> + #include <dt-bindings/clock/qcom,gcc-sm8450.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sm8450.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@ae00000 { + compatible = "qcom,sm8450-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, + <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x2800 0x402>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sm8450-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-172000000{ + opp-hz = /bits/ 64 <172000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160310000{ + opp-hz = /bits/ 64 <160310000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-5nm-8450"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94900 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + + dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x0ae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-5nm-8450"; + reg = <0x0ae96400 0x200>, + <0x0ae96600 0x280>, + <0x0ae96900 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + }; +... -- 2.35.1 ^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 3/8] dt-bindings: display/msm: add support for the display on SM8450 @ 2022-11-04 13:03 ` Dmitry Baryshkov 0 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-04 13:03 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, freedreno Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- .../bindings/display/msm/qcom,sm8450-dpu.yaml | 132 +++++++ .../display/msm/qcom,sm8450-mdss.yaml | 347 ++++++++++++++++++ 2 files changed, 479 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml new file mode 100644 index 000000000000..090a6506c8e9 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8450 Display DPU + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sm8450-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display hf axi + - description: Display sf axi + - description: Display ahb + - description: Display lut + - description: Display core + - description: Display vsync + + clock-names: + items: + - const: bus + - const: nrt_bus + - const: iface + - const: lut + - const: core + - const: vsync + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8450-dispcc.h> + #include <dt-bindings/clock/qcom,gcc-sm8450.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sm8450.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-controller@ae01000 { + compatible = "qcom,sm8450-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-172000000{ + opp-hz = /bits/ 64 <172000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml new file mode 100644 index 000000000000..9b6e1e03dc78 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml @@ -0,0 +1,347 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8450 Display MDSS + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +description: + SM8450 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like + DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sm8450-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display sf AXI + - description: Display core + + clock-names: + items: + - const: iface + - const: bus + - const: nrt_bus + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm8450-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,dsi-phy-5nm-8450 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8450-dispcc.h> + #include <dt-bindings/clock/qcom,gcc-sm8450.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sm8450.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@ae00000 { + compatible = "qcom,sm8450-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, + <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x2800 0x402>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sm8450-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-172000000{ + opp-hz = /bits/ 64 <172000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160310000{ + opp-hz = /bits/ 64 <160310000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-5nm-8450"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94900 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + + dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x0ae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-5nm-8450"; + reg = <0x0ae96400 0x200>, + <0x0ae96600 0x280>, + <0x0ae96900 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + }; +... -- 2.35.1 ^ permalink raw reply related [flat|nested] 62+ messages in thread
* Re: [PATCH v3 3/8] dt-bindings: display/msm: add support for the display on SM8450 2022-11-04 13:03 ` Dmitry Baryshkov @ 2022-11-04 17:54 ` Rob Herring -1 siblings, 0 replies; 62+ messages in thread From: Rob Herring @ 2022-11-04 17:54 UTC (permalink / raw) To: Dmitry Baryshkov Cc: Sean Paul, linux-arm-msm, Rob Clark, Rob Herring, Daniel Vetter, freedreno, dri-devel, Andy Gross, Konrad Dybcio, Krzysztof Kozlowski, Stephen Boyd, David Airlie, devicetree, Abhinav Kumar, Bjorn Andersson On Fri, 04 Nov 2022 16:03:19 +0300, Dmitry Baryshkov wrote: > Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm > SM8450 platform. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > .../bindings/display/msm/qcom,sm8450-dpu.yaml | 132 +++++++ > .../display/msm/qcom,sm8450-mdss.yaml | 347 ++++++++++++++++++ > 2 files changed, 479 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml > create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: ./Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/display/msm/mdss-common.yaml ./Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/display/msm/dpu-common.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.example.dtb: display-controller@ae01000: False schema does not allow {'compatible': ['qcom,sm8450-dpu'], 'reg': [[182456320, 585728], [183173120, 8200]], 'reg-names': ['mdp', 'vbif'], 'clocks': [[4294967295, 28], [4294967295, 29], [4294967295, 1], [4294967295, 63], [4294967295, 60], [4294967295, 75]], 'clock-names': ['bus', 'nrt_bus', 'iface', 'lut', 'core', 'vsync'], 'assigned-clocks': [[4294967295, 75]], 'assigned-clock-rates': [[19200000]], 'operating-points-v2': [[1]], 'power-domains': [[4294967295, 6]], 'interrupts': [[0]], 'ports': {'#address-cells': [[1]], '#size-cells': [[0]], 'port@0': {'reg': [[0]], 'endpoint': {'remote-endpoint': [[4294967295]]}}, 'port@1': {'reg': [[1]], 'endpoint': {'remote-endpoint': [[4294967295]]}}}, 'opp-table': {'compatible': ['operating-points-v2'], 'phandle': [[1]], 'opp-172000000': {'opp-hz': [[0], [172000000]], 'required-opps': [[4294967295]]}, 'o pp-200000000': {'opp-hz': [[0], [200000000]], 'required-opps': [[4294967295]]}, 'opp-325000000': {'opp-hz': [[0], [325000000]], 'required-opps': [[4294967295]]}, 'opp-375000000': {'opp-hz': [[0], [375000000]], 'required-opps': [[4294967295]]}, 'opp-500000000': {'opp-hz': [[0], [500000000]], 'required-opps': [[4294967295]]}}, '$nodename': ['display-controller@ae01000']} From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.example.dtb: display-controller@ae01000: Unevaluated properties are not allowed ('interrupts', 'operating-points-v2', 'opp-table', 'ports', 'power-domains' were unexpected) From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.example.dtb: display-subsystem@ae00000: False schema does not allow {'compatible': ['qcom,sm8450-mdss'], 'reg': [[182452224, 4096]], 'reg-names': ['mdss'], 'interconnects': [[4294967295, 14, 0, 4294967295, 3, 0], [4294967295, 14, 0, 4294967295, 3, 0]], 'interconnect-names': ['mdp0-mem', 'mdp1-mem'], 'resets': [[4294967295, 0]], 'power-domains': [[4294967295, 0]], 'clocks': [[4294967295, 1], [4294967295, 28], [4294967295, 29], [4294967295, 60]], 'clock-names': ['iface', 'bus', 'nrt_bus', 'core'], 'interrupts': [[0, 83, 4]], 'interrupt-controller': True, '#interrupt-cells': [[1]], 'iommus': [[4294967295, 10240, 1026]], '#address-cells': [[1]], '#size-cells': [[1]], 'ranges': True, 'display-controller@ae01000': {'compatible': ['qcom,sm8450-dpu'], 'reg': [[182456320, 585728], [183173120, 8200]], 'reg-names': ['mdp', 'vbif'], 'clocks': [[4294967295, 28], [4294967295, 29], [4294967295, 1], [4294967295, 63], [4294967295, 60], [4294967295, 75]], 'clock-names': ['bus', 'nrt_bus', 'iface', 'lut', 'core', 'vsync'], 'assigned-clocks': [[4294967295, 75]], 'assigned-clock-rates': [[19200000]], 'operating-points-v2': [[1]], 'power-domains': [[4294967295, 6]], 'interrupts': [[0]], 'ports': {'#address-cells': [[1]], '#size-cells': [[0]], 'port@0': {'reg': [[0]], 'endpoint': {'remote-endpoint': [[2]], 'phandle': [[6]]}}, 'port@1': {'reg': [[1]], 'endpoint': {'remote-endpoint': [[3]], 'phandle': [[8]]}}}, 'opp-table': {'compatible': ['operating-points-v2'], 'phandle': [[1]], 'opp-172000000': {'opp-hz': [[0], [172000000]], 'required-opps': [[4294967295]]}, 'opp-200000000': {'opp-hz': [[0], [200000000]], 'required-opps': [[4294967295]]}, 'opp-325000000': {'opp-hz': [[0], [325000000]], 'required-opps': [[4294967295]]}, 'opp-375000000': {'opp-hz': [[0], [375000000]], 'required-opps': [[4294967295]]}, 'opp-500000000': {'opp-hz': [[0], [500000000]], 'required-opps': [[4294967295]]}}}, ' dsi@ae94000': {'compatible': ['qcom,mdss-dsi-ctrl'], 'reg': [[183058432, 1024]], 'reg-names': ['dsi_ctrl'], 'interrupts': [[4]], 'clocks': [[4294967295, 3], [4294967295, 6], [4294967295, 65], [4294967295, 55], [4294967295, 1], [4294967295, 28]], 'clock-names': ['byte', 'byte_intf', 'pixel', 'core', 'iface', 'bus'], 'assigned-clocks': [[4294967295, 4], [4294967295, 66]], 'assigned-clock-parents': [[4, 0], [4, 1]], 'operating-points-v2': [[5]], 'power-domains': [[4294967295, 6]], 'phys': [[4]], 'phy-names': ['dsi'], '#address-cells': [[1]], '#size-cells': [[0]], 'ports': {'#address-cells': [[1]], '#size-cells': [[0]], 'port@0': {'reg': [[0]], 'endpoint': {'remote-endpoint': [[6]], 'phandle': [[2]]}}, 'port@1': {'reg': [[1]], 'endpoint': {}}}, 'opp-table': {'compatible': ['operating-points-v2'], 'phandle': [[5]], 'opp-160310000': {'opp-hz': [[0], [160310000]], 'required-opps': [[4294967295]]}, 'opp-187500000': {'opp-hz': [[0], [187500000]], 'required-opps': [[4294967295]]}, 'opp-300000 000': {'opp-hz': [[0], [300000000]], 'required-opps': [[4294967295]]}, 'opp-358000000': {'opp-hz': [[0], [358000000]], 'required-opps': [[4294967295]]}}}, 'phy@ae94400': {'compatible': ['qcom,dsi-phy-5nm-8450'], 'reg': [[183059456, 512], [183059968, 640], [183060736, 608]], 'reg-names': ['dsi_phy', 'dsi_phy_lane', 'dsi_pll'], '#clock-cells': [[1]], '#phy-cells': [[0]], 'clocks': [[4294967295, 1], [4294967295, 0]], 'clock-names': ['iface', 'ref'], 'vdds-supply': [[4294967295]], 'phandle': [[4]]}, 'dsi@ae96000': {'compatible': ['qcom,mdss-dsi-ctrl'], 'reg': [[183066624, 1024]], 'reg-names': ['dsi_ctrl'], 'interrupts': [[5]], 'clocks': [[4294967295, 7], [4294967295, 10], [4294967295, 67], [4294967295, 57], [4294967295, 1], [4294967295, 28]], 'clock-names': ['byte', 'byte_intf', 'pixel', 'core', 'iface', 'bus'], 'assigned-clocks': [[4294967295, 8], [4294967295, 68]], 'assigned-clock-parents': [[7, 0], [7, 1]], 'operating-points-v2': [[5]], 'power-domains': [[4294967295, 6]], 'phys': [[7 ]], 'phy-names': ['dsi'], '#address-cells': [[1]], '#size-cells': [[0]], 'ports': {'#address-cells': [[1]], '#size-cells': [[0]], 'port@0': {'reg': [[0]], 'endpoint': {'remote-endpoint': [[8]], 'phandle': [[3]]}}, 'port@1': {'reg': [[1]], 'endpoint': {}}}}, 'phy@ae96400': {'compatible': ['qcom,dsi-phy-5nm-8450'], 'reg': [[183067648, 512], [183068160, 640], [183068928, 608]], 'reg-names': ['dsi_phy', 'dsi_phy_lane', 'dsi_pll'], '#clock-cells': [[1]], '#phy-cells': [[0]], 'clocks': [[4294967295, 1], [4294967295, 0]], 'clock-names': ['iface', 'ref'], 'vdds-supply': [[4294967295]], 'phandle': [[7]]}, '$nodename': ['display-subsystem@ae00000']} From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.example.dtb: display-subsystem@ae00000: Unevaluated properties are not allowed ('#address-cells', '#interrupt-cells', '#size-cells', 'interrupt-controller', 'interrupts', 'power-domains', 'ranges', 'reg', 'reg-names', 'resets' were unexpected) From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.example.dtb: display-controller@ae01000: False schema does not allow {'compatible': ['qcom,sm8450-dpu'], 'reg': [[182456320, 585728], [183173120, 8200]], 'reg-names': ['mdp', 'vbif'], 'clocks': [[4294967295, 28], [4294967295, 29], [4294967295, 1], [4294967295, 63], [4294967295, 60], [4294967295, 75]], 'clock-names': ['bus', 'nrt_bus', 'iface', 'lut', 'core', 'vsync'], 'assigned-clocks': [[4294967295, 75]], 'assigned-clock-rates': [[19200000]], 'operating-points-v2': [[1]], 'power-domains': [[4294967295, 6]], 'interrupts': [[0]], 'ports': {'#address-cells': [[1]], '#size-cells': [[0]], 'port@0': {'reg': [[0]], 'endpoint': {'remote-endpoint': [[2]], 'phandle': [[6]]}}, 'port@1': {'reg': [[1]], 'endpoint': {'remote-endpoint': [[3]], 'phandle': [[8]]}}}, 'opp-table': {'compatible': ['operating-points-v2'], 'phandle': [[1]], 'opp-172000000': {'opp-hz': [[0], [172000000]], 'required-opps': [[4294967295]]}, 'opp-200000000': {'opp-hz': [[0], [200000000]], 'required-opps': [[4294967295]]}, 'opp-325000000': {'opp-hz': [[0], [325000000]], 'required-opps': [[4294967295]]}, 'opp-375000000': {'opp-hz': [[0], [375000000]], 'required-opps': [[4294967295]]}, 'opp-500000000': {'opp-hz': [[0], [500000000]], 'required-opps': [[4294967295]]}}, '$nodename': ['display-controller@ae01000']} From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.example.dtb: display-controller@ae01000: Unevaluated properties are not allowed ('interrupts', 'operating-points-v2', 'opp-table', 'ports', 'power-domains' were unexpected) From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 3/8] dt-bindings: display/msm: add support for the display on SM8450 @ 2022-11-04 17:54 ` Rob Herring 0 siblings, 0 replies; 62+ messages in thread From: Rob Herring @ 2022-11-04 17:54 UTC (permalink / raw) To: Dmitry Baryshkov Cc: Sean Paul, devicetree, Krzysztof Kozlowski, Abhinav Kumar, linux-arm-msm, Bjorn Andersson, Konrad Dybcio, Andy Gross, dri-devel, Stephen Boyd, Rob Herring, freedreno On Fri, 04 Nov 2022 16:03:19 +0300, Dmitry Baryshkov wrote: > Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm > SM8450 platform. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > .../bindings/display/msm/qcom,sm8450-dpu.yaml | 132 +++++++ > .../display/msm/qcom,sm8450-mdss.yaml | 347 ++++++++++++++++++ > 2 files changed, 479 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml > create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: ./Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/display/msm/mdss-common.yaml ./Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/display/msm/dpu-common.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.example.dtb: display-controller@ae01000: False schema does not allow {'compatible': ['qcom,sm8450-dpu'], 'reg': [[182456320, 585728], [183173120, 8200]], 'reg-names': ['mdp', 'vbif'], 'clocks': [[4294967295, 28], [4294967295, 29], [4294967295, 1], [4294967295, 63], [4294967295, 60], [4294967295, 75]], 'clock-names': ['bus', 'nrt_bus', 'iface', 'lut', 'core', 'vsync'], 'assigned-clocks': [[4294967295, 75]], 'assigned-clock-rates': [[19200000]], 'operating-points-v2': [[1]], 'power-domains': [[4294967295, 6]], 'interrupts': [[0]], 'ports': {'#address-cells': [[1]], '#size-cells': [[0]], 'port@0': {'reg': [[0]], 'endpoint': {'remote-endpoint': [[4294967295]]}}, 'port@1': {'reg': [[1]], 'endpoint': {'remote-endpoint': [[4294967295]]}}}, 'opp-table': {'compatible': ['operating-points-v2'], 'phandle': [[1]], 'opp-172000000': {'opp-hz': [[0], [172000000]], 'required-opps': [[4294967295]]}, 'o pp-200000000': {'opp-hz': [[0], [200000000]], 'required-opps': [[4294967295]]}, 'opp-325000000': {'opp-hz': [[0], [325000000]], 'required-opps': [[4294967295]]}, 'opp-375000000': {'opp-hz': [[0], [375000000]], 'required-opps': [[4294967295]]}, 'opp-500000000': {'opp-hz': [[0], [500000000]], 'required-opps': [[4294967295]]}}, '$nodename': ['display-controller@ae01000']} From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.example.dtb: display-controller@ae01000: Unevaluated properties are not allowed ('interrupts', 'operating-points-v2', 'opp-table', 'ports', 'power-domains' were unexpected) From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.example.dtb: display-subsystem@ae00000: False schema does not allow {'compatible': ['qcom,sm8450-mdss'], 'reg': [[182452224, 4096]], 'reg-names': ['mdss'], 'interconnects': [[4294967295, 14, 0, 4294967295, 3, 0], [4294967295, 14, 0, 4294967295, 3, 0]], 'interconnect-names': ['mdp0-mem', 'mdp1-mem'], 'resets': [[4294967295, 0]], 'power-domains': [[4294967295, 0]], 'clocks': [[4294967295, 1], [4294967295, 28], [4294967295, 29], [4294967295, 60]], 'clock-names': ['iface', 'bus', 'nrt_bus', 'core'], 'interrupts': [[0, 83, 4]], 'interrupt-controller': True, '#interrupt-cells': [[1]], 'iommus': [[4294967295, 10240, 1026]], '#address-cells': [[1]], '#size-cells': [[1]], 'ranges': True, 'display-controller@ae01000': {'compatible': ['qcom,sm8450-dpu'], 'reg': [[182456320, 585728], [183173120, 8200]], 'reg-names': ['mdp', 'vbif'], 'clocks': [[4294967295, 28], [4294967295, 29], [4294967295, 1], [4294967295, 63], [4294967295, 60], [4294967295, 75]], 'clock-names': ['bus', 'nrt_bus', 'iface', 'lut', 'core', 'vsync'], 'assigned-clocks': [[4294967295, 75]], 'assigned-clock-rates': [[19200000]], 'operating-points-v2': [[1]], 'power-domains': [[4294967295, 6]], 'interrupts': [[0]], 'ports': {'#address-cells': [[1]], '#size-cells': [[0]], 'port@0': {'reg': [[0]], 'endpoint': {'remote-endpoint': [[2]], 'phandle': [[6]]}}, 'port@1': {'reg': [[1]], 'endpoint': {'remote-endpoint': [[3]], 'phandle': [[8]]}}}, 'opp-table': {'compatible': ['operating-points-v2'], 'phandle': [[1]], 'opp-172000000': {'opp-hz': [[0], [172000000]], 'required-opps': [[4294967295]]}, 'opp-200000000': {'opp-hz': [[0], [200000000]], 'required-opps': [[4294967295]]}, 'opp-325000000': {'opp-hz': [[0], [325000000]], 'required-opps': [[4294967295]]}, 'opp-375000000': {'opp-hz': [[0], [375000000]], 'required-opps': [[4294967295]]}, 'opp-500000000': {'opp-hz': [[0], [500000000]], 'required-opps': [[4294967295]]}}}, ' dsi@ae94000': {'compatible': ['qcom,mdss-dsi-ctrl'], 'reg': [[183058432, 1024]], 'reg-names': ['dsi_ctrl'], 'interrupts': [[4]], 'clocks': [[4294967295, 3], [4294967295, 6], [4294967295, 65], [4294967295, 55], [4294967295, 1], [4294967295, 28]], 'clock-names': ['byte', 'byte_intf', 'pixel', 'core', 'iface', 'bus'], 'assigned-clocks': [[4294967295, 4], [4294967295, 66]], 'assigned-clock-parents': [[4, 0], [4, 1]], 'operating-points-v2': [[5]], 'power-domains': [[4294967295, 6]], 'phys': [[4]], 'phy-names': ['dsi'], '#address-cells': [[1]], '#size-cells': [[0]], 'ports': {'#address-cells': [[1]], '#size-cells': [[0]], 'port@0': {'reg': [[0]], 'endpoint': {'remote-endpoint': [[6]], 'phandle': [[2]]}}, 'port@1': {'reg': [[1]], 'endpoint': {}}}, 'opp-table': {'compatible': ['operating-points-v2'], 'phandle': [[5]], 'opp-160310000': {'opp-hz': [[0], [160310000]], 'required-opps': [[4294967295]]}, 'opp-187500000': {'opp-hz': [[0], [187500000]], 'required-opps': [[4294967295]]}, 'opp-300000 000': {'opp-hz': [[0], [300000000]], 'required-opps': [[4294967295]]}, 'opp-358000000': {'opp-hz': [[0], [358000000]], 'required-opps': [[4294967295]]}}}, 'phy@ae94400': {'compatible': ['qcom,dsi-phy-5nm-8450'], 'reg': [[183059456, 512], [183059968, 640], [183060736, 608]], 'reg-names': ['dsi_phy', 'dsi_phy_lane', 'dsi_pll'], '#clock-cells': [[1]], '#phy-cells': [[0]], 'clocks': [[4294967295, 1], [4294967295, 0]], 'clock-names': ['iface', 'ref'], 'vdds-supply': [[4294967295]], 'phandle': [[4]]}, 'dsi@ae96000': {'compatible': ['qcom,mdss-dsi-ctrl'], 'reg': [[183066624, 1024]], 'reg-names': ['dsi_ctrl'], 'interrupts': [[5]], 'clocks': [[4294967295, 7], [4294967295, 10], [4294967295, 67], [4294967295, 57], [4294967295, 1], [4294967295, 28]], 'clock-names': ['byte', 'byte_intf', 'pixel', 'core', 'iface', 'bus'], 'assigned-clocks': [[4294967295, 8], [4294967295, 68]], 'assigned-clock-parents': [[7, 0], [7, 1]], 'operating-points-v2': [[5]], 'power-domains': [[4294967295, 6]], 'phys': [[7 ]], 'phy-names': ['dsi'], '#address-cells': [[1]], '#size-cells': [[0]], 'ports': {'#address-cells': [[1]], '#size-cells': [[0]], 'port@0': {'reg': [[0]], 'endpoint': {'remote-endpoint': [[8]], 'phandle': [[3]]}}, 'port@1': {'reg': [[1]], 'endpoint': {}}}}, 'phy@ae96400': {'compatible': ['qcom,dsi-phy-5nm-8450'], 'reg': [[183067648, 512], [183068160, 640], [183068928, 608]], 'reg-names': ['dsi_phy', 'dsi_phy_lane', 'dsi_pll'], '#clock-cells': [[1]], '#phy-cells': [[0]], 'clocks': [[4294967295, 1], [4294967295, 0]], 'clock-names': ['iface', 'ref'], 'vdds-supply': [[4294967295]], 'phandle': [[7]]}, '$nodename': ['display-subsystem@ae00000']} From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.example.dtb: display-subsystem@ae00000: Unevaluated properties are not allowed ('#address-cells', '#interrupt-cells', '#size-cells', 'interrupt-controller', 'interrupts', 'power-domains', 'ranges', 'reg', 'reg-names', 'resets' were unexpected) From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.example.dtb: display-controller@ae01000: False schema does not allow {'compatible': ['qcom,sm8450-dpu'], 'reg': [[182456320, 585728], [183173120, 8200]], 'reg-names': ['mdp', 'vbif'], 'clocks': [[4294967295, 28], [4294967295, 29], [4294967295, 1], [4294967295, 63], [4294967295, 60], [4294967295, 75]], 'clock-names': ['bus', 'nrt_bus', 'iface', 'lut', 'core', 'vsync'], 'assigned-clocks': [[4294967295, 75]], 'assigned-clock-rates': [[19200000]], 'operating-points-v2': [[1]], 'power-domains': [[4294967295, 6]], 'interrupts': [[0]], 'ports': {'#address-cells': [[1]], '#size-cells': [[0]], 'port@0': {'reg': [[0]], 'endpoint': {'remote-endpoint': [[2]], 'phandle': [[6]]}}, 'port@1': {'reg': [[1]], 'endpoint': {'remote-endpoint': [[3]], 'phandle': [[8]]}}}, 'opp-table': {'compatible': ['operating-points-v2'], 'phandle': [[1]], 'opp-172000000': {'opp-hz': [[0], [172000000]], 'required-opps': [[4294967295]]}, 'opp-200000000': {'opp-hz': [[0], [200000000]], 'required-opps': [[4294967295]]}, 'opp-325000000': {'opp-hz': [[0], [325000000]], 'required-opps': [[4294967295]]}, 'opp-375000000': {'opp-hz': [[0], [375000000]], 'required-opps': [[4294967295]]}, 'opp-500000000': {'opp-hz': [[0], [500000000]], 'required-opps': [[4294967295]]}}, '$nodename': ['display-controller@ae01000']} From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.example.dtb: display-controller@ae01000: Unevaluated properties are not allowed ('interrupts', 'operating-points-v2', 'opp-table', 'ports', 'power-domains' were unexpected) From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 3/8] dt-bindings: display/msm: add support for the display on SM8450 2022-11-04 13:03 ` Dmitry Baryshkov @ 2022-11-08 11:02 ` Krzysztof Kozlowski -1 siblings, 0 replies; 62+ messages in thread From: Krzysztof Kozlowski @ 2022-11-08 11:02 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno On 04/11/2022 14:03, Dmitry Baryshkov wrote: > Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm > SM8450 platform. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > .../bindings/display/msm/qcom,sm8450-dpu.yaml | 132 +++++++ > .../display/msm/qcom,sm8450-mdss.yaml | 347 ++++++++++++++++++ > 2 files changed, 479 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml > create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml > > diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml > new file mode 100644 > index 000000000000..090a6506c8e9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml > @@ -0,0 +1,132 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm SM8450 Display DPU > + > +maintainers: > + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > + > +$ref: /schemas/display/msm/dpu-common.yaml# > + > +properties: > + compatible: > + const: qcom,sm8450-dpu > + > + reg: > + items: > + - description: Address offset and size for mdp register set > + - description: Address offset and size for vbif register set > + > + reg-names: > + items: > + - const: mdp > + - const: vbif > + > + clocks: > + items: > + - description: Display hf axi > + - description: Display sf axi > + - description: Display ahb > + - description: Display lut > + - description: Display core > + - description: Display vsync > + > + clock-names: > + items: > + - const: bus > + - const: nrt_bus > + - const: iface > + - const: lut > + - const: core > + - const: vsync > + > +unevaluatedProperties: false You should require here properties provided by this schema. Otherwise it is a bit trickier to get what is actually required. I'll comment on your dependency patchset as well. > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,sm8450-dispcc.h> > + #include <dt-bindings/clock/qcom,gcc-sm8450.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interconnect/qcom,sm8450.h> > + #include <dt-bindings/power/qcom-rpmpd.h> > + > + display-controller@ae01000 { > + compatible = "qcom,sm8450-dpu"; > + reg = <0x0ae01000 0x8f000>, > + <0x0aeb0000 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", > + "nrt_bus", > + "iface", > + "lut", > + "core", > + "vsync"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <19200000>; > + > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmhpd SM8450_MMCX>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&dsi0_in>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dpu_intf2_out: endpoint { > + remote-endpoint = <&dsi1_in>; > + }; > + }; > + }; > + > + mdp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-172000000{ > + opp-hz = /bits/ 64 <172000000>; > + required-opps = <&rpmhpd_opp_low_svs_d1>; > + }; > + > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-325000000 { > + opp-hz = /bits/ 64 <325000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-375000000 { > + opp-hz = /bits/ 64 <375000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-500000000 { > + opp-hz = /bits/ 64 <500000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > +... > diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml > new file mode 100644 > index 000000000000..9b6e1e03dc78 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml > @@ -0,0 +1,347 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm SM8450 Display MDSS > + > +maintainers: > + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > + > +description: > + SM8450 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like > + DPU display controller, DSI and DP interfaces etc. > + > +$ref: /schemas/display/msm/mdss-common.yaml# > + > +properties: > + compatible: > + const: qcom,sm8450-mdss > + > + clocks: > + items: > + - description: Display AHB > + - description: Display hf AXI > + - description: Display sf AXI > + - description: Display core > + > + clock-names: > + items: > + - const: iface > + - const: bus > + - const: nrt_bus > + - const: core > + > + iommus: > + maxItems: 1 > + > + interconnects: > + maxItems: 2 > + > + interconnect-names: > + maxItems: 2 > + > +patternProperties: > + "^display-controller@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: qcom,sm8450-dpu > + > + "^dsi@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: qcom,mdss-dsi-ctrl > + > + "^phy@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: qcom,dsi-phy-5nm-8450 > + > +unevaluatedProperties: false Ditto Best regards, Krzysztof ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 3/8] dt-bindings: display/msm: add support for the display on SM8450 @ 2022-11-08 11:02 ` Krzysztof Kozlowski 0 siblings, 0 replies; 62+ messages in thread From: Krzysztof Kozlowski @ 2022-11-08 11:02 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, freedreno On 04/11/2022 14:03, Dmitry Baryshkov wrote: > Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm > SM8450 platform. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > .../bindings/display/msm/qcom,sm8450-dpu.yaml | 132 +++++++ > .../display/msm/qcom,sm8450-mdss.yaml | 347 ++++++++++++++++++ > 2 files changed, 479 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml > create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml > > diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml > new file mode 100644 > index 000000000000..090a6506c8e9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml > @@ -0,0 +1,132 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm SM8450 Display DPU > + > +maintainers: > + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > + > +$ref: /schemas/display/msm/dpu-common.yaml# > + > +properties: > + compatible: > + const: qcom,sm8450-dpu > + > + reg: > + items: > + - description: Address offset and size for mdp register set > + - description: Address offset and size for vbif register set > + > + reg-names: > + items: > + - const: mdp > + - const: vbif > + > + clocks: > + items: > + - description: Display hf axi > + - description: Display sf axi > + - description: Display ahb > + - description: Display lut > + - description: Display core > + - description: Display vsync > + > + clock-names: > + items: > + - const: bus > + - const: nrt_bus > + - const: iface > + - const: lut > + - const: core > + - const: vsync > + > +unevaluatedProperties: false You should require here properties provided by this schema. Otherwise it is a bit trickier to get what is actually required. I'll comment on your dependency patchset as well. > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,sm8450-dispcc.h> > + #include <dt-bindings/clock/qcom,gcc-sm8450.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interconnect/qcom,sm8450.h> > + #include <dt-bindings/power/qcom-rpmpd.h> > + > + display-controller@ae01000 { > + compatible = "qcom,sm8450-dpu"; > + reg = <0x0ae01000 0x8f000>, > + <0x0aeb0000 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&gcc GCC_DISP_SF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", > + "nrt_bus", > + "iface", > + "lut", > + "core", > + "vsync"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <19200000>; > + > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmhpd SM8450_MMCX>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&dsi0_in>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dpu_intf2_out: endpoint { > + remote-endpoint = <&dsi1_in>; > + }; > + }; > + }; > + > + mdp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-172000000{ > + opp-hz = /bits/ 64 <172000000>; > + required-opps = <&rpmhpd_opp_low_svs_d1>; > + }; > + > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-325000000 { > + opp-hz = /bits/ 64 <325000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-375000000 { > + opp-hz = /bits/ 64 <375000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-500000000 { > + opp-hz = /bits/ 64 <500000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > +... > diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml > new file mode 100644 > index 000000000000..9b6e1e03dc78 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml > @@ -0,0 +1,347 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm SM8450 Display MDSS > + > +maintainers: > + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > + > +description: > + SM8450 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like > + DPU display controller, DSI and DP interfaces etc. > + > +$ref: /schemas/display/msm/mdss-common.yaml# > + > +properties: > + compatible: > + const: qcom,sm8450-mdss > + > + clocks: > + items: > + - description: Display AHB > + - description: Display hf AXI > + - description: Display sf AXI > + - description: Display core > + > + clock-names: > + items: > + - const: iface > + - const: bus > + - const: nrt_bus > + - const: core > + > + iommus: > + maxItems: 1 > + > + interconnects: > + maxItems: 2 > + > + interconnect-names: > + maxItems: 2 > + > +patternProperties: > + "^display-controller@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: qcom,sm8450-dpu > + > + "^dsi@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: qcom,mdss-dsi-ctrl > + > + "^phy@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: qcom,dsi-phy-5nm-8450 > + > +unevaluatedProperties: false Ditto Best regards, Krzysztof ^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v3 4/8] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450 2022-11-04 13:03 ` Dmitry Baryshkov @ 2022-11-04 13:03 ` Dmitry Baryshkov -1 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-04 13:03 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Robert Foss, Vinod Koul SM8350 and SM8450 use 5nm DSI PHYs, which share register definitions with 7nm DSI PHYs. Rather than duplicating the driver, handle 5nm variants inside the common 5+7nm driver. Co-developed-by: Robert Foss <robert.foss@linaro.org> Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/Kconfig | 6 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 128 ++++++++++++++++++++-- 4 files changed, 127 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index 3c9dfdb0b328..e7b100d97f88 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -140,12 +140,12 @@ config DRM_MSM_DSI_10NM_PHY Choose this option if DSI PHY on SDM845 is used on the platform. config DRM_MSM_DSI_7NM_PHY - bool "Enable DSI 7nm PHY driver in MSM DRM" + bool "Enable DSI 7nm/5nm PHY driver in MSM DRM" depends on DRM_MSM_DSI default y help - Choose this option if DSI PHY on SM8150/SM8250/SC7280 is used on - the platform. + Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SC7280 + is used on the platform. config DRM_MSM_HDMI bool "Enable HDMI support in MSM DRM driver" diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index ee6051367679..0c956fdab23e 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -569,6 +569,10 @@ static const struct of_device_id dsi_phy_dt_match[] = { .data = &dsi_phy_7nm_8150_cfgs }, { .compatible = "qcom,sc7280-dsi-phy-7nm", .data = &dsi_phy_7nm_7280_cfgs }, + { .compatible = "qcom,dsi-phy-5nm-8350", + .data = &dsi_phy_5nm_8350_cfgs }, + { .compatible = "qcom,dsi-phy-5nm-8450", + .data = &dsi_phy_5nm_8450_cfgs }, #endif {} }; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 1096afedd616..f7a907ed2b4b 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -57,6 +57,8 @@ extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; struct msm_dsi_dphy_timing { u32 clk_zero; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 9e7fa7d88ead..00d92fe97bc3 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -39,8 +39,14 @@ #define VCO_REF_CLK_RATE 19200000 #define FRAC_BITS 18 +/* Hardware is pre V4.1 */ +#define DSI_PHY_7NM_QUIRK_PRE_V4_1 BIT(0) /* Hardware is V4.1 */ -#define DSI_PHY_7NM_QUIRK_V4_1 BIT(0) +#define DSI_PHY_7NM_QUIRK_V4_1 BIT(1) +/* Hardware is V4.2 */ +#define DSI_PHY_7NM_QUIRK_V4_2 BIT(2) +/* Hardware is V4.3 */ +#define DSI_PHY_7NM_QUIRK_V4_3 BIT(3) struct dsi_pll_config { bool enable_ssc; @@ -116,7 +122,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config dec_multiple = div_u64(pll_freq * multiplier, divider); dec = div_u64_rem(dec_multiple, multiplier, &frac); - if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)) + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) config->pll_clock_inverters = 0x28; else if (pll_freq <= 1000000000ULL) config->pll_clock_inverters = 0xa0; @@ -197,16 +203,25 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) void __iomem *base = pll->phy->pll_base; u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00; - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) if (pll->vco_current_rate >= 3100000000ULL) analog_controls_five_1 = 0x03; + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { if (pll->vco_current_rate < 1520000000ULL) vco_config_1 = 0x08; else if (pll->vco_current_rate < 2990000000ULL) vco_config_1 = 0x01; } + if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) || + (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) { + if (pll->vco_current_rate < 1520000000ULL) + vco_config_1 = 0x08; + else if (pll->vco_current_rate >= 2990000000ULL) + vco_config_1 = 0x01; + } + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1, analog_controls_five_1); dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1); @@ -231,9 +246,9 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f); dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a); dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, - pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22); + !(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) ? 0x3f : 0x22); - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) { dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); if (pll->slave) dsi_phy_write(pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); @@ -788,7 +803,7 @@ static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy) const u8 *tx_dctrl = tx_dctrl_0; void __iomem *lane_base = phy->lane_base; - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) + if (!(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) tx_dctrl = tx_dctrl_1; /* Strength ctrl settings */ @@ -844,6 +859,12 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, if (dsi_phy_hw_v4_0_is_pll_on(phy)) pr_warn("PLL turned on before configuring PHY\n"); + /* Request for REFGEN READY */ + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { + dsi_phy_write(phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x1); + udelay(500); + } + /* wait for REFGEN READY */ ret = readl_poll_timeout_atomic(base + REG_DSI_7nm_PHY_CMN_PHY_STATUS, status, (status & BIT(0)), @@ -858,23 +879,53 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, /* Alter PHY configurations if data rate less than 1.5GHZ*/ less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000); - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { - vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { + if (phy->cphy_mode) { + vreg_ctrl_0 = 0x51; + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; + glbl_str_swi_cal_sel_ctrl = 0x00; + glbl_hstx_str_ctrl_0 = 0x00; + } else { + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; + glbl_str_swi_cal_sel_ctrl = 0x00; + glbl_hstx_str_ctrl_0 = 0x88; + } + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) { + if (phy->cphy_mode) { + vreg_ctrl_0 = 0x51; + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; + glbl_str_swi_cal_sel_ctrl = 0x00; + glbl_hstx_str_ctrl_0 = 0x00; + } else { + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x00; + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; + glbl_str_swi_cal_sel_ctrl = 0x00; + glbl_hstx_str_ctrl_0 = 0x88; + } + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { if (phy->cphy_mode) { + vreg_ctrl_0 = 0x51; glbl_rescode_top_ctrl = 0x00; glbl_rescode_bot_ctrl = 0x3c; } else { + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00; glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c; } glbl_str_swi_cal_sel_ctrl = 0x00; glbl_hstx_str_ctrl_0 = 0x88; } else { - vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; if (phy->cphy_mode) { + vreg_ctrl_0 = 0x51; glbl_str_swi_cal_sel_ctrl = 0x03; glbl_hstx_str_ctrl_0 = 0x66; } else { + vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00; glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88; } @@ -883,7 +934,6 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, } if (phy->cphy_mode) { - vreg_ctrl_0 = 0x51; vreg_ctrl_1 = 0x55; glbl_pemph_ctrl_0 = 0x11; lane_ctrl0 = 0x17; @@ -1017,6 +1067,13 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy) pr_warn("Turning OFF PHY while PLL is on\n"); dsi_phy_hw_v4_0_config_lpcdrx(phy, false); + + /* Turn off REFGEN Vote */ + dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x0); + wmb(); + /* Delay to ensure HW removes vote before PHY shut down */ + udelay(2); + data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_CTRL_0); /* disable all lanes */ @@ -1040,6 +1097,10 @@ static const struct regulator_bulk_data dsi_phy_7nm_37750uA_regulators[] = { { .supply = "vdds", .init_load_uA = 37550 }, }; +static const struct regulator_bulk_data dsi_phy_7nm_97800uA_regulators[] = { + { .supply = "vdds", .init_load_uA = 97800}, +}; + const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { .has_phy_lane = true, .regulator_data = dsi_phy_7nm_36mA_regulators, @@ -1079,6 +1140,7 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = { .max_pll_rate = 3500000000UL, .io_start = { 0xae94400, 0xae96400 }, .num_dsi_phy = 2, + .quirks = DSI_PHY_7NM_QUIRK_PRE_V4_1, }; const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = { @@ -1102,3 +1164,49 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = { .num_dsi_phy = 1, .quirks = DSI_PHY_7NM_QUIRK_V4_1, }; + +const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs = { + .has_phy_lane = true, + .regulator_data = dsi_phy_7nm_37750uA_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_37750uA_regulators), + .ops = { + .enable = dsi_7nm_phy_enable, + .disable = dsi_7nm_phy_disable, + .pll_init = dsi_pll_7nm_init, + .save_pll_state = dsi_7nm_pll_save_state, + .restore_pll_state = dsi_7nm_pll_restore_state, + .set_continuous_clock = dsi_7nm_set_continuous_clock, + }, + .min_pll_rate = 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate = 5000000000UL, +#else + .max_pll_rate = ULONG_MAX, +#endif + .io_start = { 0xae94400, 0xae96400 }, + .num_dsi_phy = 2, + .quirks = DSI_PHY_7NM_QUIRK_V4_2, +}; + +const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = { + .has_phy_lane = true, + .regulator_data = dsi_phy_7nm_97800uA_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_97800uA_regulators), + .ops = { + .enable = dsi_7nm_phy_enable, + .disable = dsi_7nm_phy_disable, + .pll_init = dsi_pll_7nm_init, + .save_pll_state = dsi_7nm_pll_save_state, + .restore_pll_state = dsi_7nm_pll_restore_state, + .set_continuous_clock = dsi_7nm_set_continuous_clock, + }, + .min_pll_rate = 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate = 5000000000UL, +#else + .max_pll_rate = ULONG_MAX, +#endif + .io_start = { 0xae94400, 0xae96400 }, + .num_dsi_phy = 2, + .quirks = DSI_PHY_7NM_QUIRK_V4_3, +}; -- 2.35.1 ^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 4/8] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450 @ 2022-11-04 13:03 ` Dmitry Baryshkov 0 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-04 13:03 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, Robert Foss, freedreno SM8350 and SM8450 use 5nm DSI PHYs, which share register definitions with 7nm DSI PHYs. Rather than duplicating the driver, handle 5nm variants inside the common 5+7nm driver. Co-developed-by: Robert Foss <robert.foss@linaro.org> Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/Kconfig | 6 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 128 ++++++++++++++++++++-- 4 files changed, 127 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index 3c9dfdb0b328..e7b100d97f88 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -140,12 +140,12 @@ config DRM_MSM_DSI_10NM_PHY Choose this option if DSI PHY on SDM845 is used on the platform. config DRM_MSM_DSI_7NM_PHY - bool "Enable DSI 7nm PHY driver in MSM DRM" + bool "Enable DSI 7nm/5nm PHY driver in MSM DRM" depends on DRM_MSM_DSI default y help - Choose this option if DSI PHY on SM8150/SM8250/SC7280 is used on - the platform. + Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SC7280 + is used on the platform. config DRM_MSM_HDMI bool "Enable HDMI support in MSM DRM driver" diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index ee6051367679..0c956fdab23e 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -569,6 +569,10 @@ static const struct of_device_id dsi_phy_dt_match[] = { .data = &dsi_phy_7nm_8150_cfgs }, { .compatible = "qcom,sc7280-dsi-phy-7nm", .data = &dsi_phy_7nm_7280_cfgs }, + { .compatible = "qcom,dsi-phy-5nm-8350", + .data = &dsi_phy_5nm_8350_cfgs }, + { .compatible = "qcom,dsi-phy-5nm-8450", + .data = &dsi_phy_5nm_8450_cfgs }, #endif {} }; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 1096afedd616..f7a907ed2b4b 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -57,6 +57,8 @@ extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; struct msm_dsi_dphy_timing { u32 clk_zero; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 9e7fa7d88ead..00d92fe97bc3 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -39,8 +39,14 @@ #define VCO_REF_CLK_RATE 19200000 #define FRAC_BITS 18 +/* Hardware is pre V4.1 */ +#define DSI_PHY_7NM_QUIRK_PRE_V4_1 BIT(0) /* Hardware is V4.1 */ -#define DSI_PHY_7NM_QUIRK_V4_1 BIT(0) +#define DSI_PHY_7NM_QUIRK_V4_1 BIT(1) +/* Hardware is V4.2 */ +#define DSI_PHY_7NM_QUIRK_V4_2 BIT(2) +/* Hardware is V4.3 */ +#define DSI_PHY_7NM_QUIRK_V4_3 BIT(3) struct dsi_pll_config { bool enable_ssc; @@ -116,7 +122,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config dec_multiple = div_u64(pll_freq * multiplier, divider); dec = div_u64_rem(dec_multiple, multiplier, &frac); - if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)) + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) config->pll_clock_inverters = 0x28; else if (pll_freq <= 1000000000ULL) config->pll_clock_inverters = 0xa0; @@ -197,16 +203,25 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) void __iomem *base = pll->phy->pll_base; u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00; - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) if (pll->vco_current_rate >= 3100000000ULL) analog_controls_five_1 = 0x03; + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { if (pll->vco_current_rate < 1520000000ULL) vco_config_1 = 0x08; else if (pll->vco_current_rate < 2990000000ULL) vco_config_1 = 0x01; } + if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) || + (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) { + if (pll->vco_current_rate < 1520000000ULL) + vco_config_1 = 0x08; + else if (pll->vco_current_rate >= 2990000000ULL) + vco_config_1 = 0x01; + } + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1, analog_controls_five_1); dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1); @@ -231,9 +246,9 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f); dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a); dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, - pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22); + !(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) ? 0x3f : 0x22); - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) { dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); if (pll->slave) dsi_phy_write(pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); @@ -788,7 +803,7 @@ static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy) const u8 *tx_dctrl = tx_dctrl_0; void __iomem *lane_base = phy->lane_base; - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) + if (!(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) tx_dctrl = tx_dctrl_1; /* Strength ctrl settings */ @@ -844,6 +859,12 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, if (dsi_phy_hw_v4_0_is_pll_on(phy)) pr_warn("PLL turned on before configuring PHY\n"); + /* Request for REFGEN READY */ + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { + dsi_phy_write(phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x1); + udelay(500); + } + /* wait for REFGEN READY */ ret = readl_poll_timeout_atomic(base + REG_DSI_7nm_PHY_CMN_PHY_STATUS, status, (status & BIT(0)), @@ -858,23 +879,53 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, /* Alter PHY configurations if data rate less than 1.5GHZ*/ less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000); - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { - vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { + if (phy->cphy_mode) { + vreg_ctrl_0 = 0x51; + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; + glbl_str_swi_cal_sel_ctrl = 0x00; + glbl_hstx_str_ctrl_0 = 0x00; + } else { + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; + glbl_str_swi_cal_sel_ctrl = 0x00; + glbl_hstx_str_ctrl_0 = 0x88; + } + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) { + if (phy->cphy_mode) { + vreg_ctrl_0 = 0x51; + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; + glbl_str_swi_cal_sel_ctrl = 0x00; + glbl_hstx_str_ctrl_0 = 0x00; + } else { + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x00; + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; + glbl_str_swi_cal_sel_ctrl = 0x00; + glbl_hstx_str_ctrl_0 = 0x88; + } + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { if (phy->cphy_mode) { + vreg_ctrl_0 = 0x51; glbl_rescode_top_ctrl = 0x00; glbl_rescode_bot_ctrl = 0x3c; } else { + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00; glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c; } glbl_str_swi_cal_sel_ctrl = 0x00; glbl_hstx_str_ctrl_0 = 0x88; } else { - vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; if (phy->cphy_mode) { + vreg_ctrl_0 = 0x51; glbl_str_swi_cal_sel_ctrl = 0x03; glbl_hstx_str_ctrl_0 = 0x66; } else { + vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00; glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88; } @@ -883,7 +934,6 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, } if (phy->cphy_mode) { - vreg_ctrl_0 = 0x51; vreg_ctrl_1 = 0x55; glbl_pemph_ctrl_0 = 0x11; lane_ctrl0 = 0x17; @@ -1017,6 +1067,13 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy) pr_warn("Turning OFF PHY while PLL is on\n"); dsi_phy_hw_v4_0_config_lpcdrx(phy, false); + + /* Turn off REFGEN Vote */ + dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x0); + wmb(); + /* Delay to ensure HW removes vote before PHY shut down */ + udelay(2); + data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_CTRL_0); /* disable all lanes */ @@ -1040,6 +1097,10 @@ static const struct regulator_bulk_data dsi_phy_7nm_37750uA_regulators[] = { { .supply = "vdds", .init_load_uA = 37550 }, }; +static const struct regulator_bulk_data dsi_phy_7nm_97800uA_regulators[] = { + { .supply = "vdds", .init_load_uA = 97800}, +}; + const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { .has_phy_lane = true, .regulator_data = dsi_phy_7nm_36mA_regulators, @@ -1079,6 +1140,7 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = { .max_pll_rate = 3500000000UL, .io_start = { 0xae94400, 0xae96400 }, .num_dsi_phy = 2, + .quirks = DSI_PHY_7NM_QUIRK_PRE_V4_1, }; const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = { @@ -1102,3 +1164,49 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = { .num_dsi_phy = 1, .quirks = DSI_PHY_7NM_QUIRK_V4_1, }; + +const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs = { + .has_phy_lane = true, + .regulator_data = dsi_phy_7nm_37750uA_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_37750uA_regulators), + .ops = { + .enable = dsi_7nm_phy_enable, + .disable = dsi_7nm_phy_disable, + .pll_init = dsi_pll_7nm_init, + .save_pll_state = dsi_7nm_pll_save_state, + .restore_pll_state = dsi_7nm_pll_restore_state, + .set_continuous_clock = dsi_7nm_set_continuous_clock, + }, + .min_pll_rate = 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate = 5000000000UL, +#else + .max_pll_rate = ULONG_MAX, +#endif + .io_start = { 0xae94400, 0xae96400 }, + .num_dsi_phy = 2, + .quirks = DSI_PHY_7NM_QUIRK_V4_2, +}; + +const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = { + .has_phy_lane = true, + .regulator_data = dsi_phy_7nm_97800uA_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_97800uA_regulators), + .ops = { + .enable = dsi_7nm_phy_enable, + .disable = dsi_7nm_phy_disable, + .pll_init = dsi_pll_7nm_init, + .save_pll_state = dsi_7nm_pll_save_state, + .restore_pll_state = dsi_7nm_pll_restore_state, + .set_continuous_clock = dsi_7nm_set_continuous_clock, + }, + .min_pll_rate = 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate = 5000000000UL, +#else + .max_pll_rate = ULONG_MAX, +#endif + .io_start = { 0xae94400, 0xae96400 }, + .num_dsi_phy = 2, + .quirks = DSI_PHY_7NM_QUIRK_V4_3, +}; -- 2.35.1 ^ permalink raw reply related [flat|nested] 62+ messages in thread
* Re: [PATCH v3 4/8] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450 2022-11-04 13:03 ` Dmitry Baryshkov @ 2022-11-04 13:54 ` Konrad Dybcio -1 siblings, 0 replies; 62+ messages in thread From: Konrad Dybcio @ 2022-11-04 13:54 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Robert Foss, Vinod Koul On 04/11/2022 14:03, Dmitry Baryshkov wrote: > SM8350 and SM8450 use 5nm DSI PHYs, which share register definitions > with 7nm DSI PHYs. Rather than duplicating the driver, handle 5nm > variants inside the common 5+7nm driver. > > Co-developed-by: Robert Foss <robert.foss@linaro.org> > Tested-by: Vinod Koul <vkoul@kernel.org> > Reviewed-by: Vinod Koul <vkoul@kernel.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/gpu/drm/msm/Kconfig | 6 +- > drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 + > drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 + > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 128 ++++++++++++++++++++-- > 4 files changed, 127 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig > index 3c9dfdb0b328..e7b100d97f88 100644 > --- a/drivers/gpu/drm/msm/Kconfig > +++ b/drivers/gpu/drm/msm/Kconfig > @@ -140,12 +140,12 @@ config DRM_MSM_DSI_10NM_PHY > Choose this option if DSI PHY on SDM845 is used on the platform. > > config DRM_MSM_DSI_7NM_PHY > - bool "Enable DSI 7nm PHY driver in MSM DRM" > + bool "Enable DSI 7nm/5nm PHY driver in MSM DRM" > depends on DRM_MSM_DSI > default y > help > - Choose this option if DSI PHY on SM8150/SM8250/SC7280 is used on > - the platform. > + Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SC7280 > + is used on the platform. > > config DRM_MSM_HDMI > bool "Enable HDMI support in MSM DRM driver" > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > index ee6051367679..0c956fdab23e 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > @@ -569,6 +569,10 @@ static const struct of_device_id dsi_phy_dt_match[] = { > .data = &dsi_phy_7nm_8150_cfgs }, > { .compatible = "qcom,sc7280-dsi-phy-7nm", > .data = &dsi_phy_7nm_7280_cfgs }, > + { .compatible = "qcom,dsi-phy-5nm-8350", > + .data = &dsi_phy_5nm_8350_cfgs }, > + { .compatible = "qcom,dsi-phy-5nm-8450", > + .data = &dsi_phy_5nm_8450_cfgs }, > #endif > {} > }; > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > index 1096afedd616..f7a907ed2b4b 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > @@ -57,6 +57,8 @@ extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs; > +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; > +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; > > struct msm_dsi_dphy_timing { > u32 clk_zero; > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > index 9e7fa7d88ead..00d92fe97bc3 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > @@ -39,8 +39,14 @@ > #define VCO_REF_CLK_RATE 19200000 > #define FRAC_BITS 18 > > +/* Hardware is pre V4.1 */ > +#define DSI_PHY_7NM_QUIRK_PRE_V4_1 BIT(0) > /* Hardware is V4.1 */ > -#define DSI_PHY_7NM_QUIRK_V4_1 BIT(0) > +#define DSI_PHY_7NM_QUIRK_V4_1 BIT(1) > +/* Hardware is V4.2 */ > +#define DSI_PHY_7NM_QUIRK_V4_2 BIT(2) > +/* Hardware is V4.3 */ > +#define DSI_PHY_7NM_QUIRK_V4_3 BIT(3) Quirk is quite an unfortunate name considering what we use it for.. but I suppose it can stay, as otherwise even more renaming would have to be done. > > struct dsi_pll_config { > bool enable_ssc; > @@ -116,7 +122,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config > dec_multiple = div_u64(pll_freq * multiplier, divider); > dec = div_u64_rem(dec_multiple, multiplier, &frac); > > - if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)) > + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) > config->pll_clock_inverters = 0x28; > else if (pll_freq <= 1000000000ULL) > config->pll_clock_inverters = 0xa0; > @@ -197,16 +203,25 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) > void __iomem *base = pll->phy->pll_base; > u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00; > > - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { > + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) > if (pll->vco_current_rate >= 3100000000ULL) > analog_controls_five_1 = 0x03; > > + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { > if (pll->vco_current_rate < 1520000000ULL) > vco_config_1 = 0x08; > else if (pll->vco_current_rate < 2990000000ULL) > vco_config_1 = 0x01; > } > > + if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) || > + (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) { > + if (pll->vco_current_rate < 1520000000ULL) > + vco_config_1 = 0x08; > + else if (pll->vco_current_rate >= 2990000000ULL) > + vco_config_1 = 0x01; > + } > + > dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1, > analog_controls_five_1); > dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1); > @@ -231,9 +246,9 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) > dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f); > dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a); > dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, > - pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22); > + !(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) ? 0x3f : 0x22); > > - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { > + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) { > dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); > if (pll->slave) > dsi_phy_write(pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); > @@ -788,7 +803,7 @@ static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy) > const u8 *tx_dctrl = tx_dctrl_0; > void __iomem *lane_base = phy->lane_base; > > - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) > + if (!(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) > tx_dctrl = tx_dctrl_1; > > /* Strength ctrl settings */ > @@ -844,6 +859,12 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, > if (dsi_phy_hw_v4_0_is_pll_on(phy)) > pr_warn("PLL turned on before configuring PHY\n"); > > + /* Request for REFGEN READY */ > + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { > + dsi_phy_write(phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x1); > + udelay(500); > + } > + > /* wait for REFGEN READY */ > ret = readl_poll_timeout_atomic(base + REG_DSI_7nm_PHY_CMN_PHY_STATUS, > status, (status & BIT(0)), > @@ -858,23 +879,53 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, > /* Alter PHY configurations if data rate less than 1.5GHZ*/ > less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000); > > - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { > - vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; > + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { > + if (phy->cphy_mode) { > + vreg_ctrl_0 = 0x51; > + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; > + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; > + glbl_str_swi_cal_sel_ctrl = 0x00; > + glbl_hstx_str_ctrl_0 = 0x00; > + } else { > + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; > + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; msm-5.10 has it as 0x3d : 0x00 for both v4.2 and v4.3 in DPHY mode > + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; > + glbl_str_swi_cal_sel_ctrl = 0x00; > + glbl_hstx_str_ctrl_0 = 0x88; > + } > + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) { > + if (phy->cphy_mode) { > + vreg_ctrl_0 = 0x51; > + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; > + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; > + glbl_str_swi_cal_sel_ctrl = 0x00; > + glbl_hstx_str_ctrl_0 = 0x00; > + } else { > + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; > + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x00; > + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; > + glbl_str_swi_cal_sel_ctrl = 0x00; > + glbl_hstx_str_ctrl_0 = 0x88; > + } > + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { > if (phy->cphy_mode) { > + vreg_ctrl_0 = 0x51; > glbl_rescode_top_ctrl = 0x00; > glbl_rescode_bot_ctrl = 0x3c; > } else { > + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; > glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00; > glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c; > } > glbl_str_swi_cal_sel_ctrl = 0x00; > glbl_hstx_str_ctrl_0 = 0x88; > } else { > - vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; > if (phy->cphy_mode) { > + vreg_ctrl_0 = 0x51; > glbl_str_swi_cal_sel_ctrl = 0x03; > glbl_hstx_str_ctrl_0 = 0x66; > } else { > + vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; > glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00; > glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88; > } > @@ -883,7 +934,6 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, > } > > if (phy->cphy_mode) { > - vreg_ctrl_0 = 0x51; > vreg_ctrl_1 = 0x55; > glbl_pemph_ctrl_0 = 0x11; > lane_ctrl0 = 0x17; > @@ -1017,6 +1067,13 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy) > pr_warn("Turning OFF PHY while PLL is on\n"); > > dsi_phy_hw_v4_0_config_lpcdrx(phy, false); > + > + /* Turn off REFGEN Vote */ > + dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x0); > + wmb(); > + /* Delay to ensure HW removes vote before PHY shut down */ > + udelay(2); Either thunderbird is acting up (again) or the code after the first comment is indented with spaces instead of tabs. Other than that, Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Konrad > + > data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_CTRL_0); > > /* disable all lanes */ > @@ -1040,6 +1097,10 @@ static const struct regulator_bulk_data dsi_phy_7nm_37750uA_regulators[] = { > { .supply = "vdds", .init_load_uA = 37550 }, > }; > > +static const struct regulator_bulk_data dsi_phy_7nm_97800uA_regulators[] = { > + { .supply = "vdds", .init_load_uA = 97800}, > +}; > + > const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { > .has_phy_lane = true, > .regulator_data = dsi_phy_7nm_36mA_regulators, > @@ -1079,6 +1140,7 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = { > .max_pll_rate = 3500000000UL, > .io_start = { 0xae94400, 0xae96400 }, > .num_dsi_phy = 2, > + .quirks = DSI_PHY_7NM_QUIRK_PRE_V4_1, > }; > > const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = { > @@ -1102,3 +1164,49 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = { > .num_dsi_phy = 1, > .quirks = DSI_PHY_7NM_QUIRK_V4_1, > }; > + > +const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs = { > + .has_phy_lane = true, > + .regulator_data = dsi_phy_7nm_37750uA_regulators, > + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_37750uA_regulators), > + .ops = { > + .enable = dsi_7nm_phy_enable, > + .disable = dsi_7nm_phy_disable, > + .pll_init = dsi_pll_7nm_init, > + .save_pll_state = dsi_7nm_pll_save_state, > + .restore_pll_state = dsi_7nm_pll_restore_state, > + .set_continuous_clock = dsi_7nm_set_continuous_clock, > + }, > + .min_pll_rate = 600000000UL, > +#ifdef CONFIG_64BIT > + .max_pll_rate = 5000000000UL, > +#else > + .max_pll_rate = ULONG_MAX, > +#endif > + .io_start = { 0xae94400, 0xae96400 }, > + .num_dsi_phy = 2, > + .quirks = DSI_PHY_7NM_QUIRK_V4_2, > +}; > + > +const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = { > + .has_phy_lane = true, > + .regulator_data = dsi_phy_7nm_97800uA_regulators, > + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_97800uA_regulators), > + .ops = { > + .enable = dsi_7nm_phy_enable, > + .disable = dsi_7nm_phy_disable, > + .pll_init = dsi_pll_7nm_init, > + .save_pll_state = dsi_7nm_pll_save_state, > + .restore_pll_state = dsi_7nm_pll_restore_state, > + .set_continuous_clock = dsi_7nm_set_continuous_clock, > + }, > + .min_pll_rate = 600000000UL, > +#ifdef CONFIG_64BIT > + .max_pll_rate = 5000000000UL, > +#else > + .max_pll_rate = ULONG_MAX, > +#endif > + .io_start = { 0xae94400, 0xae96400 }, > + .num_dsi_phy = 2, > + .quirks = DSI_PHY_7NM_QUIRK_V4_3, > +}; ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 4/8] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450 @ 2022-11-04 13:54 ` Konrad Dybcio 0 siblings, 0 replies; 62+ messages in thread From: Konrad Dybcio @ 2022-11-04 13:54 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, Robert Foss, freedreno On 04/11/2022 14:03, Dmitry Baryshkov wrote: > SM8350 and SM8450 use 5nm DSI PHYs, which share register definitions > with 7nm DSI PHYs. Rather than duplicating the driver, handle 5nm > variants inside the common 5+7nm driver. > > Co-developed-by: Robert Foss <robert.foss@linaro.org> > Tested-by: Vinod Koul <vkoul@kernel.org> > Reviewed-by: Vinod Koul <vkoul@kernel.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/gpu/drm/msm/Kconfig | 6 +- > drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 + > drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 + > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 128 ++++++++++++++++++++-- > 4 files changed, 127 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig > index 3c9dfdb0b328..e7b100d97f88 100644 > --- a/drivers/gpu/drm/msm/Kconfig > +++ b/drivers/gpu/drm/msm/Kconfig > @@ -140,12 +140,12 @@ config DRM_MSM_DSI_10NM_PHY > Choose this option if DSI PHY on SDM845 is used on the platform. > > config DRM_MSM_DSI_7NM_PHY > - bool "Enable DSI 7nm PHY driver in MSM DRM" > + bool "Enable DSI 7nm/5nm PHY driver in MSM DRM" > depends on DRM_MSM_DSI > default y > help > - Choose this option if DSI PHY on SM8150/SM8250/SC7280 is used on > - the platform. > + Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SC7280 > + is used on the platform. > > config DRM_MSM_HDMI > bool "Enable HDMI support in MSM DRM driver" > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > index ee6051367679..0c956fdab23e 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > @@ -569,6 +569,10 @@ static const struct of_device_id dsi_phy_dt_match[] = { > .data = &dsi_phy_7nm_8150_cfgs }, > { .compatible = "qcom,sc7280-dsi-phy-7nm", > .data = &dsi_phy_7nm_7280_cfgs }, > + { .compatible = "qcom,dsi-phy-5nm-8350", > + .data = &dsi_phy_5nm_8350_cfgs }, > + { .compatible = "qcom,dsi-phy-5nm-8450", > + .data = &dsi_phy_5nm_8450_cfgs }, > #endif > {} > }; > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > index 1096afedd616..f7a907ed2b4b 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > @@ -57,6 +57,8 @@ extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs; > +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; > +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; > > struct msm_dsi_dphy_timing { > u32 clk_zero; > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > index 9e7fa7d88ead..00d92fe97bc3 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > @@ -39,8 +39,14 @@ > #define VCO_REF_CLK_RATE 19200000 > #define FRAC_BITS 18 > > +/* Hardware is pre V4.1 */ > +#define DSI_PHY_7NM_QUIRK_PRE_V4_1 BIT(0) > /* Hardware is V4.1 */ > -#define DSI_PHY_7NM_QUIRK_V4_1 BIT(0) > +#define DSI_PHY_7NM_QUIRK_V4_1 BIT(1) > +/* Hardware is V4.2 */ > +#define DSI_PHY_7NM_QUIRK_V4_2 BIT(2) > +/* Hardware is V4.3 */ > +#define DSI_PHY_7NM_QUIRK_V4_3 BIT(3) Quirk is quite an unfortunate name considering what we use it for.. but I suppose it can stay, as otherwise even more renaming would have to be done. > > struct dsi_pll_config { > bool enable_ssc; > @@ -116,7 +122,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config > dec_multiple = div_u64(pll_freq * multiplier, divider); > dec = div_u64_rem(dec_multiple, multiplier, &frac); > > - if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)) > + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) > config->pll_clock_inverters = 0x28; > else if (pll_freq <= 1000000000ULL) > config->pll_clock_inverters = 0xa0; > @@ -197,16 +203,25 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) > void __iomem *base = pll->phy->pll_base; > u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00; > > - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { > + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) > if (pll->vco_current_rate >= 3100000000ULL) > analog_controls_five_1 = 0x03; > > + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { > if (pll->vco_current_rate < 1520000000ULL) > vco_config_1 = 0x08; > else if (pll->vco_current_rate < 2990000000ULL) > vco_config_1 = 0x01; > } > > + if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) || > + (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) { > + if (pll->vco_current_rate < 1520000000ULL) > + vco_config_1 = 0x08; > + else if (pll->vco_current_rate >= 2990000000ULL) > + vco_config_1 = 0x01; > + } > + > dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1, > analog_controls_five_1); > dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1); > @@ -231,9 +246,9 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) > dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f); > dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a); > dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, > - pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22); > + !(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) ? 0x3f : 0x22); > > - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { > + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) { > dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); > if (pll->slave) > dsi_phy_write(pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); > @@ -788,7 +803,7 @@ static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy) > const u8 *tx_dctrl = tx_dctrl_0; > void __iomem *lane_base = phy->lane_base; > > - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) > + if (!(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) > tx_dctrl = tx_dctrl_1; > > /* Strength ctrl settings */ > @@ -844,6 +859,12 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, > if (dsi_phy_hw_v4_0_is_pll_on(phy)) > pr_warn("PLL turned on before configuring PHY\n"); > > + /* Request for REFGEN READY */ > + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { > + dsi_phy_write(phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x1); > + udelay(500); > + } > + > /* wait for REFGEN READY */ > ret = readl_poll_timeout_atomic(base + REG_DSI_7nm_PHY_CMN_PHY_STATUS, > status, (status & BIT(0)), > @@ -858,23 +879,53 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, > /* Alter PHY configurations if data rate less than 1.5GHZ*/ > less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000); > > - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { > - vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; > + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { > + if (phy->cphy_mode) { > + vreg_ctrl_0 = 0x51; > + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; > + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; > + glbl_str_swi_cal_sel_ctrl = 0x00; > + glbl_hstx_str_ctrl_0 = 0x00; > + } else { > + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; > + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; msm-5.10 has it as 0x3d : 0x00 for both v4.2 and v4.3 in DPHY mode > + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; > + glbl_str_swi_cal_sel_ctrl = 0x00; > + glbl_hstx_str_ctrl_0 = 0x88; > + } > + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) { > + if (phy->cphy_mode) { > + vreg_ctrl_0 = 0x51; > + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; > + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; > + glbl_str_swi_cal_sel_ctrl = 0x00; > + glbl_hstx_str_ctrl_0 = 0x00; > + } else { > + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; > + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x00; > + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; > + glbl_str_swi_cal_sel_ctrl = 0x00; > + glbl_hstx_str_ctrl_0 = 0x88; > + } > + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { > if (phy->cphy_mode) { > + vreg_ctrl_0 = 0x51; > glbl_rescode_top_ctrl = 0x00; > glbl_rescode_bot_ctrl = 0x3c; > } else { > + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; > glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00; > glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c; > } > glbl_str_swi_cal_sel_ctrl = 0x00; > glbl_hstx_str_ctrl_0 = 0x88; > } else { > - vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; > if (phy->cphy_mode) { > + vreg_ctrl_0 = 0x51; > glbl_str_swi_cal_sel_ctrl = 0x03; > glbl_hstx_str_ctrl_0 = 0x66; > } else { > + vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; > glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00; > glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88; > } > @@ -883,7 +934,6 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, > } > > if (phy->cphy_mode) { > - vreg_ctrl_0 = 0x51; > vreg_ctrl_1 = 0x55; > glbl_pemph_ctrl_0 = 0x11; > lane_ctrl0 = 0x17; > @@ -1017,6 +1067,13 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy) > pr_warn("Turning OFF PHY while PLL is on\n"); > > dsi_phy_hw_v4_0_config_lpcdrx(phy, false); > + > + /* Turn off REFGEN Vote */ > + dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x0); > + wmb(); > + /* Delay to ensure HW removes vote before PHY shut down */ > + udelay(2); Either thunderbird is acting up (again) or the code after the first comment is indented with spaces instead of tabs. Other than that, Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Konrad > + > data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_CTRL_0); > > /* disable all lanes */ > @@ -1040,6 +1097,10 @@ static const struct regulator_bulk_data dsi_phy_7nm_37750uA_regulators[] = { > { .supply = "vdds", .init_load_uA = 37550 }, > }; > > +static const struct regulator_bulk_data dsi_phy_7nm_97800uA_regulators[] = { > + { .supply = "vdds", .init_load_uA = 97800}, > +}; > + > const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { > .has_phy_lane = true, > .regulator_data = dsi_phy_7nm_36mA_regulators, > @@ -1079,6 +1140,7 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = { > .max_pll_rate = 3500000000UL, > .io_start = { 0xae94400, 0xae96400 }, > .num_dsi_phy = 2, > + .quirks = DSI_PHY_7NM_QUIRK_PRE_V4_1, > }; > > const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = { > @@ -1102,3 +1164,49 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = { > .num_dsi_phy = 1, > .quirks = DSI_PHY_7NM_QUIRK_V4_1, > }; > + > +const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs = { > + .has_phy_lane = true, > + .regulator_data = dsi_phy_7nm_37750uA_regulators, > + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_37750uA_regulators), > + .ops = { > + .enable = dsi_7nm_phy_enable, > + .disable = dsi_7nm_phy_disable, > + .pll_init = dsi_pll_7nm_init, > + .save_pll_state = dsi_7nm_pll_save_state, > + .restore_pll_state = dsi_7nm_pll_restore_state, > + .set_continuous_clock = dsi_7nm_set_continuous_clock, > + }, > + .min_pll_rate = 600000000UL, > +#ifdef CONFIG_64BIT > + .max_pll_rate = 5000000000UL, > +#else > + .max_pll_rate = ULONG_MAX, > +#endif > + .io_start = { 0xae94400, 0xae96400 }, > + .num_dsi_phy = 2, > + .quirks = DSI_PHY_7NM_QUIRK_V4_2, > +}; > + > +const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = { > + .has_phy_lane = true, > + .regulator_data = dsi_phy_7nm_97800uA_regulators, > + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_97800uA_regulators), > + .ops = { > + .enable = dsi_7nm_phy_enable, > + .disable = dsi_7nm_phy_disable, > + .pll_init = dsi_pll_7nm_init, > + .save_pll_state = dsi_7nm_pll_save_state, > + .restore_pll_state = dsi_7nm_pll_restore_state, > + .set_continuous_clock = dsi_7nm_set_continuous_clock, > + }, > + .min_pll_rate = 600000000UL, > +#ifdef CONFIG_64BIT > + .max_pll_rate = 5000000000UL, > +#else > + .max_pll_rate = ULONG_MAX, > +#endif > + .io_start = { 0xae94400, 0xae96400 }, > + .num_dsi_phy = 2, > + .quirks = DSI_PHY_7NM_QUIRK_V4_3, > +}; ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 4/8] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450 2022-11-04 13:54 ` Konrad Dybcio @ 2022-11-10 22:16 ` Dmitry Baryshkov -1 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-10 22:16 UTC (permalink / raw) To: Konrad Dybcio, Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Robert Foss, Vinod Koul On 04/11/2022 16:54, Konrad Dybcio wrote: > > On 04/11/2022 14:03, Dmitry Baryshkov wrote: >> SM8350 and SM8450 use 5nm DSI PHYs, which share register definitions >> with 7nm DSI PHYs. Rather than duplicating the driver, handle 5nm >> variants inside the common 5+7nm driver. >> >> Co-developed-by: Robert Foss <robert.foss@linaro.org> >> Tested-by: Vinod Koul <vkoul@kernel.org> >> Reviewed-by: Vinod Koul <vkoul@kernel.org> >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> --- >> drivers/gpu/drm/msm/Kconfig | 6 +- >> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 + >> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 + >> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 128 ++++++++++++++++++++-- >> 4 files changed, 127 insertions(+), 13 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig >> index 3c9dfdb0b328..e7b100d97f88 100644 >> --- a/drivers/gpu/drm/msm/Kconfig >> +++ b/drivers/gpu/drm/msm/Kconfig >> @@ -140,12 +140,12 @@ config DRM_MSM_DSI_10NM_PHY >> Choose this option if DSI PHY on SDM845 is used on the platform. >> config DRM_MSM_DSI_7NM_PHY >> - bool "Enable DSI 7nm PHY driver in MSM DRM" >> + bool "Enable DSI 7nm/5nm PHY driver in MSM DRM" >> depends on DRM_MSM_DSI >> default y >> help >> - Choose this option if DSI PHY on SM8150/SM8250/SC7280 is used on >> - the platform. >> + Choose this option if DSI PHY on >> SM8150/SM8250/SM8350/SM8450/SC7280 >> + is used on the platform. >> config DRM_MSM_HDMI >> bool "Enable HDMI support in MSM DRM driver" >> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >> index ee6051367679..0c956fdab23e 100644 >> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >> @@ -569,6 +569,10 @@ static const struct of_device_id >> dsi_phy_dt_match[] = { >> .data = &dsi_phy_7nm_8150_cfgs }, >> { .compatible = "qcom,sc7280-dsi-phy-7nm", >> .data = &dsi_phy_7nm_7280_cfgs }, >> + { .compatible = "qcom,dsi-phy-5nm-8350", >> + .data = &dsi_phy_5nm_8350_cfgs }, >> + { .compatible = "qcom,dsi-phy-5nm-8450", >> + .data = &dsi_phy_5nm_8450_cfgs }, >> #endif >> {} >> }; >> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >> index 1096afedd616..f7a907ed2b4b 100644 >> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >> @@ -57,6 +57,8 @@ extern const struct msm_dsi_phy_cfg >> dsi_phy_10nm_8998_cfgs; >> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs; >> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs; >> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs; >> +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; >> +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; >> struct msm_dsi_dphy_timing { >> u32 clk_zero; >> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >> index 9e7fa7d88ead..00d92fe97bc3 100644 >> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >> @@ -39,8 +39,14 @@ >> #define VCO_REF_CLK_RATE 19200000 >> #define FRAC_BITS 18 >> +/* Hardware is pre V4.1 */ >> +#define DSI_PHY_7NM_QUIRK_PRE_V4_1 BIT(0) >> /* Hardware is V4.1 */ >> -#define DSI_PHY_7NM_QUIRK_V4_1 BIT(0) >> +#define DSI_PHY_7NM_QUIRK_V4_1 BIT(1) >> +/* Hardware is V4.2 */ >> +#define DSI_PHY_7NM_QUIRK_V4_2 BIT(2) >> +/* Hardware is V4.3 */ >> +#define DSI_PHY_7NM_QUIRK_V4_3 BIT(3) > > Quirk is quite an unfortunate name considering what we use it for.. but I > > suppose it can stay, as otherwise even more renaming would have to be done. > > >> struct dsi_pll_config { >> bool enable_ssc; >> @@ -116,7 +122,7 @@ static void dsi_pll_calc_dec_frac(struct >> dsi_pll_7nm *pll, struct dsi_pll_config >> dec_multiple = div_u64(pll_freq * multiplier, divider); >> dec = div_u64_rem(dec_multiple, multiplier, &frac); >> - if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)) >> + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) >> config->pll_clock_inverters = 0x28; >> else if (pll_freq <= 1000000000ULL) >> config->pll_clock_inverters = 0xa0; >> @@ -197,16 +203,25 @@ static void dsi_pll_config_hzindep_reg(struct >> dsi_pll_7nm *pll) >> void __iomem *base = pll->phy->pll_base; >> u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00; >> - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { >> + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) >> if (pll->vco_current_rate >= 3100000000ULL) >> analog_controls_five_1 = 0x03; >> + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { >> if (pll->vco_current_rate < 1520000000ULL) >> vco_config_1 = 0x08; >> else if (pll->vco_current_rate < 2990000000ULL) >> vco_config_1 = 0x01; >> } >> + if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) || >> + (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) { >> + if (pll->vco_current_rate < 1520000000ULL) >> + vco_config_1 = 0x08; >> + else if (pll->vco_current_rate >= 2990000000ULL) >> + vco_config_1 = 0x01; >> + } >> + >> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1, >> analog_controls_five_1); >> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, >> vco_config_1); >> @@ -231,9 +246,9 @@ static void dsi_pll_config_hzindep_reg(struct >> dsi_pll_7nm *pll) >> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f); >> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a); >> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, >> - pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22); >> + !(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) ? >> 0x3f : 0x22); >> - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { >> + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) { >> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); >> if (pll->slave) >> dsi_phy_write(pll->slave->phy->pll_base + >> REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); >> @@ -788,7 +803,7 @@ static void dsi_phy_hw_v4_0_lane_settings(struct >> msm_dsi_phy *phy) >> const u8 *tx_dctrl = tx_dctrl_0; >> void __iomem *lane_base = phy->lane_base; >> - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) >> + if (!(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) >> tx_dctrl = tx_dctrl_1; >> /* Strength ctrl settings */ >> @@ -844,6 +859,12 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy >> *phy, >> if (dsi_phy_hw_v4_0_is_pll_on(phy)) >> pr_warn("PLL turned on before configuring PHY\n"); >> + /* Request for REFGEN READY */ >> + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { >> + dsi_phy_write(phy->base + >> REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x1); >> + udelay(500); >> + } >> + >> /* wait for REFGEN READY */ >> ret = readl_poll_timeout_atomic(base + >> REG_DSI_7nm_PHY_CMN_PHY_STATUS, >> status, (status & BIT(0)), >> @@ -858,23 +879,53 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy >> *phy, >> /* Alter PHY configurations if data rate less than 1.5GHZ*/ >> less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000); >> - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { >> - vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; >> + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { >> + if (phy->cphy_mode) { >> + vreg_ctrl_0 = 0x51; >> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; >> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; >> + glbl_str_swi_cal_sel_ctrl = 0x00; >> + glbl_hstx_str_ctrl_0 = 0x00; >> + } else { >> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; >> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; > > msm-5.10 has it as 0x3d : 0x00 for both v4.2 and v4.3 in DPHY mode Checking with the latest display-drivers sources at [1]: There is a common code block using 0x3c : 0x00, but after that at line 398 comes the special case for >= 4.3, which sets 0x3d : 0x01; [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers/-/blob/DISPLAY.LA.2.0.r1-08400-WAIPIO.0/msm/dsi/dsi_phy_hw_v4_0.c#L378 This big if/switch is a little bit excessive, but I thought it might be easier to review it this way. I might still merge some of the clauses. Would you find the following code part cleaner to review/compare? glbl_str_swi_cal_sel_ctrl = 0x00; if (phy->cphy_mode) { vreg_ctrl_0 = 0x51; vreg_ctrl_1 = 0x55; glbl_pemph_ctrl_0 = 0x11; glbl_hstx_str_ctrl_0 = 0x00; lane_ctrl0 = 0x17; } else { vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; vreg_ctrl_1 = 0x5c; glbl_pemph_ctrl_0 = 0x00; glbl_hstx_str_ctrl_0 = 0x88; lane_ctrl0 = 0x1f; } if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { if (phy->cphy_mode) { glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; } else { glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; } } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) { if (phy->cphy_mode) { glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; } else { glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x00; glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; } } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { if (phy->cphy_mode) { glbl_rescode_top_ctrl = 0x00; glbl_rescode_bot_ctrl = 0x3c; glbl_hstx_str_ctrl_0 = 0x88; } else { glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00; glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c; } } else { if (phy->cphy_mode) { glbl_str_swi_cal_sel_ctrl = 0x03; glbl_hstx_str_ctrl_0 = 0x66; } else { vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00; glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88; } glbl_rescode_top_ctrl = 0x03; glbl_rescode_bot_ctrl = 0x3c; } > > >> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; >> + glbl_str_swi_cal_sel_ctrl = 0x00; >> + glbl_hstx_str_ctrl_0 = 0x88; >> + } >> + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) { >> + if (phy->cphy_mode) { >> + vreg_ctrl_0 = 0x51; >> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; >> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; >> + glbl_str_swi_cal_sel_ctrl = 0x00; >> + glbl_hstx_str_ctrl_0 = 0x00; >> + } else { >> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; >> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x00; >> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; >> + glbl_str_swi_cal_sel_ctrl = 0x00; >> + glbl_hstx_str_ctrl_0 = 0x88; >> + } >> + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { >> if (phy->cphy_mode) { >> + vreg_ctrl_0 = 0x51; >> glbl_rescode_top_ctrl = 0x00; >> glbl_rescode_bot_ctrl = 0x3c; >> } else { >> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; >> glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00; >> glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c; >> } >> glbl_str_swi_cal_sel_ctrl = 0x00; >> glbl_hstx_str_ctrl_0 = 0x88; >> } else { >> - vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; >> if (phy->cphy_mode) { >> + vreg_ctrl_0 = 0x51; >> glbl_str_swi_cal_sel_ctrl = 0x03; >> glbl_hstx_str_ctrl_0 = 0x66; >> } else { >> + vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; >> glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : >> 0x00; >> glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88; >> } >> @@ -883,7 +934,6 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy >> *phy, >> } >> if (phy->cphy_mode) { >> - vreg_ctrl_0 = 0x51; >> vreg_ctrl_1 = 0x55; >> glbl_pemph_ctrl_0 = 0x11; >> lane_ctrl0 = 0x17; >> @@ -1017,6 +1067,13 @@ static void dsi_7nm_phy_disable(struct >> msm_dsi_phy *phy) >> pr_warn("Turning OFF PHY while PLL is on\n"); >> dsi_phy_hw_v4_0_config_lpcdrx(phy, false); >> + >> + /* Turn off REFGEN Vote */ >> + dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, >> 0x0); >> + wmb(); >> + /* Delay to ensure HW removes vote before PHY shut down */ >> + udelay(2); > > Either thunderbird is acting up (again) or the code after the first > comment is > > indented with spaces instead of tabs. > > > Other than that, > > Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> > > > Konrad > >> + >> data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_CTRL_0); >> /* disable all lanes */ >> @@ -1040,6 +1097,10 @@ static const struct regulator_bulk_data >> dsi_phy_7nm_37750uA_regulators[] = { >> { .supply = "vdds", .init_load_uA = 37550 }, >> }; >> +static const struct regulator_bulk_data >> dsi_phy_7nm_97800uA_regulators[] = { >> + { .supply = "vdds", .init_load_uA = 97800}, >> +}; >> + >> const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { >> .has_phy_lane = true, >> .regulator_data = dsi_phy_7nm_36mA_regulators, >> @@ -1079,6 +1140,7 @@ const struct msm_dsi_phy_cfg >> dsi_phy_7nm_8150_cfgs = { >> .max_pll_rate = 3500000000UL, >> .io_start = { 0xae94400, 0xae96400 }, >> .num_dsi_phy = 2, >> + .quirks = DSI_PHY_7NM_QUIRK_PRE_V4_1, >> }; >> const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = { >> @@ -1102,3 +1164,49 @@ const struct msm_dsi_phy_cfg >> dsi_phy_7nm_7280_cfgs = { >> .num_dsi_phy = 1, >> .quirks = DSI_PHY_7NM_QUIRK_V4_1, >> }; >> + >> +const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs = { >> + .has_phy_lane = true, >> + .regulator_data = dsi_phy_7nm_37750uA_regulators, >> + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_37750uA_regulators), >> + .ops = { >> + .enable = dsi_7nm_phy_enable, >> + .disable = dsi_7nm_phy_disable, >> + .pll_init = dsi_pll_7nm_init, >> + .save_pll_state = dsi_7nm_pll_save_state, >> + .restore_pll_state = dsi_7nm_pll_restore_state, >> + .set_continuous_clock = dsi_7nm_set_continuous_clock, >> + }, >> + .min_pll_rate = 600000000UL, >> +#ifdef CONFIG_64BIT >> + .max_pll_rate = 5000000000UL, >> +#else >> + .max_pll_rate = ULONG_MAX, >> +#endif >> + .io_start = { 0xae94400, 0xae96400 }, >> + .num_dsi_phy = 2, >> + .quirks = DSI_PHY_7NM_QUIRK_V4_2, >> +}; >> + >> +const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = { >> + .has_phy_lane = true, >> + .regulator_data = dsi_phy_7nm_97800uA_regulators, >> + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_97800uA_regulators), >> + .ops = { >> + .enable = dsi_7nm_phy_enable, >> + .disable = dsi_7nm_phy_disable, >> + .pll_init = dsi_pll_7nm_init, >> + .save_pll_state = dsi_7nm_pll_save_state, >> + .restore_pll_state = dsi_7nm_pll_restore_state, >> + .set_continuous_clock = dsi_7nm_set_continuous_clock, >> + }, >> + .min_pll_rate = 600000000UL, >> +#ifdef CONFIG_64BIT >> + .max_pll_rate = 5000000000UL, >> +#else >> + .max_pll_rate = ULONG_MAX, >> +#endif >> + .io_start = { 0xae94400, 0xae96400 }, >> + .num_dsi_phy = 2, >> + .quirks = DSI_PHY_7NM_QUIRK_V4_3, >> +}; -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 4/8] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450 @ 2022-11-10 22:16 ` Dmitry Baryshkov 0 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-10 22:16 UTC (permalink / raw) To: Konrad Dybcio, Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, Robert Foss, freedreno On 04/11/2022 16:54, Konrad Dybcio wrote: > > On 04/11/2022 14:03, Dmitry Baryshkov wrote: >> SM8350 and SM8450 use 5nm DSI PHYs, which share register definitions >> with 7nm DSI PHYs. Rather than duplicating the driver, handle 5nm >> variants inside the common 5+7nm driver. >> >> Co-developed-by: Robert Foss <robert.foss@linaro.org> >> Tested-by: Vinod Koul <vkoul@kernel.org> >> Reviewed-by: Vinod Koul <vkoul@kernel.org> >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> --- >> drivers/gpu/drm/msm/Kconfig | 6 +- >> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 + >> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 + >> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 128 ++++++++++++++++++++-- >> 4 files changed, 127 insertions(+), 13 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig >> index 3c9dfdb0b328..e7b100d97f88 100644 >> --- a/drivers/gpu/drm/msm/Kconfig >> +++ b/drivers/gpu/drm/msm/Kconfig >> @@ -140,12 +140,12 @@ config DRM_MSM_DSI_10NM_PHY >> Choose this option if DSI PHY on SDM845 is used on the platform. >> config DRM_MSM_DSI_7NM_PHY >> - bool "Enable DSI 7nm PHY driver in MSM DRM" >> + bool "Enable DSI 7nm/5nm PHY driver in MSM DRM" >> depends on DRM_MSM_DSI >> default y >> help >> - Choose this option if DSI PHY on SM8150/SM8250/SC7280 is used on >> - the platform. >> + Choose this option if DSI PHY on >> SM8150/SM8250/SM8350/SM8450/SC7280 >> + is used on the platform. >> config DRM_MSM_HDMI >> bool "Enable HDMI support in MSM DRM driver" >> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >> index ee6051367679..0c956fdab23e 100644 >> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >> @@ -569,6 +569,10 @@ static const struct of_device_id >> dsi_phy_dt_match[] = { >> .data = &dsi_phy_7nm_8150_cfgs }, >> { .compatible = "qcom,sc7280-dsi-phy-7nm", >> .data = &dsi_phy_7nm_7280_cfgs }, >> + { .compatible = "qcom,dsi-phy-5nm-8350", >> + .data = &dsi_phy_5nm_8350_cfgs }, >> + { .compatible = "qcom,dsi-phy-5nm-8450", >> + .data = &dsi_phy_5nm_8450_cfgs }, >> #endif >> {} >> }; >> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >> index 1096afedd616..f7a907ed2b4b 100644 >> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >> @@ -57,6 +57,8 @@ extern const struct msm_dsi_phy_cfg >> dsi_phy_10nm_8998_cfgs; >> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs; >> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs; >> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs; >> +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; >> +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; >> struct msm_dsi_dphy_timing { >> u32 clk_zero; >> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >> index 9e7fa7d88ead..00d92fe97bc3 100644 >> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >> @@ -39,8 +39,14 @@ >> #define VCO_REF_CLK_RATE 19200000 >> #define FRAC_BITS 18 >> +/* Hardware is pre V4.1 */ >> +#define DSI_PHY_7NM_QUIRK_PRE_V4_1 BIT(0) >> /* Hardware is V4.1 */ >> -#define DSI_PHY_7NM_QUIRK_V4_1 BIT(0) >> +#define DSI_PHY_7NM_QUIRK_V4_1 BIT(1) >> +/* Hardware is V4.2 */ >> +#define DSI_PHY_7NM_QUIRK_V4_2 BIT(2) >> +/* Hardware is V4.3 */ >> +#define DSI_PHY_7NM_QUIRK_V4_3 BIT(3) > > Quirk is quite an unfortunate name considering what we use it for.. but I > > suppose it can stay, as otherwise even more renaming would have to be done. > > >> struct dsi_pll_config { >> bool enable_ssc; >> @@ -116,7 +122,7 @@ static void dsi_pll_calc_dec_frac(struct >> dsi_pll_7nm *pll, struct dsi_pll_config >> dec_multiple = div_u64(pll_freq * multiplier, divider); >> dec = div_u64_rem(dec_multiple, multiplier, &frac); >> - if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)) >> + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) >> config->pll_clock_inverters = 0x28; >> else if (pll_freq <= 1000000000ULL) >> config->pll_clock_inverters = 0xa0; >> @@ -197,16 +203,25 @@ static void dsi_pll_config_hzindep_reg(struct >> dsi_pll_7nm *pll) >> void __iomem *base = pll->phy->pll_base; >> u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00; >> - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { >> + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) >> if (pll->vco_current_rate >= 3100000000ULL) >> analog_controls_five_1 = 0x03; >> + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { >> if (pll->vco_current_rate < 1520000000ULL) >> vco_config_1 = 0x08; >> else if (pll->vco_current_rate < 2990000000ULL) >> vco_config_1 = 0x01; >> } >> + if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) || >> + (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) { >> + if (pll->vco_current_rate < 1520000000ULL) >> + vco_config_1 = 0x08; >> + else if (pll->vco_current_rate >= 2990000000ULL) >> + vco_config_1 = 0x01; >> + } >> + >> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1, >> analog_controls_five_1); >> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, >> vco_config_1); >> @@ -231,9 +246,9 @@ static void dsi_pll_config_hzindep_reg(struct >> dsi_pll_7nm *pll) >> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f); >> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a); >> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, >> - pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22); >> + !(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) ? >> 0x3f : 0x22); >> - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { >> + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) { >> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); >> if (pll->slave) >> dsi_phy_write(pll->slave->phy->pll_base + >> REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); >> @@ -788,7 +803,7 @@ static void dsi_phy_hw_v4_0_lane_settings(struct >> msm_dsi_phy *phy) >> const u8 *tx_dctrl = tx_dctrl_0; >> void __iomem *lane_base = phy->lane_base; >> - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) >> + if (!(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) >> tx_dctrl = tx_dctrl_1; >> /* Strength ctrl settings */ >> @@ -844,6 +859,12 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy >> *phy, >> if (dsi_phy_hw_v4_0_is_pll_on(phy)) >> pr_warn("PLL turned on before configuring PHY\n"); >> + /* Request for REFGEN READY */ >> + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { >> + dsi_phy_write(phy->base + >> REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x1); >> + udelay(500); >> + } >> + >> /* wait for REFGEN READY */ >> ret = readl_poll_timeout_atomic(base + >> REG_DSI_7nm_PHY_CMN_PHY_STATUS, >> status, (status & BIT(0)), >> @@ -858,23 +879,53 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy >> *phy, >> /* Alter PHY configurations if data rate less than 1.5GHZ*/ >> less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000); >> - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { >> - vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; >> + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { >> + if (phy->cphy_mode) { >> + vreg_ctrl_0 = 0x51; >> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; >> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; >> + glbl_str_swi_cal_sel_ctrl = 0x00; >> + glbl_hstx_str_ctrl_0 = 0x00; >> + } else { >> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; >> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; > > msm-5.10 has it as 0x3d : 0x00 for both v4.2 and v4.3 in DPHY mode Checking with the latest display-drivers sources at [1]: There is a common code block using 0x3c : 0x00, but after that at line 398 comes the special case for >= 4.3, which sets 0x3d : 0x01; [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers/-/blob/DISPLAY.LA.2.0.r1-08400-WAIPIO.0/msm/dsi/dsi_phy_hw_v4_0.c#L378 This big if/switch is a little bit excessive, but I thought it might be easier to review it this way. I might still merge some of the clauses. Would you find the following code part cleaner to review/compare? glbl_str_swi_cal_sel_ctrl = 0x00; if (phy->cphy_mode) { vreg_ctrl_0 = 0x51; vreg_ctrl_1 = 0x55; glbl_pemph_ctrl_0 = 0x11; glbl_hstx_str_ctrl_0 = 0x00; lane_ctrl0 = 0x17; } else { vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; vreg_ctrl_1 = 0x5c; glbl_pemph_ctrl_0 = 0x00; glbl_hstx_str_ctrl_0 = 0x88; lane_ctrl0 = 0x1f; } if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { if (phy->cphy_mode) { glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; } else { glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; } } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) { if (phy->cphy_mode) { glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; } else { glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x00; glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; } } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { if (phy->cphy_mode) { glbl_rescode_top_ctrl = 0x00; glbl_rescode_bot_ctrl = 0x3c; glbl_hstx_str_ctrl_0 = 0x88; } else { glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00; glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c; } } else { if (phy->cphy_mode) { glbl_str_swi_cal_sel_ctrl = 0x03; glbl_hstx_str_ctrl_0 = 0x66; } else { vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00; glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88; } glbl_rescode_top_ctrl = 0x03; glbl_rescode_bot_ctrl = 0x3c; } > > >> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; >> + glbl_str_swi_cal_sel_ctrl = 0x00; >> + glbl_hstx_str_ctrl_0 = 0x88; >> + } >> + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) { >> + if (phy->cphy_mode) { >> + vreg_ctrl_0 = 0x51; >> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; >> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; >> + glbl_str_swi_cal_sel_ctrl = 0x00; >> + glbl_hstx_str_ctrl_0 = 0x00; >> + } else { >> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; >> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x00; >> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; >> + glbl_str_swi_cal_sel_ctrl = 0x00; >> + glbl_hstx_str_ctrl_0 = 0x88; >> + } >> + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { >> if (phy->cphy_mode) { >> + vreg_ctrl_0 = 0x51; >> glbl_rescode_top_ctrl = 0x00; >> glbl_rescode_bot_ctrl = 0x3c; >> } else { >> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; >> glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00; >> glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c; >> } >> glbl_str_swi_cal_sel_ctrl = 0x00; >> glbl_hstx_str_ctrl_0 = 0x88; >> } else { >> - vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; >> if (phy->cphy_mode) { >> + vreg_ctrl_0 = 0x51; >> glbl_str_swi_cal_sel_ctrl = 0x03; >> glbl_hstx_str_ctrl_0 = 0x66; >> } else { >> + vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; >> glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : >> 0x00; >> glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88; >> } >> @@ -883,7 +934,6 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy >> *phy, >> } >> if (phy->cphy_mode) { >> - vreg_ctrl_0 = 0x51; >> vreg_ctrl_1 = 0x55; >> glbl_pemph_ctrl_0 = 0x11; >> lane_ctrl0 = 0x17; >> @@ -1017,6 +1067,13 @@ static void dsi_7nm_phy_disable(struct >> msm_dsi_phy *phy) >> pr_warn("Turning OFF PHY while PLL is on\n"); >> dsi_phy_hw_v4_0_config_lpcdrx(phy, false); >> + >> + /* Turn off REFGEN Vote */ >> + dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, >> 0x0); >> + wmb(); >> + /* Delay to ensure HW removes vote before PHY shut down */ >> + udelay(2); > > Either thunderbird is acting up (again) or the code after the first > comment is > > indented with spaces instead of tabs. > > > Other than that, > > Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> > > > Konrad > >> + >> data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_CTRL_0); >> /* disable all lanes */ >> @@ -1040,6 +1097,10 @@ static const struct regulator_bulk_data >> dsi_phy_7nm_37750uA_regulators[] = { >> { .supply = "vdds", .init_load_uA = 37550 }, >> }; >> +static const struct regulator_bulk_data >> dsi_phy_7nm_97800uA_regulators[] = { >> + { .supply = "vdds", .init_load_uA = 97800}, >> +}; >> + >> const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { >> .has_phy_lane = true, >> .regulator_data = dsi_phy_7nm_36mA_regulators, >> @@ -1079,6 +1140,7 @@ const struct msm_dsi_phy_cfg >> dsi_phy_7nm_8150_cfgs = { >> .max_pll_rate = 3500000000UL, >> .io_start = { 0xae94400, 0xae96400 }, >> .num_dsi_phy = 2, >> + .quirks = DSI_PHY_7NM_QUIRK_PRE_V4_1, >> }; >> const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = { >> @@ -1102,3 +1164,49 @@ const struct msm_dsi_phy_cfg >> dsi_phy_7nm_7280_cfgs = { >> .num_dsi_phy = 1, >> .quirks = DSI_PHY_7NM_QUIRK_V4_1, >> }; >> + >> +const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs = { >> + .has_phy_lane = true, >> + .regulator_data = dsi_phy_7nm_37750uA_regulators, >> + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_37750uA_regulators), >> + .ops = { >> + .enable = dsi_7nm_phy_enable, >> + .disable = dsi_7nm_phy_disable, >> + .pll_init = dsi_pll_7nm_init, >> + .save_pll_state = dsi_7nm_pll_save_state, >> + .restore_pll_state = dsi_7nm_pll_restore_state, >> + .set_continuous_clock = dsi_7nm_set_continuous_clock, >> + }, >> + .min_pll_rate = 600000000UL, >> +#ifdef CONFIG_64BIT >> + .max_pll_rate = 5000000000UL, >> +#else >> + .max_pll_rate = ULONG_MAX, >> +#endif >> + .io_start = { 0xae94400, 0xae96400 }, >> + .num_dsi_phy = 2, >> + .quirks = DSI_PHY_7NM_QUIRK_V4_2, >> +}; >> + >> +const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = { >> + .has_phy_lane = true, >> + .regulator_data = dsi_phy_7nm_97800uA_regulators, >> + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_97800uA_regulators), >> + .ops = { >> + .enable = dsi_7nm_phy_enable, >> + .disable = dsi_7nm_phy_disable, >> + .pll_init = dsi_pll_7nm_init, >> + .save_pll_state = dsi_7nm_pll_save_state, >> + .restore_pll_state = dsi_7nm_pll_restore_state, >> + .set_continuous_clock = dsi_7nm_set_continuous_clock, >> + }, >> + .min_pll_rate = 600000000UL, >> +#ifdef CONFIG_64BIT >> + .max_pll_rate = 5000000000UL, >> +#else >> + .max_pll_rate = ULONG_MAX, >> +#endif >> + .io_start = { 0xae94400, 0xae96400 }, >> + .num_dsi_phy = 2, >> + .quirks = DSI_PHY_7NM_QUIRK_V4_3, >> +}; -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 4/8] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450 2022-11-10 22:16 ` Dmitry Baryshkov @ 2022-11-14 16:13 ` Konrad Dybcio -1 siblings, 0 replies; 62+ messages in thread From: Konrad Dybcio @ 2022-11-14 16:13 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Robert Foss, Vinod Koul On 10/11/2022 23:16, Dmitry Baryshkov wrote: > On 04/11/2022 16:54, Konrad Dybcio wrote: >> >> On 04/11/2022 14:03, Dmitry Baryshkov wrote: >>> SM8350 and SM8450 use 5nm DSI PHYs, which share register definitions >>> with 7nm DSI PHYs. Rather than duplicating the driver, handle 5nm >>> variants inside the common 5+7nm driver. >>> >>> Co-developed-by: Robert Foss <robert.foss@linaro.org> >>> Tested-by: Vinod Koul <vkoul@kernel.org> >>> Reviewed-by: Vinod Koul <vkoul@kernel.org> >>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>> --- >>> drivers/gpu/drm/msm/Kconfig | 6 +- >>> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 + >>> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 + >>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 128 ++++++++++++++++++++-- >>> 4 files changed, 127 insertions(+), 13 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig >>> index 3c9dfdb0b328..e7b100d97f88 100644 >>> --- a/drivers/gpu/drm/msm/Kconfig >>> +++ b/drivers/gpu/drm/msm/Kconfig >>> @@ -140,12 +140,12 @@ config DRM_MSM_DSI_10NM_PHY >>> Choose this option if DSI PHY on SDM845 is used on the platform. >>> config DRM_MSM_DSI_7NM_PHY >>> - bool "Enable DSI 7nm PHY driver in MSM DRM" >>> + bool "Enable DSI 7nm/5nm PHY driver in MSM DRM" >>> depends on DRM_MSM_DSI >>> default y >>> help >>> - Choose this option if DSI PHY on SM8150/SM8250/SC7280 is used on >>> - the platform. >>> + Choose this option if DSI PHY on >>> SM8150/SM8250/SM8350/SM8450/SC7280 >>> + is used on the platform. >>> config DRM_MSM_HDMI >>> bool "Enable HDMI support in MSM DRM driver" >>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >>> index ee6051367679..0c956fdab23e 100644 >>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >>> @@ -569,6 +569,10 @@ static const struct of_device_id >>> dsi_phy_dt_match[] = { >>> .data = &dsi_phy_7nm_8150_cfgs }, >>> { .compatible = "qcom,sc7280-dsi-phy-7nm", >>> .data = &dsi_phy_7nm_7280_cfgs }, >>> + { .compatible = "qcom,dsi-phy-5nm-8350", >>> + .data = &dsi_phy_5nm_8350_cfgs }, >>> + { .compatible = "qcom,dsi-phy-5nm-8450", >>> + .data = &dsi_phy_5nm_8450_cfgs }, >>> #endif >>> {} >>> }; >>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >>> index 1096afedd616..f7a907ed2b4b 100644 >>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >>> @@ -57,6 +57,8 @@ extern const struct msm_dsi_phy_cfg >>> dsi_phy_10nm_8998_cfgs; >>> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs; >>> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs; >>> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs; >>> +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; >>> +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; >>> struct msm_dsi_dphy_timing { >>> u32 clk_zero; >>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >>> index 9e7fa7d88ead..00d92fe97bc3 100644 >>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >>> @@ -39,8 +39,14 @@ >>> #define VCO_REF_CLK_RATE 19200000 >>> #define FRAC_BITS 18 >>> +/* Hardware is pre V4.1 */ >>> +#define DSI_PHY_7NM_QUIRK_PRE_V4_1 BIT(0) >>> /* Hardware is V4.1 */ >>> -#define DSI_PHY_7NM_QUIRK_V4_1 BIT(0) >>> +#define DSI_PHY_7NM_QUIRK_V4_1 BIT(1) >>> +/* Hardware is V4.2 */ >>> +#define DSI_PHY_7NM_QUIRK_V4_2 BIT(2) >>> +/* Hardware is V4.3 */ >>> +#define DSI_PHY_7NM_QUIRK_V4_3 BIT(3) >> >> Quirk is quite an unfortunate name considering what we use it for.. but I >> >> suppose it can stay, as otherwise even more renaming would have to be >> done. >> >> >>> struct dsi_pll_config { >>> bool enable_ssc; >>> @@ -116,7 +122,7 @@ static void dsi_pll_calc_dec_frac(struct >>> dsi_pll_7nm *pll, struct dsi_pll_config >>> dec_multiple = div_u64(pll_freq * multiplier, divider); >>> dec = div_u64_rem(dec_multiple, multiplier, &frac); >>> - if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)) >>> + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) >>> config->pll_clock_inverters = 0x28; >>> else if (pll_freq <= 1000000000ULL) >>> config->pll_clock_inverters = 0xa0; >>> @@ -197,16 +203,25 @@ static void dsi_pll_config_hzindep_reg(struct >>> dsi_pll_7nm *pll) >>> void __iomem *base = pll->phy->pll_base; >>> u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00; >>> - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { >>> + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) >>> if (pll->vco_current_rate >= 3100000000ULL) >>> analog_controls_five_1 = 0x03; >>> + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { >>> if (pll->vco_current_rate < 1520000000ULL) >>> vco_config_1 = 0x08; >>> else if (pll->vco_current_rate < 2990000000ULL) >>> vco_config_1 = 0x01; >>> } >>> + if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) || >>> + (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) { >>> + if (pll->vco_current_rate < 1520000000ULL) >>> + vco_config_1 = 0x08; >>> + else if (pll->vco_current_rate >= 2990000000ULL) >>> + vco_config_1 = 0x01; >>> + } >>> + >>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1, >>> analog_controls_five_1); >>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, >>> vco_config_1); >>> @@ -231,9 +246,9 @@ static void dsi_pll_config_hzindep_reg(struct >>> dsi_pll_7nm *pll) >>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f); >>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a); >>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, >>> - pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : >>> 0x22); >>> + !(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) ? >>> 0x3f : 0x22); >>> - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { >>> + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) { >>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); >>> if (pll->slave) >>> dsi_phy_write(pll->slave->phy->pll_base + >>> REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); >>> @@ -788,7 +803,7 @@ static void dsi_phy_hw_v4_0_lane_settings(struct >>> msm_dsi_phy *phy) >>> const u8 *tx_dctrl = tx_dctrl_0; >>> void __iomem *lane_base = phy->lane_base; >>> - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) >>> + if (!(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) >>> tx_dctrl = tx_dctrl_1; >>> /* Strength ctrl settings */ >>> @@ -844,6 +859,12 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy >>> *phy, >>> if (dsi_phy_hw_v4_0_is_pll_on(phy)) >>> pr_warn("PLL turned on before configuring PHY\n"); >>> + /* Request for REFGEN READY */ >>> + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { >>> + dsi_phy_write(phy->base + >>> REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x1); >>> + udelay(500); >>> + } >>> + >>> /* wait for REFGEN READY */ >>> ret = readl_poll_timeout_atomic(base + >>> REG_DSI_7nm_PHY_CMN_PHY_STATUS, >>> status, (status & BIT(0)), >>> @@ -858,23 +879,53 @@ static int dsi_7nm_phy_enable(struct >>> msm_dsi_phy *phy, >>> /* Alter PHY configurations if data rate less than 1.5GHZ*/ >>> less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000); >>> - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { >>> - vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; >>> + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { >>> + if (phy->cphy_mode) { >>> + vreg_ctrl_0 = 0x51; >>> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; >>> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; >>> + glbl_str_swi_cal_sel_ctrl = 0x00; >>> + glbl_hstx_str_ctrl_0 = 0x00; >>> + } else { >>> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; >>> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; >> >> msm-5.10 has it as 0x3d : 0x00 for both v4.2 and v4.3 in DPHY mode > > Checking with the latest display-drivers sources at [1]: > > There is a common code block using 0x3c : 0x00, but after that at line > 398 comes the special case for >= 4.3, which sets 0x3d : 0x01; Ack. > > > [1] > https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers/-/blob/DISPLAY.LA.2.0.r1-08400-WAIPIO.0/msm/dsi/dsi_phy_hw_v4_0.c#L378 > > This big if/switch is a little bit excessive, but I thought it might be > easier to review it this way. I might still merge some of the clauses. > > Would you find the following code part cleaner to review/compare? > > glbl_str_swi_cal_sel_ctrl = 0x00; > if (phy->cphy_mode) { > vreg_ctrl_0 = 0x51; > vreg_ctrl_1 = 0x55; > glbl_pemph_ctrl_0 = 0x11; > glbl_hstx_str_ctrl_0 = 0x00; > lane_ctrl0 = 0x17; > } else { > vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; > vreg_ctrl_1 = 0x5c; > glbl_pemph_ctrl_0 = 0x00; > glbl_hstx_str_ctrl_0 = 0x88; > lane_ctrl0 = 0x1f; > } > > if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { > if (phy->cphy_mode) { > glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; > glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; > } else { > glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; > glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; > } > } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) { > if (phy->cphy_mode) { > glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; > glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; > } else { > glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x00; > glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; > } > } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { > if (phy->cphy_mode) { > glbl_rescode_top_ctrl = 0x00; > glbl_rescode_bot_ctrl = 0x3c; > glbl_hstx_str_ctrl_0 = 0x88; > } else { > glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00; > glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c; > } > } else { > if (phy->cphy_mode) { > glbl_str_swi_cal_sel_ctrl = 0x03; > glbl_hstx_str_ctrl_0 = 0x66; > } else { > vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; > glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00; > glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88; > } > glbl_rescode_top_ctrl = 0x03; > glbl_rescode_bot_ctrl = 0x3c; > } This looks much easier to read, yes. Konrad > > >> >> >>> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; >>> + glbl_str_swi_cal_sel_ctrl = 0x00; >>> + glbl_hstx_str_ctrl_0 = 0x88; >>> + } >>> + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) { >>> + if (phy->cphy_mode) { >>> + vreg_ctrl_0 = 0x51; >>> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; >>> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; >>> + glbl_str_swi_cal_sel_ctrl = 0x00; >>> + glbl_hstx_str_ctrl_0 = 0x00; >>> + } else { >>> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; >>> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x00; >>> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; >>> + glbl_str_swi_cal_sel_ctrl = 0x00; >>> + glbl_hstx_str_ctrl_0 = 0x88; >>> + } >>> + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { >>> if (phy->cphy_mode) { >>> + vreg_ctrl_0 = 0x51; >>> glbl_rescode_top_ctrl = 0x00; >>> glbl_rescode_bot_ctrl = 0x3c; >>> } else { >>> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; >>> glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00; >>> glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c; >>> } >>> glbl_str_swi_cal_sel_ctrl = 0x00; >>> glbl_hstx_str_ctrl_0 = 0x88; >>> } else { >>> - vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; >>> if (phy->cphy_mode) { >>> + vreg_ctrl_0 = 0x51; >>> glbl_str_swi_cal_sel_ctrl = 0x03; >>> glbl_hstx_str_ctrl_0 = 0x66; >>> } else { >>> + vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; >>> glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : >>> 0x00; >>> glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88; >>> } >>> @@ -883,7 +934,6 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy >>> *phy, >>> } >>> if (phy->cphy_mode) { >>> - vreg_ctrl_0 = 0x51; >>> vreg_ctrl_1 = 0x55; >>> glbl_pemph_ctrl_0 = 0x11; >>> lane_ctrl0 = 0x17; >>> @@ -1017,6 +1067,13 @@ static void dsi_7nm_phy_disable(struct >>> msm_dsi_phy *phy) >>> pr_warn("Turning OFF PHY while PLL is on\n"); >>> dsi_phy_hw_v4_0_config_lpcdrx(phy, false); >>> + >>> + /* Turn off REFGEN Vote */ >>> + dsi_phy_write(base + >>> REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x0); >>> + wmb(); >>> + /* Delay to ensure HW removes vote before PHY shut down */ >>> + udelay(2); >> >> Either thunderbird is acting up (again) or the code after the first >> comment is >> >> indented with spaces instead of tabs. >> >> >> Other than that, >> >> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> >> >> >> Konrad >> >>> + >>> data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_CTRL_0); >>> /* disable all lanes */ >>> @@ -1040,6 +1097,10 @@ static const struct regulator_bulk_data >>> dsi_phy_7nm_37750uA_regulators[] = { >>> { .supply = "vdds", .init_load_uA = 37550 }, >>> }; >>> +static const struct regulator_bulk_data >>> dsi_phy_7nm_97800uA_regulators[] = { >>> + { .supply = "vdds", .init_load_uA = 97800}, >>> +}; >>> + >>> const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { >>> .has_phy_lane = true, >>> .regulator_data = dsi_phy_7nm_36mA_regulators, >>> @@ -1079,6 +1140,7 @@ const struct msm_dsi_phy_cfg >>> dsi_phy_7nm_8150_cfgs = { >>> .max_pll_rate = 3500000000UL, >>> .io_start = { 0xae94400, 0xae96400 }, >>> .num_dsi_phy = 2, >>> + .quirks = DSI_PHY_7NM_QUIRK_PRE_V4_1, >>> }; >>> const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = { >>> @@ -1102,3 +1164,49 @@ const struct msm_dsi_phy_cfg >>> dsi_phy_7nm_7280_cfgs = { >>> .num_dsi_phy = 1, >>> .quirks = DSI_PHY_7NM_QUIRK_V4_1, >>> }; >>> + >>> +const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs = { >>> + .has_phy_lane = true, >>> + .regulator_data = dsi_phy_7nm_37750uA_regulators, >>> + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_37750uA_regulators), >>> + .ops = { >>> + .enable = dsi_7nm_phy_enable, >>> + .disable = dsi_7nm_phy_disable, >>> + .pll_init = dsi_pll_7nm_init, >>> + .save_pll_state = dsi_7nm_pll_save_state, >>> + .restore_pll_state = dsi_7nm_pll_restore_state, >>> + .set_continuous_clock = dsi_7nm_set_continuous_clock, >>> + }, >>> + .min_pll_rate = 600000000UL, >>> +#ifdef CONFIG_64BIT >>> + .max_pll_rate = 5000000000UL, >>> +#else >>> + .max_pll_rate = ULONG_MAX, >>> +#endif >>> + .io_start = { 0xae94400, 0xae96400 }, >>> + .num_dsi_phy = 2, >>> + .quirks = DSI_PHY_7NM_QUIRK_V4_2, >>> +}; >>> + >>> +const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = { >>> + .has_phy_lane = true, >>> + .regulator_data = dsi_phy_7nm_97800uA_regulators, >>> + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_97800uA_regulators), >>> + .ops = { >>> + .enable = dsi_7nm_phy_enable, >>> + .disable = dsi_7nm_phy_disable, >>> + .pll_init = dsi_pll_7nm_init, >>> + .save_pll_state = dsi_7nm_pll_save_state, >>> + .restore_pll_state = dsi_7nm_pll_restore_state, >>> + .set_continuous_clock = dsi_7nm_set_continuous_clock, >>> + }, >>> + .min_pll_rate = 600000000UL, >>> +#ifdef CONFIG_64BIT >>> + .max_pll_rate = 5000000000UL, >>> +#else >>> + .max_pll_rate = ULONG_MAX, >>> +#endif >>> + .io_start = { 0xae94400, 0xae96400 }, >>> + .num_dsi_phy = 2, >>> + .quirks = DSI_PHY_7NM_QUIRK_V4_3, >>> +}; > ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 4/8] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450 @ 2022-11-14 16:13 ` Konrad Dybcio 0 siblings, 0 replies; 62+ messages in thread From: Konrad Dybcio @ 2022-11-14 16:13 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, Robert Foss, freedreno On 10/11/2022 23:16, Dmitry Baryshkov wrote: > On 04/11/2022 16:54, Konrad Dybcio wrote: >> >> On 04/11/2022 14:03, Dmitry Baryshkov wrote: >>> SM8350 and SM8450 use 5nm DSI PHYs, which share register definitions >>> with 7nm DSI PHYs. Rather than duplicating the driver, handle 5nm >>> variants inside the common 5+7nm driver. >>> >>> Co-developed-by: Robert Foss <robert.foss@linaro.org> >>> Tested-by: Vinod Koul <vkoul@kernel.org> >>> Reviewed-by: Vinod Koul <vkoul@kernel.org> >>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>> --- >>> drivers/gpu/drm/msm/Kconfig | 6 +- >>> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 + >>> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 + >>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 128 ++++++++++++++++++++-- >>> 4 files changed, 127 insertions(+), 13 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig >>> index 3c9dfdb0b328..e7b100d97f88 100644 >>> --- a/drivers/gpu/drm/msm/Kconfig >>> +++ b/drivers/gpu/drm/msm/Kconfig >>> @@ -140,12 +140,12 @@ config DRM_MSM_DSI_10NM_PHY >>> Choose this option if DSI PHY on SDM845 is used on the platform. >>> config DRM_MSM_DSI_7NM_PHY >>> - bool "Enable DSI 7nm PHY driver in MSM DRM" >>> + bool "Enable DSI 7nm/5nm PHY driver in MSM DRM" >>> depends on DRM_MSM_DSI >>> default y >>> help >>> - Choose this option if DSI PHY on SM8150/SM8250/SC7280 is used on >>> - the platform. >>> + Choose this option if DSI PHY on >>> SM8150/SM8250/SM8350/SM8450/SC7280 >>> + is used on the platform. >>> config DRM_MSM_HDMI >>> bool "Enable HDMI support in MSM DRM driver" >>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >>> index ee6051367679..0c956fdab23e 100644 >>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c >>> @@ -569,6 +569,10 @@ static const struct of_device_id >>> dsi_phy_dt_match[] = { >>> .data = &dsi_phy_7nm_8150_cfgs }, >>> { .compatible = "qcom,sc7280-dsi-phy-7nm", >>> .data = &dsi_phy_7nm_7280_cfgs }, >>> + { .compatible = "qcom,dsi-phy-5nm-8350", >>> + .data = &dsi_phy_5nm_8350_cfgs }, >>> + { .compatible = "qcom,dsi-phy-5nm-8450", >>> + .data = &dsi_phy_5nm_8450_cfgs }, >>> #endif >>> {} >>> }; >>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >>> index 1096afedd616..f7a907ed2b4b 100644 >>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h >>> @@ -57,6 +57,8 @@ extern const struct msm_dsi_phy_cfg >>> dsi_phy_10nm_8998_cfgs; >>> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs; >>> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs; >>> extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs; >>> +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; >>> +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; >>> struct msm_dsi_dphy_timing { >>> u32 clk_zero; >>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >>> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >>> index 9e7fa7d88ead..00d92fe97bc3 100644 >>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >>> @@ -39,8 +39,14 @@ >>> #define VCO_REF_CLK_RATE 19200000 >>> #define FRAC_BITS 18 >>> +/* Hardware is pre V4.1 */ >>> +#define DSI_PHY_7NM_QUIRK_PRE_V4_1 BIT(0) >>> /* Hardware is V4.1 */ >>> -#define DSI_PHY_7NM_QUIRK_V4_1 BIT(0) >>> +#define DSI_PHY_7NM_QUIRK_V4_1 BIT(1) >>> +/* Hardware is V4.2 */ >>> +#define DSI_PHY_7NM_QUIRK_V4_2 BIT(2) >>> +/* Hardware is V4.3 */ >>> +#define DSI_PHY_7NM_QUIRK_V4_3 BIT(3) >> >> Quirk is quite an unfortunate name considering what we use it for.. but I >> >> suppose it can stay, as otherwise even more renaming would have to be >> done. >> >> >>> struct dsi_pll_config { >>> bool enable_ssc; >>> @@ -116,7 +122,7 @@ static void dsi_pll_calc_dec_frac(struct >>> dsi_pll_7nm *pll, struct dsi_pll_config >>> dec_multiple = div_u64(pll_freq * multiplier, divider); >>> dec = div_u64_rem(dec_multiple, multiplier, &frac); >>> - if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)) >>> + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) >>> config->pll_clock_inverters = 0x28; >>> else if (pll_freq <= 1000000000ULL) >>> config->pll_clock_inverters = 0xa0; >>> @@ -197,16 +203,25 @@ static void dsi_pll_config_hzindep_reg(struct >>> dsi_pll_7nm *pll) >>> void __iomem *base = pll->phy->pll_base; >>> u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00; >>> - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { >>> + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) >>> if (pll->vco_current_rate >= 3100000000ULL) >>> analog_controls_five_1 = 0x03; >>> + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { >>> if (pll->vco_current_rate < 1520000000ULL) >>> vco_config_1 = 0x08; >>> else if (pll->vco_current_rate < 2990000000ULL) >>> vco_config_1 = 0x01; >>> } >>> + if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) || >>> + (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) { >>> + if (pll->vco_current_rate < 1520000000ULL) >>> + vco_config_1 = 0x08; >>> + else if (pll->vco_current_rate >= 2990000000ULL) >>> + vco_config_1 = 0x01; >>> + } >>> + >>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1, >>> analog_controls_five_1); >>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, >>> vco_config_1); >>> @@ -231,9 +246,9 @@ static void dsi_pll_config_hzindep_reg(struct >>> dsi_pll_7nm *pll) >>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f); >>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a); >>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, >>> - pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : >>> 0x22); >>> + !(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) ? >>> 0x3f : 0x22); >>> - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { >>> + if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) { >>> dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); >>> if (pll->slave) >>> dsi_phy_write(pll->slave->phy->pll_base + >>> REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22); >>> @@ -788,7 +803,7 @@ static void dsi_phy_hw_v4_0_lane_settings(struct >>> msm_dsi_phy *phy) >>> const u8 *tx_dctrl = tx_dctrl_0; >>> void __iomem *lane_base = phy->lane_base; >>> - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) >>> + if (!(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)) >>> tx_dctrl = tx_dctrl_1; >>> /* Strength ctrl settings */ >>> @@ -844,6 +859,12 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy >>> *phy, >>> if (dsi_phy_hw_v4_0_is_pll_on(phy)) >>> pr_warn("PLL turned on before configuring PHY\n"); >>> + /* Request for REFGEN READY */ >>> + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { >>> + dsi_phy_write(phy->base + >>> REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x1); >>> + udelay(500); >>> + } >>> + >>> /* wait for REFGEN READY */ >>> ret = readl_poll_timeout_atomic(base + >>> REG_DSI_7nm_PHY_CMN_PHY_STATUS, >>> status, (status & BIT(0)), >>> @@ -858,23 +879,53 @@ static int dsi_7nm_phy_enable(struct >>> msm_dsi_phy *phy, >>> /* Alter PHY configurations if data rate less than 1.5GHZ*/ >>> less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000); >>> - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { >>> - vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; >>> + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { >>> + if (phy->cphy_mode) { >>> + vreg_ctrl_0 = 0x51; >>> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; >>> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; >>> + glbl_str_swi_cal_sel_ctrl = 0x00; >>> + glbl_hstx_str_ctrl_0 = 0x00; >>> + } else { >>> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; >>> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; >> >> msm-5.10 has it as 0x3d : 0x00 for both v4.2 and v4.3 in DPHY mode > > Checking with the latest display-drivers sources at [1]: > > There is a common code block using 0x3c : 0x00, but after that at line > 398 comes the special case for >= 4.3, which sets 0x3d : 0x01; Ack. > > > [1] > https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers/-/blob/DISPLAY.LA.2.0.r1-08400-WAIPIO.0/msm/dsi/dsi_phy_hw_v4_0.c#L378 > > This big if/switch is a little bit excessive, but I thought it might be > easier to review it this way. I might still merge some of the clauses. > > Would you find the following code part cleaner to review/compare? > > glbl_str_swi_cal_sel_ctrl = 0x00; > if (phy->cphy_mode) { > vreg_ctrl_0 = 0x51; > vreg_ctrl_1 = 0x55; > glbl_pemph_ctrl_0 = 0x11; > glbl_hstx_str_ctrl_0 = 0x00; > lane_ctrl0 = 0x17; > } else { > vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; > vreg_ctrl_1 = 0x5c; > glbl_pemph_ctrl_0 = 0x00; > glbl_hstx_str_ctrl_0 = 0x88; > lane_ctrl0 = 0x1f; > } > > if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { > if (phy->cphy_mode) { > glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; > glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; > } else { > glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; > glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; > } > } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) { > if (phy->cphy_mode) { > glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; > glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; > } else { > glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x00; > glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; > } > } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { > if (phy->cphy_mode) { > glbl_rescode_top_ctrl = 0x00; > glbl_rescode_bot_ctrl = 0x3c; > glbl_hstx_str_ctrl_0 = 0x88; > } else { > glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00; > glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c; > } > } else { > if (phy->cphy_mode) { > glbl_str_swi_cal_sel_ctrl = 0x03; > glbl_hstx_str_ctrl_0 = 0x66; > } else { > vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; > glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00; > glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88; > } > glbl_rescode_top_ctrl = 0x03; > glbl_rescode_bot_ctrl = 0x3c; > } This looks much easier to read, yes. Konrad > > >> >> >>> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; >>> + glbl_str_swi_cal_sel_ctrl = 0x00; >>> + glbl_hstx_str_ctrl_0 = 0x88; >>> + } >>> + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) { >>> + if (phy->cphy_mode) { >>> + vreg_ctrl_0 = 0x51; >>> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x01; >>> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3b; >>> + glbl_str_swi_cal_sel_ctrl = 0x00; >>> + glbl_hstx_str_ctrl_0 = 0x00; >>> + } else { >>> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; >>> + glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x00; >>> + glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x39; >>> + glbl_str_swi_cal_sel_ctrl = 0x00; >>> + glbl_hstx_str_ctrl_0 = 0x88; >>> + } >>> + } else if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { >>> if (phy->cphy_mode) { >>> + vreg_ctrl_0 = 0x51; >>> glbl_rescode_top_ctrl = 0x00; >>> glbl_rescode_bot_ctrl = 0x3c; >>> } else { >>> + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; >>> glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00; >>> glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c; >>> } >>> glbl_str_swi_cal_sel_ctrl = 0x00; >>> glbl_hstx_str_ctrl_0 = 0x88; >>> } else { >>> - vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; >>> if (phy->cphy_mode) { >>> + vreg_ctrl_0 = 0x51; >>> glbl_str_swi_cal_sel_ctrl = 0x03; >>> glbl_hstx_str_ctrl_0 = 0x66; >>> } else { >>> + vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; >>> glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : >>> 0x00; >>> glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88; >>> } >>> @@ -883,7 +934,6 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy >>> *phy, >>> } >>> if (phy->cphy_mode) { >>> - vreg_ctrl_0 = 0x51; >>> vreg_ctrl_1 = 0x55; >>> glbl_pemph_ctrl_0 = 0x11; >>> lane_ctrl0 = 0x17; >>> @@ -1017,6 +1067,13 @@ static void dsi_7nm_phy_disable(struct >>> msm_dsi_phy *phy) >>> pr_warn("Turning OFF PHY while PLL is on\n"); >>> dsi_phy_hw_v4_0_config_lpcdrx(phy, false); >>> + >>> + /* Turn off REFGEN Vote */ >>> + dsi_phy_write(base + >>> REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x0); >>> + wmb(); >>> + /* Delay to ensure HW removes vote before PHY shut down */ >>> + udelay(2); >> >> Either thunderbird is acting up (again) or the code after the first >> comment is >> >> indented with spaces instead of tabs. >> >> >> Other than that, >> >> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> >> >> >> Konrad >> >>> + >>> data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_CTRL_0); >>> /* disable all lanes */ >>> @@ -1040,6 +1097,10 @@ static const struct regulator_bulk_data >>> dsi_phy_7nm_37750uA_regulators[] = { >>> { .supply = "vdds", .init_load_uA = 37550 }, >>> }; >>> +static const struct regulator_bulk_data >>> dsi_phy_7nm_97800uA_regulators[] = { >>> + { .supply = "vdds", .init_load_uA = 97800}, >>> +}; >>> + >>> const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { >>> .has_phy_lane = true, >>> .regulator_data = dsi_phy_7nm_36mA_regulators, >>> @@ -1079,6 +1140,7 @@ const struct msm_dsi_phy_cfg >>> dsi_phy_7nm_8150_cfgs = { >>> .max_pll_rate = 3500000000UL, >>> .io_start = { 0xae94400, 0xae96400 }, >>> .num_dsi_phy = 2, >>> + .quirks = DSI_PHY_7NM_QUIRK_PRE_V4_1, >>> }; >>> const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = { >>> @@ -1102,3 +1164,49 @@ const struct msm_dsi_phy_cfg >>> dsi_phy_7nm_7280_cfgs = { >>> .num_dsi_phy = 1, >>> .quirks = DSI_PHY_7NM_QUIRK_V4_1, >>> }; >>> + >>> +const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs = { >>> + .has_phy_lane = true, >>> + .regulator_data = dsi_phy_7nm_37750uA_regulators, >>> + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_37750uA_regulators), >>> + .ops = { >>> + .enable = dsi_7nm_phy_enable, >>> + .disable = dsi_7nm_phy_disable, >>> + .pll_init = dsi_pll_7nm_init, >>> + .save_pll_state = dsi_7nm_pll_save_state, >>> + .restore_pll_state = dsi_7nm_pll_restore_state, >>> + .set_continuous_clock = dsi_7nm_set_continuous_clock, >>> + }, >>> + .min_pll_rate = 600000000UL, >>> +#ifdef CONFIG_64BIT >>> + .max_pll_rate = 5000000000UL, >>> +#else >>> + .max_pll_rate = ULONG_MAX, >>> +#endif >>> + .io_start = { 0xae94400, 0xae96400 }, >>> + .num_dsi_phy = 2, >>> + .quirks = DSI_PHY_7NM_QUIRK_V4_2, >>> +}; >>> + >>> +const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = { >>> + .has_phy_lane = true, >>> + .regulator_data = dsi_phy_7nm_97800uA_regulators, >>> + .num_regulators = ARRAY_SIZE(dsi_phy_7nm_97800uA_regulators), >>> + .ops = { >>> + .enable = dsi_7nm_phy_enable, >>> + .disable = dsi_7nm_phy_disable, >>> + .pll_init = dsi_pll_7nm_init, >>> + .save_pll_state = dsi_7nm_pll_save_state, >>> + .restore_pll_state = dsi_7nm_pll_restore_state, >>> + .set_continuous_clock = dsi_7nm_set_continuous_clock, >>> + }, >>> + .min_pll_rate = 600000000UL, >>> +#ifdef CONFIG_64BIT >>> + .max_pll_rate = 5000000000UL, >>> +#else >>> + .max_pll_rate = ULONG_MAX, >>> +#endif >>> + .io_start = { 0xae94400, 0xae96400 }, >>> + .num_dsi_phy = 2, >>> + .quirks = DSI_PHY_7NM_QUIRK_V4_3, >>> +}; > ^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v3 5/8] drm/msm/dsi: add support for DSI 2.6.0 2022-11-04 13:03 ` Dmitry Baryshkov @ 2022-11-04 13:03 ` Dmitry Baryshkov -1 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-04 13:03 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul Add support for DSI 2.6.0 (block used on sm8450). Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++ drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c index 7e97c239ed48..59a4cc95a251 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -300,6 +300,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = { &sc7180_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_5_0, &sc7280_dsi_cfg, &msm_dsi_6g_v2_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_6_0, + &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, }; const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h index 8f04e685a74e..95957fab499d 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h @@ -25,6 +25,7 @@ #define MSM_DSI_6G_VER_MINOR_V2_4_0 0x20040000 #define MSM_DSI_6G_VER_MINOR_V2_4_1 0x20040001 #define MSM_DSI_6G_VER_MINOR_V2_5_0 0x20050000 +#define MSM_DSI_6G_VER_MINOR_V2_6_0 0x20060000 #define MSM_DSI_V2_VER_MINOR_8064 0x0 -- 2.35.1 ^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 5/8] drm/msm/dsi: add support for DSI 2.6.0 @ 2022-11-04 13:03 ` Dmitry Baryshkov 0 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-04 13:03 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, freedreno Add support for DSI 2.6.0 (block used on sm8450). Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++ drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c index 7e97c239ed48..59a4cc95a251 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -300,6 +300,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = { &sc7180_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_5_0, &sc7280_dsi_cfg, &msm_dsi_6g_v2_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_6_0, + &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, }; const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h index 8f04e685a74e..95957fab499d 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h @@ -25,6 +25,7 @@ #define MSM_DSI_6G_VER_MINOR_V2_4_0 0x20040000 #define MSM_DSI_6G_VER_MINOR_V2_4_1 0x20040001 #define MSM_DSI_6G_VER_MINOR_V2_5_0 0x20050000 +#define MSM_DSI_6G_VER_MINOR_V2_6_0 0x20060000 #define MSM_DSI_V2_VER_MINOR_8064 0x0 -- 2.35.1 ^ permalink raw reply related [flat|nested] 62+ messages in thread
* Re: [PATCH v3 5/8] drm/msm/dsi: add support for DSI 2.6.0 2022-11-04 13:03 ` Dmitry Baryshkov @ 2022-11-04 13:55 ` Konrad Dybcio -1 siblings, 0 replies; 62+ messages in thread From: Konrad Dybcio @ 2022-11-04 13:55 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul On 04/11/2022 14:03, Dmitry Baryshkov wrote: > Add support for DSI 2.6.0 (block used on sm8450). > > Tested-by: Vinod Koul <vkoul@kernel.org> > Reviewed-by: Vinod Koul <vkoul@kernel.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Konrad > drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++ > drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + > 2 files changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c > index 7e97c239ed48..59a4cc95a251 100644 > --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c > +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c > @@ -300,6 +300,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = { > &sc7180_dsi_cfg, &msm_dsi_6g_v2_host_ops}, > {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_5_0, > &sc7280_dsi_cfg, &msm_dsi_6g_v2_host_ops}, > + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_6_0, > + &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, > }; > > const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor) > diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h > index 8f04e685a74e..95957fab499d 100644 > --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h > +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h > @@ -25,6 +25,7 @@ > #define MSM_DSI_6G_VER_MINOR_V2_4_0 0x20040000 > #define MSM_DSI_6G_VER_MINOR_V2_4_1 0x20040001 > #define MSM_DSI_6G_VER_MINOR_V2_5_0 0x20050000 > +#define MSM_DSI_6G_VER_MINOR_V2_6_0 0x20060000 > > #define MSM_DSI_V2_VER_MINOR_8064 0x0 > ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 5/8] drm/msm/dsi: add support for DSI 2.6.0 @ 2022-11-04 13:55 ` Konrad Dybcio 0 siblings, 0 replies; 62+ messages in thread From: Konrad Dybcio @ 2022-11-04 13:55 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, freedreno On 04/11/2022 14:03, Dmitry Baryshkov wrote: > Add support for DSI 2.6.0 (block used on sm8450). > > Tested-by: Vinod Koul <vkoul@kernel.org> > Reviewed-by: Vinod Koul <vkoul@kernel.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Konrad > drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++ > drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + > 2 files changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c > index 7e97c239ed48..59a4cc95a251 100644 > --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c > +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c > @@ -300,6 +300,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = { > &sc7180_dsi_cfg, &msm_dsi_6g_v2_host_ops}, > {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_5_0, > &sc7280_dsi_cfg, &msm_dsi_6g_v2_host_ops}, > + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_6_0, > + &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, > }; > > const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor) > diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h > index 8f04e685a74e..95957fab499d 100644 > --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h > +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h > @@ -25,6 +25,7 @@ > #define MSM_DSI_6G_VER_MINOR_V2_4_0 0x20040000 > #define MSM_DSI_6G_VER_MINOR_V2_4_1 0x20040001 > #define MSM_DSI_6G_VER_MINOR_V2_5_0 0x20050000 > +#define MSM_DSI_6G_VER_MINOR_V2_6_0 0x20060000 > > #define MSM_DSI_V2_VER_MINOR_8064 0x0 > ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 5/8] drm/msm/dsi: add support for DSI 2.6.0 2022-11-04 13:03 ` Dmitry Baryshkov @ 2022-11-16 7:35 ` Abhinav Kumar -1 siblings, 0 replies; 62+ messages in thread From: Abhinav Kumar @ 2022-11-16 7:35 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, freedreno On 11/4/2022 6:03 AM, Dmitry Baryshkov wrote: > Add support for DSI 2.6.0 (block used on sm8450). > > Tested-by: Vinod Koul <vkoul@kernel.org> > Reviewed-by: Vinod Koul <vkoul@kernel.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > --- > drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++ > drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + > 2 files changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c > index 7e97c239ed48..59a4cc95a251 100644 > --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c > +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c > @@ -300,6 +300,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = { > &sc7180_dsi_cfg, &msm_dsi_6g_v2_host_ops}, > {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_5_0, > &sc7280_dsi_cfg, &msm_dsi_6g_v2_host_ops}, > + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_6_0, > + &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, > }; > > const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor) > diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h > index 8f04e685a74e..95957fab499d 100644 > --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h > +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h > @@ -25,6 +25,7 @@ > #define MSM_DSI_6G_VER_MINOR_V2_4_0 0x20040000 > #define MSM_DSI_6G_VER_MINOR_V2_4_1 0x20040001 > #define MSM_DSI_6G_VER_MINOR_V2_5_0 0x20050000 > +#define MSM_DSI_6G_VER_MINOR_V2_6_0 0x20060000 > > #define MSM_DSI_V2_VER_MINOR_8064 0x0 > ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 5/8] drm/msm/dsi: add support for DSI 2.6.0 @ 2022-11-16 7:35 ` Abhinav Kumar 0 siblings, 0 replies; 62+ messages in thread From: Abhinav Kumar @ 2022-11-16 7:35 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul On 11/4/2022 6:03 AM, Dmitry Baryshkov wrote: > Add support for DSI 2.6.0 (block used on sm8450). > > Tested-by: Vinod Koul <vkoul@kernel.org> > Reviewed-by: Vinod Koul <vkoul@kernel.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > --- > drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++ > drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + > 2 files changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c > index 7e97c239ed48..59a4cc95a251 100644 > --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c > +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c > @@ -300,6 +300,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = { > &sc7180_dsi_cfg, &msm_dsi_6g_v2_host_ops}, > {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_5_0, > &sc7280_dsi_cfg, &msm_dsi_6g_v2_host_ops}, > + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_6_0, > + &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, > }; > > const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor) > diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h > index 8f04e685a74e..95957fab499d 100644 > --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h > +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h > @@ -25,6 +25,7 @@ > #define MSM_DSI_6G_VER_MINOR_V2_4_0 0x20040000 > #define MSM_DSI_6G_VER_MINOR_V2_4_1 0x20040001 > #define MSM_DSI_6G_VER_MINOR_V2_5_0 0x20050000 > +#define MSM_DSI_6G_VER_MINOR_V2_6_0 0x20060000 > > #define MSM_DSI_V2_VER_MINOR_8064 0x0 > ^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v3 6/8] drm/msm/dpu: add support for MDP_TOP blackhole 2022-11-04 13:03 ` Dmitry Baryshkov @ 2022-11-04 13:03 ` Dmitry Baryshkov -1 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-04 13:03 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul On sm8450 a register block was removed from MDP TOP. Accessing it during snapshotting results in NoC errors / immediate reboot. Skip accessing these registers during snapshot. Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 38aa38ab1568..4730f8268f2a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -92,6 +92,7 @@ enum { DPU_MDP_UBWC_1_0, DPU_MDP_UBWC_1_5, DPU_MDP_AUDIO_SELECT, + DPU_MDP_PERIPH_0_REMOVED, DPU_MDP_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index f3660cd14f4f..95d8765c1c53 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, - dpu_kms->mmio + cat->mdp[0].base, "top"); + if (dpu_kms->hw_mdp->caps->features & BIT(DPU_MDP_PERIPH_0_REMOVED)) { + msm_disp_snapshot_add_block(disp_state, 0x380, + dpu_kms->mmio + cat->mdp[0].base, "top"); + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - 0x3a8, + dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2"); + } else { + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, + dpu_kms->mmio + cat->mdp[0].base, "top"); + } pm_runtime_put_sync(&dpu_kms->pdev->dev); } -- 2.35.1 ^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 6/8] drm/msm/dpu: add support for MDP_TOP blackhole @ 2022-11-04 13:03 ` Dmitry Baryshkov 0 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-04 13:03 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, freedreno On sm8450 a register block was removed from MDP TOP. Accessing it during snapshotting results in NoC errors / immediate reboot. Skip accessing these registers during snapshot. Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 38aa38ab1568..4730f8268f2a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -92,6 +92,7 @@ enum { DPU_MDP_UBWC_1_0, DPU_MDP_UBWC_1_5, DPU_MDP_AUDIO_SELECT, + DPU_MDP_PERIPH_0_REMOVED, DPU_MDP_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index f3660cd14f4f..95d8765c1c53 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, - dpu_kms->mmio + cat->mdp[0].base, "top"); + if (dpu_kms->hw_mdp->caps->features & BIT(DPU_MDP_PERIPH_0_REMOVED)) { + msm_disp_snapshot_add_block(disp_state, 0x380, + dpu_kms->mmio + cat->mdp[0].base, "top"); + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - 0x3a8, + dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2"); + } else { + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, + dpu_kms->mmio + cat->mdp[0].base, "top"); + } pm_runtime_put_sync(&dpu_kms->pdev->dev); } -- 2.35.1 ^ permalink raw reply related [flat|nested] 62+ messages in thread
* Re: [PATCH v3 6/8] drm/msm/dpu: add support for MDP_TOP blackhole 2022-11-04 13:03 ` Dmitry Baryshkov @ 2022-11-04 13:58 ` Konrad Dybcio -1 siblings, 0 replies; 62+ messages in thread From: Konrad Dybcio @ 2022-11-04 13:58 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul On 04/11/2022 14:03, Dmitry Baryshkov wrote: > On sm8450 a register block was removed from MDP TOP. Accessing it during > snapshotting results in NoC errors / immediate reboot. Skip accessing > these registers during snapshot. Must have been fun to debug.. > > Tested-by: Vinod Koul <vkoul@kernel.org> > Reviewed-by: Vinod Koul <vkoul@kernel.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++-- > 2 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 38aa38ab1568..4730f8268f2a 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -92,6 +92,7 @@ enum { > DPU_MDP_UBWC_1_0, > DPU_MDP_UBWC_1_5, > DPU_MDP_AUDIO_SELECT, > + DPU_MDP_PERIPH_0_REMOVED, > DPU_MDP_MAX > }; > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > index f3660cd14f4f..95d8765c1c53 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > @@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k > msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, > dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); > > - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, > - dpu_kms->mmio + cat->mdp[0].base, "top"); > + if (dpu_kms->hw_mdp->caps->features & BIT(DPU_MDP_PERIPH_0_REMOVED)) { > + msm_disp_snapshot_add_block(disp_state, 0x380, > + dpu_kms->mmio + cat->mdp[0].base, "top"); > + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - 0x3a8, > + dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2"); Are these values expected to stay the same on different new-gen SoCs? Maybe it would be worth making it dynamic. Konrad > + } else { > + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, > + dpu_kms->mmio + cat->mdp[0].base, "top"); > + } > > pm_runtime_put_sync(&dpu_kms->pdev->dev); > } ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 6/8] drm/msm/dpu: add support for MDP_TOP blackhole @ 2022-11-04 13:58 ` Konrad Dybcio 0 siblings, 0 replies; 62+ messages in thread From: Konrad Dybcio @ 2022-11-04 13:58 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, freedreno On 04/11/2022 14:03, Dmitry Baryshkov wrote: > On sm8450 a register block was removed from MDP TOP. Accessing it during > snapshotting results in NoC errors / immediate reboot. Skip accessing > these registers during snapshot. Must have been fun to debug.. > > Tested-by: Vinod Koul <vkoul@kernel.org> > Reviewed-by: Vinod Koul <vkoul@kernel.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++-- > 2 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 38aa38ab1568..4730f8268f2a 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -92,6 +92,7 @@ enum { > DPU_MDP_UBWC_1_0, > DPU_MDP_UBWC_1_5, > DPU_MDP_AUDIO_SELECT, > + DPU_MDP_PERIPH_0_REMOVED, > DPU_MDP_MAX > }; > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > index f3660cd14f4f..95d8765c1c53 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > @@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k > msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, > dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); > > - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, > - dpu_kms->mmio + cat->mdp[0].base, "top"); > + if (dpu_kms->hw_mdp->caps->features & BIT(DPU_MDP_PERIPH_0_REMOVED)) { > + msm_disp_snapshot_add_block(disp_state, 0x380, > + dpu_kms->mmio + cat->mdp[0].base, "top"); > + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - 0x3a8, > + dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2"); Are these values expected to stay the same on different new-gen SoCs? Maybe it would be worth making it dynamic. Konrad > + } else { > + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, > + dpu_kms->mmio + cat->mdp[0].base, "top"); > + } > > pm_runtime_put_sync(&dpu_kms->pdev->dev); > } ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 6/8] drm/msm/dpu: add support for MDP_TOP blackhole 2022-11-04 13:58 ` Konrad Dybcio @ 2022-11-10 20:19 ` Dmitry Baryshkov -1 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-10 20:19 UTC (permalink / raw) To: Konrad Dybcio, Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, freedreno On 04/11/2022 16:58, Konrad Dybcio wrote: > > On 04/11/2022 14:03, Dmitry Baryshkov wrote: >> On sm8450 a register block was removed from MDP TOP. Accessing it during >> snapshotting results in NoC errors / immediate reboot. Skip accessing >> these registers during snapshot. > > Must have been fun to debug.. > > >> >> Tested-by: Vinod Koul <vkoul@kernel.org> >> Reviewed-by: Vinod Koul <vkoul@kernel.org> >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> --- >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + >> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++-- >> 2 files changed, 10 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> index 38aa38ab1568..4730f8268f2a 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> @@ -92,6 +92,7 @@ enum { >> DPU_MDP_UBWC_1_0, >> DPU_MDP_UBWC_1_5, >> DPU_MDP_AUDIO_SELECT, >> + DPU_MDP_PERIPH_0_REMOVED, >> DPU_MDP_MAX >> }; >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> index f3660cd14f4f..95d8765c1c53 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> @@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct >> msm_disp_state *disp_state, struct msm_k >> msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, >> dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); >> - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >> - dpu_kms->mmio + cat->mdp[0].base, "top"); >> + if (dpu_kms->hw_mdp->caps->features & >> BIT(DPU_MDP_PERIPH_0_REMOVED)) { >> + msm_disp_snapshot_add_block(disp_state, 0x380, >> + dpu_kms->mmio + cat->mdp[0].base, "top"); >> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - 0x3a8, >> + dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2"); > > Are these values expected to stay the same on different new-gen SoCs? > Maybe it would > > be worth making it dynamic. I do not want to overcomplicate this. Let's make it dynamic once there is need for that. For now I expect this will be static. > > > Konrad > >> + } else { >> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >> + dpu_kms->mmio + cat->mdp[0].base, "top"); >> + } >> pm_runtime_put_sync(&dpu_kms->pdev->dev); >> } -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 6/8] drm/msm/dpu: add support for MDP_TOP blackhole @ 2022-11-10 20:19 ` Dmitry Baryshkov 0 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-10 20:19 UTC (permalink / raw) To: Konrad Dybcio, Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul On 04/11/2022 16:58, Konrad Dybcio wrote: > > On 04/11/2022 14:03, Dmitry Baryshkov wrote: >> On sm8450 a register block was removed from MDP TOP. Accessing it during >> snapshotting results in NoC errors / immediate reboot. Skip accessing >> these registers during snapshot. > > Must have been fun to debug.. > > >> >> Tested-by: Vinod Koul <vkoul@kernel.org> >> Reviewed-by: Vinod Koul <vkoul@kernel.org> >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> --- >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + >> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++-- >> 2 files changed, 10 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> index 38aa38ab1568..4730f8268f2a 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> @@ -92,6 +92,7 @@ enum { >> DPU_MDP_UBWC_1_0, >> DPU_MDP_UBWC_1_5, >> DPU_MDP_AUDIO_SELECT, >> + DPU_MDP_PERIPH_0_REMOVED, >> DPU_MDP_MAX >> }; >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> index f3660cd14f4f..95d8765c1c53 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> @@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct >> msm_disp_state *disp_state, struct msm_k >> msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, >> dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); >> - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >> - dpu_kms->mmio + cat->mdp[0].base, "top"); >> + if (dpu_kms->hw_mdp->caps->features & >> BIT(DPU_MDP_PERIPH_0_REMOVED)) { >> + msm_disp_snapshot_add_block(disp_state, 0x380, >> + dpu_kms->mmio + cat->mdp[0].base, "top"); >> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - 0x3a8, >> + dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2"); > > Are these values expected to stay the same on different new-gen SoCs? > Maybe it would > > be worth making it dynamic. I do not want to overcomplicate this. Let's make it dynamic once there is need for that. For now I expect this will be static. > > > Konrad > >> + } else { >> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >> + dpu_kms->mmio + cat->mdp[0].base, "top"); >> + } >> pm_runtime_put_sync(&dpu_kms->pdev->dev); >> } -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 6/8] drm/msm/dpu: add support for MDP_TOP blackhole 2022-11-10 20:19 ` Dmitry Baryshkov @ 2022-11-10 20:21 ` Konrad Dybcio -1 siblings, 0 replies; 62+ messages in thread From: Konrad Dybcio @ 2022-11-10 20:21 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul On 10/11/2022 21:19, Dmitry Baryshkov wrote: > On 04/11/2022 16:58, Konrad Dybcio wrote: >> >> On 04/11/2022 14:03, Dmitry Baryshkov wrote: >>> On sm8450 a register block was removed from MDP TOP. Accessing it during >>> snapshotting results in NoC errors / immediate reboot. Skip accessing >>> these registers during snapshot. >> >> Must have been fun to debug.. >> >> >>> >>> Tested-by: Vinod Koul <vkoul@kernel.org> >>> Reviewed-by: Vinod Koul <vkoul@kernel.org> >>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>> --- >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + >>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++-- >>> 2 files changed, 10 insertions(+), 2 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>> index 38aa38ab1568..4730f8268f2a 100644 >>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>> @@ -92,6 +92,7 @@ enum { >>> DPU_MDP_UBWC_1_0, >>> DPU_MDP_UBWC_1_5, >>> DPU_MDP_AUDIO_SELECT, >>> + DPU_MDP_PERIPH_0_REMOVED, >>> DPU_MDP_MAX >>> }; >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>> index f3660cd14f4f..95d8765c1c53 100644 >>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>> @@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct >>> msm_disp_state *disp_state, struct msm_k >>> msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, >>> dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); >>> - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >>> - dpu_kms->mmio + cat->mdp[0].base, "top"); >>> + if (dpu_kms->hw_mdp->caps->features & >>> BIT(DPU_MDP_PERIPH_0_REMOVED)) { >>> + msm_disp_snapshot_add_block(disp_state, 0x380, >>> + dpu_kms->mmio + cat->mdp[0].base, "top"); >>> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - >>> 0x3a8, >>> + dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2"); >> >> Are these values expected to stay the same on different new-gen SoCs? >> Maybe it would >> >> be worth making it dynamic. > > I do not want to overcomplicate this. Let's make it dynamic once there > is need for that. For now I expect this will be static. Let's roll with that. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > >> >> >> Konrad >> >>> + } else { >>> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >>> + dpu_kms->mmio + cat->mdp[0].base, "top"); >>> + } >>> pm_runtime_put_sync(&dpu_kms->pdev->dev); >>> } > ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 6/8] drm/msm/dpu: add support for MDP_TOP blackhole @ 2022-11-10 20:21 ` Konrad Dybcio 0 siblings, 0 replies; 62+ messages in thread From: Konrad Dybcio @ 2022-11-10 20:21 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, freedreno On 10/11/2022 21:19, Dmitry Baryshkov wrote: > On 04/11/2022 16:58, Konrad Dybcio wrote: >> >> On 04/11/2022 14:03, Dmitry Baryshkov wrote: >>> On sm8450 a register block was removed from MDP TOP. Accessing it during >>> snapshotting results in NoC errors / immediate reboot. Skip accessing >>> these registers during snapshot. >> >> Must have been fun to debug.. >> >> >>> >>> Tested-by: Vinod Koul <vkoul@kernel.org> >>> Reviewed-by: Vinod Koul <vkoul@kernel.org> >>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>> --- >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + >>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++-- >>> 2 files changed, 10 insertions(+), 2 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>> index 38aa38ab1568..4730f8268f2a 100644 >>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>> @@ -92,6 +92,7 @@ enum { >>> DPU_MDP_UBWC_1_0, >>> DPU_MDP_UBWC_1_5, >>> DPU_MDP_AUDIO_SELECT, >>> + DPU_MDP_PERIPH_0_REMOVED, >>> DPU_MDP_MAX >>> }; >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>> index f3660cd14f4f..95d8765c1c53 100644 >>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>> @@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct >>> msm_disp_state *disp_state, struct msm_k >>> msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, >>> dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); >>> - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >>> - dpu_kms->mmio + cat->mdp[0].base, "top"); >>> + if (dpu_kms->hw_mdp->caps->features & >>> BIT(DPU_MDP_PERIPH_0_REMOVED)) { >>> + msm_disp_snapshot_add_block(disp_state, 0x380, >>> + dpu_kms->mmio + cat->mdp[0].base, "top"); >>> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - >>> 0x3a8, >>> + dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2"); >> >> Are these values expected to stay the same on different new-gen SoCs? >> Maybe it would >> >> be worth making it dynamic. > > I do not want to overcomplicate this. Let's make it dynamic once there > is need for that. For now I expect this will be static. Let's roll with that. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > >> >> >> Konrad >> >>> + } else { >>> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >>> + dpu_kms->mmio + cat->mdp[0].base, "top"); >>> + } >>> pm_runtime_put_sync(&dpu_kms->pdev->dev); >>> } > ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 6/8] drm/msm/dpu: add support for MDP_TOP blackhole 2022-11-04 13:03 ` Dmitry Baryshkov @ 2022-11-16 7:50 ` Abhinav Kumar -1 siblings, 0 replies; 62+ messages in thread From: Abhinav Kumar @ 2022-11-16 7:50 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul On 11/4/2022 6:03 AM, Dmitry Baryshkov wrote: > On sm8450 a register block was removed from MDP TOP. Accessing it during > snapshotting results in NoC errors / immediate reboot. Skip accessing > these registers during snapshot. > > Tested-by: Vinod Koul <vkoul@kernel.org> > Reviewed-by: Vinod Koul <vkoul@kernel.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> I am confused with both the ordering and the split of this patch. You have defined DPU_MDP_PERIPH_0_REMOVED in the catalog header file in this patch but used it in the next. But you also have code in this patch which relies on setting of this bit. So if this patch is taken without the next, it will still crash. Rather, you should combine the define part of this patch to the next patch in the series https://patchwork.freedesktop.org/patch/510114/?series=108883&rev=3 , then move that one in front of this patch. So that its much more coherent that you defined DPU_MDP_PERIPH_0_REMOVED both in the catalog header and used it in the catalog.c file and the in the next change you used the caps to avoid touching that register. Regarding the TOP hole itself, I need one day to investigate this. I am waiting for permissions to the documentation. If i cannot get access by the time you have re-ordered this, I will ack this once the reorder is done within a day. > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++-- > 2 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 38aa38ab1568..4730f8268f2a 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -92,6 +92,7 @@ enum { > DPU_MDP_UBWC_1_0, > DPU_MDP_UBWC_1_5, > DPU_MDP_AUDIO_SELECT, > + DPU_MDP_PERIPH_0_REMOVED, > DPU_MDP_MAX > }; > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > index f3660cd14f4f..95d8765c1c53 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > @@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k > msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, > dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); > > - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, > - dpu_kms->mmio + cat->mdp[0].base, "top"); > + if (dpu_kms->hw_mdp->caps->features & BIT(DPU_MDP_PERIPH_0_REMOVED)) { > + msm_disp_snapshot_add_block(disp_state, 0x380, > + dpu_kms->mmio + cat->mdp[0].base, "top"); > + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - 0x3a8, > + dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2"); > + } else { > + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, > + dpu_kms->mmio + cat->mdp[0].base, "top"); > + } > > pm_runtime_put_sync(&dpu_kms->pdev->dev); > } ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 6/8] drm/msm/dpu: add support for MDP_TOP blackhole @ 2022-11-16 7:50 ` Abhinav Kumar 0 siblings, 0 replies; 62+ messages in thread From: Abhinav Kumar @ 2022-11-16 7:50 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, freedreno On 11/4/2022 6:03 AM, Dmitry Baryshkov wrote: > On sm8450 a register block was removed from MDP TOP. Accessing it during > snapshotting results in NoC errors / immediate reboot. Skip accessing > these registers during snapshot. > > Tested-by: Vinod Koul <vkoul@kernel.org> > Reviewed-by: Vinod Koul <vkoul@kernel.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> I am confused with both the ordering and the split of this patch. You have defined DPU_MDP_PERIPH_0_REMOVED in the catalog header file in this patch but used it in the next. But you also have code in this patch which relies on setting of this bit. So if this patch is taken without the next, it will still crash. Rather, you should combine the define part of this patch to the next patch in the series https://patchwork.freedesktop.org/patch/510114/?series=108883&rev=3 , then move that one in front of this patch. So that its much more coherent that you defined DPU_MDP_PERIPH_0_REMOVED both in the catalog header and used it in the catalog.c file and the in the next change you used the caps to avoid touching that register. Regarding the TOP hole itself, I need one day to investigate this. I am waiting for permissions to the documentation. If i cannot get access by the time you have re-ordered this, I will ack this once the reorder is done within a day. > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++-- > 2 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 38aa38ab1568..4730f8268f2a 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -92,6 +92,7 @@ enum { > DPU_MDP_UBWC_1_0, > DPU_MDP_UBWC_1_5, > DPU_MDP_AUDIO_SELECT, > + DPU_MDP_PERIPH_0_REMOVED, > DPU_MDP_MAX > }; > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > index f3660cd14f4f..95d8765c1c53 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > @@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k > msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, > dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); > > - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, > - dpu_kms->mmio + cat->mdp[0].base, "top"); > + if (dpu_kms->hw_mdp->caps->features & BIT(DPU_MDP_PERIPH_0_REMOVED)) { > + msm_disp_snapshot_add_block(disp_state, 0x380, > + dpu_kms->mmio + cat->mdp[0].base, "top"); > + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - 0x3a8, > + dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2"); > + } else { > + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, > + dpu_kms->mmio + cat->mdp[0].base, "top"); > + } > > pm_runtime_put_sync(&dpu_kms->pdev->dev); > } ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 6/8] drm/msm/dpu: add support for MDP_TOP blackhole 2022-11-16 7:50 ` Abhinav Kumar @ 2022-11-16 8:19 ` Dmitry Baryshkov -1 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-16 8:19 UTC (permalink / raw) To: Abhinav Kumar, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, freedreno On 16/11/2022 10:50, Abhinav Kumar wrote: > > > On 11/4/2022 6:03 AM, Dmitry Baryshkov wrote: >> On sm8450 a register block was removed from MDP TOP. Accessing it during >> snapshotting results in NoC errors / immediate reboot. Skip accessing >> these registers during snapshot. >> >> Tested-by: Vinod Koul <vkoul@kernel.org> >> Reviewed-by: Vinod Koul <vkoul@kernel.org> >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > I am confused with both the ordering and the split of this patch. > > You have defined DPU_MDP_PERIPH_0_REMOVED in the catalog header file in > this patch but used it in the next. > > But you also have code in this patch which relies on setting of this bit. > > So if this patch is taken without the next, it will still crash. It will not crash if this patch is taken without the next one. Without the next patch the DPU driver will not match and bind against the qcom,sm8450-dpu device. So, the ordering is quite logical from my point of view: - add support for all the features required for the device - add the device compat string & catalog entry > > Rather, you should combine the define part of this patch to the next > patch in the series > https://patchwork.freedesktop.org/patch/510114/?series=108883&rev=3 , > then move that one in front of this patch. No. This way we'll have a state (after adding the next patch) when the sm8450 support is enabled, but the top-hole is not handled, leading to a crash. > > So that its much more coherent that you defined DPU_MDP_PERIPH_0_REMOVED > both in the catalog header and used it in the catalog.c file and the in > the next change you used the caps to avoid touching that register. I'd say it's rather strange way. When I see a define/feature addition, I'd prefer to seethe implementation too. > Regarding the TOP hole itself, I need one day to investigate this. I am > waiting for permissions to the documentation. > > If i cannot get access by the time you have re-ordered this, I will ack > this once the reorder is done within a day. For the reference: [1] [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers/-/commit/f9ff8af5b640147f3651c23551c60f81f62874b1 > >> --- >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + >> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++-- >> 2 files changed, 10 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> index 38aa38ab1568..4730f8268f2a 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> @@ -92,6 +92,7 @@ enum { >> DPU_MDP_UBWC_1_0, >> DPU_MDP_UBWC_1_5, >> DPU_MDP_AUDIO_SELECT, >> + DPU_MDP_PERIPH_0_REMOVED, >> DPU_MDP_MAX >> }; >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> index f3660cd14f4f..95d8765c1c53 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> @@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct >> msm_disp_state *disp_state, struct msm_k >> msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, >> dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); >> - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >> - dpu_kms->mmio + cat->mdp[0].base, "top"); >> + if (dpu_kms->hw_mdp->caps->features & >> BIT(DPU_MDP_PERIPH_0_REMOVED)) { >> + msm_disp_snapshot_add_block(disp_state, 0x380, >> + dpu_kms->mmio + cat->mdp[0].base, "top"); >> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - 0x3a8, >> + dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2"); >> + } else { >> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >> + dpu_kms->mmio + cat->mdp[0].base, "top"); >> + } >> pm_runtime_put_sync(&dpu_kms->pdev->dev); >> } -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 6/8] drm/msm/dpu: add support for MDP_TOP blackhole @ 2022-11-16 8:19 ` Dmitry Baryshkov 0 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-16 8:19 UTC (permalink / raw) To: Abhinav Kumar, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul On 16/11/2022 10:50, Abhinav Kumar wrote: > > > On 11/4/2022 6:03 AM, Dmitry Baryshkov wrote: >> On sm8450 a register block was removed from MDP TOP. Accessing it during >> snapshotting results in NoC errors / immediate reboot. Skip accessing >> these registers during snapshot. >> >> Tested-by: Vinod Koul <vkoul@kernel.org> >> Reviewed-by: Vinod Koul <vkoul@kernel.org> >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > I am confused with both the ordering and the split of this patch. > > You have defined DPU_MDP_PERIPH_0_REMOVED in the catalog header file in > this patch but used it in the next. > > But you also have code in this patch which relies on setting of this bit. > > So if this patch is taken without the next, it will still crash. It will not crash if this patch is taken without the next one. Without the next patch the DPU driver will not match and bind against the qcom,sm8450-dpu device. So, the ordering is quite logical from my point of view: - add support for all the features required for the device - add the device compat string & catalog entry > > Rather, you should combine the define part of this patch to the next > patch in the series > https://patchwork.freedesktop.org/patch/510114/?series=108883&rev=3 , > then move that one in front of this patch. No. This way we'll have a state (after adding the next patch) when the sm8450 support is enabled, but the top-hole is not handled, leading to a crash. > > So that its much more coherent that you defined DPU_MDP_PERIPH_0_REMOVED > both in the catalog header and used it in the catalog.c file and the in > the next change you used the caps to avoid touching that register. I'd say it's rather strange way. When I see a define/feature addition, I'd prefer to seethe implementation too. > Regarding the TOP hole itself, I need one day to investigate this. I am > waiting for permissions to the documentation. > > If i cannot get access by the time you have re-ordered this, I will ack > this once the reorder is done within a day. For the reference: [1] [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers/-/commit/f9ff8af5b640147f3651c23551c60f81f62874b1 > >> --- >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + >> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++-- >> 2 files changed, 10 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> index 38aa38ab1568..4730f8268f2a 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> @@ -92,6 +92,7 @@ enum { >> DPU_MDP_UBWC_1_0, >> DPU_MDP_UBWC_1_5, >> DPU_MDP_AUDIO_SELECT, >> + DPU_MDP_PERIPH_0_REMOVED, >> DPU_MDP_MAX >> }; >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> index f3660cd14f4f..95d8765c1c53 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >> @@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct >> msm_disp_state *disp_state, struct msm_k >> msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, >> dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); >> - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >> - dpu_kms->mmio + cat->mdp[0].base, "top"); >> + if (dpu_kms->hw_mdp->caps->features & >> BIT(DPU_MDP_PERIPH_0_REMOVED)) { >> + msm_disp_snapshot_add_block(disp_state, 0x380, >> + dpu_kms->mmio + cat->mdp[0].base, "top"); >> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - 0x3a8, >> + dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2"); >> + } else { >> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >> + dpu_kms->mmio + cat->mdp[0].base, "top"); >> + } >> pm_runtime_put_sync(&dpu_kms->pdev->dev); >> } -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 6/8] drm/msm/dpu: add support for MDP_TOP blackhole 2022-11-16 8:19 ` Dmitry Baryshkov @ 2022-11-16 8:30 ` Abhinav Kumar -1 siblings, 0 replies; 62+ messages in thread From: Abhinav Kumar @ 2022-11-16 8:30 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, freedreno On 11/16/2022 12:19 AM, Dmitry Baryshkov wrote: > On 16/11/2022 10:50, Abhinav Kumar wrote: >> >> >> On 11/4/2022 6:03 AM, Dmitry Baryshkov wrote: >>> On sm8450 a register block was removed from MDP TOP. Accessing it during >>> snapshotting results in NoC errors / immediate reboot. Skip accessing >>> these registers during snapshot. >>> >>> Tested-by: Vinod Koul <vkoul@kernel.org> >>> Reviewed-by: Vinod Koul <vkoul@kernel.org> >>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> >> I am confused with both the ordering and the split of this patch. >> >> You have defined DPU_MDP_PERIPH_0_REMOVED in the catalog header file >> in this patch but used it in the next. >> >> But you also have code in this patch which relies on setting of this bit. >> >> So if this patch is taken without the next, it will still crash. > > It will not crash if this patch is taken without the next one. Without > the next patch the DPU driver will not match and bind against the > qcom,sm8450-dpu device. Ah okay, I just now saw that you have the compatible change also in the next patch. > > So, the ordering is quite logical from my point of view: > - add support for all the features required for the device > - add the device compat string & catalog entry > >> >> Rather, you should combine the define part of this patch to the next >> patch in the series >> https://patchwork.freedesktop.org/patch/510114/?series=108883&rev=3 , >> then move that one in front of this patch. > > No. This way we'll have a state (after adding the next patch) when the > sm8450 support is enabled, but the top-hole is not handled, leading to a > crash. > What if you split the compatible to a separate patch like what SM8350 did. https://patchwork.freedesktop.org/patch/511659/?series=110924&rev=1 So, we have hw catalog changes ---> snapshot fix ---> add the compatible. That will make both of us happy? >> >> So that its much more coherent that you defined >> DPU_MDP_PERIPH_0_REMOVED both in the catalog header and used it in the >> catalog.c file and the in the next change you used the caps to avoid >> touching that register. > > I'd say it's rather strange way. When I see a define/feature addition, > I'd prefer to seethe implementation too. > >> Regarding the TOP hole itself, I need one day to investigate this. I >> am waiting for permissions to the documentation. >> >> If i cannot get access by the time you have re-ordered this, I will >> ack this once the reorder is done within a day. > > > For the reference: [1] > > [1] > https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers/-/commit/f9ff8af5b640147f3651c23551c60f81f62874b1 > > >> >>> --- >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + >>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++-- >>> 2 files changed, 10 insertions(+), 2 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>> index 38aa38ab1568..4730f8268f2a 100644 >>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>> @@ -92,6 +92,7 @@ enum { >>> DPU_MDP_UBWC_1_0, >>> DPU_MDP_UBWC_1_5, >>> DPU_MDP_AUDIO_SELECT, >>> + DPU_MDP_PERIPH_0_REMOVED, >>> DPU_MDP_MAX >>> }; >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>> index f3660cd14f4f..95d8765c1c53 100644 >>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>> @@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct >>> msm_disp_state *disp_state, struct msm_k >>> msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, >>> dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); >>> - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >>> - dpu_kms->mmio + cat->mdp[0].base, "top"); >>> + if (dpu_kms->hw_mdp->caps->features & >>> BIT(DPU_MDP_PERIPH_0_REMOVED)) { >>> + msm_disp_snapshot_add_block(disp_state, 0x380, >>> + dpu_kms->mmio + cat->mdp[0].base, "top"); >>> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - >>> 0x3a8, >>> + dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2"); >>> + } else { >>> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >>> + dpu_kms->mmio + cat->mdp[0].base, "top"); >>> + } >>> pm_runtime_put_sync(&dpu_kms->pdev->dev); >>> } > ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 6/8] drm/msm/dpu: add support for MDP_TOP blackhole @ 2022-11-16 8:30 ` Abhinav Kumar 0 siblings, 0 replies; 62+ messages in thread From: Abhinav Kumar @ 2022-11-16 8:30 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul On 11/16/2022 12:19 AM, Dmitry Baryshkov wrote: > On 16/11/2022 10:50, Abhinav Kumar wrote: >> >> >> On 11/4/2022 6:03 AM, Dmitry Baryshkov wrote: >>> On sm8450 a register block was removed from MDP TOP. Accessing it during >>> snapshotting results in NoC errors / immediate reboot. Skip accessing >>> these registers during snapshot. >>> >>> Tested-by: Vinod Koul <vkoul@kernel.org> >>> Reviewed-by: Vinod Koul <vkoul@kernel.org> >>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> >> I am confused with both the ordering and the split of this patch. >> >> You have defined DPU_MDP_PERIPH_0_REMOVED in the catalog header file >> in this patch but used it in the next. >> >> But you also have code in this patch which relies on setting of this bit. >> >> So if this patch is taken without the next, it will still crash. > > It will not crash if this patch is taken without the next one. Without > the next patch the DPU driver will not match and bind against the > qcom,sm8450-dpu device. Ah okay, I just now saw that you have the compatible change also in the next patch. > > So, the ordering is quite logical from my point of view: > - add support for all the features required for the device > - add the device compat string & catalog entry > >> >> Rather, you should combine the define part of this patch to the next >> patch in the series >> https://patchwork.freedesktop.org/patch/510114/?series=108883&rev=3 , >> then move that one in front of this patch. > > No. This way we'll have a state (after adding the next patch) when the > sm8450 support is enabled, but the top-hole is not handled, leading to a > crash. > What if you split the compatible to a separate patch like what SM8350 did. https://patchwork.freedesktop.org/patch/511659/?series=110924&rev=1 So, we have hw catalog changes ---> snapshot fix ---> add the compatible. That will make both of us happy? >> >> So that its much more coherent that you defined >> DPU_MDP_PERIPH_0_REMOVED both in the catalog header and used it in the >> catalog.c file and the in the next change you used the caps to avoid >> touching that register. > > I'd say it's rather strange way. When I see a define/feature addition, > I'd prefer to seethe implementation too. > >> Regarding the TOP hole itself, I need one day to investigate this. I >> am waiting for permissions to the documentation. >> >> If i cannot get access by the time you have re-ordered this, I will >> ack this once the reorder is done within a day. > > > For the reference: [1] > > [1] > https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers/-/commit/f9ff8af5b640147f3651c23551c60f81f62874b1 > > >> >>> --- >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + >>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++-- >>> 2 files changed, 10 insertions(+), 2 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>> index 38aa38ab1568..4730f8268f2a 100644 >>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>> @@ -92,6 +92,7 @@ enum { >>> DPU_MDP_UBWC_1_0, >>> DPU_MDP_UBWC_1_5, >>> DPU_MDP_AUDIO_SELECT, >>> + DPU_MDP_PERIPH_0_REMOVED, >>> DPU_MDP_MAX >>> }; >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>> index f3660cd14f4f..95d8765c1c53 100644 >>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>> @@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct >>> msm_disp_state *disp_state, struct msm_k >>> msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, >>> dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); >>> - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >>> - dpu_kms->mmio + cat->mdp[0].base, "top"); >>> + if (dpu_kms->hw_mdp->caps->features & >>> BIT(DPU_MDP_PERIPH_0_REMOVED)) { >>> + msm_disp_snapshot_add_block(disp_state, 0x380, >>> + dpu_kms->mmio + cat->mdp[0].base, "top"); >>> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - >>> 0x3a8, >>> + dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2"); >>> + } else { >>> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >>> + dpu_kms->mmio + cat->mdp[0].base, "top"); >>> + } >>> pm_runtime_put_sync(&dpu_kms->pdev->dev); >>> } > ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 6/8] drm/msm/dpu: add support for MDP_TOP blackhole 2022-11-16 8:30 ` Abhinav Kumar @ 2022-11-16 9:18 ` Dmitry Baryshkov -1 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-16 9:18 UTC (permalink / raw) To: Abhinav Kumar, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, freedreno On 16/11/2022 11:30, Abhinav Kumar wrote: > > > On 11/16/2022 12:19 AM, Dmitry Baryshkov wrote: >> On 16/11/2022 10:50, Abhinav Kumar wrote: >>> >>> >>> On 11/4/2022 6:03 AM, Dmitry Baryshkov wrote: >>>> On sm8450 a register block was removed from MDP TOP. Accessing it >>>> during >>>> snapshotting results in NoC errors / immediate reboot. Skip accessing >>>> these registers during snapshot. >>>> >>>> Tested-by: Vinod Koul <vkoul@kernel.org> >>>> Reviewed-by: Vinod Koul <vkoul@kernel.org> >>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>> >>> I am confused with both the ordering and the split of this patch. >>> >>> You have defined DPU_MDP_PERIPH_0_REMOVED in the catalog header file >>> in this patch but used it in the next. >>> >>> But you also have code in this patch which relies on setting of this >>> bit. >>> >>> So if this patch is taken without the next, it will still crash. >> >> It will not crash if this patch is taken without the next one. Without >> the next patch the DPU driver will not match and bind against the >> qcom,sm8450-dpu device. > > Ah okay, I just now saw that you have the compatible change also in the > next patch. > >> >> So, the ordering is quite logical from my point of view: >> - add support for all the features required for the device >> - add the device compat string & catalog entry >> >>> >>> Rather, you should combine the define part of this patch to the next >>> patch in the series >>> https://patchwork.freedesktop.org/patch/510114/?series=108883&rev=3 , >>> then move that one in front of this patch. >> >> No. This way we'll have a state (after adding the next patch) when the >> sm8450 support is enabled, but the top-hole is not handled, leading to >> a crash. >> > > What if you split the compatible to a separate patch like what SM8350 did. > > https://patchwork.freedesktop.org/patch/511659/?series=110924&rev=1 > > So, we have hw catalog changes ---> snapshot fix ---> add the compatible. I don't see any good reason to do this. Adding a define without backing implementation is a bad idea in my opinion. Regarding splitting the hw_catalog and compat. I have always considered the hw catalog entry as of_device_id.data. In other words, a devices' match data, which makes a little sense without compat entry. With the current approach each patch is atomic, it changes single point or adds a single feature, etc. > > That will make both of us happy? > >>> >>> So that its much more coherent that you defined >>> DPU_MDP_PERIPH_0_REMOVED both in the catalog header and used it in >>> the catalog.c file and the in the next change you used the caps to >>> avoid touching that register. >> >> I'd say it's rather strange way. When I see a define/feature addition, >> I'd prefer to seethe implementation too. >> >>> Regarding the TOP hole itself, I need one day to investigate this. I >>> am waiting for permissions to the documentation. >>> >>> If i cannot get access by the time you have re-ordered this, I will >>> ack this once the reorder is done within a day. >> >> >> For the reference: [1] >> >> [1] >> https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers/-/commit/f9ff8af5b640147f3651c23551c60f81f62874b1 >> >>> >>>> --- >>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + >>>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++-- >>>> 2 files changed, 10 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>> index 38aa38ab1568..4730f8268f2a 100644 >>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>> @@ -92,6 +92,7 @@ enum { >>>> DPU_MDP_UBWC_1_0, >>>> DPU_MDP_UBWC_1_5, >>>> DPU_MDP_AUDIO_SELECT, >>>> + DPU_MDP_PERIPH_0_REMOVED, >>>> DPU_MDP_MAX >>>> }; >>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>> index f3660cd14f4f..95d8765c1c53 100644 >>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>> @@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct >>>> msm_disp_state *disp_state, struct msm_k >>>> msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, >>>> dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); >>>> - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >>>> - dpu_kms->mmio + cat->mdp[0].base, "top"); >>>> + if (dpu_kms->hw_mdp->caps->features & >>>> BIT(DPU_MDP_PERIPH_0_REMOVED)) { >>>> + msm_disp_snapshot_add_block(disp_state, 0x380, >>>> + dpu_kms->mmio + cat->mdp[0].base, "top"); >>>> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - >>>> 0x3a8, >>>> + dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2"); >>>> + } else { >>>> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >>>> + dpu_kms->mmio + cat->mdp[0].base, "top"); >>>> + } >>>> pm_runtime_put_sync(&dpu_kms->pdev->dev); >>>> } >> -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 6/8] drm/msm/dpu: add support for MDP_TOP blackhole @ 2022-11-16 9:18 ` Dmitry Baryshkov 0 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-16 9:18 UTC (permalink / raw) To: Abhinav Kumar, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul On 16/11/2022 11:30, Abhinav Kumar wrote: > > > On 11/16/2022 12:19 AM, Dmitry Baryshkov wrote: >> On 16/11/2022 10:50, Abhinav Kumar wrote: >>> >>> >>> On 11/4/2022 6:03 AM, Dmitry Baryshkov wrote: >>>> On sm8450 a register block was removed from MDP TOP. Accessing it >>>> during >>>> snapshotting results in NoC errors / immediate reboot. Skip accessing >>>> these registers during snapshot. >>>> >>>> Tested-by: Vinod Koul <vkoul@kernel.org> >>>> Reviewed-by: Vinod Koul <vkoul@kernel.org> >>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>> >>> I am confused with both the ordering and the split of this patch. >>> >>> You have defined DPU_MDP_PERIPH_0_REMOVED in the catalog header file >>> in this patch but used it in the next. >>> >>> But you also have code in this patch which relies on setting of this >>> bit. >>> >>> So if this patch is taken without the next, it will still crash. >> >> It will not crash if this patch is taken without the next one. Without >> the next patch the DPU driver will not match and bind against the >> qcom,sm8450-dpu device. > > Ah okay, I just now saw that you have the compatible change also in the > next patch. > >> >> So, the ordering is quite logical from my point of view: >> - add support for all the features required for the device >> - add the device compat string & catalog entry >> >>> >>> Rather, you should combine the define part of this patch to the next >>> patch in the series >>> https://patchwork.freedesktop.org/patch/510114/?series=108883&rev=3 , >>> then move that one in front of this patch. >> >> No. This way we'll have a state (after adding the next patch) when the >> sm8450 support is enabled, but the top-hole is not handled, leading to >> a crash. >> > > What if you split the compatible to a separate patch like what SM8350 did. > > https://patchwork.freedesktop.org/patch/511659/?series=110924&rev=1 > > So, we have hw catalog changes ---> snapshot fix ---> add the compatible. I don't see any good reason to do this. Adding a define without backing implementation is a bad idea in my opinion. Regarding splitting the hw_catalog and compat. I have always considered the hw catalog entry as of_device_id.data. In other words, a devices' match data, which makes a little sense without compat entry. With the current approach each patch is atomic, it changes single point or adds a single feature, etc. > > That will make both of us happy? > >>> >>> So that its much more coherent that you defined >>> DPU_MDP_PERIPH_0_REMOVED both in the catalog header and used it in >>> the catalog.c file and the in the next change you used the caps to >>> avoid touching that register. >> >> I'd say it's rather strange way. When I see a define/feature addition, >> I'd prefer to seethe implementation too. >> >>> Regarding the TOP hole itself, I need one day to investigate this. I >>> am waiting for permissions to the documentation. >>> >>> If i cannot get access by the time you have re-ordered this, I will >>> ack this once the reorder is done within a day. >> >> >> For the reference: [1] >> >> [1] >> https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers/-/commit/f9ff8af5b640147f3651c23551c60f81f62874b1 >> >>> >>>> --- >>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + >>>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++-- >>>> 2 files changed, 10 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>> index 38aa38ab1568..4730f8268f2a 100644 >>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>> @@ -92,6 +92,7 @@ enum { >>>> DPU_MDP_UBWC_1_0, >>>> DPU_MDP_UBWC_1_5, >>>> DPU_MDP_AUDIO_SELECT, >>>> + DPU_MDP_PERIPH_0_REMOVED, >>>> DPU_MDP_MAX >>>> }; >>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>> index f3660cd14f4f..95d8765c1c53 100644 >>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>> @@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct >>>> msm_disp_state *disp_state, struct msm_k >>>> msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, >>>> dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); >>>> - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >>>> - dpu_kms->mmio + cat->mdp[0].base, "top"); >>>> + if (dpu_kms->hw_mdp->caps->features & >>>> BIT(DPU_MDP_PERIPH_0_REMOVED)) { >>>> + msm_disp_snapshot_add_block(disp_state, 0x380, >>>> + dpu_kms->mmio + cat->mdp[0].base, "top"); >>>> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - >>>> 0x3a8, >>>> + dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2"); >>>> + } else { >>>> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >>>> + dpu_kms->mmio + cat->mdp[0].base, "top"); >>>> + } >>>> pm_runtime_put_sync(&dpu_kms->pdev->dev); >>>> } >> -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 6/8] drm/msm/dpu: add support for MDP_TOP blackhole 2022-11-16 9:18 ` Dmitry Baryshkov @ 2022-11-16 9:29 ` Abhinav Kumar -1 siblings, 0 replies; 62+ messages in thread From: Abhinav Kumar @ 2022-11-16 9:29 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul On 11/16/2022 1:18 AM, Dmitry Baryshkov wrote: > On 16/11/2022 11:30, Abhinav Kumar wrote: >> >> >> On 11/16/2022 12:19 AM, Dmitry Baryshkov wrote: >>> On 16/11/2022 10:50, Abhinav Kumar wrote: >>>> >>>> >>>> On 11/4/2022 6:03 AM, Dmitry Baryshkov wrote: >>>>> On sm8450 a register block was removed from MDP TOP. Accessing it >>>>> during >>>>> snapshotting results in NoC errors / immediate reboot. Skip accessing >>>>> these registers during snapshot. >>>>> >>>>> Tested-by: Vinod Koul <vkoul@kernel.org> >>>>> Reviewed-by: Vinod Koul <vkoul@kernel.org> >>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>>> >>>> I am confused with both the ordering and the split of this patch. >>>> >>>> You have defined DPU_MDP_PERIPH_0_REMOVED in the catalog header file >>>> in this patch but used it in the next. >>>> >>>> But you also have code in this patch which relies on setting of this >>>> bit. >>>> >>>> So if this patch is taken without the next, it will still crash. >>> >>> It will not crash if this patch is taken without the next one. >>> Without the next patch the DPU driver will not match and bind against >>> the qcom,sm8450-dpu device. >> >> Ah okay, I just now saw that you have the compatible change also in >> the next patch. >> >>> >>> So, the ordering is quite logical from my point of view: >>> - add support for all the features required for the device >>> - add the device compat string & catalog entry >>> >>>> >>>> Rather, you should combine the define part of this patch to the next >>>> patch in the series >>>> https://patchwork.freedesktop.org/patch/510114/?series=108883&rev=3 >>>> , then move that one in front of this patch. >>> >>> No. This way we'll have a state (after adding the next patch) when >>> the sm8450 support is enabled, but the top-hole is not handled, >>> leading to a crash. >>> >> >> What if you split the compatible to a separate patch like what SM8350 >> did. >> >> https://patchwork.freedesktop.org/patch/511659/?series=110924&rev=1 >> >> So, we have hw catalog changes ---> snapshot fix ---> add the compatible. > > I don't see any good reason to do this. Adding a define without backing > implementation is a bad idea in my opinion. > The define is used in two places today. First in the catalog and second in the snapshot (which is your change). Even with the split i am suggesting the define and usage will be together. In fact, in my opinion thats more coherent because you defined the macro, used it to show that sm8450 has this TOP_HOLE. Then, you are using the hw->caps which will be set in the previous patch to avoid that region in the snapshot. The good reason to do it this way is that, with this current ordering of patch, this patch is essentially a dummy patch because technically no chipset has set this capability. But if you follow the order i am suggesting, it actually has more meaning because we know sm8450 has set it in its caps before you use it. > Regarding splitting the hw_catalog and compat. I have always considered > the hw catalog entry as of_device_id.data. In other words, a devices' > match data, which makes a little sense without compat entry. > > With the current approach each patch is atomic, it changes single point > or adds a single feature, etc. > >> >> That will make both of us happy? >> >>>> >>>> So that its much more coherent that you defined >>>> DPU_MDP_PERIPH_0_REMOVED both in the catalog header and used it in >>>> the catalog.c file and the in the next change you used the caps to >>>> avoid touching that register. >>> >>> I'd say it's rather strange way. When I see a define/feature >>> addition, I'd prefer to seethe implementation too. >>> >>>> Regarding the TOP hole itself, I need one day to investigate this. I >>>> am waiting for permissions to the documentation. >>>> >>>> If i cannot get access by the time you have re-ordered this, I will >>>> ack this once the reorder is done within a day. >>> >>> >>> For the reference: [1] >>> >>> [1] >>> https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers/-/commit/f9ff8af5b640147f3651c23551c60f81f62874b1 >>> >>> >>>> >>>>> --- >>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + >>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++-- >>>>> 2 files changed, 10 insertions(+), 2 deletions(-) >>>>> >>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>>> index 38aa38ab1568..4730f8268f2a 100644 >>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>>> @@ -92,6 +92,7 @@ enum { >>>>> DPU_MDP_UBWC_1_0, >>>>> DPU_MDP_UBWC_1_5, >>>>> DPU_MDP_AUDIO_SELECT, >>>>> + DPU_MDP_PERIPH_0_REMOVED, >>>>> DPU_MDP_MAX >>>>> }; >>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>>> index f3660cd14f4f..95d8765c1c53 100644 >>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>>> @@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct >>>>> msm_disp_state *disp_state, struct msm_k >>>>> msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, >>>>> dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); >>>>> - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >>>>> - dpu_kms->mmio + cat->mdp[0].base, "top"); >>>>> + if (dpu_kms->hw_mdp->caps->features & >>>>> BIT(DPU_MDP_PERIPH_0_REMOVED)) { >>>>> + msm_disp_snapshot_add_block(disp_state, 0x380, >>>>> + dpu_kms->mmio + cat->mdp[0].base, "top"); >>>>> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - >>>>> 0x3a8, >>>>> + dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2"); >>>>> + } else { >>>>> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >>>>> + dpu_kms->mmio + cat->mdp[0].base, "top"); >>>>> + } >>>>> pm_runtime_put_sync(&dpu_kms->pdev->dev); >>>>> } >>> > ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 6/8] drm/msm/dpu: add support for MDP_TOP blackhole @ 2022-11-16 9:29 ` Abhinav Kumar 0 siblings, 0 replies; 62+ messages in thread From: Abhinav Kumar @ 2022-11-16 9:29 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, freedreno On 11/16/2022 1:18 AM, Dmitry Baryshkov wrote: > On 16/11/2022 11:30, Abhinav Kumar wrote: >> >> >> On 11/16/2022 12:19 AM, Dmitry Baryshkov wrote: >>> On 16/11/2022 10:50, Abhinav Kumar wrote: >>>> >>>> >>>> On 11/4/2022 6:03 AM, Dmitry Baryshkov wrote: >>>>> On sm8450 a register block was removed from MDP TOP. Accessing it >>>>> during >>>>> snapshotting results in NoC errors / immediate reboot. Skip accessing >>>>> these registers during snapshot. >>>>> >>>>> Tested-by: Vinod Koul <vkoul@kernel.org> >>>>> Reviewed-by: Vinod Koul <vkoul@kernel.org> >>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>>> >>>> I am confused with both the ordering and the split of this patch. >>>> >>>> You have defined DPU_MDP_PERIPH_0_REMOVED in the catalog header file >>>> in this patch but used it in the next. >>>> >>>> But you also have code in this patch which relies on setting of this >>>> bit. >>>> >>>> So if this patch is taken without the next, it will still crash. >>> >>> It will not crash if this patch is taken without the next one. >>> Without the next patch the DPU driver will not match and bind against >>> the qcom,sm8450-dpu device. >> >> Ah okay, I just now saw that you have the compatible change also in >> the next patch. >> >>> >>> So, the ordering is quite logical from my point of view: >>> - add support for all the features required for the device >>> - add the device compat string & catalog entry >>> >>>> >>>> Rather, you should combine the define part of this patch to the next >>>> patch in the series >>>> https://patchwork.freedesktop.org/patch/510114/?series=108883&rev=3 >>>> , then move that one in front of this patch. >>> >>> No. This way we'll have a state (after adding the next patch) when >>> the sm8450 support is enabled, but the top-hole is not handled, >>> leading to a crash. >>> >> >> What if you split the compatible to a separate patch like what SM8350 >> did. >> >> https://patchwork.freedesktop.org/patch/511659/?series=110924&rev=1 >> >> So, we have hw catalog changes ---> snapshot fix ---> add the compatible. > > I don't see any good reason to do this. Adding a define without backing > implementation is a bad idea in my opinion. > The define is used in two places today. First in the catalog and second in the snapshot (which is your change). Even with the split i am suggesting the define and usage will be together. In fact, in my opinion thats more coherent because you defined the macro, used it to show that sm8450 has this TOP_HOLE. Then, you are using the hw->caps which will be set in the previous patch to avoid that region in the snapshot. The good reason to do it this way is that, with this current ordering of patch, this patch is essentially a dummy patch because technically no chipset has set this capability. But if you follow the order i am suggesting, it actually has more meaning because we know sm8450 has set it in its caps before you use it. > Regarding splitting the hw_catalog and compat. I have always considered > the hw catalog entry as of_device_id.data. In other words, a devices' > match data, which makes a little sense without compat entry. > > With the current approach each patch is atomic, it changes single point > or adds a single feature, etc. > >> >> That will make both of us happy? >> >>>> >>>> So that its much more coherent that you defined >>>> DPU_MDP_PERIPH_0_REMOVED both in the catalog header and used it in >>>> the catalog.c file and the in the next change you used the caps to >>>> avoid touching that register. >>> >>> I'd say it's rather strange way. When I see a define/feature >>> addition, I'd prefer to seethe implementation too. >>> >>>> Regarding the TOP hole itself, I need one day to investigate this. I >>>> am waiting for permissions to the documentation. >>>> >>>> If i cannot get access by the time you have re-ordered this, I will >>>> ack this once the reorder is done within a day. >>> >>> >>> For the reference: [1] >>> >>> [1] >>> https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers/-/commit/f9ff8af5b640147f3651c23551c60f81f62874b1 >>> >>> >>>> >>>>> --- >>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + >>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++-- >>>>> 2 files changed, 10 insertions(+), 2 deletions(-) >>>>> >>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>>> index 38aa38ab1568..4730f8268f2a 100644 >>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>>> @@ -92,6 +92,7 @@ enum { >>>>> DPU_MDP_UBWC_1_0, >>>>> DPU_MDP_UBWC_1_5, >>>>> DPU_MDP_AUDIO_SELECT, >>>>> + DPU_MDP_PERIPH_0_REMOVED, >>>>> DPU_MDP_MAX >>>>> }; >>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>>> index f3660cd14f4f..95d8765c1c53 100644 >>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>>> @@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct >>>>> msm_disp_state *disp_state, struct msm_k >>>>> msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, >>>>> dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); >>>>> - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >>>>> - dpu_kms->mmio + cat->mdp[0].base, "top"); >>>>> + if (dpu_kms->hw_mdp->caps->features & >>>>> BIT(DPU_MDP_PERIPH_0_REMOVED)) { >>>>> + msm_disp_snapshot_add_block(disp_state, 0x380, >>>>> + dpu_kms->mmio + cat->mdp[0].base, "top"); >>>>> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - >>>>> 0x3a8, >>>>> + dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2"); >>>>> + } else { >>>>> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >>>>> + dpu_kms->mmio + cat->mdp[0].base, "top"); >>>>> + } >>>>> pm_runtime_put_sync(&dpu_kms->pdev->dev); >>>>> } >>> > ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 6/8] drm/msm/dpu: add support for MDP_TOP blackhole 2022-11-16 9:29 ` Abhinav Kumar @ 2022-11-16 9:43 ` Dmitry Baryshkov -1 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-16 9:43 UTC (permalink / raw) To: Abhinav Kumar, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul On 16/11/2022 12:29, Abhinav Kumar wrote: > > > On 11/16/2022 1:18 AM, Dmitry Baryshkov wrote: >> On 16/11/2022 11:30, Abhinav Kumar wrote: >>> >>> >>> On 11/16/2022 12:19 AM, Dmitry Baryshkov wrote: >>>> On 16/11/2022 10:50, Abhinav Kumar wrote: >>>>> >>>>> >>>>> On 11/4/2022 6:03 AM, Dmitry Baryshkov wrote: >>>>>> On sm8450 a register block was removed from MDP TOP. Accessing it >>>>>> during >>>>>> snapshotting results in NoC errors / immediate reboot. Skip accessing >>>>>> these registers during snapshot. >>>>>> >>>>>> Tested-by: Vinod Koul <vkoul@kernel.org> >>>>>> Reviewed-by: Vinod Koul <vkoul@kernel.org> >>>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>>>> >>>>> I am confused with both the ordering and the split of this patch. >>>>> >>>>> You have defined DPU_MDP_PERIPH_0_REMOVED in the catalog header >>>>> file in this patch but used it in the next. >>>>> >>>>> But you also have code in this patch which relies on setting of >>>>> this bit. >>>>> >>>>> So if this patch is taken without the next, it will still crash. >>>> >>>> It will not crash if this patch is taken without the next one. >>>> Without the next patch the DPU driver will not match and bind >>>> against the qcom,sm8450-dpu device. >>> >>> Ah okay, I just now saw that you have the compatible change also in >>> the next patch. >>> >>>> >>>> So, the ordering is quite logical from my point of view: >>>> - add support for all the features required for the device >>>> - add the device compat string & catalog entry >>>> >>>>> >>>>> Rather, you should combine the define part of this patch to the >>>>> next patch in the series >>>>> https://patchwork.freedesktop.org/patch/510114/?series=108883&rev=3 >>>>> , then move that one in front of this patch. >>>> >>>> No. This way we'll have a state (after adding the next patch) when >>>> the sm8450 support is enabled, but the top-hole is not handled, >>>> leading to a crash. >>>> >>> >>> What if you split the compatible to a separate patch like what SM8350 >>> did. >>> >>> https://patchwork.freedesktop.org/patch/511659/?series=110924&rev=1 >>> >>> So, we have hw catalog changes ---> snapshot fix ---> add the >>> compatible. >> >> I don't see any good reason to do this. Adding a define without >> backing implementation is a bad idea in my opinion. >> > > The define is used in two places today. First in the catalog and second > in the snapshot (which is your change). > > Even with the split i am suggesting the define and usage will be together. > > In fact, in my opinion thats more coherent because you defined the > macro, used it to show that sm8450 has this TOP_HOLE. > > Then, you are using the hw->caps which will be set in the previous patch > to avoid that region in the snapshot. > > The good reason to do it this way is that, with this current ordering of > patch, this patch is essentially a dummy patch because technically no > chipset has set this capability. It's not dummy, because it clearly shows, what really is beyond this capability. A feature without a backing implementation would be a dummy patch (even if it's mentioned in the hw catalog entry). Just a simple check. If we use a guillotine and cut the patch series in the middle, which one will make more sense: - #define DPU_MDP_TOP_UGLY add DPU_MDP_TOP_UGLY to sdm999's features - #define DPU_MDP_TOP_UGLY add an implementation of DPU_MDP_TOP_UGLY describing what it does With the first approach the MDP_TOP_UGLY is an ugly define without any particular meaning. Mentioning it in the hw_catalog doesn't bring us any additional information (in other words, what does it mean that sdm999 has MDP_TOP_UGLY feature?). The second approach doesn't bind any chipset to use MDP_TOP_UGLY. But knowing the implementation, one can check whether it applies to his chipset or not. Yes, I must admit, this case is a little bit odd. Regularly I'd have added the sm8450's compat string and catalog entries, then I'd have populated the catalog with new features one by one (using implementation + define + hw_catalog patch), like we do e.g. for DSC, WB, DSPP_sub_flush, etc. In this particular case, sm8450 will not work without PERIPH_0_REMOVED, as the first DSI underrun, which can easily happen while turning on the INTF, will reboot the board. > > But if you follow the order i am suggesting, it actually has more > meaning because we know sm8450 has set it in its caps before you use it. > >> Regarding splitting the hw_catalog and compat. I have always >> considered the hw catalog entry as of_device_id.data. In other words, >> a devices' match data, which makes a little sense without compat entry. >> >> With the current approach each patch is atomic, it changes single >> point or adds a single feature, etc. >> >>> >>> That will make both of us happy? >>> >>>>> >>>>> So that its much more coherent that you defined >>>>> DPU_MDP_PERIPH_0_REMOVED both in the catalog header and used it in >>>>> the catalog.c file and the in the next change you used the caps to >>>>> avoid touching that register. >>>> >>>> I'd say it's rather strange way. When I see a define/feature >>>> addition, I'd prefer to seethe implementation too. >>>> >>>>> Regarding the TOP hole itself, I need one day to investigate this. >>>>> I am waiting for permissions to the documentation. >>>>> >>>>> If i cannot get access by the time you have re-ordered this, I will >>>>> ack this once the reorder is done within a day. >>>> >>>> >>>> For the reference: [1] >>>> >>>> [1] >>>> https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers/-/commit/f9ff8af5b640147f3651c23551c60f81f62874b1 >>>> >>>>> >>>>>> --- >>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + >>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++-- >>>>>> 2 files changed, 10 insertions(+), 2 deletions(-) >>>>>> >>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>>>> index 38aa38ab1568..4730f8268f2a 100644 >>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>>>> @@ -92,6 +92,7 @@ enum { >>>>>> DPU_MDP_UBWC_1_0, >>>>>> DPU_MDP_UBWC_1_5, >>>>>> DPU_MDP_AUDIO_SELECT, >>>>>> + DPU_MDP_PERIPH_0_REMOVED, >>>>>> DPU_MDP_MAX >>>>>> }; >>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>>>> index f3660cd14f4f..95d8765c1c53 100644 >>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>>>> @@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct >>>>>> msm_disp_state *disp_state, struct msm_k >>>>>> msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, >>>>>> dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); >>>>>> - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >>>>>> - dpu_kms->mmio + cat->mdp[0].base, "top"); >>>>>> + if (dpu_kms->hw_mdp->caps->features & >>>>>> BIT(DPU_MDP_PERIPH_0_REMOVED)) { >>>>>> + msm_disp_snapshot_add_block(disp_state, 0x380, >>>>>> + dpu_kms->mmio + cat->mdp[0].base, "top"); >>>>>> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - >>>>>> 0x3a8, >>>>>> + dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2"); >>>>>> + } else { >>>>>> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >>>>>> + dpu_kms->mmio + cat->mdp[0].base, "top"); >>>>>> + } >>>>>> pm_runtime_put_sync(&dpu_kms->pdev->dev); >>>>>> } >>>> >> -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 6/8] drm/msm/dpu: add support for MDP_TOP blackhole @ 2022-11-16 9:43 ` Dmitry Baryshkov 0 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-16 9:43 UTC (permalink / raw) To: Abhinav Kumar, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, freedreno On 16/11/2022 12:29, Abhinav Kumar wrote: > > > On 11/16/2022 1:18 AM, Dmitry Baryshkov wrote: >> On 16/11/2022 11:30, Abhinav Kumar wrote: >>> >>> >>> On 11/16/2022 12:19 AM, Dmitry Baryshkov wrote: >>>> On 16/11/2022 10:50, Abhinav Kumar wrote: >>>>> >>>>> >>>>> On 11/4/2022 6:03 AM, Dmitry Baryshkov wrote: >>>>>> On sm8450 a register block was removed from MDP TOP. Accessing it >>>>>> during >>>>>> snapshotting results in NoC errors / immediate reboot. Skip accessing >>>>>> these registers during snapshot. >>>>>> >>>>>> Tested-by: Vinod Koul <vkoul@kernel.org> >>>>>> Reviewed-by: Vinod Koul <vkoul@kernel.org> >>>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>>>> >>>>> I am confused with both the ordering and the split of this patch. >>>>> >>>>> You have defined DPU_MDP_PERIPH_0_REMOVED in the catalog header >>>>> file in this patch but used it in the next. >>>>> >>>>> But you also have code in this patch which relies on setting of >>>>> this bit. >>>>> >>>>> So if this patch is taken without the next, it will still crash. >>>> >>>> It will not crash if this patch is taken without the next one. >>>> Without the next patch the DPU driver will not match and bind >>>> against the qcom,sm8450-dpu device. >>> >>> Ah okay, I just now saw that you have the compatible change also in >>> the next patch. >>> >>>> >>>> So, the ordering is quite logical from my point of view: >>>> - add support for all the features required for the device >>>> - add the device compat string & catalog entry >>>> >>>>> >>>>> Rather, you should combine the define part of this patch to the >>>>> next patch in the series >>>>> https://patchwork.freedesktop.org/patch/510114/?series=108883&rev=3 >>>>> , then move that one in front of this patch. >>>> >>>> No. This way we'll have a state (after adding the next patch) when >>>> the sm8450 support is enabled, but the top-hole is not handled, >>>> leading to a crash. >>>> >>> >>> What if you split the compatible to a separate patch like what SM8350 >>> did. >>> >>> https://patchwork.freedesktop.org/patch/511659/?series=110924&rev=1 >>> >>> So, we have hw catalog changes ---> snapshot fix ---> add the >>> compatible. >> >> I don't see any good reason to do this. Adding a define without >> backing implementation is a bad idea in my opinion. >> > > The define is used in two places today. First in the catalog and second > in the snapshot (which is your change). > > Even with the split i am suggesting the define and usage will be together. > > In fact, in my opinion thats more coherent because you defined the > macro, used it to show that sm8450 has this TOP_HOLE. > > Then, you are using the hw->caps which will be set in the previous patch > to avoid that region in the snapshot. > > The good reason to do it this way is that, with this current ordering of > patch, this patch is essentially a dummy patch because technically no > chipset has set this capability. It's not dummy, because it clearly shows, what really is beyond this capability. A feature without a backing implementation would be a dummy patch (even if it's mentioned in the hw catalog entry). Just a simple check. If we use a guillotine and cut the patch series in the middle, which one will make more sense: - #define DPU_MDP_TOP_UGLY add DPU_MDP_TOP_UGLY to sdm999's features - #define DPU_MDP_TOP_UGLY add an implementation of DPU_MDP_TOP_UGLY describing what it does With the first approach the MDP_TOP_UGLY is an ugly define without any particular meaning. Mentioning it in the hw_catalog doesn't bring us any additional information (in other words, what does it mean that sdm999 has MDP_TOP_UGLY feature?). The second approach doesn't bind any chipset to use MDP_TOP_UGLY. But knowing the implementation, one can check whether it applies to his chipset or not. Yes, I must admit, this case is a little bit odd. Regularly I'd have added the sm8450's compat string and catalog entries, then I'd have populated the catalog with new features one by one (using implementation + define + hw_catalog patch), like we do e.g. for DSC, WB, DSPP_sub_flush, etc. In this particular case, sm8450 will not work without PERIPH_0_REMOVED, as the first DSI underrun, which can easily happen while turning on the INTF, will reboot the board. > > But if you follow the order i am suggesting, it actually has more > meaning because we know sm8450 has set it in its caps before you use it. > >> Regarding splitting the hw_catalog and compat. I have always >> considered the hw catalog entry as of_device_id.data. In other words, >> a devices' match data, which makes a little sense without compat entry. >> >> With the current approach each patch is atomic, it changes single >> point or adds a single feature, etc. >> >>> >>> That will make both of us happy? >>> >>>>> >>>>> So that its much more coherent that you defined >>>>> DPU_MDP_PERIPH_0_REMOVED both in the catalog header and used it in >>>>> the catalog.c file and the in the next change you used the caps to >>>>> avoid touching that register. >>>> >>>> I'd say it's rather strange way. When I see a define/feature >>>> addition, I'd prefer to seethe implementation too. >>>> >>>>> Regarding the TOP hole itself, I need one day to investigate this. >>>>> I am waiting for permissions to the documentation. >>>>> >>>>> If i cannot get access by the time you have re-ordered this, I will >>>>> ack this once the reorder is done within a day. >>>> >>>> >>>> For the reference: [1] >>>> >>>> [1] >>>> https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers/-/commit/f9ff8af5b640147f3651c23551c60f81f62874b1 >>>> >>>>> >>>>>> --- >>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + >>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++-- >>>>>> 2 files changed, 10 insertions(+), 2 deletions(-) >>>>>> >>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>>>> index 38aa38ab1568..4730f8268f2a 100644 >>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>>>> @@ -92,6 +92,7 @@ enum { >>>>>> DPU_MDP_UBWC_1_0, >>>>>> DPU_MDP_UBWC_1_5, >>>>>> DPU_MDP_AUDIO_SELECT, >>>>>> + DPU_MDP_PERIPH_0_REMOVED, >>>>>> DPU_MDP_MAX >>>>>> }; >>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>>>> index f3660cd14f4f..95d8765c1c53 100644 >>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>>>> @@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct >>>>>> msm_disp_state *disp_state, struct msm_k >>>>>> msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, >>>>>> dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); >>>>>> - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >>>>>> - dpu_kms->mmio + cat->mdp[0].base, "top"); >>>>>> + if (dpu_kms->hw_mdp->caps->features & >>>>>> BIT(DPU_MDP_PERIPH_0_REMOVED)) { >>>>>> + msm_disp_snapshot_add_block(disp_state, 0x380, >>>>>> + dpu_kms->mmio + cat->mdp[0].base, "top"); >>>>>> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - >>>>>> 0x3a8, >>>>>> + dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2"); >>>>>> + } else { >>>>>> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >>>>>> + dpu_kms->mmio + cat->mdp[0].base, "top"); >>>>>> + } >>>>>> pm_runtime_put_sync(&dpu_kms->pdev->dev); >>>>>> } >>>> >> -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 6/8] drm/msm/dpu: add support for MDP_TOP blackhole 2022-11-16 9:43 ` Dmitry Baryshkov @ 2022-11-16 9:59 ` Abhinav Kumar -1 siblings, 0 replies; 62+ messages in thread From: Abhinav Kumar @ 2022-11-16 9:59 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul On 11/16/2022 1:43 AM, Dmitry Baryshkov wrote: > On 16/11/2022 12:29, Abhinav Kumar wrote: >> >> >> On 11/16/2022 1:18 AM, Dmitry Baryshkov wrote: >>> On 16/11/2022 11:30, Abhinav Kumar wrote: >>>> >>>> >>>> On 11/16/2022 12:19 AM, Dmitry Baryshkov wrote: >>>>> On 16/11/2022 10:50, Abhinav Kumar wrote: >>>>>> >>>>>> >>>>>> On 11/4/2022 6:03 AM, Dmitry Baryshkov wrote: >>>>>>> On sm8450 a register block was removed from MDP TOP. Accessing it >>>>>>> during >>>>>>> snapshotting results in NoC errors / immediate reboot. Skip >>>>>>> accessing >>>>>>> these registers during snapshot. >>>>>>> >>>>>>> Tested-by: Vinod Koul <vkoul@kernel.org> >>>>>>> Reviewed-by: Vinod Koul <vkoul@kernel.org> >>>>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>>>>> >>>>>> I am confused with both the ordering and the split of this patch. >>>>>> >>>>>> You have defined DPU_MDP_PERIPH_0_REMOVED in the catalog header >>>>>> file in this patch but used it in the next. >>>>>> >>>>>> But you also have code in this patch which relies on setting of >>>>>> this bit. >>>>>> >>>>>> So if this patch is taken without the next, it will still crash. >>>>> >>>>> It will not crash if this patch is taken without the next one. >>>>> Without the next patch the DPU driver will not match and bind >>>>> against the qcom,sm8450-dpu device. >>>> >>>> Ah okay, I just now saw that you have the compatible change also in >>>> the next patch. >>>> >>>>> >>>>> So, the ordering is quite logical from my point of view: >>>>> - add support for all the features required for the device >>>>> - add the device compat string & catalog entry >>>>> >>>>>> >>>>>> Rather, you should combine the define part of this patch to the >>>>>> next patch in the series >>>>>> https://patchwork.freedesktop.org/patch/510114/?series=108883&rev=3 , >>>>>> then move that one in front of this patch. >>>>> >>>>> No. This way we'll have a state (after adding the next patch) when >>>>> the sm8450 support is enabled, but the top-hole is not handled, >>>>> leading to a crash. >>>>> >>>> >>>> What if you split the compatible to a separate patch like what >>>> SM8350 did. >>>> >>>> https://patchwork.freedesktop.org/patch/511659/?series=110924&rev=1 >>>> >>>> So, we have hw catalog changes ---> snapshot fix ---> add the >>>> compatible. >>> >>> I don't see any good reason to do this. Adding a define without >>> backing implementation is a bad idea in my opinion. >>> >> >> The define is used in two places today. First in the catalog and >> second in the snapshot (which is your change). >> >> Even with the split i am suggesting the define and usage will be >> together. >> >> In fact, in my opinion thats more coherent because you defined the >> macro, used it to show that sm8450 has this TOP_HOLE. >> >> Then, you are using the hw->caps which will be set in the previous >> patch to avoid that region in the snapshot. >> >> The good reason to do it this way is that, with this current ordering >> of patch, this patch is essentially a dummy patch because technically >> no chipset has set this capability. > > It's not dummy, because it clearly shows, what really is beyond this > capability. A feature without a backing implementation would be a dummy > patch (even if it's mentioned in the hw catalog entry). > > Just a simple check. If we use a guillotine and cut the patch series in > the middle, which one will make more sense: > > - #define DPU_MDP_TOP_UGLY > add DPU_MDP_TOP_UGLY to sdm999's features > > - #define DPU_MDP_TOP_UGLY > add an implementation of DPU_MDP_TOP_UGLY describing what it does > > With the first approach the MDP_TOP_UGLY is an ugly define without any > particular meaning. Mentioning it in the hw_catalog doesn't bring us any > additional information (in other words, what does it mean that sdm999 > has MDP_TOP_UGLY feature?). Okay, one last point about this. Your response actually brought up another comment on this patch. You have not documented what this macro does in this enum either in this patch or the next. 78 * MDP TOP BLOCK features 79 * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe 80 * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats 81 * @DPU_MDP_BWC, MDSS HW supports Bandwidth compression. 82 * @DPU_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth 83 * compression initial revision 84 * @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5 85 * @DPU_MDP_MAX Maximum value 86 87 */ 88 enum { 89 DPU_MDP_PANIC_PER_PIPE = 0x1, 90 DPU_MDP_10BIT_SUPPORT, 91 DPU_MDP_BWC, 92 DPU_MDP_UBWC_1_0, 93 DPU_MDP_UBWC_1_5, 94 DPU_MDP_AUDIO_SELECT, 95 DPU_MDP_MAX 96 }; If that was done, that would certainly clear the doubts about what this does. Snapshot is just one usage of this enum. We are advertizing this enum as a chipset level capability. So if we group it the way you mentioned as incorrect, lets view it another way. - #define DPU_MDP_TOP_UGLY AND document what it means as we are supposed to add DPU_MDP_TOP_UGLY to sdm999's features Now, we know what it means and also which chipset it applies to in the same change rather than looking at two changes to achieve this. Lastly, we are using this capability to avoid access to the snapshot. That may not be the only usage of that capability. > > The second approach doesn't bind any chipset to use MDP_TOP_UGLY. But > knowing the implementation, one can check whether it applies to his > chipset or not. > > Yes, I must admit, this case is a little bit odd. Regularly I'd have > added the sm8450's compat string and catalog entries, then I'd have > populated the catalog with new features one by one (using implementation > + define + hw_catalog patch), like we do e.g. for DSC, WB, > DSPP_sub_flush, etc. In this particular case, sm8450 will not work > without PERIPH_0_REMOVED, as the first DSI underrun, which can easily > happen while turning on the INTF, will reboot the board. I am not going to hold off this patch for this reason but like I have said before, even if the order is maintained the way I mentioned by splitting the compatible similar to the SM8350 series, it will not cause reboot. Yes, I do recall the first DSI underrun issue on the SM8450 board so i certainly realize we cannot let it boot without blocking access to the hole. > >> >> But if you follow the order i am suggesting, it actually has more >> meaning because we know sm8450 has set it in its caps before you use it. >> >>> Regarding splitting the hw_catalog and compat. I have always >>> considered the hw catalog entry as of_device_id.data. In other words, >>> a devices' match data, which makes a little sense without compat entry. >>> >>> With the current approach each patch is atomic, it changes single >>> point or adds a single feature, etc. >>> >>>> >>>> That will make both of us happy? >>>> >>>>>> >>>>>> So that its much more coherent that you defined >>>>>> DPU_MDP_PERIPH_0_REMOVED both in the catalog header and used it in >>>>>> the catalog.c file and the in the next change you used the caps to >>>>>> avoid touching that register. >>>>> >>>>> I'd say it's rather strange way. When I see a define/feature >>>>> addition, I'd prefer to seethe implementation too. >>>>> >>>>>> Regarding the TOP hole itself, I need one day to investigate this. >>>>>> I am waiting for permissions to the documentation. >>>>>> >>>>>> If i cannot get access by the time you have re-ordered this, I >>>>>> will ack this once the reorder is done within a day. >>>>> >>>>> >>>>> For the reference: [1] >>>>> >>>>> [1] >>>>> https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers/-/commit/f9ff8af5b640147f3651c23551c60f81f62874b1 >>>>> >>>>> >>>>>> >>>>>>> --- >>>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + >>>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++-- >>>>>>> 2 files changed, 10 insertions(+), 2 deletions(-) >>>>>>> >>>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>>>>> index 38aa38ab1568..4730f8268f2a 100644 >>>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>>>>> @@ -92,6 +92,7 @@ enum { >>>>>>> DPU_MDP_UBWC_1_0, >>>>>>> DPU_MDP_UBWC_1_5, >>>>>>> DPU_MDP_AUDIO_SELECT, >>>>>>> + DPU_MDP_PERIPH_0_REMOVED, >>>>>>> DPU_MDP_MAX >>>>>>> }; >>>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>>>>> index f3660cd14f4f..95d8765c1c53 100644 >>>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>>>>> @@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct >>>>>>> msm_disp_state *disp_state, struct msm_k >>>>>>> msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, >>>>>>> dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); >>>>>>> - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >>>>>>> - dpu_kms->mmio + cat->mdp[0].base, "top"); >>>>>>> + if (dpu_kms->hw_mdp->caps->features & >>>>>>> BIT(DPU_MDP_PERIPH_0_REMOVED)) { >>>>>>> + msm_disp_snapshot_add_block(disp_state, 0x380, >>>>>>> + dpu_kms->mmio + cat->mdp[0].base, "top"); >>>>>>> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len >>>>>>> - 0x3a8, >>>>>>> + dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2"); >>>>>>> + } else { >>>>>>> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >>>>>>> + dpu_kms->mmio + cat->mdp[0].base, "top"); >>>>>>> + } >>>>>>> pm_runtime_put_sync(&dpu_kms->pdev->dev); >>>>>>> } >>>>> >>> > ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 6/8] drm/msm/dpu: add support for MDP_TOP blackhole @ 2022-11-16 9:59 ` Abhinav Kumar 0 siblings, 0 replies; 62+ messages in thread From: Abhinav Kumar @ 2022-11-16 9:59 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, freedreno On 11/16/2022 1:43 AM, Dmitry Baryshkov wrote: > On 16/11/2022 12:29, Abhinav Kumar wrote: >> >> >> On 11/16/2022 1:18 AM, Dmitry Baryshkov wrote: >>> On 16/11/2022 11:30, Abhinav Kumar wrote: >>>> >>>> >>>> On 11/16/2022 12:19 AM, Dmitry Baryshkov wrote: >>>>> On 16/11/2022 10:50, Abhinav Kumar wrote: >>>>>> >>>>>> >>>>>> On 11/4/2022 6:03 AM, Dmitry Baryshkov wrote: >>>>>>> On sm8450 a register block was removed from MDP TOP. Accessing it >>>>>>> during >>>>>>> snapshotting results in NoC errors / immediate reboot. Skip >>>>>>> accessing >>>>>>> these registers during snapshot. >>>>>>> >>>>>>> Tested-by: Vinod Koul <vkoul@kernel.org> >>>>>>> Reviewed-by: Vinod Koul <vkoul@kernel.org> >>>>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>>>>> >>>>>> I am confused with both the ordering and the split of this patch. >>>>>> >>>>>> You have defined DPU_MDP_PERIPH_0_REMOVED in the catalog header >>>>>> file in this patch but used it in the next. >>>>>> >>>>>> But you also have code in this patch which relies on setting of >>>>>> this bit. >>>>>> >>>>>> So if this patch is taken without the next, it will still crash. >>>>> >>>>> It will not crash if this patch is taken without the next one. >>>>> Without the next patch the DPU driver will not match and bind >>>>> against the qcom,sm8450-dpu device. >>>> >>>> Ah okay, I just now saw that you have the compatible change also in >>>> the next patch. >>>> >>>>> >>>>> So, the ordering is quite logical from my point of view: >>>>> - add support for all the features required for the device >>>>> - add the device compat string & catalog entry >>>>> >>>>>> >>>>>> Rather, you should combine the define part of this patch to the >>>>>> next patch in the series >>>>>> https://patchwork.freedesktop.org/patch/510114/?series=108883&rev=3 , >>>>>> then move that one in front of this patch. >>>>> >>>>> No. This way we'll have a state (after adding the next patch) when >>>>> the sm8450 support is enabled, but the top-hole is not handled, >>>>> leading to a crash. >>>>> >>>> >>>> What if you split the compatible to a separate patch like what >>>> SM8350 did. >>>> >>>> https://patchwork.freedesktop.org/patch/511659/?series=110924&rev=1 >>>> >>>> So, we have hw catalog changes ---> snapshot fix ---> add the >>>> compatible. >>> >>> I don't see any good reason to do this. Adding a define without >>> backing implementation is a bad idea in my opinion. >>> >> >> The define is used in two places today. First in the catalog and >> second in the snapshot (which is your change). >> >> Even with the split i am suggesting the define and usage will be >> together. >> >> In fact, in my opinion thats more coherent because you defined the >> macro, used it to show that sm8450 has this TOP_HOLE. >> >> Then, you are using the hw->caps which will be set in the previous >> patch to avoid that region in the snapshot. >> >> The good reason to do it this way is that, with this current ordering >> of patch, this patch is essentially a dummy patch because technically >> no chipset has set this capability. > > It's not dummy, because it clearly shows, what really is beyond this > capability. A feature without a backing implementation would be a dummy > patch (even if it's mentioned in the hw catalog entry). > > Just a simple check. If we use a guillotine and cut the patch series in > the middle, which one will make more sense: > > - #define DPU_MDP_TOP_UGLY > add DPU_MDP_TOP_UGLY to sdm999's features > > - #define DPU_MDP_TOP_UGLY > add an implementation of DPU_MDP_TOP_UGLY describing what it does > > With the first approach the MDP_TOP_UGLY is an ugly define without any > particular meaning. Mentioning it in the hw_catalog doesn't bring us any > additional information (in other words, what does it mean that sdm999 > has MDP_TOP_UGLY feature?). Okay, one last point about this. Your response actually brought up another comment on this patch. You have not documented what this macro does in this enum either in this patch or the next. 78 * MDP TOP BLOCK features 79 * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe 80 * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats 81 * @DPU_MDP_BWC, MDSS HW supports Bandwidth compression. 82 * @DPU_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth 83 * compression initial revision 84 * @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5 85 * @DPU_MDP_MAX Maximum value 86 87 */ 88 enum { 89 DPU_MDP_PANIC_PER_PIPE = 0x1, 90 DPU_MDP_10BIT_SUPPORT, 91 DPU_MDP_BWC, 92 DPU_MDP_UBWC_1_0, 93 DPU_MDP_UBWC_1_5, 94 DPU_MDP_AUDIO_SELECT, 95 DPU_MDP_MAX 96 }; If that was done, that would certainly clear the doubts about what this does. Snapshot is just one usage of this enum. We are advertizing this enum as a chipset level capability. So if we group it the way you mentioned as incorrect, lets view it another way. - #define DPU_MDP_TOP_UGLY AND document what it means as we are supposed to add DPU_MDP_TOP_UGLY to sdm999's features Now, we know what it means and also which chipset it applies to in the same change rather than looking at two changes to achieve this. Lastly, we are using this capability to avoid access to the snapshot. That may not be the only usage of that capability. > > The second approach doesn't bind any chipset to use MDP_TOP_UGLY. But > knowing the implementation, one can check whether it applies to his > chipset or not. > > Yes, I must admit, this case is a little bit odd. Regularly I'd have > added the sm8450's compat string and catalog entries, then I'd have > populated the catalog with new features one by one (using implementation > + define + hw_catalog patch), like we do e.g. for DSC, WB, > DSPP_sub_flush, etc. In this particular case, sm8450 will not work > without PERIPH_0_REMOVED, as the first DSI underrun, which can easily > happen while turning on the INTF, will reboot the board. I am not going to hold off this patch for this reason but like I have said before, even if the order is maintained the way I mentioned by splitting the compatible similar to the SM8350 series, it will not cause reboot. Yes, I do recall the first DSI underrun issue on the SM8450 board so i certainly realize we cannot let it boot without blocking access to the hole. > >> >> But if you follow the order i am suggesting, it actually has more >> meaning because we know sm8450 has set it in its caps before you use it. >> >>> Regarding splitting the hw_catalog and compat. I have always >>> considered the hw catalog entry as of_device_id.data. In other words, >>> a devices' match data, which makes a little sense without compat entry. >>> >>> With the current approach each patch is atomic, it changes single >>> point or adds a single feature, etc. >>> >>>> >>>> That will make both of us happy? >>>> >>>>>> >>>>>> So that its much more coherent that you defined >>>>>> DPU_MDP_PERIPH_0_REMOVED both in the catalog header and used it in >>>>>> the catalog.c file and the in the next change you used the caps to >>>>>> avoid touching that register. >>>>> >>>>> I'd say it's rather strange way. When I see a define/feature >>>>> addition, I'd prefer to seethe implementation too. >>>>> >>>>>> Regarding the TOP hole itself, I need one day to investigate this. >>>>>> I am waiting for permissions to the documentation. >>>>>> >>>>>> If i cannot get access by the time you have re-ordered this, I >>>>>> will ack this once the reorder is done within a day. >>>>> >>>>> >>>>> For the reference: [1] >>>>> >>>>> [1] >>>>> https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers/-/commit/f9ff8af5b640147f3651c23551c60f81f62874b1 >>>>> >>>>> >>>>>> >>>>>>> --- >>>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + >>>>>>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++-- >>>>>>> 2 files changed, 10 insertions(+), 2 deletions(-) >>>>>>> >>>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>>>>> index 38aa38ab1568..4730f8268f2a 100644 >>>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >>>>>>> @@ -92,6 +92,7 @@ enum { >>>>>>> DPU_MDP_UBWC_1_0, >>>>>>> DPU_MDP_UBWC_1_5, >>>>>>> DPU_MDP_AUDIO_SELECT, >>>>>>> + DPU_MDP_PERIPH_0_REMOVED, >>>>>>> DPU_MDP_MAX >>>>>>> }; >>>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>>>>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>>>>> index f3660cd14f4f..95d8765c1c53 100644 >>>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c >>>>>>> @@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct >>>>>>> msm_disp_state *disp_state, struct msm_k >>>>>>> msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, >>>>>>> dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); >>>>>>> - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >>>>>>> - dpu_kms->mmio + cat->mdp[0].base, "top"); >>>>>>> + if (dpu_kms->hw_mdp->caps->features & >>>>>>> BIT(DPU_MDP_PERIPH_0_REMOVED)) { >>>>>>> + msm_disp_snapshot_add_block(disp_state, 0x380, >>>>>>> + dpu_kms->mmio + cat->mdp[0].base, "top"); >>>>>>> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len >>>>>>> - 0x3a8, >>>>>>> + dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2"); >>>>>>> + } else { >>>>>>> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, >>>>>>> + dpu_kms->mmio + cat->mdp[0].base, "top"); >>>>>>> + } >>>>>>> pm_runtime_put_sync(&dpu_kms->pdev->dev); >>>>>>> } >>>>> >>> > ^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v3 7/8] drm/msm/dpu: add support for SM8450 2022-11-04 13:03 ` Dmitry Baryshkov @ 2022-11-04 13:03 ` Dmitry Baryshkov -1 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-04 13:03 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul Add definitions for the display hardware used on Qualcomm SM8450 platform. Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 224 ++++++++++++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 229 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 1ce237e18506..3934d8976833 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -124,6 +124,15 @@ BIT(MDP_AD4_0_INTR) | \ BIT(MDP_AD4_1_INTR)) +#define IRQ_SM8450_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_7xxx_INTR) | \ + BIT(MDP_INTF1_7xxx_INTR) | \ + BIT(MDP_INTF2_7xxx_INTR) | \ + BIT(MDP_INTF3_7xxx_INTR) | \ + 0) + #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ BIT(DPU_WB_UBWC) | \ BIT(DPU_WB_YUV_CONFIG) | \ @@ -367,6 +376,20 @@ static const struct dpu_caps sm8250_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; +static const struct dpu_caps sm8450_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages = 0xb, + .qseed_type = DPU_SSPP_SCALER_QSEED4, + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ + .ubwc_version = DPU_HW_UBWC_VER_40, + .has_src_split = true, + .has_dim_layer = true, + .has_idle_pc = true, + .has_3d_merge = true, + .max_linewidth = 5120, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, +}; + static const struct dpu_caps sc7280_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x7, @@ -504,6 +527,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = { }, }; +static const struct dpu_mdp_cfg sm8450_mdp[] = { + { + .name = "top_0", .id = MDP_TOP, + .base = 0x0, .len = 0x494, + .features = BIT(DPU_MDP_PERIPH_0_REMOVED), + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { + .reg_off = 0x2AC, .bit_off = 0}, + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { + .reg_off = 0x2B4, .bit_off = 0}, + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { + .reg_off = 0x2BC, .bit_off = 0}, + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { + .reg_off = 0x2C4, .bit_off = 0}, + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { + .reg_off = 0x2AC, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { + .reg_off = 0x2B4, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { + .reg_off = 0x2BC, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { + .reg_off = 0x2C4, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { + .reg_off = 0x2BC, .bit_off = 20}, + }, +}; + static const struct dpu_mdp_cfg sc7280_mdp[] = { { .name = "top_0", .id = MDP_TOP, @@ -662,6 +712,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = { }, }; +static const struct dpu_ctl_cfg sm8450_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x15000, .len = 0x204, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, + { + .name = "ctl_1", .id = CTL_1, + .base = 0x16000, .len = 0x204, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, + { + .name = "ctl_2", .id = CTL_2, + .base = 0x17000, .len = 0x204, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, + { + .name = "ctl_3", .id = CTL_3, + .base = 0x18000, .len = 0x204, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, + { + .name = "ctl_4", .id = CTL_4, + .base = 0x19000, .len = 0x204, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, + { + .name = "ctl_5", .id = CTL_5, + .base = 0x1a000, .len = 0x204, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + static const struct dpu_ctl_cfg sc7280_ctl[] = { { .name = "ctl_0", .id = CTL_0, @@ -880,6 +969,34 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = { sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), }; +static const struct dpu_sspp_sub_blks sm8450_vig_sblk_0 = + _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE); +static const struct dpu_sspp_sub_blks sm8450_vig_sblk_1 = + _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE); +static const struct dpu_sspp_sub_blks sm8450_vig_sblk_2 = + _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE); +static const struct dpu_sspp_sub_blks sm8450_vig_sblk_3 = + _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE); + +static const struct dpu_sspp_cfg sm8450_sspp[] = { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, + sm8450_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK, + sm8450_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK, + sm8450_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK, + sm8450_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), +}; + static const struct dpu_sspp_cfg sc7280_sspp[] = { SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7280_MASK, sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), @@ -1191,6 +1308,34 @@ static struct dpu_pingpong_cfg qcm2290_pp[] = { DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), }; +/* FIXME: interrupts */ +static const struct dpu_pingpong_cfg sm8450_pp[] = { + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), + PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), + PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), + PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + -1), + PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + -1), + PP_BLK("pingpong_6", PINGPONG_6, 0x65800, MERGE_3D_3, sdm845_pp_sblk, + -1, + -1), + PP_BLK("pingpong_7", PINGPONG_7, 0x65c00, MERGE_3D_3, sdm845_pp_sblk, + -1, + -1), +}; + /************************************************************* * MERGE_3D sub blocks config *************************************************************/ @@ -1208,6 +1353,13 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), }; +static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), + MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00), +}; + /************************************************************* * DSC sub blocks config *************************************************************/ @@ -1287,6 +1439,13 @@ static const struct dpu_intf_cfg qcm2290_intf[] = { INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), }; +static const struct dpu_intf_cfg sm8450_intf[] = { + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29), + INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), +}; + /************************************************************* * Writeback blocks config *************************************************************/ @@ -1400,6 +1559,14 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = { .clk_ctrl = DPU_CLK_CTRL_REG_DMA, }; +static const struct dpu_reg_dma_cfg sm8450_regdma = { + .base = 0x0, + .version = 0x00020000, + .trigger_sel_off = 0x119c, + .xin_id = 7, + .clk_ctrl = DPU_CLK_CTRL_REG_DMA, +}; + /************************************************************* * PERF data config *************************************************************/ @@ -1675,6 +1842,36 @@ static const struct dpu_perf_cfg sm8250_perf_data = { .bw_inefficiency_factor = 120, }; +static const struct dpu_perf_cfg sm8450_perf_data = { + .max_bw_low = 13600000, + .max_bw_high = 18200000, + .min_core_ib = 2500000, + .min_llcc_ib = 0, + .min_dram_ib = 800000, + .min_prefill_lines = 35, + /* FIXME: lut tables */ + .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, + .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(sc7180_qos_linear), + .entries = sc7180_qos_linear + }, + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), + .entries = sc7180_qos_macrotile + }, + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), + .entries = sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, +}; + static const struct dpu_perf_cfg sc7280_perf_data = { .max_bw_low = 4700000, .max_bw_high = 8800000, @@ -1879,6 +2076,32 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = { .mdss_irqs = IRQ_SM8250_MASK, }; +static const struct dpu_mdss_cfg sm8450_dpu_cfg = { + .caps = &sm8450_dpu_caps, + .mdp_count = ARRAY_SIZE(sm8450_mdp), + .mdp = sm8450_mdp, + .ctl_count = ARRAY_SIZE(sm8450_ctl), + .ctl = sm8450_ctl, + .sspp_count = ARRAY_SIZE(sm8450_sspp), + .sspp = sm8450_sspp, + .mixer_count = ARRAY_SIZE(sm8150_lm), + .mixer = sm8150_lm, + .dspp_count = ARRAY_SIZE(sm8150_dspp), + .dspp = sm8150_dspp, + .pingpong_count = ARRAY_SIZE(sm8450_pp), + .pingpong = sm8450_pp, + .merge_3d_count = ARRAY_SIZE(sm8450_merge_3d), + .merge_3d = sm8450_merge_3d, + .intf_count = ARRAY_SIZE(sm8450_intf), + .intf = sm8450_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .reg_dma_count = 1, + .dma_cfg = &sm8450_regdma, + .perf = &sm8450_perf_data, + .mdss_irqs = IRQ_SM8450_MASK, +}; + static const struct dpu_mdss_cfg sc7280_dpu_cfg = { .caps = &sc7280_dpu_caps, .mdp_count = ARRAY_SIZE(sc7280_mdp), @@ -1937,6 +2160,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg}, { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg}, { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg}, + { .hw_rev = DPU_HW_VER_810, .dpu_cfg = &sm8450_dpu_cfg}, }; const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 4730f8268f2a..4526ef71c326 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -46,6 +46,7 @@ #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */ #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ +#define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */ #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170) #define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h index d3b0ed0a9c6c..6d8e1bb3b3cc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -195,6 +195,8 @@ enum dpu_pingpong { PINGPONG_3, PINGPONG_4, PINGPONG_5, + PINGPONG_6, + PINGPONG_7, PINGPONG_S0, PINGPONG_MAX }; @@ -203,6 +205,7 @@ enum dpu_merge_3d { MERGE_3D_0 = 1, MERGE_3D_1, MERGE_3D_2, + MERGE_3D_3, MERGE_3D_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 95d8765c1c53..68d09a2d809d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1301,6 +1301,7 @@ static const struct of_device_id dpu_dt_match[] = { { .compatible = "qcom,sc8180x-dpu", }, { .compatible = "qcom,sm8150-dpu", }, { .compatible = "qcom,sm8250-dpu", }, + { .compatible = "qcom,sm8450-dpu", }, {} }; MODULE_DEVICE_TABLE(of, dpu_dt_match); -- 2.35.1 ^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 7/8] drm/msm/dpu: add support for SM8450 @ 2022-11-04 13:03 ` Dmitry Baryshkov 0 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-04 13:03 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, freedreno Add definitions for the display hardware used on Qualcomm SM8450 platform. Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 224 ++++++++++++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 229 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 1ce237e18506..3934d8976833 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -124,6 +124,15 @@ BIT(MDP_AD4_0_INTR) | \ BIT(MDP_AD4_1_INTR)) +#define IRQ_SM8450_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_7xxx_INTR) | \ + BIT(MDP_INTF1_7xxx_INTR) | \ + BIT(MDP_INTF2_7xxx_INTR) | \ + BIT(MDP_INTF3_7xxx_INTR) | \ + 0) + #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ BIT(DPU_WB_UBWC) | \ BIT(DPU_WB_YUV_CONFIG) | \ @@ -367,6 +376,20 @@ static const struct dpu_caps sm8250_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; +static const struct dpu_caps sm8450_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages = 0xb, + .qseed_type = DPU_SSPP_SCALER_QSEED4, + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ + .ubwc_version = DPU_HW_UBWC_VER_40, + .has_src_split = true, + .has_dim_layer = true, + .has_idle_pc = true, + .has_3d_merge = true, + .max_linewidth = 5120, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, +}; + static const struct dpu_caps sc7280_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x7, @@ -504,6 +527,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = { }, }; +static const struct dpu_mdp_cfg sm8450_mdp[] = { + { + .name = "top_0", .id = MDP_TOP, + .base = 0x0, .len = 0x494, + .features = BIT(DPU_MDP_PERIPH_0_REMOVED), + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { + .reg_off = 0x2AC, .bit_off = 0}, + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { + .reg_off = 0x2B4, .bit_off = 0}, + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { + .reg_off = 0x2BC, .bit_off = 0}, + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { + .reg_off = 0x2C4, .bit_off = 0}, + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { + .reg_off = 0x2AC, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { + .reg_off = 0x2B4, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { + .reg_off = 0x2BC, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { + .reg_off = 0x2C4, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { + .reg_off = 0x2BC, .bit_off = 20}, + }, +}; + static const struct dpu_mdp_cfg sc7280_mdp[] = { { .name = "top_0", .id = MDP_TOP, @@ -662,6 +712,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = { }, }; +static const struct dpu_ctl_cfg sm8450_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x15000, .len = 0x204, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, + { + .name = "ctl_1", .id = CTL_1, + .base = 0x16000, .len = 0x204, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, + { + .name = "ctl_2", .id = CTL_2, + .base = 0x17000, .len = 0x204, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, + { + .name = "ctl_3", .id = CTL_3, + .base = 0x18000, .len = 0x204, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, + { + .name = "ctl_4", .id = CTL_4, + .base = 0x19000, .len = 0x204, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, + { + .name = "ctl_5", .id = CTL_5, + .base = 0x1a000, .len = 0x204, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + static const struct dpu_ctl_cfg sc7280_ctl[] = { { .name = "ctl_0", .id = CTL_0, @@ -880,6 +969,34 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = { sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), }; +static const struct dpu_sspp_sub_blks sm8450_vig_sblk_0 = + _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE); +static const struct dpu_sspp_sub_blks sm8450_vig_sblk_1 = + _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE); +static const struct dpu_sspp_sub_blks sm8450_vig_sblk_2 = + _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE); +static const struct dpu_sspp_sub_blks sm8450_vig_sblk_3 = + _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE); + +static const struct dpu_sspp_cfg sm8450_sspp[] = { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, + sm8450_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK, + sm8450_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK, + sm8450_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK, + sm8450_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), +}; + static const struct dpu_sspp_cfg sc7280_sspp[] = { SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7280_MASK, sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), @@ -1191,6 +1308,34 @@ static struct dpu_pingpong_cfg qcm2290_pp[] = { DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), }; +/* FIXME: interrupts */ +static const struct dpu_pingpong_cfg sm8450_pp[] = { + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), + PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), + PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), + PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + -1), + PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + -1), + PP_BLK("pingpong_6", PINGPONG_6, 0x65800, MERGE_3D_3, sdm845_pp_sblk, + -1, + -1), + PP_BLK("pingpong_7", PINGPONG_7, 0x65c00, MERGE_3D_3, sdm845_pp_sblk, + -1, + -1), +}; + /************************************************************* * MERGE_3D sub blocks config *************************************************************/ @@ -1208,6 +1353,13 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), }; +static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), + MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00), +}; + /************************************************************* * DSC sub blocks config *************************************************************/ @@ -1287,6 +1439,13 @@ static const struct dpu_intf_cfg qcm2290_intf[] = { INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), }; +static const struct dpu_intf_cfg sm8450_intf[] = { + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29), + INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), +}; + /************************************************************* * Writeback blocks config *************************************************************/ @@ -1400,6 +1559,14 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = { .clk_ctrl = DPU_CLK_CTRL_REG_DMA, }; +static const struct dpu_reg_dma_cfg sm8450_regdma = { + .base = 0x0, + .version = 0x00020000, + .trigger_sel_off = 0x119c, + .xin_id = 7, + .clk_ctrl = DPU_CLK_CTRL_REG_DMA, +}; + /************************************************************* * PERF data config *************************************************************/ @@ -1675,6 +1842,36 @@ static const struct dpu_perf_cfg sm8250_perf_data = { .bw_inefficiency_factor = 120, }; +static const struct dpu_perf_cfg sm8450_perf_data = { + .max_bw_low = 13600000, + .max_bw_high = 18200000, + .min_core_ib = 2500000, + .min_llcc_ib = 0, + .min_dram_ib = 800000, + .min_prefill_lines = 35, + /* FIXME: lut tables */ + .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, + .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(sc7180_qos_linear), + .entries = sc7180_qos_linear + }, + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), + .entries = sc7180_qos_macrotile + }, + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), + .entries = sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, +}; + static const struct dpu_perf_cfg sc7280_perf_data = { .max_bw_low = 4700000, .max_bw_high = 8800000, @@ -1879,6 +2076,32 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = { .mdss_irqs = IRQ_SM8250_MASK, }; +static const struct dpu_mdss_cfg sm8450_dpu_cfg = { + .caps = &sm8450_dpu_caps, + .mdp_count = ARRAY_SIZE(sm8450_mdp), + .mdp = sm8450_mdp, + .ctl_count = ARRAY_SIZE(sm8450_ctl), + .ctl = sm8450_ctl, + .sspp_count = ARRAY_SIZE(sm8450_sspp), + .sspp = sm8450_sspp, + .mixer_count = ARRAY_SIZE(sm8150_lm), + .mixer = sm8150_lm, + .dspp_count = ARRAY_SIZE(sm8150_dspp), + .dspp = sm8150_dspp, + .pingpong_count = ARRAY_SIZE(sm8450_pp), + .pingpong = sm8450_pp, + .merge_3d_count = ARRAY_SIZE(sm8450_merge_3d), + .merge_3d = sm8450_merge_3d, + .intf_count = ARRAY_SIZE(sm8450_intf), + .intf = sm8450_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .reg_dma_count = 1, + .dma_cfg = &sm8450_regdma, + .perf = &sm8450_perf_data, + .mdss_irqs = IRQ_SM8450_MASK, +}; + static const struct dpu_mdss_cfg sc7280_dpu_cfg = { .caps = &sc7280_dpu_caps, .mdp_count = ARRAY_SIZE(sc7280_mdp), @@ -1937,6 +2160,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg}, { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg}, { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg}, + { .hw_rev = DPU_HW_VER_810, .dpu_cfg = &sm8450_dpu_cfg}, }; const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 4730f8268f2a..4526ef71c326 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -46,6 +46,7 @@ #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */ #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ +#define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */ #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170) #define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h index d3b0ed0a9c6c..6d8e1bb3b3cc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -195,6 +195,8 @@ enum dpu_pingpong { PINGPONG_3, PINGPONG_4, PINGPONG_5, + PINGPONG_6, + PINGPONG_7, PINGPONG_S0, PINGPONG_MAX }; @@ -203,6 +205,7 @@ enum dpu_merge_3d { MERGE_3D_0 = 1, MERGE_3D_1, MERGE_3D_2, + MERGE_3D_3, MERGE_3D_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 95d8765c1c53..68d09a2d809d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1301,6 +1301,7 @@ static const struct of_device_id dpu_dt_match[] = { { .compatible = "qcom,sc8180x-dpu", }, { .compatible = "qcom,sm8150-dpu", }, { .compatible = "qcom,sm8250-dpu", }, + { .compatible = "qcom,sm8450-dpu", }, {} }; MODULE_DEVICE_TABLE(of, dpu_dt_match); -- 2.35.1 ^ permalink raw reply related [flat|nested] 62+ messages in thread
* Re: [PATCH v3 7/8] drm/msm/dpu: add support for SM8450 2022-11-04 13:03 ` Dmitry Baryshkov @ 2022-11-04 14:12 ` Konrad Dybcio -1 siblings, 0 replies; 62+ messages in thread From: Konrad Dybcio @ 2022-11-04 14:12 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul On 04/11/2022 14:03, Dmitry Baryshkov wrote: > Add definitions for the display hardware used on Qualcomm SM8450 > platform. > > Tested-by: Vinod Koul <vkoul@kernel.org> > Reviewed-by: Vinod Koul <vkoul@kernel.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Konrad > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 224 ++++++++++++++++++ > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 + > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + > 4 files changed, 229 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 1ce237e18506..3934d8976833 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -124,6 +124,15 @@ > BIT(MDP_AD4_0_INTR) | \ > BIT(MDP_AD4_1_INTR)) > > +#define IRQ_SM8450_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ > + BIT(MDP_SSPP_TOP0_INTR2) | \ > + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ > + BIT(MDP_INTF0_7xxx_INTR) | \ > + BIT(MDP_INTF1_7xxx_INTR) | \ > + BIT(MDP_INTF2_7xxx_INTR) | \ > + BIT(MDP_INTF3_7xxx_INTR) | \ > + 0) > + > #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ > BIT(DPU_WB_UBWC) | \ > BIT(DPU_WB_YUV_CONFIG) | \ > @@ -367,6 +376,20 @@ static const struct dpu_caps sm8250_dpu_caps = { > .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > }; > > +static const struct dpu_caps sm8450_dpu_caps = { > + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > + .max_mixer_blendstages = 0xb, > + .qseed_type = DPU_SSPP_SCALER_QSEED4, > + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ > + .ubwc_version = DPU_HW_UBWC_VER_40, > + .has_src_split = true, > + .has_dim_layer = true, > + .has_idle_pc = true, > + .has_3d_merge = true, > + .max_linewidth = 5120, > + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > +}; > + > static const struct dpu_caps sc7280_dpu_caps = { > .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > .max_mixer_blendstages = 0x7, > @@ -504,6 +527,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = { > }, > }; > > +static const struct dpu_mdp_cfg sm8450_mdp[] = { > + { > + .name = "top_0", .id = MDP_TOP, > + .base = 0x0, .len = 0x494, > + .features = BIT(DPU_MDP_PERIPH_0_REMOVED), > + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ I think it's about time we handle the two-memory-configs situation.. In my opinion, a dt property would be sane (just like downstream does it), as it's *really really really* unlikely that the same SKU would be shipped with 2 different memory gens. > + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { > + .reg_off = 0x2AC, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { > + .reg_off = 0x2B4, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { > + .reg_off = 0x2BC, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { > + .reg_off = 0x2C4, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { > + .reg_off = 0x2AC, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { > + .reg_off = 0x2B4, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { > + .reg_off = 0x2BC, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { > + .reg_off = 0x2C4, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { > + .reg_off = 0x2BC, .bit_off = 20}, > + }, > +}; > + > static const struct dpu_mdp_cfg sc7280_mdp[] = { > { > .name = "top_0", .id = MDP_TOP, > @@ -662,6 +712,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = { > }, > }; > > +static const struct dpu_ctl_cfg sm8450_ctl[] = { > + { > + .name = "ctl_0", .id = CTL_0, > + .base = 0x15000, .len = 0x204, > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), > + }, > + { > + .name = "ctl_1", .id = CTL_1, > + .base = 0x16000, .len = 0x204, > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), > + }, > + { > + .name = "ctl_2", .id = CTL_2, > + .base = 0x17000, .len = 0x204, > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), > + }, > + { > + .name = "ctl_3", .id = CTL_3, > + .base = 0x18000, .len = 0x204, > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), > + }, > + { > + .name = "ctl_4", .id = CTL_4, > + .base = 0x19000, .len = 0x204, > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), > + }, > + { > + .name = "ctl_5", .id = CTL_5, > + .base = 0x1a000, .len = 0x204, > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), > + }, > +}; > + > static const struct dpu_ctl_cfg sc7280_ctl[] = { > { > .name = "ctl_0", .id = CTL_0, > @@ -880,6 +969,34 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = { > sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > }; > > +static const struct dpu_sspp_sub_blks sm8450_vig_sblk_0 = > + _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE); > +static const struct dpu_sspp_sub_blks sm8450_vig_sblk_1 = > + _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE); > +static const struct dpu_sspp_sub_blks sm8450_vig_sblk_2 = > + _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE); > +static const struct dpu_sspp_sub_blks sm8450_vig_sblk_3 = > + _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE); > + > +static const struct dpu_sspp_cfg sm8450_sspp[] = { > + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, > + sm8450_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), > + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK, > + sm8450_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), > + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK, > + sm8450_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), > + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK, > + sm8450_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), > + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, > + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), > + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, > + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), > + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, > + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), > + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, > + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > +}; > + > static const struct dpu_sspp_cfg sc7280_sspp[] = { > SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7280_MASK, > sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), > @@ -1191,6 +1308,34 @@ static struct dpu_pingpong_cfg qcm2290_pp[] = { > DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), > }; > > +/* FIXME: interrupts */ > +static const struct dpu_pingpong_cfg sm8450_pp[] = { > + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), > + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), > + PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), > + PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), > + PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), > + -1), > + PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), > + -1), > + PP_BLK("pingpong_6", PINGPONG_6, 0x65800, MERGE_3D_3, sdm845_pp_sblk, > + -1, > + -1), > + PP_BLK("pingpong_7", PINGPONG_7, 0x65c00, MERGE_3D_3, sdm845_pp_sblk, > + -1, > + -1), > +}; > + > /************************************************************* > * MERGE_3D sub blocks config > *************************************************************/ > @@ -1208,6 +1353,13 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { > MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), > }; > > +static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { > + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), > + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), > + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), > + MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00), > +}; > + > /************************************************************* > * DSC sub blocks config > *************************************************************/ > @@ -1287,6 +1439,13 @@ static const struct dpu_intf_cfg qcm2290_intf[] = { > INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), > }; > > +static const struct dpu_intf_cfg sm8450_intf[] = { > + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), > + INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), > + INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29), > + INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), > +}; > + > /************************************************************* > * Writeback blocks config > *************************************************************/ > @@ -1400,6 +1559,14 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = { > .clk_ctrl = DPU_CLK_CTRL_REG_DMA, > }; > > +static const struct dpu_reg_dma_cfg sm8450_regdma = { > + .base = 0x0, > + .version = 0x00020000, > + .trigger_sel_off = 0x119c, > + .xin_id = 7, > + .clk_ctrl = DPU_CLK_CTRL_REG_DMA, > +}; > + > /************************************************************* > * PERF data config > *************************************************************/ > @@ -1675,6 +1842,36 @@ static const struct dpu_perf_cfg sm8250_perf_data = { > .bw_inefficiency_factor = 120, > }; > > +static const struct dpu_perf_cfg sm8450_perf_data = { > + .max_bw_low = 13600000, > + .max_bw_high = 18200000, > + .min_core_ib = 2500000, > + .min_llcc_ib = 0, > + .min_dram_ib = 800000, > + .min_prefill_lines = 35, > + /* FIXME: lut tables */ > + .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, > + .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, > + .qos_lut_tbl = { > + {.nentry = ARRAY_SIZE(sc7180_qos_linear), > + .entries = sc7180_qos_linear > + }, > + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), > + .entries = sc7180_qos_macrotile > + }, > + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), > + .entries = sc7180_qos_nrt > + }, > + /* TODO: macrotile-qseed is different from macrotile */ > + }, > + .cdp_cfg = { > + {.rd_enable = 1, .wr_enable = 1}, > + {.rd_enable = 1, .wr_enable = 0} > + }, > + .clk_inefficiency_factor = 105, > + .bw_inefficiency_factor = 120, > +}; > + > static const struct dpu_perf_cfg sc7280_perf_data = { > .max_bw_low = 4700000, > .max_bw_high = 8800000, > @@ -1879,6 +2076,32 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = { > .mdss_irqs = IRQ_SM8250_MASK, > }; > > +static const struct dpu_mdss_cfg sm8450_dpu_cfg = { > + .caps = &sm8450_dpu_caps, > + .mdp_count = ARRAY_SIZE(sm8450_mdp), > + .mdp = sm8450_mdp, > + .ctl_count = ARRAY_SIZE(sm8450_ctl), > + .ctl = sm8450_ctl, > + .sspp_count = ARRAY_SIZE(sm8450_sspp), > + .sspp = sm8450_sspp, > + .mixer_count = ARRAY_SIZE(sm8150_lm), > + .mixer = sm8150_lm, > + .dspp_count = ARRAY_SIZE(sm8150_dspp), > + .dspp = sm8150_dspp, > + .pingpong_count = ARRAY_SIZE(sm8450_pp), > + .pingpong = sm8450_pp, > + .merge_3d_count = ARRAY_SIZE(sm8450_merge_3d), > + .merge_3d = sm8450_merge_3d, > + .intf_count = ARRAY_SIZE(sm8450_intf), > + .intf = sm8450_intf, > + .vbif_count = ARRAY_SIZE(sdm845_vbif), > + .vbif = sdm845_vbif, > + .reg_dma_count = 1, > + .dma_cfg = &sm8450_regdma, > + .perf = &sm8450_perf_data, > + .mdss_irqs = IRQ_SM8450_MASK, > +}; > + > static const struct dpu_mdss_cfg sc7280_dpu_cfg = { > .caps = &sc7280_dpu_caps, > .mdp_count = ARRAY_SIZE(sc7280_mdp), > @@ -1937,6 +2160,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { > { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg}, > { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg}, > { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg}, > + { .hw_rev = DPU_HW_VER_810, .dpu_cfg = &sm8450_dpu_cfg}, > }; > > const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev) > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 4730f8268f2a..4526ef71c326 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -46,6 +46,7 @@ > #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ > #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */ > #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ > +#define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */ > > #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170) > #define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300) > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h > index d3b0ed0a9c6c..6d8e1bb3b3cc 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h > @@ -195,6 +195,8 @@ enum dpu_pingpong { > PINGPONG_3, > PINGPONG_4, > PINGPONG_5, > + PINGPONG_6, > + PINGPONG_7, > PINGPONG_S0, > PINGPONG_MAX > }; > @@ -203,6 +205,7 @@ enum dpu_merge_3d { > MERGE_3D_0 = 1, > MERGE_3D_1, > MERGE_3D_2, > + MERGE_3D_3, > MERGE_3D_MAX > }; > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > index 95d8765c1c53..68d09a2d809d 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > @@ -1301,6 +1301,7 @@ static const struct of_device_id dpu_dt_match[] = { > { .compatible = "qcom,sc8180x-dpu", }, > { .compatible = "qcom,sm8150-dpu", }, > { .compatible = "qcom,sm8250-dpu", }, > + { .compatible = "qcom,sm8450-dpu", }, > {} > }; > MODULE_DEVICE_TABLE(of, dpu_dt_match); ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 7/8] drm/msm/dpu: add support for SM8450 @ 2022-11-04 14:12 ` Konrad Dybcio 0 siblings, 0 replies; 62+ messages in thread From: Konrad Dybcio @ 2022-11-04 14:12 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, freedreno On 04/11/2022 14:03, Dmitry Baryshkov wrote: > Add definitions for the display hardware used on Qualcomm SM8450 > platform. > > Tested-by: Vinod Koul <vkoul@kernel.org> > Reviewed-by: Vinod Koul <vkoul@kernel.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Konrad > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 224 ++++++++++++++++++ > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 + > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + > 4 files changed, 229 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 1ce237e18506..3934d8976833 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -124,6 +124,15 @@ > BIT(MDP_AD4_0_INTR) | \ > BIT(MDP_AD4_1_INTR)) > > +#define IRQ_SM8450_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ > + BIT(MDP_SSPP_TOP0_INTR2) | \ > + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ > + BIT(MDP_INTF0_7xxx_INTR) | \ > + BIT(MDP_INTF1_7xxx_INTR) | \ > + BIT(MDP_INTF2_7xxx_INTR) | \ > + BIT(MDP_INTF3_7xxx_INTR) | \ > + 0) > + > #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ > BIT(DPU_WB_UBWC) | \ > BIT(DPU_WB_YUV_CONFIG) | \ > @@ -367,6 +376,20 @@ static const struct dpu_caps sm8250_dpu_caps = { > .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > }; > > +static const struct dpu_caps sm8450_dpu_caps = { > + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > + .max_mixer_blendstages = 0xb, > + .qseed_type = DPU_SSPP_SCALER_QSEED4, > + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ > + .ubwc_version = DPU_HW_UBWC_VER_40, > + .has_src_split = true, > + .has_dim_layer = true, > + .has_idle_pc = true, > + .has_3d_merge = true, > + .max_linewidth = 5120, > + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > +}; > + > static const struct dpu_caps sc7280_dpu_caps = { > .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > .max_mixer_blendstages = 0x7, > @@ -504,6 +527,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = { > }, > }; > > +static const struct dpu_mdp_cfg sm8450_mdp[] = { > + { > + .name = "top_0", .id = MDP_TOP, > + .base = 0x0, .len = 0x494, > + .features = BIT(DPU_MDP_PERIPH_0_REMOVED), > + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ I think it's about time we handle the two-memory-configs situation.. In my opinion, a dt property would be sane (just like downstream does it), as it's *really really really* unlikely that the same SKU would be shipped with 2 different memory gens. > + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { > + .reg_off = 0x2AC, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { > + .reg_off = 0x2B4, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { > + .reg_off = 0x2BC, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { > + .reg_off = 0x2C4, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { > + .reg_off = 0x2AC, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { > + .reg_off = 0x2B4, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { > + .reg_off = 0x2BC, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { > + .reg_off = 0x2C4, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { > + .reg_off = 0x2BC, .bit_off = 20}, > + }, > +}; > + > static const struct dpu_mdp_cfg sc7280_mdp[] = { > { > .name = "top_0", .id = MDP_TOP, > @@ -662,6 +712,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = { > }, > }; > > +static const struct dpu_ctl_cfg sm8450_ctl[] = { > + { > + .name = "ctl_0", .id = CTL_0, > + .base = 0x15000, .len = 0x204, > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), > + }, > + { > + .name = "ctl_1", .id = CTL_1, > + .base = 0x16000, .len = 0x204, > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), > + }, > + { > + .name = "ctl_2", .id = CTL_2, > + .base = 0x17000, .len = 0x204, > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), > + }, > + { > + .name = "ctl_3", .id = CTL_3, > + .base = 0x18000, .len = 0x204, > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), > + }, > + { > + .name = "ctl_4", .id = CTL_4, > + .base = 0x19000, .len = 0x204, > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), > + }, > + { > + .name = "ctl_5", .id = CTL_5, > + .base = 0x1a000, .len = 0x204, > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), > + }, > +}; > + > static const struct dpu_ctl_cfg sc7280_ctl[] = { > { > .name = "ctl_0", .id = CTL_0, > @@ -880,6 +969,34 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = { > sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > }; > > +static const struct dpu_sspp_sub_blks sm8450_vig_sblk_0 = > + _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE); > +static const struct dpu_sspp_sub_blks sm8450_vig_sblk_1 = > + _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE); > +static const struct dpu_sspp_sub_blks sm8450_vig_sblk_2 = > + _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE); > +static const struct dpu_sspp_sub_blks sm8450_vig_sblk_3 = > + _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE); > + > +static const struct dpu_sspp_cfg sm8450_sspp[] = { > + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, > + sm8450_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), > + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK, > + sm8450_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), > + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK, > + sm8450_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), > + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK, > + sm8450_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), > + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, > + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), > + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, > + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), > + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, > + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), > + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, > + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > +}; > + > static const struct dpu_sspp_cfg sc7280_sspp[] = { > SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7280_MASK, > sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), > @@ -1191,6 +1308,34 @@ static struct dpu_pingpong_cfg qcm2290_pp[] = { > DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), > }; > > +/* FIXME: interrupts */ > +static const struct dpu_pingpong_cfg sm8450_pp[] = { > + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), > + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), > + PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), > + PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), > + PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), > + -1), > + PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), > + -1), > + PP_BLK("pingpong_6", PINGPONG_6, 0x65800, MERGE_3D_3, sdm845_pp_sblk, > + -1, > + -1), > + PP_BLK("pingpong_7", PINGPONG_7, 0x65c00, MERGE_3D_3, sdm845_pp_sblk, > + -1, > + -1), > +}; > + > /************************************************************* > * MERGE_3D sub blocks config > *************************************************************/ > @@ -1208,6 +1353,13 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { > MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), > }; > > +static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { > + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), > + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), > + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), > + MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00), > +}; > + > /************************************************************* > * DSC sub blocks config > *************************************************************/ > @@ -1287,6 +1439,13 @@ static const struct dpu_intf_cfg qcm2290_intf[] = { > INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), > }; > > +static const struct dpu_intf_cfg sm8450_intf[] = { > + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), > + INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), > + INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29), > + INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), > +}; > + > /************************************************************* > * Writeback blocks config > *************************************************************/ > @@ -1400,6 +1559,14 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = { > .clk_ctrl = DPU_CLK_CTRL_REG_DMA, > }; > > +static const struct dpu_reg_dma_cfg sm8450_regdma = { > + .base = 0x0, > + .version = 0x00020000, > + .trigger_sel_off = 0x119c, > + .xin_id = 7, > + .clk_ctrl = DPU_CLK_CTRL_REG_DMA, > +}; > + > /************************************************************* > * PERF data config > *************************************************************/ > @@ -1675,6 +1842,36 @@ static const struct dpu_perf_cfg sm8250_perf_data = { > .bw_inefficiency_factor = 120, > }; > > +static const struct dpu_perf_cfg sm8450_perf_data = { > + .max_bw_low = 13600000, > + .max_bw_high = 18200000, > + .min_core_ib = 2500000, > + .min_llcc_ib = 0, > + .min_dram_ib = 800000, > + .min_prefill_lines = 35, > + /* FIXME: lut tables */ > + .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, > + .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, > + .qos_lut_tbl = { > + {.nentry = ARRAY_SIZE(sc7180_qos_linear), > + .entries = sc7180_qos_linear > + }, > + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), > + .entries = sc7180_qos_macrotile > + }, > + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), > + .entries = sc7180_qos_nrt > + }, > + /* TODO: macrotile-qseed is different from macrotile */ > + }, > + .cdp_cfg = { > + {.rd_enable = 1, .wr_enable = 1}, > + {.rd_enable = 1, .wr_enable = 0} > + }, > + .clk_inefficiency_factor = 105, > + .bw_inefficiency_factor = 120, > +}; > + > static const struct dpu_perf_cfg sc7280_perf_data = { > .max_bw_low = 4700000, > .max_bw_high = 8800000, > @@ -1879,6 +2076,32 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = { > .mdss_irqs = IRQ_SM8250_MASK, > }; > > +static const struct dpu_mdss_cfg sm8450_dpu_cfg = { > + .caps = &sm8450_dpu_caps, > + .mdp_count = ARRAY_SIZE(sm8450_mdp), > + .mdp = sm8450_mdp, > + .ctl_count = ARRAY_SIZE(sm8450_ctl), > + .ctl = sm8450_ctl, > + .sspp_count = ARRAY_SIZE(sm8450_sspp), > + .sspp = sm8450_sspp, > + .mixer_count = ARRAY_SIZE(sm8150_lm), > + .mixer = sm8150_lm, > + .dspp_count = ARRAY_SIZE(sm8150_dspp), > + .dspp = sm8150_dspp, > + .pingpong_count = ARRAY_SIZE(sm8450_pp), > + .pingpong = sm8450_pp, > + .merge_3d_count = ARRAY_SIZE(sm8450_merge_3d), > + .merge_3d = sm8450_merge_3d, > + .intf_count = ARRAY_SIZE(sm8450_intf), > + .intf = sm8450_intf, > + .vbif_count = ARRAY_SIZE(sdm845_vbif), > + .vbif = sdm845_vbif, > + .reg_dma_count = 1, > + .dma_cfg = &sm8450_regdma, > + .perf = &sm8450_perf_data, > + .mdss_irqs = IRQ_SM8450_MASK, > +}; > + > static const struct dpu_mdss_cfg sc7280_dpu_cfg = { > .caps = &sc7280_dpu_caps, > .mdp_count = ARRAY_SIZE(sc7280_mdp), > @@ -1937,6 +2160,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { > { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg}, > { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg}, > { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg}, > + { .hw_rev = DPU_HW_VER_810, .dpu_cfg = &sm8450_dpu_cfg}, > }; > > const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev) > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 4730f8268f2a..4526ef71c326 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -46,6 +46,7 @@ > #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ > #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */ > #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ > +#define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */ > > #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170) > #define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300) > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h > index d3b0ed0a9c6c..6d8e1bb3b3cc 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h > @@ -195,6 +195,8 @@ enum dpu_pingpong { > PINGPONG_3, > PINGPONG_4, > PINGPONG_5, > + PINGPONG_6, > + PINGPONG_7, > PINGPONG_S0, > PINGPONG_MAX > }; > @@ -203,6 +205,7 @@ enum dpu_merge_3d { > MERGE_3D_0 = 1, > MERGE_3D_1, > MERGE_3D_2, > + MERGE_3D_3, > MERGE_3D_MAX > }; > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > index 95d8765c1c53..68d09a2d809d 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > @@ -1301,6 +1301,7 @@ static const struct of_device_id dpu_dt_match[] = { > { .compatible = "qcom,sc8180x-dpu", }, > { .compatible = "qcom,sm8150-dpu", }, > { .compatible = "qcom,sm8250-dpu", }, > + { .compatible = "qcom,sm8450-dpu", }, > {} > }; > MODULE_DEVICE_TABLE(of, dpu_dt_match); ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 7/8] drm/msm/dpu: add support for SM8450 2022-11-04 14:12 ` Konrad Dybcio @ 2022-11-10 20:28 ` Dmitry Baryshkov -1 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-10 20:28 UTC (permalink / raw) To: Konrad Dybcio, Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul On 04/11/2022 17:12, Konrad Dybcio wrote: > > On 04/11/2022 14:03, Dmitry Baryshkov wrote: >> Add definitions for the display hardware used on Qualcomm SM8450 >> platform. >> >> Tested-by: Vinod Koul <vkoul@kernel.org> >> Reviewed-by: Vinod Koul <vkoul@kernel.org> >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> --- > > Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> > > > Konrad > >> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 224 ++++++++++++++++++ >> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 + >> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + >> 4 files changed, 229 insertions(+) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> index 1ce237e18506..3934d8976833 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> @@ -124,6 +124,15 @@ >> BIT(MDP_AD4_0_INTR) | \ >> BIT(MDP_AD4_1_INTR)) >> +#define IRQ_SM8450_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ >> + BIT(MDP_SSPP_TOP0_INTR2) | \ >> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ >> + BIT(MDP_INTF0_7xxx_INTR) | \ >> + BIT(MDP_INTF1_7xxx_INTR) | \ >> + BIT(MDP_INTF2_7xxx_INTR) | \ >> + BIT(MDP_INTF3_7xxx_INTR) | \ >> + 0) >> + >> #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ >> BIT(DPU_WB_UBWC) | \ >> BIT(DPU_WB_YUV_CONFIG) | \ >> @@ -367,6 +376,20 @@ static const struct dpu_caps sm8250_dpu_caps = { >> .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, >> }; >> +static const struct dpu_caps sm8450_dpu_caps = { >> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, >> + .max_mixer_blendstages = 0xb, >> + .qseed_type = DPU_SSPP_SCALER_QSEED4, >> + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ >> + .ubwc_version = DPU_HW_UBWC_VER_40, >> + .has_src_split = true, >> + .has_dim_layer = true, >> + .has_idle_pc = true, >> + .has_3d_merge = true, >> + .max_linewidth = 5120, >> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, >> +}; >> + >> static const struct dpu_caps sc7280_dpu_caps = { >> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, >> .max_mixer_blendstages = 0x7, >> @@ -504,6 +527,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = { >> }, >> }; >> +static const struct dpu_mdp_cfg sm8450_mdp[] = { >> + { >> + .name = "top_0", .id = MDP_TOP, >> + .base = 0x0, .len = 0x494, >> + .features = BIT(DPU_MDP_PERIPH_0_REMOVED), >> + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ > > I think it's about time we handle the two-memory-configs situation.. > > In my opinion, a dt property would be sane (just like downstream does > it), as it's > > *really really really* unlikely that the same SKU would be shipped with > 2 different memory gens. As it's really unlikely, I think we can drop the TODO comment completely until we phase a device with different memory type. WDYT? -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 7/8] drm/msm/dpu: add support for SM8450 @ 2022-11-10 20:28 ` Dmitry Baryshkov 0 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-10 20:28 UTC (permalink / raw) To: Konrad Dybcio, Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, freedreno On 04/11/2022 17:12, Konrad Dybcio wrote: > > On 04/11/2022 14:03, Dmitry Baryshkov wrote: >> Add definitions for the display hardware used on Qualcomm SM8450 >> platform. >> >> Tested-by: Vinod Koul <vkoul@kernel.org> >> Reviewed-by: Vinod Koul <vkoul@kernel.org> >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> --- > > Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> > > > Konrad > >> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 224 ++++++++++++++++++ >> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 + >> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + >> 4 files changed, 229 insertions(+) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> index 1ce237e18506..3934d8976833 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> @@ -124,6 +124,15 @@ >> BIT(MDP_AD4_0_INTR) | \ >> BIT(MDP_AD4_1_INTR)) >> +#define IRQ_SM8450_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ >> + BIT(MDP_SSPP_TOP0_INTR2) | \ >> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ >> + BIT(MDP_INTF0_7xxx_INTR) | \ >> + BIT(MDP_INTF1_7xxx_INTR) | \ >> + BIT(MDP_INTF2_7xxx_INTR) | \ >> + BIT(MDP_INTF3_7xxx_INTR) | \ >> + 0) >> + >> #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ >> BIT(DPU_WB_UBWC) | \ >> BIT(DPU_WB_YUV_CONFIG) | \ >> @@ -367,6 +376,20 @@ static const struct dpu_caps sm8250_dpu_caps = { >> .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, >> }; >> +static const struct dpu_caps sm8450_dpu_caps = { >> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, >> + .max_mixer_blendstages = 0xb, >> + .qseed_type = DPU_SSPP_SCALER_QSEED4, >> + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ >> + .ubwc_version = DPU_HW_UBWC_VER_40, >> + .has_src_split = true, >> + .has_dim_layer = true, >> + .has_idle_pc = true, >> + .has_3d_merge = true, >> + .max_linewidth = 5120, >> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, >> +}; >> + >> static const struct dpu_caps sc7280_dpu_caps = { >> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, >> .max_mixer_blendstages = 0x7, >> @@ -504,6 +527,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = { >> }, >> }; >> +static const struct dpu_mdp_cfg sm8450_mdp[] = { >> + { >> + .name = "top_0", .id = MDP_TOP, >> + .base = 0x0, .len = 0x494, >> + .features = BIT(DPU_MDP_PERIPH_0_REMOVED), >> + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ > > I think it's about time we handle the two-memory-configs situation.. > > In my opinion, a dt property would be sane (just like downstream does > it), as it's > > *really really really* unlikely that the same SKU would be shipped with > 2 different memory gens. As it's really unlikely, I think we can drop the TODO comment completely until we phase a device with different memory type. WDYT? -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 7/8] drm/msm/dpu: add support for SM8450 2022-11-10 20:28 ` Dmitry Baryshkov @ 2022-11-10 20:59 ` Konrad Dybcio -1 siblings, 0 replies; 62+ messages in thread From: Konrad Dybcio @ 2022-11-10 20:59 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul On 10/11/2022 21:28, Dmitry Baryshkov wrote: > On 04/11/2022 17:12, Konrad Dybcio wrote: >> >> On 04/11/2022 14:03, Dmitry Baryshkov wrote: >>> Add definitions for the display hardware used on Qualcomm SM8450 >>> platform. >>> >>> Tested-by: Vinod Koul <vkoul@kernel.org> >>> Reviewed-by: Vinod Koul <vkoul@kernel.org> >>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>> --- >> >> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> >> >> >> Konrad >> >>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 224 ++++++++++++++++++ >>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 + >>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + >>> 4 files changed, 229 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >>> index 1ce237e18506..3934d8976833 100644 >>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >>> @@ -124,6 +124,15 @@ >>> BIT(MDP_AD4_0_INTR) | \ >>> BIT(MDP_AD4_1_INTR)) >>> +#define IRQ_SM8450_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ >>> + BIT(MDP_SSPP_TOP0_INTR2) | \ >>> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ >>> + BIT(MDP_INTF0_7xxx_INTR) | \ >>> + BIT(MDP_INTF1_7xxx_INTR) | \ >>> + BIT(MDP_INTF2_7xxx_INTR) | \ >>> + BIT(MDP_INTF3_7xxx_INTR) | \ >>> + 0) >>> + >>> #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ >>> BIT(DPU_WB_UBWC) | \ >>> BIT(DPU_WB_YUV_CONFIG) | \ >>> @@ -367,6 +376,20 @@ static const struct dpu_caps sm8250_dpu_caps = { >>> .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, >>> }; >>> +static const struct dpu_caps sm8450_dpu_caps = { >>> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, >>> + .max_mixer_blendstages = 0xb, >>> + .qseed_type = DPU_SSPP_SCALER_QSEED4, >>> + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ >>> + .ubwc_version = DPU_HW_UBWC_VER_40, >>> + .has_src_split = true, >>> + .has_dim_layer = true, >>> + .has_idle_pc = true, >>> + .has_3d_merge = true, >>> + .max_linewidth = 5120, >>> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, >>> +}; >>> + >>> static const struct dpu_caps sc7280_dpu_caps = { >>> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, >>> .max_mixer_blendstages = 0x7, >>> @@ -504,6 +527,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = { >>> }, >>> }; >>> +static const struct dpu_mdp_cfg sm8450_mdp[] = { >>> + { >>> + .name = "top_0", .id = MDP_TOP, >>> + .base = 0x0, .len = 0x494, >>> + .features = BIT(DPU_MDP_PERIPH_0_REMOVED), >>> + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ >> >> I think it's about time we handle the two-memory-configs situation.. >> >> In my opinion, a dt property would be sane (just like downstream does >> it), as it's >> >> *really really really* unlikely that the same SKU would be shipped >> with 2 different memory gens. > > As it's really unlikely, I think we can drop the TODO comment completely > until we phase a device with different memory type. WDYT? It's really unlikely that the same device model (for example Xperia 1 III) is shipped in 2 memory configurations that would have to be discerned dynamically somehow. It is however very likely that, for example Xiaomi releases a 888 phone with LPDDR4X and Sony releases one with LPDDR5. So it's a per-device thing, not exactly per-SoC. Konrad > ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 7/8] drm/msm/dpu: add support for SM8450 @ 2022-11-10 20:59 ` Konrad Dybcio 0 siblings, 0 replies; 62+ messages in thread From: Konrad Dybcio @ 2022-11-10 20:59 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, freedreno On 10/11/2022 21:28, Dmitry Baryshkov wrote: > On 04/11/2022 17:12, Konrad Dybcio wrote: >> >> On 04/11/2022 14:03, Dmitry Baryshkov wrote: >>> Add definitions for the display hardware used on Qualcomm SM8450 >>> platform. >>> >>> Tested-by: Vinod Koul <vkoul@kernel.org> >>> Reviewed-by: Vinod Koul <vkoul@kernel.org> >>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >>> --- >> >> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> >> >> >> Konrad >> >>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 224 ++++++++++++++++++ >>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 + >>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + >>> 4 files changed, 229 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >>> index 1ce237e18506..3934d8976833 100644 >>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >>> @@ -124,6 +124,15 @@ >>> BIT(MDP_AD4_0_INTR) | \ >>> BIT(MDP_AD4_1_INTR)) >>> +#define IRQ_SM8450_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ >>> + BIT(MDP_SSPP_TOP0_INTR2) | \ >>> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ >>> + BIT(MDP_INTF0_7xxx_INTR) | \ >>> + BIT(MDP_INTF1_7xxx_INTR) | \ >>> + BIT(MDP_INTF2_7xxx_INTR) | \ >>> + BIT(MDP_INTF3_7xxx_INTR) | \ >>> + 0) >>> + >>> #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ >>> BIT(DPU_WB_UBWC) | \ >>> BIT(DPU_WB_YUV_CONFIG) | \ >>> @@ -367,6 +376,20 @@ static const struct dpu_caps sm8250_dpu_caps = { >>> .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, >>> }; >>> +static const struct dpu_caps sm8450_dpu_caps = { >>> + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, >>> + .max_mixer_blendstages = 0xb, >>> + .qseed_type = DPU_SSPP_SCALER_QSEED4, >>> + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ >>> + .ubwc_version = DPU_HW_UBWC_VER_40, >>> + .has_src_split = true, >>> + .has_dim_layer = true, >>> + .has_idle_pc = true, >>> + .has_3d_merge = true, >>> + .max_linewidth = 5120, >>> + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, >>> +}; >>> + >>> static const struct dpu_caps sc7280_dpu_caps = { >>> .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, >>> .max_mixer_blendstages = 0x7, >>> @@ -504,6 +527,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = { >>> }, >>> }; >>> +static const struct dpu_mdp_cfg sm8450_mdp[] = { >>> + { >>> + .name = "top_0", .id = MDP_TOP, >>> + .base = 0x0, .len = 0x494, >>> + .features = BIT(DPU_MDP_PERIPH_0_REMOVED), >>> + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ >> >> I think it's about time we handle the two-memory-configs situation.. >> >> In my opinion, a dt property would be sane (just like downstream does >> it), as it's >> >> *really really really* unlikely that the same SKU would be shipped >> with 2 different memory gens. > > As it's really unlikely, I think we can drop the TODO comment completely > until we phase a device with different memory type. WDYT? It's really unlikely that the same device model (for example Xperia 1 III) is shipped in 2 memory configurations that would have to be discerned dynamically somehow. It is however very likely that, for example Xiaomi releases a 888 phone with LPDDR4X and Sony releases one with LPDDR5. So it's a per-device thing, not exactly per-SoC. Konrad > ^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v3 8/8] drm/msm: mdss: add support for SM8450 2022-11-04 13:03 ` Dmitry Baryshkov @ 2022-11-04 13:03 ` Dmitry Baryshkov -1 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-04 13:03 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul Add support for the MDSS block on SM8450 platform. Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/msm_mdss.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 6a4549ef34d4..5602fbaf6e0e 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -283,6 +283,10 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) case DPU_HW_VER_720: msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1); break; + case DPU_HW_VER_810: + /* TODO: highest_bank_bit = 2 for LP_DDR4 */ + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1); + break; } return ret; @@ -511,6 +515,7 @@ static const struct of_device_id mdss_dt_match[] = { { .compatible = "qcom,sc8180x-mdss" }, { .compatible = "qcom,sm8150-mdss" }, { .compatible = "qcom,sm8250-mdss" }, + { .compatible = "qcom,sm8450-mdss" }, {} }; MODULE_DEVICE_TABLE(of, mdss_dt_match); -- 2.35.1 ^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 8/8] drm/msm: mdss: add support for SM8450 @ 2022-11-04 13:03 ` Dmitry Baryshkov 0 siblings, 0 replies; 62+ messages in thread From: Dmitry Baryshkov @ 2022-11-04 13:03 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, freedreno Add support for the MDSS block on SM8450 platform. Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/msm_mdss.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 6a4549ef34d4..5602fbaf6e0e 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -283,6 +283,10 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) case DPU_HW_VER_720: msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1); break; + case DPU_HW_VER_810: + /* TODO: highest_bank_bit = 2 for LP_DDR4 */ + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1); + break; } return ret; @@ -511,6 +515,7 @@ static const struct of_device_id mdss_dt_match[] = { { .compatible = "qcom,sc8180x-mdss" }, { .compatible = "qcom,sm8150-mdss" }, { .compatible = "qcom,sm8250-mdss" }, + { .compatible = "qcom,sm8450-mdss" }, {} }; MODULE_DEVICE_TABLE(of, mdss_dt_match); -- 2.35.1 ^ permalink raw reply related [flat|nested] 62+ messages in thread
* Re: [PATCH v3 8/8] drm/msm: mdss: add support for SM8450 2022-11-04 13:03 ` Dmitry Baryshkov @ 2022-11-04 14:12 ` Konrad Dybcio -1 siblings, 0 replies; 62+ messages in thread From: Konrad Dybcio @ 2022-11-04 14:12 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul On 04/11/2022 14:03, Dmitry Baryshkov wrote: > Add support for the MDSS block on SM8450 platform. > > Tested-by: Vinod Koul <vkoul@kernel.org> > Reviewed-by: Vinod Koul <vkoul@kernel.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Konrad > drivers/gpu/drm/msm/msm_mdss.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c > index 6a4549ef34d4..5602fbaf6e0e 100644 > --- a/drivers/gpu/drm/msm/msm_mdss.c > +++ b/drivers/gpu/drm/msm/msm_mdss.c > @@ -283,6 +283,10 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) > case DPU_HW_VER_720: > msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1); > break; > + case DPU_HW_VER_810: > + /* TODO: highest_bank_bit = 2 for LP_DDR4 */ > + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1); > + break; > } > > return ret; > @@ -511,6 +515,7 @@ static const struct of_device_id mdss_dt_match[] = { > { .compatible = "qcom,sc8180x-mdss" }, > { .compatible = "qcom,sm8150-mdss" }, > { .compatible = "qcom,sm8250-mdss" }, > + { .compatible = "qcom,sm8450-mdss" }, > {} > }; > MODULE_DEVICE_TABLE(of, mdss_dt_match); ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 8/8] drm/msm: mdss: add support for SM8450 @ 2022-11-04 14:12 ` Konrad Dybcio 0 siblings, 0 replies; 62+ messages in thread From: Konrad Dybcio @ 2022-11-04 14:12 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Rob Clark, Sean Paul, Abhinav Kumar, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, freedreno On 04/11/2022 14:03, Dmitry Baryshkov wrote: > Add support for the MDSS block on SM8450 platform. > > Tested-by: Vinod Koul <vkoul@kernel.org> > Reviewed-by: Vinod Koul <vkoul@kernel.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Konrad > drivers/gpu/drm/msm/msm_mdss.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c > index 6a4549ef34d4..5602fbaf6e0e 100644 > --- a/drivers/gpu/drm/msm/msm_mdss.c > +++ b/drivers/gpu/drm/msm/msm_mdss.c > @@ -283,6 +283,10 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) > case DPU_HW_VER_720: > msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1); > break; > + case DPU_HW_VER_810: > + /* TODO: highest_bank_bit = 2 for LP_DDR4 */ > + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1); > + break; > } > > return ret; > @@ -511,6 +515,7 @@ static const struct of_device_id mdss_dt_match[] = { > { .compatible = "qcom,sc8180x-mdss" }, > { .compatible = "qcom,sm8150-mdss" }, > { .compatible = "qcom,sm8250-mdss" }, > + { .compatible = "qcom,sm8450-mdss" }, > {} > }; > MODULE_DEVICE_TABLE(of, mdss_dt_match); ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 8/8] drm/msm: mdss: add support for SM8450 2022-11-04 13:03 ` Dmitry Baryshkov @ 2022-11-16 7:53 ` Abhinav Kumar -1 siblings, 0 replies; 62+ messages in thread From: Abhinav Kumar @ 2022-11-16 7:53 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Rob Herring, Krzysztof Kozlowski Cc: Stephen Boyd, David Airlie, Daniel Vetter, linux-arm-msm, devicetree, dri-devel, freedreno, Vinod Koul On 11/4/2022 6:03 AM, Dmitry Baryshkov wrote: > Add support for the MDSS block on SM8450 platform. > > Tested-by: Vinod Koul <vkoul@kernel.org> > Reviewed-by: Vinod Koul <vkoul@kernel.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > --- > drivers/gpu/drm/msm/msm_mdss.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c > index 6a4549ef34d4..5602fbaf6e0e 100644 > --- a/drivers/gpu/drm/msm/msm_mdss.c > +++ b/drivers/gpu/drm/msm/msm_mdss.c > @@ -283,6 +283,10 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) > case DPU_HW_VER_720: > msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1); > break; > + case DPU_HW_VER_810: > + /* TODO: highest_bank_bit = 2 for LP_DDR4 */ > + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1); > + break; > } > > return ret; > @@ -511,6 +515,7 @@ static const struct of_device_id mdss_dt_match[] = { > { .compatible = "qcom,sc8180x-mdss" }, > { .compatible = "qcom,sm8150-mdss" }, > { .compatible = "qcom,sm8250-mdss" }, > + { .compatible = "qcom,sm8450-mdss" }, > {} > }; > MODULE_DEVICE_TABLE(of, mdss_dt_match); ^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 8/8] drm/msm: mdss: add support for SM8450 @ 2022-11-16 7:53 ` Abhinav Kumar 0 siblings, 0 replies; 62+ messages in thread From: Abhinav Kumar @ 2022-11-16 7:53 UTC (permalink / raw) To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Clark, Sean Paul, Rob Herring, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, dri-devel, Stephen Boyd, Vinod Koul, freedreno On 11/4/2022 6:03 AM, Dmitry Baryshkov wrote: > Add support for the MDSS block on SM8450 platform. > > Tested-by: Vinod Koul <vkoul@kernel.org> > Reviewed-by: Vinod Koul <vkoul@kernel.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > --- > drivers/gpu/drm/msm/msm_mdss.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c > index 6a4549ef34d4..5602fbaf6e0e 100644 > --- a/drivers/gpu/drm/msm/msm_mdss.c > +++ b/drivers/gpu/drm/msm/msm_mdss.c > @@ -283,6 +283,10 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) > case DPU_HW_VER_720: > msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1); > break; > + case DPU_HW_VER_810: > + /* TODO: highest_bank_bit = 2 for LP_DDR4 */ > + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1); > + break; > } > > return ret; > @@ -511,6 +515,7 @@ static const struct of_device_id mdss_dt_match[] = { > { .compatible = "qcom,sc8180x-mdss" }, > { .compatible = "qcom,sm8150-mdss" }, > { .compatible = "qcom,sm8250-mdss" }, > + { .compatible = "qcom,sm8450-mdss" }, > {} > }; > MODULE_DEVICE_TABLE(of, mdss_dt_match); ^ permalink raw reply [flat|nested] 62+ messages in thread
end of thread, other threads:[~2022-11-16 9:59 UTC | newest] Thread overview: 62+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-11-04 13:03 [PATCH v3 0/8] drm/msm: add support for SM8450 Dmitry Baryshkov 2022-11-04 13:03 ` Dmitry Baryshkov 2022-11-04 13:03 ` [PATCH v3 1/8] dt-bindings: display/msm/dsi-controller-main: allow defining opp-table Dmitry Baryshkov 2022-11-04 13:03 ` Dmitry Baryshkov 2022-11-04 13:03 ` [PATCH v3 2/8] dt-bindings: display/msm: add sm8350 and sm8450 DSI PHYs Dmitry Baryshkov 2022-11-04 13:03 ` Dmitry Baryshkov 2022-11-04 13:03 ` [PATCH v3 3/8] dt-bindings: display/msm: add support for the display on SM8450 Dmitry Baryshkov 2022-11-04 13:03 ` Dmitry Baryshkov 2022-11-04 17:54 ` Rob Herring 2022-11-04 17:54 ` Rob Herring 2022-11-08 11:02 ` Krzysztof Kozlowski 2022-11-08 11:02 ` Krzysztof Kozlowski 2022-11-04 13:03 ` [PATCH v3 4/8] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450 Dmitry Baryshkov 2022-11-04 13:03 ` Dmitry Baryshkov 2022-11-04 13:54 ` Konrad Dybcio 2022-11-04 13:54 ` Konrad Dybcio 2022-11-10 22:16 ` Dmitry Baryshkov 2022-11-10 22:16 ` Dmitry Baryshkov 2022-11-14 16:13 ` Konrad Dybcio 2022-11-14 16:13 ` Konrad Dybcio 2022-11-04 13:03 ` [PATCH v3 5/8] drm/msm/dsi: add support for DSI 2.6.0 Dmitry Baryshkov 2022-11-04 13:03 ` Dmitry Baryshkov 2022-11-04 13:55 ` Konrad Dybcio 2022-11-04 13:55 ` Konrad Dybcio 2022-11-16 7:35 ` Abhinav Kumar 2022-11-16 7:35 ` Abhinav Kumar 2022-11-04 13:03 ` [PATCH v3 6/8] drm/msm/dpu: add support for MDP_TOP blackhole Dmitry Baryshkov 2022-11-04 13:03 ` Dmitry Baryshkov 2022-11-04 13:58 ` Konrad Dybcio 2022-11-04 13:58 ` Konrad Dybcio 2022-11-10 20:19 ` Dmitry Baryshkov 2022-11-10 20:19 ` Dmitry Baryshkov 2022-11-10 20:21 ` Konrad Dybcio 2022-11-10 20:21 ` Konrad Dybcio 2022-11-16 7:50 ` Abhinav Kumar 2022-11-16 7:50 ` Abhinav Kumar 2022-11-16 8:19 ` Dmitry Baryshkov 2022-11-16 8:19 ` Dmitry Baryshkov 2022-11-16 8:30 ` Abhinav Kumar 2022-11-16 8:30 ` Abhinav Kumar 2022-11-16 9:18 ` Dmitry Baryshkov 2022-11-16 9:18 ` Dmitry Baryshkov 2022-11-16 9:29 ` Abhinav Kumar 2022-11-16 9:29 ` Abhinav Kumar 2022-11-16 9:43 ` Dmitry Baryshkov 2022-11-16 9:43 ` Dmitry Baryshkov 2022-11-16 9:59 ` Abhinav Kumar 2022-11-16 9:59 ` Abhinav Kumar 2022-11-04 13:03 ` [PATCH v3 7/8] drm/msm/dpu: add support for SM8450 Dmitry Baryshkov 2022-11-04 13:03 ` Dmitry Baryshkov 2022-11-04 14:12 ` Konrad Dybcio 2022-11-04 14:12 ` Konrad Dybcio 2022-11-10 20:28 ` Dmitry Baryshkov 2022-11-10 20:28 ` Dmitry Baryshkov 2022-11-10 20:59 ` Konrad Dybcio 2022-11-10 20:59 ` Konrad Dybcio 2022-11-04 13:03 ` [PATCH v3 8/8] drm/msm: mdss: " Dmitry Baryshkov 2022-11-04 13:03 ` Dmitry Baryshkov 2022-11-04 14:12 ` Konrad Dybcio 2022-11-04 14:12 ` Konrad Dybcio 2022-11-16 7:53 ` Abhinav Kumar 2022-11-16 7:53 ` Abhinav Kumar
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.