* [PATCH 01/22] ppc/ppc4xx: Introduce a DCR device model
2022-08-13 15:34 [PATCH 00/22] QOMify PPC4xx devices and minor clean ups BALATON Zoltan
@ 2022-08-13 15:34 ` BALATON Zoltan
2022-08-16 7:32 ` Cédric Le Goater
2022-08-13 15:34 ` [PATCH 02/22] ppc/ppc405: QOM'ify CPC BALATON Zoltan
` (21 subsequent siblings)
22 siblings, 1 reply; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-13 15:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
From: Cédric Le Goater <clg@kaod.org>
The Device Control Registers (DCR) of on-SoC devices are accessed by
software through the use of the mtdcr and mfdcr instructions. These
are converted in transactions on a side band bus, the DCR bus, which
connects the on-SoC devices to the CPU.
Ideally, we should model these accesses with a DCR namespace and DCR
memory regions but today the DCR handlers are installed in a DCR table
under the CPU. Instead, introduce a little device model wrapper to hold
a CPU link and handle registration of DCR handlers.
The DCR device inherits from SysBus because most of these devices also
have MMIO regions and/or IRQs. Being a SysBusDevice makes things easier
to install the device model in the overall SoC.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc4xx_devs.c | 41 +++++++++++++++++++++++++++++++++++++++++
include/hw/ppc/ppc4xx.h | 17 +++++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 069b511951..f4d7ae9567 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -664,3 +664,44 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
mal, &dcr_read_mal, &dcr_write_mal);
}
}
+
+/* PPC4xx_DCR_DEVICE */
+
+void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
+ dcr_read_cb dcr_read, dcr_write_cb dcr_write)
+{
+ assert(dev->cpu);
+ ppc_dcr_register(&dev->cpu->env, dcrn, opaque, dcr_read, dcr_write);
+}
+
+bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
+ Error **errp)
+{
+ object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
+ return sysbus_realize(SYS_BUS_DEVICE(dev), errp);
+}
+
+static Property ppc4xx_dcr_properties[] = {
+ DEFINE_PROP_LINK("cpu", Ppc4xxDcrDeviceState, cpu, TYPE_POWERPC_CPU,
+ PowerPCCPU *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ device_class_set_props(dc, ppc4xx_dcr_properties);
+}
+
+static const TypeInfo ppc4xx_types[] = {
+ {
+ .name = TYPE_PPC4xx_DCR_DEVICE,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Ppc4xxDcrDeviceState),
+ .class_init = ppc4xx_dcr_class_init,
+ .abstract = true,
+ }
+};
+
+DEFINE_TYPES(ppc4xx_types)
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 591e2421a3..a537a5567b 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -27,6 +27,7 @@
#include "hw/ppc/ppc.h"
#include "exec/memory.h"
+#include "hw/sysbus.h"
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
MemoryRegion ram_memories[],
@@ -44,4 +45,20 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
+/*
+ * Generic DCR device
+ */
+#define TYPE_PPC4xx_DCR_DEVICE "ppc4xx-dcr-device"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxDcrDeviceState, PPC4xx_DCR_DEVICE);
+struct Ppc4xxDcrDeviceState {
+ SysBusDevice parent_obj;
+
+ PowerPCCPU *cpu;
+};
+
+void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
+ dcr_read_cb dcr_read, dcr_write_cb dcr_write);
+bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
+ Error **errp);
+
#endif /* PPC4XX_H */
--
2.30.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH 01/22] ppc/ppc4xx: Introduce a DCR device model
2022-08-13 15:34 ` [PATCH 01/22] ppc/ppc4xx: Introduce a DCR device model BALATON Zoltan
@ 2022-08-16 7:32 ` Cédric Le Goater
2022-08-16 9:33 ` BALATON Zoltan
0 siblings, 1 reply; 37+ messages in thread
From: Cédric Le Goater @ 2022-08-16 7:32 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc
Cc: Daniel Henrique Barboza, Peter Maydell
On 8/13/22 17:34, BALATON Zoltan wrote:
> From: Cédric Le Goater <clg@kaod.org>
>
> The Device Control Registers (DCR) of on-SoC devices are accessed by
> software through the use of the mtdcr and mfdcr instructions. These
> are converted in transactions on a side band bus, the DCR bus, which
> connects the on-SoC devices to the CPU.
>
> Ideally, we should model these accesses with a DCR namespace and DCR
> memory regions but today the DCR handlers are installed in a DCR table
> under the CPU. Instead, introduce a little device model wrapper to hold
> a CPU link and handle registration of DCR handlers.
>
> The DCR device inherits from SysBus because most of these devices also
> have MMIO regions and/or IRQs. Being a SysBusDevice makes things easier
> to install the device model in the overall SoC.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
When re-sending a patch, it is a good practice to list the changes before
the Sob of the person doing the resend.
I think you only changed the ppc4xx_dcr_register prototype. Correct ?
Thanks,
C.
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> hw/ppc/ppc4xx_devs.c | 41 +++++++++++++++++++++++++++++++++++++++++
> include/hw/ppc/ppc4xx.h | 17 +++++++++++++++++
> 2 files changed, 58 insertions(+)
>
> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
> index 069b511951..f4d7ae9567 100644
> --- a/hw/ppc/ppc4xx_devs.c
> +++ b/hw/ppc/ppc4xx_devs.c
> @@ -664,3 +664,44 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
> mal, &dcr_read_mal, &dcr_write_mal);
> }
> }
> +
> +/* PPC4xx_DCR_DEVICE */
> +
> +void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
> + dcr_read_cb dcr_read, dcr_write_cb dcr_write)
> +{
> + assert(dev->cpu);
> + ppc_dcr_register(&dev->cpu->env, dcrn, opaque, dcr_read, dcr_write);
> +}
> +
> +bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
> + Error **errp)
> +{
> + object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
> + return sysbus_realize(SYS_BUS_DEVICE(dev), errp);
> +}
> +
> +static Property ppc4xx_dcr_properties[] = {
> + DEFINE_PROP_LINK("cpu", Ppc4xxDcrDeviceState, cpu, TYPE_POWERPC_CPU,
> + PowerPCCPU *),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + device_class_set_props(dc, ppc4xx_dcr_properties);
> +}
> +
> +static const TypeInfo ppc4xx_types[] = {
> + {
> + .name = TYPE_PPC4xx_DCR_DEVICE,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(Ppc4xxDcrDeviceState),
> + .class_init = ppc4xx_dcr_class_init,
> + .abstract = true,
> + }
> +};
> +
> +DEFINE_TYPES(ppc4xx_types)
> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
> index 591e2421a3..a537a5567b 100644
> --- a/include/hw/ppc/ppc4xx.h
> +++ b/include/hw/ppc/ppc4xx.h
> @@ -27,6 +27,7 @@
>
> #include "hw/ppc/ppc.h"
> #include "exec/memory.h"
> +#include "hw/sysbus.h"
>
> void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
> MemoryRegion ram_memories[],
> @@ -44,4 +45,20 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
>
> #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
>
> +/*
> + * Generic DCR device
> + */
> +#define TYPE_PPC4xx_DCR_DEVICE "ppc4xx-dcr-device"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxDcrDeviceState, PPC4xx_DCR_DEVICE);
> +struct Ppc4xxDcrDeviceState {
> + SysBusDevice parent_obj;
> +
> + PowerPCCPU *cpu;
> +};
> +
> +void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
> + dcr_read_cb dcr_read, dcr_write_cb dcr_write);
> +bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
> + Error **errp);
> +
> #endif /* PPC4XX_H */
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 01/22] ppc/ppc4xx: Introduce a DCR device model
2022-08-16 7:32 ` Cédric Le Goater
@ 2022-08-16 9:33 ` BALATON Zoltan
2022-08-16 11:13 ` Cédric Le Goater
0 siblings, 1 reply; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-16 9:33 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 4657 bytes --]
On Tue, 16 Aug 2022, Cédric Le Goater wrote:
> On 8/13/22 17:34, BALATON Zoltan wrote:
>> From: Cédric Le Goater <clg@kaod.org>
>>
>> The Device Control Registers (DCR) of on-SoC devices are accessed by
>> software through the use of the mtdcr and mfdcr instructions. These
>> are converted in transactions on a side band bus, the DCR bus, which
>> connects the on-SoC devices to the CPU.
>>
>> Ideally, we should model these accesses with a DCR namespace and DCR
>> memory regions but today the DCR handlers are installed in a DCR table
>> under the CPU. Instead, introduce a little device model wrapper to hold
>> a CPU link and handle registration of DCR handlers.
>>
>> The DCR device inherits from SysBus because most of these devices also
>> have MMIO regions and/or IRQs. Being a SysBusDevice makes things easier
>> to install the device model in the overall SoC.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>
> When re-sending a patch, it is a good practice to list the changes before
> the Sob of the person doing the resend.
>
> I think you only changed the ppc4xx_dcr_register prototype. Correct ?
Mostly, and the resulting rebase but maybe some small changes here and
there but I think those are also just code style fixes. I did not know
what you prefer with the from line so if you're OK with keeping it I can
go through it again and mark changes before signed-off if you think that's
better.
I've also started cleaning up the sdram model, I need a bit more time for
that, I'll probably send it as a separate series.
> Thanks,
>
> C.
>
>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>> ---
>> hw/ppc/ppc4xx_devs.c | 41 +++++++++++++++++++++++++++++++++++++++++
>> include/hw/ppc/ppc4xx.h | 17 +++++++++++++++++
>> 2 files changed, 58 insertions(+)
>>
>> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
>> index 069b511951..f4d7ae9567 100644
>> --- a/hw/ppc/ppc4xx_devs.c
>> +++ b/hw/ppc/ppc4xx_devs.c
>> @@ -664,3 +664,44 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum,
>> uint8_t rxcnum,
>> mal, &dcr_read_mal, &dcr_write_mal);
>> }
>> }
>> +
>> +/* PPC4xx_DCR_DEVICE */
>> +
>> +void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void
>> *opaque,
>> + dcr_read_cb dcr_read, dcr_write_cb dcr_write)
>> +{
>> + assert(dev->cpu);
>> + ppc_dcr_register(&dev->cpu->env, dcrn, opaque, dcr_read, dcr_write);
>> +}
>> +
>> +bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
>> + Error **errp)
>> +{
>> + object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu),
>> &error_abort);
>> + return sysbus_realize(SYS_BUS_DEVICE(dev), errp);
>> +}
>> +
>> +static Property ppc4xx_dcr_properties[] = {
>> + DEFINE_PROP_LINK("cpu", Ppc4xxDcrDeviceState, cpu, TYPE_POWERPC_CPU,
>> + PowerPCCPU *),
>> + DEFINE_PROP_END_OF_LIST(),
>> +};
>> +
>> +static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(oc);
>> +
>> + device_class_set_props(dc, ppc4xx_dcr_properties);
>> +}
>> +
>> +static const TypeInfo ppc4xx_types[] = {
>> + {
>> + .name = TYPE_PPC4xx_DCR_DEVICE,
>> + .parent = TYPE_SYS_BUS_DEVICE,
>> + .instance_size = sizeof(Ppc4xxDcrDeviceState),
>> + .class_init = ppc4xx_dcr_class_init,
>> + .abstract = true,
>> + }
>> +};
>> +
>> +DEFINE_TYPES(ppc4xx_types)
>> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
>> index 591e2421a3..a537a5567b 100644
>> --- a/include/hw/ppc/ppc4xx.h
>> +++ b/include/hw/ppc/ppc4xx.h
>> @@ -27,6 +27,7 @@
>> #include "hw/ppc/ppc.h"
>> #include "exec/memory.h"
>> +#include "hw/sysbus.h"
>> void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
>> MemoryRegion ram_memories[],
>> @@ -44,4 +45,20 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum,
>> uint8_t rxcnum,
>> #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
>> +/*
>> + * Generic DCR device
>> + */
>> +#define TYPE_PPC4xx_DCR_DEVICE "ppc4xx-dcr-device"
>> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxDcrDeviceState, PPC4xx_DCR_DEVICE);
>> +struct Ppc4xxDcrDeviceState {
>> + SysBusDevice parent_obj;
>> +
>> + PowerPCCPU *cpu;
>> +};
>> +
>> +void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void
>> *opaque,
>> + dcr_read_cb dcr_read, dcr_write_cb dcr_write);
>> +bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
>> + Error **errp);
>> +
>> #endif /* PPC4XX_H */
>
>
>
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 01/22] ppc/ppc4xx: Introduce a DCR device model
2022-08-16 9:33 ` BALATON Zoltan
@ 2022-08-16 11:13 ` Cédric Le Goater
0 siblings, 0 replies; 37+ messages in thread
From: Cédric Le Goater @ 2022-08-16 11:13 UTC (permalink / raw)
To: BALATON Zoltan
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, Peter Maydell
On 8/16/22 11:33, BALATON Zoltan wrote:
> On Tue, 16 Aug 2022, Cédric Le Goater wrote:
>> On 8/13/22 17:34, BALATON Zoltan wrote:
>>> From: Cédric Le Goater <clg@kaod.org>
>>>
>>> The Device Control Registers (DCR) of on-SoC devices are accessed by
>>> software through the use of the mtdcr and mfdcr instructions. These
>>> are converted in transactions on a side band bus, the DCR bus, which
>>> connects the on-SoC devices to the CPU.
>>>
>>> Ideally, we should model these accesses with a DCR namespace and DCR
>>> memory regions but today the DCR handlers are installed in a DCR table
>>> under the CPU. Instead, introduce a little device model wrapper to hold
>>> a CPU link and handle registration of DCR handlers.
>>>
>>> The DCR device inherits from SysBus because most of these devices also
>>> have MMIO regions and/or IRQs. Being a SysBusDevice makes things easier
>>> to install the device model in the overall SoC.
>>>
>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>>
>> When re-sending a patch, it is a good practice to list the changes before
>> the Sob of the person doing the resend.
>>
>> I think you only changed the ppc4xx_dcr_register prototype. Correct ?
>
> Mostly, and the resulting rebase but maybe some small changes here and there but I think those are also just code style fixes. I did not know what you prefer with the from line
See commit 6a54ac2a9737 for next time.
> so if you're OK with keeping it I can go through it again and mark changes before signed-off if you think that's better.
Don't bother. I did a quick scan and didn't notice anything important.
> I've also started cleaning up the sdram model, I need a bit more time for that, I'll probably send it as a separate series.
OK. My initial patches were good enough for 405 and bamboo. May be keep the same
basic idea.
Thanks,
C.
>> Thanks,
>>
>> C.
>>
>>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>>> ---
>>> hw/ppc/ppc4xx_devs.c | 41 +++++++++++++++++++++++++++++++++++++++++
>>> include/hw/ppc/ppc4xx.h | 17 +++++++++++++++++
>>> 2 files changed, 58 insertions(+)
>>>
>>> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
>>> index 069b511951..f4d7ae9567 100644
>>> --- a/hw/ppc/ppc4xx_devs.c
>>> +++ b/hw/ppc/ppc4xx_devs.c
>>> @@ -664,3 +664,44 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
>>> mal, &dcr_read_mal, &dcr_write_mal);
>>> }
>>> }
>>> +
>>> +/* PPC4xx_DCR_DEVICE */
>>> +
>>> +void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
>>> + dcr_read_cb dcr_read, dcr_write_cb dcr_write)
>>> +{
>>> + assert(dev->cpu);
>>> + ppc_dcr_register(&dev->cpu->env, dcrn, opaque, dcr_read, dcr_write);
>>> +}
>>> +
>>> +bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
>>> + Error **errp)
>>> +{
>>> + object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
>>> + return sysbus_realize(SYS_BUS_DEVICE(dev), errp);
>>> +}
>>> +
>>> +static Property ppc4xx_dcr_properties[] = {
>>> + DEFINE_PROP_LINK("cpu", Ppc4xxDcrDeviceState, cpu, TYPE_POWERPC_CPU,
>>> + PowerPCCPU *),
>>> + DEFINE_PROP_END_OF_LIST(),
>>> +};
>>> +
>>> +static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data)
>>> +{
>>> + DeviceClass *dc = DEVICE_CLASS(oc);
>>> +
>>> + device_class_set_props(dc, ppc4xx_dcr_properties);
>>> +}
>>> +
>>> +static const TypeInfo ppc4xx_types[] = {
>>> + {
>>> + .name = TYPE_PPC4xx_DCR_DEVICE,
>>> + .parent = TYPE_SYS_BUS_DEVICE,
>>> + .instance_size = sizeof(Ppc4xxDcrDeviceState),
>>> + .class_init = ppc4xx_dcr_class_init,
>>> + .abstract = true,
>>> + }
>>> +};
>>> +
>>> +DEFINE_TYPES(ppc4xx_types)
>>> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
>>> index 591e2421a3..a537a5567b 100644
>>> --- a/include/hw/ppc/ppc4xx.h
>>> +++ b/include/hw/ppc/ppc4xx.h
>>> @@ -27,6 +27,7 @@
>>> #include "hw/ppc/ppc.h"
>>> #include "exec/memory.h"
>>> +#include "hw/sysbus.h"
>>> void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
>>> MemoryRegion ram_memories[],
>>> @@ -44,4 +45,20 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
>>> #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
>>> +/*
>>> + * Generic DCR device
>>> + */
>>> +#define TYPE_PPC4xx_DCR_DEVICE "ppc4xx-dcr-device"
>>> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxDcrDeviceState, PPC4xx_DCR_DEVICE);
>>> +struct Ppc4xxDcrDeviceState {
>>> + SysBusDevice parent_obj;
>>> +
>>> + PowerPCCPU *cpu;
>>> +};
>>> +
>>> +void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
>>> + dcr_read_cb dcr_read, dcr_write_cb dcr_write);
>>> +bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
>>> + Error **errp);
>>> +
>>> #endif /* PPC4XX_H */
>>
>>
>>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 02/22] ppc/ppc405: QOM'ify CPC
2022-08-13 15:34 [PATCH 00/22] QOMify PPC4xx devices and minor clean ups BALATON Zoltan
2022-08-13 15:34 ` [PATCH 01/22] ppc/ppc4xx: Introduce a DCR device model BALATON Zoltan
@ 2022-08-13 15:34 ` BALATON Zoltan
2022-08-13 15:34 ` [PATCH 03/22] ppc/ppc405: QOM'ify GPT BALATON Zoltan
` (20 subsequent siblings)
22 siblings, 0 replies; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-13 15:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
From: Cédric Le Goater <clg@kaod.org>
The CPC controller is currently modeled as a DCR device.
Now that all clock settings are handled at the CPC level, change the
SoC "sys-clk" property to be an alias on the same property in the CPC
model.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc405.h | 35 ++++++++++-
hw/ppc/ppc405_uc.c | 141 ++++++++++++++++++++-------------------------
2 files changed, 95 insertions(+), 81 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 8cc76cc8b3..2ba829988d 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,39 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+#define TYPE_PPC405_CPC "ppc405-cpc"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC);
+
+enum {
+ PPC405EP_CPU_CLK = 0,
+ PPC405EP_PLB_CLK = 1,
+ PPC405EP_OPB_CLK = 2,
+ PPC405EP_EBC_CLK = 3,
+ PPC405EP_MAL_CLK = 4,
+ PPC405EP_PCI_CLK = 5,
+ PPC405EP_UART0_CLK = 6,
+ PPC405EP_UART1_CLK = 7,
+ PPC405EP_CLK_NB = 8,
+};
+
+struct Ppc405CpcState {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ uint32_t sysclk;
+ clk_setup_t clk_setup[PPC405EP_CLK_NB];
+ uint32_t boot;
+ uint32_t epctl;
+ uint32_t pllmr[2];
+ uint32_t ucr;
+ uint32_t srr;
+ uint32_t jtagid;
+ uint32_t pci;
+ /* Clock and power management */
+ uint32_t er;
+ uint32_t fr;
+ uint32_t sr;
+};
+
#define TYPE_PPC405_SOC "ppc405-soc"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC);
@@ -78,9 +111,9 @@ struct Ppc405SoCState {
MemoryRegion *dram_mr;
hwaddr ram_size;
- uint32_t sysclk;
PowerPCCPU cpu;
DeviceState *uic;
+ Ppc405CpcState cpc;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 14a525b2eb..ec83c292a5 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1178,36 +1178,7 @@ enum {
#endif
};
-enum {
- PPC405EP_CPU_CLK = 0,
- PPC405EP_PLB_CLK = 1,
- PPC405EP_OPB_CLK = 2,
- PPC405EP_EBC_CLK = 3,
- PPC405EP_MAL_CLK = 4,
- PPC405EP_PCI_CLK = 5,
- PPC405EP_UART0_CLK = 6,
- PPC405EP_UART1_CLK = 7,
- PPC405EP_CLK_NB = 8,
-};
-
-typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
-struct ppc405ep_cpc_t {
- uint32_t sysclk;
- clk_setup_t clk_setup[PPC405EP_CLK_NB];
- uint32_t boot;
- uint32_t epctl;
- uint32_t pllmr[2];
- uint32_t ucr;
- uint32_t srr;
- uint32_t jtagid;
- uint32_t pci;
- /* Clock and power management */
- uint32_t er;
- uint32_t fr;
- uint32_t sr;
-};
-
-static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
+static void ppc405ep_compute_clocks(Ppc405CpcState *cpc)
{
uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
uint32_t UART0_clk, UART1_clk;
@@ -1300,12 +1271,11 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
}
-static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
+static uint32_t dcr_read_epcpc(void *opaque, int dcrn)
{
- ppc405ep_cpc_t *cpc;
+ Ppc405CpcState *cpc = opaque;
uint32_t ret;
- cpc = opaque;
switch (dcrn) {
case PPC405EP_CPC0_BOOT:
ret = cpc->boot;
@@ -1340,11 +1310,10 @@ static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
return ret;
}
-static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
+static void dcr_write_epcpc(void *opaque, int dcrn, uint32_t val)
{
- ppc405ep_cpc_t *cpc;
+ Ppc405CpcState *cpc = opaque;
- cpc = opaque;
switch (dcrn) {
case PPC405EP_CPC0_BOOT:
/* Read-only register */
@@ -1377,9 +1346,9 @@ static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
}
}
-static void ppc405ep_cpc_reset (void *opaque)
+static void ppc405_cpc_reset(DeviceState *dev)
{
- ppc405ep_cpc_t *cpc = opaque;
+ Ppc405CpcState *cpc = PPC405_CPC(dev);
cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
cpc->epctl = 0x00000000;
@@ -1391,53 +1360,66 @@ static void ppc405ep_cpc_reset (void *opaque)
cpc->er = 0x00000000;
cpc->fr = 0x00000000;
cpc->sr = 0x00000000;
+ cpc->jtagid = 0x20267049;
ppc405ep_compute_clocks(cpc);
}
/* XXX: sysclk should be between 25 and 100 MHz */
-static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
- uint32_t sysclk)
+static void ppc405_cpc_realize(DeviceState *dev, Error **errp)
{
- ppc405ep_cpc_t *cpc;
+ Ppc405CpcState *cpc = PPC405_CPC(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
+
+ assert(dcr->cpu);
+ cpc->clk_setup[PPC405EP_CPU_CLK].cb =
+ ppc_40x_timers_init(&dcr->cpu->env, cpc->sysclk, PPC_INTERRUPT_PIT);
+ cpc->clk_setup[PPC405EP_CPU_CLK].opaque = &dcr->cpu->env;
+
+ ppc4xx_dcr_register(dcr, PPC405EP_CPC0_BOOT, cpc,
+ &dcr_read_epcpc, &dcr_write_epcpc);
+ ppc4xx_dcr_register(dcr, PPC405EP_CPC0_EPCTL, cpc,
+ &dcr_read_epcpc, &dcr_write_epcpc);
+ ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PLLMR0, cpc,
+ &dcr_read_epcpc, &dcr_write_epcpc);
+ ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PLLMR1, cpc,
+ &dcr_read_epcpc, &dcr_write_epcpc);
+ ppc4xx_dcr_register(dcr, PPC405EP_CPC0_UCR, cpc,
+ &dcr_read_epcpc, &dcr_write_epcpc);
+ ppc4xx_dcr_register(dcr, PPC405EP_CPC0_SRR, cpc,
+ &dcr_read_epcpc, &dcr_write_epcpc);
+ ppc4xx_dcr_register(dcr, PPC405EP_CPC0_JTAGID, cpc,
+ &dcr_read_epcpc, &dcr_write_epcpc);
+ ppc4xx_dcr_register(dcr, PPC405EP_CPC0_PCI, cpc,
+ &dcr_read_epcpc, &dcr_write_epcpc);
+}
- cpc = g_new0(ppc405ep_cpc_t, 1);
- memcpy(cpc->clk_setup, clk_setup,
- PPC405EP_CLK_NB * sizeof(clk_setup_t));
- cpc->jtagid = 0x20267049;
- cpc->sysclk = sysclk;
- qemu_register_reset(&ppc405ep_cpc_reset, cpc);
- ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
- ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
- ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
- ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
- ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
- ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
- ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
- ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
-#if 0
- ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
- ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
- ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
- &dcr_read_epcpc, &dcr_write_epcpc);
-#endif
+static Property ppc405_cpc_properties[] = {
+ DEFINE_PROP_UINT32("sys-clk", Ppc405CpcState, sysclk, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc405_cpc_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_cpc_realize;
+ dc->reset = ppc405_cpc_reset;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
+ device_class_set_props(dc, ppc405_cpc_properties);
}
+/* PPC405_SOC */
+
static void ppc405_soc_instance_init(Object *obj)
{
Ppc405SoCState *s = PPC405_SOC(obj);
object_initialize_child(obj, "cpu", &s->cpu,
POWERPC_CPU_TYPE_NAME("405ep"));
+
+ object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC);
+ object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
}
static void ppc405_reset(void *opaque)
@@ -1448,12 +1430,9 @@ static void ppc405_reset(void *opaque)
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
{
Ppc405SoCState *s = PPC405_SOC(dev);
- clk_setup_t clk_setup[PPC405EP_CLK_NB];
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
CPUPPCState *env;
- memset(clk_setup, 0, sizeof(clk_setup));
-
/* init CPUs */
if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
return;
@@ -1462,14 +1441,12 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
env = &s->cpu.env;
- clk_setup[PPC405EP_CPU_CLK].cb =
- ppc_40x_timers_init(env, s->sysclk, PPC_INTERRUPT_PIT);
- clk_setup[PPC405EP_CPU_CLK].opaque = env;
-
ppc_dcr_init(env, NULL, NULL);
/* CPU control */
- ppc405ep_cpc_init(env, clk_setup, s->sysclk);
+ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->cpc), &s->cpu, errp)) {
+ return;
+ }
/* PLB arbitrer */
ppc4xx_plb_init(env);
@@ -1561,7 +1538,6 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
static Property ppc405_soc_properties[] = {
DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
MemoryRegion *),
- DEFINE_PROP_UINT32("sys-clk", Ppc405SoCState, sysclk, 0),
DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0),
DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
DEFINE_PROP_END_OF_LIST(),
@@ -1579,6 +1555,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_CPC,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc405CpcState),
+ .class_init = ppc405_cpc_class_init,
+ }, {
.name = TYPE_PPC405_SOC,
.parent = TYPE_DEVICE,
.instance_size = sizeof(Ppc405SoCState),
--
2.30.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 03/22] ppc/ppc405: QOM'ify GPT
2022-08-13 15:34 [PATCH 00/22] QOMify PPC4xx devices and minor clean ups BALATON Zoltan
2022-08-13 15:34 ` [PATCH 01/22] ppc/ppc4xx: Introduce a DCR device model BALATON Zoltan
2022-08-13 15:34 ` [PATCH 02/22] ppc/ppc405: QOM'ify CPC BALATON Zoltan
@ 2022-08-13 15:34 ` BALATON Zoltan
2022-08-13 15:34 ` [PATCH 04/22] ppc/ppc405: QOM'ify OCM BALATON Zoltan
` (19 subsequent siblings)
22 siblings, 0 replies; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-13 15:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
From: Cédric Le Goater <clg@kaod.org>
The GPT controller is currently modeled as a SysBus device with a
unique memory region, a couple of IRQs and a timer.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc405.h | 22 ++++++++++
hw/ppc/ppc405_uc.c | 99 ++++++++++++++++++++++++---------------------
hw/ppc/trace-events | 1 -
3 files changed, 75 insertions(+), 47 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 2ba829988d..bcf55e4f6b 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,27 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* General purpose timers */
+#define TYPE_PPC405_GPT "ppc405-gpt"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT);
+struct Ppc405GptState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+
+ int64_t tb_offset;
+ uint32_t tb_freq;
+ QEMUTimer *timer;
+ qemu_irq irqs[5];
+ uint32_t oe;
+ uint32_t ol;
+ uint32_t im;
+ uint32_t is;
+ uint32_t ie;
+ uint32_t comp[5];
+ uint32_t mask[5];
+};
+
#define TYPE_PPC405_CPC "ppc405-cpc"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC);
@@ -114,6 +135,7 @@ struct Ppc405SoCState {
PowerPCCPU cpu;
DeviceState *uic;
Ppc405CpcState cpc;
+ Ppc405GptState gpt;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index ec83c292a5..bf95fabdc0 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -926,34 +926,18 @@ static void ppc405_ocm_init(CPUPPCState *env)
/*****************************************************************************/
/* General purpose timers */
-typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
-struct ppc4xx_gpt_t {
- MemoryRegion iomem;
- int64_t tb_offset;
- uint32_t tb_freq;
- QEMUTimer *timer;
- qemu_irq irqs[5];
- uint32_t oe;
- uint32_t ol;
- uint32_t im;
- uint32_t is;
- uint32_t ie;
- uint32_t comp[5];
- uint32_t mask[5];
-};
-
-static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
+static int ppc4xx_gpt_compare(Ppc405GptState *gpt, int n)
{
/* XXX: TODO */
return 0;
}
-static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
+static void ppc4xx_gpt_set_output(Ppc405GptState *gpt, int n, int level)
{
/* XXX: TODO */
}
-static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
+static void ppc4xx_gpt_set_outputs(Ppc405GptState *gpt)
{
uint32_t mask;
int i;
@@ -974,7 +958,7 @@ static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
}
}
-static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
+static void ppc4xx_gpt_set_irqs(Ppc405GptState *gpt)
{
uint32_t mask;
int i;
@@ -989,14 +973,14 @@ static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
}
}
-static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
+static void ppc4xx_gpt_compute_timer(Ppc405GptState *gpt)
{
/* XXX: TODO */
}
static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
{
- ppc4xx_gpt_t *gpt = opaque;
+ Ppc405GptState *gpt = opaque;
uint32_t ret;
int idx;
@@ -1050,7 +1034,7 @@ static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
- ppc4xx_gpt_t *gpt = opaque;
+ Ppc405GptState *gpt = opaque;
int idx;
trace_ppc4xx_gpt_write(addr, size, value);
@@ -1114,22 +1098,20 @@ static const MemoryRegionOps gpt_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void ppc4xx_gpt_cb (void *opaque)
+static void ppc4xx_gpt_cb(void *opaque)
{
- ppc4xx_gpt_t *gpt;
+ Ppc405GptState *gpt = opaque;
- gpt = opaque;
ppc4xx_gpt_set_irqs(gpt);
ppc4xx_gpt_set_outputs(gpt);
ppc4xx_gpt_compute_timer(gpt);
}
-static void ppc4xx_gpt_reset (void *opaque)
+static void ppc405_gpt_reset(DeviceState *dev)
{
- ppc4xx_gpt_t *gpt;
+ Ppc405GptState *gpt = PPC405_GPT(dev);
int i;
- gpt = opaque;
timer_del(gpt->timer);
gpt->oe = 0x00000000;
gpt->ol = 0x00000000;
@@ -1142,21 +1124,34 @@ static void ppc4xx_gpt_reset (void *opaque)
}
}
-static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
+static void ppc405_gpt_realize(DeviceState *dev, Error **errp)
{
- ppc4xx_gpt_t *gpt;
+ Ppc405GptState *s = PPC405_GPT(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
int i;
- trace_ppc4xx_gpt_init(base);
+ s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, s);
+ memory_region_init_io(&s->iomem, OBJECT(s), &gpt_ops, s, "gpt", 0xd4);
+ sysbus_init_mmio(sbd, &s->iomem);
- gpt = g_new0(ppc4xx_gpt_t, 1);
- for (i = 0; i < 5; i++) {
- gpt->irqs[i] = irqs[i];
+ for (i = 0; i < ARRAY_SIZE(s->irqs); i++) {
+ sysbus_init_irq(sbd, &s->irqs[i]);
}
- gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt);
- memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4);
- memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
- qemu_register_reset(ppc4xx_gpt_reset, gpt);
+}
+
+static void ppc405_gpt_finalize(Object *obj)
+{
+ timer_del(PPC405_GPT(obj)->timer);
+}
+
+static void ppc405_gpt_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_gpt_realize;
+ dc->reset = ppc405_gpt_reset;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
}
/*****************************************************************************/
@@ -1420,6 +1415,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC);
object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
+
+ object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT);
}
static void ppc405_reset(void *opaque)
@@ -1430,8 +1427,10 @@ static void ppc405_reset(void *opaque)
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
{
Ppc405SoCState *s = PPC405_SOC(dev);
- qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
+ qemu_irq dma_irqs[4], mal_irqs[4];
CPUPPCState *env;
+ SysBusDevice *sbd;
+ int i;
/* init CPUs */
if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) {
@@ -1517,12 +1516,14 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
ppc405_ocm_init(env);
/* GPT */
- gpt_irqs[0] = qdev_get_gpio_in(s->uic, 19);
- gpt_irqs[1] = qdev_get_gpio_in(s->uic, 20);
- gpt_irqs[2] = qdev_get_gpio_in(s->uic, 21);
- gpt_irqs[3] = qdev_get_gpio_in(s->uic, 22);
- gpt_irqs[4] = qdev_get_gpio_in(s->uic, 23);
- ppc4xx_gpt_init(0xef600000, gpt_irqs);
+ sbd = SYS_BUS_DEVICE(&s->gpt);
+ if (!sysbus_realize(sbd, errp)) {
+ return;
+ }
+ sysbus_mmio_map(sbd, 0, 0xef600000);
+ for (i = 0; i < ARRAY_SIZE(s->gpt.irqs); i++) {
+ sysbus_connect_irq(sbd, i, qdev_get_gpio_in(s->uic, 19 + i));
+ }
/* MAL */
mal_irqs[0] = qdev_get_gpio_in(s->uic, 11);
@@ -1555,6 +1556,12 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_GPT,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Ppc405GptState),
+ .instance_finalize = ppc405_gpt_finalize,
+ .class_init = ppc405_gpt_class_init,
+ }, {
.name = TYPE_PPC405_CPC,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc405CpcState),
diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events
index 5c0a215cad..adb4500888 100644
--- a/hw/ppc/trace-events
+++ b/hw/ppc/trace-events
@@ -162,7 +162,6 @@ ocm_unmap(const char* prefix, uint32_t isarc) "OCM unmap %s 0x%08" PRIx32
ppc4xx_gpt_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d"
ppc4xx_gpt_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" PRIx64 " size %d = 0x%" PRIx64
-ppc4xx_gpt_init(uint64_t addr) "offet 0x%" PRIx64
ppc405ep_clocks_compute(const char *param, uint32_t param2, uint32_t val) "%s 0x%1" PRIx32 " %d"
ppc405ep_clocks_setup(const char *trace) "%s"
--
2.30.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 04/22] ppc/ppc405: QOM'ify OCM
2022-08-13 15:34 [PATCH 00/22] QOMify PPC4xx devices and minor clean ups BALATON Zoltan
` (2 preceding siblings ...)
2022-08-13 15:34 ` [PATCH 03/22] ppc/ppc405: QOM'ify GPT BALATON Zoltan
@ 2022-08-13 15:34 ` BALATON Zoltan
2022-08-13 15:34 ` [PATCH 05/22] ppc/ppc405: QOM'ify GPIO BALATON Zoltan
` (18 subsequent siblings)
22 siblings, 0 replies; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-13 15:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
From: Cédric Le Goater <clg@kaod.org>
The OCM controller is currently modeled as a simple DCR device with
a couple of memory regions.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc405.h | 16 ++++++++++
hw/ppc/ppc405_uc.c | 77 +++++++++++++++++++++++-----------------------
2 files changed, 55 insertions(+), 38 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index bcf55e4f6b..a5b493d3e7 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,21 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* On Chip Memory */
+#define TYPE_PPC405_OCM "ppc405-ocm"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM);
+struct Ppc405OcmState {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ MemoryRegion ram;
+ MemoryRegion isarc_ram;
+ MemoryRegion dsarc_ram;
+ uint32_t isarc;
+ uint32_t isacntl;
+ uint32_t dsarc;
+ uint32_t dsacntl;
+};
+
/* General purpose timers */
#define TYPE_PPC405_GPT "ppc405-gpt"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT);
@@ -136,6 +151,7 @@ struct Ppc405SoCState {
DeviceState *uic;
Ppc405CpcState cpc;
Ppc405GptState gpt;
+ Ppc405OcmState ocm;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index bf95fabdc0..2282cfcd18 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -773,20 +773,9 @@ enum {
OCM0_DSACNTL = 0x01B,
};
-typedef struct ppc405_ocm_t ppc405_ocm_t;
-struct ppc405_ocm_t {
- MemoryRegion ram;
- MemoryRegion isarc_ram;
- MemoryRegion dsarc_ram;
- uint32_t isarc;
- uint32_t isacntl;
- uint32_t dsarc;
- uint32_t dsacntl;
-};
-
-static void ocm_update_mappings (ppc405_ocm_t *ocm,
- uint32_t isarc, uint32_t isacntl,
- uint32_t dsarc, uint32_t dsacntl)
+static void ocm_update_mappings(Ppc405OcmState *ocm,
+ uint32_t isarc, uint32_t isacntl,
+ uint32_t dsarc, uint32_t dsacntl)
{
trace_ocm_update_mappings(isarc, isacntl, dsarc, dsacntl, ocm->isarc,
ocm->isacntl, ocm->dsarc, ocm->dsacntl);
@@ -828,12 +817,11 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
}
}
-static uint32_t dcr_read_ocm (void *opaque, int dcrn)
+static uint32_t dcr_read_ocm(void *opaque, int dcrn)
{
- ppc405_ocm_t *ocm;
+ Ppc405OcmState *ocm = opaque;
uint32_t ret;
- ocm = opaque;
switch (dcrn) {
case OCM0_ISARC:
ret = ocm->isarc;
@@ -855,12 +843,11 @@ static uint32_t dcr_read_ocm (void *opaque, int dcrn)
return ret;
}
-static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
+static void dcr_write_ocm(void *opaque, int dcrn, uint32_t val)
{
- ppc405_ocm_t *ocm;
+ Ppc405OcmState *ocm = opaque;
uint32_t isarc, dsarc, isacntl, dsacntl;
- ocm = opaque;
isarc = ocm->isarc;
dsarc = ocm->dsarc;
isacntl = ocm->isacntl;
@@ -886,12 +873,11 @@ static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
ocm->dsacntl = dsacntl;
}
-static void ocm_reset (void *opaque)
+static void ppc405_ocm_reset(DeviceState *dev)
{
- ppc405_ocm_t *ocm;
+ Ppc405OcmState *ocm = PPC405_OCM(dev);
uint32_t isarc, dsarc, isacntl, dsacntl;
- ocm = opaque;
isarc = 0x00000000;
isacntl = 0x00000000;
dsarc = 0x00000000;
@@ -903,25 +889,31 @@ static void ocm_reset (void *opaque)
ocm->dsacntl = dsacntl;
}
-static void ppc405_ocm_init(CPUPPCState *env)
+static void ppc405_ocm_realize(DeviceState *dev, Error **errp)
{
- ppc405_ocm_t *ocm;
+ Ppc405OcmState *ocm = PPC405_OCM(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
- ocm = g_new0(ppc405_ocm_t, 1);
/* XXX: Size is 4096 or 0x04000000 */
- memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4 * KiB,
+ memory_region_init_ram(&ocm->isarc_ram, OBJECT(ocm), "ppc405.ocm", 4 * KiB,
&error_fatal);
- memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc",
+ memory_region_init_alias(&ocm->dsarc_ram, OBJECT(ocm), "ppc405.dsarc",
&ocm->isarc_ram, 0, 4 * KiB);
- qemu_register_reset(&ocm_reset, ocm);
- ppc_dcr_register(env, OCM0_ISARC,
- ocm, &dcr_read_ocm, &dcr_write_ocm);
- ppc_dcr_register(env, OCM0_ISACNTL,
- ocm, &dcr_read_ocm, &dcr_write_ocm);
- ppc_dcr_register(env, OCM0_DSARC,
- ocm, &dcr_read_ocm, &dcr_write_ocm);
- ppc_dcr_register(env, OCM0_DSACNTL,
- ocm, &dcr_read_ocm, &dcr_write_ocm);
+
+ ppc4xx_dcr_register(dcr, OCM0_ISARC, ocm, &dcr_read_ocm, &dcr_write_ocm);
+ ppc4xx_dcr_register(dcr, OCM0_ISACNTL, ocm, &dcr_read_ocm, &dcr_write_ocm);
+ ppc4xx_dcr_register(dcr, OCM0_DSARC, ocm, &dcr_read_ocm, &dcr_write_ocm);
+ ppc4xx_dcr_register(dcr, OCM0_DSACNTL, ocm, &dcr_read_ocm, &dcr_write_ocm);
+}
+
+static void ppc405_ocm_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_ocm_realize;
+ dc->reset = ppc405_ocm_reset;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
}
/*****************************************************************************/
@@ -1417,6 +1409,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT);
+
+ object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM);
}
static void ppc405_reset(void *opaque)
@@ -1513,7 +1507,9 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
}
/* OCM */
- ppc405_ocm_init(env);
+ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ocm), &s->cpu, errp)) {
+ return;
+ }
/* GPT */
sbd = SYS_BUS_DEVICE(&s->gpt);
@@ -1556,6 +1552,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_OCM,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc405OcmState),
+ .class_init = ppc405_ocm_class_init,
+ }, {
.name = TYPE_PPC405_GPT,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Ppc405GptState),
--
2.30.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 05/22] ppc/ppc405: QOM'ify GPIO
2022-08-13 15:34 [PATCH 00/22] QOMify PPC4xx devices and minor clean ups BALATON Zoltan
` (3 preceding siblings ...)
2022-08-13 15:34 ` [PATCH 04/22] ppc/ppc405: QOM'ify OCM BALATON Zoltan
@ 2022-08-13 15:34 ` BALATON Zoltan
2022-08-13 15:34 ` [PATCH 06/22] ppc/ppc405: QOM'ify DMA BALATON Zoltan
` (17 subsequent siblings)
22 siblings, 0 replies; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-13 15:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
From: Cédric Le Goater <clg@kaod.org>
The GPIO controller is currently modeled as a simple SysBus device
with a unique memory region.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc405.h | 21 +++++++++++++++++++
hw/ppc/ppc405_uc.c | 50 ++++++++++++++++++++++-----------------------
hw/ppc/trace-events | 1 -
3 files changed, 45 insertions(+), 27 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index a5b493d3e7..21f6cb3585 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,26 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* GPIO */
+#define TYPE_PPC405_GPIO "ppc405-gpio"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO);
+struct Ppc405GpioState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion io;
+ uint32_t or;
+ uint32_t tcr;
+ uint32_t osrh;
+ uint32_t osrl;
+ uint32_t tsrh;
+ uint32_t tsrl;
+ uint32_t odr;
+ uint32_t ir;
+ uint32_t rr1;
+ uint32_t isr1h;
+ uint32_t isr1l;
+};
+
/* On Chip Memory */
#define TYPE_PPC405_OCM "ppc405-ocm"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM);
@@ -152,6 +172,7 @@ struct Ppc405SoCState {
Ppc405CpcState cpc;
Ppc405GptState gpt;
Ppc405OcmState ocm;
+ Ppc405GpioState gpio;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 2282cfcd18..7ed3cf7149 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -714,22 +714,6 @@ static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
/*****************************************************************************/
/* GPIO */
-typedef struct ppc405_gpio_t ppc405_gpio_t;
-struct ppc405_gpio_t {
- MemoryRegion io;
- uint32_t or;
- uint32_t tcr;
- uint32_t osrh;
- uint32_t osrl;
- uint32_t tsrh;
- uint32_t tsrl;
- uint32_t odr;
- uint32_t ir;
- uint32_t rr1;
- uint32_t isr1h;
- uint32_t isr1l;
-};
-
static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size)
{
trace_ppc405_gpio_read(addr, size);
@@ -748,20 +732,22 @@ static const MemoryRegionOps ppc405_gpio_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void ppc405_gpio_reset (void *opaque)
+static void ppc405_gpio_realize(DeviceState *dev, Error **errp)
{
+ Ppc405GpioState *s = PPC405_GPIO(dev);
+
+ memory_region_init_io(&s->io, OBJECT(s), &ppc405_gpio_ops, s, "gpio",
+ 0x38);
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->io);
}
-static void ppc405_gpio_init(hwaddr base)
+static void ppc405_gpio_class_init(ObjectClass *oc, void *data)
{
- ppc405_gpio_t *gpio;
-
- trace_ppc405_gpio_init(base);
+ DeviceClass *dc = DEVICE_CLASS(oc);
- gpio = g_new0(ppc405_gpio_t, 1);
- memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038);
- memory_region_add_subregion(get_system_memory(), base, &gpio->io);
- qemu_register_reset(&ppc405_gpio_reset, gpio);
+ dc->realize = ppc405_gpio_realize;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
}
/*****************************************************************************/
@@ -1411,6 +1397,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT);
object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM);
+
+ object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO);
}
static void ppc405_reset(void *opaque)
@@ -1489,8 +1477,13 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
/* I2C controller */
sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
qdev_get_gpio_in(s->uic, 2));
+
/* GPIO */
- ppc405_gpio_init(0xef600700);
+ sbd = SYS_BUS_DEVICE(&s->gpio);
+ if (!sysbus_realize(sbd, errp)) {
+ return;
+ }
+ sysbus_mmio_map(sbd, 0, 0xef600700);
/* Serial ports */
if (serial_hd(0) != NULL) {
@@ -1552,6 +1545,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_GPIO,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Ppc405GpioState),
+ .class_init = ppc405_gpio_class_init,
+ }, {
.name = TYPE_PPC405_OCM,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc405OcmState),
diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events
index adb4500888..66fbf0e035 100644
--- a/hw/ppc/trace-events
+++ b/hw/ppc/trace-events
@@ -154,7 +154,6 @@ opba_init(uint64_t addr) "offet 0x%" PRIx64
ppc405_gpio_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d"
ppc405_gpio_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" PRIx64 " size %d = 0x%" PRIx64
-ppc405_gpio_init(uint64_t addr) "offet 0x%" PRIx64
ocm_update_mappings(uint32_t isarc, uint32_t isacntl, uint32_t dsarc, uint32_t dsacntl, uint32_t ocm_isarc, uint32_t ocm_isacntl, uint32_t ocm_dsarc, uint32_t ocm_dsacntl) "OCM update ISA 0x%08" PRIx32 " 0x%08" PRIx32 " (0x%08" PRIx32" 0x%08" PRIx32 ") DSA 0x%08" PRIx32 " 0x%08" PRIx32" (0x%08" PRIx32 " 0x%08" PRIx32 ")"
ocm_map(const char* prefix, uint32_t isarc) "OCM map %s 0x%08" PRIx32
--
2.30.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 06/22] ppc/ppc405: QOM'ify DMA
2022-08-13 15:34 [PATCH 00/22] QOMify PPC4xx devices and minor clean ups BALATON Zoltan
` (4 preceding siblings ...)
2022-08-13 15:34 ` [PATCH 05/22] ppc/ppc405: QOM'ify GPIO BALATON Zoltan
@ 2022-08-13 15:34 ` BALATON Zoltan
2022-08-13 15:34 ` [PATCH 07/22] ppc/ppc405: QOM'ify EBC BALATON Zoltan
` (16 subsequent siblings)
22 siblings, 0 replies; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-13 15:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
From: Cédric Le Goater <clg@kaod.org>
The DMA controller is currently modeled as a DCR device with a couple
of IRQs.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc405.h | 19 ++++++
hw/ppc/ppc405_uc.c | 141 ++++++++++++++++++++-------------------------
2 files changed, 81 insertions(+), 79 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 21f6cb3585..c75e4c7cb5 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,24 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* DMA controller */
+#define TYPE_PPC405_DMA "ppc405-dma"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA);
+struct Ppc405DmaState {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ qemu_irq irqs[4];
+ uint32_t cr[4];
+ uint32_t ct[4];
+ uint32_t da[4];
+ uint32_t sa[4];
+ uint32_t sg[4];
+ uint32_t sr;
+ uint32_t sgc;
+ uint32_t slp;
+ uint32_t pol;
+};
+
/* GPIO */
#define TYPE_PPC405_GPIO "ppc405-gpio"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO);
@@ -173,6 +191,7 @@ struct Ppc405SoCState {
Ppc405GptState gpt;
Ppc405OcmState ocm;
Ppc405GpioState gpio;
+ Ppc405DmaState dma;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 7ed3cf7149..40af07e321 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -613,35 +613,20 @@ enum {
DMA0_POL = 0x126,
};
-typedef struct ppc405_dma_t ppc405_dma_t;
-struct ppc405_dma_t {
- qemu_irq irqs[4];
- uint32_t cr[4];
- uint32_t ct[4];
- uint32_t da[4];
- uint32_t sa[4];
- uint32_t sg[4];
- uint32_t sr;
- uint32_t sgc;
- uint32_t slp;
- uint32_t pol;
-};
-
-static uint32_t dcr_read_dma (void *opaque, int dcrn)
+static uint32_t dcr_read_dma(void *opaque, int dcrn)
{
return 0;
}
-static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
+static void dcr_write_dma(void *opaque, int dcrn, uint32_t val)
{
}
-static void ppc405_dma_reset (void *opaque)
+static void ppc405_dma_reset(DeviceState *dev)
{
- ppc405_dma_t *dma;
+ Ppc405DmaState *dma = PPC405_DMA(dev);
int i;
- dma = opaque;
for (i = 0; i < 4; i++) {
dma->cr[i] = 0x00000000;
dma->ct[i] = 0x00000000;
@@ -655,61 +640,50 @@ static void ppc405_dma_reset (void *opaque)
dma->pol = 0x00000000;
}
-static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
+static void ppc405_dma_realize(DeviceState *dev, Error **errp)
+{
+ Ppc405DmaState *dma = PPC405_DMA(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(dma->irqs); i++) {
+ sysbus_init_irq(SYS_BUS_DEVICE(dma), &dma->irqs[i]);
+ }
+
+ ppc4xx_dcr_register(dcr, DMA0_CR0, dma, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_CT0, dma, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_DA0, dma, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_SA0, dma, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_SG0, dma, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_CR1, dma, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_CT1, dma, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_DA1, dma, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_SA1, dma, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_SG1, dma, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_CR2, dma, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_CT2, dma, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_DA2, dma, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_SA2, dma, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_SG2, dma, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_CR3, dma, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_CT3, dma, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_DA3, dma, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_SA3, dma, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_SG3, dma, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_SR, dma, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_SGC, dma, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_SLP, dma, &dcr_read_dma, &dcr_write_dma);
+ ppc4xx_dcr_register(dcr, DMA0_POL, dma, &dcr_read_dma, &dcr_write_dma);
+}
+
+static void ppc405_dma_class_init(ObjectClass *oc, void *data)
{
- ppc405_dma_t *dma;
-
- dma = g_new0(ppc405_dma_t, 1);
- memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
- qemu_register_reset(&ppc405_dma_reset, dma);
- ppc_dcr_register(env, DMA0_CR0,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_CT0,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_DA0,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_SA0,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_SG0,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_CR1,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_CT1,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_DA1,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_SA1,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_SG1,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_CR2,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_CT2,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_DA2,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_SA2,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_SG2,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_CR3,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_CT3,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_DA3,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_SA3,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_SG3,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_SR,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_SGC,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_SLP,
- dma, &dcr_read_dma, &dcr_write_dma);
- ppc_dcr_register(env, DMA0_POL,
- dma, &dcr_read_dma, &dcr_write_dma);
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_dma_realize;
+ dc->reset = ppc405_dma_reset;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
}
/*****************************************************************************/
@@ -1399,6 +1373,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "ocm", &s->ocm, TYPE_PPC405_OCM);
object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO);
+
+ object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
}
static void ppc405_reset(void *opaque)
@@ -1409,7 +1385,7 @@ static void ppc405_reset(void *opaque)
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
{
Ppc405SoCState *s = PPC405_SOC(dev);
- qemu_irq dma_irqs[4], mal_irqs[4];
+ qemu_irq mal_irqs[4];
CPUPPCState *env;
SysBusDevice *sbd;
int i;
@@ -1468,11 +1444,13 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
ppc405_ebc_init(env);
/* DMA controller */
- dma_irqs[0] = qdev_get_gpio_in(s->uic, 5);
- dma_irqs[1] = qdev_get_gpio_in(s->uic, 6);
- dma_irqs[2] = qdev_get_gpio_in(s->uic, 7);
- dma_irqs[3] = qdev_get_gpio_in(s->uic, 8);
- ppc405_dma_init(env, dma_irqs);
+ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->dma), &s->cpu, errp)) {
+ return;
+ }
+ sbd = SYS_BUS_DEVICE(&s->dma);
+ for (i = 0; i < ARRAY_SIZE(s->dma.irqs); i++) {
+ sysbus_connect_irq(sbd, i, qdev_get_gpio_in(s->uic, 5 + i));
+ }
/* I2C controller */
sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
@@ -1545,6 +1523,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_DMA,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc405DmaState),
+ .class_init = ppc405_dma_class_init,
+ }, {
.name = TYPE_PPC405_GPIO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Ppc405GpioState),
--
2.30.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 07/22] ppc/ppc405: QOM'ify EBC
2022-08-13 15:34 [PATCH 00/22] QOMify PPC4xx devices and minor clean ups BALATON Zoltan
` (5 preceding siblings ...)
2022-08-13 15:34 ` [PATCH 06/22] ppc/ppc405: QOM'ify DMA BALATON Zoltan
@ 2022-08-13 15:34 ` BALATON Zoltan
2022-08-13 15:34 ` [PATCH 08/22] ppc/ppc405: QOM'ify OPBA BALATON Zoltan
` (15 subsequent siblings)
22 siblings, 0 replies; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-13 15:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
From: Cédric Le Goater <clg@kaod.org>
EBC is currently modeled as a DCR device. Also drop the ppc405_ebc_init()
helper and adapt the sam460ex machine.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc405.h | 17 ++++++++++++-
hw/ppc/ppc405_uc.c | 62 ++++++++++++++++++++++++----------------------
hw/ppc/sam460ex.c | 4 ++-
3 files changed, 51 insertions(+), 32 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index c75e4c7cb5..82bf8dae93 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,21 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* Peripheral controller */
+#define TYPE_PPC405_EBC "ppc405-ebc"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC);
+struct Ppc405EbcState {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ uint32_t addr;
+ uint32_t bcr[8];
+ uint32_t bap[8];
+ uint32_t bear;
+ uint32_t besr0;
+ uint32_t besr1;
+ uint32_t cfg;
+};
+
/* DMA controller */
#define TYPE_PPC405_DMA "ppc405-dma"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA);
@@ -192,12 +207,12 @@ struct Ppc405SoCState {
Ppc405OcmState ocm;
Ppc405GpioState gpio;
Ppc405DmaState dma;
+ Ppc405EbcState ebc;
};
/* PowerPC 405 core */
ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
void ppc4xx_plb_init(CPUPPCState *env);
-void ppc405_ebc_init(CPUPPCState *env);
#endif /* PPC405_H */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 40af07e321..f259de07e2 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -393,28 +393,16 @@ static void ppc4xx_opba_init(hwaddr base)
/*****************************************************************************/
/* Peripheral controller */
-typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
-struct ppc4xx_ebc_t {
- uint32_t addr;
- uint32_t bcr[8];
- uint32_t bap[8];
- uint32_t bear;
- uint32_t besr0;
- uint32_t besr1;
- uint32_t cfg;
-};
-
enum {
EBC0_CFGADDR = 0x012,
EBC0_CFGDATA = 0x013,
};
-static uint32_t dcr_read_ebc (void *opaque, int dcrn)
+static uint32_t dcr_read_ebc(void *opaque, int dcrn)
{
- ppc4xx_ebc_t *ebc;
+ Ppc405EbcState *ebc = opaque;
uint32_t ret;
- ebc = opaque;
switch (dcrn) {
case EBC0_CFGADDR:
ret = ebc->addr;
@@ -494,11 +482,10 @@ static uint32_t dcr_read_ebc (void *opaque, int dcrn)
return ret;
}
-static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
+static void dcr_write_ebc(void *opaque, int dcrn, uint32_t val)
{
- ppc4xx_ebc_t *ebc;
+ Ppc405EbcState *ebc = opaque;
- ebc = opaque;
switch (dcrn) {
case EBC0_CFGADDR:
ebc->addr = val;
@@ -554,12 +541,11 @@ static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
}
}
-static void ebc_reset (void *opaque)
+static void ppc405_ebc_reset(DeviceState *dev)
{
- ppc4xx_ebc_t *ebc;
+ Ppc405EbcState *ebc = PPC405_EBC(dev);
int i;
- ebc = opaque;
ebc->addr = 0x00000000;
ebc->bap[0] = 0x7F8FFE80;
ebc->bcr[0] = 0xFFE28000;
@@ -572,16 +558,23 @@ static void ebc_reset (void *opaque)
ebc->cfg = 0x80400000;
}
-void ppc405_ebc_init(CPUPPCState *env)
+static void ppc405_ebc_realize(DeviceState *dev, Error **errp)
{
- ppc4xx_ebc_t *ebc;
-
- ebc = g_new0(ppc4xx_ebc_t, 1);
- qemu_register_reset(&ebc_reset, ebc);
- ppc_dcr_register(env, EBC0_CFGADDR,
- ebc, &dcr_read_ebc, &dcr_write_ebc);
- ppc_dcr_register(env, EBC0_CFGDATA,
- ebc, &dcr_read_ebc, &dcr_write_ebc);
+ Ppc405EbcState *ebc = PPC405_EBC(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
+
+ ppc4xx_dcr_register(dcr, EBC0_CFGADDR, ebc, &dcr_read_ebc, &dcr_write_ebc);
+ ppc4xx_dcr_register(dcr, EBC0_CFGDATA, ebc, &dcr_read_ebc, &dcr_write_ebc);
+}
+
+static void ppc405_ebc_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_ebc_realize;
+ dc->reset = ppc405_ebc_reset;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
}
/*****************************************************************************/
@@ -1375,6 +1368,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO);
object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
+
+ object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
}
static void ppc405_reset(void *opaque)
@@ -1441,7 +1436,9 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
s->do_dram_init);
/* External bus controller */
- ppc405_ebc_init(env);
+ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
+ return;
+ }
/* DMA controller */
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->dma), &s->cpu, errp)) {
@@ -1523,6 +1520,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_EBC,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc405EbcState),
+ .class_init = ppc405_ebc_class_init,
+ }, {
.name = TYPE_PPC405_DMA,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc405DmaState),
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 0357ee077f..320c61a7f3 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -371,7 +371,9 @@ static void sam460ex_init(MachineState *machine)
qdev_get_gpio_in(uic[0], 3));
/* External bus controller */
- ppc405_ebc_init(env);
+ dev = qdev_new(TYPE_PPC405_EBC);
+ ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
+ object_unref(OBJECT(dev));
/* CPR */
ppc4xx_cpr_init(env);
--
2.30.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 08/22] ppc/ppc405: QOM'ify OPBA
2022-08-13 15:34 [PATCH 00/22] QOMify PPC4xx devices and minor clean ups BALATON Zoltan
` (6 preceding siblings ...)
2022-08-13 15:34 ` [PATCH 07/22] ppc/ppc405: QOM'ify EBC BALATON Zoltan
@ 2022-08-13 15:34 ` BALATON Zoltan
2022-08-13 15:34 ` [PATCH 09/22] ppc/ppc405: QOM'ify POB BALATON Zoltan
` (14 subsequent siblings)
22 siblings, 0 replies; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-13 15:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
From: Cédric Le Goater <clg@kaod.org>
The OPB arbitrer is currently modeled as a simple SysBus device with a
unique memory region.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc405.h | 12 +++++++++++
hw/ppc/ppc405_uc.c | 49 +++++++++++++++++++++++++++------------------
hw/ppc/trace-events | 1 -
3 files changed, 41 insertions(+), 21 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 82bf8dae93..d63c2acdc7 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,17 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* OPB arbitrer */
+#define TYPE_PPC405_OPBA "ppc405-opba"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA);
+struct Ppc405OpbaState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion io;
+ uint8_t cr;
+ uint8_t pr;
+};
+
/* Peripheral controller */
#define TYPE_PPC405_EBC "ppc405-ebc"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC);
@@ -208,6 +219,7 @@ struct Ppc405SoCState {
Ppc405GpioState gpio;
Ppc405DmaState dma;
Ppc405EbcState ebc;
+ Ppc405OpbaState opba;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index f259de07e2..911ec958c6 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -310,16 +310,9 @@ static void ppc4xx_pob_init(CPUPPCState *env)
/*****************************************************************************/
/* OPB arbitrer */
-typedef struct ppc4xx_opba_t ppc4xx_opba_t;
-struct ppc4xx_opba_t {
- MemoryRegion io;
- uint8_t cr;
- uint8_t pr;
-};
-
static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
{
- ppc4xx_opba_t *opba = opaque;
+ Ppc405OpbaState *opba = opaque;
uint32_t ret;
switch (addr) {
@@ -341,7 +334,7 @@ static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
static void opba_writeb(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
- ppc4xx_opba_t *opba = opaque;
+ Ppc405OpbaState *opba = opaque;
trace_opba_writeb(addr, value);
@@ -366,25 +359,30 @@ static const MemoryRegionOps opba_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static void ppc4xx_opba_reset (void *opaque)
+static void ppc405_opba_reset(DeviceState *dev)
{
- ppc4xx_opba_t *opba;
+ Ppc405OpbaState *opba = PPC405_OPBA(dev);
- opba = opaque;
opba->cr = 0x00; /* No dynamic priorities - park disabled */
opba->pr = 0x11;
}
-static void ppc4xx_opba_init(hwaddr base)
+static void ppc405_opba_realize(DeviceState *dev, Error **errp)
{
- ppc4xx_opba_t *opba;
+ Ppc405OpbaState *s = PPC405_OPBA(dev);
+
+ memory_region_init_io(&s->io, OBJECT(s), &opba_ops, s, "opba", 2);
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->io);
+}
- trace_opba_init(base);
+static void ppc405_opba_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
- opba = g_new0(ppc4xx_opba_t, 1);
- memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002);
- memory_region_add_subregion(get_system_memory(), base, &opba->io);
- qemu_register_reset(ppc4xx_opba_reset, opba);
+ dc->realize = ppc405_opba_realize;
+ dc->reset = ppc405_opba_reset;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
}
/*****************************************************************************/
@@ -1370,6 +1368,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
+
+ object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
}
static void ppc405_reset(void *opaque)
@@ -1407,7 +1407,11 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
ppc4xx_pob_init(env);
/* OBP arbitrer */
- ppc4xx_opba_init(0xef600600);
+ sbd = SYS_BUS_DEVICE(&s->opba);
+ if (!sysbus_realize(sbd, errp)) {
+ return;
+ }
+ sysbus_mmio_map(sbd, 0, 0xef600600);
/* Universal interrupt controller */
s->uic = qdev_new(TYPE_PPC_UIC);
@@ -1520,6 +1524,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_OPBA,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Ppc405OpbaState),
+ .class_init = ppc405_opba_class_init,
+ }, {
.name = TYPE_PPC405_EBC,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc405EbcState),
diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events
index 66fbf0e035..38b62e9348 100644
--- a/hw/ppc/trace-events
+++ b/hw/ppc/trace-events
@@ -150,7 +150,6 @@ ppc440_pcix_reg_write(uint64_t addr, uint32_t val, uint32_t size) "addr 0x%" PRI
# ppc405_boards.c
opba_readb(uint64_t addr, uint32_t val) "addr 0x%" PRIx64 " = 0x%" PRIx32
opba_writeb(uint64_t addr, uint64_t val) "addr 0x%" PRIx64 " = 0x%" PRIx64
-opba_init(uint64_t addr) "offet 0x%" PRIx64
ppc405_gpio_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d"
ppc405_gpio_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" PRIx64 " size %d = 0x%" PRIx64
--
2.30.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 09/22] ppc/ppc405: QOM'ify POB
2022-08-13 15:34 [PATCH 00/22] QOMify PPC4xx devices and minor clean ups BALATON Zoltan
` (7 preceding siblings ...)
2022-08-13 15:34 ` [PATCH 08/22] ppc/ppc405: QOM'ify OPBA BALATON Zoltan
@ 2022-08-13 15:34 ` BALATON Zoltan
2022-08-13 15:34 ` [PATCH 10/22] ppc/ppc405: QOM'ify PLB BALATON Zoltan
` (13 subsequent siblings)
22 siblings, 0 replies; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-13 15:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
From: Cédric Le Goater <clg@kaod.org>
POB is currently modeled as a simple DCR device.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc405.h | 12 ++++++++++
hw/ppc/ppc405_uc.c | 56 ++++++++++++++++++++++++++--------------------
2 files changed, 44 insertions(+), 24 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index d63c2acdc7..4140e811d5 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,17 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* PLB to OPB bridge */
+#define TYPE_PPC405_POB "ppc405-pob"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
+struct Ppc405PobState {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ uint32_t bear;
+ uint32_t besr0;
+ uint32_t besr1;
+};
+
/* OPB arbitrer */
#define TYPE_PPC405_OPBA "ppc405-opba"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA);
@@ -220,6 +231,7 @@ struct Ppc405SoCState {
Ppc405DmaState dma;
Ppc405EbcState ebc;
Ppc405OpbaState opba;
+ Ppc405PobState pob;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 911ec958c6..0ad1cce790 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -234,19 +234,11 @@ enum {
POB0_BEAR = 0x0A4,
};
-typedef struct ppc4xx_pob_t ppc4xx_pob_t;
-struct ppc4xx_pob_t {
- uint32_t bear;
- uint32_t besr0;
- uint32_t besr1;
-};
-
-static uint32_t dcr_read_pob (void *opaque, int dcrn)
+static uint32_t dcr_read_pob(void *opaque, int dcrn)
{
- ppc4xx_pob_t *pob;
+ Ppc405PobState *pob = opaque;
uint32_t ret;
- pob = opaque;
switch (dcrn) {
case POB0_BEAR:
ret = pob->bear;
@@ -266,11 +258,10 @@ static uint32_t dcr_read_pob (void *opaque, int dcrn)
return ret;
}
-static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
+static void dcr_write_pob(void *opaque, int dcrn, uint32_t val)
{
- ppc4xx_pob_t *pob;
+ Ppc405PobState *pob = opaque;
- pob = opaque;
switch (dcrn) {
case POB0_BEAR:
/* Read only */
@@ -286,26 +277,34 @@ static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
}
}
-static void ppc4xx_pob_reset (void *opaque)
+static void ppc405_pob_reset(DeviceState *dev)
{
- ppc4xx_pob_t *pob;
+ Ppc405PobState *pob = PPC405_POB(dev);
- pob = opaque;
/* No error */
pob->bear = 0x00000000;
pob->besr0 = 0x0000000;
pob->besr1 = 0x0000000;
}
-static void ppc4xx_pob_init(CPUPPCState *env)
+static void ppc405_pob_realize(DeviceState *dev, Error **errp)
+{
+ Ppc405PobState *pob = PPC405_POB(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
+
+ ppc4xx_dcr_register(dcr, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
+ ppc4xx_dcr_register(dcr, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
+ ppc4xx_dcr_register(dcr, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
+}
+
+static void ppc405_pob_class_init(ObjectClass *oc, void *data)
{
- ppc4xx_pob_t *pob;
+ DeviceClass *dc = DEVICE_CLASS(oc);
- pob = g_new0(ppc4xx_pob_t, 1);
- ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
- ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
- ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
- qemu_register_reset(ppc4xx_pob_reset, pob);
+ dc->realize = ppc405_pob_realize;
+ dc->reset = ppc405_pob_reset;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
}
/*****************************************************************************/
@@ -1370,6 +1369,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
+
+ object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB);
}
static void ppc405_reset(void *opaque)
@@ -1404,7 +1405,9 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
ppc4xx_plb_init(env);
/* PLB to OPB bridge */
- ppc4xx_pob_init(env);
+ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->pob), &s->cpu, errp)) {
+ return;
+ }
/* OBP arbitrer */
sbd = SYS_BUS_DEVICE(&s->opba);
@@ -1524,6 +1527,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_POB,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc405PobState),
+ .class_init = ppc405_pob_class_init,
+ }, {
.name = TYPE_PPC405_OPBA,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Ppc405OpbaState),
--
2.30.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 10/22] ppc/ppc405: QOM'ify PLB
2022-08-13 15:34 [PATCH 00/22] QOMify PPC4xx devices and minor clean ups BALATON Zoltan
` (8 preceding siblings ...)
2022-08-13 15:34 ` [PATCH 09/22] ppc/ppc405: QOM'ify POB BALATON Zoltan
@ 2022-08-13 15:34 ` BALATON Zoltan
2022-08-13 15:34 ` [PATCH 11/22] ppc/ppc405: QOM'ify MAL BALATON Zoltan
` (12 subsequent siblings)
22 siblings, 0 replies; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-13 15:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
From: Cédric Le Goater <clg@kaod.org>
PLB is currently modeled as a simple DCR device. Also drop the
ppc4xx_plb_init() helper and adapt the sam460ex machine.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc405.h | 14 ++++++++--
hw/ppc/ppc405_uc.c | 64 ++++++++++++++++++++++++++--------------------
hw/ppc/sam460ex.c | 4 ++-
3 files changed, 51 insertions(+), 31 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 4140e811d5..cb34792daf 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,6 +63,17 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+/* Peripheral local bus arbitrer */
+#define TYPE_PPC405_PLB "ppc405-plb"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PlbState, PPC405_PLB);
+struct Ppc405PlbState {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ uint32_t acr;
+ uint32_t bear;
+ uint32_t besr;
+};
+
/* PLB to OPB bridge */
#define TYPE_PPC405_POB "ppc405-pob"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
@@ -232,11 +243,10 @@ struct Ppc405SoCState {
Ppc405EbcState ebc;
Ppc405OpbaState opba;
Ppc405PobState pob;
+ Ppc405PlbState plb;
};
/* PowerPC 405 core */
ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
-void ppc4xx_plb_init(CPUPPCState *env);
-
#endif /* PPC405_H */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 0ad1cce790..94ea6b5b70 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -148,19 +148,11 @@ enum {
PLB4A1_ACR = 0x089,
};
-typedef struct ppc4xx_plb_t ppc4xx_plb_t;
-struct ppc4xx_plb_t {
- uint32_t acr;
- uint32_t bear;
- uint32_t besr;
-};
-
-static uint32_t dcr_read_plb (void *opaque, int dcrn)
+static uint32_t dcr_read_plb(void *opaque, int dcrn)
{
- ppc4xx_plb_t *plb;
+ Ppc405PlbState *plb = opaque;
uint32_t ret;
- plb = opaque;
switch (dcrn) {
case PLB0_ACR:
ret = plb->acr;
@@ -180,11 +172,10 @@ static uint32_t dcr_read_plb (void *opaque, int dcrn)
return ret;
}
-static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
+static void dcr_write_plb(void *opaque, int dcrn, uint32_t val)
{
- ppc4xx_plb_t *plb;
+ Ppc405PlbState *plb = opaque;
- plb = opaque;
switch (dcrn) {
case PLB0_ACR:
/* We don't care about the actual parameters written as
@@ -202,28 +193,36 @@ static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
}
}
-static void ppc4xx_plb_reset (void *opaque)
+static void ppc405_plb_reset(DeviceState *dev)
{
- ppc4xx_plb_t *plb;
+ Ppc405PlbState *plb = PPC405_PLB(dev);
- plb = opaque;
plb->acr = 0x00000000;
plb->bear = 0x00000000;
plb->besr = 0x00000000;
}
-void ppc4xx_plb_init(CPUPPCState *env)
+static void ppc405_plb_realize(DeviceState *dev, Error **errp)
+{
+ Ppc405PlbState *plb = PPC405_PLB(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
+
+ ppc4xx_dcr_register(dcr, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
+ ppc4xx_dcr_register(dcr, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
+ ppc4xx_dcr_register(dcr, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
+ ppc4xx_dcr_register(dcr, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
+ ppc4xx_dcr_register(dcr, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
+ ppc4xx_dcr_register(dcr, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb);
+}
+
+static void ppc405_plb_class_init(ObjectClass *oc, void *data)
{
- ppc4xx_plb_t *plb;
-
- plb = g_new0(ppc4xx_plb_t, 1);
- ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
- ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
- ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
- ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
- ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
- ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb);
- qemu_register_reset(ppc4xx_plb_reset, plb);
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_plb_realize;
+ dc->reset = ppc405_plb_reset;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
}
/*****************************************************************************/
@@ -1371,6 +1370,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB);
+
+ object_initialize_child(obj, "plb", &s->plb, TYPE_PPC405_PLB);
}
static void ppc405_reset(void *opaque)
@@ -1402,7 +1403,9 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
}
/* PLB arbitrer */
- ppc4xx_plb_init(env);
+ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->plb), &s->cpu, errp)) {
+ return;
+ }
/* PLB to OPB bridge */
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->pob), &s->cpu, errp)) {
@@ -1527,6 +1530,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
+ .name = TYPE_PPC405_PLB,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc405PlbState),
+ .class_init = ppc405_plb_class_init,
+ }, {
.name = TYPE_PPC405_POB,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc405PobState),
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 320c61a7f3..31139c1554 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -309,7 +309,9 @@ static void sam460ex_init(MachineState *machine)
ppc_dcr_init(env, NULL, NULL);
/* PLB arbitrer */
- ppc4xx_plb_init(env);
+ dev = qdev_new(TYPE_PPC405_PLB);
+ ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
+ object_unref(OBJECT(dev));
/* interrupt controllers */
for (i = 0; i < ARRAY_SIZE(uic); i++) {
--
2.30.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 11/22] ppc/ppc405: QOM'ify MAL
2022-08-13 15:34 [PATCH 00/22] QOMify PPC4xx devices and minor clean ups BALATON Zoltan
` (9 preceding siblings ...)
2022-08-13 15:34 ` [PATCH 10/22] ppc/ppc405: QOM'ify PLB BALATON Zoltan
@ 2022-08-13 15:34 ` BALATON Zoltan
2022-08-13 15:34 ` [PATCH 12/22] ppc4xx: Move PLB model to ppc4xx_devs.c BALATON Zoltan
` (11 subsequent siblings)
22 siblings, 0 replies; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-13 15:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
From: Cédric Le Goater <clg@kaod.org>
The Memory Access Layer (MAL) controller is currently modeled as a DCR
device with 4 IRQs. Also drop the ppc4xx_mal_init() helper and adapt
the sam460ex machine.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc405.h | 1 +
hw/ppc/ppc405_uc.c | 17 +++--
hw/ppc/ppc4xx_devs.c | 145 ++++++++++++++++++++--------------------
hw/ppc/sam460ex.c | 12 ++--
include/hw/ppc/ppc4xx.h | 28 +++++++-
5 files changed, 117 insertions(+), 86 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index cb34792daf..31c94e4742 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -244,6 +244,7 @@ struct Ppc405SoCState {
Ppc405OpbaState opba;
Ppc405PobState pob;
Ppc405PlbState plb;
+ Ppc4xxMalState mal;
};
/* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 94ea6b5b70..922c23346f 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1372,6 +1372,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB);
object_initialize_child(obj, "plb", &s->plb, TYPE_PPC405_PLB);
+
+ object_initialize_child(obj, "mal", &s->mal, TYPE_PPC4xx_MAL);
}
static void ppc405_reset(void *opaque)
@@ -1382,7 +1384,6 @@ static void ppc405_reset(void *opaque)
static void ppc405_soc_realize(DeviceState *dev, Error **errp)
{
Ppc405SoCState *s = PPC405_SOC(dev);
- qemu_irq mal_irqs[4];
CPUPPCState *env;
SysBusDevice *sbd;
int i;
@@ -1500,11 +1501,15 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
}
/* MAL */
- mal_irqs[0] = qdev_get_gpio_in(s->uic, 11);
- mal_irqs[1] = qdev_get_gpio_in(s->uic, 12);
- mal_irqs[2] = qdev_get_gpio_in(s->uic, 13);
- mal_irqs[3] = qdev_get_gpio_in(s->uic, 14);
- ppc4xx_mal_init(env, 4, 2, mal_irqs);
+ object_property_set_int(OBJECT(&s->mal), "txc-num", 4, &error_abort);
+ object_property_set_int(OBJECT(&s->mal), "rxc-num", 2, &error_abort);
+ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->mal), &s->cpu, errp)) {
+ return;
+ }
+ sbd = SYS_BUS_DEVICE(&s->mal);
+ for (i = 0; i < ARRAY_SIZE(s->mal.irqs); i++) {
+ sysbus_connect_irq(sbd, i, qdev_get_gpio_in(s->uic, 11 + i));
+ }
/* Ethernet */
/* Uses UIC IRQs 9, 15, 17 */
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index f4d7ae9567..7d40c1b68a 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -459,32 +459,10 @@ enum {
MAL0_RCBS1 = 0x1E1,
};
-typedef struct ppc4xx_mal_t ppc4xx_mal_t;
-struct ppc4xx_mal_t {
- qemu_irq irqs[4];
- uint32_t cfg;
- uint32_t esr;
- uint32_t ier;
- uint32_t txcasr;
- uint32_t txcarr;
- uint32_t txeobisr;
- uint32_t txdeir;
- uint32_t rxcasr;
- uint32_t rxcarr;
- uint32_t rxeobisr;
- uint32_t rxdeir;
- uint32_t *txctpr;
- uint32_t *rxctpr;
- uint32_t *rcbs;
- uint8_t txcnum;
- uint8_t rxcnum;
-};
-
-static void ppc4xx_mal_reset(void *opaque)
+static void ppc4xx_mal_reset(DeviceState *dev)
{
- ppc4xx_mal_t *mal;
+ Ppc4xxMalState *mal = PPC4xx_MAL(dev);
- mal = opaque;
mal->cfg = 0x0007C000;
mal->esr = 0x00000000;
mal->ier = 0x00000000;
@@ -498,10 +476,9 @@ static void ppc4xx_mal_reset(void *opaque)
static uint32_t dcr_read_mal(void *opaque, int dcrn)
{
- ppc4xx_mal_t *mal;
+ Ppc4xxMalState *mal = opaque;
uint32_t ret;
- mal = opaque;
switch (dcrn) {
case MAL0_CFG:
ret = mal->cfg;
@@ -555,13 +532,12 @@ static uint32_t dcr_read_mal(void *opaque, int dcrn)
static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
{
- ppc4xx_mal_t *mal;
+ Ppc4xxMalState *mal = opaque;
- mal = opaque;
switch (dcrn) {
case MAL0_CFG:
if (val & 0x80000000) {
- ppc4xx_mal_reset(mal);
+ ppc4xx_mal_reset(DEVICE(mal));
}
mal->cfg = val & 0x00FFC087;
break;
@@ -612,59 +588,76 @@ static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
}
}
-void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
- qemu_irq irqs[4])
+static void ppc4xx_mal_realize(DeviceState *dev, Error **errp)
{
- ppc4xx_mal_t *mal;
+ Ppc4xxMalState *mal = PPC4xx_MAL(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
int i;
- assert(txcnum <= 32 && rxcnum <= 32);
- mal = g_malloc0(sizeof(*mal));
- mal->txcnum = txcnum;
- mal->rxcnum = rxcnum;
- mal->txctpr = g_new0(uint32_t, txcnum);
- mal->rxctpr = g_new0(uint32_t, rxcnum);
- mal->rcbs = g_new0(uint32_t, rxcnum);
- for (i = 0; i < 4; i++) {
- mal->irqs[i] = irqs[i];
+ if (mal->txcnum > 32 || mal->rxcnum > 32) {
+ error_setg(errp, "invalid TXC/RXC number");
+ return;
+ }
+
+ mal->txctpr = g_new0(uint32_t, mal->txcnum);
+ mal->rxctpr = g_new0(uint32_t, mal->rxcnum);
+ mal->rcbs = g_new0(uint32_t, mal->rxcnum);
+
+ for (i = 0; i < ARRAY_SIZE(mal->irqs); i++) {
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &mal->irqs[i]);
}
- qemu_register_reset(&ppc4xx_mal_reset, mal);
- ppc_dcr_register(env, MAL0_CFG,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_ESR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_IER,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_TXCASR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_TXCARR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_TXEOBISR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_TXDEIR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_RXCASR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_RXCARR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_RXEOBISR,
- mal, &dcr_read_mal, &dcr_write_mal);
- ppc_dcr_register(env, MAL0_RXDEIR,
- mal, &dcr_read_mal, &dcr_write_mal);
- for (i = 0; i < txcnum; i++) {
- ppc_dcr_register(env, MAL0_TXCTP0R + i,
- mal, &dcr_read_mal, &dcr_write_mal);
+
+ ppc4xx_dcr_register(dcr, MAL0_CFG, mal, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_ESR, mal, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_IER, mal, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_TXCASR, mal, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_TXCARR, mal, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_TXEOBISR, mal, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_TXDEIR, mal, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_RXCASR, mal, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_RXCARR, mal, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_RXEOBISR, mal, &dcr_read_mal, &dcr_write_mal);
+ ppc4xx_dcr_register(dcr, MAL0_RXDEIR, mal, &dcr_read_mal, &dcr_write_mal);
+ for (i = 0; i < mal->txcnum; i++) {
+ ppc4xx_dcr_register(dcr, MAL0_TXCTP0R + i,
+ mal, &dcr_read_mal, &dcr_write_mal);
}
- for (i = 0; i < rxcnum; i++) {
- ppc_dcr_register(env, MAL0_RXCTP0R + i,
- mal, &dcr_read_mal, &dcr_write_mal);
+ for (i = 0; i < mal->rxcnum; i++) {
+ ppc4xx_dcr_register(dcr, MAL0_RXCTP0R + i,
+ mal, &dcr_read_mal, &dcr_write_mal);
}
- for (i = 0; i < rxcnum; i++) {
- ppc_dcr_register(env, MAL0_RCBS0 + i,
- mal, &dcr_read_mal, &dcr_write_mal);
+ for (i = 0; i < mal->rxcnum; i++) {
+ ppc4xx_dcr_register(dcr, MAL0_RCBS0 + i,
+ mal, &dcr_read_mal, &dcr_write_mal);
}
}
+static void ppc4xx_mal_finalize(Object *obj)
+{
+ Ppc4xxMalState *mal = PPC4xx_MAL(obj);
+
+ g_free(mal->rcbs);
+ g_free(mal->rxctpr);
+ g_free(mal->txctpr);
+}
+
+static Property ppc4xx_mal_properties[] = {
+ DEFINE_PROP_UINT8("txc-num", Ppc4xxMalState, txcnum, 0),
+ DEFINE_PROP_UINT8("rxc-num", Ppc4xxMalState, rxcnum, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc4xx_mal_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc4xx_mal_realize;
+ dc->reset = ppc4xx_mal_reset;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
+ device_class_set_props(dc, ppc4xx_mal_properties);
+}
+
/* PPC4xx_DCR_DEVICE */
void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
@@ -696,6 +689,12 @@ static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc4xx_types[] = {
{
+ .name = TYPE_PPC4xx_MAL,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc4xxMalState),
+ .instance_finalize = ppc4xx_mal_finalize,
+ .class_init = ppc4xx_mal_class_init,
+ }, {
.name = TYPE_PPC4xx_DCR_DEVICE,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Ppc4xxDcrDeviceState),
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 31139c1554..c16303462d 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -280,7 +280,6 @@ static void sam460ex_init(MachineState *machine)
hwaddr ram_sizes[SDRAM_NR_BANKS] = {0};
MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
DeviceState *uic[4];
- qemu_irq mal_irqs[4];
int i;
PCIBus *pci_bus;
PowerPCCPU *cpu;
@@ -387,10 +386,15 @@ static void sam460ex_init(MachineState *machine)
ppc4xx_sdr_init(env);
/* MAL */
- for (i = 0; i < ARRAY_SIZE(mal_irqs); i++) {
- mal_irqs[i] = qdev_get_gpio_in(uic[2], 3 + i);
+ dev = qdev_new(TYPE_PPC4xx_MAL);
+ qdev_prop_set_uint32(dev, "txc-num", 4);
+ qdev_prop_set_uint32(dev, "rxc-num", 16);
+ ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
+ object_unref(OBJECT(dev));
+ sbdev = SYS_BUS_DEVICE(dev);
+ for (i = 0; i < ARRAY_SIZE(PPC4xx_MAL(dev)->irqs); i++) {
+ sysbus_connect_irq(sbdev, i, qdev_get_gpio_in(uic[2], 3 + i));
}
- ppc4xx_mal_init(env, 4, 16, mal_irqs);
/* DMA */
ppc4xx_dma_init(env, 0x200);
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index a537a5567b..f40bd49bc7 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -40,9 +40,6 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
hwaddr *ram_sizes,
int do_init);
-void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
- qemu_irq irqs[4]);
-
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
/*
@@ -61,4 +58,29 @@ void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
Error **errp);
+/* Memory Access Layer (MAL) */
+#define TYPE_PPC4xx_MAL "ppc4xx-mal"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxMalState, PPC4xx_MAL);
+struct Ppc4xxMalState {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ qemu_irq irqs[4];
+ uint32_t cfg;
+ uint32_t esr;
+ uint32_t ier;
+ uint32_t txcasr;
+ uint32_t txcarr;
+ uint32_t txeobisr;
+ uint32_t txdeir;
+ uint32_t rxcasr;
+ uint32_t rxcarr;
+ uint32_t rxeobisr;
+ uint32_t rxdeir;
+ uint32_t *txctpr;
+ uint32_t *rxctpr;
+ uint32_t *rcbs;
+ uint8_t txcnum;
+ uint8_t rxcnum;
+};
+
#endif /* PPC4XX_H */
--
2.30.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 12/22] ppc4xx: Move PLB model to ppc4xx_devs.c
2022-08-13 15:34 [PATCH 00/22] QOMify PPC4xx devices and minor clean ups BALATON Zoltan
` (10 preceding siblings ...)
2022-08-13 15:34 ` [PATCH 11/22] ppc/ppc405: QOM'ify MAL BALATON Zoltan
@ 2022-08-13 15:34 ` BALATON Zoltan
2022-08-16 7:34 ` Cédric Le Goater
2022-08-13 15:34 ` [PATCH 13/22] ppc4xx: Move EBC " BALATON Zoltan
` (10 subsequent siblings)
22 siblings, 1 reply; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-13 15:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
The PLB is shared between 405 and 440 so move it to the shared file.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc405.h | 11 -----
hw/ppc/ppc405_uc.c | 93 ----------------------------------------
hw/ppc/ppc4xx_devs.c | 94 +++++++++++++++++++++++++++++++++++++++++
include/hw/ppc/ppc4xx.h | 11 +++++
4 files changed, 105 insertions(+), 104 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 31c94e4742..d85c595f9d 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,17 +63,6 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
-/* Peripheral local bus arbitrer */
-#define TYPE_PPC405_PLB "ppc405-plb"
-OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PlbState, PPC405_PLB);
-struct Ppc405PlbState {
- Ppc4xxDcrDeviceState parent_obj;
-
- uint32_t acr;
- uint32_t bear;
- uint32_t besr;
-};
-
/* PLB to OPB bridge */
#define TYPE_PPC405_POB "ppc405-pob"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 922c23346f..3de6c77631 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -137,94 +137,6 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size)
/*****************************************************************************/
/* Shared peripherals */
-/*****************************************************************************/
-/* Peripheral local bus arbitrer */
-enum {
- PLB3A0_ACR = 0x077,
- PLB4A0_ACR = 0x081,
- PLB0_BESR = 0x084,
- PLB0_BEAR = 0x086,
- PLB0_ACR = 0x087,
- PLB4A1_ACR = 0x089,
-};
-
-static uint32_t dcr_read_plb(void *opaque, int dcrn)
-{
- Ppc405PlbState *plb = opaque;
- uint32_t ret;
-
- switch (dcrn) {
- case PLB0_ACR:
- ret = plb->acr;
- break;
- case PLB0_BEAR:
- ret = plb->bear;
- break;
- case PLB0_BESR:
- ret = plb->besr;
- break;
- default:
- /* Avoid gcc warning */
- ret = 0;
- break;
- }
-
- return ret;
-}
-
-static void dcr_write_plb(void *opaque, int dcrn, uint32_t val)
-{
- Ppc405PlbState *plb = opaque;
-
- switch (dcrn) {
- case PLB0_ACR:
- /* We don't care about the actual parameters written as
- * we don't manage any priorities on the bus
- */
- plb->acr = val & 0xF8000000;
- break;
- case PLB0_BEAR:
- /* Read only */
- break;
- case PLB0_BESR:
- /* Write-clear */
- plb->besr &= ~val;
- break;
- }
-}
-
-static void ppc405_plb_reset(DeviceState *dev)
-{
- Ppc405PlbState *plb = PPC405_PLB(dev);
-
- plb->acr = 0x00000000;
- plb->bear = 0x00000000;
- plb->besr = 0x00000000;
-}
-
-static void ppc405_plb_realize(DeviceState *dev, Error **errp)
-{
- Ppc405PlbState *plb = PPC405_PLB(dev);
- Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
-
- ppc4xx_dcr_register(dcr, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
- ppc4xx_dcr_register(dcr, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
- ppc4xx_dcr_register(dcr, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
- ppc4xx_dcr_register(dcr, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
- ppc4xx_dcr_register(dcr, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
- ppc4xx_dcr_register(dcr, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb);
-}
-
-static void ppc405_plb_class_init(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
-
- dc->realize = ppc405_plb_realize;
- dc->reset = ppc405_plb_reset;
- /* Reason: only works as function of a ppc4xx SoC */
- dc->user_creatable = false;
-}
-
/*****************************************************************************/
/* PLB to OPB bridge */
enum {
@@ -1535,11 +1447,6 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
- .name = TYPE_PPC405_PLB,
- .parent = TYPE_PPC4xx_DCR_DEVICE,
- .instance_size = sizeof(Ppc405PlbState),
- .class_init = ppc405_plb_class_init,
- }, {
.name = TYPE_PPC405_POB,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc405PobState),
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 7d40c1b68a..843d759b1b 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -658,6 +658,95 @@ static void ppc4xx_mal_class_init(ObjectClass *oc, void *data)
device_class_set_props(dc, ppc4xx_mal_properties);
}
+/*****************************************************************************/
+/* Peripheral local bus arbitrer */
+enum {
+ PLB3A0_ACR = 0x077,
+ PLB4A0_ACR = 0x081,
+ PLB0_BESR = 0x084,
+ PLB0_BEAR = 0x086,
+ PLB0_ACR = 0x087,
+ PLB4A1_ACR = 0x089,
+};
+
+static uint32_t dcr_read_plb(void *opaque, int dcrn)
+{
+ Ppc405PlbState *plb = opaque;
+ uint32_t ret;
+
+ switch (dcrn) {
+ case PLB0_ACR:
+ ret = plb->acr;
+ break;
+ case PLB0_BEAR:
+ ret = plb->bear;
+ break;
+ case PLB0_BESR:
+ ret = plb->besr;
+ break;
+ default:
+ /* Avoid gcc warning */
+ ret = 0;
+ break;
+ }
+
+ return ret;
+}
+
+static void dcr_write_plb(void *opaque, int dcrn, uint32_t val)
+{
+ Ppc405PlbState *plb = opaque;
+
+ switch (dcrn) {
+ case PLB0_ACR:
+ /*
+ * We don't care about the actual parameters written as
+ * we don't manage any priorities on the bus
+ */
+ plb->acr = val & 0xF8000000;
+ break;
+ case PLB0_BEAR:
+ /* Read only */
+ break;
+ case PLB0_BESR:
+ /* Write-clear */
+ plb->besr &= ~val;
+ break;
+ }
+}
+
+static void ppc405_plb_reset(DeviceState *dev)
+{
+ Ppc405PlbState *plb = PPC405_PLB(dev);
+
+ plb->acr = 0x00000000;
+ plb->bear = 0x00000000;
+ plb->besr = 0x00000000;
+}
+
+static void ppc405_plb_realize(DeviceState *dev, Error **errp)
+{
+ Ppc405PlbState *plb = PPC405_PLB(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
+
+ ppc4xx_dcr_register(dcr, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
+ ppc4xx_dcr_register(dcr, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
+ ppc4xx_dcr_register(dcr, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
+ ppc4xx_dcr_register(dcr, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
+ ppc4xx_dcr_register(dcr, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
+ ppc4xx_dcr_register(dcr, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb);
+}
+
+static void ppc405_plb_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_plb_realize;
+ dc->reset = ppc405_plb_reset;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
+}
+
/* PPC4xx_DCR_DEVICE */
void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
@@ -694,6 +783,11 @@ static const TypeInfo ppc4xx_types[] = {
.instance_size = sizeof(Ppc4xxMalState),
.instance_finalize = ppc4xx_mal_finalize,
.class_init = ppc4xx_mal_class_init,
+ }, {
+ .name = TYPE_PPC405_PLB,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc405PlbState),
+ .class_init = ppc405_plb_class_init,
}, {
.name = TYPE_PPC4xx_DCR_DEVICE,
.parent = TYPE_SYS_BUS_DEVICE,
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index f40bd49bc7..e696e159f3 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -83,4 +83,15 @@ struct Ppc4xxMalState {
uint8_t rxcnum;
};
+/* Peripheral local bus arbitrer */
+#define TYPE_PPC405_PLB "ppc405-plb"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PlbState, PPC405_PLB);
+struct Ppc405PlbState {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ uint32_t acr;
+ uint32_t bear;
+ uint32_t besr;
+};
+
#endif /* PPC4XX_H */
--
2.30.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH 12/22] ppc4xx: Move PLB model to ppc4xx_devs.c
2022-08-13 15:34 ` [PATCH 12/22] ppc4xx: Move PLB model to ppc4xx_devs.c BALATON Zoltan
@ 2022-08-16 7:34 ` Cédric Le Goater
2022-08-16 9:35 ` BALATON Zoltan
0 siblings, 1 reply; 37+ messages in thread
From: Cédric Le Goater @ 2022-08-16 7:34 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc
Cc: Daniel Henrique Barboza, Peter Maydell
On 8/13/22 17:34, BALATON Zoltan wrote:
> The PLB is shared between 405 and 440 so move it to the shared file.
Should we rename the device to Ppc4xxPlbState ?
Thanks,
C.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> hw/ppc/ppc405.h | 11 -----
> hw/ppc/ppc405_uc.c | 93 ----------------------------------------
> hw/ppc/ppc4xx_devs.c | 94 +++++++++++++++++++++++++++++++++++++++++
> include/hw/ppc/ppc4xx.h | 11 +++++
> 4 files changed, 105 insertions(+), 104 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index 31c94e4742..d85c595f9d 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -63,17 +63,6 @@ struct ppc4xx_bd_info_t {
> uint32_t bi_iic_fast[2];
> };
>
> -/* Peripheral local bus arbitrer */
> -#define TYPE_PPC405_PLB "ppc405-plb"
> -OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PlbState, PPC405_PLB);
> -struct Ppc405PlbState {
> - Ppc4xxDcrDeviceState parent_obj;
> -
> - uint32_t acr;
> - uint32_t bear;
> - uint32_t besr;
> -};
> -
> /* PLB to OPB bridge */
> #define TYPE_PPC405_POB "ppc405-pob"
> OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index 922c23346f..3de6c77631 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -137,94 +137,6 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size)
> /*****************************************************************************/
> /* Shared peripherals */
>
> -/*****************************************************************************/
> -/* Peripheral local bus arbitrer */
> -enum {
> - PLB3A0_ACR = 0x077,
> - PLB4A0_ACR = 0x081,
> - PLB0_BESR = 0x084,
> - PLB0_BEAR = 0x086,
> - PLB0_ACR = 0x087,
> - PLB4A1_ACR = 0x089,
> -};
> -
> -static uint32_t dcr_read_plb(void *opaque, int dcrn)
> -{
> - Ppc405PlbState *plb = opaque;
> - uint32_t ret;
> -
> - switch (dcrn) {
> - case PLB0_ACR:
> - ret = plb->acr;
> - break;
> - case PLB0_BEAR:
> - ret = plb->bear;
> - break;
> - case PLB0_BESR:
> - ret = plb->besr;
> - break;
> - default:
> - /* Avoid gcc warning */
> - ret = 0;
> - break;
> - }
> -
> - return ret;
> -}
> -
> -static void dcr_write_plb(void *opaque, int dcrn, uint32_t val)
> -{
> - Ppc405PlbState *plb = opaque;
> -
> - switch (dcrn) {
> - case PLB0_ACR:
> - /* We don't care about the actual parameters written as
> - * we don't manage any priorities on the bus
> - */
> - plb->acr = val & 0xF8000000;
> - break;
> - case PLB0_BEAR:
> - /* Read only */
> - break;
> - case PLB0_BESR:
> - /* Write-clear */
> - plb->besr &= ~val;
> - break;
> - }
> -}
> -
> -static void ppc405_plb_reset(DeviceState *dev)
> -{
> - Ppc405PlbState *plb = PPC405_PLB(dev);
> -
> - plb->acr = 0x00000000;
> - plb->bear = 0x00000000;
> - plb->besr = 0x00000000;
> -}
> -
> -static void ppc405_plb_realize(DeviceState *dev, Error **errp)
> -{
> - Ppc405PlbState *plb = PPC405_PLB(dev);
> - Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
> -
> - ppc4xx_dcr_register(dcr, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
> - ppc4xx_dcr_register(dcr, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
> - ppc4xx_dcr_register(dcr, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
> - ppc4xx_dcr_register(dcr, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
> - ppc4xx_dcr_register(dcr, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
> - ppc4xx_dcr_register(dcr, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb);
> -}
> -
> -static void ppc405_plb_class_init(ObjectClass *oc, void *data)
> -{
> - DeviceClass *dc = DEVICE_CLASS(oc);
> -
> - dc->realize = ppc405_plb_realize;
> - dc->reset = ppc405_plb_reset;
> - /* Reason: only works as function of a ppc4xx SoC */
> - dc->user_creatable = false;
> -}
> -
> /*****************************************************************************/
> /* PLB to OPB bridge */
> enum {
> @@ -1535,11 +1447,6 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
>
> static const TypeInfo ppc405_types[] = {
> {
> - .name = TYPE_PPC405_PLB,
> - .parent = TYPE_PPC4xx_DCR_DEVICE,
> - .instance_size = sizeof(Ppc405PlbState),
> - .class_init = ppc405_plb_class_init,
> - }, {
> .name = TYPE_PPC405_POB,
> .parent = TYPE_PPC4xx_DCR_DEVICE,
> .instance_size = sizeof(Ppc405PobState),
> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
> index 7d40c1b68a..843d759b1b 100644
> --- a/hw/ppc/ppc4xx_devs.c
> +++ b/hw/ppc/ppc4xx_devs.c
> @@ -658,6 +658,95 @@ static void ppc4xx_mal_class_init(ObjectClass *oc, void *data)
> device_class_set_props(dc, ppc4xx_mal_properties);
> }
>
> +/*****************************************************************************/
> +/* Peripheral local bus arbitrer */
> +enum {
> + PLB3A0_ACR = 0x077,
> + PLB4A0_ACR = 0x081,
> + PLB0_BESR = 0x084,
> + PLB0_BEAR = 0x086,
> + PLB0_ACR = 0x087,
> + PLB4A1_ACR = 0x089,
> +};
> +
> +static uint32_t dcr_read_plb(void *opaque, int dcrn)
> +{
> + Ppc405PlbState *plb = opaque;
> + uint32_t ret;
> +
> + switch (dcrn) {
> + case PLB0_ACR:
> + ret = plb->acr;
> + break;
> + case PLB0_BEAR:
> + ret = plb->bear;
> + break;
> + case PLB0_BESR:
> + ret = plb->besr;
> + break;
> + default:
> + /* Avoid gcc warning */
> + ret = 0;
> + break;
> + }
> +
> + return ret;
> +}
> +
> +static void dcr_write_plb(void *opaque, int dcrn, uint32_t val)
> +{
> + Ppc405PlbState *plb = opaque;
> +
> + switch (dcrn) {
> + case PLB0_ACR:
> + /*
> + * We don't care about the actual parameters written as
> + * we don't manage any priorities on the bus
> + */
> + plb->acr = val & 0xF8000000;
> + break;
> + case PLB0_BEAR:
> + /* Read only */
> + break;
> + case PLB0_BESR:
> + /* Write-clear */
> + plb->besr &= ~val;
> + break;
> + }
> +}
> +
> +static void ppc405_plb_reset(DeviceState *dev)
> +{
> + Ppc405PlbState *plb = PPC405_PLB(dev);
> +
> + plb->acr = 0x00000000;
> + plb->bear = 0x00000000;
> + plb->besr = 0x00000000;
> +}
> +
> +static void ppc405_plb_realize(DeviceState *dev, Error **errp)
> +{
> + Ppc405PlbState *plb = PPC405_PLB(dev);
> + Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
> +
> + ppc4xx_dcr_register(dcr, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
> + ppc4xx_dcr_register(dcr, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
> + ppc4xx_dcr_register(dcr, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
> + ppc4xx_dcr_register(dcr, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
> + ppc4xx_dcr_register(dcr, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
> + ppc4xx_dcr_register(dcr, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb);
> +}
> +
> +static void ppc405_plb_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = ppc405_plb_realize;
> + dc->reset = ppc405_plb_reset;
> + /* Reason: only works as function of a ppc4xx SoC */
> + dc->user_creatable = false;
> +}
> +
> /* PPC4xx_DCR_DEVICE */
>
> void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
> @@ -694,6 +783,11 @@ static const TypeInfo ppc4xx_types[] = {
> .instance_size = sizeof(Ppc4xxMalState),
> .instance_finalize = ppc4xx_mal_finalize,
> .class_init = ppc4xx_mal_class_init,
> + }, {
> + .name = TYPE_PPC405_PLB,
> + .parent = TYPE_PPC4xx_DCR_DEVICE,
> + .instance_size = sizeof(Ppc405PlbState),
> + .class_init = ppc405_plb_class_init,
> }, {
> .name = TYPE_PPC4xx_DCR_DEVICE,
> .parent = TYPE_SYS_BUS_DEVICE,
> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
> index f40bd49bc7..e696e159f3 100644
> --- a/include/hw/ppc/ppc4xx.h
> +++ b/include/hw/ppc/ppc4xx.h
> @@ -83,4 +83,15 @@ struct Ppc4xxMalState {
> uint8_t rxcnum;
> };
>
> +/* Peripheral local bus arbitrer */
> +#define TYPE_PPC405_PLB "ppc405-plb"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PlbState, PPC405_PLB);
> +struct Ppc405PlbState {
> + Ppc4xxDcrDeviceState parent_obj;
> +
> + uint32_t acr;
> + uint32_t bear;
> + uint32_t besr;
> +};
> +
> #endif /* PPC4XX_H */
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 12/22] ppc4xx: Move PLB model to ppc4xx_devs.c
2022-08-16 7:34 ` Cédric Le Goater
@ 2022-08-16 9:35 ` BALATON Zoltan
0 siblings, 0 replies; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-16 9:35 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 9263 bytes --]
On Tue, 16 Aug 2022, Cédric Le Goater wrote:
> On 8/13/22 17:34, BALATON Zoltan wrote:
>> The PLB is shared between 405 and 440 so move it to the shared file.
>
> Should we rename the device to Ppc4xxPlbState ?
I could do that (also for the other one moved). Ptobably nothing in these
boards care about the names so it shouldn't break anything.
Regards,
BALATON Zoltan
> Thanks,
>
> C.
>
>>
>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>> ---
>> hw/ppc/ppc405.h | 11 -----
>> hw/ppc/ppc405_uc.c | 93 ----------------------------------------
>> hw/ppc/ppc4xx_devs.c | 94 +++++++++++++++++++++++++++++++++++++++++
>> include/hw/ppc/ppc4xx.h | 11 +++++
>> 4 files changed, 105 insertions(+), 104 deletions(-)
>>
>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>> index 31c94e4742..d85c595f9d 100644
>> --- a/hw/ppc/ppc405.h
>> +++ b/hw/ppc/ppc405.h
>> @@ -63,17 +63,6 @@ struct ppc4xx_bd_info_t {
>> uint32_t bi_iic_fast[2];
>> };
>> -/* Peripheral local bus arbitrer */
>> -#define TYPE_PPC405_PLB "ppc405-plb"
>> -OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PlbState, PPC405_PLB);
>> -struct Ppc405PlbState {
>> - Ppc4xxDcrDeviceState parent_obj;
>> -
>> - uint32_t acr;
>> - uint32_t bear;
>> - uint32_t besr;
>> -};
>> -
>> /* PLB to OPB bridge */
>> #define TYPE_PPC405_POB "ppc405-pob"
>> OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
>> index 922c23346f..3de6c77631 100644
>> --- a/hw/ppc/ppc405_uc.c
>> +++ b/hw/ppc/ppc405_uc.c
>> @@ -137,94 +137,6 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env,
>> ram_addr_t ram_size)
>> /*****************************************************************************/
>> /* Shared peripherals */
>>
>> -/*****************************************************************************/
>> -/* Peripheral local bus arbitrer */
>> -enum {
>> - PLB3A0_ACR = 0x077,
>> - PLB4A0_ACR = 0x081,
>> - PLB0_BESR = 0x084,
>> - PLB0_BEAR = 0x086,
>> - PLB0_ACR = 0x087,
>> - PLB4A1_ACR = 0x089,
>> -};
>> -
>> -static uint32_t dcr_read_plb(void *opaque, int dcrn)
>> -{
>> - Ppc405PlbState *plb = opaque;
>> - uint32_t ret;
>> -
>> - switch (dcrn) {
>> - case PLB0_ACR:
>> - ret = plb->acr;
>> - break;
>> - case PLB0_BEAR:
>> - ret = plb->bear;
>> - break;
>> - case PLB0_BESR:
>> - ret = plb->besr;
>> - break;
>> - default:
>> - /* Avoid gcc warning */
>> - ret = 0;
>> - break;
>> - }
>> -
>> - return ret;
>> -}
>> -
>> -static void dcr_write_plb(void *opaque, int dcrn, uint32_t val)
>> -{
>> - Ppc405PlbState *plb = opaque;
>> -
>> - switch (dcrn) {
>> - case PLB0_ACR:
>> - /* We don't care about the actual parameters written as
>> - * we don't manage any priorities on the bus
>> - */
>> - plb->acr = val & 0xF8000000;
>> - break;
>> - case PLB0_BEAR:
>> - /* Read only */
>> - break;
>> - case PLB0_BESR:
>> - /* Write-clear */
>> - plb->besr &= ~val;
>> - break;
>> - }
>> -}
>> -
>> -static void ppc405_plb_reset(DeviceState *dev)
>> -{
>> - Ppc405PlbState *plb = PPC405_PLB(dev);
>> -
>> - plb->acr = 0x00000000;
>> - plb->bear = 0x00000000;
>> - plb->besr = 0x00000000;
>> -}
>> -
>> -static void ppc405_plb_realize(DeviceState *dev, Error **errp)
>> -{
>> - Ppc405PlbState *plb = PPC405_PLB(dev);
>> - Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
>> -
>> - ppc4xx_dcr_register(dcr, PLB3A0_ACR, plb, &dcr_read_plb,
>> &dcr_write_plb);
>> - ppc4xx_dcr_register(dcr, PLB4A0_ACR, plb, &dcr_read_plb,
>> &dcr_write_plb);
>> - ppc4xx_dcr_register(dcr, PLB0_ACR, plb, &dcr_read_plb,
>> &dcr_write_plb);
>> - ppc4xx_dcr_register(dcr, PLB0_BEAR, plb, &dcr_read_plb,
>> &dcr_write_plb);
>> - ppc4xx_dcr_register(dcr, PLB0_BESR, plb, &dcr_read_plb,
>> &dcr_write_plb);
>> - ppc4xx_dcr_register(dcr, PLB4A1_ACR, plb, &dcr_read_plb,
>> &dcr_write_plb);
>> -}
>> -
>> -static void ppc405_plb_class_init(ObjectClass *oc, void *data)
>> -{
>> - DeviceClass *dc = DEVICE_CLASS(oc);
>> -
>> - dc->realize = ppc405_plb_realize;
>> - dc->reset = ppc405_plb_reset;
>> - /* Reason: only works as function of a ppc4xx SoC */
>> - dc->user_creatable = false;
>> -}
>> -
>> /*****************************************************************************/
>> /* PLB to OPB bridge */
>> enum {
>> @@ -1535,11 +1447,6 @@ static void ppc405_soc_class_init(ObjectClass *oc,
>> void *data)
>> static const TypeInfo ppc405_types[] = {
>> {
>> - .name = TYPE_PPC405_PLB,
>> - .parent = TYPE_PPC4xx_DCR_DEVICE,
>> - .instance_size = sizeof(Ppc405PlbState),
>> - .class_init = ppc405_plb_class_init,
>> - }, {
>> .name = TYPE_PPC405_POB,
>> .parent = TYPE_PPC4xx_DCR_DEVICE,
>> .instance_size = sizeof(Ppc405PobState),
>> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
>> index 7d40c1b68a..843d759b1b 100644
>> --- a/hw/ppc/ppc4xx_devs.c
>> +++ b/hw/ppc/ppc4xx_devs.c
>> @@ -658,6 +658,95 @@ static void ppc4xx_mal_class_init(ObjectClass *oc,
>> void *data)
>> device_class_set_props(dc, ppc4xx_mal_properties);
>> }
>> +/*****************************************************************************/
>> +/* Peripheral local bus arbitrer */
>> +enum {
>> + PLB3A0_ACR = 0x077,
>> + PLB4A0_ACR = 0x081,
>> + PLB0_BESR = 0x084,
>> + PLB0_BEAR = 0x086,
>> + PLB0_ACR = 0x087,
>> + PLB4A1_ACR = 0x089,
>> +};
>> +
>> +static uint32_t dcr_read_plb(void *opaque, int dcrn)
>> +{
>> + Ppc405PlbState *plb = opaque;
>> + uint32_t ret;
>> +
>> + switch (dcrn) {
>> + case PLB0_ACR:
>> + ret = plb->acr;
>> + break;
>> + case PLB0_BEAR:
>> + ret = plb->bear;
>> + break;
>> + case PLB0_BESR:
>> + ret = plb->besr;
>> + break;
>> + default:
>> + /* Avoid gcc warning */
>> + ret = 0;
>> + break;
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +static void dcr_write_plb(void *opaque, int dcrn, uint32_t val)
>> +{
>> + Ppc405PlbState *plb = opaque;
>> +
>> + switch (dcrn) {
>> + case PLB0_ACR:
>> + /*
>> + * We don't care about the actual parameters written as
>> + * we don't manage any priorities on the bus
>> + */
>> + plb->acr = val & 0xF8000000;
>> + break;
>> + case PLB0_BEAR:
>> + /* Read only */
>> + break;
>> + case PLB0_BESR:
>> + /* Write-clear */
>> + plb->besr &= ~val;
>> + break;
>> + }
>> +}
>> +
>> +static void ppc405_plb_reset(DeviceState *dev)
>> +{
>> + Ppc405PlbState *plb = PPC405_PLB(dev);
>> +
>> + plb->acr = 0x00000000;
>> + plb->bear = 0x00000000;
>> + plb->besr = 0x00000000;
>> +}
>> +
>> +static void ppc405_plb_realize(DeviceState *dev, Error **errp)
>> +{
>> + Ppc405PlbState *plb = PPC405_PLB(dev);
>> + Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
>> +
>> + ppc4xx_dcr_register(dcr, PLB3A0_ACR, plb, &dcr_read_plb,
>> &dcr_write_plb);
>> + ppc4xx_dcr_register(dcr, PLB4A0_ACR, plb, &dcr_read_plb,
>> &dcr_write_plb);
>> + ppc4xx_dcr_register(dcr, PLB0_ACR, plb, &dcr_read_plb,
>> &dcr_write_plb);
>> + ppc4xx_dcr_register(dcr, PLB0_BEAR, plb, &dcr_read_plb,
>> &dcr_write_plb);
>> + ppc4xx_dcr_register(dcr, PLB0_BESR, plb, &dcr_read_plb,
>> &dcr_write_plb);
>> + ppc4xx_dcr_register(dcr, PLB4A1_ACR, plb, &dcr_read_plb,
>> &dcr_write_plb);
>> +}
>> +
>> +static void ppc405_plb_class_init(ObjectClass *oc, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(oc);
>> +
>> + dc->realize = ppc405_plb_realize;
>> + dc->reset = ppc405_plb_reset;
>> + /* Reason: only works as function of a ppc4xx SoC */
>> + dc->user_creatable = false;
>> +}
>> +
>> /* PPC4xx_DCR_DEVICE */
>> void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void
>> *opaque,
>> @@ -694,6 +783,11 @@ static const TypeInfo ppc4xx_types[] = {
>> .instance_size = sizeof(Ppc4xxMalState),
>> .instance_finalize = ppc4xx_mal_finalize,
>> .class_init = ppc4xx_mal_class_init,
>> + }, {
>> + .name = TYPE_PPC405_PLB,
>> + .parent = TYPE_PPC4xx_DCR_DEVICE,
>> + .instance_size = sizeof(Ppc405PlbState),
>> + .class_init = ppc405_plb_class_init,
>> }, {
>> .name = TYPE_PPC4xx_DCR_DEVICE,
>> .parent = TYPE_SYS_BUS_DEVICE,
>> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
>> index f40bd49bc7..e696e159f3 100644
>> --- a/include/hw/ppc/ppc4xx.h
>> +++ b/include/hw/ppc/ppc4xx.h
>> @@ -83,4 +83,15 @@ struct Ppc4xxMalState {
>> uint8_t rxcnum;
>> };
>> +/* Peripheral local bus arbitrer */
>> +#define TYPE_PPC405_PLB "ppc405-plb"
>> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PlbState, PPC405_PLB);
>> +struct Ppc405PlbState {
>> + Ppc4xxDcrDeviceState parent_obj;
>> +
>> + uint32_t acr;
>> + uint32_t bear;
>> + uint32_t besr;
>> +};
>> +
>> #endif /* PPC4XX_H */
>
>
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 13/22] ppc4xx: Move EBC model to ppc4xx_devs.c
2022-08-13 15:34 [PATCH 00/22] QOMify PPC4xx devices and minor clean ups BALATON Zoltan
` (11 preceding siblings ...)
2022-08-13 15:34 ` [PATCH 12/22] ppc4xx: Move PLB model to ppc4xx_devs.c BALATON Zoltan
@ 2022-08-13 15:34 ` BALATON Zoltan
2022-08-16 7:35 ` Cédric Le Goater
2022-08-13 15:34 ` [PATCH 14/22] ppc/ppc405: Use an embedded PPCUIC model in SoC state BALATON Zoltan
` (9 subsequent siblings)
22 siblings, 1 reply; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-13 15:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
The EBC is shared between 405 and 440 so move it to shared file.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc405.h | 15 ----
hw/ppc/ppc405_uc.c | 191 ----------------------------------------
hw/ppc/ppc4xx_devs.c | 191 ++++++++++++++++++++++++++++++++++++++++
include/hw/ppc/ppc4xx.h | 15 ++++
4 files changed, 206 insertions(+), 206 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index d85c595f9d..c0251f0894 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -85,21 +85,6 @@ struct Ppc405OpbaState {
uint8_t pr;
};
-/* Peripheral controller */
-#define TYPE_PPC405_EBC "ppc405-ebc"
-OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC);
-struct Ppc405EbcState {
- Ppc4xxDcrDeviceState parent_obj;
-
- uint32_t addr;
- uint32_t bcr[8];
- uint32_t bap[8];
- uint32_t bear;
- uint32_t besr0;
- uint32_t besr1;
- uint32_t cfg;
-};
-
/* DMA controller */
#define TYPE_PPC405_DMA "ppc405-dma"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA);
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 3de6c77631..01625e3237 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -299,192 +299,6 @@ static void ppc405_opba_class_init(ObjectClass *oc, void *data)
/* Code decompression controller */
/* XXX: TODO */
-/*****************************************************************************/
-/* Peripheral controller */
-enum {
- EBC0_CFGADDR = 0x012,
- EBC0_CFGDATA = 0x013,
-};
-
-static uint32_t dcr_read_ebc(void *opaque, int dcrn)
-{
- Ppc405EbcState *ebc = opaque;
- uint32_t ret;
-
- switch (dcrn) {
- case EBC0_CFGADDR:
- ret = ebc->addr;
- break;
- case EBC0_CFGDATA:
- switch (ebc->addr) {
- case 0x00: /* B0CR */
- ret = ebc->bcr[0];
- break;
- case 0x01: /* B1CR */
- ret = ebc->bcr[1];
- break;
- case 0x02: /* B2CR */
- ret = ebc->bcr[2];
- break;
- case 0x03: /* B3CR */
- ret = ebc->bcr[3];
- break;
- case 0x04: /* B4CR */
- ret = ebc->bcr[4];
- break;
- case 0x05: /* B5CR */
- ret = ebc->bcr[5];
- break;
- case 0x06: /* B6CR */
- ret = ebc->bcr[6];
- break;
- case 0x07: /* B7CR */
- ret = ebc->bcr[7];
- break;
- case 0x10: /* B0AP */
- ret = ebc->bap[0];
- break;
- case 0x11: /* B1AP */
- ret = ebc->bap[1];
- break;
- case 0x12: /* B2AP */
- ret = ebc->bap[2];
- break;
- case 0x13: /* B3AP */
- ret = ebc->bap[3];
- break;
- case 0x14: /* B4AP */
- ret = ebc->bap[4];
- break;
- case 0x15: /* B5AP */
- ret = ebc->bap[5];
- break;
- case 0x16: /* B6AP */
- ret = ebc->bap[6];
- break;
- case 0x17: /* B7AP */
- ret = ebc->bap[7];
- break;
- case 0x20: /* BEAR */
- ret = ebc->bear;
- break;
- case 0x21: /* BESR0 */
- ret = ebc->besr0;
- break;
- case 0x22: /* BESR1 */
- ret = ebc->besr1;
- break;
- case 0x23: /* CFG */
- ret = ebc->cfg;
- break;
- default:
- ret = 0x00000000;
- break;
- }
- break;
- default:
- ret = 0x00000000;
- break;
- }
-
- return ret;
-}
-
-static void dcr_write_ebc(void *opaque, int dcrn, uint32_t val)
-{
- Ppc405EbcState *ebc = opaque;
-
- switch (dcrn) {
- case EBC0_CFGADDR:
- ebc->addr = val;
- break;
- case EBC0_CFGDATA:
- switch (ebc->addr) {
- case 0x00: /* B0CR */
- break;
- case 0x01: /* B1CR */
- break;
- case 0x02: /* B2CR */
- break;
- case 0x03: /* B3CR */
- break;
- case 0x04: /* B4CR */
- break;
- case 0x05: /* B5CR */
- break;
- case 0x06: /* B6CR */
- break;
- case 0x07: /* B7CR */
- break;
- case 0x10: /* B0AP */
- break;
- case 0x11: /* B1AP */
- break;
- case 0x12: /* B2AP */
- break;
- case 0x13: /* B3AP */
- break;
- case 0x14: /* B4AP */
- break;
- case 0x15: /* B5AP */
- break;
- case 0x16: /* B6AP */
- break;
- case 0x17: /* B7AP */
- break;
- case 0x20: /* BEAR */
- break;
- case 0x21: /* BESR0 */
- break;
- case 0x22: /* BESR1 */
- break;
- case 0x23: /* CFG */
- break;
- default:
- break;
- }
- break;
- default:
- break;
- }
-}
-
-static void ppc405_ebc_reset(DeviceState *dev)
-{
- Ppc405EbcState *ebc = PPC405_EBC(dev);
- int i;
-
- ebc->addr = 0x00000000;
- ebc->bap[0] = 0x7F8FFE80;
- ebc->bcr[0] = 0xFFE28000;
- for (i = 0; i < 8; i++) {
- ebc->bap[i] = 0x00000000;
- ebc->bcr[i] = 0x00000000;
- }
- ebc->besr0 = 0x00000000;
- ebc->besr1 = 0x00000000;
- ebc->cfg = 0x80400000;
-}
-
-static void ppc405_ebc_realize(DeviceState *dev, Error **errp)
-{
- Ppc405EbcState *ebc = PPC405_EBC(dev);
- Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
-
- ppc4xx_dcr_register(dcr, EBC0_CFGADDR, ebc, &dcr_read_ebc, &dcr_write_ebc);
- ppc4xx_dcr_register(dcr, EBC0_CFGDATA, ebc, &dcr_read_ebc, &dcr_write_ebc);
-}
-
-static void ppc405_ebc_class_init(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
-
- dc->realize = ppc405_ebc_realize;
- dc->reset = ppc405_ebc_reset;
- /* Reason: only works as function of a ppc4xx SoC */
- dc->user_creatable = false;
-}
-
/*****************************************************************************/
/* DMA controller */
enum {
@@ -1456,11 +1270,6 @@ static const TypeInfo ppc405_types[] = {
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Ppc405OpbaState),
.class_init = ppc405_opba_class_init,
- }, {
- .name = TYPE_PPC405_EBC,
- .parent = TYPE_PPC4xx_DCR_DEVICE,
- .instance_size = sizeof(Ppc405EbcState),
- .class_init = ppc405_ebc_class_init,
}, {
.name = TYPE_PPC405_DMA,
.parent = TYPE_PPC4xx_DCR_DEVICE,
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 843d759b1b..96941ae040 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -747,6 +747,192 @@ static void ppc405_plb_class_init(ObjectClass *oc, void *data)
dc->user_creatable = false;
}
+/*****************************************************************************/
+/* Peripheral controller */
+enum {
+ EBC0_CFGADDR = 0x012,
+ EBC0_CFGDATA = 0x013,
+};
+
+static uint32_t dcr_read_ebc(void *opaque, int dcrn)
+{
+ Ppc405EbcState *ebc = opaque;
+ uint32_t ret;
+
+ switch (dcrn) {
+ case EBC0_CFGADDR:
+ ret = ebc->addr;
+ break;
+ case EBC0_CFGDATA:
+ switch (ebc->addr) {
+ case 0x00: /* B0CR */
+ ret = ebc->bcr[0];
+ break;
+ case 0x01: /* B1CR */
+ ret = ebc->bcr[1];
+ break;
+ case 0x02: /* B2CR */
+ ret = ebc->bcr[2];
+ break;
+ case 0x03: /* B3CR */
+ ret = ebc->bcr[3];
+ break;
+ case 0x04: /* B4CR */
+ ret = ebc->bcr[4];
+ break;
+ case 0x05: /* B5CR */
+ ret = ebc->bcr[5];
+ break;
+ case 0x06: /* B6CR */
+ ret = ebc->bcr[6];
+ break;
+ case 0x07: /* B7CR */
+ ret = ebc->bcr[7];
+ break;
+ case 0x10: /* B0AP */
+ ret = ebc->bap[0];
+ break;
+ case 0x11: /* B1AP */
+ ret = ebc->bap[1];
+ break;
+ case 0x12: /* B2AP */
+ ret = ebc->bap[2];
+ break;
+ case 0x13: /* B3AP */
+ ret = ebc->bap[3];
+ break;
+ case 0x14: /* B4AP */
+ ret = ebc->bap[4];
+ break;
+ case 0x15: /* B5AP */
+ ret = ebc->bap[5];
+ break;
+ case 0x16: /* B6AP */
+ ret = ebc->bap[6];
+ break;
+ case 0x17: /* B7AP */
+ ret = ebc->bap[7];
+ break;
+ case 0x20: /* BEAR */
+ ret = ebc->bear;
+ break;
+ case 0x21: /* BESR0 */
+ ret = ebc->besr0;
+ break;
+ case 0x22: /* BESR1 */
+ ret = ebc->besr1;
+ break;
+ case 0x23: /* CFG */
+ ret = ebc->cfg;
+ break;
+ default:
+ ret = 0x00000000;
+ break;
+ }
+ break;
+ default:
+ ret = 0x00000000;
+ break;
+ }
+
+ return ret;
+}
+
+static void dcr_write_ebc(void *opaque, int dcrn, uint32_t val)
+{
+ Ppc405EbcState *ebc = opaque;
+
+ switch (dcrn) {
+ case EBC0_CFGADDR:
+ ebc->addr = val;
+ break;
+ case EBC0_CFGDATA:
+ switch (ebc->addr) {
+ case 0x00: /* B0CR */
+ break;
+ case 0x01: /* B1CR */
+ break;
+ case 0x02: /* B2CR */
+ break;
+ case 0x03: /* B3CR */
+ break;
+ case 0x04: /* B4CR */
+ break;
+ case 0x05: /* B5CR */
+ break;
+ case 0x06: /* B6CR */
+ break;
+ case 0x07: /* B7CR */
+ break;
+ case 0x10: /* B0AP */
+ break;
+ case 0x11: /* B1AP */
+ break;
+ case 0x12: /* B2AP */
+ break;
+ case 0x13: /* B3AP */
+ break;
+ case 0x14: /* B4AP */
+ break;
+ case 0x15: /* B5AP */
+ break;
+ case 0x16: /* B6AP */
+ break;
+ case 0x17: /* B7AP */
+ break;
+ case 0x20: /* BEAR */
+ break;
+ case 0x21: /* BESR0 */
+ break;
+ case 0x22: /* BESR1 */
+ break;
+ case 0x23: /* CFG */
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+static void ppc405_ebc_reset(DeviceState *dev)
+{
+ Ppc405EbcState *ebc = PPC405_EBC(dev);
+ int i;
+
+ ebc->addr = 0x00000000;
+ ebc->bap[0] = 0x7F8FFE80;
+ ebc->bcr[0] = 0xFFE28000;
+ for (i = 0; i < 8; i++) {
+ ebc->bap[i] = 0x00000000;
+ ebc->bcr[i] = 0x00000000;
+ }
+ ebc->besr0 = 0x00000000;
+ ebc->besr1 = 0x00000000;
+ ebc->cfg = 0x80400000;
+}
+
+static void ppc405_ebc_realize(DeviceState *dev, Error **errp)
+{
+ Ppc405EbcState *ebc = PPC405_EBC(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
+
+ ppc4xx_dcr_register(dcr, EBC0_CFGADDR, ebc, &dcr_read_ebc, &dcr_write_ebc);
+ ppc4xx_dcr_register(dcr, EBC0_CFGDATA, ebc, &dcr_read_ebc, &dcr_write_ebc);
+}
+
+static void ppc405_ebc_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_ebc_realize;
+ dc->reset = ppc405_ebc_reset;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
+}
+
/* PPC4xx_DCR_DEVICE */
void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
@@ -788,6 +974,11 @@ static const TypeInfo ppc4xx_types[] = {
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc405PlbState),
.class_init = ppc405_plb_class_init,
+ }, {
+ .name = TYPE_PPC405_EBC,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc405EbcState),
+ .class_init = ppc405_ebc_class_init,
}, {
.name = TYPE_PPC4xx_DCR_DEVICE,
.parent = TYPE_SYS_BUS_DEVICE,
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index e696e159f3..6e361cf254 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -94,4 +94,19 @@ struct Ppc405PlbState {
uint32_t besr;
};
+/* Peripheral controller */
+#define TYPE_PPC405_EBC "ppc405-ebc"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC);
+struct Ppc405EbcState {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ uint32_t addr;
+ uint32_t bcr[8];
+ uint32_t bap[8];
+ uint32_t bear;
+ uint32_t besr0;
+ uint32_t besr1;
+ uint32_t cfg;
+};
+
#endif /* PPC4XX_H */
--
2.30.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH 13/22] ppc4xx: Move EBC model to ppc4xx_devs.c
2022-08-13 15:34 ` [PATCH 13/22] ppc4xx: Move EBC " BALATON Zoltan
@ 2022-08-16 7:35 ` Cédric Le Goater
0 siblings, 0 replies; 37+ messages in thread
From: Cédric Le Goater @ 2022-08-16 7:35 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc
Cc: Daniel Henrique Barboza, Peter Maydell
On 8/13/22 17:34, BALATON Zoltan wrote:
> The EBC is shared between 405 and 440 so move it to shared file.
Should we rename the device to Ppc4xxEbcState ?
Thanks,
C.
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> hw/ppc/ppc405.h | 15 ----
> hw/ppc/ppc405_uc.c | 191 ----------------------------------------
> hw/ppc/ppc4xx_devs.c | 191 ++++++++++++++++++++++++++++++++++++++++
> include/hw/ppc/ppc4xx.h | 15 ++++
> 4 files changed, 206 insertions(+), 206 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index d85c595f9d..c0251f0894 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -85,21 +85,6 @@ struct Ppc405OpbaState {
> uint8_t pr;
> };
>
> -/* Peripheral controller */
> -#define TYPE_PPC405_EBC "ppc405-ebc"
> -OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC);
> -struct Ppc405EbcState {
> - Ppc4xxDcrDeviceState parent_obj;
> -
> - uint32_t addr;
> - uint32_t bcr[8];
> - uint32_t bap[8];
> - uint32_t bear;
> - uint32_t besr0;
> - uint32_t besr1;
> - uint32_t cfg;
> -};
> -
> /* DMA controller */
> #define TYPE_PPC405_DMA "ppc405-dma"
> OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA);
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index 3de6c77631..01625e3237 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -299,192 +299,6 @@ static void ppc405_opba_class_init(ObjectClass *oc, void *data)
> /* Code decompression controller */
> /* XXX: TODO */
>
> -/*****************************************************************************/
> -/* Peripheral controller */
> -enum {
> - EBC0_CFGADDR = 0x012,
> - EBC0_CFGDATA = 0x013,
> -};
> -
> -static uint32_t dcr_read_ebc(void *opaque, int dcrn)
> -{
> - Ppc405EbcState *ebc = opaque;
> - uint32_t ret;
> -
> - switch (dcrn) {
> - case EBC0_CFGADDR:
> - ret = ebc->addr;
> - break;
> - case EBC0_CFGDATA:
> - switch (ebc->addr) {
> - case 0x00: /* B0CR */
> - ret = ebc->bcr[0];
> - break;
> - case 0x01: /* B1CR */
> - ret = ebc->bcr[1];
> - break;
> - case 0x02: /* B2CR */
> - ret = ebc->bcr[2];
> - break;
> - case 0x03: /* B3CR */
> - ret = ebc->bcr[3];
> - break;
> - case 0x04: /* B4CR */
> - ret = ebc->bcr[4];
> - break;
> - case 0x05: /* B5CR */
> - ret = ebc->bcr[5];
> - break;
> - case 0x06: /* B6CR */
> - ret = ebc->bcr[6];
> - break;
> - case 0x07: /* B7CR */
> - ret = ebc->bcr[7];
> - break;
> - case 0x10: /* B0AP */
> - ret = ebc->bap[0];
> - break;
> - case 0x11: /* B1AP */
> - ret = ebc->bap[1];
> - break;
> - case 0x12: /* B2AP */
> - ret = ebc->bap[2];
> - break;
> - case 0x13: /* B3AP */
> - ret = ebc->bap[3];
> - break;
> - case 0x14: /* B4AP */
> - ret = ebc->bap[4];
> - break;
> - case 0x15: /* B5AP */
> - ret = ebc->bap[5];
> - break;
> - case 0x16: /* B6AP */
> - ret = ebc->bap[6];
> - break;
> - case 0x17: /* B7AP */
> - ret = ebc->bap[7];
> - break;
> - case 0x20: /* BEAR */
> - ret = ebc->bear;
> - break;
> - case 0x21: /* BESR0 */
> - ret = ebc->besr0;
> - break;
> - case 0x22: /* BESR1 */
> - ret = ebc->besr1;
> - break;
> - case 0x23: /* CFG */
> - ret = ebc->cfg;
> - break;
> - default:
> - ret = 0x00000000;
> - break;
> - }
> - break;
> - default:
> - ret = 0x00000000;
> - break;
> - }
> -
> - return ret;
> -}
> -
> -static void dcr_write_ebc(void *opaque, int dcrn, uint32_t val)
> -{
> - Ppc405EbcState *ebc = opaque;
> -
> - switch (dcrn) {
> - case EBC0_CFGADDR:
> - ebc->addr = val;
> - break;
> - case EBC0_CFGDATA:
> - switch (ebc->addr) {
> - case 0x00: /* B0CR */
> - break;
> - case 0x01: /* B1CR */
> - break;
> - case 0x02: /* B2CR */
> - break;
> - case 0x03: /* B3CR */
> - break;
> - case 0x04: /* B4CR */
> - break;
> - case 0x05: /* B5CR */
> - break;
> - case 0x06: /* B6CR */
> - break;
> - case 0x07: /* B7CR */
> - break;
> - case 0x10: /* B0AP */
> - break;
> - case 0x11: /* B1AP */
> - break;
> - case 0x12: /* B2AP */
> - break;
> - case 0x13: /* B3AP */
> - break;
> - case 0x14: /* B4AP */
> - break;
> - case 0x15: /* B5AP */
> - break;
> - case 0x16: /* B6AP */
> - break;
> - case 0x17: /* B7AP */
> - break;
> - case 0x20: /* BEAR */
> - break;
> - case 0x21: /* BESR0 */
> - break;
> - case 0x22: /* BESR1 */
> - break;
> - case 0x23: /* CFG */
> - break;
> - default:
> - break;
> - }
> - break;
> - default:
> - break;
> - }
> -}
> -
> -static void ppc405_ebc_reset(DeviceState *dev)
> -{
> - Ppc405EbcState *ebc = PPC405_EBC(dev);
> - int i;
> -
> - ebc->addr = 0x00000000;
> - ebc->bap[0] = 0x7F8FFE80;
> - ebc->bcr[0] = 0xFFE28000;
> - for (i = 0; i < 8; i++) {
> - ebc->bap[i] = 0x00000000;
> - ebc->bcr[i] = 0x00000000;
> - }
> - ebc->besr0 = 0x00000000;
> - ebc->besr1 = 0x00000000;
> - ebc->cfg = 0x80400000;
> -}
> -
> -static void ppc405_ebc_realize(DeviceState *dev, Error **errp)
> -{
> - Ppc405EbcState *ebc = PPC405_EBC(dev);
> - Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
> -
> - ppc4xx_dcr_register(dcr, EBC0_CFGADDR, ebc, &dcr_read_ebc, &dcr_write_ebc);
> - ppc4xx_dcr_register(dcr, EBC0_CFGDATA, ebc, &dcr_read_ebc, &dcr_write_ebc);
> -}
> -
> -static void ppc405_ebc_class_init(ObjectClass *oc, void *data)
> -{
> - DeviceClass *dc = DEVICE_CLASS(oc);
> -
> - dc->realize = ppc405_ebc_realize;
> - dc->reset = ppc405_ebc_reset;
> - /* Reason: only works as function of a ppc4xx SoC */
> - dc->user_creatable = false;
> -}
> -
> /*****************************************************************************/
> /* DMA controller */
> enum {
> @@ -1456,11 +1270,6 @@ static const TypeInfo ppc405_types[] = {
> .parent = TYPE_SYS_BUS_DEVICE,
> .instance_size = sizeof(Ppc405OpbaState),
> .class_init = ppc405_opba_class_init,
> - }, {
> - .name = TYPE_PPC405_EBC,
> - .parent = TYPE_PPC4xx_DCR_DEVICE,
> - .instance_size = sizeof(Ppc405EbcState),
> - .class_init = ppc405_ebc_class_init,
> }, {
> .name = TYPE_PPC405_DMA,
> .parent = TYPE_PPC4xx_DCR_DEVICE,
> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
> index 843d759b1b..96941ae040 100644
> --- a/hw/ppc/ppc4xx_devs.c
> +++ b/hw/ppc/ppc4xx_devs.c
> @@ -747,6 +747,192 @@ static void ppc405_plb_class_init(ObjectClass *oc, void *data)
> dc->user_creatable = false;
> }
>
> +/*****************************************************************************/
> +/* Peripheral controller */
> +enum {
> + EBC0_CFGADDR = 0x012,
> + EBC0_CFGDATA = 0x013,
> +};
> +
> +static uint32_t dcr_read_ebc(void *opaque, int dcrn)
> +{
> + Ppc405EbcState *ebc = opaque;
> + uint32_t ret;
> +
> + switch (dcrn) {
> + case EBC0_CFGADDR:
> + ret = ebc->addr;
> + break;
> + case EBC0_CFGDATA:
> + switch (ebc->addr) {
> + case 0x00: /* B0CR */
> + ret = ebc->bcr[0];
> + break;
> + case 0x01: /* B1CR */
> + ret = ebc->bcr[1];
> + break;
> + case 0x02: /* B2CR */
> + ret = ebc->bcr[2];
> + break;
> + case 0x03: /* B3CR */
> + ret = ebc->bcr[3];
> + break;
> + case 0x04: /* B4CR */
> + ret = ebc->bcr[4];
> + break;
> + case 0x05: /* B5CR */
> + ret = ebc->bcr[5];
> + break;
> + case 0x06: /* B6CR */
> + ret = ebc->bcr[6];
> + break;
> + case 0x07: /* B7CR */
> + ret = ebc->bcr[7];
> + break;
> + case 0x10: /* B0AP */
> + ret = ebc->bap[0];
> + break;
> + case 0x11: /* B1AP */
> + ret = ebc->bap[1];
> + break;
> + case 0x12: /* B2AP */
> + ret = ebc->bap[2];
> + break;
> + case 0x13: /* B3AP */
> + ret = ebc->bap[3];
> + break;
> + case 0x14: /* B4AP */
> + ret = ebc->bap[4];
> + break;
> + case 0x15: /* B5AP */
> + ret = ebc->bap[5];
> + break;
> + case 0x16: /* B6AP */
> + ret = ebc->bap[6];
> + break;
> + case 0x17: /* B7AP */
> + ret = ebc->bap[7];
> + break;
> + case 0x20: /* BEAR */
> + ret = ebc->bear;
> + break;
> + case 0x21: /* BESR0 */
> + ret = ebc->besr0;
> + break;
> + case 0x22: /* BESR1 */
> + ret = ebc->besr1;
> + break;
> + case 0x23: /* CFG */
> + ret = ebc->cfg;
> + break;
> + default:
> + ret = 0x00000000;
> + break;
> + }
> + break;
> + default:
> + ret = 0x00000000;
> + break;
> + }
> +
> + return ret;
> +}
> +
> +static void dcr_write_ebc(void *opaque, int dcrn, uint32_t val)
> +{
> + Ppc405EbcState *ebc = opaque;
> +
> + switch (dcrn) {
> + case EBC0_CFGADDR:
> + ebc->addr = val;
> + break;
> + case EBC0_CFGDATA:
> + switch (ebc->addr) {
> + case 0x00: /* B0CR */
> + break;
> + case 0x01: /* B1CR */
> + break;
> + case 0x02: /* B2CR */
> + break;
> + case 0x03: /* B3CR */
> + break;
> + case 0x04: /* B4CR */
> + break;
> + case 0x05: /* B5CR */
> + break;
> + case 0x06: /* B6CR */
> + break;
> + case 0x07: /* B7CR */
> + break;
> + case 0x10: /* B0AP */
> + break;
> + case 0x11: /* B1AP */
> + break;
> + case 0x12: /* B2AP */
> + break;
> + case 0x13: /* B3AP */
> + break;
> + case 0x14: /* B4AP */
> + break;
> + case 0x15: /* B5AP */
> + break;
> + case 0x16: /* B6AP */
> + break;
> + case 0x17: /* B7AP */
> + break;
> + case 0x20: /* BEAR */
> + break;
> + case 0x21: /* BESR0 */
> + break;
> + case 0x22: /* BESR1 */
> + break;
> + case 0x23: /* CFG */
> + break;
> + default:
> + break;
> + }
> + break;
> + default:
> + break;
> + }
> +}
> +
> +static void ppc405_ebc_reset(DeviceState *dev)
> +{
> + Ppc405EbcState *ebc = PPC405_EBC(dev);
> + int i;
> +
> + ebc->addr = 0x00000000;
> + ebc->bap[0] = 0x7F8FFE80;
> + ebc->bcr[0] = 0xFFE28000;
> + for (i = 0; i < 8; i++) {
> + ebc->bap[i] = 0x00000000;
> + ebc->bcr[i] = 0x00000000;
> + }
> + ebc->besr0 = 0x00000000;
> + ebc->besr1 = 0x00000000;
> + ebc->cfg = 0x80400000;
> +}
> +
> +static void ppc405_ebc_realize(DeviceState *dev, Error **errp)
> +{
> + Ppc405EbcState *ebc = PPC405_EBC(dev);
> + Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
> +
> + ppc4xx_dcr_register(dcr, EBC0_CFGADDR, ebc, &dcr_read_ebc, &dcr_write_ebc);
> + ppc4xx_dcr_register(dcr, EBC0_CFGDATA, ebc, &dcr_read_ebc, &dcr_write_ebc);
> +}
> +
> +static void ppc405_ebc_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = ppc405_ebc_realize;
> + dc->reset = ppc405_ebc_reset;
> + /* Reason: only works as function of a ppc4xx SoC */
> + dc->user_creatable = false;
> +}
> +
> /* PPC4xx_DCR_DEVICE */
>
> void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
> @@ -788,6 +974,11 @@ static const TypeInfo ppc4xx_types[] = {
> .parent = TYPE_PPC4xx_DCR_DEVICE,
> .instance_size = sizeof(Ppc405PlbState),
> .class_init = ppc405_plb_class_init,
> + }, {
> + .name = TYPE_PPC405_EBC,
> + .parent = TYPE_PPC4xx_DCR_DEVICE,
> + .instance_size = sizeof(Ppc405EbcState),
> + .class_init = ppc405_ebc_class_init,
> }, {
> .name = TYPE_PPC4xx_DCR_DEVICE,
> .parent = TYPE_SYS_BUS_DEVICE,
> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
> index e696e159f3..6e361cf254 100644
> --- a/include/hw/ppc/ppc4xx.h
> +++ b/include/hw/ppc/ppc4xx.h
> @@ -94,4 +94,19 @@ struct Ppc405PlbState {
> uint32_t besr;
> };
>
> +/* Peripheral controller */
> +#define TYPE_PPC405_EBC "ppc405-ebc"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC);
> +struct Ppc405EbcState {
> + Ppc4xxDcrDeviceState parent_obj;
> +
> + uint32_t addr;
> + uint32_t bcr[8];
> + uint32_t bap[8];
> + uint32_t bear;
> + uint32_t besr0;
> + uint32_t besr1;
> + uint32_t cfg;
> +};
> +
> #endif /* PPC4XX_H */
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 14/22] ppc/ppc405: Use an embedded PPCUIC model in SoC state
2022-08-13 15:34 [PATCH 00/22] QOMify PPC4xx devices and minor clean ups BALATON Zoltan
` (12 preceding siblings ...)
2022-08-13 15:34 ` [PATCH 13/22] ppc4xx: Move EBC " BALATON Zoltan
@ 2022-08-13 15:34 ` BALATON Zoltan
2022-08-13 15:34 ` [PATCH 15/22] hw/intc/ppc-uic: Convert ppc-uic to a PPC4xx DCR device BALATON Zoltan
` (8 subsequent siblings)
22 siblings, 0 replies; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-13 15:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
From: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc405.h | 3 ++-
hw/ppc/ppc405_uc.c | 28 ++++++++++++++--------------
2 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index c0251f0894..5bcbce2893 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -27,6 +27,7 @@
#include "qom/object.h"
#include "hw/ppc/ppc4xx.h"
+#include "hw/intc/ppc-uic.h"
#define PPC405EP_SDRAM_BASE 0x00000000
#define PPC405EP_NVRAM_BASE 0xF0000000
@@ -208,7 +209,7 @@ struct Ppc405SoCState {
hwaddr ram_size;
PowerPCCPU cpu;
- DeviceState *uic;
+ PPCUIC uic;
Ppc405CpcState cpc;
Ppc405GptState gpt;
Ppc405OcmState ocm;
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 01625e3237..82830f52bf 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1080,6 +1080,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "cpu", &s->cpu,
POWERPC_CPU_TYPE_NAME("405ep"));
+ object_initialize_child(obj, "uic", &s->uic, TYPE_PPC_UIC);
+
object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC);
object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk");
@@ -1147,17 +1149,15 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(sbd, 0, 0xef600600);
/* Universal interrupt controller */
- s->uic = qdev_new(TYPE_PPC_UIC);
-
- object_property_set_link(OBJECT(s->uic), "cpu", OBJECT(&s->cpu),
+ object_property_set_link(OBJECT(&s->uic), "cpu", OBJECT(&s->cpu),
&error_fatal);
- if (!sysbus_realize(SYS_BUS_DEVICE(s->uic), errp)) {
+ sbd = SYS_BUS_DEVICE(&s->uic);
+ if (!sysbus_realize(sbd, errp)) {
return;
}
-
- sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_INT,
+ sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT,
qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_INT));
- sysbus_connect_irq(SYS_BUS_DEVICE(s->uic), PPCUIC_OUTPUT_CINT,
+ sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT,
qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
@@ -1168,7 +1168,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
"ppc405.sdram0", s->dram_mr,
s->ram_bases[0], s->ram_sizes[0]);
- ppc4xx_sdram_init(env, qdev_get_gpio_in(s->uic, 17), 1,
+ ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
s->ram_banks, s->ram_bases, s->ram_sizes,
s->do_dram_init);
@@ -1183,12 +1183,12 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
}
sbd = SYS_BUS_DEVICE(&s->dma);
for (i = 0; i < ARRAY_SIZE(s->dma.irqs); i++) {
- sysbus_connect_irq(sbd, i, qdev_get_gpio_in(s->uic, 5 + i));
+ sysbus_connect_irq(sbd, i, qdev_get_gpio_in(DEVICE(&s->uic), 5 + i));
}
/* I2C controller */
sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
- qdev_get_gpio_in(s->uic, 2));
+ qdev_get_gpio_in(DEVICE(&s->uic), 2));
/* GPIO */
sbd = SYS_BUS_DEVICE(&s->gpio);
@@ -1200,13 +1200,13 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
/* Serial ports */
if (serial_hd(0) != NULL) {
serial_mm_init(get_system_memory(), 0xef600300, 0,
- qdev_get_gpio_in(s->uic, 0),
+ qdev_get_gpio_in(DEVICE(&s->uic), 0),
PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
DEVICE_BIG_ENDIAN);
}
if (serial_hd(1) != NULL) {
serial_mm_init(get_system_memory(), 0xef600400, 0,
- qdev_get_gpio_in(s->uic, 1),
+ qdev_get_gpio_in(DEVICE(&s->uic), 1),
PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
DEVICE_BIG_ENDIAN);
}
@@ -1223,7 +1223,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
}
sysbus_mmio_map(sbd, 0, 0xef600000);
for (i = 0; i < ARRAY_SIZE(s->gpt.irqs); i++) {
- sysbus_connect_irq(sbd, i, qdev_get_gpio_in(s->uic, 19 + i));
+ sysbus_connect_irq(sbd, i, qdev_get_gpio_in(DEVICE(&s->uic), 19 + i));
}
/* MAL */
@@ -1234,7 +1234,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
}
sbd = SYS_BUS_DEVICE(&s->mal);
for (i = 0; i < ARRAY_SIZE(s->mal.irqs); i++) {
- sysbus_connect_irq(sbd, i, qdev_get_gpio_in(s->uic, 11 + i));
+ sysbus_connect_irq(sbd, i, qdev_get_gpio_in(DEVICE(&s->uic), 11 + i));
}
/* Ethernet */
--
2.30.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 15/22] hw/intc/ppc-uic: Convert ppc-uic to a PPC4xx DCR device
2022-08-13 15:34 [PATCH 00/22] QOMify PPC4xx devices and minor clean ups BALATON Zoltan
` (13 preceding siblings ...)
2022-08-13 15:34 ` [PATCH 14/22] ppc/ppc405: Use an embedded PPCUIC model in SoC state BALATON Zoltan
@ 2022-08-13 15:34 ` BALATON Zoltan
2022-08-16 7:36 ` Cédric Le Goater
2022-08-13 15:34 ` [PATCH 16/22] ppc/ppc405: Use an explicit I2C object BALATON Zoltan
` (7 subsequent siblings)
22 siblings, 1 reply; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-13 15:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Make ppc-uic a subclass of ppc4xx-dcr-device which will handle the cpu
link and make it uniform with the other PPC4xx devices.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/intc/ppc-uic.c | 26 ++++++--------------------
hw/ppc/ppc405_uc.c | 6 ++----
hw/ppc/ppc440_bamboo.c | 7 ++-----
hw/ppc/ppc4xx_devs.c | 1 -
hw/ppc/sam460ex.c | 17 +++++++----------
hw/ppc/virtex_ml507.c | 7 ++-----
include/hw/intc/ppc-uic.h | 6 ++----
7 files changed, 21 insertions(+), 49 deletions(-)
diff --git a/hw/intc/ppc-uic.c b/hw/intc/ppc-uic.c
index 60013f2dde..dcf5de5d43 100644
--- a/hw/intc/ppc-uic.c
+++ b/hw/intc/ppc-uic.c
@@ -25,11 +25,8 @@
#include "qemu/osdep.h"
#include "hw/intc/ppc-uic.h"
#include "hw/irq.h"
-#include "cpu.h"
-#include "hw/ppc/ppc.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
-#include "qapi/error.h"
enum {
DCR_UICSR = 0x000,
@@ -105,10 +102,9 @@ static void ppcuic_trigger_irq(PPCUIC *uic)
static void ppcuic_set_irq(void *opaque, int irq_num, int level)
{
- PPCUIC *uic;
+ PPCUIC *uic = opaque;
uint32_t mask, sr;
- uic = opaque;
mask = 1U << (31 - irq_num);
LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
" mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
@@ -144,10 +140,9 @@ static void ppcuic_set_irq(void *opaque, int irq_num, int level)
static uint32_t dcr_read_uic(void *opaque, int dcrn)
{
- PPCUIC *uic;
+ PPCUIC *uic = opaque;
uint32_t ret;
- uic = opaque;
dcrn -= uic->dcr_base;
switch (dcrn) {
case DCR_UICSR:
@@ -192,9 +187,8 @@ static uint32_t dcr_read_uic(void *opaque, int dcrn)
static void dcr_write_uic(void *opaque, int dcrn, uint32_t val)
{
- PPCUIC *uic;
+ PPCUIC *uic = opaque;
- uic = opaque;
dcrn -= uic->dcr_base;
LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val);
switch (dcrn) {
@@ -251,19 +245,12 @@ static void ppc_uic_reset(DeviceState *dev)
static void ppc_uic_realize(DeviceState *dev, Error **errp)
{
PPCUIC *uic = PPC_UIC(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
- PowerPCCPU *cpu;
int i;
- if (!uic->cpu) {
- /* This is a programming error in the code using this device */
- error_setg(errp, "ppc-uic 'cpu' link property was not set");
- return;
- }
-
- cpu = POWERPC_CPU(uic->cpu);
for (i = 0; i < DCR_UICMAX; i++) {
- ppc_dcr_register(&cpu->env, uic->dcr_base + i, uic,
+ ppc4xx_dcr_register(dcr, uic->dcr_base + i, uic,
&dcr_read_uic, &dcr_write_uic);
}
@@ -273,7 +260,6 @@ static void ppc_uic_realize(DeviceState *dev, Error **errp)
}
static Property ppc_uic_properties[] = {
- DEFINE_PROP_LINK("cpu", PPCUIC, cpu, TYPE_CPU, CPUState *),
DEFINE_PROP_UINT32("dcr-base", PPCUIC, dcr_base, 0xc0),
DEFINE_PROP_BOOL("use-vectors", PPCUIC, use_vectors, true),
DEFINE_PROP_END_OF_LIST()
@@ -308,7 +294,7 @@ static void ppc_uic_class_init(ObjectClass *klass, void *data)
static const TypeInfo ppc_uic_info = {
.name = TYPE_PPC_UIC,
- .parent = TYPE_SYS_BUS_DEVICE,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(PPCUIC),
.class_init = ppc_uic_class_init,
};
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 82830f52bf..aa3617f876 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1149,12 +1149,10 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(sbd, 0, 0xef600600);
/* Universal interrupt controller */
- object_property_set_link(OBJECT(&s->uic), "cpu", OBJECT(&s->cpu),
- &error_fatal);
- sbd = SYS_BUS_DEVICE(&s->uic);
- if (!sysbus_realize(sbd, errp)) {
+ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->uic), &s->cpu, errp)) {
return;
}
+ sbd = SYS_BUS_DEVICE(&s->uic);
sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT,
qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_INT));
sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT,
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 873f930c77..b14a9ef776 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -193,12 +193,9 @@ static void bamboo_init(MachineState *machine)
/* interrupt controller */
uicdev = qdev_new(TYPE_PPC_UIC);
+ ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uicdev), cpu, &error_fatal);
+ object_unref(OBJECT(uicdev));
uicsbd = SYS_BUS_DEVICE(uicdev);
-
- object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
- &error_fatal);
- sysbus_realize_and_unref(uicsbd, &error_fatal);
-
sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));
sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 96941ae040..49793b56cd 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -29,7 +29,6 @@
#include "hw/irq.h"
#include "hw/ppc/ppc.h"
#include "hw/ppc/ppc4xx.h"
-#include "hw/intc/ppc-uic.h"
#include "hw/qdev-properties.h"
#include "qemu/log.h"
#include "exec/address-spaces.h"
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index c16303462d..c96de98690 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -314,7 +314,6 @@ static void sam460ex_init(MachineState *machine)
/* interrupt controllers */
for (i = 0; i < ARRAY_SIZE(uic); i++) {
- SysBusDevice *sbd;
/*
* UICs 1, 2 and 3 are cascaded through UIC 0.
* input_ints[n] is the interrupt number on UIC 0 which
@@ -326,22 +325,20 @@ static void sam460ex_init(MachineState *machine)
const int input_ints[] = { -1, 30, 10, 16 };
uic[i] = qdev_new(TYPE_PPC_UIC);
- sbd = SYS_BUS_DEVICE(uic[i]);
-
qdev_prop_set_uint32(uic[i], "dcr-base", 0xc0 + i * 0x10);
- object_property_set_link(OBJECT(uic[i]), "cpu", OBJECT(cpu),
- &error_fatal);
- sysbus_realize_and_unref(sbd, &error_fatal);
+ ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uic[i]), cpu, &error_fatal);
+ object_unref(OBJECT(uic[i]));
+ sbdev = SYS_BUS_DEVICE(uic[i]);
if (i == 0) {
- sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT,
+ sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_INT,
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));
- sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT,
+ sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_CINT,
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
} else {
- sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT,
+ sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_INT,
qdev_get_gpio_in(uic[0], input_ints[i]));
- sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT,
+ sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_CINT,
qdev_get_gpio_in(uic[0], input_ints[i] + 1));
}
}
diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c
index 53b126ff48..493ea0c19f 100644
--- a/hw/ppc/virtex_ml507.c
+++ b/hw/ppc/virtex_ml507.c
@@ -104,12 +104,9 @@ static PowerPCCPU *ppc440_init_xilinx(const char *cpu_type, uint32_t sysclk)
/* interrupt controller */
uicdev = qdev_new(TYPE_PPC_UIC);
+ ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uicdev), cpu, &error_fatal);
+ object_unref(OBJECT(uicdev));
uicsbd = SYS_BUS_DEVICE(uicdev);
-
- object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
- &error_fatal);
- sysbus_realize_and_unref(uicsbd, &error_fatal);
-
sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));
sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
diff --git a/include/hw/intc/ppc-uic.h b/include/hw/intc/ppc-uic.h
index 22dd5e5ac2..4d82e9a3c6 100644
--- a/include/hw/intc/ppc-uic.h
+++ b/include/hw/intc/ppc-uic.h
@@ -25,8 +25,7 @@
#ifndef HW_INTC_PPC_UIC_H
#define HW_INTC_PPC_UIC_H
-#include "hw/sysbus.h"
-#include "qom/object.h"
+#include "hw/ppc/ppc4xx.h"
#define TYPE_PPC_UIC "ppc-uic"
OBJECT_DECLARE_SIMPLE_TYPE(PPCUIC, PPC_UIC)
@@ -56,14 +55,13 @@ enum {
struct PPCUIC {
/*< private >*/
- SysBusDevice parent_obj;
+ Ppc4xxDcrDeviceState parent_obj;
/*< public >*/
qemu_irq output_int;
qemu_irq output_cint;
/* properties */
- CPUState *cpu;
uint32_t dcr_base;
bool use_vectors;
--
2.30.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH 15/22] hw/intc/ppc-uic: Convert ppc-uic to a PPC4xx DCR device
2022-08-13 15:34 ` [PATCH 15/22] hw/intc/ppc-uic: Convert ppc-uic to a PPC4xx DCR device BALATON Zoltan
@ 2022-08-16 7:36 ` Cédric Le Goater
0 siblings, 0 replies; 37+ messages in thread
From: Cédric Le Goater @ 2022-08-16 7:36 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc
Cc: Daniel Henrique Barboza, Peter Maydell
On 8/13/22 17:34, BALATON Zoltan wrote:
> Make ppc-uic a subclass of ppc4xx-dcr-device which will handle the cpu
> link and make it uniform with the other PPC4xx devices.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> hw/intc/ppc-uic.c | 26 ++++++--------------------
> hw/ppc/ppc405_uc.c | 6 ++----
> hw/ppc/ppc440_bamboo.c | 7 ++-----
> hw/ppc/ppc4xx_devs.c | 1 -
> hw/ppc/sam460ex.c | 17 +++++++----------
> hw/ppc/virtex_ml507.c | 7 ++-----
> include/hw/intc/ppc-uic.h | 6 ++----
> 7 files changed, 21 insertions(+), 49 deletions(-)
>
> diff --git a/hw/intc/ppc-uic.c b/hw/intc/ppc-uic.c
> index 60013f2dde..dcf5de5d43 100644
> --- a/hw/intc/ppc-uic.c
> +++ b/hw/intc/ppc-uic.c
> @@ -25,11 +25,8 @@
> #include "qemu/osdep.h"
> #include "hw/intc/ppc-uic.h"
> #include "hw/irq.h"
> -#include "cpu.h"
> -#include "hw/ppc/ppc.h"
> #include "hw/qdev-properties.h"
> #include "migration/vmstate.h"
> -#include "qapi/error.h"
>
> enum {
> DCR_UICSR = 0x000,
> @@ -105,10 +102,9 @@ static void ppcuic_trigger_irq(PPCUIC *uic)
>
> static void ppcuic_set_irq(void *opaque, int irq_num, int level)
> {
> - PPCUIC *uic;
> + PPCUIC *uic = opaque;
> uint32_t mask, sr;
>
> - uic = opaque;
> mask = 1U << (31 - irq_num);
> LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
> " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
> @@ -144,10 +140,9 @@ static void ppcuic_set_irq(void *opaque, int irq_num, int level)
>
> static uint32_t dcr_read_uic(void *opaque, int dcrn)
> {
> - PPCUIC *uic;
> + PPCUIC *uic = opaque;
> uint32_t ret;
>
> - uic = opaque;
> dcrn -= uic->dcr_base;
> switch (dcrn) {
> case DCR_UICSR:
> @@ -192,9 +187,8 @@ static uint32_t dcr_read_uic(void *opaque, int dcrn)
>
> static void dcr_write_uic(void *opaque, int dcrn, uint32_t val)
> {
> - PPCUIC *uic;
> + PPCUIC *uic = opaque;
>
> - uic = opaque;
> dcrn -= uic->dcr_base;
> LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val);
> switch (dcrn) {
> @@ -251,19 +245,12 @@ static void ppc_uic_reset(DeviceState *dev)
> static void ppc_uic_realize(DeviceState *dev, Error **errp)
> {
> PPCUIC *uic = PPC_UIC(dev);
> + Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
> SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> - PowerPCCPU *cpu;
> int i;
>
> - if (!uic->cpu) {
> - /* This is a programming error in the code using this device */
> - error_setg(errp, "ppc-uic 'cpu' link property was not set");
> - return;
> - }
> -
> - cpu = POWERPC_CPU(uic->cpu);
> for (i = 0; i < DCR_UICMAX; i++) {
> - ppc_dcr_register(&cpu->env, uic->dcr_base + i, uic,
> + ppc4xx_dcr_register(dcr, uic->dcr_base + i, uic,
> &dcr_read_uic, &dcr_write_uic);
> }
>
> @@ -273,7 +260,6 @@ static void ppc_uic_realize(DeviceState *dev, Error **errp)
> }
>
> static Property ppc_uic_properties[] = {
> - DEFINE_PROP_LINK("cpu", PPCUIC, cpu, TYPE_CPU, CPUState *),
> DEFINE_PROP_UINT32("dcr-base", PPCUIC, dcr_base, 0xc0),
> DEFINE_PROP_BOOL("use-vectors", PPCUIC, use_vectors, true),
> DEFINE_PROP_END_OF_LIST()
> @@ -308,7 +294,7 @@ static void ppc_uic_class_init(ObjectClass *klass, void *data)
>
> static const TypeInfo ppc_uic_info = {
> .name = TYPE_PPC_UIC,
> - .parent = TYPE_SYS_BUS_DEVICE,
> + .parent = TYPE_PPC4xx_DCR_DEVICE,
> .instance_size = sizeof(PPCUIC),
> .class_init = ppc_uic_class_init,
> };
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index 82830f52bf..aa3617f876 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -1149,12 +1149,10 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> sysbus_mmio_map(sbd, 0, 0xef600600);
>
> /* Universal interrupt controller */
> - object_property_set_link(OBJECT(&s->uic), "cpu", OBJECT(&s->cpu),
> - &error_fatal);
> - sbd = SYS_BUS_DEVICE(&s->uic);
> - if (!sysbus_realize(sbd, errp)) {
> + if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->uic), &s->cpu, errp)) {
> return;
> }
> + sbd = SYS_BUS_DEVICE(&s->uic);
> sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT,
> qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_INT));
> sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT,
> diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
> index 873f930c77..b14a9ef776 100644
> --- a/hw/ppc/ppc440_bamboo.c
> +++ b/hw/ppc/ppc440_bamboo.c
> @@ -193,12 +193,9 @@ static void bamboo_init(MachineState *machine)
>
> /* interrupt controller */
> uicdev = qdev_new(TYPE_PPC_UIC);
> + ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uicdev), cpu, &error_fatal);
> + object_unref(OBJECT(uicdev));
> uicsbd = SYS_BUS_DEVICE(uicdev);
> -
> - object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
> - &error_fatal);
> - sysbus_realize_and_unref(uicsbd, &error_fatal);
> -
> sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
> qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));
> sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
> index 96941ae040..49793b56cd 100644
> --- a/hw/ppc/ppc4xx_devs.c
> +++ b/hw/ppc/ppc4xx_devs.c
> @@ -29,7 +29,6 @@
> #include "hw/irq.h"
> #include "hw/ppc/ppc.h"
> #include "hw/ppc/ppc4xx.h"
> -#include "hw/intc/ppc-uic.h"
> #include "hw/qdev-properties.h"
> #include "qemu/log.h"
> #include "exec/address-spaces.h"
> diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
> index c16303462d..c96de98690 100644
> --- a/hw/ppc/sam460ex.c
> +++ b/hw/ppc/sam460ex.c
> @@ -314,7 +314,6 @@ static void sam460ex_init(MachineState *machine)
>
> /* interrupt controllers */
> for (i = 0; i < ARRAY_SIZE(uic); i++) {
> - SysBusDevice *sbd;
> /*
> * UICs 1, 2 and 3 are cascaded through UIC 0.
> * input_ints[n] is the interrupt number on UIC 0 which
> @@ -326,22 +325,20 @@ static void sam460ex_init(MachineState *machine)
> const int input_ints[] = { -1, 30, 10, 16 };
>
> uic[i] = qdev_new(TYPE_PPC_UIC);
> - sbd = SYS_BUS_DEVICE(uic[i]);
> -
> qdev_prop_set_uint32(uic[i], "dcr-base", 0xc0 + i * 0x10);
> - object_property_set_link(OBJECT(uic[i]), "cpu", OBJECT(cpu),
> - &error_fatal);
> - sysbus_realize_and_unref(sbd, &error_fatal);
> + ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uic[i]), cpu, &error_fatal);
> + object_unref(OBJECT(uic[i]));
>
> + sbdev = SYS_BUS_DEVICE(uic[i]);
> if (i == 0) {
> - sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT,
> + sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_INT,
> qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));
> - sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT,
> + sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_CINT,
> qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
> } else {
> - sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT,
> + sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_INT,
> qdev_get_gpio_in(uic[0], input_ints[i]));
> - sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT,
> + sysbus_connect_irq(sbdev, PPCUIC_OUTPUT_CINT,
> qdev_get_gpio_in(uic[0], input_ints[i] + 1));
> }
> }
> diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c
> index 53b126ff48..493ea0c19f 100644
> --- a/hw/ppc/virtex_ml507.c
> +++ b/hw/ppc/virtex_ml507.c
> @@ -104,12 +104,9 @@ static PowerPCCPU *ppc440_init_xilinx(const char *cpu_type, uint32_t sysclk)
>
> /* interrupt controller */
> uicdev = qdev_new(TYPE_PPC_UIC);
> + ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uicdev), cpu, &error_fatal);
> + object_unref(OBJECT(uicdev));
> uicsbd = SYS_BUS_DEVICE(uicdev);
> -
> - object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
> - &error_fatal);
> - sysbus_realize_and_unref(uicsbd, &error_fatal);
> -
> sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
> qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));
> sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
> diff --git a/include/hw/intc/ppc-uic.h b/include/hw/intc/ppc-uic.h
> index 22dd5e5ac2..4d82e9a3c6 100644
> --- a/include/hw/intc/ppc-uic.h
> +++ b/include/hw/intc/ppc-uic.h
> @@ -25,8 +25,7 @@
> #ifndef HW_INTC_PPC_UIC_H
> #define HW_INTC_PPC_UIC_H
>
> -#include "hw/sysbus.h"
> -#include "qom/object.h"
> +#include "hw/ppc/ppc4xx.h"
>
> #define TYPE_PPC_UIC "ppc-uic"
> OBJECT_DECLARE_SIMPLE_TYPE(PPCUIC, PPC_UIC)
> @@ -56,14 +55,13 @@ enum {
>
> struct PPCUIC {
> /*< private >*/
> - SysBusDevice parent_obj;
> + Ppc4xxDcrDeviceState parent_obj;
>
> /*< public >*/
> qemu_irq output_int;
> qemu_irq output_cint;
>
> /* properties */
> - CPUState *cpu;
> uint32_t dcr_base;
> bool use_vectors;
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 16/22] ppc/ppc405: Use an explicit I2C object
2022-08-13 15:34 [PATCH 00/22] QOMify PPC4xx devices and minor clean ups BALATON Zoltan
` (14 preceding siblings ...)
2022-08-13 15:34 ` [PATCH 15/22] hw/intc/ppc-uic: Convert ppc-uic to a PPC4xx DCR device BALATON Zoltan
@ 2022-08-13 15:34 ` BALATON Zoltan
2022-08-13 15:34 ` [PATCH 17/22] ppc/ppc405: QOM'ify FPGA BALATON Zoltan
` (6 subsequent siblings)
22 siblings, 0 replies; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-13 15:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
From: Cédric Le Goater <clg@kaod.org>
Having an explicit I2C model object will help if one day we want to
add I2C devices on the bus from the machine init routine.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc405.h | 2 ++
hw/ppc/ppc405_uc.c | 10 ++++++++--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 5bcbce2893..12eee97169 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -28,6 +28,7 @@
#include "qom/object.h"
#include "hw/ppc/ppc4xx.h"
#include "hw/intc/ppc-uic.h"
+#include "hw/i2c/ppc4xx_i2c.h"
#define PPC405EP_SDRAM_BASE 0x00000000
#define PPC405EP_NVRAM_BASE 0xF0000000
@@ -215,6 +216,7 @@ struct Ppc405SoCState {
Ppc405OcmState ocm;
Ppc405GpioState gpio;
Ppc405DmaState dma;
+ PPC4xxI2CState i2c;
Ppc405EbcState ebc;
Ppc405OpbaState opba;
Ppc405PobState pob;
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index aa3617f876..a7a7d7e65b 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1093,6 +1093,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
+ object_initialize_child(obj, "i2c", &s->i2c, TYPE_PPC4xx_I2C);
+
object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
@@ -1185,8 +1187,12 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
}
/* I2C controller */
- sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
- qdev_get_gpio_in(DEVICE(&s->uic), 2));
+ sbd = SYS_BUS_DEVICE(&s->i2c);
+ if (!sysbus_realize(sbd, errp)) {
+ return;
+ }
+ sysbus_mmio_map(sbd, 0, 0xef600500);
+ sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(DEVICE(&s->uic), 2));
/* GPIO */
sbd = SYS_BUS_DEVICE(&s->gpio);
--
2.30.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 17/22] ppc/ppc405: QOM'ify FPGA
2022-08-13 15:34 [PATCH 00/22] QOMify PPC4xx devices and minor clean ups BALATON Zoltan
` (15 preceding siblings ...)
2022-08-13 15:34 ` [PATCH 16/22] ppc/ppc405: Use an explicit I2C object BALATON Zoltan
@ 2022-08-13 15:34 ` BALATON Zoltan
2022-08-13 15:34 ` [PATCH 18/22] ppc405: Move machine specific code to ppc405_boards.c BALATON Zoltan
` (5 subsequent siblings)
22 siblings, 0 replies; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-13 15:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
From: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc405_boards.c | 56 +++++++++++++++++++++++++++++-------------
1 file changed, 39 insertions(+), 17 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 3677793adc..7af0d7feef 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -71,18 +71,23 @@ struct Ppc405MachineState {
* - NVRAM (0xF0000000)
* - FPGA (0xF0300000)
*/
-typedef struct ref405ep_fpga_t ref405ep_fpga_t;
-struct ref405ep_fpga_t {
+
+#define TYPE_REF405EP_FPGA "ref405ep-fpga"
+OBJECT_DECLARE_SIMPLE_TYPE(Ref405epFpgaState, REF405EP_FPGA);
+struct Ref405epFpgaState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+
uint8_t reg0;
uint8_t reg1;
};
static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
{
- ref405ep_fpga_t *fpga;
+ Ref405epFpgaState *fpga = opaque;
uint32_t ret;
- fpga = opaque;
switch (addr) {
case 0x0:
ret = fpga->reg0;
@@ -101,9 +106,8 @@ static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
- ref405ep_fpga_t *fpga;
+ Ref405epFpgaState *fpga = opaque;
- fpga = opaque;
switch (addr) {
case 0x0:
/* Read only */
@@ -126,27 +130,40 @@ static const MemoryRegionOps ref405ep_fpga_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static void ref405ep_fpga_reset (void *opaque)
+static void ref405ep_fpga_reset(DeviceState *dev)
{
- ref405ep_fpga_t *fpga;
+ Ref405epFpgaState *fpga = REF405EP_FPGA(dev);
- fpga = opaque;
fpga->reg0 = 0x00;
fpga->reg1 = 0x0F;
}
-static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
+static void ref405ep_fpga_realize(DeviceState *dev, Error **errp)
{
- ref405ep_fpga_t *fpga;
- MemoryRegion *fpga_memory = g_new(MemoryRegion, 1);
+ Ref405epFpgaState *s = REF405EP_FPGA(dev);
- fpga = g_new0(ref405ep_fpga_t, 1);
- memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga,
+ memory_region_init_io(&s->iomem, OBJECT(s), &ref405ep_fpga_ops, s,
"fpga", 0x00000100);
- memory_region_add_subregion(sysmem, base, fpga_memory);
- qemu_register_reset(&ref405ep_fpga_reset, fpga);
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
+}
+
+static void ref405ep_fpga_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ref405ep_fpga_realize;
+ dc->reset = ref405ep_fpga_reset;
+ /* Reason: only works as part of a ppc405 board */
+ dc->user_creatable = false;
}
+static const TypeInfo ref405ep_fpga_type = {
+ .name = TYPE_REF405EP_FPGA,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Ref405epFpgaState),
+ .class_init = ref405ep_fpga_class_init,
+};
+
/*
* CPU reset handler when booting directly from a loaded kernel
*/
@@ -331,7 +348,11 @@ static void ref405ep_init(MachineState *machine)
memory_region_add_subregion(get_system_memory(), PPC405EP_SRAM_BASE, sram);
/* Register FPGA */
- ref405ep_fpga_init(get_system_memory(), PPC405EP_FPGA_BASE);
+ dev = qdev_new(TYPE_REF405EP_FPGA);
+ object_property_add_child(OBJECT(machine), "fpga", OBJECT(dev));
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, PPC405EP_FPGA_BASE);
+
/* Register NVRAM */
dev = qdev_new("sysbus-m48t08");
qdev_prop_set_int32(dev, "base-year", 1968);
@@ -376,6 +397,7 @@ static void ppc405_machine_init(void)
{
type_register_static(&ppc405_machine_type);
type_register_static(&ref405ep_type);
+ type_register_static(&ref405ep_fpga_type);
}
type_init(ppc405_machine_init)
--
2.30.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* [PATCH 18/22] ppc405: Move machine specific code to ppc405_boards.c
2022-08-13 15:34 [PATCH 00/22] QOMify PPC4xx devices and minor clean ups BALATON Zoltan
` (16 preceding siblings ...)
2022-08-13 15:34 ` [PATCH 17/22] ppc/ppc405: QOM'ify FPGA BALATON Zoltan
@ 2022-08-13 15:34 ` BALATON Zoltan
2022-08-16 7:46 ` Cédric Le Goater
2022-08-13 15:34 ` [PATCH 19/22] hw/ppc/Kconfig: Remove PPC405 dependency from sam460ex BALATON Zoltan
` (4 subsequent siblings)
22 siblings, 1 reply; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-13 15:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
These are only used by tha board code so move out from the shared SoC
model and put it in the boards file.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc405.h | 38 -----
hw/ppc/ppc405_boards.c | 375 +++++++++++++++++++++++++++--------------
hw/ppc/ppc405_uc.c | 92 ----------
3 files changed, 251 insertions(+), 254 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 12eee97169..6b26fc6d17 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -30,41 +30,6 @@
#include "hw/intc/ppc-uic.h"
#include "hw/i2c/ppc4xx_i2c.h"
-#define PPC405EP_SDRAM_BASE 0x00000000
-#define PPC405EP_NVRAM_BASE 0xF0000000
-#define PPC405EP_FPGA_BASE 0xF0300000
-#define PPC405EP_SRAM_BASE 0xFFF00000
-#define PPC405EP_SRAM_SIZE (512 * KiB)
-#define PPC405EP_FLASH_BASE 0xFFF80000
-
-/* Bootinfo as set-up by u-boot */
-typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t;
-struct ppc4xx_bd_info_t {
- uint32_t bi_memstart;
- uint32_t bi_memsize;
- uint32_t bi_flashstart;
- uint32_t bi_flashsize;
- uint32_t bi_flashoffset; /* 0x10 */
- uint32_t bi_sramstart;
- uint32_t bi_sramsize;
- uint32_t bi_bootflags;
- uint32_t bi_ipaddr; /* 0x20 */
- uint8_t bi_enetaddr[6];
- uint16_t bi_ethspeed;
- uint32_t bi_intfreq;
- uint32_t bi_busfreq; /* 0x30 */
- uint32_t bi_baudrate;
- uint8_t bi_s_version[4];
- uint8_t bi_r_version[32];
- uint32_t bi_procfreq;
- uint32_t bi_plb_busfreq;
- uint32_t bi_pci_busfreq;
- uint8_t bi_pci_enetaddr[6];
- uint8_t bi_pci_enetaddr2[6]; /* PPC405EP specific */
- uint32_t bi_opbfreq;
- uint32_t bi_iic_fast[2];
-};
-
/* PLB to OPB bridge */
#define TYPE_PPC405_POB "ppc405-pob"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
@@ -224,7 +189,4 @@ struct Ppc405SoCState {
Ppc4xxMalState mal;
};
-/* PowerPC 405 core */
-ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
-
#endif /* PPC405_H */
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 7af0d7feef..083f12b23e 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -48,6 +48,10 @@
#define KERNEL_LOAD_ADDR 0x01000000
#define INITRD_LOAD_ADDR 0x01800000
+#define PPC405EP_SDRAM_BASE 0x00000000
+#define PPC405EP_SRAM_BASE 0xFFF00000
+#define PPC405EP_SRAM_SIZE (512 * KiB)
+
#define USE_FLASH_BIOS
#define TYPE_PPC405_MACHINE MACHINE_TYPE_NAME("ppc405")
@@ -61,112 +65,7 @@ struct Ppc405MachineState {
Ppc405SoCState soc;
};
-/*****************************************************************************/
-/* PPC405EP reference board (IBM) */
-/* Standalone board with:
- * - PowerPC 405EP CPU
- * - SDRAM (0x00000000)
- * - Flash (0xFFF80000)
- * - SRAM (0xFFF00000)
- * - NVRAM (0xF0000000)
- * - FPGA (0xF0300000)
- */
-
-#define TYPE_REF405EP_FPGA "ref405ep-fpga"
-OBJECT_DECLARE_SIMPLE_TYPE(Ref405epFpgaState, REF405EP_FPGA);
-struct Ref405epFpgaState {
- SysBusDevice parent_obj;
-
- MemoryRegion iomem;
-
- uint8_t reg0;
- uint8_t reg1;
-};
-
-static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
-{
- Ref405epFpgaState *fpga = opaque;
- uint32_t ret;
-
- switch (addr) {
- case 0x0:
- ret = fpga->reg0;
- break;
- case 0x1:
- ret = fpga->reg1;
- break;
- default:
- ret = 0;
- break;
- }
-
- return ret;
-}
-
-static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
- unsigned size)
-{
- Ref405epFpgaState *fpga = opaque;
-
- switch (addr) {
- case 0x0:
- /* Read only */
- break;
- case 0x1:
- fpga->reg1 = value;
- break;
- default:
- break;
- }
-}
-
-static const MemoryRegionOps ref405ep_fpga_ops = {
- .read = ref405ep_fpga_readb,
- .write = ref405ep_fpga_writeb,
- .impl.min_access_size = 1,
- .impl.max_access_size = 1,
- .valid.min_access_size = 1,
- .valid.max_access_size = 4,
- .endianness = DEVICE_BIG_ENDIAN,
-};
-
-static void ref405ep_fpga_reset(DeviceState *dev)
-{
- Ref405epFpgaState *fpga = REF405EP_FPGA(dev);
-
- fpga->reg0 = 0x00;
- fpga->reg1 = 0x0F;
-}
-
-static void ref405ep_fpga_realize(DeviceState *dev, Error **errp)
-{
- Ref405epFpgaState *s = REF405EP_FPGA(dev);
-
- memory_region_init_io(&s->iomem, OBJECT(s), &ref405ep_fpga_ops, s,
- "fpga", 0x00000100);
- sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
-}
-
-static void ref405ep_fpga_class_init(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
-
- dc->realize = ref405ep_fpga_realize;
- dc->reset = ref405ep_fpga_reset;
- /* Reason: only works as part of a ppc405 board */
- dc->user_creatable = false;
-}
-
-static const TypeInfo ref405ep_fpga_type = {
- .name = TYPE_REF405EP_FPGA,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(Ref405epFpgaState),
- .class_init = ref405ep_fpga_class_init,
-};
-
-/*
- * CPU reset handler when booting directly from a loaded kernel
- */
+/* CPU reset handler when booting directly from a loaded kernel */
static struct boot_info {
uint32_t entry;
uint32_t bdloc;
@@ -197,6 +96,126 @@ static void main_cpu_reset(void *opaque)
env->nip = bi->entry;
}
+/* Bootinfo as set-up by u-boot */
+typedef struct {
+ uint32_t bi_memstart;
+ uint32_t bi_memsize;
+ uint32_t bi_flashstart;
+ uint32_t bi_flashsize;
+ uint32_t bi_flashoffset; /* 0x10 */
+ uint32_t bi_sramstart;
+ uint32_t bi_sramsize;
+ uint32_t bi_bootflags;
+ uint32_t bi_ipaddr; /* 0x20 */
+ uint8_t bi_enetaddr[6];
+ uint16_t bi_ethspeed;
+ uint32_t bi_intfreq;
+ uint32_t bi_busfreq; /* 0x30 */
+ uint32_t bi_baudrate;
+ uint8_t bi_s_version[4];
+ uint8_t bi_r_version[32];
+ uint32_t bi_procfreq;
+ uint32_t bi_plb_busfreq;
+ uint32_t bi_pci_busfreq;
+ uint8_t bi_pci_enetaddr[6];
+ uint8_t bi_pci_enetaddr2[6]; /* PPC405EP specific */
+ uint32_t bi_opbfreq;
+ uint32_t bi_iic_fast[2];
+} ppc4xx_bd_info_t;
+
+static void ppc405_set_default_bootinfo(ppc4xx_bd_info_t *bd,
+ ram_addr_t ram_size)
+{
+ memset(bd, 0, sizeof(*bd));
+
+ bd->bi_memstart = PPC405EP_SDRAM_BASE;
+ bd->bi_memsize = ram_size;
+ bd->bi_sramstart = PPC405EP_SRAM_BASE;
+ bd->bi_sramsize = PPC405EP_SRAM_SIZE;
+ bd->bi_bootflags = 0;
+ bd->bi_intfreq = 133333333;
+ bd->bi_busfreq = 33333333;
+ bd->bi_baudrate = 115200;
+ bd->bi_s_version[0] = 'Q';
+ bd->bi_s_version[1] = 'M';
+ bd->bi_s_version[2] = 'U';
+ bd->bi_s_version[3] = '\0';
+ bd->bi_r_version[0] = 'Q';
+ bd->bi_r_version[1] = 'E';
+ bd->bi_r_version[2] = 'M';
+ bd->bi_r_version[3] = 'U';
+ bd->bi_r_version[4] = '\0';
+ bd->bi_procfreq = 133333333;
+ bd->bi_plb_busfreq = 33333333;
+ bd->bi_pci_busfreq = 33333333;
+ bd->bi_opbfreq = 33333333;
+}
+
+static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd)
+{
+ CPUState *cs = env_cpu(env);
+ ram_addr_t bdloc;
+ int i, n;
+
+ /* We put the bd structure at the top of memory */
+ if (bd->bi_memsize >= 0x01000000UL) {
+ bdloc = 0x01000000UL - sizeof(ppc4xx_bd_info_t);
+ } else {
+ bdloc = bd->bi_memsize - sizeof(ppc4xx_bd_info_t);
+ }
+ stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart);
+ stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize);
+ stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart);
+ stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize);
+ stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset);
+ stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart);
+ stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize);
+ stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags);
+ stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr);
+ for (i = 0; i < 6; i++) {
+ stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]);
+ }
+ stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
+ stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
+ stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
+ stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
+ for (i = 0; i < 4; i++) {
+ stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]);
+ }
+ for (i = 0; i < 32; i++) {
+ stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
+ }
+ stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_procfreq);
+ stl_be_phys(cs->as, bdloc + 0x60, bd->bi_plb_busfreq);
+ stl_be_phys(cs->as, bdloc + 0x64, bd->bi_pci_busfreq);
+ for (i = 0; i < 6; i++) {
+ stb_phys(cs->as, bdloc + 0x68 + i, bd->bi_pci_enetaddr[i]);
+ }
+ n = 0x70; /* includes 2 bytes hole */
+ for (i = 0; i < 6; i++) {
+ stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
+ }
+ stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq);
+ n += 4;
+ for (i = 0; i < 2; i++) {
+ stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]);
+ n += 4;
+ }
+
+ return bdloc;
+}
+
+static ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size)
+{
+ ppc4xx_bd_info_t bd;
+
+ memset(&bd, 0, sizeof(bd));
+
+ ppc405_set_default_bootinfo(&bd, ram_size);
+
+ return __ppc405_set_bootinfo(env, &bd);
+}
+
static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
@@ -334,6 +353,132 @@ static void ppc405_init(MachineState *machine)
}
}
+static void ppc405_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "PPC405 generic machine";
+ mc->init = ppc405_init;
+ mc->default_ram_size = 128 * MiB;
+ mc->default_ram_id = "ppc405.ram";
+}
+
+static const TypeInfo ppc405_machine_type = {
+ .name = TYPE_PPC405_MACHINE,
+ .parent = TYPE_MACHINE,
+ .instance_size = sizeof(Ppc405MachineState),
+ .class_init = ppc405_machine_class_init,
+ .abstract = true,
+};
+
+/*****************************************************************************/
+/* PPC405EP reference board (IBM) */
+/*
+ * Standalone board with:
+ * - PowerPC 405EP CPU
+ * - SDRAM (0x00000000)
+ * - Flash (0xFFF80000)
+ * - SRAM (0xFFF00000)
+ * - NVRAM (0xF0000000)
+ * - FPGA (0xF0300000)
+ */
+
+#define PPC405EP_NVRAM_BASE 0xF0000000
+#define PPC405EP_FPGA_BASE 0xF0300000
+#define PPC405EP_FLASH_BASE 0xFFF80000
+
+#define TYPE_REF405EP_FPGA "ref405ep-fpga"
+OBJECT_DECLARE_SIMPLE_TYPE(Ref405epFpgaState, REF405EP_FPGA);
+struct Ref405epFpgaState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+
+ uint8_t reg0;
+ uint8_t reg1;
+};
+
+static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
+{
+ Ref405epFpgaState *fpga = opaque;
+ uint32_t ret;
+
+ switch (addr) {
+ case 0x0:
+ ret = fpga->reg0;
+ break;
+ case 0x1:
+ ret = fpga->reg1;
+ break;
+ default:
+ ret = 0;
+ break;
+ }
+
+ return ret;
+}
+
+static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ Ref405epFpgaState *fpga = opaque;
+
+ switch (addr) {
+ case 0x0:
+ /* Read only */
+ break;
+ case 0x1:
+ fpga->reg1 = value;
+ break;
+ default:
+ break;
+ }
+}
+
+static const MemoryRegionOps ref405ep_fpga_ops = {
+ .read = ref405ep_fpga_readb,
+ .write = ref405ep_fpga_writeb,
+ .impl.min_access_size = 1,
+ .impl.max_access_size = 1,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 4,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
+static void ref405ep_fpga_reset(DeviceState *dev)
+{
+ Ref405epFpgaState *fpga = REF405EP_FPGA(dev);
+
+ fpga->reg0 = 0x00;
+ fpga->reg1 = 0x0F;
+}
+
+static void ref405ep_fpga_realize(DeviceState *dev, Error **errp)
+{
+ Ref405epFpgaState *s = REF405EP_FPGA(dev);
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &ref405ep_fpga_ops, s,
+ "fpga", 0x00000100);
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
+}
+
+static void ref405ep_fpga_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ref405ep_fpga_realize;
+ dc->reset = ref405ep_fpga_reset;
+ /* Reason: only works as part of a ppc405 board */
+ dc->user_creatable = false;
+}
+
+static const TypeInfo ref405ep_fpga_type = {
+ .name = TYPE_REF405EP_FPGA,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Ref405epFpgaState),
+ .class_init = ref405ep_fpga_class_init,
+};
+
static void ref405ep_init(MachineState *machine)
{
DeviceState *dev;
@@ -375,24 +520,6 @@ static const TypeInfo ref405ep_type = {
.class_init = ref405ep_class_init,
};
-static void ppc405_machine_class_init(ObjectClass *oc, void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
-
- mc->desc = "PPC405 generic machine";
- mc->init = ppc405_init;
- mc->default_ram_size = 128 * MiB;
- mc->default_ram_id = "ppc405.ram";
-}
-
-static const TypeInfo ppc405_machine_type = {
- .name = TYPE_PPC405_MACHINE,
- .parent = TYPE_MACHINE,
- .instance_size = sizeof(Ppc405MachineState),
- .class_init = ppc405_machine_class_init,
- .abstract = true,
-};
-
static void ppc405_machine_init(void)
{
type_register_static(&ppc405_machine_type);
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index a7a7d7e65b..b13026200f 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -42,98 +42,6 @@
#include "qapi/error.h"
#include "trace.h"
-static void ppc405_set_default_bootinfo(ppc4xx_bd_info_t *bd,
- ram_addr_t ram_size)
-{
- memset(bd, 0, sizeof(*bd));
-
- bd->bi_memstart = PPC405EP_SDRAM_BASE;
- bd->bi_memsize = ram_size;
- bd->bi_sramstart = PPC405EP_SRAM_BASE;
- bd->bi_sramsize = PPC405EP_SRAM_SIZE;
- bd->bi_bootflags = 0;
- bd->bi_intfreq = 133333333;
- bd->bi_busfreq = 33333333;
- bd->bi_baudrate = 115200;
- bd->bi_s_version[0] = 'Q';
- bd->bi_s_version[1] = 'M';
- bd->bi_s_version[2] = 'U';
- bd->bi_s_version[3] = '\0';
- bd->bi_r_version[0] = 'Q';
- bd->bi_r_version[1] = 'E';
- bd->bi_r_version[2] = 'M';
- bd->bi_r_version[3] = 'U';
- bd->bi_r_version[4] = '\0';
- bd->bi_procfreq = 133333333;
- bd->bi_plb_busfreq = 33333333;
- bd->bi_pci_busfreq = 33333333;
- bd->bi_opbfreq = 33333333;
-}
-
-static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd)
-{
- CPUState *cs = env_cpu(env);
- ram_addr_t bdloc;
- int i, n;
-
- /* We put the bd structure at the top of memory */
- if (bd->bi_memsize >= 0x01000000UL)
- bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
- else
- bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
- stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart);
- stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize);
- stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart);
- stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize);
- stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset);
- stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart);
- stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize);
- stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags);
- stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr);
- for (i = 0; i < 6; i++) {
- stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]);
- }
- stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
- stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
- stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
- stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
- for (i = 0; i < 4; i++) {
- stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]);
- }
- for (i = 0; i < 32; i++) {
- stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
- }
- stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_procfreq);
- stl_be_phys(cs->as, bdloc + 0x60, bd->bi_plb_busfreq);
- stl_be_phys(cs->as, bdloc + 0x64, bd->bi_pci_busfreq);
- for (i = 0; i < 6; i++) {
- stb_phys(cs->as, bdloc + 0x68 + i, bd->bi_pci_enetaddr[i]);
- }
- n = 0x70; /* includes 2 bytes hole */
- for (i = 0; i < 6; i++) {
- stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
- }
- stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq);
- n += 4;
- for (i = 0; i < 2; i++) {
- stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]);
- n += 4;
- }
-
- return bdloc;
-}
-
-ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size)
-{
- ppc4xx_bd_info_t bd;
-
- memset(&bd, 0, sizeof(bd));
-
- ppc405_set_default_bootinfo(&bd, ram_size);
-
- return __ppc405_set_bootinfo(env, &bd);
-}
-
/*****************************************************************************/
/* Shared peripherals */
--
2.30.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH 18/22] ppc405: Move machine specific code to ppc405_boards.c
2022-08-13 15:34 ` [PATCH 18/22] ppc405: Move machine specific code to ppc405_boards.c BALATON Zoltan
@ 2022-08-16 7:46 ` Cédric Le Goater
0 siblings, 0 replies; 37+ messages in thread
From: Cédric Le Goater @ 2022-08-16 7:46 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc
Cc: Daniel Henrique Barboza, Peter Maydell
On 8/13/22 17:34, BALATON Zoltan wrote:
> These are only used by tha board code so move out from the shared SoC
s/tha/the/
> model and put it in the boards file.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> hw/ppc/ppc405.h | 38 -----
> hw/ppc/ppc405_boards.c | 375 +++++++++++++++++++++++++++--------------
> hw/ppc/ppc405_uc.c | 92 ----------
> 3 files changed, 251 insertions(+), 254 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index 12eee97169..6b26fc6d17 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -30,41 +30,6 @@
> #include "hw/intc/ppc-uic.h"
> #include "hw/i2c/ppc4xx_i2c.h"
>
> -#define PPC405EP_SDRAM_BASE 0x00000000
> -#define PPC405EP_NVRAM_BASE 0xF0000000
> -#define PPC405EP_FPGA_BASE 0xF0300000
> -#define PPC405EP_SRAM_BASE 0xFFF00000
> -#define PPC405EP_SRAM_SIZE (512 * KiB)
> -#define PPC405EP_FLASH_BASE 0xFFF80000
> -
> -/* Bootinfo as set-up by u-boot */
> -typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t;
> -struct ppc4xx_bd_info_t {
> - uint32_t bi_memstart;
> - uint32_t bi_memsize;
> - uint32_t bi_flashstart;
> - uint32_t bi_flashsize;
> - uint32_t bi_flashoffset; /* 0x10 */
> - uint32_t bi_sramstart;
> - uint32_t bi_sramsize;
> - uint32_t bi_bootflags;
> - uint32_t bi_ipaddr; /* 0x20 */
> - uint8_t bi_enetaddr[6];
> - uint16_t bi_ethspeed;
> - uint32_t bi_intfreq;
> - uint32_t bi_busfreq; /* 0x30 */
> - uint32_t bi_baudrate;
> - uint8_t bi_s_version[4];
> - uint8_t bi_r_version[32];
> - uint32_t bi_procfreq;
> - uint32_t bi_plb_busfreq;
> - uint32_t bi_pci_busfreq;
> - uint8_t bi_pci_enetaddr[6];
> - uint8_t bi_pci_enetaddr2[6]; /* PPC405EP specific */
> - uint32_t bi_opbfreq;
> - uint32_t bi_iic_fast[2];
> -};
> -
> /* PLB to OPB bridge */
> #define TYPE_PPC405_POB "ppc405-pob"
> OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
> @@ -224,7 +189,4 @@ struct Ppc405SoCState {
> Ppc4xxMalState mal;
> };
>
> -/* PowerPC 405 core */
> -ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
> -
> #endif /* PPC405_H */
> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
> index 7af0d7feef..083f12b23e 100644
> --- a/hw/ppc/ppc405_boards.c
> +++ b/hw/ppc/ppc405_boards.c
> @@ -48,6 +48,10 @@
> #define KERNEL_LOAD_ADDR 0x01000000
> #define INITRD_LOAD_ADDR 0x01800000
>
> +#define PPC405EP_SDRAM_BASE 0x00000000
> +#define PPC405EP_SRAM_BASE 0xFFF00000
> +#define PPC405EP_SRAM_SIZE (512 * KiB)
> +
> #define USE_FLASH_BIOS
>
> #define TYPE_PPC405_MACHINE MACHINE_TYPE_NAME("ppc405")
> @@ -61,112 +65,7 @@ struct Ppc405MachineState {
> Ppc405SoCState soc;
> };
>
> -/*****************************************************************************/
> -/* PPC405EP reference board (IBM) */
> -/* Standalone board with:
> - * - PowerPC 405EP CPU
> - * - SDRAM (0x00000000)
> - * - Flash (0xFFF80000)
> - * - SRAM (0xFFF00000)
> - * - NVRAM (0xF0000000)
> - * - FPGA (0xF0300000)
> - */
> -
> -#define TYPE_REF405EP_FPGA "ref405ep-fpga"
> -OBJECT_DECLARE_SIMPLE_TYPE(Ref405epFpgaState, REF405EP_FPGA);
> -struct Ref405epFpgaState {
> - SysBusDevice parent_obj;
> -
> - MemoryRegion iomem;
> -
> - uint8_t reg0;
> - uint8_t reg1;
> -};
> -
> -static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
> -{
> - Ref405epFpgaState *fpga = opaque;
> - uint32_t ret;
> -
> - switch (addr) {
> - case 0x0:
> - ret = fpga->reg0;
> - break;
> - case 0x1:
> - ret = fpga->reg1;
> - break;
> - default:
> - ret = 0;
> - break;
> - }
> -
> - return ret;
> -}
> -
> -static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
> - unsigned size)
> -{
> - Ref405epFpgaState *fpga = opaque;
> -
> - switch (addr) {
> - case 0x0:
> - /* Read only */
> - break;
> - case 0x1:
> - fpga->reg1 = value;
> - break;
> - default:
> - break;
> - }
> -}
> -
> -static const MemoryRegionOps ref405ep_fpga_ops = {
> - .read = ref405ep_fpga_readb,
> - .write = ref405ep_fpga_writeb,
> - .impl.min_access_size = 1,
> - .impl.max_access_size = 1,
> - .valid.min_access_size = 1,
> - .valid.max_access_size = 4,
> - .endianness = DEVICE_BIG_ENDIAN,
> -};
> -
> -static void ref405ep_fpga_reset(DeviceState *dev)
> -{
> - Ref405epFpgaState *fpga = REF405EP_FPGA(dev);
> -
> - fpga->reg0 = 0x00;
> - fpga->reg1 = 0x0F;
> -}
> -
> -static void ref405ep_fpga_realize(DeviceState *dev, Error **errp)
> -{
> - Ref405epFpgaState *s = REF405EP_FPGA(dev);
> -
> - memory_region_init_io(&s->iomem, OBJECT(s), &ref405ep_fpga_ops, s,
> - "fpga", 0x00000100);
> - sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
> -}
> -
> -static void ref405ep_fpga_class_init(ObjectClass *oc, void *data)
> -{
> - DeviceClass *dc = DEVICE_CLASS(oc);
> -
> - dc->realize = ref405ep_fpga_realize;
> - dc->reset = ref405ep_fpga_reset;
> - /* Reason: only works as part of a ppc405 board */
> - dc->user_creatable = false;
> -}
> -
> -static const TypeInfo ref405ep_fpga_type = {
> - .name = TYPE_REF405EP_FPGA,
> - .parent = TYPE_SYS_BUS_DEVICE,
> - .instance_size = sizeof(Ref405epFpgaState),
> - .class_init = ref405ep_fpga_class_init,
> -};
> -
> -/*
> - * CPU reset handler when booting directly from a loaded kernel
> - */
> +/* CPU reset handler when booting directly from a loaded kernel */
> static struct boot_info {
> uint32_t entry;
> uint32_t bdloc;
> @@ -197,6 +96,126 @@ static void main_cpu_reset(void *opaque)
> env->nip = bi->entry;
> }
>
> +/* Bootinfo as set-up by u-boot */
> +typedef struct {
> + uint32_t bi_memstart;
> + uint32_t bi_memsize;
> + uint32_t bi_flashstart;
> + uint32_t bi_flashsize;
> + uint32_t bi_flashoffset; /* 0x10 */
> + uint32_t bi_sramstart;
> + uint32_t bi_sramsize;
> + uint32_t bi_bootflags;
> + uint32_t bi_ipaddr; /* 0x20 */
> + uint8_t bi_enetaddr[6];
> + uint16_t bi_ethspeed;
> + uint32_t bi_intfreq;
> + uint32_t bi_busfreq; /* 0x30 */
> + uint32_t bi_baudrate;
> + uint8_t bi_s_version[4];
> + uint8_t bi_r_version[32];
> + uint32_t bi_procfreq;
> + uint32_t bi_plb_busfreq;
> + uint32_t bi_pci_busfreq;
> + uint8_t bi_pci_enetaddr[6];
> + uint8_t bi_pci_enetaddr2[6]; /* PPC405EP specific */
> + uint32_t bi_opbfreq;
> + uint32_t bi_iic_fast[2];
> +} ppc4xx_bd_info_t;
> +
> +static void ppc405_set_default_bootinfo(ppc4xx_bd_info_t *bd,
> + ram_addr_t ram_size)
> +{
> + memset(bd, 0, sizeof(*bd));
> +
> + bd->bi_memstart = PPC405EP_SDRAM_BASE;
> + bd->bi_memsize = ram_size;
> + bd->bi_sramstart = PPC405EP_SRAM_BASE;
> + bd->bi_sramsize = PPC405EP_SRAM_SIZE;
> + bd->bi_bootflags = 0;
> + bd->bi_intfreq = 133333333;
> + bd->bi_busfreq = 33333333;
> + bd->bi_baudrate = 115200;
> + bd->bi_s_version[0] = 'Q';
> + bd->bi_s_version[1] = 'M';
> + bd->bi_s_version[2] = 'U';
> + bd->bi_s_version[3] = '\0';
> + bd->bi_r_version[0] = 'Q';
> + bd->bi_r_version[1] = 'E';
> + bd->bi_r_version[2] = 'M';
> + bd->bi_r_version[3] = 'U';
> + bd->bi_r_version[4] = '\0';
> + bd->bi_procfreq = 133333333;
> + bd->bi_plb_busfreq = 33333333;
> + bd->bi_pci_busfreq = 33333333;
> + bd->bi_opbfreq = 33333333;
> +}
> +
> +static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd)
> +{
> + CPUState *cs = env_cpu(env);
> + ram_addr_t bdloc;
> + int i, n;
> +
> + /* We put the bd structure at the top of memory */
> + if (bd->bi_memsize >= 0x01000000UL) {
> + bdloc = 0x01000000UL - sizeof(ppc4xx_bd_info_t);
> + } else {
> + bdloc = bd->bi_memsize - sizeof(ppc4xx_bd_info_t);
> + }
> + stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart);
> + stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize);
> + stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart);
> + stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize);
> + stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset);
> + stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart);
> + stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize);
> + stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags);
> + stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr);
> + for (i = 0; i < 6; i++) {
> + stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]);
> + }
> + stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
> + stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
> + stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
> + stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
> + for (i = 0; i < 4; i++) {
> + stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]);
> + }
> + for (i = 0; i < 32; i++) {
> + stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
> + }
> + stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_procfreq);
> + stl_be_phys(cs->as, bdloc + 0x60, bd->bi_plb_busfreq);
> + stl_be_phys(cs->as, bdloc + 0x64, bd->bi_pci_busfreq);
> + for (i = 0; i < 6; i++) {
> + stb_phys(cs->as, bdloc + 0x68 + i, bd->bi_pci_enetaddr[i]);
> + }
> + n = 0x70; /* includes 2 bytes hole */
> + for (i = 0; i < 6; i++) {
> + stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
> + }
> + stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq);
> + n += 4;
> + for (i = 0; i < 2; i++) {
> + stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]);
> + n += 4;
> + }
> +
> + return bdloc;
> +}
> +
> +static ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size)
> +{
> + ppc4xx_bd_info_t bd;
> +
> + memset(&bd, 0, sizeof(bd));
> +
> + ppc405_set_default_bootinfo(&bd, ram_size);
> +
> + return __ppc405_set_bootinfo(env, &bd);
> +}
> +
> static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu)
> {
> CPUPPCState *env = &cpu->env;
> @@ -334,6 +353,132 @@ static void ppc405_init(MachineState *machine)
> }
> }
>
> +static void ppc405_machine_class_init(ObjectClass *oc, void *data)
> +{
> + MachineClass *mc = MACHINE_CLASS(oc);
> +
> + mc->desc = "PPC405 generic machine";
> + mc->init = ppc405_init;
> + mc->default_ram_size = 128 * MiB;
> + mc->default_ram_id = "ppc405.ram";
> +}
> +
> +static const TypeInfo ppc405_machine_type = {
> + .name = TYPE_PPC405_MACHINE,
> + .parent = TYPE_MACHINE,
> + .instance_size = sizeof(Ppc405MachineState),
> + .class_init = ppc405_machine_class_init,
> + .abstract = true,
> +};
> +
> +/*****************************************************************************/
> +/* PPC405EP reference board (IBM) */
> +/*
> + * Standalone board with:
> + * - PowerPC 405EP CPU
> + * - SDRAM (0x00000000)
> + * - Flash (0xFFF80000)
> + * - SRAM (0xFFF00000)
> + * - NVRAM (0xF0000000)
> + * - FPGA (0xF0300000)
> + */
> +
> +#define PPC405EP_NVRAM_BASE 0xF0000000
> +#define PPC405EP_FPGA_BASE 0xF0300000
> +#define PPC405EP_FLASH_BASE 0xFFF80000
> +
> +#define TYPE_REF405EP_FPGA "ref405ep-fpga"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ref405epFpgaState, REF405EP_FPGA);
> +struct Ref405epFpgaState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion iomem;
> +
> + uint8_t reg0;
> + uint8_t reg1;
> +};
> +
> +static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
> +{
> + Ref405epFpgaState *fpga = opaque;
> + uint32_t ret;
> +
> + switch (addr) {
> + case 0x0:
> + ret = fpga->reg0;
> + break;
> + case 0x1:
> + ret = fpga->reg1;
> + break;
> + default:
> + ret = 0;
> + break;
> + }
> +
> + return ret;
> +}
> +
> +static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
> + unsigned size)
> +{
> + Ref405epFpgaState *fpga = opaque;
> +
> + switch (addr) {
> + case 0x0:
> + /* Read only */
> + break;
> + case 0x1:
> + fpga->reg1 = value;
> + break;
> + default:
> + break;
> + }
> +}
> +
> +static const MemoryRegionOps ref405ep_fpga_ops = {
> + .read = ref405ep_fpga_readb,
> + .write = ref405ep_fpga_writeb,
> + .impl.min_access_size = 1,
> + .impl.max_access_size = 1,
> + .valid.min_access_size = 1,
> + .valid.max_access_size = 4,
> + .endianness = DEVICE_BIG_ENDIAN,
> +};
> +
> +static void ref405ep_fpga_reset(DeviceState *dev)
> +{
> + Ref405epFpgaState *fpga = REF405EP_FPGA(dev);
> +
> + fpga->reg0 = 0x00;
> + fpga->reg1 = 0x0F;
> +}
> +
> +static void ref405ep_fpga_realize(DeviceState *dev, Error **errp)
> +{
> + Ref405epFpgaState *s = REF405EP_FPGA(dev);
> +
> + memory_region_init_io(&s->iomem, OBJECT(s), &ref405ep_fpga_ops, s,
> + "fpga", 0x00000100);
> + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
> +}
> +
> +static void ref405ep_fpga_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = ref405ep_fpga_realize;
> + dc->reset = ref405ep_fpga_reset;
> + /* Reason: only works as part of a ppc405 board */
> + dc->user_creatable = false;
> +}
> +
> +static const TypeInfo ref405ep_fpga_type = {
> + .name = TYPE_REF405EP_FPGA,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(Ref405epFpgaState),
> + .class_init = ref405ep_fpga_class_init,
> +};
> +
> static void ref405ep_init(MachineState *machine)
> {
> DeviceState *dev;
> @@ -375,24 +520,6 @@ static const TypeInfo ref405ep_type = {
> .class_init = ref405ep_class_init,
> };
>
> -static void ppc405_machine_class_init(ObjectClass *oc, void *data)
> -{
> - MachineClass *mc = MACHINE_CLASS(oc);
> -
> - mc->desc = "PPC405 generic machine";
> - mc->init = ppc405_init;
> - mc->default_ram_size = 128 * MiB;
> - mc->default_ram_id = "ppc405.ram";
> -}
> -
> -static const TypeInfo ppc405_machine_type = {
> - .name = TYPE_PPC405_MACHINE,
> - .parent = TYPE_MACHINE,
> - .instance_size = sizeof(Ppc405MachineState),
> - .class_init = ppc405_machine_class_init,
> - .abstract = true,
> -};
> -
> static void ppc405_machine_init(void)
> {
> type_register_static(&ppc405_machine_type);
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index a7a7d7e65b..b13026200f 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -42,98 +42,6 @@
> #include "qapi/error.h"
> #include "trace.h"
>
> -static void ppc405_set_default_bootinfo(ppc4xx_bd_info_t *bd,
> - ram_addr_t ram_size)
> -{
> - memset(bd, 0, sizeof(*bd));
> -
> - bd->bi_memstart = PPC405EP_SDRAM_BASE;
> - bd->bi_memsize = ram_size;
> - bd->bi_sramstart = PPC405EP_SRAM_BASE;
> - bd->bi_sramsize = PPC405EP_SRAM_SIZE;
> - bd->bi_bootflags = 0;
> - bd->bi_intfreq = 133333333;
> - bd->bi_busfreq = 33333333;
> - bd->bi_baudrate = 115200;
> - bd->bi_s_version[0] = 'Q';
> - bd->bi_s_version[1] = 'M';
> - bd->bi_s_version[2] = 'U';
> - bd->bi_s_version[3] = '\0';
> - bd->bi_r_version[0] = 'Q';
> - bd->bi_r_version[1] = 'E';
> - bd->bi_r_version[2] = 'M';
> - bd->bi_r_version[3] = 'U';
> - bd->bi_r_version[4] = '\0';
> - bd->bi_procfreq = 133333333;
> - bd->bi_plb_busfreq = 33333333;
> - bd->bi_pci_busfreq = 33333333;
> - bd->bi_opbfreq = 33333333;
> -}
> -
> -static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd)
> -{
> - CPUState *cs = env_cpu(env);
> - ram_addr_t bdloc;
> - int i, n;
> -
> - /* We put the bd structure at the top of memory */
> - if (bd->bi_memsize >= 0x01000000UL)
> - bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
> - else
> - bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
> - stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart);
> - stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize);
> - stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart);
> - stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize);
> - stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset);
> - stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart);
> - stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize);
> - stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags);
> - stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr);
> - for (i = 0; i < 6; i++) {
> - stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]);
> - }
> - stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
> - stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
> - stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
> - stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
> - for (i = 0; i < 4; i++) {
> - stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]);
> - }
> - for (i = 0; i < 32; i++) {
> - stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
> - }
> - stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_procfreq);
> - stl_be_phys(cs->as, bdloc + 0x60, bd->bi_plb_busfreq);
> - stl_be_phys(cs->as, bdloc + 0x64, bd->bi_pci_busfreq);
> - for (i = 0; i < 6; i++) {
> - stb_phys(cs->as, bdloc + 0x68 + i, bd->bi_pci_enetaddr[i]);
> - }
> - n = 0x70; /* includes 2 bytes hole */
> - for (i = 0; i < 6; i++) {
> - stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
> - }
> - stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq);
> - n += 4;
> - for (i = 0; i < 2; i++) {
> - stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]);
> - n += 4;
> - }
> -
> - return bdloc;
> -}
> -
> -ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size)
> -{
> - ppc4xx_bd_info_t bd;
> -
> - memset(&bd, 0, sizeof(bd));
> -
> - ppc405_set_default_bootinfo(&bd, ram_size);
> -
> - return __ppc405_set_bootinfo(env, &bd);
> -}
> -
> /*****************************************************************************/
> /* Shared peripherals */
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 19/22] hw/ppc/Kconfig: Remove PPC405 dependency from sam460ex
2022-08-13 15:34 [PATCH 00/22] QOMify PPC4xx devices and minor clean ups BALATON Zoltan
` (17 preceding siblings ...)
2022-08-13 15:34 ` [PATCH 18/22] ppc405: Move machine specific code to ppc405_boards.c BALATON Zoltan
@ 2022-08-13 15:34 ` BALATON Zoltan
2022-08-16 7:39 ` Cédric Le Goater
2022-08-13 15:34 ` [PATCH 20/22] hw/ppc/Kconfig: Move imply before select BALATON Zoltan
` (3 subsequent siblings)
22 siblings, 1 reply; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-13 15:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Now that shared PPC4xx devices are separated from PPC405 ones we can
drop this depencency.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index 400511c6b7..205f9f98d7 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -58,7 +58,6 @@ config PPC4XX
config SAM460EX
bool
- select PPC405
select PFLASH_CFI01
select IDE_SII3112
select M41T80
--
2.30.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH 19/22] hw/ppc/Kconfig: Remove PPC405 dependency from sam460ex
2022-08-13 15:34 ` [PATCH 19/22] hw/ppc/Kconfig: Remove PPC405 dependency from sam460ex BALATON Zoltan
@ 2022-08-16 7:39 ` Cédric Le Goater
0 siblings, 0 replies; 37+ messages in thread
From: Cédric Le Goater @ 2022-08-16 7:39 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc
Cc: Daniel Henrique Barboza, Peter Maydell
On 8/13/22 17:34, BALATON Zoltan wrote:
> Now that shared PPC4xx devices are separated from PPC405 ones we can
> drop this depencency.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> hw/ppc/Kconfig | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
> index 400511c6b7..205f9f98d7 100644
> --- a/hw/ppc/Kconfig
> +++ b/hw/ppc/Kconfig
> @@ -58,7 +58,6 @@ config PPC4XX
>
> config SAM460EX
> bool
> - select PPC405
> select PFLASH_CFI01
> select IDE_SII3112
> select M41T80
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 20/22] hw/ppc/Kconfig: Move imply before select
2022-08-13 15:34 [PATCH 00/22] QOMify PPC4xx devices and minor clean ups BALATON Zoltan
` (18 preceding siblings ...)
2022-08-13 15:34 ` [PATCH 19/22] hw/ppc/Kconfig: Remove PPC405 dependency from sam460ex BALATON Zoltan
@ 2022-08-13 15:34 ` BALATON Zoltan
2022-08-16 7:39 ` Cédric Le Goater
2022-08-13 15:34 ` [PATCH 21/22] ppc4xx: Drop empty default cases BALATON Zoltan
` (2 subsequent siblings)
22 siblings, 1 reply; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-13 15:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
In pegasos2 section move imply before select to match other sections.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index 205f9f98d7..3a4418a69e 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -71,6 +71,7 @@ config SAM460EX
config PEGASOS2
bool
+ imply ATI_VGA
select MV64361
select VT82C686
select IDE_VIA
@@ -78,7 +79,6 @@ config PEGASOS2
select VOF
# This should come with VT82C686
select ACPI_X86
- imply ATI_VGA
config PREP
bool
--
2.30.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH 20/22] hw/ppc/Kconfig: Move imply before select
2022-08-13 15:34 ` [PATCH 20/22] hw/ppc/Kconfig: Move imply before select BALATON Zoltan
@ 2022-08-16 7:39 ` Cédric Le Goater
0 siblings, 0 replies; 37+ messages in thread
From: Cédric Le Goater @ 2022-08-16 7:39 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc
Cc: Daniel Henrique Barboza, Peter Maydell
On 8/13/22 17:34, BALATON Zoltan wrote:
> In pegasos2 section move imply before select to match other sections.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> hw/ppc/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
> index 205f9f98d7..3a4418a69e 100644
> --- a/hw/ppc/Kconfig
> +++ b/hw/ppc/Kconfig
> @@ -71,6 +71,7 @@ config SAM460EX
>
> config PEGASOS2
> bool
> + imply ATI_VGA
> select MV64361
> select VT82C686
> select IDE_VIA
> @@ -78,7 +79,6 @@ config PEGASOS2
> select VOF
> # This should come with VT82C686
> select ACPI_X86
> - imply ATI_VGA
>
> config PREP
> bool
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 21/22] ppc4xx: Drop empty default cases
2022-08-13 15:34 [PATCH 00/22] QOMify PPC4xx devices and minor clean ups BALATON Zoltan
` (19 preceding siblings ...)
2022-08-13 15:34 ` [PATCH 20/22] hw/ppc/Kconfig: Move imply before select BALATON Zoltan
@ 2022-08-13 15:34 ` BALATON Zoltan
2022-08-16 11:18 ` Cédric Le Goater
2022-08-13 15:34 ` [PATCH 22/22] ppc/ppc4xx: Fix sdram trace events BALATON Zoltan
2022-08-16 11:19 ` [PATCH 00/22] QOMify PPC4xx devices and minor clean ups Cédric Le Goater
22 siblings, 1 reply; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-13 15:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Remove default case labels that do nothing or only there to set a
default value that could easily be done at the variable definition
instead.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc405_boards.c | 7 +------
hw/ppc/ppc405_uc.c | 29 +++++------------------------
hw/ppc/ppc440_uc.c | 27 ---------------------------
hw/ppc/ppc4xx_devs.c | 31 ++++---------------------------
4 files changed, 10 insertions(+), 84 deletions(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 083f12b23e..a876b4af85 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -401,7 +401,7 @@ struct Ref405epFpgaState {
static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
{
Ref405epFpgaState *fpga = opaque;
- uint32_t ret;
+ uint32_t ret = 0;
switch (addr) {
case 0x0:
@@ -410,9 +410,6 @@ static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
case 0x1:
ret = fpga->reg1;
break;
- default:
- ret = 0;
- break;
}
return ret;
@@ -430,8 +427,6 @@ static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
case 0x1:
fpga->reg1 = value;
break;
- default:
- break;
}
}
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index b13026200f..6c84d87330 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -56,7 +56,7 @@ enum {
static uint32_t dcr_read_pob(void *opaque, int dcrn)
{
Ppc405PobState *pob = opaque;
- uint32_t ret;
+ uint32_t ret = 0;
switch (dcrn) {
case POB0_BEAR:
@@ -68,10 +68,6 @@ static uint32_t dcr_read_pob(void *opaque, int dcrn)
case POB0_BESR1:
ret = pob->besr1;
break;
- default:
- /* Avoid gcc warning */
- ret = 0;
- break;
}
return ret;
@@ -131,7 +127,7 @@ static void ppc405_pob_class_init(ObjectClass *oc, void *data)
static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
{
Ppc405OpbaState *opba = opaque;
- uint32_t ret;
+ uint32_t ret = 0;
switch (addr) {
case 0x00:
@@ -140,9 +136,6 @@ static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
case 0x01:
ret = opba->pr;
break;
- default:
- ret = 0x00;
- break;
}
trace_opba_readb(addr, ret);
@@ -163,8 +156,6 @@ static void opba_writeb(void *opaque, hwaddr addr, uint64_t value,
case 0x01:
opba->pr = value & 0xFF;
break;
- default:
- break;
}
}
static const MemoryRegionOps opba_ops = {
@@ -403,7 +394,7 @@ static void ocm_update_mappings(Ppc405OcmState *ocm,
static uint32_t dcr_read_ocm(void *opaque, int dcrn)
{
Ppc405OcmState *ocm = opaque;
- uint32_t ret;
+ uint32_t ret = 0;
switch (dcrn) {
case OCM0_ISARC:
@@ -418,9 +409,6 @@ static uint32_t dcr_read_ocm(void *opaque, int dcrn)
case OCM0_DSACNTL:
ret = ocm->dsacntl;
break;
- default:
- ret = 0;
- break;
}
return ret;
@@ -556,7 +544,7 @@ static void ppc4xx_gpt_compute_timer(Ppc405GptState *gpt)
static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
{
Ppc405GptState *gpt = opaque;
- uint32_t ret;
+ uint32_t ret = -1;
int idx;
trace_ppc4xx_gpt_read(addr, size);
@@ -598,9 +586,6 @@ static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
idx = (addr - 0xC0) >> 2;
ret = gpt->mask[idx];
break;
- default:
- ret = -1;
- break;
}
return ret;
@@ -844,7 +829,7 @@ static void ppc405ep_compute_clocks(Ppc405CpcState *cpc)
static uint32_t dcr_read_epcpc(void *opaque, int dcrn)
{
Ppc405CpcState *cpc = opaque;
- uint32_t ret;
+ uint32_t ret = 0;
switch (dcrn) {
case PPC405EP_CPC0_BOOT:
@@ -871,10 +856,6 @@ static uint32_t dcr_read_epcpc(void *opaque, int dcrn)
case PPC405EP_CPC0_PCI:
ret = cpc->pci;
break;
- default:
- /* Avoid gcc warning */
- ret = 0;
- break;
}
return ret;
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 11fdb88c22..b390672bce 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -147,9 +147,6 @@ static uint32_t dcr_read_l2sram(void *opaque, int dcrn)
case DCR_ISRAM0_DPC:
ret = l2sram->isram0[dcrn - DCR_ISRAM0_BASE];
break;
-
- default:
- break;
}
return ret;
@@ -304,12 +301,8 @@ static uint32_t dcr_read_cpr(void *opaque, int dcrn)
case CPR0_AHBD:
ret = (1 << 24);
break;
- default:
- break;
}
break;
- default:
- break;
}
return ret;
@@ -325,8 +318,6 @@ static void dcr_write_cpr(void *opaque, int dcrn, uint32_t val)
break;
case CPR0_CFGDATA:
break;
- default:
- break;
}
}
@@ -421,12 +412,8 @@ static uint32_t dcr_read_sdr(void *opaque, int dcrn)
case PESDR1_LOOP:
ret = 1 << 12;
break;
- default:
- break;
}
break;
- default:
- break;
}
return ret;
@@ -444,12 +431,8 @@ static void dcr_write_sdr(void *opaque, int dcrn, uint32_t val)
switch (sdr->addr) {
case 0x00: /* B0CR */
break;
- default:
- break;
}
break;
- default:
- break;
}
}
@@ -646,12 +629,8 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
case 0xE1: /* SDR0_DDR0 */
ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1;
break;
- default:
- break;
}
break;
- default:
- break;
}
return ret;
@@ -679,12 +658,8 @@ static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
switch (sdram->addr) {
case 0x00: /* B0CR */
break;
- default:
- break;
}
break;
- default:
- break;
}
}
@@ -760,8 +735,6 @@ static uint32_t dcr_read_ahb(void *opaque, int dcrn)
case AHB_BOT:
ret = ahb->bot;
break;
- default:
- break;
}
return ret;
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 49793b56cd..f5806f06e7 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -182,7 +182,7 @@ static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
static uint32_t dcr_read_sdram (void *opaque, int dcrn)
{
ppc4xx_sdram_t *sdram;
- uint32_t ret;
+ uint32_t ret = 0;
sdram = opaque;
switch (dcrn) {
@@ -238,10 +238,6 @@ static uint32_t dcr_read_sdram (void *opaque, int dcrn)
break;
}
break;
- default:
- /* Avoid gcc warning */
- ret = 0x00000000;
- break;
}
return ret;
@@ -321,8 +317,6 @@ static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val)
qemu_irq_lower(sdram->irq);
sdram->eccesr = val;
break;
- default: /* Error */
- break;
}
break;
}
@@ -476,7 +470,7 @@ static void ppc4xx_mal_reset(DeviceState *dev)
static uint32_t dcr_read_mal(void *opaque, int dcrn)
{
Ppc4xxMalState *mal = opaque;
- uint32_t ret;
+ uint32_t ret = 0;
switch (dcrn) {
case MAL0_CFG:
@@ -512,9 +506,6 @@ static uint32_t dcr_read_mal(void *opaque, int dcrn)
case MAL0_RXDEIR:
ret = mal->rxdeir;
break;
- default:
- ret = 0;
- break;
}
if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) {
ret = mal->txctpr[dcrn - MAL0_TXCTP0R];
@@ -671,7 +662,7 @@ enum {
static uint32_t dcr_read_plb(void *opaque, int dcrn)
{
Ppc405PlbState *plb = opaque;
- uint32_t ret;
+ uint32_t ret = 0;
switch (dcrn) {
case PLB0_ACR:
@@ -683,10 +674,6 @@ static uint32_t dcr_read_plb(void *opaque, int dcrn)
case PLB0_BESR:
ret = plb->besr;
break;
- default:
- /* Avoid gcc warning */
- ret = 0;
- break;
}
return ret;
@@ -756,7 +743,7 @@ enum {
static uint32_t dcr_read_ebc(void *opaque, int dcrn)
{
Ppc405EbcState *ebc = opaque;
- uint32_t ret;
+ uint32_t ret = 0;
switch (dcrn) {
case EBC0_CFGADDR:
@@ -824,14 +811,8 @@ static uint32_t dcr_read_ebc(void *opaque, int dcrn)
case 0x23: /* CFG */
ret = ebc->cfg;
break;
- default:
- ret = 0x00000000;
- break;
}
break;
- default:
- ret = 0x00000000;
- break;
}
return ret;
@@ -887,12 +868,8 @@ static void dcr_write_ebc(void *opaque, int dcrn, uint32_t val)
break;
case 0x23: /* CFG */
break;
- default:
- break;
}
break;
- default:
- break;
}
}
--
2.30.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH 21/22] ppc4xx: Drop empty default cases
2022-08-13 15:34 ` [PATCH 21/22] ppc4xx: Drop empty default cases BALATON Zoltan
@ 2022-08-16 11:18 ` Cédric Le Goater
2022-08-16 11:59 ` BALATON Zoltan
0 siblings, 1 reply; 37+ messages in thread
From: Cédric Le Goater @ 2022-08-16 11:18 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc
Cc: Daniel Henrique Barboza, Peter Maydell
On 8/13/22 17:34, BALATON Zoltan wrote:
> Remove default case labels that do nothing or only there to set a
> default value that could easily be done at the variable definition
> instead.
May be instead, the default case labels deserve a LOG_GUEST_ERROR or
a UNIMP or even g_assert_not_reached() ?
C.
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> hw/ppc/ppc405_boards.c | 7 +------
> hw/ppc/ppc405_uc.c | 29 +++++------------------------
> hw/ppc/ppc440_uc.c | 27 ---------------------------
> hw/ppc/ppc4xx_devs.c | 31 ++++---------------------------
> 4 files changed, 10 insertions(+), 84 deletions(-)
>
> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
> index 083f12b23e..a876b4af85 100644
> --- a/hw/ppc/ppc405_boards.c
> +++ b/hw/ppc/ppc405_boards.c
> @@ -401,7 +401,7 @@ struct Ref405epFpgaState {
> static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
> {
> Ref405epFpgaState *fpga = opaque;
> - uint32_t ret;
> + uint32_t ret = 0;
>
> switch (addr) {
> case 0x0:
> @@ -410,9 +410,6 @@ static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
> case 0x1:
> ret = fpga->reg1;
> break;
> - default:
> - ret = 0;
> - break;
> }
>
> return ret;
> @@ -430,8 +427,6 @@ static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
> case 0x1:
> fpga->reg1 = value;
> break;
> - default:
> - break;
> }
> }
>
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index b13026200f..6c84d87330 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -56,7 +56,7 @@ enum {
> static uint32_t dcr_read_pob(void *opaque, int dcrn)
> {
> Ppc405PobState *pob = opaque;
> - uint32_t ret;
> + uint32_t ret = 0;
>
> switch (dcrn) {
> case POB0_BEAR:
> @@ -68,10 +68,6 @@ static uint32_t dcr_read_pob(void *opaque, int dcrn)
> case POB0_BESR1:
> ret = pob->besr1;
> break;
> - default:
> - /* Avoid gcc warning */
> - ret = 0;
> - break;
> }
>
> return ret;
> @@ -131,7 +127,7 @@ static void ppc405_pob_class_init(ObjectClass *oc, void *data)
> static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
> {
> Ppc405OpbaState *opba = opaque;
> - uint32_t ret;
> + uint32_t ret = 0;
>
> switch (addr) {
> case 0x00:
> @@ -140,9 +136,6 @@ static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
> case 0x01:
> ret = opba->pr;
> break;
> - default:
> - ret = 0x00;
> - break;
> }
>
> trace_opba_readb(addr, ret);
> @@ -163,8 +156,6 @@ static void opba_writeb(void *opaque, hwaddr addr, uint64_t value,
> case 0x01:
> opba->pr = value & 0xFF;
> break;
> - default:
> - break;
> }
> }
> static const MemoryRegionOps opba_ops = {
> @@ -403,7 +394,7 @@ static void ocm_update_mappings(Ppc405OcmState *ocm,
> static uint32_t dcr_read_ocm(void *opaque, int dcrn)
> {
> Ppc405OcmState *ocm = opaque;
> - uint32_t ret;
> + uint32_t ret = 0;
>
> switch (dcrn) {
> case OCM0_ISARC:
> @@ -418,9 +409,6 @@ static uint32_t dcr_read_ocm(void *opaque, int dcrn)
> case OCM0_DSACNTL:
> ret = ocm->dsacntl;
> break;
> - default:
> - ret = 0;
> - break;
> }
>
> return ret;
> @@ -556,7 +544,7 @@ static void ppc4xx_gpt_compute_timer(Ppc405GptState *gpt)
> static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
> {
> Ppc405GptState *gpt = opaque;
> - uint32_t ret;
> + uint32_t ret = -1;
> int idx;
>
> trace_ppc4xx_gpt_read(addr, size);
> @@ -598,9 +586,6 @@ static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
> idx = (addr - 0xC0) >> 2;
> ret = gpt->mask[idx];
> break;
> - default:
> - ret = -1;
> - break;
> }
>
> return ret;
> @@ -844,7 +829,7 @@ static void ppc405ep_compute_clocks(Ppc405CpcState *cpc)
> static uint32_t dcr_read_epcpc(void *opaque, int dcrn)
> {
> Ppc405CpcState *cpc = opaque;
> - uint32_t ret;
> + uint32_t ret = 0;
>
> switch (dcrn) {
> case PPC405EP_CPC0_BOOT:
> @@ -871,10 +856,6 @@ static uint32_t dcr_read_epcpc(void *opaque, int dcrn)
> case PPC405EP_CPC0_PCI:
> ret = cpc->pci;
> break;
> - default:
> - /* Avoid gcc warning */
> - ret = 0;
> - break;
> }
>
> return ret;
> diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
> index 11fdb88c22..b390672bce 100644
> --- a/hw/ppc/ppc440_uc.c
> +++ b/hw/ppc/ppc440_uc.c
> @@ -147,9 +147,6 @@ static uint32_t dcr_read_l2sram(void *opaque, int dcrn)
> case DCR_ISRAM0_DPC:
> ret = l2sram->isram0[dcrn - DCR_ISRAM0_BASE];
> break;
> -
> - default:
> - break;
> }
>
> return ret;
> @@ -304,12 +301,8 @@ static uint32_t dcr_read_cpr(void *opaque, int dcrn)
> case CPR0_AHBD:
> ret = (1 << 24);
> break;
> - default:
> - break;
> }
> break;
> - default:
> - break;
> }
>
> return ret;
> @@ -325,8 +318,6 @@ static void dcr_write_cpr(void *opaque, int dcrn, uint32_t val)
> break;
> case CPR0_CFGDATA:
> break;
> - default:
> - break;
> }
> }
>
> @@ -421,12 +412,8 @@ static uint32_t dcr_read_sdr(void *opaque, int dcrn)
> case PESDR1_LOOP:
> ret = 1 << 12;
> break;
> - default:
> - break;
> }
> break;
> - default:
> - break;
> }
>
> return ret;
> @@ -444,12 +431,8 @@ static void dcr_write_sdr(void *opaque, int dcrn, uint32_t val)
> switch (sdr->addr) {
> case 0x00: /* B0CR */
> break;
> - default:
> - break;
> }
> break;
> - default:
> - break;
> }
> }
>
> @@ -646,12 +629,8 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
> case 0xE1: /* SDR0_DDR0 */
> ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1;
> break;
> - default:
> - break;
> }
> break;
> - default:
> - break;
> }
>
> return ret;
> @@ -679,12 +658,8 @@ static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
> switch (sdram->addr) {
> case 0x00: /* B0CR */
> break;
> - default:
> - break;
> }
> break;
> - default:
> - break;
> }
> }
>
> @@ -760,8 +735,6 @@ static uint32_t dcr_read_ahb(void *opaque, int dcrn)
> case AHB_BOT:
> ret = ahb->bot;
> break;
> - default:
> - break;
> }
>
> return ret;
> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
> index 49793b56cd..f5806f06e7 100644
> --- a/hw/ppc/ppc4xx_devs.c
> +++ b/hw/ppc/ppc4xx_devs.c
> @@ -182,7 +182,7 @@ static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
> static uint32_t dcr_read_sdram (void *opaque, int dcrn)
> {
> ppc4xx_sdram_t *sdram;
> - uint32_t ret;
> + uint32_t ret = 0;
>
> sdram = opaque;
> switch (dcrn) {
> @@ -238,10 +238,6 @@ static uint32_t dcr_read_sdram (void *opaque, int dcrn)
> break;
> }
> break;
> - default:
> - /* Avoid gcc warning */
> - ret = 0x00000000;
> - break;
> }
>
> return ret;
> @@ -321,8 +317,6 @@ static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val)
> qemu_irq_lower(sdram->irq);
> sdram->eccesr = val;
> break;
> - default: /* Error */
> - break;
> }
> break;
> }
> @@ -476,7 +470,7 @@ static void ppc4xx_mal_reset(DeviceState *dev)
> static uint32_t dcr_read_mal(void *opaque, int dcrn)
> {
> Ppc4xxMalState *mal = opaque;
> - uint32_t ret;
> + uint32_t ret = 0;
>
> switch (dcrn) {
> case MAL0_CFG:
> @@ -512,9 +506,6 @@ static uint32_t dcr_read_mal(void *opaque, int dcrn)
> case MAL0_RXDEIR:
> ret = mal->rxdeir;
> break;
> - default:
> - ret = 0;
> - break;
> }
> if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) {
> ret = mal->txctpr[dcrn - MAL0_TXCTP0R];
> @@ -671,7 +662,7 @@ enum {
> static uint32_t dcr_read_plb(void *opaque, int dcrn)
> {
> Ppc405PlbState *plb = opaque;
> - uint32_t ret;
> + uint32_t ret = 0;
>
> switch (dcrn) {
> case PLB0_ACR:
> @@ -683,10 +674,6 @@ static uint32_t dcr_read_plb(void *opaque, int dcrn)
> case PLB0_BESR:
> ret = plb->besr;
> break;
> - default:
> - /* Avoid gcc warning */
> - ret = 0;
> - break;
> }
>
> return ret;
> @@ -756,7 +743,7 @@ enum {
> static uint32_t dcr_read_ebc(void *opaque, int dcrn)
> {
> Ppc405EbcState *ebc = opaque;
> - uint32_t ret;
> + uint32_t ret = 0;
>
> switch (dcrn) {
> case EBC0_CFGADDR:
> @@ -824,14 +811,8 @@ static uint32_t dcr_read_ebc(void *opaque, int dcrn)
> case 0x23: /* CFG */
> ret = ebc->cfg;
> break;
> - default:
> - ret = 0x00000000;
> - break;
> }
> break;
> - default:
> - ret = 0x00000000;
> - break;
> }
>
> return ret;
> @@ -887,12 +868,8 @@ static void dcr_write_ebc(void *opaque, int dcrn, uint32_t val)
> break;
> case 0x23: /* CFG */
> break;
> - default:
> - break;
> }
> break;
> - default:
> - break;
> }
> }
>
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 21/22] ppc4xx: Drop empty default cases
2022-08-16 11:18 ` Cédric Le Goater
@ 2022-08-16 11:59 ` BALATON Zoltan
0 siblings, 0 replies; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-16 11:59 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 10709 bytes --]
On Tue, 16 Aug 2022, Cédric Le Goater wrote:
> On 8/13/22 17:34, BALATON Zoltan wrote:
>> Remove default case labels that do nothing or only there to set a
>> default value that could easily be done at the variable definition
>> instead.
>
> May be instead, the default case labels deserve a LOG_GUEST_ERROR or
> a UNIMP or even g_assert_not_reached() ?
g_assert_not_reached() is probably too much as a lot of these models may
be incomplete so I think that could cause crashes where it works now but
adding LOG_UNIMP could be useful to detect missing pieces.
Regards,
BALATON Zoltan
> C.
>
>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>> ---
>> hw/ppc/ppc405_boards.c | 7 +------
>> hw/ppc/ppc405_uc.c | 29 +++++------------------------
>> hw/ppc/ppc440_uc.c | 27 ---------------------------
>> hw/ppc/ppc4xx_devs.c | 31 ++++---------------------------
>> 4 files changed, 10 insertions(+), 84 deletions(-)
>>
>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>> index 083f12b23e..a876b4af85 100644
>> --- a/hw/ppc/ppc405_boards.c
>> +++ b/hw/ppc/ppc405_boards.c
>> @@ -401,7 +401,7 @@ struct Ref405epFpgaState {
>> static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned
>> size)
>> {
>> Ref405epFpgaState *fpga = opaque;
>> - uint32_t ret;
>> + uint32_t ret = 0;
>> switch (addr) {
>> case 0x0:
>> @@ -410,9 +410,6 @@ static uint64_t ref405ep_fpga_readb(void *opaque,
>> hwaddr addr, unsigned size)
>> case 0x1:
>> ret = fpga->reg1;
>> break;
>> - default:
>> - ret = 0;
>> - break;
>> }
>> return ret;
>> @@ -430,8 +427,6 @@ static void ref405ep_fpga_writeb(void *opaque, hwaddr
>> addr, uint64_t value,
>> case 0x1:
>> fpga->reg1 = value;
>> break;
>> - default:
>> - break;
>> }
>> }
>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
>> index b13026200f..6c84d87330 100644
>> --- a/hw/ppc/ppc405_uc.c
>> +++ b/hw/ppc/ppc405_uc.c
>> @@ -56,7 +56,7 @@ enum {
>> static uint32_t dcr_read_pob(void *opaque, int dcrn)
>> {
>> Ppc405PobState *pob = opaque;
>> - uint32_t ret;
>> + uint32_t ret = 0;
>> switch (dcrn) {
>> case POB0_BEAR:
>> @@ -68,10 +68,6 @@ static uint32_t dcr_read_pob(void *opaque, int dcrn)
>> case POB0_BESR1:
>> ret = pob->besr1;
>> break;
>> - default:
>> - /* Avoid gcc warning */
>> - ret = 0;
>> - break;
>> }
>> return ret;
>> @@ -131,7 +127,7 @@ static void ppc405_pob_class_init(ObjectClass *oc, void
>> *data)
>> static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
>> {
>> Ppc405OpbaState *opba = opaque;
>> - uint32_t ret;
>> + uint32_t ret = 0;
>> switch (addr) {
>> case 0x00:
>> @@ -140,9 +136,6 @@ static uint64_t opba_readb(void *opaque, hwaddr addr,
>> unsigned size)
>> case 0x01:
>> ret = opba->pr;
>> break;
>> - default:
>> - ret = 0x00;
>> - break;
>> }
>> trace_opba_readb(addr, ret);
>> @@ -163,8 +156,6 @@ static void opba_writeb(void *opaque, hwaddr addr,
>> uint64_t value,
>> case 0x01:
>> opba->pr = value & 0xFF;
>> break;
>> - default:
>> - break;
>> }
>> }
>> static const MemoryRegionOps opba_ops = {
>> @@ -403,7 +394,7 @@ static void ocm_update_mappings(Ppc405OcmState *ocm,
>> static uint32_t dcr_read_ocm(void *opaque, int dcrn)
>> {
>> Ppc405OcmState *ocm = opaque;
>> - uint32_t ret;
>> + uint32_t ret = 0;
>> switch (dcrn) {
>> case OCM0_ISARC:
>> @@ -418,9 +409,6 @@ static uint32_t dcr_read_ocm(void *opaque, int dcrn)
>> case OCM0_DSACNTL:
>> ret = ocm->dsacntl;
>> break;
>> - default:
>> - ret = 0;
>> - break;
>> }
>> return ret;
>> @@ -556,7 +544,7 @@ static void ppc4xx_gpt_compute_timer(Ppc405GptState
>> *gpt)
>> static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
>> {
>> Ppc405GptState *gpt = opaque;
>> - uint32_t ret;
>> + uint32_t ret = -1;
>> int idx;
>> trace_ppc4xx_gpt_read(addr, size);
>> @@ -598,9 +586,6 @@ static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr
>> addr, unsigned size)
>> idx = (addr - 0xC0) >> 2;
>> ret = gpt->mask[idx];
>> break;
>> - default:
>> - ret = -1;
>> - break;
>> }
>> return ret;
>> @@ -844,7 +829,7 @@ static void ppc405ep_compute_clocks(Ppc405CpcState
>> *cpc)
>> static uint32_t dcr_read_epcpc(void *opaque, int dcrn)
>> {
>> Ppc405CpcState *cpc = opaque;
>> - uint32_t ret;
>> + uint32_t ret = 0;
>> switch (dcrn) {
>> case PPC405EP_CPC0_BOOT:
>> @@ -871,10 +856,6 @@ static uint32_t dcr_read_epcpc(void *opaque, int dcrn)
>> case PPC405EP_CPC0_PCI:
>> ret = cpc->pci;
>> break;
>> - default:
>> - /* Avoid gcc warning */
>> - ret = 0;
>> - break;
>> }
>> return ret;
>> diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
>> index 11fdb88c22..b390672bce 100644
>> --- a/hw/ppc/ppc440_uc.c
>> +++ b/hw/ppc/ppc440_uc.c
>> @@ -147,9 +147,6 @@ static uint32_t dcr_read_l2sram(void *opaque, int dcrn)
>> case DCR_ISRAM0_DPC:
>> ret = l2sram->isram0[dcrn - DCR_ISRAM0_BASE];
>> break;
>> -
>> - default:
>> - break;
>> }
>> return ret;
>> @@ -304,12 +301,8 @@ static uint32_t dcr_read_cpr(void *opaque, int dcrn)
>> case CPR0_AHBD:
>> ret = (1 << 24);
>> break;
>> - default:
>> - break;
>> }
>> break;
>> - default:
>> - break;
>> }
>> return ret;
>> @@ -325,8 +318,6 @@ static void dcr_write_cpr(void *opaque, int dcrn,
>> uint32_t val)
>> break;
>> case CPR0_CFGDATA:
>> break;
>> - default:
>> - break;
>> }
>> }
>> @@ -421,12 +412,8 @@ static uint32_t dcr_read_sdr(void *opaque, int dcrn)
>> case PESDR1_LOOP:
>> ret = 1 << 12;
>> break;
>> - default:
>> - break;
>> }
>> break;
>> - default:
>> - break;
>> }
>> return ret;
>> @@ -444,12 +431,8 @@ static void dcr_write_sdr(void *opaque, int dcrn,
>> uint32_t val)
>> switch (sdr->addr) {
>> case 0x00: /* B0CR */
>> break;
>> - default:
>> - break;
>> }
>> break;
>> - default:
>> - break;
>> }
>> }
>> @@ -646,12 +629,8 @@ static uint32_t dcr_read_sdram(void *opaque, int
>> dcrn)
>> case 0xE1: /* SDR0_DDR0 */
>> ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1;
>> break;
>> - default:
>> - break;
>> }
>> break;
>> - default:
>> - break;
>> }
>> return ret;
>> @@ -679,12 +658,8 @@ static void dcr_write_sdram(void *opaque, int dcrn,
>> uint32_t val)
>> switch (sdram->addr) {
>> case 0x00: /* B0CR */
>> break;
>> - default:
>> - break;
>> }
>> break;
>> - default:
>> - break;
>> }
>> }
>> @@ -760,8 +735,6 @@ static uint32_t dcr_read_ahb(void *opaque, int dcrn)
>> case AHB_BOT:
>> ret = ahb->bot;
>> break;
>> - default:
>> - break;
>> }
>> return ret;
>> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
>> index 49793b56cd..f5806f06e7 100644
>> --- a/hw/ppc/ppc4xx_devs.c
>> +++ b/hw/ppc/ppc4xx_devs.c
>> @@ -182,7 +182,7 @@ static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
>> static uint32_t dcr_read_sdram (void *opaque, int dcrn)
>> {
>> ppc4xx_sdram_t *sdram;
>> - uint32_t ret;
>> + uint32_t ret = 0;
>> sdram = opaque;
>> switch (dcrn) {
>> @@ -238,10 +238,6 @@ static uint32_t dcr_read_sdram (void *opaque, int
>> dcrn)
>> break;
>> }
>> break;
>> - default:
>> - /* Avoid gcc warning */
>> - ret = 0x00000000;
>> - break;
>> }
>> return ret;
>> @@ -321,8 +317,6 @@ static void dcr_write_sdram (void *opaque, int dcrn,
>> uint32_t val)
>> qemu_irq_lower(sdram->irq);
>> sdram->eccesr = val;
>> break;
>> - default: /* Error */
>> - break;
>> }
>> break;
>> }
>> @@ -476,7 +470,7 @@ static void ppc4xx_mal_reset(DeviceState *dev)
>> static uint32_t dcr_read_mal(void *opaque, int dcrn)
>> {
>> Ppc4xxMalState *mal = opaque;
>> - uint32_t ret;
>> + uint32_t ret = 0;
>> switch (dcrn) {
>> case MAL0_CFG:
>> @@ -512,9 +506,6 @@ static uint32_t dcr_read_mal(void *opaque, int dcrn)
>> case MAL0_RXDEIR:
>> ret = mal->rxdeir;
>> break;
>> - default:
>> - ret = 0;
>> - break;
>> }
>> if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) {
>> ret = mal->txctpr[dcrn - MAL0_TXCTP0R];
>> @@ -671,7 +662,7 @@ enum {
>> static uint32_t dcr_read_plb(void *opaque, int dcrn)
>> {
>> Ppc405PlbState *plb = opaque;
>> - uint32_t ret;
>> + uint32_t ret = 0;
>> switch (dcrn) {
>> case PLB0_ACR:
>> @@ -683,10 +674,6 @@ static uint32_t dcr_read_plb(void *opaque, int dcrn)
>> case PLB0_BESR:
>> ret = plb->besr;
>> break;
>> - default:
>> - /* Avoid gcc warning */
>> - ret = 0;
>> - break;
>> }
>> return ret;
>> @@ -756,7 +743,7 @@ enum {
>> static uint32_t dcr_read_ebc(void *opaque, int dcrn)
>> {
>> Ppc405EbcState *ebc = opaque;
>> - uint32_t ret;
>> + uint32_t ret = 0;
>> switch (dcrn) {
>> case EBC0_CFGADDR:
>> @@ -824,14 +811,8 @@ static uint32_t dcr_read_ebc(void *opaque, int dcrn)
>> case 0x23: /* CFG */
>> ret = ebc->cfg;
>> break;
>> - default:
>> - ret = 0x00000000;
>> - break;
>> }
>> break;
>> - default:
>> - ret = 0x00000000;
>> - break;
>> }
>> return ret;
>> @@ -887,12 +868,8 @@ static void dcr_write_ebc(void *opaque, int dcrn,
>> uint32_t val)
>> break;
>> case 0x23: /* CFG */
>> break;
>> - default:
>> - break;
>> }
>> break;
>> - default:
>> - break;
>> }
>> }
>>
>
>
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 22/22] ppc/ppc4xx: Fix sdram trace events
2022-08-13 15:34 [PATCH 00/22] QOMify PPC4xx devices and minor clean ups BALATON Zoltan
` (20 preceding siblings ...)
2022-08-13 15:34 ` [PATCH 21/22] ppc4xx: Drop empty default cases BALATON Zoltan
@ 2022-08-13 15:34 ` BALATON Zoltan
2022-08-16 11:19 ` [PATCH 00/22] QOMify PPC4xx devices and minor clean ups Cédric Le Goater
22 siblings, 0 replies; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-13 15:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
From: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc4xx_devs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index f5806f06e7..3311b30a81 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -142,7 +142,7 @@ static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i,
}
sdram->bcr[i] = bcr & 0xFFDEE001;
if (enabled && (bcr & 0x00000001)) {
- trace_ppc4xx_sdram_unmap(sdram_base(bcr), sdram_size(bcr));
+ trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
memory_region_init(&sdram->containers[i], NULL, "sdram-containers",
sdram_size(bcr));
memory_region_add_subregion(&sdram->containers[i], 0,
--
2.30.4
^ permalink raw reply related [flat|nested] 37+ messages in thread* Re: [PATCH 00/22] QOMify PPC4xx devices and minor clean ups
2022-08-13 15:34 [PATCH 00/22] QOMify PPC4xx devices and minor clean ups BALATON Zoltan
` (21 preceding siblings ...)
2022-08-13 15:34 ` [PATCH 22/22] ppc/ppc4xx: Fix sdram trace events BALATON Zoltan
@ 2022-08-16 11:19 ` Cédric Le Goater
2022-08-17 15:13 ` BALATON Zoltan
22 siblings, 1 reply; 37+ messages in thread
From: Cédric Le Goater @ 2022-08-16 11:19 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc
Cc: Daniel Henrique Barboza, Peter Maydell
On 8/13/22 17:34, BALATON Zoltan wrote:
> Hello,
>
> This is mased on gitlab.com/danielhb/qemu/tree/ppc-7.2
>
> This series contains the rest of Cédric's patches modified according
> my review comments and some other small clean ups I've noticed along
> the way. I've kept the From line of Cédric for patches that were
> originally his even though they are modified a bit. Not sure what's
> the best way for this or what Cédric prefers.
>
> The last sdram changes are not yet here because I'm still looking at
> those and will come back to them but this series is ready to merge
> unless there are comments that need further changes. Please let me
> know what do you think.
LGTM. In case you resend, may be change the names of the models which
are now common to PPC4xx. That's minor really.
I would dig the default case labels a little more before removing
them.
Thanks,
C.
>
> Regards,
> BALATON Zoltan
>
> BALATON Zoltan (22):
> ppc/ppc4xx: Introduce a DCR device model
> ppc/ppc405: QOM'ify CPC
> ppc/ppc405: QOM'ify GPT
> ppc/ppc405: QOM'ify OCM
> ppc/ppc405: QOM'ify GPIO
> ppc/ppc405: QOM'ify DMA
> ppc/ppc405: QOM'ify EBC
> ppc/ppc405: QOM'ify OPBA
> ppc/ppc405: QOM'ify POB
> ppc/ppc405: QOM'ify PLB
> ppc/ppc405: QOM'ify MAL
> ppc4xx: Move PLB model to ppc4xx_devs.c
> ppc4xx: Move EBC model to ppc4xx_devs.c
> ppc/ppc405: Use an embedded PPCUIC model in SoC state
> hw/intc/ppc-uic: Convert ppc-uic to a PPC4xx DCR device
> ppc/ppc405: Use an explicit I2C object
> ppc/ppc405: QOM'ify FPGA
> ppc405: Move machine specific code to ppc405_boards.c
> hw/ppc/Kconfig: Remove PPC405 dependency from sam460ex
> hw/ppc/Kconfig: Move imply before select
> ppc4xx: Drop empty default cases
> ppc/ppc4xx: Fix sdram trace events
>
> hw/intc/ppc-uic.c | 26 +-
> hw/ppc/Kconfig | 3 +-
> hw/ppc/ppc405.h | 182 +++++--
> hw/ppc/ppc405_boards.c | 360 +++++++++----
> hw/ppc/ppc405_uc.c | 1071 ++++++++++++-------------------------
> hw/ppc/ppc440_bamboo.c | 7 +-
> hw/ppc/ppc440_uc.c | 27 -
> hw/ppc/ppc4xx_devs.c | 473 +++++++++++++---
> hw/ppc/sam460ex.c | 37 +-
> hw/ppc/trace-events | 3 -
> hw/ppc/virtex_ml507.c | 7 +-
> include/hw/intc/ppc-uic.h | 6 +-
> include/hw/ppc/ppc4xx.h | 71 ++-
> 13 files changed, 1223 insertions(+), 1050 deletions(-)
>
^ permalink raw reply [flat|nested] 37+ messages in thread* Re: [PATCH 00/22] QOMify PPC4xx devices and minor clean ups
2022-08-16 11:19 ` [PATCH 00/22] QOMify PPC4xx devices and minor clean ups Cédric Le Goater
@ 2022-08-17 15:13 ` BALATON Zoltan
0 siblings, 0 replies; 37+ messages in thread
From: BALATON Zoltan @ 2022-08-17 15:13 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, Peter Maydell
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On Tue, 16 Aug 2022, Cédric Le Goater wrote:
> On 8/13/22 17:34, BALATON Zoltan wrote:
>> Hello,
>>
>> This is mased on gitlab.com/danielhb/qemu/tree/ppc-7.2
>>
>> This series contains the rest of Cédric's patches modified according
>> my review comments and some other small clean ups I've noticed along
>> the way. I've kept the From line of Cédric for patches that were
>> originally his even though they are modified a bit. Not sure what's
>> the best way for this or what Cédric prefers.
>>
>> The last sdram changes are not yet here because I'm still looking at
>> those and will come back to them but this series is ready to merge
>> unless there are comments that need further changes. Please let me
>> know what do you think.
>
> LGTM. In case you resend, may be change the names of the models which
> are now common to PPC4xx. That's minor really.
>
> I would dig the default case labels a little more before removing
> them.
I've sent a v2 that includes the proposed name changes and dropped the
patch removing empty default cases for now. This v2 now also includes my
version of the sdram changes so that's all from me for now.
Regards,
BALATON Zoltan
> Thanks,
>
> C.
>
>
>>
>> Regards,
>> BALATON Zoltan
>>
>> BALATON Zoltan (22):
>> ppc/ppc4xx: Introduce a DCR device model
>> ppc/ppc405: QOM'ify CPC
>> ppc/ppc405: QOM'ify GPT
>> ppc/ppc405: QOM'ify OCM
>> ppc/ppc405: QOM'ify GPIO
>> ppc/ppc405: QOM'ify DMA
>> ppc/ppc405: QOM'ify EBC
>> ppc/ppc405: QOM'ify OPBA
>> ppc/ppc405: QOM'ify POB
>> ppc/ppc405: QOM'ify PLB
>> ppc/ppc405: QOM'ify MAL
>> ppc4xx: Move PLB model to ppc4xx_devs.c
>> ppc4xx: Move EBC model to ppc4xx_devs.c
>> ppc/ppc405: Use an embedded PPCUIC model in SoC state
>> hw/intc/ppc-uic: Convert ppc-uic to a PPC4xx DCR device
>> ppc/ppc405: Use an explicit I2C object
>> ppc/ppc405: QOM'ify FPGA
>> ppc405: Move machine specific code to ppc405_boards.c
>> hw/ppc/Kconfig: Remove PPC405 dependency from sam460ex
>> hw/ppc/Kconfig: Move imply before select
>> ppc4xx: Drop empty default cases
>> ppc/ppc4xx: Fix sdram trace events
>>
>> hw/intc/ppc-uic.c | 26 +-
>> hw/ppc/Kconfig | 3 +-
>> hw/ppc/ppc405.h | 182 +++++--
>> hw/ppc/ppc405_boards.c | 360 +++++++++----
>> hw/ppc/ppc405_uc.c | 1071 ++++++++++++-------------------------
>> hw/ppc/ppc440_bamboo.c | 7 +-
>> hw/ppc/ppc440_uc.c | 27 -
>> hw/ppc/ppc4xx_devs.c | 473 +++++++++++++---
>> hw/ppc/sam460ex.c | 37 +-
>> hw/ppc/trace-events | 3 -
>> hw/ppc/virtex_ml507.c | 7 +-
>> include/hw/intc/ppc-uic.h | 6 +-
>> include/hw/ppc/ppc4xx.h | 71 ++-
>> 13 files changed, 1223 insertions(+), 1050 deletions(-)
>>
>
>
>
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