* [U-Boot] [GIT PULL] Xilinx changes for v2018.11-rc2
@ 2018-10-15 14:25 Michal Simek
2018-10-16 0:32 ` Tom Rini
0 siblings, 1 reply; 6+ messages in thread
From: Michal Simek @ 2018-10-15 14:25 UTC (permalink / raw)
To: u-boot
Hi Tom,
please consider to pull these patches to your tree.
Buildmain for xilinx boards looks good and travis is not done yet but
link is here (I have seen several timeouts recently but it was there
even on clear mainline).
https://travis-ci.org/michalsimek/u-boot/builds/441591781
If you don't like this please at least cherry-pick this one
Revert "fdt: fdtdec_setup_memory_banksize() use livetree"
(sha1: 01ac0843aeedc3c95fe68e7ce6a8f35bf1a04b23)
which I need for getting SPL up and running again on zynq/zynqmp boards.
Thanks,
Michal
The following changes since commit 15f22ac2eea5ee9f17b14a143c94e7480bbafbff:
ldpaa_eth.c: Fix warning when PHYLIB is not enabled (2018-10-12
07:41:24 -0400)
are available in the git repository at:
git://www.denx.de/git/u-boot-microblaze.git tags/xilinx-for-v2018.11-rc2
for you to fetch changes up to 045c62be10d64a558f56febcaa2d01b1abbcfa00:
cmd: kgdb: Enable kgdb only for PPC (2018-10-15 12:36:37 +0200)
----------------------------------------------------------------
Xilinx changes for v2018.11-rc2
FPGA:
- Fix SPL fpga loading from FIT
ARM64:
- Fix gic accesses in EL2/EL1
Xilinx:
- Add dlc20 board support
- Add Versal board support
- Sync defconfigs
- Enable MP via Kconfig
- Add missing efuse node
- Enable CDC for zcu100
cmd:
- Fix kgdb Kconfig dependency
serial-pl01x:
- Add support for handling clk from DT
----------------------------------------------------------------
Michal Simek (13):
spl: fpga: Implement fpga bistream loading with fpga_load
arm: zynq: Enable FIT fpga loading in SPL for zc706
arm: zynq: Add support for DLC20 board
Revert "fdt: fdtdec_setup_memory_banksize() use livetree"
arm: zynq: Add efuse node for Zynq-7000S devices
xilinx: Sync defconfigs with current Kconfig
arm64: zynqmp: Enable CDC ethernet gadget for zcu100/Ultra96
arm64: gic: Do gicv3 secure initialization based on EL level
arm64: versal: Add support for new Xilinx Versal ACAPs
net: gem: Do not setup any clock for Xilinx SoC Versal
arm64: versal: Add Xilinx Versal Virtual QEMU board
arm64: zynqmp: Enable MP by default via Kconfig
cmd: kgdb: Enable kgdb only for PPC
Siva Durga Prasad Paladugu (3):
serial: pl01x: Get clock from clock node if no clock property found
arm64: zynqmp: Move TCM initialization to a separate routine
arm64: zynqmp: Add new command for TCM initialization
Kconfig | 2 +-
MAINTAINERS | 6 ++++
arch/arm/Kconfig | 11 +++++++
arch/arm/Makefile | 1 +
arch/arm/cpu/armv8/zynqmp/cpu.c | 12 +++++--
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynq-7000.dtsi | 5 +++
arch/arm/dts/zynq-dlc20-rev1.0.dts | 103
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++
arch/arm/include/asm/arch-zynqmp/sys_proto.h | 3 ++
arch/arm/lib/gic_64.S | 16 +++++----
arch/arm/mach-versal/Kconfig | 44
+++++++++++++++++++++++++
arch/arm/mach-versal/Makefile | 8 +++++
arch/arm/mach-versal/clk.c | 30 +++++++++++++++++
arch/arm/mach-versal/cpu.c | 83
++++++++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-versal/include/mach/gpio.h | 6 ++++
arch/arm/mach-versal/include/mach/hardware.h | 34
+++++++++++++++++++
arch/arm/mach-versal/include/mach/sys_proto.h | 6 ++++
board/xilinx/versal/MAINTAINERS | 7 ++++
board/xilinx/versal/Makefile | 7 ++++
board/xilinx/versal/board.c | 81
+++++++++++++++++++++++++++++++++++++++++++++
board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c | 280
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
board/xilinx/zynqmp/cmds.c | 37
++++++++++++++++++++-
cmd/Kconfig | 1 +
common/spl/spl_fit.c | 34
+++++++++----------
configs/avnet_ultra96_rev1_defconfig | 8 +++--
configs/microblaze-generic_defconfig | 2 +-
configs/xilinx_versal_virt_defconfig | 68
++++++++++++++++++++++++++++++++++++++
configs/xilinx_zynqmp_mini_emmc0_defconfig | 1 +
configs/xilinx_zynqmp_mini_emmc1_defconfig | 1 +
configs/xilinx_zynqmp_mini_nand_defconfig | 1 +
configs/xilinx_zynqmp_mini_qspi_defconfig | 1 -
configs/xilinx_zynqmp_zc1232_revA_defconfig | 1 -
configs/xilinx_zynqmp_zc1254_revA_defconfig | 1 -
configs/xilinx_zynqmp_zc1275_revA_defconfig | 1 -
configs/xilinx_zynqmp_zc1275_revB_defconfig | 1 -
configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 -
configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 -
configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig | 1 -
configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 -
configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 1 -
configs/xilinx_zynqmp_zcu100_revC_defconfig | 8 +++--
configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 -
configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 -
configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 -
configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 -
configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 -
configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 -
configs/xilinx_zynqmp_zcu111_revA_defconfig | 1 -
configs/zynq_dlc20_rev1_0_defconfig | 74
+++++++++++++++++++++++++++++++++++++++++
configs/zynq_zc706_defconfig | 4 +++
drivers/mmc/Kconfig | 2 +-
drivers/net/Kconfig | 2 +-
drivers/net/zynq_gem.c | 4 +++
drivers/serial/serial_pl01x.c | 26 +++++++++++++++
drivers/spi/Kconfig | 4 +--
env/Kconfig | 4 +--
include/configs/xilinx_versal.h | 91
++++++++++++++++++++++++++++++++++++++++++++++++++
lib/fdtdec.c | 44
+++++++++++++------------
58 files changed, 1101 insertions(+), 78 deletions(-)
create mode 100644 arch/arm/dts/zynq-dlc20-rev1.0.dts
create mode 100644 arch/arm/mach-versal/Kconfig
create mode 100644 arch/arm/mach-versal/Makefile
create mode 100644 arch/arm/mach-versal/clk.c
create mode 100644 arch/arm/mach-versal/cpu.c
create mode 100644 arch/arm/mach-versal/include/mach/gpio.h
create mode 100644 arch/arm/mach-versal/include/mach/hardware.h
create mode 100644 arch/arm/mach-versal/include/mach/sys_proto.h
create mode 100644 board/xilinx/versal/MAINTAINERS
create mode 100644 board/xilinx/versal/Makefile
create mode 100644 board/xilinx/versal/board.c
create mode 100644 board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c
create mode 100644 configs/xilinx_versal_virt_defconfig
create mode 100644 configs/zynq_dlc20_rev1_0_defconfig
create mode 100644 include/configs/xilinx_versal.h
^ permalink raw reply [flat|nested] 6+ messages in thread* [U-Boot] [GIT PULL] Xilinx changes for v2018.11-rc2 2018-10-15 14:25 [U-Boot] [GIT PULL] Xilinx changes for v2018.11-rc2 Michal Simek @ 2018-10-16 0:32 ` Tom Rini 2018-10-16 8:32 ` Michal Simek 0 siblings, 1 reply; 6+ messages in thread From: Tom Rini @ 2018-10-16 0:32 UTC (permalink / raw) To: u-boot On Mon, Oct 15, 2018 at 04:25:01PM +0200, Michal Simek wrote: > Hi Tom, > > please consider to pull these patches to your tree. > Buildmain for xilinx boards looks good and travis is not done yet but > link is here (I have seen several timeouts recently but it was there > even on clear mainline). > https://travis-ci.org/michalsimek/u-boot/builds/441591781 > > If you don't like this please at least cherry-pick this one > Revert "fdt: fdtdec_setup_memory_banksize() use livetree" > (sha1: 01ac0843aeedc3c95fe68e7ce6a8f35bf1a04b23) > which I need for getting SPL up and running again on zynq/zynqmp boards. > > Thanks, > Michal > > The following changes since commit 15f22ac2eea5ee9f17b14a143c94e7480bbafbff: > > ldpaa_eth.c: Fix warning when PHYLIB is not enabled (2018-10-12 > 07:41:24 -0400) > > are available in the git repository at: > > git://www.denx.de/git/u-boot-microblaze.git tags/xilinx-for-v2018.11-rc2 > > for you to fetch changes up to 045c62be10d64a558f56febcaa2d01b1abbcfa00: > > cmd: kgdb: Enable kgdb only for PPC (2018-10-15 12:36:37 +0200) > NAK. As this stands it breaks qemu_arm running the test.py code due to: commit 6d213c125c45db9c9d4dde5348d6e002c9f58909 Author: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Date: Mon Jan 22 17:49:37 2018 +0530 serial: pl01x: Get clock from clock node if no clock property found This patch gets clock from clock nodes if no clock property found in serial node. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Now that said, I have cherry-picked out: Author: Michal Simek <michal.simek@xilinx.com> Date: Wed Oct 3 15:53:52 2018 +0200 Revert "fdt: fdtdec_setup_memory_banksize() use livetree" This reverts commit c35a7d375ec8f0a8ee343ae4868be3242172632e. This commit is breaking SPL on zc706. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrice Chotard <patrice.chotard@st.com> [on STM32F746-disco] out of the PR as I had intended to bring that in myself but missed when Simon RB'd it. -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: <http://lists.denx.de/pipermail/u-boot/attachments/20181015/c695251b/attachment.sig> ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [GIT PULL] Xilinx changes for v2018.11-rc2 2018-10-16 0:32 ` Tom Rini @ 2018-10-16 8:32 ` Michal Simek 2018-10-16 13:38 ` Tom Rini 0 siblings, 1 reply; 6+ messages in thread From: Michal Simek @ 2018-10-16 8:32 UTC (permalink / raw) To: u-boot On 16.10.2018 02:32, Tom Rini wrote: > On Mon, Oct 15, 2018 at 04:25:01PM +0200, Michal Simek wrote: > >> Hi Tom, >> >> please consider to pull these patches to your tree. >> Buildmain for xilinx boards looks good and travis is not done yet but >> link is here (I have seen several timeouts recently but it was there >> even on clear mainline). >> https://travis-ci.org/michalsimek/u-boot/builds/441591781 >> >> If you don't like this please at least cherry-pick this one >> Revert "fdt: fdtdec_setup_memory_banksize() use livetree" >> (sha1: 01ac0843aeedc3c95fe68e7ce6a8f35bf1a04b23) >> which I need for getting SPL up and running again on zynq/zynqmp boards. >> >> Thanks, >> Michal >> >> The following changes since commit 15f22ac2eea5ee9f17b14a143c94e7480bbafbff: >> >> ldpaa_eth.c: Fix warning when PHYLIB is not enabled (2018-10-12 >> 07:41:24 -0400) >> >> are available in the git repository at: >> >> git://www.denx.de/git/u-boot-microblaze.git tags/xilinx-for-v2018.11-rc2 >> >> for you to fetch changes up to 045c62be10d64a558f56febcaa2d01b1abbcfa00: >> >> cmd: kgdb: Enable kgdb only for PPC (2018-10-15 12:36:37 +0200) >> > > NAK. As this stands it breaks qemu_arm running the test.py code due to: > commit 6d213c125c45db9c9d4dde5348d6e002c9f58909 > Author: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> > Date: Mon Jan 22 17:49:37 2018 +0530 > > serial: pl01x: Get clock from clock node if no clock property found > > This patch gets clock from clock nodes if no clock property found > in serial node. > > Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> > Signed-off-by: Michal Simek <michal.simek@xilinx.com> I have debugged it more and the patch is good but information coming from qemu are not correct for u-boot. What it is happening for arm case is that qemu passing DT which contains these 2 fragments: pl011 at 9000000 { clock-names = "uartclk", "apb_pclk"; clocks = <0x00008000 0x00008000>; interrupts = <0x00000000 0x00000001 0x00000004>; reg = <0x00000000 0x09000000 0x00000000 0x00001000>; compatible = "arm,pl011", "arm,primecell"; }; apb-pclk { phandle = <0x00008000>; clock-output-names = "clk24mhz"; clock-frequency = <0x016e3600>; #clock-cells = <0x00000000>; compatible = "fixed-clock"; }; That means that when this patch is applied new code is taken because plat->clock = dev_read_u32_default(dev, "clock", 1); is returning default value 1. (I see clock property used by hi6220 which should be out of DT binding) Then clocks are taken and we get to apb-pclk which is fixed clock but it is missing "u-boot,dm-pre-reloc" property to get it work. (In connection to that CONFIG_CLK should be enabled for qemu_arm_defconfig). Just a summary of this is that it requires updating qemu by 1. adding non standard "clock" property to qemu hw/arm/virt.c or 2. by enabling CONFIG_CLK(easy) and again adding "u-boot,dm-pre-reloc" to qemu hw/arm/virt.c As is visible this requires qemu updates to get this work. Can you please tell me which way you want to go? It should be fine to merge my queue without this patch because qemu is ignoring this clock setup anyway. Thanks, Michal ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [GIT PULL] Xilinx changes for v2018.11-rc2 2018-10-16 8:32 ` Michal Simek @ 2018-10-16 13:38 ` Tom Rini 2018-10-16 15:04 ` Michal Simek 0 siblings, 1 reply; 6+ messages in thread From: Tom Rini @ 2018-10-16 13:38 UTC (permalink / raw) To: u-boot On Tue, Oct 16, 2018 at 10:32:14AM +0200, Michal Simek wrote: > On 16.10.2018 02:32, Tom Rini wrote: > > On Mon, Oct 15, 2018 at 04:25:01PM +0200, Michal Simek wrote: > > > >> Hi Tom, > >> > >> please consider to pull these patches to your tree. > >> Buildmain for xilinx boards looks good and travis is not done yet but > >> link is here (I have seen several timeouts recently but it was there > >> even on clear mainline). > >> https://travis-ci.org/michalsimek/u-boot/builds/441591781 > >> > >> If you don't like this please at least cherry-pick this one > >> Revert "fdt: fdtdec_setup_memory_banksize() use livetree" > >> (sha1: 01ac0843aeedc3c95fe68e7ce6a8f35bf1a04b23) > >> which I need for getting SPL up and running again on zynq/zynqmp boards. > >> > >> Thanks, > >> Michal > >> > >> The following changes since commit 15f22ac2eea5ee9f17b14a143c94e7480bbafbff: > >> > >> ldpaa_eth.c: Fix warning when PHYLIB is not enabled (2018-10-12 > >> 07:41:24 -0400) > >> > >> are available in the git repository at: > >> > >> git://www.denx.de/git/u-boot-microblaze.git tags/xilinx-for-v2018.11-rc2 > >> > >> for you to fetch changes up to 045c62be10d64a558f56febcaa2d01b1abbcfa00: > >> > >> cmd: kgdb: Enable kgdb only for PPC (2018-10-15 12:36:37 +0200) > >> > > > > NAK. As this stands it breaks qemu_arm running the test.py code due to: > > commit 6d213c125c45db9c9d4dde5348d6e002c9f58909 > > Author: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> > > Date: Mon Jan 22 17:49:37 2018 +0530 > > > > serial: pl01x: Get clock from clock node if no clock property found > > > > This patch gets clock from clock nodes if no clock property found > > in serial node. > > > > Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> > > Signed-off-by: Michal Simek <michal.simek@xilinx.com> > > I have debugged it more and the patch is good but information coming > from qemu are not correct for u-boot. > > What it is happening for arm case is that qemu passing DT which contains > these 2 fragments: > > pl011 at 9000000 { > clock-names = "uartclk", "apb_pclk"; > clocks = <0x00008000 0x00008000>; > interrupts = <0x00000000 0x00000001 0x00000004>; > reg = <0x00000000 0x09000000 0x00000000 0x00001000>; > compatible = "arm,pl011", "arm,primecell"; > }; > > apb-pclk { > phandle = <0x00008000>; > clock-output-names = "clk24mhz"; > clock-frequency = <0x016e3600>; > #clock-cells = <0x00000000>; > compatible = "fixed-clock"; > }; > > That means that when this patch is applied new code is taken because > plat->clock = dev_read_u32_default(dev, "clock", 1); > is returning default value 1. > (I see clock property used by hi6220 which should be out of DT binding) > > Then clocks are taken and we get to apb-pclk which is fixed clock but it > is missing "u-boot,dm-pre-reloc" property to get it work. (In connection > to that CONFIG_CLK should be enabled for qemu_arm_defconfig). > > Just a summary of this is that it requires updating qemu by > 1. adding non standard "clock" property to qemu hw/arm/virt.c > or > 2. by enabling CONFIG_CLK(easy) and again adding "u-boot,dm-pre-reloc" > to qemu hw/arm/virt.c > > As is visible this requires qemu updates to get this work. > > Can you please tell me which way you want to go? I think we need a 3rd option as I can't see upstream qemu accepting a U-Boot specific U-Boot property, and it'll create a bit of a support nightmare too. > It should be fine to merge my queue without this patch because qemu is > ignoring this clock setup anyway. OK, I'll test out an updated PR of yours once you send it, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: <http://lists.denx.de/pipermail/u-boot/attachments/20181016/61758466/attachment.sig> ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [GIT PULL] Xilinx changes for v2018.11-rc2 2018-10-16 13:38 ` Tom Rini @ 2018-10-16 15:04 ` Michal Simek 2018-11-06 11:16 ` Michal Simek 0 siblings, 1 reply; 6+ messages in thread From: Michal Simek @ 2018-10-16 15:04 UTC (permalink / raw) To: u-boot On 16.10.2018 15:38, Tom Rini wrote: > On Tue, Oct 16, 2018 at 10:32:14AM +0200, Michal Simek wrote: >> On 16.10.2018 02:32, Tom Rini wrote: >>> On Mon, Oct 15, 2018 at 04:25:01PM +0200, Michal Simek wrote: >>> >>>> Hi Tom, >>>> >>>> please consider to pull these patches to your tree. >>>> Buildmain for xilinx boards looks good and travis is not done yet but >>>> link is here (I have seen several timeouts recently but it was there >>>> even on clear mainline). >>>> https://travis-ci.org/michalsimek/u-boot/builds/441591781 >>>> >>>> If you don't like this please at least cherry-pick this one >>>> Revert "fdt: fdtdec_setup_memory_banksize() use livetree" >>>> (sha1: 01ac0843aeedc3c95fe68e7ce6a8f35bf1a04b23) >>>> which I need for getting SPL up and running again on zynq/zynqmp boards. >>>> >>>> Thanks, >>>> Michal >>>> >>>> The following changes since commit 15f22ac2eea5ee9f17b14a143c94e7480bbafbff: >>>> >>>> ldpaa_eth.c: Fix warning when PHYLIB is not enabled (2018-10-12 >>>> 07:41:24 -0400) >>>> >>>> are available in the git repository at: >>>> >>>> git://www.denx.de/git/u-boot-microblaze.git tags/xilinx-for-v2018.11-rc2 >>>> >>>> for you to fetch changes up to 045c62be10d64a558f56febcaa2d01b1abbcfa00: >>>> >>>> cmd: kgdb: Enable kgdb only for PPC (2018-10-15 12:36:37 +0200) >>>> >>> >>> NAK. As this stands it breaks qemu_arm running the test.py code due to: >>> commit 6d213c125c45db9c9d4dde5348d6e002c9f58909 >>> Author: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> >>> Date: Mon Jan 22 17:49:37 2018 +0530 >>> >>> serial: pl01x: Get clock from clock node if no clock property found >>> >>> This patch gets clock from clock nodes if no clock property found >>> in serial node. >>> >>> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> >>> Signed-off-by: Michal Simek <michal.simek@xilinx.com> >> >> I have debugged it more and the patch is good but information coming >> from qemu are not correct for u-boot. >> >> What it is happening for arm case is that qemu passing DT which contains >> these 2 fragments: >> >> pl011 at 9000000 { >> clock-names = "uartclk", "apb_pclk"; >> clocks = <0x00008000 0x00008000>; >> interrupts = <0x00000000 0x00000001 0x00000004>; >> reg = <0x00000000 0x09000000 0x00000000 0x00001000>; >> compatible = "arm,pl011", "arm,primecell"; >> }; >> >> apb-pclk { >> phandle = <0x00008000>; >> clock-output-names = "clk24mhz"; >> clock-frequency = <0x016e3600>; >> #clock-cells = <0x00000000>; >> compatible = "fixed-clock"; >> }; >> >> That means that when this patch is applied new code is taken because >> plat->clock = dev_read_u32_default(dev, "clock", 1); >> is returning default value 1. >> (I see clock property used by hi6220 which should be out of DT binding) >> >> Then clocks are taken and we get to apb-pclk which is fixed clock but it >> is missing "u-boot,dm-pre-reloc" property to get it work. (In connection >> to that CONFIG_CLK should be enabled for qemu_arm_defconfig). >> >> Just a summary of this is that it requires updating qemu by >> 1. adding non standard "clock" property to qemu hw/arm/virt.c >> or >> 2. by enabling CONFIG_CLK(easy) and again adding "u-boot,dm-pre-reloc" >> to qemu hw/arm/virt.c >> >> As is visible this requires qemu updates to get this work. >> >> Can you please tell me which way you want to go? > > I think we need a 3rd option as I can't see upstream qemu accepting a > U-Boot specific U-Boot property, and it'll create a bit of a support > nightmare too. Good. I want to also wired Versal ASAP when qemu patches reach mainline to make sure that we have good coverage from the beginning that's why having 3rd option with different qemu HEAD would be good. And as the part of Versal qemu upstreaming we have added u-boot property and will see how it goes. >> It should be fine to merge my queue without this patch because qemu is >> ignoring this clock setup anyway. > > OK, I'll test out an updated PR of yours once you send it, thanks! ok. Thanks, Michal ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [GIT PULL] Xilinx changes for v2018.11-rc2 2018-10-16 15:04 ` Michal Simek @ 2018-11-06 11:16 ` Michal Simek 0 siblings, 0 replies; 6+ messages in thread From: Michal Simek @ 2018-11-06 11:16 UTC (permalink / raw) To: u-boot Hi Tom, On 16. 10. 18 17:04, Michal Simek wrote: > On 16.10.2018 15:38, Tom Rini wrote: >> On Tue, Oct 16, 2018 at 10:32:14AM +0200, Michal Simek wrote: >>> On 16.10.2018 02:32, Tom Rini wrote: >>>> On Mon, Oct 15, 2018 at 04:25:01PM +0200, Michal Simek wrote: >>>> >>>>> Hi Tom, >>>>> >>>>> please consider to pull these patches to your tree. >>>>> Buildmain for xilinx boards looks good and travis is not done yet but >>>>> link is here (I have seen several timeouts recently but it was there >>>>> even on clear mainline). >>>>> https://travis-ci.org/michalsimek/u-boot/builds/441591781 >>>>> >>>>> If you don't like this please at least cherry-pick this one >>>>> Revert "fdt: fdtdec_setup_memory_banksize() use livetree" >>>>> (sha1: 01ac0843aeedc3c95fe68e7ce6a8f35bf1a04b23) >>>>> which I need for getting SPL up and running again on zynq/zynqmp boards. >>>>> >>>>> Thanks, >>>>> Michal >>>>> >>>>> The following changes since commit 15f22ac2eea5ee9f17b14a143c94e7480bbafbff: >>>>> >>>>> ldpaa_eth.c: Fix warning when PHYLIB is not enabled (2018-10-12 >>>>> 07:41:24 -0400) >>>>> >>>>> are available in the git repository at: >>>>> >>>>> git://www.denx.de/git/u-boot-microblaze.git tags/xilinx-for-v2018.11-rc2 >>>>> >>>>> for you to fetch changes up to 045c62be10d64a558f56febcaa2d01b1abbcfa00: >>>>> >>>>> cmd: kgdb: Enable kgdb only for PPC (2018-10-15 12:36:37 +0200) >>>>> >>>> >>>> NAK. As this stands it breaks qemu_arm running the test.py code due to: >>>> commit 6d213c125c45db9c9d4dde5348d6e002c9f58909 >>>> Author: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> >>>> Date: Mon Jan 22 17:49:37 2018 +0530 >>>> >>>> serial: pl01x: Get clock from clock node if no clock property found >>>> >>>> This patch gets clock from clock nodes if no clock property found >>>> in serial node. >>>> >>>> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> >>>> Signed-off-by: Michal Simek <michal.simek@xilinx.com> >>> >>> I have debugged it more and the patch is good but information coming >>> from qemu are not correct for u-boot. >>> >>> What it is happening for arm case is that qemu passing DT which contains >>> these 2 fragments: >>> >>> pl011 at 9000000 { >>> clock-names = "uartclk", "apb_pclk"; >>> clocks = <0x00008000 0x00008000>; >>> interrupts = <0x00000000 0x00000001 0x00000004>; >>> reg = <0x00000000 0x09000000 0x00000000 0x00001000>; >>> compatible = "arm,pl011", "arm,primecell"; >>> }; >>> >>> apb-pclk { >>> phandle = <0x00008000>; >>> clock-output-names = "clk24mhz"; >>> clock-frequency = <0x016e3600>; >>> #clock-cells = <0x00000000>; >>> compatible = "fixed-clock"; >>> }; >>> >>> That means that when this patch is applied new code is taken because >>> plat->clock = dev_read_u32_default(dev, "clock", 1); >>> is returning default value 1. >>> (I see clock property used by hi6220 which should be out of DT binding) >>> >>> Then clocks are taken and we get to apb-pclk which is fixed clock but it >>> is missing "u-boot,dm-pre-reloc" property to get it work. (In connection >>> to that CONFIG_CLK should be enabled for qemu_arm_defconfig). >>> >>> Just a summary of this is that it requires updating qemu by >>> 1. adding non standard "clock" property to qemu hw/arm/virt.c >>> or >>> 2. by enabling CONFIG_CLK(easy) and again adding "u-boot,dm-pre-reloc" >>> to qemu hw/arm/virt.c >>> >>> As is visible this requires qemu updates to get this work. >>> >>> Can you please tell me which way you want to go? >> >> I think we need a 3rd option as I can't see upstream qemu accepting a >> U-Boot specific U-Boot property, and it'll create a bit of a support >> nightmare too. > > Good. I want to also wired Versal ASAP when qemu patches reach mainline > to make sure that we have good coverage from the beginning that's why > having 3rd option with different qemu HEAD would be good. > > And as the part of Versal qemu upstreaming we have added u-boot property > and will see how it goes. I have an updated on this thread. Xilinx Versal was merged to mainline qemu and even with u-boot,dm-pre-reloc property. https://github.com/qemu/qemu/blob/master/hw/arm/xlnx-versal-virt.c#L88 It means there shouldn't be a problem to add the same property to hw/arm/virt.c. Thanks, Michal ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-11-06 11:16 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-10-15 14:25 [U-Boot] [GIT PULL] Xilinx changes for v2018.11-rc2 Michal Simek 2018-10-16 0:32 ` Tom Rini 2018-10-16 8:32 ` Michal Simek 2018-10-16 13:38 ` Tom Rini 2018-10-16 15:04 ` Michal Simek 2018-11-06 11:16 ` Michal Simek
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