* [PATCH 2/7] drm/amd/pm: record the RPM and PWM based fan speed settings
2021-07-07 1:56 [PATCH 1/7] drm/amd/pm: correct the fan speed RPM setting Evan Quan
@ 2021-07-07 1:56 ` Evan Quan
2021-07-07 4:53 ` Chen, Guchun
2021-07-07 8:53 ` Lazar, Lijo
2021-07-07 1:56 ` [PATCH 3/7] drm/amd/pm: correct the fan speed PWM retrieving Evan Quan
` (6 subsequent siblings)
7 siblings, 2 replies; 20+ messages in thread
From: Evan Quan @ 2021-07-07 1:56 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Evan Quan
As the relationship "PWM = RPM / smu->fan_max_rpm" between fan speed
PWM and RPM is not true for SMU11 ASICs. So, both the RPM and PWM
settings need to be saved.
Change-Id: I318c134d442273d518b805339cdf383e151b935d
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 8 ++++++++
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 20 +++++++++++++++-----
2 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 6301e4cb3c2a..fa585f0be530 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -226,10 +226,18 @@ enum smu_memory_pool_size
SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000,
};
+enum custom_fan_speed_mode
+{
+ SMU_CUSTOM_FAN_SPEED_RPM = 1 << 0,
+ SMU_CUSTOM_FAN_SPEED_PWM = 1 << 1,
+};
+
struct smu_user_dpm_profile {
uint32_t fan_mode;
uint32_t power_limit;
+ uint32_t custom_fan_speed;
uint32_t fan_speed_percent;
+ uint32_t fan_speed_rpm;
uint32_t flags;
/* user clock state information */
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 576e9ea68fd1..9a25443988e3 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -414,6 +414,12 @@ static void smu_restore_dpm_user_profile(struct smu_context *smu)
if (ret)
dev_err(smu->adev->dev, "Failed to set manual fan speed\n");
}
+
+ if (!ret && smu->user_dpm_profile.fan_speed_rpm) {
+ ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm);
+ if (ret)
+ dev_err(smu->adev->dev, "Failed to set manual fan speed\n");
+ }
}
/* Disable restore flag */
@@ -2166,7 +2172,6 @@ static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
{
struct smu_context *smu = handle;
- u32 percent;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
@@ -2177,8 +2182,8 @@ static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
if (smu->ppt_funcs->set_fan_speed_rpm) {
ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
if (!ret && smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE) {
- percent = speed * 100 / smu->fan_max_rpm;
- smu->user_dpm_profile.fan_speed_percent = percent;
+ smu->user_dpm_profile.custom_fan_speed |= SMU_CUSTOM_FAN_SPEED_RPM;
+ smu->user_dpm_profile.fan_speed_rpm = speed;
}
}
@@ -2539,8 +2544,11 @@ static int smu_set_fan_control_mode(struct smu_context *smu, int value)
/* reset user dpm fan speed */
if (!ret && value != AMD_FAN_CTRL_MANUAL &&
- !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
+ !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
smu->user_dpm_profile.fan_speed_percent = 0;
+ smu->user_dpm_profile.fan_speed_rpm = 0;
+ smu->user_dpm_profile.custom_fan_speed = 0;
+ }
return ret;
}
@@ -2591,8 +2599,10 @@ static int smu_set_fan_speed_percent(void *handle, u32 speed)
if (speed > 100)
speed = 100;
ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
- if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
+ if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
+ smu->user_dpm_profile.custom_fan_speed |= SMU_CUSTOM_FAN_SPEED_PWM;
smu->user_dpm_profile.fan_speed_percent = speed;
+ }
}
mutex_unlock(&smu->mutex);
--
2.29.0
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^ permalink raw reply related [flat|nested] 20+ messages in thread* RE: [PATCH 2/7] drm/amd/pm: record the RPM and PWM based fan speed settings
2021-07-07 1:56 ` [PATCH 2/7] drm/amd/pm: record the RPM and PWM based fan speed settings Evan Quan
@ 2021-07-07 4:53 ` Chen, Guchun
2021-07-07 8:53 ` Lazar, Lijo
1 sibling, 0 replies; 20+ messages in thread
From: Chen, Guchun @ 2021-07-07 4:53 UTC (permalink / raw)
To: Quan, Evan, amd-gfx; +Cc: Deucher, Alexander, Quan, Evan
[Public]
Two nit-picks.
Regards,
Guchun
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Evan Quan
Sent: Wednesday, July 7, 2021 9:57 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Quan, Evan <Evan.Quan@amd.com>
Subject: [PATCH 2/7] drm/amd/pm: record the RPM and PWM based fan speed settings
As the relationship "PWM = RPM / smu->fan_max_rpm" between fan speed PWM and RPM is not true for SMU11 ASICs. So, both the RPM and PWM settings need to be saved.
Change-Id: I318c134d442273d518b805339cdf383e151b935d
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 8 ++++++++
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 20 +++++++++++++++-----
2 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 6301e4cb3c2a..fa585f0be530 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -226,10 +226,18 @@ enum smu_memory_pool_size
SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000,
};
+enum custom_fan_speed_mode
+{
+ SMU_CUSTOM_FAN_SPEED_RPM = 1 << 0,
+ SMU_CUSTOM_FAN_SPEED_PWM = 1 << 1,
+};
+
[Guchun]A coding style problem. Put '{' on the same line as custom_fan_speed_mode.
struct smu_user_dpm_profile {
uint32_t fan_mode;
uint32_t power_limit;
+ uint32_t custom_fan_speed;
uint32_t fan_speed_percent;
+ uint32_t fan_speed_rpm;
uint32_t flags;
/* user clock state information */
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 576e9ea68fd1..9a25443988e3 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -414,6 +414,12 @@ static void smu_restore_dpm_user_profile(struct smu_context *smu)
if (ret)
dev_err(smu->adev->dev, "Failed to set manual fan speed\n");
}
+
+ if (!ret && smu->user_dpm_profile.fan_speed_rpm) {
+ ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm);
+ if (ret)
+ dev_err(smu->adev->dev, "Failed to set manual fan speed\n");
[Guchun] The error log is the same as above error case. It should help debug if we can improve it a bit to be well distinguished.
+ }
}
/* Disable restore flag */
@@ -2166,7 +2172,6 @@ static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) {
struct smu_context *smu = handle;
- u32 percent;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) @@ -2177,8 +2182,8 @@ static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
if (smu->ppt_funcs->set_fan_speed_rpm) {
ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
if (!ret && smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE) {
- percent = speed * 100 / smu->fan_max_rpm;
- smu->user_dpm_profile.fan_speed_percent = percent;
+ smu->user_dpm_profile.custom_fan_speed |= SMU_CUSTOM_FAN_SPEED_RPM;
+ smu->user_dpm_profile.fan_speed_rpm = speed;
}
}
@@ -2539,8 +2544,11 @@ static int smu_set_fan_control_mode(struct smu_context *smu, int value)
/* reset user dpm fan speed */
if (!ret && value != AMD_FAN_CTRL_MANUAL &&
- !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
+ !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
smu->user_dpm_profile.fan_speed_percent = 0;
+ smu->user_dpm_profile.fan_speed_rpm = 0;
+ smu->user_dpm_profile.custom_fan_speed = 0;
+ }
return ret;
}
@@ -2591,8 +2599,10 @@ static int smu_set_fan_speed_percent(void *handle, u32 speed)
if (speed > 100)
speed = 100;
ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
- if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
+ if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
+ smu->user_dpm_profile.custom_fan_speed |= SMU_CUSTOM_FAN_SPEED_PWM;
smu->user_dpm_profile.fan_speed_percent = speed;
+ }
}
mutex_unlock(&smu->mutex);
--
2.29.0
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^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 2/7] drm/amd/pm: record the RPM and PWM based fan speed settings
2021-07-07 1:56 ` [PATCH 2/7] drm/amd/pm: record the RPM and PWM based fan speed settings Evan Quan
2021-07-07 4:53 ` Chen, Guchun
@ 2021-07-07 8:53 ` Lazar, Lijo
1 sibling, 0 replies; 20+ messages in thread
From: Lazar, Lijo @ 2021-07-07 8:53 UTC (permalink / raw)
To: Evan Quan, amd-gfx; +Cc: Alexander.Deucher
On 7/7/2021 7:26 AM, Evan Quan wrote:
> As the relationship "PWM = RPM / smu->fan_max_rpm" between fan speed
> PWM and RPM is not true for SMU11 ASICs. So, both the RPM and PWM
> settings need to be saved.
>
> Change-Id: I318c134d442273d518b805339cdf383e151b935d
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
> drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 8 ++++++++
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 20 +++++++++++++++-----
> 2 files changed, 23 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> index 6301e4cb3c2a..fa585f0be530 100644
> --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> @@ -226,10 +226,18 @@ enum smu_memory_pool_size
> SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000,
> };
>
> +enum custom_fan_speed_mode
> +{
> + SMU_CUSTOM_FAN_SPEED_RPM = 1 << 0,
> + SMU_CUSTOM_FAN_SPEED_PWM = 1 << 1,
> +};
> +
> struct smu_user_dpm_profile {
> uint32_t fan_mode;
> uint32_t power_limit;
> + uint32_t custom_fan_speed;
Use the flags field to indicate if custom mode uses PWM or RPM, no need
to have a separate field.
Thanks,
Lijo
> uint32_t fan_speed_percent;
> + uint32_t fan_speed_rpm;
> uint32_t flags;
>
> /* user clock state information */
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 576e9ea68fd1..9a25443988e3 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -414,6 +414,12 @@ static void smu_restore_dpm_user_profile(struct smu_context *smu)
> if (ret)
> dev_err(smu->adev->dev, "Failed to set manual fan speed\n");
> }
> +
> + if (!ret && smu->user_dpm_profile.fan_speed_rpm) {
> + ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm);
> + if (ret)
> + dev_err(smu->adev->dev, "Failed to set manual fan speed\n");
> + }
> }
>
> /* Disable restore flag */
> @@ -2166,7 +2172,6 @@ static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
> static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
> {
> struct smu_context *smu = handle;
> - u32 percent;
> int ret = 0;
>
> if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
> @@ -2177,8 +2182,8 @@ static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
> if (smu->ppt_funcs->set_fan_speed_rpm) {
> ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
> if (!ret && smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE) {
> - percent = speed * 100 / smu->fan_max_rpm;
> - smu->user_dpm_profile.fan_speed_percent = percent;
> + smu->user_dpm_profile.custom_fan_speed |= SMU_CUSTOM_FAN_SPEED_RPM;
> + smu->user_dpm_profile.fan_speed_rpm = speed;
> }
> }
>
> @@ -2539,8 +2544,11 @@ static int smu_set_fan_control_mode(struct smu_context *smu, int value)
>
> /* reset user dpm fan speed */
> if (!ret && value != AMD_FAN_CTRL_MANUAL &&
> - !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
> + !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
> smu->user_dpm_profile.fan_speed_percent = 0;
> + smu->user_dpm_profile.fan_speed_rpm = 0;
> + smu->user_dpm_profile.custom_fan_speed = 0;
> + }
>
> return ret;
> }
> @@ -2591,8 +2599,10 @@ static int smu_set_fan_speed_percent(void *handle, u32 speed)
> if (speed > 100)
> speed = 100;
> ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
> - if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
> + if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
> + smu->user_dpm_profile.custom_fan_speed |= SMU_CUSTOM_FAN_SPEED_PWM;
> smu->user_dpm_profile.fan_speed_percent = speed;
> + }
> }
>
> mutex_unlock(&smu->mutex);
>
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 3/7] drm/amd/pm: correct the fan speed PWM retrieving
2021-07-07 1:56 [PATCH 1/7] drm/amd/pm: correct the fan speed RPM setting Evan Quan
2021-07-07 1:56 ` [PATCH 2/7] drm/amd/pm: record the RPM and PWM based fan speed settings Evan Quan
@ 2021-07-07 1:56 ` Evan Quan
2021-07-07 9:03 ` Lazar, Lijo
2021-07-07 1:56 ` [PATCH 4/7] drm/amd/pm: correct the fan speed RPM retrieving Evan Quan
` (5 subsequent siblings)
7 siblings, 1 reply; 20+ messages in thread
From: Evan Quan @ 2021-07-07 1:56 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Evan Quan
The relationship "PWM = RPM / smu->fan_max_rpm" between fan speed
PWM and RPM is not true for SMU11 ASICs. So, we need a new way to
retrieving the fan speed PWM.
Change-Id: Idfe0276d7113b9c921b88fa08085a33fd971d621
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
.../include/asic_reg/thm/thm_11_0_2_offset.h | 3 ++
.../include/asic_reg/thm/thm_11_0_2_sh_mask.h | 3 ++
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 3 ++
.../amd/pm/powerplay/hwmgr/vega20_thermal.c | 24 ++++++++-----
.../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 25 +------------
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 25 +------------
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 25 +------------
.../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 35 +++++++++++++++++++
8 files changed, 62 insertions(+), 81 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
index a485526f3a51..eca96abef445 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
@@ -49,4 +49,7 @@
#define mmTHM_BACO_CNTL 0x0081
#define mmTHM_BACO_CNTL_BASE_IDX 0
+#define mmCG_THERMAL_STATUS 0x006C
+#define mmCG_THERMAL_STATUS_BASE_IDX 0
+
#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_sh_mask.h
index d130d92aee19..f2f9eae9a68f 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_sh_mask.h
@@ -92,5 +92,8 @@
#define THM_TCON_THERM_TRIP__RSVD3_MASK 0x7FFFC000L
#define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK 0x80000000L
+#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9
+#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x0001FE00L
+
#endif
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 134a33e3de91..8e0f8e9a1665 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -226,6 +226,9 @@ int smu_v11_0_set_fan_speed_percent(struct smu_context *smu,
int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
uint32_t speed);
+int smu_v11_0_get_fan_speed_percent(struct smu_context *smu,
+ uint32_t *speed);
+
int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
uint32_t pstate);
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
index 269dd7e95a44..43d754952bd9 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
@@ -117,18 +117,24 @@ static int vega20_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
int vega20_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
uint32_t *speed)
{
- struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
- PPTable_t *pp_table = &(data->smc_state_table.pp_table);
- uint32_t current_rpm, percent = 0;
- int ret = 0;
+ struct amdgpu_device *adev = hwmgr->adev;
+ uint32_t duty100, duty;
+ uint64_t tmp64;
- ret = vega20_get_current_rpm(hwmgr, ¤t_rpm);
- if (ret)
- return ret;
+ duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
+ CG_FDO_CTRL1, FMAX_DUTY100);
+ duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
+ CG_THERMAL_STATUS, FDO_PWM_DUTY);
+
+ if (!duty100)
+ return -EINVAL;
- percent = current_rpm * 100 / pp_table->FanMaximumRpm;
+ tmp64 = (uint64_t)duty * 100;
+ do_div(tmp64, duty100);
+ *speed = (uint32_t)tmp64;
- *speed = percent > 100 ? 100 : percent;
+ if (*speed > 100)
+ *speed = 100;
return 0;
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 047adf6dd444..4a6544b8e05e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -1162,29 +1162,6 @@ static int arcturus_read_sensor(struct smu_context *smu,
return ret;
}
-static int arcturus_get_fan_speed_percent(struct smu_context *smu,
- uint32_t *speed)
-{
- int ret;
- u32 rpm;
-
- if (!speed)
- return -EINVAL;
-
- switch (smu_v11_0_get_fan_control_mode(smu)) {
- case AMD_FAN_CTRL_AUTO:
- ret = arcturus_get_smu_metrics_data(smu,
- METRICS_CURR_FANSPEED,
- &rpm);
- if (!ret && smu->fan_max_rpm)
- *speed = rpm * 100 / smu->fan_max_rpm;
- return ret;
- default:
- *speed = smu->user_dpm_profile.fan_speed_percent;
- return 0;
- }
-}
-
static int arcturus_get_fan_parameters(struct smu_context *smu)
{
PPTable_t *pptable = smu->smu_table.driver_pptable;
@@ -2268,7 +2245,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.print_clk_levels = arcturus_print_clk_levels,
.force_clk_levels = arcturus_force_clk_levels,
.read_sensor = arcturus_read_sensor,
- .get_fan_speed_percent = arcturus_get_fan_speed_percent,
+ .get_fan_speed_percent = smu_v11_0_get_fan_speed_percent,
.get_power_profile_mode = arcturus_get_power_profile_mode,
.set_power_profile_mode = arcturus_set_power_profile_mode,
.set_performance_level = arcturus_set_performance_level,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index d8a011483dcf..2ddf35788672 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -1668,29 +1668,6 @@ static bool navi10_is_dpm_running(struct smu_context *smu)
return !!(feature_enabled & SMC_DPM_FEATURE);
}
-static int navi10_get_fan_speed_percent(struct smu_context *smu,
- uint32_t *speed)
-{
- int ret;
- u32 rpm;
-
- if (!speed)
- return -EINVAL;
-
- switch (smu_v11_0_get_fan_control_mode(smu)) {
- case AMD_FAN_CTRL_AUTO:
- ret = navi1x_get_smu_metrics_data(smu,
- METRICS_CURR_FANSPEED,
- &rpm);
- if (!ret && smu->fan_max_rpm)
- *speed = rpm * 100 / smu->fan_max_rpm;
- return ret;
- default:
- *speed = smu->user_dpm_profile.fan_speed_percent;
- return 0;
- }
-}
-
static int navi10_get_fan_parameters(struct smu_context *smu)
{
PPTable_t *pptable = smu->smu_table.driver_pptable;
@@ -3204,7 +3181,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.display_config_changed = navi10_display_config_changed,
.notify_smc_display_config = navi10_notify_smc_display_config,
.is_dpm_running = navi10_is_dpm_running,
- .get_fan_speed_percent = navi10_get_fan_speed_percent,
+ .get_fan_speed_percent = smu_v11_0_get_fan_speed_percent,
.get_power_profile_mode = navi10_get_power_profile_mode,
.set_power_profile_mode = navi10_set_power_profile_mode,
.set_watermarks_table = navi10_set_watermarks_table,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index dad120294c19..e7686ce6744b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1355,29 +1355,6 @@ static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
return !!(feature_enabled & SMC_DPM_FEATURE);
}
-static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu,
- uint32_t *speed)
-{
- int ret;
- u32 rpm;
-
- if (!speed)
- return -EINVAL;
-
- switch (smu_v11_0_get_fan_control_mode(smu)) {
- case AMD_FAN_CTRL_AUTO:
- ret = sienna_cichlid_get_smu_metrics_data(smu,
- METRICS_CURR_FANSPEED,
- &rpm);
- if (!ret && smu->fan_max_rpm)
- *speed = rpm * 100 / smu->fan_max_rpm;
- return ret;
- default:
- *speed = smu->user_dpm_profile.fan_speed_percent;
- return 0;
- }
-}
-
static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
{
uint16_t *table_member;
@@ -3842,7 +3819,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.display_config_changed = sienna_cichlid_display_config_changed,
.notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
.is_dpm_running = sienna_cichlid_is_dpm_running,
- .get_fan_speed_percent = sienna_cichlid_get_fan_speed_percent,
+ .get_fan_speed_percent = smu_v11_0_get_fan_speed_percent,
.get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
.set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
.set_watermarks_table = sienna_cichlid_set_watermarks_table,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index fefc8e93fdc6..c49683b07076 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -1249,6 +1249,41 @@ int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
return ret;
}
+int smu_v11_0_get_fan_speed_percent(struct smu_context *smu,
+ uint32_t *speed)
+{
+ struct amdgpu_device *adev = smu->adev;
+ uint32_t duty100, duty;
+ uint64_t tmp64;
+
+ /*
+ * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
+ * detected via register retrieving. To workaround this, we will
+ * report the fan speed as 0 PWM if user just requested such.
+ */
+ if ((smu->user_dpm_profile.custom_fan_speed & SMU_CUSTOM_FAN_SPEED_PWM)
+ && !smu->user_dpm_profile.fan_speed_percent) {
+ *speed = 0;
+ return 0;
+ }
+
+ duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
+ CG_FDO_CTRL1, FMAX_DUTY100);
+ duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
+ CG_THERMAL_STATUS, FDO_PWM_DUTY);
+ if (!duty100)
+ return -EINVAL;
+
+ tmp64 = (uint64_t)duty * 100;
+ do_div(tmp64, duty100);
+ *speed = (uint32_t)tmp64;
+
+ if (*speed > 100)
+ *speed = 100;
+
+ return 0;
+}
+
int
smu_v11_0_set_fan_control_mode(struct smu_context *smu,
uint32_t mode)
--
2.29.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 3/7] drm/amd/pm: correct the fan speed PWM retrieving
2021-07-07 1:56 ` [PATCH 3/7] drm/amd/pm: correct the fan speed PWM retrieving Evan Quan
@ 2021-07-07 9:03 ` Lazar, Lijo
0 siblings, 0 replies; 20+ messages in thread
From: Lazar, Lijo @ 2021-07-07 9:03 UTC (permalink / raw)
To: Evan Quan, amd-gfx; +Cc: Alexander.Deucher
On 7/7/2021 7:26 AM, Evan Quan wrote:
> The relationship "PWM = RPM / smu->fan_max_rpm" between fan speed
> PWM and RPM is not true for SMU11 ASICs. So, we need a new way to
> retrieving the fan speed PWM.
>
> Change-Id: Idfe0276d7113b9c921b88fa08085a33fd971d621
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
> .../include/asic_reg/thm/thm_11_0_2_offset.h | 3 ++
> .../include/asic_reg/thm/thm_11_0_2_sh_mask.h | 3 ++
> drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 3 ++
> .../amd/pm/powerplay/hwmgr/vega20_thermal.c | 24 ++++++++-----
> .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 25 +------------
> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 25 +------------
> .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 25 +------------
> .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 35 +++++++++++++++++++
> 8 files changed, 62 insertions(+), 81 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
> index a485526f3a51..eca96abef445 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
> @@ -49,4 +49,7 @@
> #define mmTHM_BACO_CNTL 0x0081
> #define mmTHM_BACO_CNTL_BASE_IDX 0
>
> +#define mmCG_THERMAL_STATUS 0x006C
> +#define mmCG_THERMAL_STATUS_BASE_IDX 0
> +
> #endif
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_sh_mask.h
> index d130d92aee19..f2f9eae9a68f 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_sh_mask.h
> @@ -92,5 +92,8 @@
> #define THM_TCON_THERM_TRIP__RSVD3_MASK 0x7FFFC000L
> #define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK 0x80000000L
>
> +#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9
> +#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x0001FE00L
> +
> #endif
>
> diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> index 134a33e3de91..8e0f8e9a1665 100644
> --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> @@ -226,6 +226,9 @@ int smu_v11_0_set_fan_speed_percent(struct smu_context *smu,
> int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
> uint32_t speed);
>
> +int smu_v11_0_get_fan_speed_percent(struct smu_context *smu,
> + uint32_t *speed);
> +
> int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
> uint32_t pstate);
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
> index 269dd7e95a44..43d754952bd9 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
> @@ -117,18 +117,24 @@ static int vega20_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
> int vega20_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
> uint32_t *speed)
> {
> - struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
> - PPTable_t *pp_table = &(data->smc_state_table.pp_table);
> - uint32_t current_rpm, percent = 0;
> - int ret = 0;
> + struct amdgpu_device *adev = hwmgr->adev;
> + uint32_t duty100, duty;
> + uint64_t tmp64;
>
> - ret = vega20_get_current_rpm(hwmgr, ¤t_rpm);
> - if (ret)
> - return ret;
> + duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
> + CG_FDO_CTRL1, FMAX_DUTY100);
> + duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
> + CG_THERMAL_STATUS, FDO_PWM_DUTY);
> +
> + if (!duty100)
> + return -EINVAL;
>
> - percent = current_rpm * 100 / pp_table->FanMaximumRpm;
> + tmp64 = (uint64_t)duty * 100;
> + do_div(tmp64, duty100);
> + *speed = (uint32_t)tmp64;
>
> - *speed = percent > 100 ? 100 : percent;
> + if (*speed > 100)
> + *speed = 100;
Patch 5 avoids conversion as the relation between PWM and RPM is not
linear. Suggest to return PWM value (0-255) directly instead of
percentage. Since the function cannot be reused for rpm, it may make
sense to rename to set/get pwm instead of percent.
Thanks,
Lijo
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 4/7] drm/amd/pm: correct the fan speed RPM retrieving
2021-07-07 1:56 [PATCH 1/7] drm/amd/pm: correct the fan speed RPM setting Evan Quan
2021-07-07 1:56 ` [PATCH 2/7] drm/amd/pm: record the RPM and PWM based fan speed settings Evan Quan
2021-07-07 1:56 ` [PATCH 3/7] drm/amd/pm: correct the fan speed PWM retrieving Evan Quan
@ 2021-07-07 1:56 ` Evan Quan
2021-07-07 4:58 ` Chen, Guchun
2021-07-07 9:05 ` Lazar, Lijo
2021-07-07 1:56 ` [PATCH 5/7] drm/amd/pm: drop the unnecessary intermediate percent-based transition Evan Quan
` (4 subsequent siblings)
7 siblings, 2 replies; 20+ messages in thread
From: Evan Quan @ 2021-07-07 1:56 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Evan Quan
The relationship "PWM = RPM / smu->fan_max_rpm" between fan speed
PWM and RPM is not true for SMU11 ASICs. So, we need a new way to
retrieving the fan speed RPM.
Change-Id: Ife4298c8b7ec93ef023a7da27d59654e0444e044
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
.../include/asic_reg/thm/thm_11_0_2_offset.h | 3 ++
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 5 ++++
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 3 ++
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 7 ++---
.../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 24 ++++++++++++++++
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 24 ++++++++++++++++
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 21 ++++++++++++++
.../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 28 +++++++++++++++++++
8 files changed, 110 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
index eca96abef445..8474f419caa5 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
@@ -38,6 +38,9 @@
#define mmCG_TACH_CTRL 0x006a
#define mmCG_TACH_CTRL_BASE_IDX 0
+#define mmCG_TACH_STATUS 0x006b
+#define mmCG_TACH_STATUS_BASE_IDX 0
+
#define mmTHM_THERMAL_INT_ENA 0x000a
#define mmTHM_THERMAL_INT_ENA_BASE_IDX 0
#define mmTHM_THERMAL_INT_CTRL 0x000b
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index fa585f0be530..db5123fc6042 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -726,6 +726,11 @@ struct pptable_funcs {
*/
int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
+ /**
+ * @get_fan_speed_rpm: Get the current fan speed in rpm.
+ */
+ int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
+
/**
* @set_watermarks_table: Configure and upload the watermarks tables to
* the SMU.
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 8e0f8e9a1665..05c8fc8fc3f9 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -229,6 +229,9 @@ int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
int smu_v11_0_get_fan_speed_percent(struct smu_context *smu,
uint32_t *speed);
+int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
+ uint32_t *speed);
+
int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
uint32_t pstate);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 9a25443988e3..54fb3d7d23ee 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2614,17 +2614,14 @@ static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed)
{
struct smu_context *smu = handle;
int ret = 0;
- u32 percent;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return -EOPNOTSUPP;
mutex_lock(&smu->mutex);
- if (smu->ppt_funcs->get_fan_speed_percent) {
- ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent);
- *speed = percent * smu->fan_max_rpm / 100;
- }
+ if (smu->ppt_funcs->get_fan_speed_rpm)
+ ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
mutex_unlock(&smu->mutex);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 4a6544b8e05e..e3303c8dcaca 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -1162,6 +1162,29 @@ static int arcturus_read_sensor(struct smu_context *smu,
return ret;
}
+static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
+ uint32_t *speed)
+{
+ int ret = 0;
+
+ if (!speed)
+ return -EINVAL;
+
+ switch (smu_v11_0_get_fan_control_mode(smu)) {
+ case AMD_FAN_CTRL_AUTO:
+ ret = arcturus_get_smu_metrics_data(smu,
+ METRICS_CURR_FANSPEED,
+ speed);
+ break;
+ default:
+ ret = smu_v11_0_get_fan_speed_rpm(smu,
+ speed);
+ break;
+ }
+
+ return ret;
+}
+
static int arcturus_get_fan_parameters(struct smu_context *smu)
{
PPTable_t *pptable = smu->smu_table.driver_pptable;
@@ -2246,6 +2269,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.force_clk_levels = arcturus_force_clk_levels,
.read_sensor = arcturus_read_sensor,
.get_fan_speed_percent = smu_v11_0_get_fan_speed_percent,
+ .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
.get_power_profile_mode = arcturus_get_power_profile_mode,
.set_power_profile_mode = arcturus_set_power_profile_mode,
.set_performance_level = arcturus_set_performance_level,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 2ddf35788672..7dce5ea7c1a0 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -1668,6 +1668,29 @@ static bool navi10_is_dpm_running(struct smu_context *smu)
return !!(feature_enabled & SMC_DPM_FEATURE);
}
+static int navi10_get_fan_speed_rpm(struct smu_context *smu,
+ uint32_t *speed)
+{
+ int ret = 0;
+
+ if (!speed)
+ return -EINVAL;
+
+ switch (smu_v11_0_get_fan_control_mode(smu)) {
+ case AMD_FAN_CTRL_AUTO:
+ ret = navi10_get_smu_metrics_data(smu,
+ METRICS_CURR_FANSPEED,
+ speed);
+ break;
+ default:
+ ret = smu_v11_0_get_fan_speed_rpm(smu,
+ speed);
+ break;
+ }
+
+ return ret;
+}
+
static int navi10_get_fan_parameters(struct smu_context *smu)
{
PPTable_t *pptable = smu->smu_table.driver_pptable;
@@ -3182,6 +3205,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.notify_smc_display_config = navi10_notify_smc_display_config,
.is_dpm_running = navi10_is_dpm_running,
.get_fan_speed_percent = smu_v11_0_get_fan_speed_percent,
+ .get_fan_speed_rpm = navi10_get_fan_speed_rpm,
.get_power_profile_mode = navi10_get_power_profile_mode,
.set_power_profile_mode = navi10_set_power_profile_mode,
.set_watermarks_table = navi10_set_watermarks_table,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index e7686ce6744b..2f93dc4b5968 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1355,6 +1355,26 @@ static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
return !!(feature_enabled & SMC_DPM_FEATURE);
}
+static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
+ uint32_t *speed)
+{
+ int ret = 0;
+
+ if (!speed)
+ return -EINVAL;
+
+ /*
+ * For Sienna_Cichlid and later, the fan speed(rpm) reported
+ * by pmfw is always trustable(even when the fan control feature
+ * disabled or 0 RPM kicked in).
+ */
+ ret = sienna_cichlid_get_smu_metrics_data(smu,
+ METRICS_CURR_FANSPEED,
+ speed);
+
+ return ret;
+}
+
static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
{
uint16_t *table_member;
@@ -3820,6 +3840,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
.is_dpm_running = sienna_cichlid_is_dpm_running,
.get_fan_speed_percent = smu_v11_0_get_fan_speed_percent,
+ .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
.get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
.set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
.set_watermarks_table = sienna_cichlid_set_watermarks_table,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index c49683b07076..0cdf55a0dba2 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -1284,6 +1284,34 @@ int smu_v11_0_get_fan_speed_percent(struct smu_context *smu,
return 0;
}
+int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
+ uint32_t *speed)
+{
+ struct amdgpu_device *adev = smu->adev;
+ uint32_t tach_status, crystal_clock_freq;
+ uint64_t tmp64;
+
+ /*
+ * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
+ * detected via register retrieving. To workaround this, we will
+ * report the fan speed as 0 RPM if user just requested such.
+ */
+ if ((smu->user_dpm_profile.custom_fan_speed & SMU_CUSTOM_FAN_SPEED_RPM)
+ && !smu->user_dpm_profile.fan_speed_rpm) {
+ *speed = 0;
+ return 0;
+ }
+
+ crystal_clock_freq = amdgpu_asic_get_xclk(adev) / 4;
+ tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
+
+ tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS);
+ do_div(tmp64, tach_status);
+ *speed = (uint32_t)tmp64;
+
+ return 0;
+}
+
int
smu_v11_0_set_fan_control_mode(struct smu_context *smu,
uint32_t mode)
--
2.29.0
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^ permalink raw reply related [flat|nested] 20+ messages in thread* RE: [PATCH 4/7] drm/amd/pm: correct the fan speed RPM retrieving
2021-07-07 1:56 ` [PATCH 4/7] drm/amd/pm: correct the fan speed RPM retrieving Evan Quan
@ 2021-07-07 4:58 ` Chen, Guchun
2021-07-07 9:05 ` Lazar, Lijo
1 sibling, 0 replies; 20+ messages in thread
From: Chen, Guchun @ 2021-07-07 4:58 UTC (permalink / raw)
To: Quan, Evan, amd-gfx; +Cc: Deucher, Alexander, Quan, Evan
[Public]
A comment inline.
Regards,
Guchun
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Evan Quan
Sent: Wednesday, July 7, 2021 9:57 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Quan, Evan <Evan.Quan@amd.com>
Subject: [PATCH 4/7] drm/amd/pm: correct the fan speed RPM retrieving
The relationship "PWM = RPM / smu->fan_max_rpm" between fan speed PWM and RPM is not true for SMU11 ASICs. So, we need a new way to retrieving the fan speed RPM.
Change-Id: Ife4298c8b7ec93ef023a7da27d59654e0444e044
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
.../include/asic_reg/thm/thm_11_0_2_offset.h | 3 ++
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 5 ++++
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 3 ++
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 7 ++---
.../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 24 ++++++++++++++++
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 24 ++++++++++++++++
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 21 ++++++++++++++
.../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 28 +++++++++++++++++++
8 files changed, 110 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
index eca96abef445..8474f419caa5 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
@@ -38,6 +38,9 @@
#define mmCG_TACH_CTRL 0x006a
#define mmCG_TACH_CTRL_BASE_IDX 0
+#define mmCG_TACH_STATUS 0x006b
+#define mmCG_TACH_STATUS_BASE_IDX 0
+
#define mmTHM_THERMAL_INT_ENA 0x000a
#define mmTHM_THERMAL_INT_ENA_BASE_IDX 0
#define mmTHM_THERMAL_INT_CTRL 0x000b
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index fa585f0be530..db5123fc6042 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -726,6 +726,11 @@ struct pptable_funcs {
*/
int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
+ /**
+ * @get_fan_speed_rpm: Get the current fan speed in rpm.
+ */
+ int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
+
/**
* @set_watermarks_table: Configure and upload the watermarks tables to
* the SMU.
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 8e0f8e9a1665..05c8fc8fc3f9 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -229,6 +229,9 @@ int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu, int smu_v11_0_get_fan_speed_percent(struct smu_context *smu,
uint32_t *speed);
+int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
+ uint32_t *speed);
+
int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
uint32_t pstate);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 9a25443988e3..54fb3d7d23ee 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2614,17 +2614,14 @@ static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) {
struct smu_context *smu = handle;
int ret = 0;
- u32 percent;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return -EOPNOTSUPP;
mutex_lock(&smu->mutex);
- if (smu->ppt_funcs->get_fan_speed_percent) {
- ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent);
- *speed = percent * smu->fan_max_rpm / 100;
- }
+ if (smu->ppt_funcs->get_fan_speed_rpm)
+ ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
mutex_unlock(&smu->mutex);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 4a6544b8e05e..e3303c8dcaca 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -1162,6 +1162,29 @@ static int arcturus_read_sensor(struct smu_context *smu,
return ret;
}
+static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
+ uint32_t *speed)
+{
+ int ret = 0;
+
+ if (!speed)
+ return -EINVAL;
+
+ switch (smu_v11_0_get_fan_control_mode(smu)) {
+ case AMD_FAN_CTRL_AUTO:
+ ret = arcturus_get_smu_metrics_data(smu,
+ METRICS_CURR_FANSPEED,
+ speed);
+ break;
+ default:
+ ret = smu_v11_0_get_fan_speed_rpm(smu,
+ speed);
+ break;
+ }
+
+ return ret;
+}
+
static int arcturus_get_fan_parameters(struct smu_context *smu) {
PPTable_t *pptable = smu->smu_table.driver_pptable; @@ -2246,6 +2269,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.force_clk_levels = arcturus_force_clk_levels,
.read_sensor = arcturus_read_sensor,
.get_fan_speed_percent = smu_v11_0_get_fan_speed_percent,
+ .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
.get_power_profile_mode = arcturus_get_power_profile_mode,
.set_power_profile_mode = arcturus_set_power_profile_mode,
.set_performance_level = arcturus_set_performance_level, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 2ddf35788672..7dce5ea7c1a0 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -1668,6 +1668,29 @@ static bool navi10_is_dpm_running(struct smu_context *smu)
return !!(feature_enabled & SMC_DPM_FEATURE); }
+static int navi10_get_fan_speed_rpm(struct smu_context *smu,
+ uint32_t *speed)
+{
+ int ret = 0;
+
+ if (!speed)
+ return -EINVAL;
+
+ switch (smu_v11_0_get_fan_control_mode(smu)) {
+ case AMD_FAN_CTRL_AUTO:
+ ret = navi10_get_smu_metrics_data(smu,
+ METRICS_CURR_FANSPEED,
+ speed);
+ break;
+ default:
+ ret = smu_v11_0_get_fan_speed_rpm(smu,
+ speed);
+ break;
+ }
+
+ return ret;
+}
+
static int navi10_get_fan_parameters(struct smu_context *smu) {
PPTable_t *pptable = smu->smu_table.driver_pptable; @@ -3182,6 +3205,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.notify_smc_display_config = navi10_notify_smc_display_config,
.is_dpm_running = navi10_is_dpm_running,
.get_fan_speed_percent = smu_v11_0_get_fan_speed_percent,
+ .get_fan_speed_rpm = navi10_get_fan_speed_rpm,
.get_power_profile_mode = navi10_get_power_profile_mode,
.set_power_profile_mode = navi10_set_power_profile_mode,
.set_watermarks_table = navi10_set_watermarks_table, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index e7686ce6744b..2f93dc4b5968 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1355,6 +1355,26 @@ static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
return !!(feature_enabled & SMC_DPM_FEATURE); }
+static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
+ uint32_t *speed)
+{
+ int ret = 0;
+
+ if (!speed)
+ return -EINVAL;
+
+ /*
+ * For Sienna_Cichlid and later, the fan speed(rpm) reported
+ * by pmfw is always trustable(even when the fan control feature
+ * disabled or 0 RPM kicked in).
+ */
+ ret = sienna_cichlid_get_smu_metrics_data(smu,
+ METRICS_CURR_FANSPEED,
+ speed);
+
+ return ret;
[Guchun] More simple if directly return function sienna_cichlid_get_smu_metrics_data, then variable 'ret' can be dropped.
+}
+
static int sienna_cichlid_get_fan_parameters(struct smu_context *smu) {
uint16_t *table_member;
@@ -3820,6 +3840,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
.is_dpm_running = sienna_cichlid_is_dpm_running,
.get_fan_speed_percent = smu_v11_0_get_fan_speed_percent,
+ .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
.get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
.set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
.set_watermarks_table = sienna_cichlid_set_watermarks_table,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index c49683b07076..0cdf55a0dba2 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -1284,6 +1284,34 @@ int smu_v11_0_get_fan_speed_percent(struct smu_context *smu,
return 0;
}
+int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
+ uint32_t *speed)
+{
+ struct amdgpu_device *adev = smu->adev;
+ uint32_t tach_status, crystal_clock_freq;
+ uint64_t tmp64;
+
+ /*
+ * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
+ * detected via register retrieving. To workaround this, we will
+ * report the fan speed as 0 RPM if user just requested such.
+ */
+ if ((smu->user_dpm_profile.custom_fan_speed & SMU_CUSTOM_FAN_SPEED_RPM)
+ && !smu->user_dpm_profile.fan_speed_rpm) {
+ *speed = 0;
+ return 0;
+ }
+
+ crystal_clock_freq = amdgpu_asic_get_xclk(adev) / 4;
+ tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
+
+ tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS);
+ do_div(tmp64, tach_status);
+ *speed = (uint32_t)tmp64;
+
+ return 0;
+}
+
int
smu_v11_0_set_fan_control_mode(struct smu_context *smu,
uint32_t mode)
--
2.29.0
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^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 4/7] drm/amd/pm: correct the fan speed RPM retrieving
2021-07-07 1:56 ` [PATCH 4/7] drm/amd/pm: correct the fan speed RPM retrieving Evan Quan
2021-07-07 4:58 ` Chen, Guchun
@ 2021-07-07 9:05 ` Lazar, Lijo
1 sibling, 0 replies; 20+ messages in thread
From: Lazar, Lijo @ 2021-07-07 9:05 UTC (permalink / raw)
To: Evan Quan, amd-gfx; +Cc: Alexander.Deucher
On 7/7/2021 7:26 AM, Evan Quan wrote:
> The relationship "PWM = RPM / smu->fan_max_rpm" between fan speed
> PWM and RPM is not true for SMU11 ASICs. So, we need a new way to
> retrieving the fan speed RPM.
>
> Change-Id: Ife4298c8b7ec93ef023a7da27d59654e0444e044
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
> .../include/asic_reg/thm/thm_11_0_2_offset.h | 3 ++
> drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 5 ++++
> drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 3 ++
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 7 ++---
> .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 24 ++++++++++++++++
> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 24 ++++++++++++++++
> .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 21 ++++++++++++++
> .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 28 +++++++++++++++++++
> 8 files changed, 110 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
> index eca96abef445..8474f419caa5 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
> @@ -38,6 +38,9 @@
> #define mmCG_TACH_CTRL 0x006a
> #define mmCG_TACH_CTRL_BASE_IDX 0
>
> +#define mmCG_TACH_STATUS 0x006b
> +#define mmCG_TACH_STATUS_BASE_IDX 0
> +
> #define mmTHM_THERMAL_INT_ENA 0x000a
> #define mmTHM_THERMAL_INT_ENA_BASE_IDX 0
> #define mmTHM_THERMAL_INT_CTRL 0x000b
> diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> index fa585f0be530..db5123fc6042 100644
> --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> @@ -726,6 +726,11 @@ struct pptable_funcs {
> */
> int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
>
> + /**
> + * @get_fan_speed_rpm: Get the current fan speed in rpm.
> + */
> + int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
> +
> /**
> * @set_watermarks_table: Configure and upload the watermarks tables to
> * the SMU.
> diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> index 8e0f8e9a1665..05c8fc8fc3f9 100644
> --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> @@ -229,6 +229,9 @@ int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
> int smu_v11_0_get_fan_speed_percent(struct smu_context *smu,
> uint32_t *speed);
>
> +int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
> + uint32_t *speed);
> +
> int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
> uint32_t pstate);
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 9a25443988e3..54fb3d7d23ee 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -2614,17 +2614,14 @@ static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed)
> {
> struct smu_context *smu = handle;
> int ret = 0;
> - u32 percent;
>
> if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
> return -EOPNOTSUPP;
>
> mutex_lock(&smu->mutex);
>
> - if (smu->ppt_funcs->get_fan_speed_percent) {
> - ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent);
> - *speed = percent * smu->fan_max_rpm / 100;
> - }
> + if (smu->ppt_funcs->get_fan_speed_rpm)
> + ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
>
> mutex_unlock(&smu->mutex);
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> index 4a6544b8e05e..e3303c8dcaca 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> @@ -1162,6 +1162,29 @@ static int arcturus_read_sensor(struct smu_context *smu,
> return ret;
> }
>
> +static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
> + uint32_t *speed)
> +{
> + int ret = 0;
> +
> + if (!speed)
> + return -EINVAL;
> +
> + switch (smu_v11_0_get_fan_control_mode(smu)) {
> + case AMD_FAN_CTRL_AUTO:
> + ret = arcturus_get_smu_metrics_data(smu,
> + METRICS_CURR_FANSPEED,
> + speed);
> + break;
> + default:
> + ret = smu_v11_0_get_fan_speed_rpm(smu,
> + speed);
> + break;
> + }
> +
> + return ret;
> +}
> +
> static int arcturus_get_fan_parameters(struct smu_context *smu)
> {
> PPTable_t *pptable = smu->smu_table.driver_pptable;
> @@ -2246,6 +2269,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
> .force_clk_levels = arcturus_force_clk_levels,
> .read_sensor = arcturus_read_sensor,
> .get_fan_speed_percent = smu_v11_0_get_fan_speed_percent,
> + .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
> .get_power_profile_mode = arcturus_get_power_profile_mode,
> .set_power_profile_mode = arcturus_set_power_profile_mode,
> .set_performance_level = arcturus_set_performance_level,
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> index 2ddf35788672..7dce5ea7c1a0 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> @@ -1668,6 +1668,29 @@ static bool navi10_is_dpm_running(struct smu_context *smu)
> return !!(feature_enabled & SMC_DPM_FEATURE);
> }
>
> +static int navi10_get_fan_speed_rpm(struct smu_context *smu,
> + uint32_t *speed)
> +{
> + int ret = 0;
> +
> + if (!speed)
> + return -EINVAL;
> +
> + switch (smu_v11_0_get_fan_control_mode(smu)) {
> + case AMD_FAN_CTRL_AUTO:
> + ret = navi10_get_smu_metrics_data(smu,
> + METRICS_CURR_FANSPEED,
> + speed);
> + break;
> + default:
> + ret = smu_v11_0_get_fan_speed_rpm(smu,
> + speed);
> + break;
> + }
> +
> + return ret;
> +}
> +
> static int navi10_get_fan_parameters(struct smu_context *smu)
> {
> PPTable_t *pptable = smu->smu_table.driver_pptable;
> @@ -3182,6 +3205,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
> .notify_smc_display_config = navi10_notify_smc_display_config,
> .is_dpm_running = navi10_is_dpm_running,
> .get_fan_speed_percent = smu_v11_0_get_fan_speed_percent,
> + .get_fan_speed_rpm = navi10_get_fan_speed_rpm,
> .get_power_profile_mode = navi10_get_power_profile_mode,
> .set_power_profile_mode = navi10_set_power_profile_mode,
> .set_watermarks_table = navi10_set_watermarks_table,
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index e7686ce6744b..2f93dc4b5968 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -1355,6 +1355,26 @@ static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
> return !!(feature_enabled & SMC_DPM_FEATURE);
> }
>
> +static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
> + uint32_t *speed)
> +{
> + int ret = 0;
> +
> + if (!speed)
> + return -EINVAL;
> +
> + /*
> + * For Sienna_Cichlid and later, the fan speed(rpm) reported
> + * by pmfw is always trustable(even when the fan control feature
> + * disabled or 0 RPM kicked in).
> + */
> + ret = sienna_cichlid_get_smu_metrics_data(smu,
> + METRICS_CURR_FANSPEED,
> + speed);
> +
> + return ret;
> +}
> +
> static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
> {
> uint16_t *table_member;
> @@ -3820,6 +3840,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
> .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
> .is_dpm_running = sienna_cichlid_is_dpm_running,
> .get_fan_speed_percent = smu_v11_0_get_fan_speed_percent,
> + .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
> .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
> .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
> .set_watermarks_table = sienna_cichlid_set_watermarks_table,
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> index c49683b07076..0cdf55a0dba2 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> @@ -1284,6 +1284,34 @@ int smu_v11_0_get_fan_speed_percent(struct smu_context *smu,
> return 0;
> }
>
> +int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
> + uint32_t *speed)
> +{
> + struct amdgpu_device *adev = smu->adev;
> + uint32_t tach_status, crystal_clock_freq;
> + uint64_t tmp64;
> +
> + /*
> + * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
> + * detected via register retrieving. To workaround this, we will
> + * report the fan speed as 0 RPM if user just requested such.
> + */
> + if ((smu->user_dpm_profile.custom_fan_speed & SMU_CUSTOM_FAN_SPEED_RPM)
> + && !smu->user_dpm_profile.fan_speed_rpm) {
> + *speed = 0;
> + return 0;
> + }
> +
> + crystal_clock_freq = amdgpu_asic_get_xclk(adev) / 4;
Same frequency comment - no need to related to ASIC refclk, define and
use fan control crystal clock.
Thanks,
Lijo
> + tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
> +
> + tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS);
> + do_div(tmp64, tach_status);
> + *speed = (uint32_t)tmp64;
> +
> + return 0;
> +}
> +
> int
> smu_v11_0_set_fan_control_mode(struct smu_context *smu,
> uint32_t mode)
>
_______________________________________________
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 5/7] drm/amd/pm: drop the unnecessary intermediate percent-based transition
2021-07-07 1:56 [PATCH 1/7] drm/amd/pm: correct the fan speed RPM setting Evan Quan
` (2 preceding siblings ...)
2021-07-07 1:56 ` [PATCH 4/7] drm/amd/pm: correct the fan speed RPM retrieving Evan Quan
@ 2021-07-07 1:56 ` Evan Quan
2021-07-07 5:00 ` Chen, Guchun
` (2 more replies)
2021-07-07 1:56 ` [PATCH 6/7] drm/amd/pm: drop unnecessary manual mode check Evan Quan
` (3 subsequent siblings)
7 siblings, 3 replies; 20+ messages in thread
From: Evan Quan @ 2021-07-07 1:56 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Evan Quan
Currently, the readout of fan speed pwm is transited into percent-based
and then pwm-based. However, the transition into percent-based is totally
unnecessary and make the final output less accurate.
Change-Id: Ib99e088cda1875b4e2601f7077a178af6fe8a6cb
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 4 ----
.../gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 4 ++--
.../gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c | 12 ++++++------
.../gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 2 +-
.../drm/amd/pm/powerplay/hwmgr/vega10_thermal.c | 10 +++++-----
.../gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 2 +-
.../drm/amd/pm/powerplay/hwmgr/vega20_thermal.c | 12 ++++++------
drivers/gpu/drm/amd/pm/powerplay/si_dpm.c | 10 +++++-----
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 12 ++----------
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 14 +++++++-------
10 files changed, 35 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 769f58d5ae1a..e9c98e3f4cfb 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2469,8 +2469,6 @@ static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
return err;
}
- value = (value * 100) / 255;
-
if (adev->powerplay.pp_funcs->set_fan_speed_percent)
err = amdgpu_dpm_set_fan_speed_percent(adev, value);
else
@@ -2515,8 +2513,6 @@ static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
if (err)
return err;
- speed = (speed * 255) / 100;
-
return sprintf(buf, "%i\n", speed);
}
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
index 0541bfc81c1b..aa353a628c50 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
@@ -3212,7 +3212,7 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
if (!ret) {
if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
- smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
+ smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 255);
else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr);
}
@@ -4988,7 +4988,7 @@ static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
{
switch (mode) {
case AMD_FAN_CTRL_NONE:
- smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
+ smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 255);
break;
case AMD_FAN_CTRL_MANUAL:
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
index 6cfe148ed45b..70ccc127e3fd 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
@@ -70,12 +70,12 @@ int smu7_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
return -EINVAL;
- tmp64 = (uint64_t)duty * 100;
+ tmp64 = (uint64_t)duty * 255;
do_div(tmp64, duty100);
*speed = (uint32_t)tmp64;
- if (*speed > 100)
- *speed = 100;
+ if (*speed > 255)
+ *speed = 255;
return 0;
}
@@ -214,8 +214,8 @@ int smu7_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
if (hwmgr->thermal_controller.fanInfo.bNoFan)
return 0;
- if (speed > 100)
- speed = 100;
+ if (speed > 255)
+ speed = 255;
if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
@@ -227,7 +227,7 @@ int smu7_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
return -EINVAL;
tmp64 = (uint64_t)speed * duty100;
- do_div(tmp64, 100);
+ do_div(tmp64, 255);
duty = (uint32_t)tmp64;
PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
index 25979106fd25..44c5e2588046 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
@@ -4199,7 +4199,7 @@ static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
switch (mode) {
case AMD_FAN_CTRL_NONE:
- vega10_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
+ vega10_fan_ctrl_set_fan_speed_percent(hwmgr, 255);
break;
case AMD_FAN_CTRL_MANUAL:
if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
index 9b46b27bd30c..6b4c4294afca 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
@@ -78,11 +78,11 @@ int vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
if (hwmgr->thermal_controller.
advanceFanControlParameters.usMaxFanRPM != 0)
- percent = current_rpm * 100 /
+ percent = current_rpm * 255 /
hwmgr->thermal_controller.
advanceFanControlParameters.usMaxFanRPM;
- *speed = percent > 100 ? 100 : percent;
+ *speed = percent > 255 ? 255 : percent;
return 0;
}
@@ -257,8 +257,8 @@ int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
if (hwmgr->thermal_controller.fanInfo.bNoFan)
return 0;
- if (speed > 100)
- speed = 100;
+ if (speed > 255)
+ speed = 255;
if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
@@ -270,7 +270,7 @@ int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
return -EINVAL;
tmp64 = (uint64_t)speed * duty100;
- do_div(tmp64, 100);
+ do_div(tmp64, 255);
duty = (uint32_t)tmp64;
WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
index 0791309586c5..cbe5f8027ee0 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
@@ -2769,7 +2769,7 @@ static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
{
switch (mode) {
case AMD_FAN_CTRL_NONE:
- vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
+ vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 255);
break;
case AMD_FAN_CTRL_MANUAL:
if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
index 43d754952bd9..eb007c00d7c6 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
@@ -129,12 +129,12 @@ int vega20_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
if (!duty100)
return -EINVAL;
- tmp64 = (uint64_t)duty * 100;
+ tmp64 = (uint64_t)duty * 255;
do_div(tmp64, duty100);
*speed = (uint32_t)tmp64;
- if (*speed > 100)
- *speed = 100;
+ if (*speed > 255)
+ *speed = 255;
return 0;
}
@@ -147,8 +147,8 @@ int vega20_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
uint32_t duty;
uint64_t tmp64;
- if (speed > 100)
- speed = 100;
+ if (speed > 255)
+ speed = 255;
if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
@@ -160,7 +160,7 @@ int vega20_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
return -EINVAL;
tmp64 = (uint64_t)speed * duty100;
- do_div(tmp64, 100);
+ do_div(tmp64, 255);
duty = (uint32_t)tmp64;
WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
diff --git a/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c b/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c
index 15c0b8af376f..96ca359c10a5 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c
@@ -6555,12 +6555,12 @@ static int si_dpm_get_fan_speed_percent(void *handle,
if (duty100 == 0)
return -EINVAL;
- tmp64 = (u64)duty * 100;
+ tmp64 = (u64)duty * 255;
do_div(tmp64, duty100);
*speed = (u32)tmp64;
- if (*speed > 100)
- *speed = 100;
+ if (*speed > 255)
+ *speed = 255;
return 0;
}
@@ -6580,7 +6580,7 @@ static int si_dpm_set_fan_speed_percent(void *handle,
if (si_pi->fan_is_controlled_by_smc)
return -EINVAL;
- if (speed > 100)
+ if (speed > 255)
return -EINVAL;
duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
@@ -6589,7 +6589,7 @@ static int si_dpm_set_fan_speed_percent(void *handle,
return -EINVAL;
tmp64 = (u64)speed * duty100;
- do_div(tmp64, 100);
+ do_div(tmp64, 255);
duty = (u32)tmp64;
tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 54fb3d7d23ee..94c15526ad21 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2565,23 +2565,17 @@ static int smu_get_fan_speed_percent(void *handle, u32 *speed)
{
struct smu_context *smu = handle;
int ret = 0;
- uint32_t percent;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return -EOPNOTSUPP;
mutex_lock(&smu->mutex);
- if (smu->ppt_funcs->get_fan_speed_percent) {
- ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent);
- if (!ret) {
- *speed = percent > 100 ? 100 : percent;
- }
- }
+ if (smu->ppt_funcs->get_fan_speed_percent)
+ ret = smu->ppt_funcs->get_fan_speed_percent(smu, speed);
mutex_unlock(&smu->mutex);
-
return ret;
}
@@ -2596,8 +2590,6 @@ static int smu_set_fan_speed_percent(void *handle, u32 speed)
mutex_lock(&smu->mutex);
if (smu->ppt_funcs->set_fan_speed_percent) {
- if (speed > 100)
- speed = 100;
ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
smu->user_dpm_profile.custom_fan_speed |= SMU_CUSTOM_FAN_SPEED_PWM;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 0cdf55a0dba2..f0ae0920c07e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -1191,8 +1191,8 @@ smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
uint32_t duty100, duty;
uint64_t tmp64;
- if (speed > 100)
- speed = 100;
+ if (speed > 255)
+ speed = 255;
if (smu_v11_0_auto_fan_control(smu, 0))
return -EINVAL;
@@ -1203,7 +1203,7 @@ smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
return -EINVAL;
tmp64 = (uint64_t)speed * duty100;
- do_div(tmp64, 100);
+ do_div(tmp64, 255);
duty = (uint32_t)tmp64;
WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
@@ -1274,12 +1274,12 @@ int smu_v11_0_get_fan_speed_percent(struct smu_context *smu,
if (!duty100)
return -EINVAL;
- tmp64 = (uint64_t)duty * 100;
+ tmp64 = (uint64_t)duty * 255;
do_div(tmp64, duty100);
*speed = (uint32_t)tmp64;
- if (*speed > 100)
- *speed = 100;
+ if (*speed > 255)
+ *speed = 255;
return 0;
}
@@ -1320,7 +1320,7 @@ smu_v11_0_set_fan_control_mode(struct smu_context *smu,
switch (mode) {
case AMD_FAN_CTRL_NONE:
- ret = smu_v11_0_set_fan_speed_percent(smu, 100);
+ ret = smu_v11_0_set_fan_speed_percent(smu, 255);
break;
case AMD_FAN_CTRL_MANUAL:
ret = smu_v11_0_auto_fan_control(smu, 0);
--
2.29.0
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread* RE: [PATCH 5/7] drm/amd/pm: drop the unnecessary intermediate percent-based transition
2021-07-07 1:56 ` [PATCH 5/7] drm/amd/pm: drop the unnecessary intermediate percent-based transition Evan Quan
@ 2021-07-07 5:00 ` Chen, Guchun
2021-07-07 6:26 ` Nils Wallménius
2021-07-07 9:07 ` Lazar, Lijo
2 siblings, 0 replies; 20+ messages in thread
From: Chen, Guchun @ 2021-07-07 5:00 UTC (permalink / raw)
To: Quan, Evan, amd-gfx; +Cc: Deucher, Alexander, Quan, Evan
[Public]
Seems 255 and 100 are used multiple times in different files. Is it better to define them as a macro?
Regards,
Guchun
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Evan Quan
Sent: Wednesday, July 7, 2021 9:57 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Quan, Evan <Evan.Quan@amd.com>
Subject: [PATCH 5/7] drm/amd/pm: drop the unnecessary intermediate percent-based transition
Currently, the readout of fan speed pwm is transited into percent-based and then pwm-based. However, the transition into percent-based is totally unnecessary and make the final output less accurate.
Change-Id: Ib99e088cda1875b4e2601f7077a178af6fe8a6cb
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 4 ----
.../gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 4 ++--
.../gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c | 12 ++++++------ .../gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 2 +-
.../drm/amd/pm/powerplay/hwmgr/vega10_thermal.c | 10 +++++-----
.../gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 2 +-
.../drm/amd/pm/powerplay/hwmgr/vega20_thermal.c | 12 ++++++------
drivers/gpu/drm/amd/pm/powerplay/si_dpm.c | 10 +++++-----
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 12 ++----------
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 14 +++++++-------
10 files changed, 35 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 769f58d5ae1a..e9c98e3f4cfb 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2469,8 +2469,6 @@ static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
return err;
}
- value = (value * 100) / 255;
-
if (adev->powerplay.pp_funcs->set_fan_speed_percent)
err = amdgpu_dpm_set_fan_speed_percent(adev, value);
else
@@ -2515,8 +2513,6 @@ static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
if (err)
return err;
- speed = (speed * 255) / 100;
-
return sprintf(buf, "%i\n", speed);
}
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
index 0541bfc81c1b..aa353a628c50 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
@@ -3212,7 +3212,7 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
if (!ret) {
if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
- smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
+ smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 255);
else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr);
}
@@ -4988,7 +4988,7 @@ static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) {
switch (mode) {
case AMD_FAN_CTRL_NONE:
- smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
+ smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 255);
break;
case AMD_FAN_CTRL_MANUAL:
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
index 6cfe148ed45b..70ccc127e3fd 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
@@ -70,12 +70,12 @@ int smu7_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
return -EINVAL;
- tmp64 = (uint64_t)duty * 100;
+ tmp64 = (uint64_t)duty * 255;
do_div(tmp64, duty100);
*speed = (uint32_t)tmp64;
- if (*speed > 100)
- *speed = 100;
+ if (*speed > 255)
+ *speed = 255;
return 0;
}
@@ -214,8 +214,8 @@ int smu7_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
if (hwmgr->thermal_controller.fanInfo.bNoFan)
return 0;
- if (speed > 100)
- speed = 100;
+ if (speed > 255)
+ speed = 255;
if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
@@ -227,7 +227,7 @@ int smu7_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
return -EINVAL;
tmp64 = (uint64_t)speed * duty100;
- do_div(tmp64, 100);
+ do_div(tmp64, 255);
duty = (uint32_t)tmp64;
PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
index 25979106fd25..44c5e2588046 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
@@ -4199,7 +4199,7 @@ static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
switch (mode) {
case AMD_FAN_CTRL_NONE:
- vega10_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
+ vega10_fan_ctrl_set_fan_speed_percent(hwmgr, 255);
break;
case AMD_FAN_CTRL_MANUAL:
if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
index 9b46b27bd30c..6b4c4294afca 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
@@ -78,11 +78,11 @@ int vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
if (hwmgr->thermal_controller.
advanceFanControlParameters.usMaxFanRPM != 0)
- percent = current_rpm * 100 /
+ percent = current_rpm * 255 /
hwmgr->thermal_controller.
advanceFanControlParameters.usMaxFanRPM;
- *speed = percent > 100 ? 100 : percent;
+ *speed = percent > 255 ? 255 : percent;
return 0;
}
@@ -257,8 +257,8 @@ int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
if (hwmgr->thermal_controller.fanInfo.bNoFan)
return 0;
- if (speed > 100)
- speed = 100;
+ if (speed > 255)
+ speed = 255;
if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
@@ -270,7 +270,7 @@ int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
return -EINVAL;
tmp64 = (uint64_t)speed * duty100;
- do_div(tmp64, 100);
+ do_div(tmp64, 255);
duty = (uint32_t)tmp64;
WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
index 0791309586c5..cbe5f8027ee0 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
@@ -2769,7 +2769,7 @@ static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) {
switch (mode) {
case AMD_FAN_CTRL_NONE:
- vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
+ vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 255);
break;
case AMD_FAN_CTRL_MANUAL:
if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
index 43d754952bd9..eb007c00d7c6 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
@@ -129,12 +129,12 @@ int vega20_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
if (!duty100)
return -EINVAL;
- tmp64 = (uint64_t)duty * 100;
+ tmp64 = (uint64_t)duty * 255;
do_div(tmp64, duty100);
*speed = (uint32_t)tmp64;
- if (*speed > 100)
- *speed = 100;
+ if (*speed > 255)
+ *speed = 255;
return 0;
}
@@ -147,8 +147,8 @@ int vega20_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
uint32_t duty;
uint64_t tmp64;
- if (speed > 100)
- speed = 100;
+ if (speed > 255)
+ speed = 255;
if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
@@ -160,7 +160,7 @@ int vega20_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
return -EINVAL;
tmp64 = (uint64_t)speed * duty100;
- do_div(tmp64, 100);
+ do_div(tmp64, 255);
duty = (uint32_t)tmp64;
WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
diff --git a/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c b/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c
index 15c0b8af376f..96ca359c10a5 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c
@@ -6555,12 +6555,12 @@ static int si_dpm_get_fan_speed_percent(void *handle,
if (duty100 == 0)
return -EINVAL;
- tmp64 = (u64)duty * 100;
+ tmp64 = (u64)duty * 255;
do_div(tmp64, duty100);
*speed = (u32)tmp64;
- if (*speed > 100)
- *speed = 100;
+ if (*speed > 255)
+ *speed = 255;
return 0;
}
@@ -6580,7 +6580,7 @@ static int si_dpm_set_fan_speed_percent(void *handle,
if (si_pi->fan_is_controlled_by_smc)
return -EINVAL;
- if (speed > 100)
+ if (speed > 255)
return -EINVAL;
duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; @@ -6589,7 +6589,7 @@ static int si_dpm_set_fan_speed_percent(void *handle,
return -EINVAL;
tmp64 = (u64)speed * duty100;
- do_div(tmp64, 100);
+ do_div(tmp64, 255);
duty = (u32)tmp64;
tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 54fb3d7d23ee..94c15526ad21 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2565,23 +2565,17 @@ static int smu_get_fan_speed_percent(void *handle, u32 *speed) {
struct smu_context *smu = handle;
int ret = 0;
- uint32_t percent;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return -EOPNOTSUPP;
mutex_lock(&smu->mutex);
- if (smu->ppt_funcs->get_fan_speed_percent) {
- ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent);
- if (!ret) {
- *speed = percent > 100 ? 100 : percent;
- }
- }
+ if (smu->ppt_funcs->get_fan_speed_percent)
+ ret = smu->ppt_funcs->get_fan_speed_percent(smu, speed);
mutex_unlock(&smu->mutex);
-
return ret;
}
@@ -2596,8 +2590,6 @@ static int smu_set_fan_speed_percent(void *handle, u32 speed)
mutex_lock(&smu->mutex);
if (smu->ppt_funcs->set_fan_speed_percent) {
- if (speed > 100)
- speed = 100;
ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
smu->user_dpm_profile.custom_fan_speed |= SMU_CUSTOM_FAN_SPEED_PWM; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 0cdf55a0dba2..f0ae0920c07e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -1191,8 +1191,8 @@ smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
uint32_t duty100, duty;
uint64_t tmp64;
- if (speed > 100)
- speed = 100;
+ if (speed > 255)
+ speed = 255;
if (smu_v11_0_auto_fan_control(smu, 0))
return -EINVAL;
@@ -1203,7 +1203,7 @@ smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
return -EINVAL;
tmp64 = (uint64_t)speed * duty100;
- do_div(tmp64, 100);
+ do_div(tmp64, 255);
duty = (uint32_t)tmp64;
WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
@@ -1274,12 +1274,12 @@ int smu_v11_0_get_fan_speed_percent(struct smu_context *smu,
if (!duty100)
return -EINVAL;
- tmp64 = (uint64_t)duty * 100;
+ tmp64 = (uint64_t)duty * 255;
do_div(tmp64, duty100);
*speed = (uint32_t)tmp64;
- if (*speed > 100)
- *speed = 100;
+ if (*speed > 255)
+ *speed = 255;
return 0;
}
@@ -1320,7 +1320,7 @@ smu_v11_0_set_fan_control_mode(struct smu_context *smu,
switch (mode) {
case AMD_FAN_CTRL_NONE:
- ret = smu_v11_0_set_fan_speed_percent(smu, 100);
+ ret = smu_v11_0_set_fan_speed_percent(smu, 255);
break;
case AMD_FAN_CTRL_MANUAL:
ret = smu_v11_0_auto_fan_control(smu, 0);
--
2.29.0
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^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 5/7] drm/amd/pm: drop the unnecessary intermediate percent-based transition
2021-07-07 1:56 ` [PATCH 5/7] drm/amd/pm: drop the unnecessary intermediate percent-based transition Evan Quan
2021-07-07 5:00 ` Chen, Guchun
@ 2021-07-07 6:26 ` Nils Wallménius
2021-07-07 9:07 ` Lazar, Lijo
2 siblings, 0 replies; 20+ messages in thread
From: Nils Wallménius @ 2021-07-07 6:26 UTC (permalink / raw)
To: Evan Quan; +Cc: Alex Deucher, amd-gfx
[-- Attachment #1.1: Type: text/plain, Size: 14391 bytes --]
Hi Evan,
Bit of a drive by comment but I think that maybe all the
*_fan_speed_percent() function names are a bit confusing if they no longer
operate on percents but on a duty cycle unit of 0-255. No good idea what to
call them though :-\
Also max() could be used in a bunch of places instead of
if (speed > 255)
speed = 255;
Regards,
Nils
Den ons 7 juli 2021 03:59Evan Quan <evan.quan@amd.com> skrev:
> Currently, the readout of fan speed pwm is transited into percent-based
> and then pwm-based. However, the transition into percent-based is totally
> unnecessary and make the final output less accurate.
>
> Change-Id: Ib99e088cda1875b4e2601f7077a178af6fe8a6cb
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
> drivers/gpu/drm/amd/pm/amdgpu_pm.c | 4 ----
> .../gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 4 ++--
> .../gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c | 12 ++++++------
> .../gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 2 +-
> .../drm/amd/pm/powerplay/hwmgr/vega10_thermal.c | 10 +++++-----
> .../gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 2 +-
> .../drm/amd/pm/powerplay/hwmgr/vega20_thermal.c | 12 ++++++------
> drivers/gpu/drm/amd/pm/powerplay/si_dpm.c | 10 +++++-----
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 12 ++----------
> drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 14 +++++++-------
> 10 files changed, 35 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> index 769f58d5ae1a..e9c98e3f4cfb 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> @@ -2469,8 +2469,6 @@ static ssize_t amdgpu_hwmon_set_pwm1(struct device
> *dev,
> return err;
> }
>
> - value = (value * 100) / 255;
> -
> if (adev->powerplay.pp_funcs->set_fan_speed_percent)
> err = amdgpu_dpm_set_fan_speed_percent(adev, value);
> else
> @@ -2515,8 +2513,6 @@ static ssize_t amdgpu_hwmon_get_pwm1(struct device
> *dev,
> if (err)
> return err;
>
> - speed = (speed * 255) / 100;
> -
> return sprintf(buf, "%i\n", speed);
> }
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> index 0541bfc81c1b..aa353a628c50 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> @@ -3212,7 +3212,7 @@ static int smu7_force_dpm_level(struct pp_hwmgr
> *hwmgr,
>
> if (!ret) {
> if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK &&
> hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
> - smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
> + smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 255);
> else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK &&
> hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
> smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr);
> }
> @@ -4988,7 +4988,7 @@ static void smu7_set_fan_control_mode(struct
> pp_hwmgr *hwmgr, uint32_t mode)
> {
> switch (mode) {
> case AMD_FAN_CTRL_NONE:
> - smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
> + smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 255);
> break;
> case AMD_FAN_CTRL_MANUAL:
> if
> (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
> index 6cfe148ed45b..70ccc127e3fd 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
> @@ -70,12 +70,12 @@ int smu7_fan_ctrl_get_fan_speed_percent(struct
> pp_hwmgr *hwmgr,
> return -EINVAL;
>
>
> - tmp64 = (uint64_t)duty * 100;
> + tmp64 = (uint64_t)duty * 255;
> do_div(tmp64, duty100);
> *speed = (uint32_t)tmp64;
>
> - if (*speed > 100)
> - *speed = 100;
> + if (*speed > 255)
> + *speed = 255;
>
> return 0;
> }
> @@ -214,8 +214,8 @@ int smu7_fan_ctrl_set_fan_speed_percent(struct
> pp_hwmgr *hwmgr,
> if (hwmgr->thermal_controller.fanInfo.bNoFan)
> return 0;
>
> - if (speed > 100)
> - speed = 100;
> + if (speed > 255)
> + speed = 255;
>
> if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
> smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
> @@ -227,7 +227,7 @@ int smu7_fan_ctrl_set_fan_speed_percent(struct
> pp_hwmgr *hwmgr,
> return -EINVAL;
>
> tmp64 = (uint64_t)speed * duty100;
> - do_div(tmp64, 100);
> + do_div(tmp64, 255);
> duty = (uint32_t)tmp64;
>
> PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> index 25979106fd25..44c5e2588046 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> @@ -4199,7 +4199,7 @@ static void vega10_set_fan_control_mode(struct
> pp_hwmgr *hwmgr, uint32_t mode)
>
> switch (mode) {
> case AMD_FAN_CTRL_NONE:
> - vega10_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
> + vega10_fan_ctrl_set_fan_speed_percent(hwmgr, 255);
> break;
> case AMD_FAN_CTRL_MANUAL:
> if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
> index 9b46b27bd30c..6b4c4294afca 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
> @@ -78,11 +78,11 @@ int vega10_fan_ctrl_get_fan_speed_percent(struct
> pp_hwmgr *hwmgr,
>
> if (hwmgr->thermal_controller.
> advanceFanControlParameters.usMaxFanRPM != 0)
> - percent = current_rpm * 100 /
> + percent = current_rpm * 255 /
> hwmgr->thermal_controller.
> advanceFanControlParameters.usMaxFanRPM;
>
> - *speed = percent > 100 ? 100 : percent;
> + *speed = percent > 255 ? 255 : percent;
>
> return 0;
> }
> @@ -257,8 +257,8 @@ int vega10_fan_ctrl_set_fan_speed_percent(struct
> pp_hwmgr *hwmgr,
> if (hwmgr->thermal_controller.fanInfo.bNoFan)
> return 0;
>
> - if (speed > 100)
> - speed = 100;
> + if (speed > 255)
> + speed = 255;
>
> if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
> vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
> @@ -270,7 +270,7 @@ int vega10_fan_ctrl_set_fan_speed_percent(struct
> pp_hwmgr *hwmgr,
> return -EINVAL;
>
> tmp64 = (uint64_t)speed * duty100;
> - do_div(tmp64, 100);
> + do_div(tmp64, 255);
> duty = (uint32_t)tmp64;
>
> WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
> index 0791309586c5..cbe5f8027ee0 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
> @@ -2769,7 +2769,7 @@ static void vega20_set_fan_control_mode(struct
> pp_hwmgr *hwmgr, uint32_t mode)
> {
> switch (mode) {
> case AMD_FAN_CTRL_NONE:
> - vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
> + vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 255);
> break;
> case AMD_FAN_CTRL_MANUAL:
> if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
> b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
> index 43d754952bd9..eb007c00d7c6 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
> @@ -129,12 +129,12 @@ int vega20_fan_ctrl_get_fan_speed_percent(struct
> pp_hwmgr *hwmgr,
> if (!duty100)
> return -EINVAL;
>
> - tmp64 = (uint64_t)duty * 100;
> + tmp64 = (uint64_t)duty * 255;
> do_div(tmp64, duty100);
> *speed = (uint32_t)tmp64;
>
> - if (*speed > 100)
> - *speed = 100;
> + if (*speed > 255)
> + *speed = 255;
>
> return 0;
> }
> @@ -147,8 +147,8 @@ int vega20_fan_ctrl_set_fan_speed_percent(struct
> pp_hwmgr *hwmgr,
> uint32_t duty;
> uint64_t tmp64;
>
> - if (speed > 100)
> - speed = 100;
> + if (speed > 255)
> + speed = 255;
>
> if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
> vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
> @@ -160,7 +160,7 @@ int vega20_fan_ctrl_set_fan_speed_percent(struct
> pp_hwmgr *hwmgr,
> return -EINVAL;
>
> tmp64 = (uint64_t)speed * duty100;
> - do_div(tmp64, 100);
> + do_div(tmp64, 255);
> duty = (uint32_t)tmp64;
>
> WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c
> b/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c
> index 15c0b8af376f..96ca359c10a5 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c
> @@ -6555,12 +6555,12 @@ static int si_dpm_get_fan_speed_percent(void
> *handle,
> if (duty100 == 0)
> return -EINVAL;
>
> - tmp64 = (u64)duty * 100;
> + tmp64 = (u64)duty * 255;
> do_div(tmp64, duty100);
> *speed = (u32)tmp64;
>
> - if (*speed > 100)
> - *speed = 100;
> + if (*speed > 255)
> + *speed = 255;
>
> return 0;
> }
> @@ -6580,7 +6580,7 @@ static int si_dpm_set_fan_speed_percent(void *handle,
> if (si_pi->fan_is_controlled_by_smc)
> return -EINVAL;
>
> - if (speed > 100)
> + if (speed > 255)
> return -EINVAL;
>
> duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >>
> FMAX_DUTY100_SHIFT;
> @@ -6589,7 +6589,7 @@ static int si_dpm_set_fan_speed_percent(void *handle,
> return -EINVAL;
>
> tmp64 = (u64)speed * duty100;
> - do_div(tmp64, 100);
> + do_div(tmp64, 255);
> duty = (u32)tmp64;
>
> tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 54fb3d7d23ee..94c15526ad21 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -2565,23 +2565,17 @@ static int smu_get_fan_speed_percent(void *handle,
> u32 *speed)
> {
> struct smu_context *smu = handle;
> int ret = 0;
> - uint32_t percent;
>
> if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
> return -EOPNOTSUPP;
>
> mutex_lock(&smu->mutex);
>
> - if (smu->ppt_funcs->get_fan_speed_percent) {
> - ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent);
> - if (!ret) {
> - *speed = percent > 100 ? 100 : percent;
> - }
> - }
> + if (smu->ppt_funcs->get_fan_speed_percent)
> + ret = smu->ppt_funcs->get_fan_speed_percent(smu, speed);
>
> mutex_unlock(&smu->mutex);
>
> -
> return ret;
> }
>
> @@ -2596,8 +2590,6 @@ static int smu_set_fan_speed_percent(void *handle,
> u32 speed)
> mutex_lock(&smu->mutex);
>
> if (smu->ppt_funcs->set_fan_speed_percent) {
> - if (speed > 100)
> - speed = 100;
> ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
> if (!ret && !(smu->user_dpm_profile.flags &
> SMU_DPM_USER_PROFILE_RESTORE)) {
> smu->user_dpm_profile.custom_fan_speed |=
> SMU_CUSTOM_FAN_SPEED_PWM;
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> index 0cdf55a0dba2..f0ae0920c07e 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> @@ -1191,8 +1191,8 @@ smu_v11_0_set_fan_speed_percent(struct smu_context
> *smu, uint32_t speed)
> uint32_t duty100, duty;
> uint64_t tmp64;
>
> - if (speed > 100)
> - speed = 100;
> + if (speed > 255)
> + speed = 255;
>
> if (smu_v11_0_auto_fan_control(smu, 0))
> return -EINVAL;
> @@ -1203,7 +1203,7 @@ smu_v11_0_set_fan_speed_percent(struct smu_context
> *smu, uint32_t speed)
> return -EINVAL;
>
> tmp64 = (uint64_t)speed * duty100;
> - do_div(tmp64, 100);
> + do_div(tmp64, 255);
> duty = (uint32_t)tmp64;
>
> WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
> @@ -1274,12 +1274,12 @@ int smu_v11_0_get_fan_speed_percent(struct
> smu_context *smu,
> if (!duty100)
> return -EINVAL;
>
> - tmp64 = (uint64_t)duty * 100;
> + tmp64 = (uint64_t)duty * 255;
> do_div(tmp64, duty100);
> *speed = (uint32_t)tmp64;
>
> - if (*speed > 100)
> - *speed = 100;
> + if (*speed > 255)
> + *speed = 255;
>
> return 0;
> }
> @@ -1320,7 +1320,7 @@ smu_v11_0_set_fan_control_mode(struct smu_context
> *smu,
>
> switch (mode) {
> case AMD_FAN_CTRL_NONE:
> - ret = smu_v11_0_set_fan_speed_percent(smu, 100);
> + ret = smu_v11_0_set_fan_speed_percent(smu, 255);
> break;
> case AMD_FAN_CTRL_MANUAL:
> ret = smu_v11_0_auto_fan_control(smu, 0);
> --
> 2.29.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
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_______________________________________________
amd-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 5/7] drm/amd/pm: drop the unnecessary intermediate percent-based transition
2021-07-07 1:56 ` [PATCH 5/7] drm/amd/pm: drop the unnecessary intermediate percent-based transition Evan Quan
2021-07-07 5:00 ` Chen, Guchun
2021-07-07 6:26 ` Nils Wallménius
@ 2021-07-07 9:07 ` Lazar, Lijo
2 siblings, 0 replies; 20+ messages in thread
From: Lazar, Lijo @ 2021-07-07 9:07 UTC (permalink / raw)
To: Evan Quan, amd-gfx; +Cc: Alexander.Deucher
As mentioned in another patch, renaming function to set_/get_ pwm will
clarify things better. The scale is 0-255 in hwmon as well.
Thanks,
Lijo
On 7/7/2021 7:26 AM, Evan Quan wrote:
> Currently, the readout of fan speed pwm is transited into percent-based
> and then pwm-based. However, the transition into percent-based is totally
> unnecessary and make the final output less accurate.
>
> Change-Id: Ib99e088cda1875b4e2601f7077a178af6fe8a6cb
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
> drivers/gpu/drm/amd/pm/amdgpu_pm.c | 4 ----
> .../gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 4 ++--
> .../gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c | 12 ++++++------
> .../gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 2 +-
> .../drm/amd/pm/powerplay/hwmgr/vega10_thermal.c | 10 +++++-----
> .../gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 2 +-
> .../drm/amd/pm/powerplay/hwmgr/vega20_thermal.c | 12 ++++++------
> drivers/gpu/drm/amd/pm/powerplay/si_dpm.c | 10 +++++-----
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 12 ++----------
> drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 14 +++++++-------
> 10 files changed, 35 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> index 769f58d5ae1a..e9c98e3f4cfb 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> @@ -2469,8 +2469,6 @@ static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
> return err;
> }
>
> - value = (value * 100) / 255;
> -
> if (adev->powerplay.pp_funcs->set_fan_speed_percent)
> err = amdgpu_dpm_set_fan_speed_percent(adev, value);
> else
> @@ -2515,8 +2513,6 @@ static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
> if (err)
> return err;
>
> - speed = (speed * 255) / 100;
> -
> return sprintf(buf, "%i\n", speed);
> }
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> index 0541bfc81c1b..aa353a628c50 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> @@ -3212,7 +3212,7 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
>
> if (!ret) {
> if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
> - smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
> + smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 255);
> else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
> smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr);
> }
> @@ -4988,7 +4988,7 @@ static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
> {
> switch (mode) {
> case AMD_FAN_CTRL_NONE:
> - smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
> + smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 255);
> break;
> case AMD_FAN_CTRL_MANUAL:
> if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
> index 6cfe148ed45b..70ccc127e3fd 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_thermal.c
> @@ -70,12 +70,12 @@ int smu7_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
> return -EINVAL;
>
>
> - tmp64 = (uint64_t)duty * 100;
> + tmp64 = (uint64_t)duty * 255;
> do_div(tmp64, duty100);
> *speed = (uint32_t)tmp64;
>
> - if (*speed > 100)
> - *speed = 100;
> + if (*speed > 255)
> + *speed = 255;
>
> return 0;
> }
> @@ -214,8 +214,8 @@ int smu7_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
> if (hwmgr->thermal_controller.fanInfo.bNoFan)
> return 0;
>
> - if (speed > 100)
> - speed = 100;
> + if (speed > 255)
> + speed = 255;
>
> if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
> smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
> @@ -227,7 +227,7 @@ int smu7_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
> return -EINVAL;
>
> tmp64 = (uint64_t)speed * duty100;
> - do_div(tmp64, 100);
> + do_div(tmp64, 255);
> duty = (uint32_t)tmp64;
>
> PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> index 25979106fd25..44c5e2588046 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c
> @@ -4199,7 +4199,7 @@ static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
>
> switch (mode) {
> case AMD_FAN_CTRL_NONE:
> - vega10_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
> + vega10_fan_ctrl_set_fan_speed_percent(hwmgr, 255);
> break;
> case AMD_FAN_CTRL_MANUAL:
> if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
> index 9b46b27bd30c..6b4c4294afca 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
> @@ -78,11 +78,11 @@ int vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
>
> if (hwmgr->thermal_controller.
> advanceFanControlParameters.usMaxFanRPM != 0)
> - percent = current_rpm * 100 /
> + percent = current_rpm * 255 /
> hwmgr->thermal_controller.
> advanceFanControlParameters.usMaxFanRPM;
>
> - *speed = percent > 100 ? 100 : percent;
> + *speed = percent > 255 ? 255 : percent;
>
> return 0;
> }
> @@ -257,8 +257,8 @@ int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
> if (hwmgr->thermal_controller.fanInfo.bNoFan)
> return 0;
>
> - if (speed > 100)
> - speed = 100;
> + if (speed > 255)
> + speed = 255;
>
> if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
> vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
> @@ -270,7 +270,7 @@ int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
> return -EINVAL;
>
> tmp64 = (uint64_t)speed * duty100;
> - do_div(tmp64, 100);
> + do_div(tmp64, 255);
> duty = (uint32_t)tmp64;
>
> WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
> index 0791309586c5..cbe5f8027ee0 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
> @@ -2769,7 +2769,7 @@ static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
> {
> switch (mode) {
> case AMD_FAN_CTRL_NONE:
> - vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
> + vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 255);
> break;
> case AMD_FAN_CTRL_MANUAL:
> if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
> index 43d754952bd9..eb007c00d7c6 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_thermal.c
> @@ -129,12 +129,12 @@ int vega20_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
> if (!duty100)
> return -EINVAL;
>
> - tmp64 = (uint64_t)duty * 100;
> + tmp64 = (uint64_t)duty * 255;
> do_div(tmp64, duty100);
> *speed = (uint32_t)tmp64;
>
> - if (*speed > 100)
> - *speed = 100;
> + if (*speed > 255)
> + *speed = 255;
>
> return 0;
> }
> @@ -147,8 +147,8 @@ int vega20_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
> uint32_t duty;
> uint64_t tmp64;
>
> - if (speed > 100)
> - speed = 100;
> + if (speed > 255)
> + speed = 255;
>
> if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
> vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
> @@ -160,7 +160,7 @@ int vega20_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
> return -EINVAL;
>
> tmp64 = (uint64_t)speed * duty100;
> - do_div(tmp64, 100);
> + do_div(tmp64, 255);
> duty = (uint32_t)tmp64;
>
> WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c b/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c
> index 15c0b8af376f..96ca359c10a5 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/si_dpm.c
> @@ -6555,12 +6555,12 @@ static int si_dpm_get_fan_speed_percent(void *handle,
> if (duty100 == 0)
> return -EINVAL;
>
> - tmp64 = (u64)duty * 100;
> + tmp64 = (u64)duty * 255;
> do_div(tmp64, duty100);
> *speed = (u32)tmp64;
>
> - if (*speed > 100)
> - *speed = 100;
> + if (*speed > 255)
> + *speed = 255;
>
> return 0;
> }
> @@ -6580,7 +6580,7 @@ static int si_dpm_set_fan_speed_percent(void *handle,
> if (si_pi->fan_is_controlled_by_smc)
> return -EINVAL;
>
> - if (speed > 100)
> + if (speed > 255)
> return -EINVAL;
>
> duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
> @@ -6589,7 +6589,7 @@ static int si_dpm_set_fan_speed_percent(void *handle,
> return -EINVAL;
>
> tmp64 = (u64)speed * duty100;
> - do_div(tmp64, 100);
> + do_div(tmp64, 255);
> duty = (u32)tmp64;
>
> tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 54fb3d7d23ee..94c15526ad21 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -2565,23 +2565,17 @@ static int smu_get_fan_speed_percent(void *handle, u32 *speed)
> {
> struct smu_context *smu = handle;
> int ret = 0;
> - uint32_t percent;
>
> if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
> return -EOPNOTSUPP;
>
> mutex_lock(&smu->mutex);
>
> - if (smu->ppt_funcs->get_fan_speed_percent) {
> - ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent);
> - if (!ret) {
> - *speed = percent > 100 ? 100 : percent;
> - }
> - }
> + if (smu->ppt_funcs->get_fan_speed_percent)
> + ret = smu->ppt_funcs->get_fan_speed_percent(smu, speed);
>
> mutex_unlock(&smu->mutex);
>
> -
> return ret;
> }
>
> @@ -2596,8 +2590,6 @@ static int smu_set_fan_speed_percent(void *handle, u32 speed)
> mutex_lock(&smu->mutex);
>
> if (smu->ppt_funcs->set_fan_speed_percent) {
> - if (speed > 100)
> - speed = 100;
> ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
> if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
> smu->user_dpm_profile.custom_fan_speed |= SMU_CUSTOM_FAN_SPEED_PWM;
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> index 0cdf55a0dba2..f0ae0920c07e 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> @@ -1191,8 +1191,8 @@ smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
> uint32_t duty100, duty;
> uint64_t tmp64;
>
> - if (speed > 100)
> - speed = 100;
> + if (speed > 255)
> + speed = 255;
>
> if (smu_v11_0_auto_fan_control(smu, 0))
> return -EINVAL;
> @@ -1203,7 +1203,7 @@ smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
> return -EINVAL;
>
> tmp64 = (uint64_t)speed * duty100;
> - do_div(tmp64, 100);
> + do_div(tmp64, 255);
> duty = (uint32_t)tmp64;
>
> WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
> @@ -1274,12 +1274,12 @@ int smu_v11_0_get_fan_speed_percent(struct smu_context *smu,
> if (!duty100)
> return -EINVAL;
>
> - tmp64 = (uint64_t)duty * 100;
> + tmp64 = (uint64_t)duty * 255;
> do_div(tmp64, duty100);
> *speed = (uint32_t)tmp64;
>
> - if (*speed > 100)
> - *speed = 100;
> + if (*speed > 255)
> + *speed = 255;
>
> return 0;
> }
> @@ -1320,7 +1320,7 @@ smu_v11_0_set_fan_control_mode(struct smu_context *smu,
>
> switch (mode) {
> case AMD_FAN_CTRL_NONE:
> - ret = smu_v11_0_set_fan_speed_percent(smu, 100);
> + ret = smu_v11_0_set_fan_speed_percent(smu, 255);
> break;
> case AMD_FAN_CTRL_MANUAL:
> ret = smu_v11_0_auto_fan_control(smu, 0);
>
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 6/7] drm/amd/pm: drop unnecessary manual mode check
2021-07-07 1:56 [PATCH 1/7] drm/amd/pm: correct the fan speed RPM setting Evan Quan
` (3 preceding siblings ...)
2021-07-07 1:56 ` [PATCH 5/7] drm/amd/pm: drop the unnecessary intermediate percent-based transition Evan Quan
@ 2021-07-07 1:56 ` Evan Quan
2021-07-07 1:56 ` [PATCH 7/7] drm/amd/pm: correct the address of Arcturus fan related registers Evan Quan
` (2 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: Evan Quan @ 2021-07-07 1:56 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Evan Quan
As the fan control was guarded under manual mode before fan speed
RPM/PWM setting. Thus the extra check is totally redundant.
Change-Id: Ia9d776141ec4aa39255accbf00d7e7ed81c8424d
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index f0ae0920c07e..319bd7689df4 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -1194,9 +1194,6 @@ smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
if (speed > 255)
speed = 255;
- if (smu_v11_0_auto_fan_control(smu, 0))
- return -EINVAL;
-
duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
CG_FDO_CTRL1, FMAX_DUTY100);
if (!duty100)
@@ -1218,11 +1215,6 @@ int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
{
struct amdgpu_device *adev = smu->adev;
uint32_t tach_period, crystal_clock_freq;
- int ret;
-
- ret = smu_v11_0_auto_fan_control(smu, 0);
- if (ret)
- return ret;
/*
* crystal_clock_freq div by 4 is required since the fan control
@@ -1244,9 +1236,7 @@ int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
CG_TACH_CTRL, TARGET_PERIOD,
tach_period));
- ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
-
- return ret;
+ return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
}
int smu_v11_0_get_fan_speed_percent(struct smu_context *smu,
--
2.29.0
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH 7/7] drm/amd/pm: correct the address of Arcturus fan related registers
2021-07-07 1:56 [PATCH 1/7] drm/amd/pm: correct the fan speed RPM setting Evan Quan
` (4 preceding siblings ...)
2021-07-07 1:56 ` [PATCH 6/7] drm/amd/pm: drop unnecessary manual mode check Evan Quan
@ 2021-07-07 1:56 ` Evan Quan
2021-07-07 9:10 ` Lazar, Lijo
2021-07-07 4:47 ` [PATCH 1/7] drm/amd/pm: correct the fan speed RPM setting Chen, Guchun
2021-07-07 8:49 ` Lazar, Lijo
7 siblings, 1 reply; 20+ messages in thread
From: Evan Quan @ 2021-07-07 1:56 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Evan Quan
These registers have different address from other SMU V11 ASICs.
Change-Id: Iaeb0438331eed9b0313933da25622f8e4c048fab
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
.../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 104 +++++++++++++-----
1 file changed, 78 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 319bd7689df4..414c8674e32f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -79,6 +79,24 @@ MODULE_FIRMWARE("amdgpu/beige_goby_smc.bin");
#define mmTHM_BACO_CNTL_ARCT 0xA7
#define mmTHM_BACO_CNTL_ARCT_BASE_IDX 0
+#define mmCG_FDO_CTRL0_ARCT 0x8B
+#define mmCG_FDO_CTRL0_ARCT_BASE_IDX 0
+
+#define mmCG_FDO_CTRL1_ARCT 0x8C
+#define mmCG_FDO_CTRL1_ARCT_BASE_IDX 0
+
+#define mmCG_FDO_CTRL2_ARCT 0x8D
+#define mmCG_FDO_CTRL2_ARCT_BASE_IDX 0
+
+#define mmCG_TACH_CTRL_ARCT 0x8E
+#define mmCG_TACH_CTRL_ARCT_BASE_IDX 0
+
+#define mmCG_TACH_STATUS_ARCT 0x8F
+#define mmCG_TACH_STATUS_ARCT_BASE_IDX 0
+
+#define mmCG_THERMAL_STATUS_ARCT 0x90
+#define mmCG_THERMAL_STATUS_ARCT_BASE_IDX 0
+
int smu_v11_0_init_microcode(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
@@ -1174,12 +1192,21 @@ smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
{
struct amdgpu_device *adev = smu->adev;
- WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
- REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
- CG_FDO_CTRL2, TMIN, 0));
- WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
- REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
- CG_FDO_CTRL2, FDO_PWM_MODE, mode));
+ if (adev->asic_type == CHIP_ARCTURUS) {
+ WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT,
+ REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),
+ CG_FDO_CTRL2, TMIN, 0));
+ WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT,
+ REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),
+ CG_FDO_CTRL2, FDO_PWM_MODE, mode));
+ } else {
+ WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
+ REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
+ CG_FDO_CTRL2, TMIN, 0));
+ WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
+ REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
+ CG_FDO_CTRL2, FDO_PWM_MODE, mode));
+ }
return 0;
}
@@ -1194,8 +1221,12 @@ smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
if (speed > 255)
speed = 255;
- duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
- CG_FDO_CTRL1, FMAX_DUTY100);
+ if (adev->asic_type == CHIP_ARCTURUS)
+ duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),
+ CG_FDO_CTRL1, FMAX_DUTY100);
+ else
+ duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
+ CG_FDO_CTRL1, FMAX_DUTY100);
if (!duty100)
return -EINVAL;
@@ -1203,9 +1234,14 @@ smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
do_div(tmp64, 255);
duty = (uint32_t)tmp64;
- WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
- REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
- CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
+ if (adev->asic_type == CHIP_ARCTURUS)
+ WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT,
+ REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT),
+ CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
+ else
+ WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
+ REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
+ CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
}
@@ -1214,13 +1250,14 @@ int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
uint32_t speed)
{
struct amdgpu_device *adev = smu->adev;
- uint32_t tach_period, crystal_clock_freq;
-
/*
* crystal_clock_freq div by 4 is required since the fan control
* module refers to 25MHz
+ * crystal_clock_freq used for fan speed rpm calculation is
+ * always 25Mhz. So, hardcode it as 2500(in 10K unit).
*/
- crystal_clock_freq = amdgpu_asic_get_xclk(adev) / 4;
+ uint32_t crystal_clock_freq = 2500;
+ uint32_t tach_period;
/*
* To prevent from possible overheat, some ASICs may have requirement
@@ -1231,10 +1268,16 @@ int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
* lower than 500 RPM.
*/
tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
- WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
- REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
- CG_TACH_CTRL, TARGET_PERIOD,
- tach_period));
+ if (adev->asic_type == CHIP_ARCTURUS)
+ WREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT,
+ REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT),
+ CG_TACH_CTRL, TARGET_PERIOD,
+ tach_period));
+ else
+ WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
+ REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
+ CG_TACH_CTRL, TARGET_PERIOD,
+ tach_period));
return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
}
@@ -1257,10 +1300,17 @@ int smu_v11_0_get_fan_speed_percent(struct smu_context *smu,
return 0;
}
- duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
- CG_FDO_CTRL1, FMAX_DUTY100);
- duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
- CG_THERMAL_STATUS, FDO_PWM_DUTY);
+ if (adev->asic_type == CHIP_ARCTURUS) {
+ duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),
+ CG_FDO_CTRL1, FMAX_DUTY100);
+ duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS_ARCT),
+ CG_THERMAL_STATUS, FDO_PWM_DUTY);
+ } else {
+ duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
+ CG_FDO_CTRL1, FMAX_DUTY100);
+ duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
+ CG_THERMAL_STATUS, FDO_PWM_DUTY);
+ }
if (!duty100)
return -EINVAL;
@@ -1278,7 +1328,8 @@ int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
uint32_t *speed)
{
struct amdgpu_device *adev = smu->adev;
- uint32_t tach_status, crystal_clock_freq;
+ uint32_t crystal_clock_freq = 2500;
+ uint32_t tach_status;
uint64_t tmp64;
/*
@@ -1292,10 +1343,11 @@ int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
return 0;
}
- crystal_clock_freq = amdgpu_asic_get_xclk(adev) / 4;
tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
-
- tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS);
+ if (adev->asic_type == CHIP_ARCTURUS)
+ tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS_ARCT);
+ else
+ tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS);
do_div(tmp64, tach_status);
*speed = (uint32_t)tmp64;
--
2.29.0
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^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH 7/7] drm/amd/pm: correct the address of Arcturus fan related registers
2021-07-07 1:56 ` [PATCH 7/7] drm/amd/pm: correct the address of Arcturus fan related registers Evan Quan
@ 2021-07-07 9:10 ` Lazar, Lijo
0 siblings, 0 replies; 20+ messages in thread
From: Lazar, Lijo @ 2021-07-07 9:10 UTC (permalink / raw)
To: Evan Quan, amd-gfx; +Cc: Alexander.Deucher
Arcturus callbacks were dropped in another patch in this series. Instead
of dropping, better to keep the callbacks and use the specific reg offsets.
Thanks,
Lijo
On 7/7/2021 7:26 AM, Evan Quan wrote:
> These registers have different address from other SMU V11 ASICs.
>
> Change-Id: Iaeb0438331eed9b0313933da25622f8e4c048fab
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
> .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 104 +++++++++++++-----
> 1 file changed, 78 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> index 319bd7689df4..414c8674e32f 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> @@ -79,6 +79,24 @@ MODULE_FIRMWARE("amdgpu/beige_goby_smc.bin");
> #define mmTHM_BACO_CNTL_ARCT 0xA7
> #define mmTHM_BACO_CNTL_ARCT_BASE_IDX 0
>
> +#define mmCG_FDO_CTRL0_ARCT 0x8B
> +#define mmCG_FDO_CTRL0_ARCT_BASE_IDX 0
> +
> +#define mmCG_FDO_CTRL1_ARCT 0x8C
> +#define mmCG_FDO_CTRL1_ARCT_BASE_IDX 0
> +
> +#define mmCG_FDO_CTRL2_ARCT 0x8D
> +#define mmCG_FDO_CTRL2_ARCT_BASE_IDX 0
> +
> +#define mmCG_TACH_CTRL_ARCT 0x8E
> +#define mmCG_TACH_CTRL_ARCT_BASE_IDX 0
> +
> +#define mmCG_TACH_STATUS_ARCT 0x8F
> +#define mmCG_TACH_STATUS_ARCT_BASE_IDX 0
> +
> +#define mmCG_THERMAL_STATUS_ARCT 0x90
> +#define mmCG_THERMAL_STATUS_ARCT_BASE_IDX 0
> +
> int smu_v11_0_init_microcode(struct smu_context *smu)
> {
> struct amdgpu_device *adev = smu->adev;
> @@ -1174,12 +1192,21 @@ smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
> {
> struct amdgpu_device *adev = smu->adev;
>
> - WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
> - REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
> - CG_FDO_CTRL2, TMIN, 0));
> - WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
> - REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
> - CG_FDO_CTRL2, FDO_PWM_MODE, mode));
> + if (adev->asic_type == CHIP_ARCTURUS) {
> + WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT,
> + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),
> + CG_FDO_CTRL2, TMIN, 0));
> + WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT,
> + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),
> + CG_FDO_CTRL2, FDO_PWM_MODE, mode));
> + } else {
> + WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
> + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
> + CG_FDO_CTRL2, TMIN, 0));
> + WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
> + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
> + CG_FDO_CTRL2, FDO_PWM_MODE, mode));
> + }
>
> return 0;
> }
> @@ -1194,8 +1221,12 @@ smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
> if (speed > 255)
> speed = 255;
>
> - duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
> - CG_FDO_CTRL1, FMAX_DUTY100);
> + if (adev->asic_type == CHIP_ARCTURUS)
> + duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),
> + CG_FDO_CTRL1, FMAX_DUTY100);
> + else
> + duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
> + CG_FDO_CTRL1, FMAX_DUTY100);
> if (!duty100)
> return -EINVAL;
>
> @@ -1203,9 +1234,14 @@ smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
> do_div(tmp64, 255);
> duty = (uint32_t)tmp64;
>
> - WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
> - REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
> - CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
> + if (adev->asic_type == CHIP_ARCTURUS)
> + WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT,
> + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT),
> + CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
> + else
> + WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
> + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
> + CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
>
> return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
> }
> @@ -1214,13 +1250,14 @@ int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
> uint32_t speed)
> {
> struct amdgpu_device *adev = smu->adev;
> - uint32_t tach_period, crystal_clock_freq;
> -
> /*
> * crystal_clock_freq div by 4 is required since the fan control
> * module refers to 25MHz
> + * crystal_clock_freq used for fan speed rpm calculation is
> + * always 25Mhz. So, hardcode it as 2500(in 10K unit).
> */
> - crystal_clock_freq = amdgpu_asic_get_xclk(adev) / 4;
> + uint32_t crystal_clock_freq = 2500;
> + uint32_t tach_period;
>
> /*
> * To prevent from possible overheat, some ASICs may have requirement
> @@ -1231,10 +1268,16 @@ int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
> * lower than 500 RPM.
> */
> tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
> - WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
> - REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
> - CG_TACH_CTRL, TARGET_PERIOD,
> - tach_period));
> + if (adev->asic_type == CHIP_ARCTURUS)
> + WREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT,
> + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT),
> + CG_TACH_CTRL, TARGET_PERIOD,
> + tach_period));
> + else
> + WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
> + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
> + CG_TACH_CTRL, TARGET_PERIOD,
> + tach_period));
>
> return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
> }
> @@ -1257,10 +1300,17 @@ int smu_v11_0_get_fan_speed_percent(struct smu_context *smu,
> return 0;
> }
>
> - duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
> - CG_FDO_CTRL1, FMAX_DUTY100);
> - duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
> - CG_THERMAL_STATUS, FDO_PWM_DUTY);
> + if (adev->asic_type == CHIP_ARCTURUS) {
> + duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),
> + CG_FDO_CTRL1, FMAX_DUTY100);
> + duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS_ARCT),
> + CG_THERMAL_STATUS, FDO_PWM_DUTY);
> + } else {
> + duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
> + CG_FDO_CTRL1, FMAX_DUTY100);
> + duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
> + CG_THERMAL_STATUS, FDO_PWM_DUTY);
> + }
> if (!duty100)
> return -EINVAL;
>
> @@ -1278,7 +1328,8 @@ int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
> uint32_t *speed)
> {
> struct amdgpu_device *adev = smu->adev;
> - uint32_t tach_status, crystal_clock_freq;
> + uint32_t crystal_clock_freq = 2500;
> + uint32_t tach_status;
> uint64_t tmp64;
>
> /*
> @@ -1292,10 +1343,11 @@ int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
> return 0;
> }
>
> - crystal_clock_freq = amdgpu_asic_get_xclk(adev) / 4;
> tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
> -
> - tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS);
> + if (adev->asic_type == CHIP_ARCTURUS)
> + tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS_ARCT);
> + else
> + tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS);
> do_div(tmp64, tach_status);
> *speed = (uint32_t)tmp64;
>
>
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^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [PATCH 1/7] drm/amd/pm: correct the fan speed RPM setting
2021-07-07 1:56 [PATCH 1/7] drm/amd/pm: correct the fan speed RPM setting Evan Quan
` (5 preceding siblings ...)
2021-07-07 1:56 ` [PATCH 7/7] drm/amd/pm: correct the address of Arcturus fan related registers Evan Quan
@ 2021-07-07 4:47 ` Chen, Guchun
2021-08-11 7:58 ` Quan, Evan
2021-07-07 8:49 ` Lazar, Lijo
7 siblings, 1 reply; 20+ messages in thread
From: Chen, Guchun @ 2021-07-07 4:47 UTC (permalink / raw)
To: Quan, Evan, amd-gfx; +Cc: Deucher, Alexander, Quan, Evan
[Public]
tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
Any multiplication's overflow possibility?
Regards,
Guchun
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Evan Quan
Sent: Wednesday, July 7, 2021 9:57 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Quan, Evan <Evan.Quan@amd.com>
Subject: [PATCH 1/7] drm/amd/pm: correct the fan speed RPM setting
The relationship "PWM = RPM / smu->fan_max_rpm" between fan speed PWM and RPM is not true for SMU11 ASICs. So, we need a new way to perform the fan speed RPM setting.
Change-Id: I1afe8102f02ead9a8a07c7105f689ac60a85b0d8
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 5 +++
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 3 ++
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 9 ++---
.../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 1 +
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 1 +
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 1 +
.../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 36 +++++++++++++++++++
7 files changed, 52 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 3e89852e4820..6301e4cb3c2a 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -1039,6 +1039,11 @@ struct pptable_funcs {
*/
int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);
+ /**
+ * @set_fan_speed_rpm: Set a static fan speed in rpm.
+ */
+ int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
+
/**
* @set_xgmi_pstate: Set inter-chip global memory interconnect pstate.
* &pstate: Pstate to set. D0 if Nonzero, D3 otherwise.
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index b89e7dca8906..134a33e3de91 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -223,6 +223,9 @@ smu_v11_0_set_fan_control_mode(struct smu_context *smu, int smu_v11_0_set_fan_speed_percent(struct smu_context *smu,
uint32_t speed);
+int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
+ uint32_t speed);
+
int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
uint32_t pstate);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index ebe672142808..576e9ea68fd1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2174,11 +2174,12 @@ static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
mutex_lock(&smu->mutex);
- if (smu->ppt_funcs->set_fan_speed_percent) {
- percent = speed * 100 / smu->fan_max_rpm;
- ret = smu->ppt_funcs->set_fan_speed_percent(smu, percent);
- if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
+ if (smu->ppt_funcs->set_fan_speed_rpm) {
+ ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
+ if (!ret && smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE) {
+ percent = speed * 100 / smu->fan_max_rpm;
smu->user_dpm_profile.fan_speed_percent = percent;
+ }
}
mutex_unlock(&smu->mutex);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 6b3e0ea10163..047adf6dd444 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -2314,6 +2314,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.get_fan_control_mode = smu_v11_0_get_fan_control_mode,
.set_fan_control_mode = smu_v11_0_set_fan_control_mode,
.set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
+ .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
.set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
.gfx_off_control = smu_v11_0_gfx_off_control,
.register_irq_handler = smu_v11_0_register_irq_handler, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 59ea59acfb00..d8a011483dcf 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -3248,6 +3248,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.get_fan_control_mode = smu_v11_0_get_fan_control_mode,
.set_fan_control_mode = smu_v11_0_set_fan_control_mode,
.set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
+ .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
.set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
.gfx_off_control = smu_v11_0_gfx_off_control,
.register_irq_handler = smu_v11_0_register_irq_handler, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 83d8e53ca1f8..dad120294c19 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -3886,6 +3886,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.get_fan_control_mode = smu_v11_0_get_fan_control_mode,
.set_fan_control_mode = smu_v11_0_set_fan_control_mode,
.set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
+ .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
.set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
.gfx_off_control = smu_v11_0_gfx_off_control,
.register_irq_handler = smu_v11_0_register_irq_handler, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 388c5cb5c647..fefc8e93fdc6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -1213,6 +1213,42 @@ smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC); }
+int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
+ uint32_t speed)
+{
+ struct amdgpu_device *adev = smu->adev;
+ uint32_t tach_period, crystal_clock_freq;
+ int ret;
+
+ ret = smu_v11_0_auto_fan_control(smu, 0);
+ if (ret)
+ return ret;
+
+ /*
+ * crystal_clock_freq div by 4 is required since the fan control
+ * module refers to 25MHz
+ */
+ crystal_clock_freq = amdgpu_asic_get_xclk(adev) / 4;
+
+ /*
+ * To prevent from possible overheat, some ASICs may have requirement
+ * for minimum fan speed:
+ * - For some NV10 SKU, the fan speed cannot be set lower than
+ * 700 RPM.
+ * - For some Sienna Cichlid SKU, the fan speed cannot be set
+ * lower than 500 RPM.
+ */
+ tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
+ WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
+ REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
+ CG_TACH_CTRL, TARGET_PERIOD,
+ tach_period));
+
+ ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
+
+ return ret;
+}
+
int
smu_v11_0_set_fan_control_mode(struct smu_context *smu,
uint32_t mode)
--
2.29.0
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^ permalink raw reply related [flat|nested] 20+ messages in thread* RE: [PATCH 1/7] drm/amd/pm: correct the fan speed RPM setting
2021-07-07 4:47 ` [PATCH 1/7] drm/amd/pm: correct the fan speed RPM setting Chen, Guchun
@ 2021-08-11 7:58 ` Quan, Evan
0 siblings, 0 replies; 20+ messages in thread
From: Quan, Evan @ 2021-08-11 7:58 UTC (permalink / raw)
To: Chen, Guchun, amd-gfx; +Cc: Deucher, Alexander
[Public]
> -----Original Message-----
> From: Chen, Guchun <Guchun.Chen@amd.com>
> Sent: Wednesday, July 7, 2021 12:48 PM
> To: Quan, Evan <Evan.Quan@amd.com>; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Quan, Evan
> <Evan.Quan@amd.com>
> Subject: RE: [PATCH 1/7] drm/amd/pm: correct the fan speed RPM setting
>
> [Public]
>
> tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
>
> Any multiplication's overflow possibility?
[Quan, Evan] crystal_clock_freq is actually always 2500. So, it's pretty safe here.
BR
Evan
> Regards,
> Guchun
>
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Evan
> Quan
> Sent: Wednesday, July 7, 2021 9:57 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Quan, Evan
> <Evan.Quan@amd.com>
> Subject: [PATCH 1/7] drm/amd/pm: correct the fan speed RPM setting
>
> The relationship "PWM = RPM / smu->fan_max_rpm" between fan speed
> PWM and RPM is not true for SMU11 ASICs. So, we need a new way to
> perform the fan speed RPM setting.
>
> Change-Id: I1afe8102f02ead9a8a07c7105f689ac60a85b0d8
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
> drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 5 +++
> drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 3 ++
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 9 ++---
> .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 1 +
> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 1 +
> .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 1 +
> .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 36
> +++++++++++++++++++
> 7 files changed, 52 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> index 3e89852e4820..6301e4cb3c2a 100644
> --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> @@ -1039,6 +1039,11 @@ struct pptable_funcs {
> */
> int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t
> speed);
>
> + /**
> + * @set_fan_speed_rpm: Set a static fan speed in rpm.
> + */
> + int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t
> speed);
> +
> /**
> * @set_xgmi_pstate: Set inter-chip global memory interconnect
> pstate.
> * &pstate: Pstate to set. D0 if Nonzero, D3 otherwise.
> diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> index b89e7dca8906..134a33e3de91 100644
> --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> @@ -223,6 +223,9 @@ smu_v11_0_set_fan_control_mode(struct
> smu_context *smu, int smu_v11_0_set_fan_speed_percent(struct
> smu_context *smu,
> uint32_t speed);
>
> +int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
> + uint32_t speed);
> +
> int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
> uint32_t pstate);
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index ebe672142808..576e9ea68fd1 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -2174,11 +2174,12 @@ static int smu_set_fan_speed_rpm(void *handle,
> uint32_t speed)
>
> mutex_lock(&smu->mutex);
>
> - if (smu->ppt_funcs->set_fan_speed_percent) {
> - percent = speed * 100 / smu->fan_max_rpm;
> - ret = smu->ppt_funcs->set_fan_speed_percent(smu,
> percent);
> - if (!ret && !(smu->user_dpm_profile.flags &
> SMU_DPM_USER_PROFILE_RESTORE))
> + if (smu->ppt_funcs->set_fan_speed_rpm) {
> + ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
> + if (!ret && smu->user_dpm_profile.flags &
> SMU_DPM_USER_PROFILE_RESTORE) {
> + percent = speed * 100 / smu->fan_max_rpm;
> smu->user_dpm_profile.fan_speed_percent =
> percent;
> + }
> }
>
> mutex_unlock(&smu->mutex);
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> index 6b3e0ea10163..047adf6dd444 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> @@ -2314,6 +2314,7 @@ static const struct pptable_funcs
> arcturus_ppt_funcs = {
> .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
> .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
> .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
> + .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
> .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
> .gfx_off_control = smu_v11_0_gfx_off_control,
> .register_irq_handler = smu_v11_0_register_irq_handler, diff --git
> a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> index 59ea59acfb00..d8a011483dcf 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> @@ -3248,6 +3248,7 @@ static const struct pptable_funcs navi10_ppt_funcs
> = {
> .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
> .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
> .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
> + .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
> .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
> .gfx_off_control = smu_v11_0_gfx_off_control,
> .register_irq_handler = smu_v11_0_register_irq_handler, diff --git
> a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index 83d8e53ca1f8..dad120294c19 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -3886,6 +3886,7 @@ static const struct pptable_funcs
> sienna_cichlid_ppt_funcs = {
> .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
> .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
> .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
> + .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
> .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
> .gfx_off_control = smu_v11_0_gfx_off_control,
> .register_irq_handler = smu_v11_0_register_irq_handler, diff --git
> a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> index 388c5cb5c647..fefc8e93fdc6 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> @@ -1213,6 +1213,42 @@ smu_v11_0_set_fan_speed_percent(struct
> smu_context *smu, uint32_t speed)
> return smu_v11_0_set_fan_static_mode(smu,
> FDO_PWM_MODE_STATIC); }
>
> +int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
> + uint32_t speed)
> +{
> + struct amdgpu_device *adev = smu->adev;
> + uint32_t tach_period, crystal_clock_freq;
> + int ret;
> +
> + ret = smu_v11_0_auto_fan_control(smu, 0);
> + if (ret)
> + return ret;
> +
> + /*
> + * crystal_clock_freq div by 4 is required since the fan control
> + * module refers to 25MHz
> + */
> + crystal_clock_freq = amdgpu_asic_get_xclk(adev) / 4;
> +
> + /*
> + * To prevent from possible overheat, some ASICs may have
> requirement
> + * for minimum fan speed:
> + * - For some NV10 SKU, the fan speed cannot be set lower than
> + * 700 RPM.
> + * - For some Sienna Cichlid SKU, the fan speed cannot be set
> + * lower than 500 RPM.
> + */
> + tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
> + WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
> + REG_SET_FIELD(RREG32_SOC15(THM, 0,
> mmCG_TACH_CTRL),
> + CG_TACH_CTRL, TARGET_PERIOD,
> + tach_period));
> +
> + ret = smu_v11_0_set_fan_static_mode(smu,
> FDO_PWM_MODE_STATIC_RPM);
> +
> + return ret;
> +}
> +
> int
> smu_v11_0_set_fan_control_mode(struct smu_context *smu,
> uint32_t mode)
> --
> 2.29.0
>
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 1/7] drm/amd/pm: correct the fan speed RPM setting
2021-07-07 1:56 [PATCH 1/7] drm/amd/pm: correct the fan speed RPM setting Evan Quan
` (6 preceding siblings ...)
2021-07-07 4:47 ` [PATCH 1/7] drm/amd/pm: correct the fan speed RPM setting Chen, Guchun
@ 2021-07-07 8:49 ` Lazar, Lijo
2021-08-11 7:57 ` Quan, Evan
7 siblings, 1 reply; 20+ messages in thread
From: Lazar, Lijo @ 2021-07-07 8:49 UTC (permalink / raw)
To: Evan Quan, amd-gfx; +Cc: Alexander.Deucher
On 7/7/2021 7:26 AM, Evan Quan wrote:
> The relationship "PWM = RPM / smu->fan_max_rpm" between fan speed
> PWM and RPM is not true for SMU11 ASICs. So, we need a new way to
> perform the fan speed RPM setting.
>
> Change-Id: I1afe8102f02ead9a8a07c7105f689ac60a85b0d8
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
> drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 5 +++
> drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 3 ++
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 9 ++---
> .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 1 +
> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 1 +
> .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 1 +
> .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 36 +++++++++++++++++++
> 7 files changed, 52 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> index 3e89852e4820..6301e4cb3c2a 100644
> --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> @@ -1039,6 +1039,11 @@ struct pptable_funcs {
> */
> int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);
>
> + /**
> + * @set_fan_speed_rpm: Set a static fan speed in rpm.
> + */
> + int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
> +
> /**
> * @set_xgmi_pstate: Set inter-chip global memory interconnect pstate.
> * &pstate: Pstate to set. D0 if Nonzero, D3 otherwise.
> diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> index b89e7dca8906..134a33e3de91 100644
> --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> @@ -223,6 +223,9 @@ smu_v11_0_set_fan_control_mode(struct smu_context *smu,
> int smu_v11_0_set_fan_speed_percent(struct smu_context *smu,
> uint32_t speed);
>
> +int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
> + uint32_t speed);
> +
> int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
> uint32_t pstate);
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index ebe672142808..576e9ea68fd1 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -2174,11 +2174,12 @@ static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
>
> mutex_lock(&smu->mutex);
>
> - if (smu->ppt_funcs->set_fan_speed_percent) {
> - percent = speed * 100 / smu->fan_max_rpm;
> - ret = smu->ppt_funcs->set_fan_speed_percent(smu, percent);
> - if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
> + if (smu->ppt_funcs->set_fan_speed_rpm) {
> + ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
> + if (!ret && smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE) {
> + percent = speed * 100 / smu->fan_max_rpm;
> smu->user_dpm_profile.fan_speed_percent = percent;
> + }
> }
>
> mutex_unlock(&smu->mutex);
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> index 6b3e0ea10163..047adf6dd444 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> @@ -2314,6 +2314,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
> .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
> .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
> .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
> + .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
> .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
> .gfx_off_control = smu_v11_0_gfx_off_control,
> .register_irq_handler = smu_v11_0_register_irq_handler,
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> index 59ea59acfb00..d8a011483dcf 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> @@ -3248,6 +3248,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
> .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
> .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
> .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
> + .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
> .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
> .gfx_off_control = smu_v11_0_gfx_off_control,
> .register_irq_handler = smu_v11_0_register_irq_handler,
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index 83d8e53ca1f8..dad120294c19 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -3886,6 +3886,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
> .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
> .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
> .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
> + .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
> .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
> .gfx_off_control = smu_v11_0_gfx_off_control,
> .register_irq_handler = smu_v11_0_register_irq_handler,
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> index 388c5cb5c647..fefc8e93fdc6 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> @@ -1213,6 +1213,42 @@ smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
> return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
> }
>
> +int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
> + uint32_t speed)
> +{
> + struct amdgpu_device *adev = smu->adev;
> + uint32_t tach_period, crystal_clock_freq;
> + int ret;
> +
> + ret = smu_v11_0_auto_fan_control(smu, 0);
> + if (ret)
> + return ret;
> +
> + /*
> + * crystal_clock_freq div by 4 is required since the fan control
> + * module refers to 25MHz
> + */
> + crystal_clock_freq = amdgpu_asic_get_xclk(adev) / 4;
> +
Just hardcode this as 25MHz, no need to relate it to ASIC clk.
Thanks,
Lijo
> + /*
> + * To prevent from possible overheat, some ASICs may have requirement
> + * for minimum fan speed:
> + * - For some NV10 SKU, the fan speed cannot be set lower than
> + * 700 RPM.
> + * - For some Sienna Cichlid SKU, the fan speed cannot be set
> + * lower than 500 RPM.
> + */
> + tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
> + WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
> + REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
> + CG_TACH_CTRL, TARGET_PERIOD,
> + tach_period));
> +
> + ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
> +
> + return ret;
> +}
> +
> int
> smu_v11_0_set_fan_control_mode(struct smu_context *smu,
> uint32_t mode)
>
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^ permalink raw reply [flat|nested] 20+ messages in thread* RE: [PATCH 1/7] drm/amd/pm: correct the fan speed RPM setting
2021-07-07 8:49 ` Lazar, Lijo
@ 2021-08-11 7:57 ` Quan, Evan
0 siblings, 0 replies; 20+ messages in thread
From: Quan, Evan @ 2021-08-11 7:57 UTC (permalink / raw)
To: Lazar, Lijo, amd-gfx; +Cc: Deucher, Alexander
[AMD Official Use Only]
> -----Original Message-----
> From: Lazar, Lijo <Lijo.Lazar@amd.com>
> Sent: Wednesday, July 7, 2021 4:50 PM
> To: Quan, Evan <Evan.Quan@amd.com>; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
> Subject: Re: [PATCH 1/7] drm/amd/pm: correct the fan speed RPM setting
>
>
>
> On 7/7/2021 7:26 AM, Evan Quan wrote:
> > The relationship "PWM = RPM / smu->fan_max_rpm" between fan speed
> PWM
> > and RPM is not true for SMU11 ASICs. So, we need a new way to perform
> > the fan speed RPM setting.
> >
> > Change-Id: I1afe8102f02ead9a8a07c7105f689ac60a85b0d8
> > Signed-off-by: Evan Quan <evan.quan@amd.com>
> > ---
> > drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 5 +++
> > drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 3 ++
> > drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 9 ++---
> > .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 1 +
> > .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 1 +
> > .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 1 +
> > .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 36
> +++++++++++++++++++
> > 7 files changed, 52 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> > b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> > index 3e89852e4820..6301e4cb3c2a 100644
> > --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> > +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> > @@ -1039,6 +1039,11 @@ struct pptable_funcs {
> > */
> > int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t
> > speed);
> >
> > + /**
> > + * @set_fan_speed_rpm: Set a static fan speed in rpm.
> > + */
> > + int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t
> speed);
> > +
> > /**
> > * @set_xgmi_pstate: Set inter-chip global memory interconnect
> pstate.
> > * &pstate: Pstate to set. D0 if Nonzero, D3 otherwise.
> > diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> > b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> > index b89e7dca8906..134a33e3de91 100644
> > --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> > +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> > @@ -223,6 +223,9 @@ smu_v11_0_set_fan_control_mode(struct
> smu_context *smu,
> > int smu_v11_0_set_fan_speed_percent(struct smu_context *smu,
> > uint32_t speed);
> >
> > +int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
> > + uint32_t speed);
> > +
> > int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
> > uint32_t pstate);
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > index ebe672142808..576e9ea68fd1 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > @@ -2174,11 +2174,12 @@ static int smu_set_fan_speed_rpm(void
> *handle,
> > uint32_t speed)
> >
> > mutex_lock(&smu->mutex);
> >
> > - if (smu->ppt_funcs->set_fan_speed_percent) {
> > - percent = speed * 100 / smu->fan_max_rpm;
> > - ret = smu->ppt_funcs->set_fan_speed_percent(smu,
> percent);
> > - if (!ret && !(smu->user_dpm_profile.flags &
> SMU_DPM_USER_PROFILE_RESTORE))
> > + if (smu->ppt_funcs->set_fan_speed_rpm) {
> > + ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
> > + if (!ret && smu->user_dpm_profile.flags &
> SMU_DPM_USER_PROFILE_RESTORE) {
> > + percent = speed * 100 / smu->fan_max_rpm;
> > smu->user_dpm_profile.fan_speed_percent =
> percent;
> > + }
> > }
> >
> > mutex_unlock(&smu->mutex);
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > index 6b3e0ea10163..047adf6dd444 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> > @@ -2314,6 +2314,7 @@ static const struct pptable_funcs
> arcturus_ppt_funcs = {
> > .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
> > .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
> > .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
> > + .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
> > .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
> > .gfx_off_control = smu_v11_0_gfx_off_control,
> > .register_irq_handler = smu_v11_0_register_irq_handler, diff --git
> > a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> > index 59ea59acfb00..d8a011483dcf 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> > @@ -3248,6 +3248,7 @@ static const struct pptable_funcs
> navi10_ppt_funcs = {
> > .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
> > .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
> > .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
> > + .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
> > .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
> > .gfx_off_control = smu_v11_0_gfx_off_control,
> > .register_irq_handler = smu_v11_0_register_irq_handler, diff --git
> > a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > index 83d8e53ca1f8..dad120294c19 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > @@ -3886,6 +3886,7 @@ static const struct pptable_funcs
> sienna_cichlid_ppt_funcs = {
> > .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
> > .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
> > .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
> > + .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
> > .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
> > .gfx_off_control = smu_v11_0_gfx_off_control,
> > .register_irq_handler = smu_v11_0_register_irq_handler, diff --git
> > a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> > index 388c5cb5c647..fefc8e93fdc6 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> > @@ -1213,6 +1213,42 @@ smu_v11_0_set_fan_speed_percent(struct
> smu_context *smu, uint32_t speed)
> > return smu_v11_0_set_fan_static_mode(smu,
> FDO_PWM_MODE_STATIC);
> > }
> >
> > +int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
> > + uint32_t speed)
> > +{
> > + struct amdgpu_device *adev = smu->adev;
> > + uint32_t tach_period, crystal_clock_freq;
> > + int ret;
> > +
> > + ret = smu_v11_0_auto_fan_control(smu, 0);
> > + if (ret)
> > + return ret;
> > +
> > + /*
> > + * crystal_clock_freq div by 4 is required since the fan control
> > + * module refers to 25MHz
> > + */
> > + crystal_clock_freq = amdgpu_asic_get_xclk(adev) / 4;
> > +
>
> Just hardcode this as 25MHz, no need to relate it to ASIC clk.
>
[Quan, Evan] Sure, will update it in V2.
BR
Evan
> Thanks,
> Lijo
>
> > + /*
> > + * To prevent from possible overheat, some ASICs may have
> requirement
> > + * for minimum fan speed:
> > + * - For some NV10 SKU, the fan speed cannot be set lower than
> > + * 700 RPM.
> > + * - For some Sienna Cichlid SKU, the fan speed cannot be set
> > + * lower than 500 RPM.
> > + */
> > + tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
> > + WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
> > + REG_SET_FIELD(RREG32_SOC15(THM, 0,
> mmCG_TACH_CTRL),
> > + CG_TACH_CTRL, TARGET_PERIOD,
> > + tach_period));
> > +
> > + ret = smu_v11_0_set_fan_static_mode(smu,
> FDO_PWM_MODE_STATIC_RPM);
> > +
> > + return ret;
> > +}
> > +
> > int
> > smu_v11_0_set_fan_control_mode(struct smu_context *smu,
> > uint32_t mode)
> >
^ permalink raw reply [flat|nested] 20+ messages in thread