[RFC PATCH 00/42] target/mips: Reintroduce the R5900 CPU (with more testing)

[RFC PATCH 00/42] target/mips: Reintroduce the R5900 CPU (with more testing)

[Philippe Mathieu-Daudé]

The R5900 CPU was removed some time ago (frankly I don't remember
why). This series add it back, but to prove it works, we also add
testing at the end.

The main motivation is to have MIPS R5900 coverage, but to be able
to run real world r5900 binaries, I had to implement more opcodes.

42 patches are a lot, but 3 are already queued in linux-user-for-6.0,
and the 11 last ones are pure testing. I suppose in next versions
I'll split the testing patches, but to show the final objective I
included them in here.

I tagged it RFC because some parts because:

- We'd rather not add yet another target, but we need the
  ILP32-on-64bit ABI (o32 64-bit)

- RDHWR glibc kludge for user-mode

- Avocado patches are only here to show the final test.
  They are useful for my set of tests, but not meant to
  be merged in mainstream.

- gitlab jobs are only here to show the tests work.
  If the target is ever accepted, it would go in an already
  existing job.

I'm OK to maintain 64-bit o32 and the testing out of tree, but the
TCG opcodes are worthwhile review for mainstream.

Note: there is a sign-extension bug somewhere but I can't find it:

 $ qemu-r5900o32el busybox free
  =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0total =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0used =C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0free =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0sha=
red =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0buffers
  =C2=A0Mem: =C2=A0=C2=A0=C2=A0=C2=A0=C2=A03682012 =C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0812620 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A02869392 =C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A01367556 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0321136
  Swap: =C2=A0=C2=A0=C2=A0=C2=A0=C2=A02095100 =C2=A0=C2=A0=C2=A0=C2=A0-149854=
4 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A03593644
 Total: =C2=A0=C2=A0=C2=A0=C2=A0=C2=A05777112 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0-=
685924 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A06463036

 $ free # host
  =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0total =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0used =C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0free =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0shared =C2=A0buff/cac=
he =C2=A0=C2=A0available
 Mem: =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A016264924 =C2=A0=C2=A0=C2=A0=C2=A093=
23500 =C2=A0=C2=A0=C2=A0=C2=A02822500 =C2=A0=C2=A0=C2=A0=C2=A01377288 =C2=A0=
=C2=A0=C2=A0=C2=A04118924 =C2=A0=C2=A0=C2=A0=C2=A05149548
 Swap: =C2=A0=C2=A0=C2=A0=C2=A0=C2=A018872316 =C2=A0=C2=A0=C2=A011084368 =C2=
=A0=C2=A0=C2=A0=C2=A07787948

See the used swap:

  11084368 =3D 0x00a92250
  -1498544 =3D 0xffe92250

Fredrik Noring (2):
  linux-user/mips64: Support the n32 ABI for the R5900
  tests/tcg/mips: Test user mode DMULT for the R5900

Philippe Mathieu-Daud=C3=A9 (40):
  linux-user/mips64: Restore setup_frame() for o32 ABI
  linux-user/mips64: Support o32 ABI syscalls
  target/mips/translate: Make cpu_HI/LO registers public
  target/mips: Promote 128-bit multimedia registers as global ones
  target/mips: Rename 128-bit upper halve GPR registers
  target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers
  target/mips/translate: Use GPR move functions in gen_HILO1_tx79()
  target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree
  target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree
  target/mips/translate: Simplify PCPYH using deposit_i64()
  target/mips/tx79: Move PCPYH opcode to decodetree
  target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree
  target/mips: Remove 'C790 Multimedia Instructions' dead code
  target/mips/tx79: Salvage instructions description comment
  target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel
    logic)
  target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract)
  target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word)
  target/mips/tx79: Introduce PEXTU[BHW] opcodes (Parallel Extend Lower)
  target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal)
  target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than)
  target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word)
  target/mips/tx79: Introduce PINTEH (Parallel Interleave Even Halfword)
  target/mips/tx79: Introduce PEXE[HW] opcodes (Parallel Exchange Even)
  target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words)
  target/mips/tx79: Introduce LQ opcode (Load Quadword)
  target/mips/tx79: Introduce SQ opcode (Store Quadword)
  target/mips/translate: Make gen_rdhwr() public
  target/mips/tx79: Move RDHWR usermode kludge to trans_SQ()
  target/mips: Reintroduce the R5900 CPU
  default-configs: Support o32 ABI with R5900 64-bit MIPS CPU
  docker: Add gentoo-mipsr5900el-cross image
  gitlab-ci: Pass optional EXTRA_FILES when building docker images
  gitlab-ci: Build MIPS R5900 cross-toolchain (Gentoo based)
  tests/tcg: Add MIPS R5900 to arches filter
  gitlab-ci: Add job to test the MIPS r5900o32el target
  tests/acceptance: Extract QemuBaseTest from Test
  tests/acceptance: Make pick_default_qemu_bin() more generic
  tests/acceptance: Introduce QemuUserTest base class
  tests/acceptance: Test R5900 CPU with BusyBox from Sony PS2
  gitlab-ci: Add job to run integration tests for the r5900o32el target

 docs/user/main.rst                            |   3 +
 .../targets/r5900o32el-linux-user.mak         |   7 +
 linux-user/mips64/syscall_nr.h                |   5 +-
 linux-user/mips64/target_elf.h                |   3 +
 linux-user/mips64/target_signal.h             |   4 +
 target/mips/cpu.h                             |  10 +-
 target/mips/translate.h                       |  14 +
 target/mips/tx79.decode                       |  76 ++
 target/mips/translate.c                       | 862 +----------------
 target/mips/tx79_translate.c                  | 877 ++++++++++++++++++
 target/mips/txx9_translate.c                  |  20 +
 tests/tcg/mips/mipsn32r5900/dmult.c           |  40 +
 target/mips/cpu-defs.c.inc                    |  59 ++
 .gitlab-ci.d/containers.yml                   |   8 +
 .gitlab-ci.yml                                |  22 +
 MAINTAINERS                                   |   1 +
 target/mips/meson.build                       |   5 +
 tests/acceptance/avocado_qemu/__init__.py     |  56 +-
 tests/acceptance/mips_r5900_ps2.py            |  69 ++
 tests/docker/Makefile.include                 |   3 +
 .../gentoo-mipsr5900el-cross.docker           |  35 +
 .../crossdev.conf                             |   5 +
 tests/tcg/configure.sh                        |   8 +-
 tests/tcg/mips/mipsn32r5900/Makefile          |  25 +
 24 files changed, 1375 insertions(+), 842 deletions(-)
 create mode 100644 default-configs/targets/r5900o32el-linux-user.mak
 create mode 100644 target/mips/tx79.decode
 create mode 100644 target/mips/tx79_translate.c
 create mode 100644 target/mips/txx9_translate.c
 create mode 100644 tests/tcg/mips/mipsn32r5900/dmult.c
 create mode 100644 tests/acceptance/mips_r5900_ps2.py
 create mode 100644 tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker
 create mode 100644 tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker.=
d/crossdev.conf
 create mode 100644 tests/tcg/mips/mipsn32r5900/Makefile

--=20
2.26.2

[RFC PATCH 01/42] linux-user/mips64: Restore setup_frame() for o32 ABI

[Philippe Mathieu-Daudé]

64-bit MIPS targets lost setup_frame() during the refactor in commit
8949bef18b9. Restore it declaring TARGET_ARCH_HAS_SETUP_FRAME, to be
able to build the o32 ABI target.

Fixes: 8949bef18b9 ("linux-user: move mips/mips64 signal.c parts to mips directory")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 linux-user/mips64/target_signal.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/linux-user/mips64/target_signal.h b/linux-user/mips64/target_signal.h
index 799f7a668cd..f1f0ed7f706 100644
--- a/linux-user/mips64/target_signal.h
+++ b/linux-user/mips64/target_signal.h
@@ -67,4 +67,8 @@ typedef struct target_sigaltstack {
 #define TARGET_MINSIGSTKSZ    2048
 #define TARGET_SIGSTKSZ       8192
 
+#if defined(TARGET_ABI_MIPSO32)
+/* compare linux/arch/mips/kernel/signal.c:setup_frame() */
+#define TARGET_ARCH_HAS_SETUP_FRAME
+#endif
 #endif /* MIPS64_TARGET_SIGNAL_H */
-- 
2.26.2

[RFC PATCH 02/42] linux-user/mips64: Support o32 ABI syscalls

[Philippe Mathieu-Daudé]

o32 ABI syscalls start at offset 4000.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 linux-user/mips64/syscall_nr.h | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/linux-user/mips64/syscall_nr.h b/linux-user/mips64/syscall_nr.h
index 672f2fa51cb..6579421fa63 100644
--- a/linux-user/mips64/syscall_nr.h
+++ b/linux-user/mips64/syscall_nr.h
@@ -1,4 +1,7 @@
-#ifdef TARGET_ABI_MIPSN32
+#if defined(TARGET_ABI_MIPSO32)
+#define TARGET_SYSCALL_OFFSET 4000
+#include "syscall_o32_nr.h"
+#elif defined(TARGET_ABI_MIPSN32)
 #define TARGET_SYSCALL_OFFSET 6000
 #include "syscall_n32_nr.h"
 #else
-- 
2.26.2

[RFC PATCH 03/42] target/mips/translate: Make cpu_HI/LO registers public

[Philippe Mathieu-Daudé]

We will access the cpu_HI/LO registers outside of translate.c.
Make them publicly accessible.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.h | 1 +
 target/mips/translate.c | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/mips/translate.h b/target/mips/translate.h
index f47b5f2c8d0..2a1d8f570bb 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -145,6 +145,7 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
 bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
 
 extern TCGv cpu_gpr[32], cpu_PC;
+extern TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
 extern TCGv_i32 fpu_fcr0, fpu_fcr31;
 extern TCGv_i64 fpu_f64[32];
 extern TCGv bcond;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a5cf1742a8b..be40f79229f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2179,7 +2179,7 @@ enum {
 
 /* global register indices */
 TCGv cpu_gpr[32], cpu_PC;
-static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
+TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
 static TCGv cpu_dspctrl, btarget;
 TCGv bcond;
 static TCGv cpu_lladdr, cpu_llval;
-- 
2.26.2

Re: [RFC PATCH 03/42] target/mips/translate: Make cpu_HI/LO registers public

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> We will access the cpu_HI/LO registers outside of translate.c.
> Make them publicly accessible.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/translate.h | 1 +
>  target/mips/translate.c | 2 +-
>  2 files changed, 2 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[RFC PATCH 04/42] target/mips: Promote 128-bit multimedia registers as global ones

[Philippe Mathieu-Daudé]

The cpu::mmr[] array contains the upper halves of 128-bit GPR
registers. While they are only used by the R5900 CPU, the
concept is generic and could be used by another MIPS implementation.

Rename 'cpu::mmr' as 'cpu::gpr_hi' and make them global.

When the code is similar to the GPR lower halves, move it
close by.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/cpu.h       | 10 ++++++---
 target/mips/translate.h |  3 +++
 target/mips/translate.c | 48 ++++++++++++++++++++---------------------
 3 files changed, 34 insertions(+), 27 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index b9e227a30e9..7011d0dc707 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -460,6 +460,13 @@ typedef struct mips_def_t mips_def_t;
 typedef struct TCState TCState;
 struct TCState {
     target_ulong gpr[32];
+#if defined(TARGET_MIPS64)
+    /*
+     * For CPUs using 128-bit GPR registers, we put the lower halves in gpr[])
+     * and the upper halves in gpr_hi[].
+     */
+    uint64_t gpr_hi[32];
+#endif /* TARGET_MIPS64 */
     target_ulong PC;
     target_ulong HI[MIPS_DSP_ACC];
     target_ulong LO[MIPS_DSP_ACC];
@@ -505,9 +512,6 @@ struct TCState {
 
     float_status msa_fp_status;
 
-    /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */
-    uint64_t mmr[32];
-
 #define NUMBER_OF_MXU_REGISTERS 16
     target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
     target_ulong mxu_cr;
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 2a1d8f570bb..3014c20cadb 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -145,6 +145,9 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
 bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
 
 extern TCGv cpu_gpr[32], cpu_PC;
+#if defined(TARGET_MIPS64)
+extern TCGv_i64 cpu_gpr_hi[32];
+#endif
 extern TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
 extern TCGv_i32 fpu_fcr0, fpu_fcr31;
 extern TCGv_i64 fpu_f64[32];
diff --git a/target/mips/translate.c b/target/mips/translate.c
index be40f79229f..ab9b0999c93 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2179,6 +2179,11 @@ enum {
 
 /* global register indices */
 TCGv cpu_gpr[32], cpu_PC;
+/*
+ * For CPUs using 128-bit GPR registers, we put the lower halves in cpu_gpr[])
+ * and the upper halves in cpu_gpr_hi[].
+ */
+TCGv_i64 cpu_gpr_hi[32];
 TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
 static TCGv cpu_dspctrl, btarget;
 TCGv bcond;
@@ -2187,11 +2192,6 @@ static TCGv_i32 hflags;
 TCGv_i32 fpu_fcr0, fpu_fcr31;
 TCGv_i64 fpu_f64[32];
 
-#if defined(TARGET_MIPS64)
-/* Upper halves of R5900's 128-bit registers: MMRs (multimedia registers) */
-static TCGv_i64 cpu_mmr[32];
-#endif
-
 #if !defined(TARGET_MIPS64)
 /* MXU registers */
 static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
@@ -24784,7 +24784,7 @@ static void gen_mmi_pcpyh(DisasContext *ctx)
         /* nop */
     } else if (rt == 0) {
         tcg_gen_movi_i64(cpu_gpr[rd], 0);
-        tcg_gen_movi_i64(cpu_mmr[rd], 0);
+        tcg_gen_movi_i64(cpu_gpr_hi[rd], 0);
     } else {
         TCGv_i64 t0 = tcg_temp_new();
         TCGv_i64 t1 = tcg_temp_new();
@@ -24802,7 +24802,7 @@ static void gen_mmi_pcpyh(DisasContext *ctx)
 
         tcg_gen_mov_i64(cpu_gpr[rd], t1);
 
-        tcg_gen_andi_i64(t0, cpu_mmr[rt], mask);
+        tcg_gen_andi_i64(t0, cpu_gpr_hi[rt], mask);
         tcg_gen_movi_i64(t1, 0);
         tcg_gen_or_i64(t1, t0, t1);
         tcg_gen_shli_i64(t0, t0, 16);
@@ -24812,7 +24812,7 @@ static void gen_mmi_pcpyh(DisasContext *ctx)
         tcg_gen_shli_i64(t0, t0, 16);
         tcg_gen_or_i64(t1, t0, t1);
 
-        tcg_gen_mov_i64(cpu_mmr[rd], t1);
+        tcg_gen_mov_i64(cpu_gpr_hi[rd], t1);
 
         tcg_temp_free(t0);
         tcg_temp_free(t1);
@@ -24844,9 +24844,9 @@ static void gen_mmi_pcpyld(DisasContext *ctx)
         /* nop */
     } else {
         if (rs == 0) {
-            tcg_gen_movi_i64(cpu_mmr[rd], 0);
+            tcg_gen_movi_i64(cpu_gpr_hi[rd], 0);
         } else {
-            tcg_gen_mov_i64(cpu_mmr[rd], cpu_gpr[rs]);
+            tcg_gen_mov_i64(cpu_gpr_hi[rd], cpu_gpr[rs]);
         }
         if (rt == 0) {
             tcg_gen_movi_i64(cpu_gpr[rd], 0);
@@ -24885,13 +24885,13 @@ static void gen_mmi_pcpyud(DisasContext *ctx)
         if (rs == 0) {
             tcg_gen_movi_i64(cpu_gpr[rd], 0);
         } else {
-            tcg_gen_mov_i64(cpu_gpr[rd], cpu_mmr[rs]);
+            tcg_gen_mov_i64(cpu_gpr[rd], cpu_gpr_hi[rs]);
         }
         if (rt == 0) {
-            tcg_gen_movi_i64(cpu_mmr[rd], 0);
+            tcg_gen_movi_i64(cpu_gpr_hi[rd], 0);
         } else {
             if (rd != rt) {
-                tcg_gen_mov_i64(cpu_mmr[rd], cpu_mmr[rt]);
+                tcg_gen_mov_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rt]);
             }
         }
     }
@@ -29285,6 +29285,16 @@ void mips_tcg_init(void)
                                         offsetof(CPUMIPSState,
                                                  active_tc.gpr[i]),
                                         regnames[i]);
+#if defined(TARGET_MIPS64)
+    cpu_gpr_hi[0] = NULL;
+
+    for (unsigned i = 1; i < 32; i++) {
+        cpu_gpr_hi[i] = tcg_global_mem_new_i64(cpu_env,
+                                               offsetof(CPUMIPSState,
+                                                        active_tc.gpr_hi[i]),
+                                               regnames[i]);
+    }
+#endif /* !TARGET_MIPS64 */
     for (i = 0; i < 32; i++) {
         int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
 
@@ -29323,16 +29333,6 @@ void mips_tcg_init(void)
     cpu_llval = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval),
                                    "llval");
 
-#if defined(TARGET_MIPS64)
-    cpu_mmr[0] = NULL;
-    for (i = 1; i < 32; i++) {
-        cpu_mmr[i] = tcg_global_mem_new_i64(cpu_env,
-                                            offsetof(CPUMIPSState,
-                                                     active_tc.mmr[i]),
-                                            regnames[i]);
-    }
-#endif
-
 #if !defined(TARGET_MIPS64)
     for (i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) {
         mxu_gpr[i] = tcg_global_mem_new(cpu_env,
@@ -29344,7 +29344,7 @@ void mips_tcg_init(void)
     mxu_CR = tcg_global_mem_new(cpu_env,
                                 offsetof(CPUMIPSState, active_tc.mxu_cr),
                                 mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]);
-#endif
+#endif /* !TARGET_MIPS64 */
 }
 
 void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb,
-- 
2.26.2

Re: [RFC PATCH 04/42] target/mips: Promote 128-bit multimedia registers as global ones

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> +#if defined(TARGET_MIPS64)
> +extern TCGv_i64 cpu_gpr_hi[32];
> +#endif

Declaration needs to match...

> +/*
> + * For CPUs using 128-bit GPR registers, we put the lower halves in cpu_gpr[])
> + * and the upper halves in cpu_gpr_hi[].
> + */
> +TCGv_i64 cpu_gpr_hi[32];

definition wrt ifdef.

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[RFC PATCH 05/42] target/mips: Rename 128-bit upper halve GPR registers

[Philippe Mathieu-Daudé]

TCG displays the upper halve registers with the same name
as their lower halves. Rename the upper halves with the
'[hi]' suffix.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index ab9b0999c93..9c034c934d5 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29289,10 +29289,12 @@ void mips_tcg_init(void)
     cpu_gpr_hi[0] = NULL;
 
     for (unsigned i = 1; i < 32; i++) {
+        g_autofree char *rname = g_strdup_printf("%s[hi]", regnames[i]);
+
         cpu_gpr_hi[i] = tcg_global_mem_new_i64(cpu_env,
                                                offsetof(CPUMIPSState,
                                                         active_tc.gpr_hi[i]),
-                                               regnames[i]);
+                                               rname);
     }
 #endif /* !TARGET_MIPS64 */
     for (i = 0; i < 32; i++) {
-- 
2.26.2

Re: [RFC PATCH 05/42] target/mips: Rename 128-bit upper halve GPR registers

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> TCG displays the upper halve registers with the same name
> as their lower halves. Rename the upper halves with the
> '[hi]' suffix.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/translate.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[RFC PATCH 06/42] target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.h |  4 ++++
 target/mips/translate.c | 18 ++++++++++++++++++
 2 files changed, 22 insertions(+)

diff --git a/target/mips/translate.h b/target/mips/translate.h
index 3014c20cadb..468e29d7578 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -131,6 +131,10 @@ void gen_move_low32(TCGv ret, TCGv_i64 arg);
 void gen_move_high32(TCGv ret, TCGv_i64 arg);
 void gen_load_gpr(TCGv t, int reg);
 void gen_store_gpr(TCGv t, int reg);
+#if defined(TARGET_MIPS64)
+void gen_load_gpr_hi(TCGv_i64 t, int reg);
+void gen_store_gpr_hi(TCGv_i64 t, int reg);
+#endif /* TARGET_MIPS64 */
 void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg);
 void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
 void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9c034c934d5..16a731d3f37 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2291,6 +2291,24 @@ void gen_store_gpr(TCGv t, int reg)
     }
 }
 
+#if defined(TARGET_MIPS64)
+void gen_load_gpr_hi(TCGv_i64 t, int reg)
+{
+    if (reg == 0) {
+        tcg_gen_movi_i64(t, 0);
+    } else {
+        tcg_gen_mov_i64(t, cpu_gpr_hi[reg]);
+    }
+}
+
+void gen_store_gpr_hi(TCGv_i64 t, int reg)
+{
+    if (reg != 0) {
+        tcg_gen_mov_i64(cpu_gpr_hi[reg], t);
+    }
+}
+#endif /* TARGET_MIPS64 */
+
 /* Moves to/from shadow registers. */
 static inline void gen_load_srsgpr(int from, int to)
 {
-- 
2.26.2

Re: [RFC PATCH 06/42] target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/translate.h |  4 ++++
>  target/mips/translate.c | 18 ++++++++++++++++++
>  2 files changed, 22 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[RFC PATCH 07/42] target/mips/translate: Use GPR move functions in gen_HILO1_tx79()

[Philippe Mathieu-Daudé]

We have handy functions to access GPR. Use gen_store_gpr() for
Move From HI/LO Register and gen_load_gpr() for Move To opcodes.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.c | 21 ++++-----------------
 1 file changed, 4 insertions(+), 17 deletions(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 16a731d3f37..a2994eb0aa6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4126,31 +4126,18 @@ static void gen_shift(DisasContext *ctx, uint32_t opc,
 /* Copy GPR to and from TX79 HI1/LO1 register. */
 static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg)
 {
-    if (reg == 0 && (opc == MMI_OPC_MFHI1 || opc == MMI_OPC_MFLO1)) {
-        /* Treat as NOP. */
-        return;
-    }
-
     switch (opc) {
     case MMI_OPC_MFHI1:
-        tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[1]);
+        gen_store_gpr(cpu_HI[1], reg);
         break;
     case MMI_OPC_MFLO1:
-        tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[1]);
+        gen_store_gpr(cpu_LO[1], reg);
         break;
     case MMI_OPC_MTHI1:
-        if (reg != 0) {
-            tcg_gen_mov_tl(cpu_HI[1], cpu_gpr[reg]);
-        } else {
-            tcg_gen_movi_tl(cpu_HI[1], 0);
-        }
+        gen_load_gpr(cpu_HI[1], reg);
         break;
     case MMI_OPC_MTLO1:
-        if (reg != 0) {
-            tcg_gen_mov_tl(cpu_LO[1], cpu_gpr[reg]);
-        } else {
-            tcg_gen_movi_tl(cpu_LO[1], 0);
-        }
+        gen_load_gpr(cpu_LO[1], reg);
         break;
     default:
         MIPS_INVAL("mfthilo1 TX79");
-- 
2.26.2

Re: [RFC PATCH 07/42] target/mips/translate: Use GPR move functions in gen_HILO1_tx79()

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> We have handy functions to access GPR. Use gen_store_gpr() for
> Move From HI/LO Register and gen_load_gpr() for Move To opcodes.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/translate.c | 21 ++++-----------------
>  1 file changed, 4 insertions(+), 17 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[RFC PATCH 08/42] target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree

[Philippe Mathieu-Daudé]

Introduce decodetree structure to decode the tx79 opcodes.
Start it by moving the existing MFHI1 and MFLO1 opcodes.
Remove unnecessary comments.

As the TX79 share opcodes with the TX19/TX39/TX49 CPUs,
we introduce the decode_ext_txx9() dispatcher where we
will add the other decoders later.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.h      |  4 ++++
 target/mips/tx79.decode      | 25 ++++++++++++++++++++++++
 target/mips/translate.c      | 15 +++------------
 target/mips/tx79_translate.c | 37 ++++++++++++++++++++++++++++++++++++
 target/mips/txx9_translate.c | 20 +++++++++++++++++++
 target/mips/meson.build      |  5 +++++
 6 files changed, 94 insertions(+), 12 deletions(-)
 create mode 100644 target/mips/tx79.decode
 create mode 100644 target/mips/tx79_translate.c
 create mode 100644 target/mips/txx9_translate.c

diff --git a/target/mips/translate.h b/target/mips/translate.h
index 468e29d7578..bc91ac4f53f 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -181,5 +181,9 @@ void msa_translate_init(void);
 /* decodetree generated */
 bool decode_isa_rel6(DisasContext *ctx, uint32_t insn);
 bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
+bool decode_ext_txx9(DisasContext *ctx, uint32_t insn);
+#if defined(TARGET_MIPS64)
+bool decode_ext_tx79(DisasContext *ctx, uint32_t insn);
+#endif
 
 #endif
diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
new file mode 100644
index 00000000000..2e287ebbf36
--- /dev/null
+++ b/target/mips/tx79.decode
@@ -0,0 +1,25 @@
+# Toshiba C790's instruction set
+#
+# Copyright (C) 2021  Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Toshiba Appendix B  C790-Specific Instruction Set Details
+
+###########################################################################
+# Named attribute sets.  These are used to make nice(er) names
+# when creating helpers common to those for the individual
+# instruction patterns.
+
+&rtype           rs rt rd sa
+
+###########################################################################
+# Named instruction formats.  These are generally used to
+# reduce the amount of duplication between instruction patterns.
+
+@rd             ...... ..........  rd:5  ..... ......   &rtype rs=0 rt=0 sa=0
+
+###########################################################################
+
+MFHI1           011100 0000000000  ..... 00000 010000   @rd
+MFLO1           011100 0000000000  ..... 00000 010010   @rd
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a2994eb0aa6..de67e534121 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1973,9 +1973,7 @@ enum {
     MMI_OPC_PLZCW      = 0x04 | MMI_OPC_CLASS_MMI,
     MMI_OPC_CLASS_MMI0 = 0x08 | MMI_OPC_CLASS_MMI,
     MMI_OPC_CLASS_MMI2 = 0x09 | MMI_OPC_CLASS_MMI,
-    MMI_OPC_MFHI1      = 0x10 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MFHI */
     MMI_OPC_MTHI1      = 0x11 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MTHI */
-    MMI_OPC_MFLO1      = 0x12 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MFLO */
     MMI_OPC_MTLO1      = 0x13 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MTLO */
     MMI_OPC_MULT1      = 0x18 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MULT */
     MMI_OPC_MULTU1     = 0x19 | MMI_OPC_CLASS_MMI, /* Same min. as OPC_MULTU */
@@ -4127,12 +4125,6 @@ static void gen_shift(DisasContext *ctx, uint32_t opc,
 static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg)
 {
     switch (opc) {
-    case MMI_OPC_MFHI1:
-        gen_store_gpr(cpu_HI[1], reg);
-        break;
-    case MMI_OPC_MFLO1:
-        gen_store_gpr(cpu_LO[1], reg);
-        break;
     case MMI_OPC_MTHI1:
         gen_load_gpr(cpu_HI[1], reg);
         break;
@@ -28027,10 +28019,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
     case MMI_OPC_MTHI1:
         gen_HILO1_tx79(ctx, opc, rs);
         break;
-    case MMI_OPC_MFLO1:
-    case MMI_OPC_MFHI1:
-        gen_HILO1_tx79(ctx, opc, rd);
-        break;
     case MMI_OPC_PLZCW:         /* TODO: MMI_OPC_PLZCW */
     case MMI_OPC_PMFHL:         /* TODO: MMI_OPC_PMFHL */
     case MMI_OPC_PMTHL:         /* TODO: MMI_OPC_PMTHL */
@@ -28997,6 +28985,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
     if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx, ctx->opcode)) {
         return;
     }
+    if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opcode)) {
+        return;
+    }
 
     if (decode_opc_legacy(env, ctx)) {
         return;
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
new file mode 100644
index 00000000000..22bd6033e55
--- /dev/null
+++ b/target/mips/tx79_translate.c
@@ -0,0 +1,37 @@
+/*
+ * Toshiba TX79-specific instructions translation routines
+ *
+ *  Copyright (c) 2018 Fredrik Noring
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "tcg/tcg-op.h"
+#include "exec/helper-gen.h"
+#include "translate.h"
+
+/* Include the auto-generated decoder.  */
+#include "decode-tx79.c.inc"
+
+bool decode_ext_tx79(DisasContext *ctx, uint32_t insn)
+{
+    if (TARGET_LONG_BITS == 64 && decode_tx79(ctx, insn)) {
+        return true;
+    }
+    return false;
+}
+
+static bool trans_MFHI1(DisasContext *ctx, arg_rtype *a)
+{
+    gen_store_gpr(cpu_HI[1], a->rd);
+
+    return true;
+}
+
+static bool trans_MFLO1(DisasContext *ctx, arg_rtype *a)
+{
+    gen_store_gpr(cpu_LO[1], a->rd);
+
+    return true;
+}
diff --git a/target/mips/txx9_translate.c b/target/mips/txx9_translate.c
new file mode 100644
index 00000000000..8a2c0b766bd
--- /dev/null
+++ b/target/mips/txx9_translate.c
@@ -0,0 +1,20 @@
+/*
+ * Toshiba TXx9 instructions translation routines
+ *
+ *  Copyright (c) 2021 Philippe Mathieu-Daudé
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "translate.h"
+
+bool decode_ext_txx9(DisasContext *ctx, uint32_t insn)
+{
+#if defined(TARGET_MIPS64)
+    if (decode_ext_tx79(ctx, insn)) {
+        return true;
+    }
+#endif
+    return false;
+}
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 9741545440c..8836978e24a 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -3,6 +3,7 @@
   decodetree.process('mips64r6.decode', extra_args: '--static-decode=decode_mips64r6'),
   decodetree.process('msa32.decode', extra_args: '--static-decode=decode_msa32'),
   decodetree.process('msa64.decode', extra_args: '--static-decode=decode_msa64'),
+  decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
 ]
 
 mips_ss = ss.source_set()
@@ -22,6 +23,10 @@
   'tlb_helper.c',
   'translate.c',
   'translate_addr_const.c',
+  'txx9_translate.c',
+))
+mips_ss.add(when: ['CONFIG_TCG', 'TARGET_MIPS64'], if_true: files(
+  'tx79_translate.c',
 ))
 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
 
-- 
2.26.2

Re: [RFC PATCH 08/42] target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> Introduce decodetree structure to decode the tx79 opcodes.
> Start it by moving the existing MFHI1 and MFLO1 opcodes.
> Remove unnecessary comments.
> 
> As the TX79 share opcodes with the TX19/TX39/TX49 CPUs,
> we introduce the decode_ext_txx9() dispatcher where we
> will add the other decoders later.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/translate.h      |  4 ++++
>  target/mips/tx79.decode      | 25 ++++++++++++++++++++++++
>  target/mips/translate.c      | 15 +++------------
>  target/mips/tx79_translate.c | 37 ++++++++++++++++++++++++++++++++++++
>  target/mips/txx9_translate.c | 20 +++++++++++++++++++
>  target/mips/meson.build      |  5 +++++
>  6 files changed, 94 insertions(+), 12 deletions(-)
>  create mode 100644 target/mips/tx79.decode
>  create mode 100644 target/mips/tx79_translate.c
>  create mode 100644 target/mips/txx9_translate.c

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[RFC PATCH 09/42] target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tx79.decode      |  3 +++
 target/mips/translate.c      | 25 -------------------------
 target/mips/tx79_translate.c | 14 ++++++++++++++
 3 files changed, 17 insertions(+), 25 deletions(-)

diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index 2e287ebbf36..30737da54e4 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -17,9 +17,12 @@
 # Named instruction formats.  These are generally used to
 # reduce the amount of duplication between instruction patterns.
 
+@rs             ...... rs:5  ..... ..........  ......   &rtype rt=0 rd=0 sa=0
 @rd             ...... ..........  rd:5  ..... ......   &rtype rs=0 rt=0 sa=0
 
 ###########################################################################
 
 MFHI1           011100 0000000000  ..... 00000 010000   @rd
+MTHI1           011100 .....  0000000000 00000 010001   @rs
 MFLO1           011100 0000000000  ..... 00000 010010   @rd
+MTLO1           011100 .....  0000000000 00000 010011   @rs
diff --git a/target/mips/translate.c b/target/mips/translate.c
index de67e534121..7bd951d3a06 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1973,8 +1973,6 @@ enum {
     MMI_OPC_PLZCW      = 0x04 | MMI_OPC_CLASS_MMI,
     MMI_OPC_CLASS_MMI0 = 0x08 | MMI_OPC_CLASS_MMI,
     MMI_OPC_CLASS_MMI2 = 0x09 | MMI_OPC_CLASS_MMI,
-    MMI_OPC_MTHI1      = 0x11 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MTHI */
-    MMI_OPC_MTLO1      = 0x13 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MTLO */
     MMI_OPC_MULT1      = 0x18 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MULT */
     MMI_OPC_MULTU1     = 0x19 | MMI_OPC_CLASS_MMI, /* Same min. as OPC_MULTU */
     MMI_OPC_DIV1       = 0x1A | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIV  */
@@ -4120,25 +4118,6 @@ static void gen_shift(DisasContext *ctx, uint32_t opc,
     tcg_temp_free(t1);
 }
 
-#if defined(TARGET_MIPS64)
-/* Copy GPR to and from TX79 HI1/LO1 register. */
-static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg)
-{
-    switch (opc) {
-    case MMI_OPC_MTHI1:
-        gen_load_gpr(cpu_HI[1], reg);
-        break;
-    case MMI_OPC_MTLO1:
-        gen_load_gpr(cpu_LO[1], reg);
-        break;
-    default:
-        MIPS_INVAL("mfthilo1 TX79");
-        gen_reserved_instruction(ctx);
-        break;
-    }
-}
-#endif
-
 /* Arithmetic on HI/LO registers */
 static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
 {
@@ -28015,10 +27994,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
     case MMI_OPC_DIVU1:
         gen_div1_tx79(ctx, opc, rs, rt);
         break;
-    case MMI_OPC_MTLO1:
-    case MMI_OPC_MTHI1:
-        gen_HILO1_tx79(ctx, opc, rs);
-        break;
     case MMI_OPC_PLZCW:         /* TODO: MMI_OPC_PLZCW */
     case MMI_OPC_PMFHL:         /* TODO: MMI_OPC_PMFHL */
     case MMI_OPC_PMTHL:         /* TODO: MMI_OPC_PMTHL */
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index 22bd6033e55..905245cece7 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -35,3 +35,17 @@ static bool trans_MFLO1(DisasContext *ctx, arg_rtype *a)
 
     return true;
 }
+
+static bool trans_MTHI1(DisasContext *ctx, arg_rtype *a)
+{
+    gen_load_gpr(cpu_HI[1], a->rs);
+
+    return true;
+}
+
+static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
+{
+    gen_load_gpr(cpu_LO[1], a->rs);
+
+    return true;
+}
-- 
2.26.2

Re: [RFC PATCH 09/42] target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/tx79.decode      |  3 +++
>  target/mips/translate.c      | 25 -------------------------
>  target/mips/tx79_translate.c | 14 ++++++++++++++
>  3 files changed, 17 insertions(+), 25 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[RFC PATCH 10/42] target/mips/translate: Simplify PCPYH using deposit_i64()

[Philippe Mathieu-Daudé]

Simplify the PCPYH (Parallel Copy Halfword) instruction by using
multiple calls to deposit_i64() which can be optimized by some
TCG backends.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v3: Use missing rt, optimize (Richard)
---
 target/mips/translate.c | 34 ++++------------------------------
 1 file changed, 4 insertions(+), 30 deletions(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 7bd951d3a06..a13ad4959b4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24762,36 +24762,10 @@ static void gen_mmi_pcpyh(DisasContext *ctx)
         tcg_gen_movi_i64(cpu_gpr[rd], 0);
         tcg_gen_movi_i64(cpu_gpr_hi[rd], 0);
     } else {
-        TCGv_i64 t0 = tcg_temp_new();
-        TCGv_i64 t1 = tcg_temp_new();
-        uint64_t mask = (1ULL << 16) - 1;
-
-        tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
-        tcg_gen_movi_i64(t1, 0);
-        tcg_gen_or_i64(t1, t0, t1);
-        tcg_gen_shli_i64(t0, t0, 16);
-        tcg_gen_or_i64(t1, t0, t1);
-        tcg_gen_shli_i64(t0, t0, 16);
-        tcg_gen_or_i64(t1, t0, t1);
-        tcg_gen_shli_i64(t0, t0, 16);
-        tcg_gen_or_i64(t1, t0, t1);
-
-        tcg_gen_mov_i64(cpu_gpr[rd], t1);
-
-        tcg_gen_andi_i64(t0, cpu_gpr_hi[rt], mask);
-        tcg_gen_movi_i64(t1, 0);
-        tcg_gen_or_i64(t1, t0, t1);
-        tcg_gen_shli_i64(t0, t0, 16);
-        tcg_gen_or_i64(t1, t0, t1);
-        tcg_gen_shli_i64(t0, t0, 16);
-        tcg_gen_or_i64(t1, t0, t1);
-        tcg_gen_shli_i64(t0, t0, 16);
-        tcg_gen_or_i64(t1, t0, t1);
-
-        tcg_gen_mov_i64(cpu_gpr_hi[rd], t1);
-
-        tcg_temp_free(t0);
-        tcg_temp_free(t1);
+        tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rt], cpu_gpr[rt], 16, 16);
+        tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rd], cpu_gpr[rd], 32, 32);
+        tcg_gen_deposit_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rt], cpu_gpr_hi[rt], 16, 16);
+        tcg_gen_deposit_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rd], cpu_gpr_hi[rd], 32, 32);
     }
 }
 
-- 
2.26.2

Re: [RFC PATCH 10/42] target/mips/translate: Simplify PCPYH using deposit_i64()

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> Simplify the PCPYH (Parallel Copy Halfword) instruction by using
> multiple calls to deposit_i64() which can be optimized by some
> TCG backends.
> 
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> v3: Use missing rt, optimize (Richard)
> ---
>  target/mips/translate.c | 34 ++++------------------------------
>  1 file changed, 4 insertions(+), 30 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[RFC PATCH 11/42] target/mips/tx79: Move PCPYH opcode to decodetree

[Philippe Mathieu-Daudé]

Move the existing PCPYH opcode (Parallel Copy Halfword) to decodetree.
Remove unnecessary code / comments.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tx79.decode      |  5 +++++
 target/mips/translate.c      | 39 ------------------------------------
 target/mips/tx79_translate.c | 22 ++++++++++++++++++++
 3 files changed, 27 insertions(+), 39 deletions(-)

diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index 30737da54e4..7af35458b0a 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -17,6 +17,7 @@
 # Named instruction formats.  These are generally used to
 # reduce the amount of duplication between instruction patterns.
 
+@rt_rd          ...... ..... rt:5  rd:5  ..... ......   &rtype rs=0 sa=0
 @rs             ...... rs:5  ..... ..........  ......   &rtype rt=0 rd=0 sa=0
 @rd             ...... ..........  rd:5  ..... ......   &rtype rs=0 rt=0 sa=0
 
@@ -26,3 +27,7 @@ MFHI1           011100 0000000000  ..... 00000 010000   @rd
 MTHI1           011100 .....  0000000000 00000 010001   @rs
 MFLO1           011100 0000000000  ..... 00000 010010   @rd
 MTLO1           011100 .....  0000000000 00000 010011   @rs
+
+# MMI3
+
+PCPYH           011100 00000 ..... ..... 11011 101001   @rt_rd
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a13ad4959b4..b81a66ed373 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24733,42 +24733,6 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
  *                     PEXTUW
  */
 
-/*
- *  PCPYH rd, rt
- *
- *    Parallel Copy Halfword
- *
- *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- *  +-----------+---------+---------+---------+---------+-----------+
- *  |    MMI    |0 0 0 0 0|   rt    |   rd    |  PCPYH  |    MMI3   |
- *  +-----------+---------+---------+---------+---------+-----------+
- */
-static void gen_mmi_pcpyh(DisasContext *ctx)
-{
-    uint32_t pd, rt, rd;
-    uint32_t opcode;
-
-    opcode = ctx->opcode;
-
-    pd = extract32(opcode, 21, 5);
-    rt = extract32(opcode, 16, 5);
-    rd = extract32(opcode, 11, 5);
-
-    if (unlikely(pd != 0)) {
-        gen_reserved_instruction(ctx);
-    } else if (rd == 0) {
-        /* nop */
-    } else if (rt == 0) {
-        tcg_gen_movi_i64(cpu_gpr[rd], 0);
-        tcg_gen_movi_i64(cpu_gpr_hi[rd], 0);
-    } else {
-        tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rt], cpu_gpr[rt], 16, 16);
-        tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rd], cpu_gpr[rd], 32, 32);
-        tcg_gen_deposit_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rt], cpu_gpr_hi[rt], 16, 16);
-        tcg_gen_deposit_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rd], cpu_gpr_hi[rd], 32, 32);
-    }
-}
-
 /*
  *  PCPYLD rd, rs, rt
  *
@@ -27923,9 +27887,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
     case MMI_OPC_3_PEXCW:      /* TODO: MMI_OPC_3_PEXCW */
         gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI3 */
         break;
-    case MMI_OPC_3_PCPYH:
-        gen_mmi_pcpyh(ctx);
-        break;
     case MMI_OPC_3_PCPYUD:
         gen_mmi_pcpyud(ctx);
         break;
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index 905245cece7..d58b4fcd7b3 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -49,3 +49,25 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
 
     return true;
 }
+
+/* Parallel Copy Halfword */
+static bool trans_PCPYH(DisasContext *s, arg_rtype *a)
+{
+    if (a->rd == 0) {
+        /* nop */
+        return true;
+    }
+
+    if (a->rt == 0) {
+        tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
+        tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
+        return true;
+    }
+
+    tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], cpu_gpr[a->rt], 16, 16);
+    tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], cpu_gpr[a->rd], 32, 32);
+    tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt], cpu_gpr_hi[a->rt], 16, 16);
+    tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], 32, 32);
+
+    return true;
+}
-- 
2.26.2

Re: [RFC PATCH 11/42] target/mips/tx79: Move PCPYH opcode to decodetree

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> +    if (a->rt == 0) {
> +        tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
> +        tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
> +        return true;
> +    }

Is there a good reason not to use gen_load_gpr?

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [RFC PATCH 11/42] target/mips/tx79: Move PCPYH opcode to decodetree

[Philippe Mathieu-Daudé]

On 2/15/21 5:26 PM, Richard Henderson wrote:
> On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
>> +    if (a->rt == 0) {
>> +        tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
>> +        tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
>> +        return true;
>> +    }
> 
> Is there a good reason not to use gen_load_gpr?

I suppose you meant gen_store_gpr*().

We need to check $rt anyway to not do the deposit calls
if it is non-zero.

As it is mostly code movement, I prefer to keep it as it
for now, we might improve it later.

> 
> Otherwise,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Thanks!

Re: [RFC PATCH 11/42] target/mips/tx79: Move PCPYH opcode to decodetree

[Philippe Mathieu-Daudé]

On 3/8/21 11:48 AM, Philippe Mathieu-Daudé wrote:
> On 2/15/21 5:26 PM, Richard Henderson wrote:
>> On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
>>> +    if (a->rt == 0) {
>>> +        tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
>>> +        tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
>>> +        return true;
>>> +    }
>>
>> Is there a good reason not to use gen_load_gpr?
> 
> I suppose you meant gen_store_gpr*().

Double checking, we check for $rt, not $rd, right?

> 
> We need to check $rt anyway to not do the deposit calls
> if it is non-zero.
> 
> As it is mostly code movement, I prefer to keep it as it
> for now, we might improve it later.
> 
>>
>> Otherwise,
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> 
> Thanks!
> 

Re: [RFC PATCH 11/42] target/mips/tx79: Move PCPYH opcode to decodetree

[Richard Henderson]

On 3/8/21 3:57 AM, Philippe Mathieu-Daudé wrote:
> On 3/8/21 11:48 AM, Philippe Mathieu-Daudé wrote:
>> On 2/15/21 5:26 PM, Richard Henderson wrote:
>>> On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
>>>> +    if (a->rt == 0) {
>>>> +        tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
>>>> +        tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
>>>> +        return true;
>>>> +    }
>>>
>>> Is there a good reason not to use gen_load_gpr?
>>
>> I suppose you meant gen_store_gpr*().
> 
> Double checking, we check for $rt, not $rd, right?

I think I meant gen_load_gpr on rt.


r~

[RFC PATCH 12/42] target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree

[Philippe Mathieu-Daudé]

Move PCPYLD (Parallel Copy Lower Doubleword) and PCPYUD
(Parallel Copy Upper Doubleword) to decodetree. Remove
unnecessary code / comments.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tx79.decode      |  6 +++
 target/mips/translate.c      | 84 ------------------------------------
 target/mips/tx79_translate.c | 46 ++++++++++++++++++++
 3 files changed, 52 insertions(+), 84 deletions(-)

diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index 7af35458b0a..0f748b53a64 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -17,6 +17,7 @@
 # Named instruction formats.  These are generally used to
 # reduce the amount of duplication between instruction patterns.
 
+@rs_rt_rd       ...... rs:5  rt:5  rd:5  ..... ......   &rtype sa=0
 @rt_rd          ...... ..... rt:5  rd:5  ..... ......   &rtype rs=0 sa=0
 @rs             ...... rs:5  ..... ..........  ......   &rtype rt=0 rd=0 sa=0
 @rd             ...... ..........  rd:5  ..... ......   &rtype rs=0 rt=0 sa=0
@@ -28,6 +29,11 @@ MTHI1           011100 .....  0000000000 00000 010001   @rs
 MFLO1           011100 0000000000  ..... 00000 010010   @rd
 MTLO1           011100 .....  0000000000 00000 010011   @rs
 
+# MMI2
+
+PCPYLD          011100 ..... ..... ..... 01110 001001   @rs_rt_rd
+
 # MMI3
 
+PCPYUD          011100 ..... ..... ..... 01110 101001   @rs_rt_rd
 PCPYH           011100 00000 ..... ..... 11011 101001   @rt_rd
diff --git a/target/mips/translate.c b/target/mips/translate.c
index b81a66ed373..cf5a6a83ae5 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24733,84 +24733,6 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
  *                     PEXTUW
  */
 
-/*
- *  PCPYLD rd, rs, rt
- *
- *    Parallel Copy Lower Doubleword
- *
- *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- *  +-----------+---------+---------+---------+---------+-----------+
- *  |    MMI    |   rs    |   rt    |   rd    | PCPYLD  |    MMI2   |
- *  +-----------+---------+---------+---------+---------+-----------+
- */
-static void gen_mmi_pcpyld(DisasContext *ctx)
-{
-    uint32_t rs, rt, rd;
-    uint32_t opcode;
-
-    opcode = ctx->opcode;
-
-    rs = extract32(opcode, 21, 5);
-    rt = extract32(opcode, 16, 5);
-    rd = extract32(opcode, 11, 5);
-
-    if (rd == 0) {
-        /* nop */
-    } else {
-        if (rs == 0) {
-            tcg_gen_movi_i64(cpu_gpr_hi[rd], 0);
-        } else {
-            tcg_gen_mov_i64(cpu_gpr_hi[rd], cpu_gpr[rs]);
-        }
-        if (rt == 0) {
-            tcg_gen_movi_i64(cpu_gpr[rd], 0);
-        } else {
-            if (rd != rt) {
-                tcg_gen_mov_i64(cpu_gpr[rd], cpu_gpr[rt]);
-            }
-        }
-    }
-}
-
-/*
- *  PCPYUD rd, rs, rt
- *
- *    Parallel Copy Upper Doubleword
- *
- *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- *  +-----------+---------+---------+---------+---------+-----------+
- *  |    MMI    |   rs    |   rt    |   rd    | PCPYUD  |    MMI3   |
- *  +-----------+---------+---------+---------+---------+-----------+
- */
-static void gen_mmi_pcpyud(DisasContext *ctx)
-{
-    uint32_t rs, rt, rd;
-    uint32_t opcode;
-
-    opcode = ctx->opcode;
-
-    rs = extract32(opcode, 21, 5);
-    rt = extract32(opcode, 16, 5);
-    rd = extract32(opcode, 11, 5);
-
-    if (rd == 0) {
-        /* nop */
-    } else {
-        if (rs == 0) {
-            tcg_gen_movi_i64(cpu_gpr[rd], 0);
-        } else {
-            tcg_gen_mov_i64(cpu_gpr[rd], cpu_gpr_hi[rs]);
-        }
-        if (rt == 0) {
-            tcg_gen_movi_i64(cpu_gpr_hi[rd], 0);
-        } else {
-            if (rd != rt) {
-                tcg_gen_mov_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rt]);
-            }
-        }
-    }
-}
-
 #endif
 
 
@@ -27859,9 +27781,6 @@ static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx)
     case MMI_OPC_2_PROT3W:    /* TODO: MMI_OPC_2_PROT3W */
         gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI2 */
         break;
-    case MMI_OPC_2_PCPYLD:
-        gen_mmi_pcpyld(ctx);
-        break;
     default:
         MIPS_INVAL("TX79 MMI class MMI2");
         gen_reserved_instruction(ctx);
@@ -27887,9 +27806,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
     case MMI_OPC_3_PEXCW:      /* TODO: MMI_OPC_3_PEXCW */
         gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI3 */
         break;
-    case MMI_OPC_3_PCPYUD:
-        gen_mmi_pcpyud(ctx);
-        break;
     default:
         MIPS_INVAL("TX79 MMI class MMI3");
         gen_reserved_instruction(ctx);
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index d58b4fcd7b3..de09bb0d314 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -71,3 +71,49 @@ static bool trans_PCPYH(DisasContext *s, arg_rtype *a)
 
     return true;
 }
+
+/* Parallel Copy Lower Doubleword */
+static bool trans_PCPYLD(DisasContext *s, arg_rtype *a)
+{
+    if (a->rd == 0) {
+        /* nop */
+        return true;
+    }
+
+    if (a->rs == 0) {
+        tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
+    } else {
+        tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr[a->rs]);
+    }
+
+    if (a->rt == 0) {
+        tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
+    } else if (a->rd != a->rt) {
+        tcg_gen_mov_i64(cpu_gpr[a->rd], cpu_gpr[a->rt]);
+    }
+
+    return true;
+}
+
+/* Parallel Copy Upper Doubleword */
+static bool trans_PCPYUD(DisasContext *s, arg_rtype *a)
+{
+    if (a->rd == 0) {
+        /* nop */
+        return true;
+    }
+
+    if (a->rs == 0) {
+        tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
+    } else {
+        tcg_gen_mov_i64(cpu_gpr[a->rd], cpu_gpr_hi[a->rs]);
+    }
+
+    if (a->rt == 0) {
+        tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
+    } else if (a->rd != a->rt) {
+        tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt]);
+    }
+
+    return true;
+}
-- 
2.26.2

Re: [RFC PATCH 12/42] target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> +    if (a->rs == 0) {
> +        tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
> +    } else {
> +        tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr[a->rs]);
> +    }
> +
> +    if (a->rt == 0) {
> +        tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
> +    } else if (a->rd != a->rt) {
> +        tcg_gen_mov_i64(cpu_gpr[a->rd], cpu_gpr[a->rt]);
> +    }

Use gen_load_gpr.  Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [RFC PATCH 12/42] target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree

[Philippe Mathieu-Daudé]

On 2/15/21 5:28 PM, Richard Henderson wrote:
> On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
>> +    if (a->rs == 0) {
>> +        tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
>> +    } else {
>> +        tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr[a->rs]);
>> +    }
>> +
>> +    if (a->rt == 0) {
>> +        tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
>> +    } else if (a->rd != a->rt) {
>> +        tcg_gen_mov_i64(cpu_gpr[a->rd], cpu_gpr[a->rt]);
>> +    }
> 
> Use gen_load_gpr.

This is code movement, but I'll clean in a previous patch.

> Otherwise,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Thanks!

[RFC PATCH 13/42] target/mips: Remove 'C790 Multimedia Instructions' dead code

[Philippe Mathieu-Daudé]

We have almost 400 lines of code full of /* TODO */ comments
which end calling gen_reserved_instruction().

As we are not going to implement them, and all the caller's
switch() default cases already call gen_reserved_instruction(),
we can remove this altogether.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.c | 372 ----------------------------------------
 1 file changed, 372 deletions(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index cf5a6a83ae5..22d106405c6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1970,207 +1970,12 @@ enum {
 enum {
     MMI_OPC_MADD       = 0x00 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADD */
     MMI_OPC_MADDU      = 0x01 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADDU */
-    MMI_OPC_PLZCW      = 0x04 | MMI_OPC_CLASS_MMI,
-    MMI_OPC_CLASS_MMI0 = 0x08 | MMI_OPC_CLASS_MMI,
-    MMI_OPC_CLASS_MMI2 = 0x09 | MMI_OPC_CLASS_MMI,
     MMI_OPC_MULT1      = 0x18 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MULT */
     MMI_OPC_MULTU1     = 0x19 | MMI_OPC_CLASS_MMI, /* Same min. as OPC_MULTU */
     MMI_OPC_DIV1       = 0x1A | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIV  */
     MMI_OPC_DIVU1      = 0x1B | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIVU */
     MMI_OPC_MADD1      = 0x20 | MMI_OPC_CLASS_MMI,
     MMI_OPC_MADDU1     = 0x21 | MMI_OPC_CLASS_MMI,
-    MMI_OPC_CLASS_MMI1 = 0x28 | MMI_OPC_CLASS_MMI,
-    MMI_OPC_CLASS_MMI3 = 0x29 | MMI_OPC_CLASS_MMI,
-    MMI_OPC_PMFHL      = 0x30 | MMI_OPC_CLASS_MMI,
-    MMI_OPC_PMTHL      = 0x31 | MMI_OPC_CLASS_MMI,
-    MMI_OPC_PSLLH      = 0x34 | MMI_OPC_CLASS_MMI,
-    MMI_OPC_PSRLH      = 0x36 | MMI_OPC_CLASS_MMI,
-    MMI_OPC_PSRAH      = 0x37 | MMI_OPC_CLASS_MMI,
-    MMI_OPC_PSLLW      = 0x3C | MMI_OPC_CLASS_MMI,
-    MMI_OPC_PSRLW      = 0x3E | MMI_OPC_CLASS_MMI,
-    MMI_OPC_PSRAW      = 0x3F | MMI_OPC_CLASS_MMI,
-};
-
-/*
- * MMI instructions with opcode field = MMI and bits 5..0 = MMI0:
- *
- *  31    26                        10     6 5      0
- * +--------+----------------------+--------+--------+
- * |   MMI  |                      |function|  MMI0  |
- * +--------+----------------------+--------+--------+
- *
- * function  bits 7..6
- *     bits |   0   |   1   |   2   |   3
- *    10..8 |   00  |   01  |   10  |   11
- *   -------+-------+-------+-------+-------
- *    0 000 | PADDW | PSUBW | PCGTW | PMAXW
- *    1 001 | PADDH | PSUBH | PCGTH | PMAXH
- *    2 010 | PADDB | PSUBB | PCGTB |   *
- *    3 011 |   *   |   *   |   *   |   *
- *    4 100 | PADDSW| PSUBSW| PEXTLW| PPACW
- *    5 101 | PADDSH| PSUBSH| PEXTLH| PPACH
- *    6 110 | PADDSB| PSUBSB| PEXTLB| PPACB
- *    7 111 |   *   |   *   | PEXT5 | PPAC5
- */
-
-#define MASK_MMI0(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
-enum {
-    MMI_OPC_0_PADDW  = (0x00 << 6) | MMI_OPC_CLASS_MMI0,
-    MMI_OPC_0_PSUBW  = (0x01 << 6) | MMI_OPC_CLASS_MMI0,
-    MMI_OPC_0_PCGTW  = (0x02 << 6) | MMI_OPC_CLASS_MMI0,
-    MMI_OPC_0_PMAXW  = (0x03 << 6) | MMI_OPC_CLASS_MMI0,
-    MMI_OPC_0_PADDH  = (0x04 << 6) | MMI_OPC_CLASS_MMI0,
-    MMI_OPC_0_PSUBH  = (0x05 << 6) | MMI_OPC_CLASS_MMI0,
-    MMI_OPC_0_PCGTH  = (0x06 << 6) | MMI_OPC_CLASS_MMI0,
-    MMI_OPC_0_PMAXH  = (0x07 << 6) | MMI_OPC_CLASS_MMI0,
-    MMI_OPC_0_PADDB  = (0x08 << 6) | MMI_OPC_CLASS_MMI0,
-    MMI_OPC_0_PSUBB  = (0x09 << 6) | MMI_OPC_CLASS_MMI0,
-    MMI_OPC_0_PCGTB  = (0x0A << 6) | MMI_OPC_CLASS_MMI0,
-    MMI_OPC_0_PADDSW = (0x10 << 6) | MMI_OPC_CLASS_MMI0,
-    MMI_OPC_0_PSUBSW = (0x11 << 6) | MMI_OPC_CLASS_MMI0,
-    MMI_OPC_0_PEXTLW = (0x12 << 6) | MMI_OPC_CLASS_MMI0,
-    MMI_OPC_0_PPACW  = (0x13 << 6) | MMI_OPC_CLASS_MMI0,
-    MMI_OPC_0_PADDSH = (0x14 << 6) | MMI_OPC_CLASS_MMI0,
-    MMI_OPC_0_PSUBSH = (0x15 << 6) | MMI_OPC_CLASS_MMI0,
-    MMI_OPC_0_PEXTLH = (0x16 << 6) | MMI_OPC_CLASS_MMI0,
-    MMI_OPC_0_PPACH  = (0x17 << 6) | MMI_OPC_CLASS_MMI0,
-    MMI_OPC_0_PADDSB = (0x18 << 6) | MMI_OPC_CLASS_MMI0,
-    MMI_OPC_0_PSUBSB = (0x19 << 6) | MMI_OPC_CLASS_MMI0,
-    MMI_OPC_0_PEXTLB = (0x1A << 6) | MMI_OPC_CLASS_MMI0,
-    MMI_OPC_0_PPACB  = (0x1B << 6) | MMI_OPC_CLASS_MMI0,
-    MMI_OPC_0_PEXT5  = (0x1E << 6) | MMI_OPC_CLASS_MMI0,
-    MMI_OPC_0_PPAC5  = (0x1F << 6) | MMI_OPC_CLASS_MMI0,
-};
-
-/*
- * MMI instructions with opcode field = MMI and bits 5..0 = MMI1:
- *
- *  31    26                        10     6 5      0
- * +--------+----------------------+--------+--------+
- * |   MMI  |                      |function|  MMI1  |
- * +--------+----------------------+--------+--------+
- *
- * function  bits 7..6
- *     bits |   0   |   1   |   2   |   3
- *    10..8 |   00  |   01  |   10  |   11
- *   -------+-------+-------+-------+-------
- *    0 000 |   *   | PABSW | PCEQW | PMINW
- *    1 001 | PADSBH| PABSH | PCEQH | PMINH
- *    2 010 |   *   |   *   | PCEQB |   *
- *    3 011 |   *   |   *   |   *   |   *
- *    4 100 | PADDUW| PSUBUW| PEXTUW|   *
- *    5 101 | PADDUH| PSUBUH| PEXTUH|   *
- *    6 110 | PADDUB| PSUBUB| PEXTUB| QFSRV
- *    7 111 |   *   |   *   |   *   |   *
- */
-
-#define MASK_MMI1(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
-enum {
-    MMI_OPC_1_PABSW  = (0x01 << 6) | MMI_OPC_CLASS_MMI1,
-    MMI_OPC_1_PCEQW  = (0x02 << 6) | MMI_OPC_CLASS_MMI1,
-    MMI_OPC_1_PMINW  = (0x03 << 6) | MMI_OPC_CLASS_MMI1,
-    MMI_OPC_1_PADSBH = (0x04 << 6) | MMI_OPC_CLASS_MMI1,
-    MMI_OPC_1_PABSH  = (0x05 << 6) | MMI_OPC_CLASS_MMI1,
-    MMI_OPC_1_PCEQH  = (0x06 << 6) | MMI_OPC_CLASS_MMI1,
-    MMI_OPC_1_PMINH  = (0x07 << 6) | MMI_OPC_CLASS_MMI1,
-    MMI_OPC_1_PCEQB  = (0x0A << 6) | MMI_OPC_CLASS_MMI1,
-    MMI_OPC_1_PADDUW = (0x10 << 6) | MMI_OPC_CLASS_MMI1,
-    MMI_OPC_1_PSUBUW = (0x11 << 6) | MMI_OPC_CLASS_MMI1,
-    MMI_OPC_1_PEXTUW = (0x12 << 6) | MMI_OPC_CLASS_MMI1,
-    MMI_OPC_1_PADDUH = (0x14 << 6) | MMI_OPC_CLASS_MMI1,
-    MMI_OPC_1_PSUBUH = (0x15 << 6) | MMI_OPC_CLASS_MMI1,
-    MMI_OPC_1_PEXTUH = (0x16 << 6) | MMI_OPC_CLASS_MMI1,
-    MMI_OPC_1_PADDUB = (0x18 << 6) | MMI_OPC_CLASS_MMI1,
-    MMI_OPC_1_PSUBUB = (0x19 << 6) | MMI_OPC_CLASS_MMI1,
-    MMI_OPC_1_PEXTUB = (0x1A << 6) | MMI_OPC_CLASS_MMI1,
-    MMI_OPC_1_QFSRV  = (0x1B << 6) | MMI_OPC_CLASS_MMI1,
-};
-
-/*
- * MMI instructions with opcode field = MMI and bits 5..0 = MMI2:
- *
- *  31    26                        10     6 5      0
- * +--------+----------------------+--------+--------+
- * |   MMI  |                      |function|  MMI2  |
- * +--------+----------------------+--------+--------+
- *
- * function  bits 7..6
- *     bits |   0   |   1   |   2   |   3
- *    10..8 |   00  |   01  |   10  |   11
- *   -------+-------+-------+-------+-------
- *    0 000 | PMADDW|   *   | PSLLVW| PSRLVW
- *    1 001 | PMSUBW|   *   |   *   |   *
- *    2 010 | PMFHI | PMFLO | PINTH |   *
- *    3 011 | PMULTW| PDIVW | PCPYLD|   *
- *    4 100 | PMADDH| PHMADH|  PAND |  PXOR
- *    5 101 | PMSUBH| PHMSBH|   *   |   *
- *    6 110 |   *   |   *   | PEXEH | PREVH
- *    7 111 | PMULTH| PDIVBW| PEXEW | PROT3W
- */
-
-#define MASK_MMI2(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
-enum {
-    MMI_OPC_2_PMADDW = (0x00 << 6) | MMI_OPC_CLASS_MMI2,
-    MMI_OPC_2_PSLLVW = (0x02 << 6) | MMI_OPC_CLASS_MMI2,
-    MMI_OPC_2_PSRLVW = (0x03 << 6) | MMI_OPC_CLASS_MMI2,
-    MMI_OPC_2_PMSUBW = (0x04 << 6) | MMI_OPC_CLASS_MMI2,
-    MMI_OPC_2_PMFHI  = (0x08 << 6) | MMI_OPC_CLASS_MMI2,
-    MMI_OPC_2_PMFLO  = (0x09 << 6) | MMI_OPC_CLASS_MMI2,
-    MMI_OPC_2_PINTH  = (0x0A << 6) | MMI_OPC_CLASS_MMI2,
-    MMI_OPC_2_PMULTW = (0x0C << 6) | MMI_OPC_CLASS_MMI2,
-    MMI_OPC_2_PDIVW  = (0x0D << 6) | MMI_OPC_CLASS_MMI2,
-    MMI_OPC_2_PCPYLD = (0x0E << 6) | MMI_OPC_CLASS_MMI2,
-    MMI_OPC_2_PMADDH = (0x10 << 6) | MMI_OPC_CLASS_MMI2,
-    MMI_OPC_2_PHMADH = (0x11 << 6) | MMI_OPC_CLASS_MMI2,
-    MMI_OPC_2_PAND   = (0x12 << 6) | MMI_OPC_CLASS_MMI2,
-    MMI_OPC_2_PXOR   = (0x13 << 6) | MMI_OPC_CLASS_MMI2,
-    MMI_OPC_2_PMSUBH = (0x14 << 6) | MMI_OPC_CLASS_MMI2,
-    MMI_OPC_2_PHMSBH = (0x15 << 6) | MMI_OPC_CLASS_MMI2,
-    MMI_OPC_2_PEXEH  = (0x1A << 6) | MMI_OPC_CLASS_MMI2,
-    MMI_OPC_2_PREVH  = (0x1B << 6) | MMI_OPC_CLASS_MMI2,
-    MMI_OPC_2_PMULTH = (0x1C << 6) | MMI_OPC_CLASS_MMI2,
-    MMI_OPC_2_PDIVBW = (0x1D << 6) | MMI_OPC_CLASS_MMI2,
-    MMI_OPC_2_PEXEW  = (0x1E << 6) | MMI_OPC_CLASS_MMI2,
-    MMI_OPC_2_PROT3W = (0x1F << 6) | MMI_OPC_CLASS_MMI2,
-};
-
-/*
- * MMI instructions with opcode field = MMI and bits 5..0 = MMI3:
- *
- *  31    26                        10     6 5      0
- * +--------+----------------------+--------+--------+
- * |   MMI  |                      |function|  MMI3  |
- * +--------+----------------------+--------+--------+
- *
- * function  bits 7..6
- *     bits |   0   |   1   |   2   |   3
- *    10..8 |   00  |   01  |   10  |   11
- *   -------+-------+-------+-------+-------
- *    0 000 |PMADDUW|   *   |   *   | PSRAVW
- *    1 001 |   *   |   *   |   *   |   *
- *    2 010 | PMTHI | PMTLO | PINTEH|   *
- *    3 011 |PMULTUW| PDIVUW| PCPYUD|   *
- *    4 100 |   *   |   *   |  POR  |  PNOR
- *    5 101 |   *   |   *   |   *   |   *
- *    6 110 |   *   |   *   | PEXCH | PCPYH
- *    7 111 |   *   |   *   | PEXCW |   *
- */
-
-#define MASK_MMI3(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
-enum {
-    MMI_OPC_3_PMADDUW = (0x00 << 6) | MMI_OPC_CLASS_MMI3,
-    MMI_OPC_3_PSRAVW  = (0x03 << 6) | MMI_OPC_CLASS_MMI3,
-    MMI_OPC_3_PMTHI   = (0x08 << 6) | MMI_OPC_CLASS_MMI3,
-    MMI_OPC_3_PMTLO   = (0x09 << 6) | MMI_OPC_CLASS_MMI3,
-    MMI_OPC_3_PINTEH  = (0x0A << 6) | MMI_OPC_CLASS_MMI3,
-    MMI_OPC_3_PMULTUW = (0x0C << 6) | MMI_OPC_CLASS_MMI3,
-    MMI_OPC_3_PDIVUW  = (0x0D << 6) | MMI_OPC_CLASS_MMI3,
-    MMI_OPC_3_PCPYUD  = (0x0E << 6) | MMI_OPC_CLASS_MMI3,
-    MMI_OPC_3_POR     = (0x12 << 6) | MMI_OPC_CLASS_MMI3,
-    MMI_OPC_3_PNOR    = (0x13 << 6) | MMI_OPC_CLASS_MMI3,
-    MMI_OPC_3_PEXCH   = (0x1A << 6) | MMI_OPC_CLASS_MMI3,
-    MMI_OPC_3_PCPYH   = (0x1B << 6) | MMI_OPC_CLASS_MMI3,
-    MMI_OPC_3_PEXCW   = (0x1E << 6) | MMI_OPC_CLASS_MMI3,
 };
 
 /* global register indices */
@@ -24713,29 +24518,6 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
 }
 
 
-#if defined(TARGET_MIPS64)
-
-/*
- *
- *           MMI (MultiMedia Interface) ASE instructions
- *           ===========================================
- */
-
-/*
- *          MMI instructions category: data communication
- *          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- *
- *   PCPYH    PEXCH    PEXTLB   PINTH    PPACB    PEXT5    PREVH
- *   PCPYLD   PEXCW    PEXTLH   PINTEH   PPACH    PPAC5    PROT3W
- *   PCPYUD   PEXEH    PEXTLW            PPACW
- *            PEXEW    PEXTUB
- *                     PEXTUH
- *                     PEXTUW
- */
-
-#endif
-
-
 #if !defined(TARGET_MIPS64)
 
 /* MXU accumulate add/subtract 1-bit pattern 'aptn1' */
@@ -27682,137 +27464,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
 
 #if defined(TARGET_MIPS64)
 
-static void decode_mmi0(CPUMIPSState *env, DisasContext *ctx)
-{
-    uint32_t opc = MASK_MMI0(ctx->opcode);
-
-    switch (opc) {
-    case MMI_OPC_0_PADDW:     /* TODO: MMI_OPC_0_PADDW */
-    case MMI_OPC_0_PSUBW:     /* TODO: MMI_OPC_0_PSUBW */
-    case MMI_OPC_0_PCGTW:     /* TODO: MMI_OPC_0_PCGTW */
-    case MMI_OPC_0_PMAXW:     /* TODO: MMI_OPC_0_PMAXW */
-    case MMI_OPC_0_PADDH:     /* TODO: MMI_OPC_0_PADDH */
-    case MMI_OPC_0_PSUBH:     /* TODO: MMI_OPC_0_PSUBH */
-    case MMI_OPC_0_PCGTH:     /* TODO: MMI_OPC_0_PCGTH */
-    case MMI_OPC_0_PMAXH:     /* TODO: MMI_OPC_0_PMAXH */
-    case MMI_OPC_0_PADDB:     /* TODO: MMI_OPC_0_PADDB */
-    case MMI_OPC_0_PSUBB:     /* TODO: MMI_OPC_0_PSUBB */
-    case MMI_OPC_0_PCGTB:     /* TODO: MMI_OPC_0_PCGTB */
-    case MMI_OPC_0_PADDSW:    /* TODO: MMI_OPC_0_PADDSW */
-    case MMI_OPC_0_PSUBSW:    /* TODO: MMI_OPC_0_PSUBSW */
-    case MMI_OPC_0_PEXTLW:    /* TODO: MMI_OPC_0_PEXTLW */
-    case MMI_OPC_0_PPACW:     /* TODO: MMI_OPC_0_PPACW */
-    case MMI_OPC_0_PADDSH:    /* TODO: MMI_OPC_0_PADDSH */
-    case MMI_OPC_0_PSUBSH:    /* TODO: MMI_OPC_0_PSUBSH */
-    case MMI_OPC_0_PEXTLH:    /* TODO: MMI_OPC_0_PEXTLH */
-    case MMI_OPC_0_PPACH:     /* TODO: MMI_OPC_0_PPACH */
-    case MMI_OPC_0_PADDSB:    /* TODO: MMI_OPC_0_PADDSB */
-    case MMI_OPC_0_PSUBSB:    /* TODO: MMI_OPC_0_PSUBSB */
-    case MMI_OPC_0_PEXTLB:    /* TODO: MMI_OPC_0_PEXTLB */
-    case MMI_OPC_0_PPACB:     /* TODO: MMI_OPC_0_PPACB */
-    case MMI_OPC_0_PEXT5:     /* TODO: MMI_OPC_0_PEXT5 */
-    case MMI_OPC_0_PPAC5:     /* TODO: MMI_OPC_0_PPAC5 */
-        gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI0 */
-        break;
-    default:
-        MIPS_INVAL("TX79 MMI class MMI0");
-        gen_reserved_instruction(ctx);
-        break;
-    }
-}
-
-static void decode_mmi1(CPUMIPSState *env, DisasContext *ctx)
-{
-    uint32_t opc = MASK_MMI1(ctx->opcode);
-
-    switch (opc) {
-    case MMI_OPC_1_PABSW:     /* TODO: MMI_OPC_1_PABSW */
-    case MMI_OPC_1_PCEQW:     /* TODO: MMI_OPC_1_PCEQW */
-    case MMI_OPC_1_PMINW:     /* TODO: MMI_OPC_1_PMINW */
-    case MMI_OPC_1_PADSBH:    /* TODO: MMI_OPC_1_PADSBH */
-    case MMI_OPC_1_PABSH:     /* TODO: MMI_OPC_1_PABSH */
-    case MMI_OPC_1_PCEQH:     /* TODO: MMI_OPC_1_PCEQH */
-    case MMI_OPC_1_PMINH:     /* TODO: MMI_OPC_1_PMINH */
-    case MMI_OPC_1_PCEQB:     /* TODO: MMI_OPC_1_PCEQB */
-    case MMI_OPC_1_PADDUW:    /* TODO: MMI_OPC_1_PADDUW */
-    case MMI_OPC_1_PSUBUW:    /* TODO: MMI_OPC_1_PSUBUW */
-    case MMI_OPC_1_PEXTUW:    /* TODO: MMI_OPC_1_PEXTUW */
-    case MMI_OPC_1_PADDUH:    /* TODO: MMI_OPC_1_PADDUH */
-    case MMI_OPC_1_PSUBUH:    /* TODO: MMI_OPC_1_PSUBUH */
-    case MMI_OPC_1_PEXTUH:    /* TODO: MMI_OPC_1_PEXTUH */
-    case MMI_OPC_1_PADDUB:    /* TODO: MMI_OPC_1_PADDUB */
-    case MMI_OPC_1_PSUBUB:    /* TODO: MMI_OPC_1_PSUBUB */
-    case MMI_OPC_1_PEXTUB:    /* TODO: MMI_OPC_1_PEXTUB */
-    case MMI_OPC_1_QFSRV:     /* TODO: MMI_OPC_1_QFSRV */
-        gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI1 */
-        break;
-    default:
-        MIPS_INVAL("TX79 MMI class MMI1");
-        gen_reserved_instruction(ctx);
-        break;
-    }
-}
-
-static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx)
-{
-    uint32_t opc = MASK_MMI2(ctx->opcode);
-
-    switch (opc) {
-    case MMI_OPC_2_PMADDW:    /* TODO: MMI_OPC_2_PMADDW */
-    case MMI_OPC_2_PSLLVW:    /* TODO: MMI_OPC_2_PSLLVW */
-    case MMI_OPC_2_PSRLVW:    /* TODO: MMI_OPC_2_PSRLVW */
-    case MMI_OPC_2_PMSUBW:    /* TODO: MMI_OPC_2_PMSUBW */
-    case MMI_OPC_2_PMFHI:     /* TODO: MMI_OPC_2_PMFHI */
-    case MMI_OPC_2_PMFLO:     /* TODO: MMI_OPC_2_PMFLO */
-    case MMI_OPC_2_PINTH:     /* TODO: MMI_OPC_2_PINTH */
-    case MMI_OPC_2_PMULTW:    /* TODO: MMI_OPC_2_PMULTW */
-    case MMI_OPC_2_PDIVW:     /* TODO: MMI_OPC_2_PDIVW */
-    case MMI_OPC_2_PMADDH:    /* TODO: MMI_OPC_2_PMADDH */
-    case MMI_OPC_2_PHMADH:    /* TODO: MMI_OPC_2_PHMADH */
-    case MMI_OPC_2_PAND:      /* TODO: MMI_OPC_2_PAND */
-    case MMI_OPC_2_PXOR:      /* TODO: MMI_OPC_2_PXOR */
-    case MMI_OPC_2_PMSUBH:    /* TODO: MMI_OPC_2_PMSUBH */
-    case MMI_OPC_2_PHMSBH:    /* TODO: MMI_OPC_2_PHMSBH */
-    case MMI_OPC_2_PEXEH:     /* TODO: MMI_OPC_2_PEXEH */
-    case MMI_OPC_2_PREVH:     /* TODO: MMI_OPC_2_PREVH */
-    case MMI_OPC_2_PMULTH:    /* TODO: MMI_OPC_2_PMULTH */
-    case MMI_OPC_2_PDIVBW:    /* TODO: MMI_OPC_2_PDIVBW */
-    case MMI_OPC_2_PEXEW:     /* TODO: MMI_OPC_2_PEXEW */
-    case MMI_OPC_2_PROT3W:    /* TODO: MMI_OPC_2_PROT3W */
-        gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI2 */
-        break;
-    default:
-        MIPS_INVAL("TX79 MMI class MMI2");
-        gen_reserved_instruction(ctx);
-        break;
-    }
-}
-
-static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
-{
-    uint32_t opc = MASK_MMI3(ctx->opcode);
-
-    switch (opc) {
-    case MMI_OPC_3_PMADDUW:    /* TODO: MMI_OPC_3_PMADDUW */
-    case MMI_OPC_3_PSRAVW:     /* TODO: MMI_OPC_3_PSRAVW */
-    case MMI_OPC_3_PMTHI:      /* TODO: MMI_OPC_3_PMTHI */
-    case MMI_OPC_3_PMTLO:      /* TODO: MMI_OPC_3_PMTLO */
-    case MMI_OPC_3_PINTEH:     /* TODO: MMI_OPC_3_PINTEH */
-    case MMI_OPC_3_PMULTUW:    /* TODO: MMI_OPC_3_PMULTUW */
-    case MMI_OPC_3_PDIVUW:     /* TODO: MMI_OPC_3_PDIVUW */
-    case MMI_OPC_3_POR:        /* TODO: MMI_OPC_3_POR */
-    case MMI_OPC_3_PNOR:       /* TODO: MMI_OPC_3_PNOR */
-    case MMI_OPC_3_PEXCH:      /* TODO: MMI_OPC_3_PEXCH */
-    case MMI_OPC_3_PEXCW:      /* TODO: MMI_OPC_3_PEXCW */
-        gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI3 */
-        break;
-    default:
-        MIPS_INVAL("TX79 MMI class MMI3");
-        gen_reserved_instruction(ctx);
-        break;
-    }
-}
-
 static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
 {
     uint32_t opc = MASK_MMI(ctx->opcode);
@@ -27821,18 +27472,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
     int rd = extract32(ctx->opcode, 11, 5);
 
     switch (opc) {
-    case MMI_OPC_CLASS_MMI0:
-        decode_mmi0(env, ctx);
-        break;
-    case MMI_OPC_CLASS_MMI1:
-        decode_mmi1(env, ctx);
-        break;
-    case MMI_OPC_CLASS_MMI2:
-        decode_mmi2(env, ctx);
-        break;
-    case MMI_OPC_CLASS_MMI3:
-        decode_mmi3(env, ctx);
-        break;
     case MMI_OPC_MULT1:
     case MMI_OPC_MULTU1:
     case MMI_OPC_MADD:
@@ -27845,17 +27484,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
     case MMI_OPC_DIVU1:
         gen_div1_tx79(ctx, opc, rs, rt);
         break;
-    case MMI_OPC_PLZCW:         /* TODO: MMI_OPC_PLZCW */
-    case MMI_OPC_PMFHL:         /* TODO: MMI_OPC_PMFHL */
-    case MMI_OPC_PMTHL:         /* TODO: MMI_OPC_PMTHL */
-    case MMI_OPC_PSLLH:         /* TODO: MMI_OPC_PSLLH */
-    case MMI_OPC_PSRLH:         /* TODO: MMI_OPC_PSRLH */
-    case MMI_OPC_PSRAH:         /* TODO: MMI_OPC_PSRAH */
-    case MMI_OPC_PSLLW:         /* TODO: MMI_OPC_PSLLW */
-    case MMI_OPC_PSRLW:         /* TODO: MMI_OPC_PSRLW */
-    case MMI_OPC_PSRAW:         /* TODO: MMI_OPC_PSRAW */
-        gen_reserved_instruction(ctx);    /* TODO: MMI_OPC_CLASS_MMI */
-        break;
     default:
         MIPS_INVAL("TX79 MMI class");
         gen_reserved_instruction(ctx);
-- 
2.26.2

Re: [RFC PATCH 13/42] target/mips: Remove 'C790 Multimedia Instructions' dead code

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> We have almost 400 lines of code full of /* TODO */ comments
> which end calling gen_reserved_instruction().
> 
> As we are not going to implement them, and all the caller's
> switch() default cases already call gen_reserved_instruction(),
> we can remove this altogether.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/translate.c | 372 ----------------------------------------
>  1 file changed, 372 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[RFC PATCH 14/42] target/mips/tx79: Salvage instructions description comment

[Philippe Mathieu-Daudé]

This comment describing the tx79 opcodes is helpful. As we
will implement these instructions in tx79_translate.c, move
the comment there.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.c      | 160 -----------------------------
 target/mips/tx79_translate.c | 188 +++++++++++++++++++++++++++++++++++
 2 files changed, 188 insertions(+), 160 deletions(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 22d106405c6..109f7f80f3d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1743,166 +1743,6 @@ enum {
 };
 
 /*
- *     Overview of the TX79-specific instruction set
- *     =============================================
- *
- * The R5900 and the C790 have 128-bit wide GPRs, where the upper 64 bits
- * are only used by the specific quadword (128-bit) LQ/SQ load/store
- * instructions and certain multimedia instructions (MMIs). These MMIs
- * configure the 128-bit data path as two 64-bit, four 32-bit, eight 16-bit
- * or sixteen 8-bit paths.
- *
- * Reference:
- *
- * The Toshiba TX System RISC TX79 Core Architecture manual,
- * https://wiki.qemu.org/File:C790.pdf
- *
- *     Three-Operand Multiply and Multiply-Add (4 instructions)
- *     --------------------------------------------------------
- * MADD    [rd,] rs, rt      Multiply/Add
- * MADDU   [rd,] rs, rt      Multiply/Add Unsigned
- * MULT    [rd,] rs, rt      Multiply (3-operand)
- * MULTU   [rd,] rs, rt      Multiply Unsigned (3-operand)
- *
- *     Multiply Instructions for Pipeline 1 (10 instructions)
- *     ------------------------------------------------------
- * MULT1   [rd,] rs, rt      Multiply Pipeline 1
- * MULTU1  [rd,] rs, rt      Multiply Unsigned Pipeline 1
- * DIV1    rs, rt            Divide Pipeline 1
- * DIVU1   rs, rt            Divide Unsigned Pipeline 1
- * MADD1   [rd,] rs, rt      Multiply-Add Pipeline 1
- * MADDU1  [rd,] rs, rt      Multiply-Add Unsigned Pipeline 1
- * MFHI1   rd                Move From HI1 Register
- * MFLO1   rd                Move From LO1 Register
- * MTHI1   rs                Move To HI1 Register
- * MTLO1   rs                Move To LO1 Register
- *
- *     Arithmetic (19 instructions)
- *     ----------------------------
- * PADDB   rd, rs, rt        Parallel Add Byte
- * PSUBB   rd, rs, rt        Parallel Subtract Byte
- * PADDH   rd, rs, rt        Parallel Add Halfword
- * PSUBH   rd, rs, rt        Parallel Subtract Halfword
- * PADDW   rd, rs, rt        Parallel Add Word
- * PSUBW   rd, rs, rt        Parallel Subtract Word
- * PADSBH  rd, rs, rt        Parallel Add/Subtract Halfword
- * PADDSB  rd, rs, rt        Parallel Add with Signed Saturation Byte
- * PSUBSB  rd, rs, rt        Parallel Subtract with Signed Saturation Byte
- * PADDSH  rd, rs, rt        Parallel Add with Signed Saturation Halfword
- * PSUBSH  rd, rs, rt        Parallel Subtract with Signed Saturation Halfword
- * PADDSW  rd, rs, rt        Parallel Add with Signed Saturation Word
- * PSUBSW  rd, rs, rt        Parallel Subtract with Signed Saturation Word
- * PADDUB  rd, rs, rt        Parallel Add with Unsigned saturation Byte
- * PSUBUB  rd, rs, rt        Parallel Subtract with Unsigned saturation Byte
- * PADDUH  rd, rs, rt        Parallel Add with Unsigned saturation Halfword
- * PSUBUH  rd, rs, rt        Parallel Subtract with Unsigned saturation Halfword
- * PADDUW  rd, rs, rt        Parallel Add with Unsigned saturation Word
- * PSUBUW  rd, rs, rt        Parallel Subtract with Unsigned saturation Word
- *
- *     Min/Max (4 instructions)
- *     ------------------------
- * PMAXH   rd, rs, rt        Parallel Maximum Halfword
- * PMINH   rd, rs, rt        Parallel Minimum Halfword
- * PMAXW   rd, rs, rt        Parallel Maximum Word
- * PMINW   rd, rs, rt        Parallel Minimum Word
- *
- *     Absolute (2 instructions)
- *     -------------------------
- * PABSH   rd, rt            Parallel Absolute Halfword
- * PABSW   rd, rt            Parallel Absolute Word
- *
- *     Logical (4 instructions)
- *     ------------------------
- * PAND    rd, rs, rt        Parallel AND
- * POR     rd, rs, rt        Parallel OR
- * PXOR    rd, rs, rt        Parallel XOR
- * PNOR    rd, rs, rt        Parallel NOR
- *
- *     Shift (9 instructions)
- *     ----------------------
- * PSLLH   rd, rt, sa        Parallel Shift Left Logical Halfword
- * PSRLH   rd, rt, sa        Parallel Shift Right Logical Halfword
- * PSRAH   rd, rt, sa        Parallel Shift Right Arithmetic Halfword
- * PSLLW   rd, rt, sa        Parallel Shift Left Logical Word
- * PSRLW   rd, rt, sa        Parallel Shift Right Logical Word
- * PSRAW   rd, rt, sa        Parallel Shift Right Arithmetic Word
- * PSLLVW  rd, rt, rs        Parallel Shift Left Logical Variable Word
- * PSRLVW  rd, rt, rs        Parallel Shift Right Logical Variable Word
- * PSRAVW  rd, rt, rs        Parallel Shift Right Arithmetic Variable Word
- *
- *     Compare (6 instructions)
- *     ------------------------
- * PCGTB   rd, rs, rt        Parallel Compare for Greater Than Byte
- * PCEQB   rd, rs, rt        Parallel Compare for Equal Byte
- * PCGTH   rd, rs, rt        Parallel Compare for Greater Than Halfword
- * PCEQH   rd, rs, rt        Parallel Compare for Equal Halfword
- * PCGTW   rd, rs, rt        Parallel Compare for Greater Than Word
- * PCEQW   rd, rs, rt        Parallel Compare for Equal Word
- *
- *     LZC (1 instruction)
- *     -------------------
- * PLZCW   rd, rs            Parallel Leading Zero or One Count Word
- *
- *     Quadword Load and Store (2 instructions)
- *     ----------------------------------------
- * LQ      rt, offset(base)  Load Quadword
- * SQ      rt, offset(base)  Store Quadword
- *
- *     Multiply and Divide (19 instructions)
- *     -------------------------------------
- * PMULTW  rd, rs, rt        Parallel Multiply Word
- * PMULTUW rd, rs, rt        Parallel Multiply Unsigned Word
- * PDIVW   rs, rt            Parallel Divide Word
- * PDIVUW  rs, rt            Parallel Divide Unsigned Word
- * PMADDW  rd, rs, rt        Parallel Multiply-Add Word
- * PMADDUW rd, rs, rt        Parallel Multiply-Add Unsigned Word
- * PMSUBW  rd, rs, rt        Parallel Multiply-Subtract Word
- * PMULTH  rd, rs, rt        Parallel Multiply Halfword
- * PMADDH  rd, rs, rt        Parallel Multiply-Add Halfword
- * PMSUBH  rd, rs, rt        Parallel Multiply-Subtract Halfword
- * PHMADH  rd, rs, rt        Parallel Horizontal Multiply-Add Halfword
- * PHMSBH  rd, rs, rt        Parallel Horizontal Multiply-Subtract Halfword
- * PDIVBW  rs, rt            Parallel Divide Broadcast Word
- * PMFHI   rd                Parallel Move From HI Register
- * PMFLO   rd                Parallel Move From LO Register
- * PMTHI   rs                Parallel Move To HI Register
- * PMTLO   rs                Parallel Move To LO Register
- * PMFHL   rd                Parallel Move From HI/LO Register
- * PMTHL   rs                Parallel Move To HI/LO Register
- *
- *     Pack/Extend (11 instructions)
- *     -----------------------------
- * PPAC5   rd, rt            Parallel Pack to 5 bits
- * PPACB   rd, rs, rt        Parallel Pack to Byte
- * PPACH   rd, rs, rt        Parallel Pack to Halfword
- * PPACW   rd, rs, rt        Parallel Pack to Word
- * PEXT5   rd, rt            Parallel Extend Upper from 5 bits
- * PEXTUB  rd, rs, rt        Parallel Extend Upper from Byte
- * PEXTLB  rd, rs, rt        Parallel Extend Lower from Byte
- * PEXTUH  rd, rs, rt        Parallel Extend Upper from Halfword
- * PEXTLH  rd, rs, rt        Parallel Extend Lower from Halfword
- * PEXTUW  rd, rs, rt        Parallel Extend Upper from Word
- * PEXTLW  rd, rs, rt        Parallel Extend Lower from Word
- *
- *     Others (16 instructions)
- *     ------------------------
- * PCPYH   rd, rt            Parallel Copy Halfword
- * PCPYLD  rd, rs, rt        Parallel Copy Lower Doubleword
- * PCPYUD  rd, rs, rt        Parallel Copy Upper Doubleword
- * PREVH   rd, rt            Parallel Reverse Halfword
- * PINTH   rd, rs, rt        Parallel Interleave Halfword
- * PINTEH  rd, rs, rt        Parallel Interleave Even Halfword
- * PEXEH   rd, rt            Parallel Exchange Even Halfword
- * PEXCH   rd, rt            Parallel Exchange Center Halfword
- * PEXEW   rd, rt            Parallel Exchange Even Word
- * PEXCW   rd, rt            Parallel Exchange Center Word
- * QFSRV   rd, rs, rt        Quadword Funnel Shift Right Variable
- * MFSA    rd                Move from Shift Amount Register
- * MTSA    rs                Move to Shift Amount Register
- * MTSAB   rs, immediate     Move Byte Count to Shift Amount Register
- * MTSAH   rs, immediate     Move Halfword Count to Shift Amount Register
- * PROT3W  rd, rt            Parallel Rotate 3 Words
- *
  *     MMI (MultiMedia Instruction) encodings
  *     ======================================
  *
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index de09bb0d314..243a81c3c5e 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -14,6 +14,22 @@
 /* Include the auto-generated decoder.  */
 #include "decode-tx79.c.inc"
 
+/*
+ *     Overview of the TX79-specific instruction set
+ *     =============================================
+ *
+ * The R5900 and the C790 have 128-bit wide GPRs, where the upper 64 bits
+ * are only used by the specific quadword (128-bit) LQ/SQ load/store
+ * instructions and certain multimedia instructions (MMIs). These MMIs
+ * configure the 128-bit data path as two 64-bit, four 32-bit, eight 16-bit
+ * or sixteen 8-bit paths.
+ *
+ * Reference:
+ *
+ * The Toshiba TX System RISC TX79 Core Architecture manual,
+ * https://wiki.qemu.org/File:C790.pdf
+ */
+
 bool decode_ext_tx79(DisasContext *ctx, uint32_t insn)
 {
     if (TARGET_LONG_BITS == 64 && decode_tx79(ctx, insn)) {
@@ -22,6 +38,30 @@ bool decode_ext_tx79(DisasContext *ctx, uint32_t insn)
     return false;
 }
 
+/*
+ *     Three-Operand Multiply and Multiply-Add (4 instructions)
+ *     --------------------------------------------------------
+ * MADD    [rd,] rs, rt      Multiply/Add
+ * MADDU   [rd,] rs, rt      Multiply/Add Unsigned
+ * MULT    [rd,] rs, rt      Multiply (3-operand)
+ * MULTU   [rd,] rs, rt      Multiply Unsigned (3-operand)
+ */
+
+/*
+ *     Multiply Instructions for Pipeline 1 (10 instructions)
+ *     ------------------------------------------------------
+ * MULT1   [rd,] rs, rt      Multiply Pipeline 1
+ * MULTU1  [rd,] rs, rt      Multiply Unsigned Pipeline 1
+ * DIV1    rs, rt            Divide Pipeline 1
+ * DIVU1   rs, rt            Divide Unsigned Pipeline 1
+ * MADD1   [rd,] rs, rt      Multiply-Add Pipeline 1
+ * MADDU1  [rd,] rs, rt      Multiply-Add Unsigned Pipeline 1
+ * MFHI1   rd                Move From HI1 Register
+ * MFLO1   rd                Move From LO1 Register
+ * MTHI1   rs                Move To HI1 Register
+ * MTLO1   rs                Move To LO1 Register
+ */
+
 static bool trans_MFHI1(DisasContext *ctx, arg_rtype *a)
 {
     gen_store_gpr(cpu_HI[1], a->rd);
@@ -50,6 +90,154 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
     return true;
 }
 
+/*
+ *     Arithmetic (19 instructions)
+ *     ----------------------------
+ * PADDB   rd, rs, rt        Parallel Add Byte
+ * PSUBB   rd, rs, rt        Parallel Subtract Byte
+ * PADDH   rd, rs, rt        Parallel Add Halfword
+ * PSUBH   rd, rs, rt        Parallel Subtract Halfword
+ * PADDW   rd, rs, rt        Parallel Add Word
+ * PSUBW   rd, rs, rt        Parallel Subtract Word
+ * PADSBH  rd, rs, rt        Parallel Add/Subtract Halfword
+ * PADDSB  rd, rs, rt        Parallel Add with Signed Saturation Byte
+ * PSUBSB  rd, rs, rt        Parallel Subtract with Signed Saturation Byte
+ * PADDSH  rd, rs, rt        Parallel Add with Signed Saturation Halfword
+ * PSUBSH  rd, rs, rt        Parallel Subtract with Signed Saturation Halfword
+ * PADDSW  rd, rs, rt        Parallel Add with Signed Saturation Word
+ * PSUBSW  rd, rs, rt        Parallel Subtract with Signed Saturation Word
+ * PADDUB  rd, rs, rt        Parallel Add with Unsigned saturation Byte
+ * PSUBUB  rd, rs, rt        Parallel Subtract with Unsigned saturation Byte
+ * PADDUH  rd, rs, rt        Parallel Add with Unsigned saturation Halfword
+ * PSUBUH  rd, rs, rt        Parallel Subtract with Unsigned saturation Halfword
+ * PADDUW  rd, rs, rt        Parallel Add with Unsigned saturation Word
+ * PSUBUW  rd, rs, rt        Parallel Subtract with Unsigned saturation Word
+ */
+
+/*
+ *     Min/Max (4 instructions)
+ *     ------------------------
+ * PMAXH   rd, rs, rt        Parallel Maximum Halfword
+ * PMINH   rd, rs, rt        Parallel Minimum Halfword
+ * PMAXW   rd, rs, rt        Parallel Maximum Word
+ * PMINW   rd, rs, rt        Parallel Minimum Word
+ */
+
+/*
+ *     Absolute (2 instructions)
+ *     -------------------------
+ * PABSH   rd, rt            Parallel Absolute Halfword
+ * PABSW   rd, rt            Parallel Absolute Word
+ */
+
+/*
+ *     Logical (4 instructions)
+ *     ------------------------
+ * PAND    rd, rs, rt        Parallel AND
+ * POR     rd, rs, rt        Parallel OR
+ * PXOR    rd, rs, rt        Parallel XOR
+ * PNOR    rd, rs, rt        Parallel NOR
+ */
+
+/*
+ *     Shift (9 instructions)
+ *     ----------------------
+ * PSLLH   rd, rt, sa        Parallel Shift Left Logical Halfword
+ * PSRLH   rd, rt, sa        Parallel Shift Right Logical Halfword
+ * PSRAH   rd, rt, sa        Parallel Shift Right Arithmetic Halfword
+ * PSLLW   rd, rt, sa        Parallel Shift Left Logical Word
+ * PSRLW   rd, rt, sa        Parallel Shift Right Logical Word
+ * PSRAW   rd, rt, sa        Parallel Shift Right Arithmetic Word
+ * PSLLVW  rd, rt, rs        Parallel Shift Left Logical Variable Word
+ * PSRLVW  rd, rt, rs        Parallel Shift Right Logical Variable Word
+ * PSRAVW  rd, rt, rs        Parallel Shift Right Arithmetic Variable Word
+ */
+
+/*
+ *     Compare (6 instructions)
+ *     ------------------------
+ * PCGTB   rd, rs, rt        Parallel Compare for Greater Than Byte
+ * PCEQB   rd, rs, rt        Parallel Compare for Equal Byte
+ * PCGTH   rd, rs, rt        Parallel Compare for Greater Than Halfword
+ * PCEQH   rd, rs, rt        Parallel Compare for Equal Halfword
+ * PCGTW   rd, rs, rt        Parallel Compare for Greater Than Word
+ * PCEQW   rd, rs, rt        Parallel Compare for Equal Word
+ */
+
+/*
+ *     LZC (1 instruction)
+ *     -------------------
+ * PLZCW   rd, rs            Parallel Leading Zero or One Count Word
+ */
+
+/*
+ *     Quadword Load and Store (2 instructions)
+ *     ----------------------------------------
+ * LQ      rt, offset(base)  Load Quadword
+ * SQ      rt, offset(base)  Store Quadword
+ */
+
+/*
+ *     Multiply and Divide (19 instructions)
+ *     -------------------------------------
+ * PMULTW  rd, rs, rt        Parallel Multiply Word
+ * PMULTUW rd, rs, rt        Parallel Multiply Unsigned Word
+ * PDIVW   rs, rt            Parallel Divide Word
+ * PDIVUW  rs, rt            Parallel Divide Unsigned Word
+ * PMADDW  rd, rs, rt        Parallel Multiply-Add Word
+ * PMADDUW rd, rs, rt        Parallel Multiply-Add Unsigned Word
+ * PMSUBW  rd, rs, rt        Parallel Multiply-Subtract Word
+ * PMULTH  rd, rs, rt        Parallel Multiply Halfword
+ * PMADDH  rd, rs, rt        Parallel Multiply-Add Halfword
+ * PMSUBH  rd, rs, rt        Parallel Multiply-Subtract Halfword
+ * PHMADH  rd, rs, rt        Parallel Horizontal Multiply-Add Halfword
+ * PHMSBH  rd, rs, rt        Parallel Horizontal Multiply-Subtract Halfword
+ * PDIVBW  rs, rt            Parallel Divide Broadcast Word
+ * PMFHI   rd                Parallel Move From HI Register
+ * PMFLO   rd                Parallel Move From LO Register
+ * PMTHI   rs                Parallel Move To HI Register
+ * PMTLO   rs                Parallel Move To LO Register
+ * PMFHL   rd                Parallel Move From HI/LO Register
+ * PMTHL   rs                Parallel Move To HI/LO Register
+ */
+
+/*
+ *     Pack/Extend (11 instructions)
+ *     -----------------------------
+ * PPAC5   rd, rt            Parallel Pack to 5 bits
+ * PPACB   rd, rs, rt        Parallel Pack to Byte
+ * PPACH   rd, rs, rt        Parallel Pack to Halfword
+ * PPACW   rd, rs, rt        Parallel Pack to Word
+ * PEXT5   rd, rt            Parallel Extend Upper from 5 bits
+ * PEXTUB  rd, rs, rt        Parallel Extend Upper from Byte
+ * PEXTLB  rd, rs, rt        Parallel Extend Lower from Byte
+ * PEXTUH  rd, rs, rt        Parallel Extend Upper from Halfword
+ * PEXTLH  rd, rs, rt        Parallel Extend Lower from Halfword
+ * PEXTUW  rd, rs, rt        Parallel Extend Upper from Word
+ * PEXTLW  rd, rs, rt        Parallel Extend Lower from Word
+ */
+
+/*
+ *     Others (16 instructions)
+ *     ------------------------
+ * PCPYH   rd, rt            Parallel Copy Halfword
+ * PCPYLD  rd, rs, rt        Parallel Copy Lower Doubleword
+ * PCPYUD  rd, rs, rt        Parallel Copy Upper Doubleword
+ * PREVH   rd, rt            Parallel Reverse Halfword
+ * PINTH   rd, rs, rt        Parallel Interleave Halfword
+ * PINTEH  rd, rs, rt        Parallel Interleave Even Halfword
+ * PEXEH   rd, rt            Parallel Exchange Even Halfword
+ * PEXCH   rd, rt            Parallel Exchange Center Halfword
+ * PEXEW   rd, rt            Parallel Exchange Even Word
+ * PEXCW   rd, rt            Parallel Exchange Center Word
+ * QFSRV   rd, rs, rt        Quadword Funnel Shift Right Variable
+ * MFSA    rd                Move from Shift Amount Register
+ * MTSA    rs                Move to Shift Amount Register
+ * MTSAB   rs, immediate     Move Byte Count to Shift Amount Register
+ * MTSAH   rs, immediate     Move Halfword Count to Shift Amount Register
+ * PROT3W  rd, rt            Parallel Rotate 3 Words
+ */
+
 /* Parallel Copy Halfword */
 static bool trans_PCPYH(DisasContext *s, arg_rtype *a)
 {
-- 
2.26.2

Re: [RFC PATCH 14/42] target/mips/tx79: Salvage instructions description comment

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> This comment describing the tx79 opcodes is helpful. As we
> will implement these instructions in tx79_translate.c, move
> the comment there.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/translate.c      | 160 -----------------------------
>  target/mips/tx79_translate.c | 188 +++++++++++++++++++++++++++++++++++
>  2 files changed, 188 insertions(+), 160 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[RFC PATCH 15/42] target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic)

[Philippe Mathieu-Daudé]

Introduce the parallel logic opcodes:

 - PAND (Parallel AND)
 - POR  (Parallel OR)
 - PXOR (Parallel XOR)
 - PNOR (Parallel NOR)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tx79.decode      |  4 +++
 target/mips/tx79_translate.c | 54 ++++++++++++++++++++++++++++++++++++
 2 files changed, 58 insertions(+)

diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index 0f748b53a64..26c80b9bce5 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -32,8 +32,12 @@ MTLO1           011100 .....  0000000000 00000 010011   @rs
 # MMI2
 
 PCPYLD          011100 ..... ..... ..... 01110 001001   @rs_rt_rd
+PAND            011100 ..... ..... ..... 10010 001001   @rs_rt_rd
+PXOR            011100 ..... ..... ..... 10011 001001   @rs_rt_rd
 
 # MMI3
 
 PCPYUD          011100 ..... ..... ..... 01110 101001   @rs_rt_rd
+POR             011100 ..... ..... ..... 10010 101001   @rs_rt_rd
+PNOR            011100 ..... ..... ..... 10011 101001   @rs_rt_rd
 PCPYH           011100 00000 ..... ..... 11011 101001   @rt_rd
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index 243a81c3c5e..28d07baaa73 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -2,6 +2,7 @@
  * Toshiba TX79-specific instructions translation routines
  *
  *  Copyright (c) 2018 Fredrik Noring
+ *  Copyright (c) 2021 Philippe Mathieu-Daudé
  *
  * SPDX-License-Identifier: GPL-2.0-or-later
  */
@@ -139,6 +140,59 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
  * PNOR    rd, rs, rt        Parallel NOR
  */
 
+static bool trans_parallel_logic(DisasContext *ctx, arg_rtype *a,
+                                 void (*gen_logic_i64)(TCGv_i64, TCGv_i64, TCGv_i64))
+{
+    TCGv_i64 ax, bx;
+
+    if (a->rd == 0) {
+        /* nop */
+        return true;
+    }
+
+    ax = tcg_temp_new_i64();
+    bx = tcg_temp_new_i64();
+
+    /* Lower halve */
+    gen_load_gpr(ax, a->rs);
+    gen_load_gpr(bx, a->rt);
+    gen_logic_i64(cpu_gpr[a->rd], ax, bx);
+
+    /* Upper halve */
+    gen_load_gpr_hi(ax, a->rs);
+    gen_load_gpr_hi(bx, a->rt);
+    gen_logic_i64(cpu_gpr_hi[a->rd], ax, bx);
+
+    tcg_temp_free(bx);
+    tcg_temp_free(ax);
+
+    return true;
+}
+
+/* Parallel And */
+static bool trans_PAND(DisasContext *ctx, arg_rtype *a)
+{
+    return trans_parallel_logic(ctx, a, tcg_gen_and_i64);
+}
+
+/* Parallel Or */
+static bool trans_POR(DisasContext *ctx, arg_rtype *a)
+{
+    return trans_parallel_logic(ctx, a, tcg_gen_or_i64);
+}
+
+/* Parallel Exclusive Or */
+static bool trans_PXOR(DisasContext *ctx, arg_rtype *a)
+{
+    return trans_parallel_logic(ctx, a, tcg_gen_xor_i64);
+}
+
+/* Parallel Not Or */
+static bool trans_PNOR(DisasContext *ctx, arg_rtype *a)
+{
+    return trans_parallel_logic(ctx, a, tcg_gen_nor_i64);
+}
+
 /*
  *     Shift (9 instructions)
  *     ----------------------
-- 
2.26.2

Re: [RFC PATCH 15/42] target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic)

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> +    /* Lower halve */

"half".  Lots of repetitions across the patch set.

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[RFC PATCH 16/42] target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract)

[Philippe Mathieu-Daudé]

Introduce the 'Parallel Subtract' opcodes:

 - PSUBB (Parallel Subtract Byte)
 - PSUBH (Parallel Subtract Halfword)
 - PSUBW (Parallel Subtract Word)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tx79.decode      |  6 ++++
 target/mips/tx79_translate.c | 61 ++++++++++++++++++++++++++++++++++++
 2 files changed, 67 insertions(+)

diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index 26c80b9bce5..d1c07c7d901 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -29,6 +29,12 @@ MTHI1           011100 .....  0000000000 00000 010001   @rs
 MFLO1           011100 0000000000  ..... 00000 010010   @rd
 MTLO1           011100 .....  0000000000 00000 010011   @rs
 
+# MMI0
+
+PSUBW           011100 ..... ..... ..... 00001 001000   @rs_rt_rd
+PSUBH           011100 ..... ..... ..... 00101 001000   @rs_rt_rd
+PSUBB           011100 ..... ..... ..... 01001 001000   @rs_rt_rd
+
 # MMI2
 
 PCPYLD          011100 ..... ..... ..... 01110 001001   @rs_rt_rd
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index 28d07baaa73..23146f6bfac 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -115,6 +115,67 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a)
  * PSUBUW  rd, rs, rt        Parallel Subtract with Unsigned saturation Word
  */
 
+static bool trans_parallel_substract(DisasContext *ctx, arg_rtype *a, unsigned wlen)
+{
+    TCGv_i64 ax, bx, t0, t1, t2;
+
+    if (a->rd == 0) {
+        /* nop */
+        return true;
+    }
+
+    ax = tcg_temp_new_i64();
+    bx = tcg_temp_new_i64();
+    t0 = tcg_temp_new_i64();
+    t1 = tcg_temp_new_i64();
+    t2 = tcg_temp_new_i64();
+
+    /* Lower halve */
+    gen_load_gpr(ax, a->rs);
+    gen_load_gpr(bx, a->rt);
+    for (int i = 0; i < (64 / wlen); i++) {
+        tcg_gen_sextract_i64(t0, ax, wlen * i, wlen);
+        tcg_gen_sextract_i64(t1, bx, wlen * i, wlen);
+        tcg_gen_sub_i64(t2, t0, t1);
+        tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], t2, wlen * i, wlen);
+    }
+    /* Upper halve */
+    gen_load_gpr_hi(ax, a->rs);
+    gen_load_gpr_hi(bx, a->rt);
+    for (int i = 0; i < (64 / wlen); i++) {
+        tcg_gen_sextract_i64(t0, ax, wlen * i, wlen);
+        tcg_gen_sextract_i64(t1, bx, wlen * i, wlen);
+        tcg_gen_sub_i64(t2, t0, t1);
+        tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], t2, wlen * i, wlen);
+    }
+
+    tcg_temp_free(t2);
+    tcg_temp_free(t1);
+    tcg_temp_free(t0);
+    tcg_temp_free(bx);
+    tcg_temp_free(ax);
+
+    return true;
+}
+
+/* Parallel Subtract Byte */
+static bool trans_PSUBB(DisasContext *ctx, arg_rtype *a)
+{
+    return trans_parallel_substract(ctx, a, 8);
+}
+
+/* Parallel Subtract Halfword */
+static bool trans_PSUBH(DisasContext *ctx, arg_rtype *a)
+{
+    return trans_parallel_substract(ctx, a, 16);
+}
+
+/* Parallel Subtract Word */
+static bool trans_PSUBW(DisasContext *ctx, arg_rtype *a)
+{
+    return trans_parallel_substract(ctx, a, 32);
+}
+
 /*
  *     Min/Max (4 instructions)
  *     ------------------------
-- 
2.26.2

Re: [RFC PATCH 16/42] target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract)

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> +/* Parallel Subtract Byte */
> +static bool trans_PSUBB(DisasContext *ctx, arg_rtype *a)
> +{
> +    return trans_parallel_substract(ctx, a, 8);
> +}
> +
> +/* Parallel Subtract Halfword */
> +static bool trans_PSUBH(DisasContext *ctx, arg_rtype *a)
> +{
> +    return trans_parallel_substract(ctx, a, 16);
> +}
> +
> +/* Parallel Subtract Word */
> +static bool trans_PSUBW(DisasContext *ctx, arg_rtype *a)
> +{
> +    return trans_parallel_substract(ctx, a, 32);
> +}

We already have helpers for these operations.  Use your trans_parallel_logic
with tcg_gen_vec_sub{8,16,32}_i64.


r~

Re: [RFC PATCH 16/42] target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract)

[Philippe Mathieu-Daudé]

On 2/15/21 5:38 PM, Richard Henderson wrote:
> On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
>> +/* Parallel Subtract Byte */
>> +static bool trans_PSUBB(DisasContext *ctx, arg_rtype *a)
>> +{
>> +    return trans_parallel_substract(ctx, a, 8);
>> +}
>> +
>> +/* Parallel Subtract Halfword */
>> +static bool trans_PSUBH(DisasContext *ctx, arg_rtype *a)
>> +{
>> +    return trans_parallel_substract(ctx, a, 16);
>> +}
>> +
>> +/* Parallel Subtract Word */
>> +static bool trans_PSUBW(DisasContext *ctx, arg_rtype *a)
>> +{
>> +    return trans_parallel_substract(ctx, a, 32);
>> +}
> 
> We already have helpers for these operations.  Use your trans_parallel_logic
> with tcg_gen_vec_sub{8,16,32}_i64.

Very nice :>

[RFC PATCH 17/42] target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word)

[Philippe Mathieu-Daudé]

Introduce the PEXTUW opcode (Parallel Extend Upper from Word).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tx79.decode      |  4 ++++
 target/mips/tx79_translate.c | 26 ++++++++++++++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index d1c07c7d901..ead5f8281e5 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -35,6 +35,10 @@ PSUBW           011100 ..... ..... ..... 00001 001000   @rs_rt_rd
 PSUBH           011100 ..... ..... ..... 00101 001000   @rs_rt_rd
 PSUBB           011100 ..... ..... ..... 01001 001000   @rs_rt_rd
 
+# MMI1
+
+PEXTUW          011100 ..... ..... ..... 10010 101000   @rs_rt_rd
+
 # MMI2
 
 PCPYLD          011100 ..... ..... ..... 01110 001001   @rs_rt_rd
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index 23146f6bfac..0a2fb28600b 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -332,6 +332,32 @@ static bool trans_PNOR(DisasContext *ctx, arg_rtype *a)
  * PEXTLW  rd, rs, rt        Parallel Extend Lower from Word
  */
 
+/* Parallel Extend Upper from Word */
+static bool trans_PEXTUW(DisasContext *ctx, arg_rtype *a)
+{
+    TCGv_i64 ax, bx;
+
+    if (a->rd == 0) {
+        /* nop */
+        return true;
+    }
+
+    ax = tcg_temp_new_i64();
+    bx = tcg_temp_new_i64();
+
+    gen_load_gpr_hi(ax, a->rs);
+    gen_load_gpr_hi(bx, a->rt);
+
+    tcg_gen_deposit_i64(cpu_gpr[a->rd], bx, ax, 32, 32);
+    tcg_gen_shri_i64(bx, bx, 32);
+    tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], ax, bx, 0, 32);
+
+    tcg_temp_free(bx);
+    tcg_temp_free(ax);
+
+    return true;
+}
+
 /*
  *     Others (16 instructions)
  *     ------------------------
-- 
2.26.2

Re: [RFC PATCH 17/42] target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word)

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> +    tcg_gen_deposit_i64(cpu_gpr[a->rd], bx, ax, 32, 32);
> +    tcg_gen_shri_i64(bx, bx, 32);
> +    tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], ax, bx, 0, 32);

I think you should pull this out as a helper:

void gen_pextw(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 a, TCGv_i64 b);

since you'll re-use this for PEXTLW.


r~

Re: [RFC PATCH 17/42] target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word)

[Philippe Mathieu-Daudé]

On 2/15/21 5:44 PM, Richard Henderson wrote:
> On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
>> +    tcg_gen_deposit_i64(cpu_gpr[a->rd], bx, ax, 32, 32);
>> +    tcg_gen_shri_i64(bx, bx, 32);
>> +    tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], ax, bx, 0, 32);
> 
> I think you should pull this out as a helper:
> 
> void gen_pextw(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 a, TCGv_i64 b);
> 
> since you'll re-use this for PEXTLW.

Indeed, thanks :)

[RFC PATCH 18/42] target/mips/tx79: Introduce PEXTU[BHW] opcodes (Parallel Extend Lower)

[Philippe Mathieu-Daudé]

Introduce the 'Parallel Extend Lower' opcodes:

 - PEXTLB (Parallel Extend Upper from Byte)
 - PEXTLH (Parallel Extend Upper from Halfword)
 - PEXTLW (Parallel Extend Upper from Word)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tx79.decode      |  3 ++
 target/mips/tx79_translate.c | 78 ++++++++++++++++++++++++++++++++++++
 2 files changed, 81 insertions(+)

diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index ead5f8281e5..98f21d33e3f 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -34,6 +34,9 @@ MTLO1           011100 .....  0000000000 00000 010011   @rs
 PSUBW           011100 ..... ..... ..... 00001 001000   @rs_rt_rd
 PSUBH           011100 ..... ..... ..... 00101 001000   @rs_rt_rd
 PSUBB           011100 ..... ..... ..... 01001 001000   @rs_rt_rd
+PEXTLW          011100 ..... ..... ..... 10010 001000   @rs_rt_rd
+PEXTLH          011100 ..... ..... ..... 10110 001000   @rs_rt_rd
+PEXTLB          011100 ..... ..... ..... 11010 001000   @rs_rt_rd
 
 # MMI1
 
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index 0a2fb28600b..11968d6edab 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -332,6 +332,84 @@ static bool trans_PNOR(DisasContext *ctx, arg_rtype *a)
  * PEXTLW  rd, rs, rt        Parallel Extend Lower from Word
  */
 
+static bool trans_PEXTLx(DisasContext *ctx, arg_rtype *a, unsigned wlen)
+{
+    TCGv_i64 ax, bx;
+
+    if (a->rd == 0) {
+        /* nop */
+        return true;
+    }
+
+    ax = tcg_temp_new_i64();
+    bx = tcg_temp_new_i64();
+
+    gen_load_gpr(ax, a->rs);
+    gen_load_gpr(bx, a->rt);
+
+    /* Lower halve */
+    for (int i = 0; i < 64 / (2 * wlen); i++) {
+        tcg_gen_deposit_i64(cpu_gpr[a->rd],
+                            cpu_gpr[a->rd], bx, 2 * wlen * i, wlen);
+        tcg_gen_deposit_i64(cpu_gpr[a->rd],
+                            cpu_gpr[a->rd], ax, 2 * wlen * i + wlen, wlen);
+        tcg_gen_shri_i64(bx, bx, wlen);
+        tcg_gen_shri_i64(ax, ax, wlen);
+    }
+    /* Upper halve */
+    for (int i = 0; i < 64 / (2 * wlen); i++) {
+        tcg_gen_deposit_i64(cpu_gpr_hi[a->rd],
+                            cpu_gpr_hi[a->rd], bx, 2 * wlen * i, wlen);
+        tcg_gen_deposit_i64(cpu_gpr_hi[a->rd],
+                            cpu_gpr_hi[a->rd], ax, 2 * wlen * i + wlen, wlen);
+        tcg_gen_shri_i64(bx, bx, wlen);
+        tcg_gen_shri_i64(ax, ax, wlen);
+    }
+
+    tcg_temp_free(bx);
+    tcg_temp_free(ax);
+
+    return true;
+}
+
+/* Parallel Extend Lower from Byte */
+static bool trans_PEXTLB(DisasContext *ctx, arg_rtype *a)
+{
+    return trans_PEXTLx(ctx, a, 8);
+}
+
+/* Parallel Extend Lower from Halfword */
+static bool trans_PEXTLH(DisasContext *ctx, arg_rtype *a)
+{
+    return trans_PEXTLx(ctx, a, 16);
+}
+
+/* Parallel Extend Lower from Word */
+static bool trans_PEXTLW(DisasContext *ctx, arg_rtype *a)
+{
+    TCGv_i64 ax, bx;
+
+    if (a->rd == 0) {
+        /* nop */
+        return true;
+    }
+
+    ax = tcg_temp_new_i64();
+    bx = tcg_temp_new_i64();
+
+    gen_load_gpr(ax, a->rs);
+    gen_load_gpr(bx, a->rt);
+
+    tcg_gen_deposit_i64(cpu_gpr[a->rd], bx, ax, 32, 32);
+    tcg_gen_shri_i64(bx, bx, 32);
+    tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], ax, bx, 0, 32);
+
+    tcg_temp_free(bx);
+    tcg_temp_free(ax);
+
+    return true;
+}
+
 /* Parallel Extend Upper from Word */
 static bool trans_PEXTUW(DisasContext *ctx, arg_rtype *a)
 {
-- 
2.26.2

Re: [RFC PATCH 18/42] target/mips/tx79: Introduce PEXTU[BHW] opcodes (Parallel Extend Lower)

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> Introduce the 'Parallel Extend Lower' opcodes:

$SUBJECT s/PEXTU/PEXTL/.

> +    /* Lower halve */
> +    for (int i = 0; i < 64 / (2 * wlen); i++) {
> +        tcg_gen_deposit_i64(cpu_gpr[a->rd],
> +                            cpu_gpr[a->rd], bx, 2 * wlen * i, wlen);
> +        tcg_gen_deposit_i64(cpu_gpr[a->rd],
> +                            cpu_gpr[a->rd], ax, 2 * wlen * i + wlen, wlen);
> +        tcg_gen_shri_i64(bx, bx, wlen);
> +        tcg_gen_shri_i64(ax, ax, wlen);
> +    }
> +    /* Upper halve */
> +    for (int i = 0; i < 64 / (2 * wlen); i++) {
> +        tcg_gen_deposit_i64(cpu_gpr_hi[a->rd],
> +                            cpu_gpr_hi[a->rd], bx, 2 * wlen * i, wlen);
> +        tcg_gen_deposit_i64(cpu_gpr_hi[a->rd],
> +                            cpu_gpr_hi[a->rd], ax, 2 * wlen * i + wlen, wlen);
> +        tcg_gen_shri_i64(bx, bx, wlen);
> +        tcg_gen_shri_i64(ax, ax, wlen);
> +    }

Right, so, this expands to (4 * 4 * 2) = 32 operations for pextlb, if deposit
is supported, or ((4*2 + 2) * 4 * 2) = 80 operations if not (4 per deposit).

We can do a bit better, though, exploiting parallelism.

/* 5 or 8 operations, w/ or w/o deposit */
void gen_widen_b(TCGv_i64 d, TCGv_i64 s)
{
    TCGv_i64 x = tcg_temp_new_i64();
    TCGv_i64 y = tcg_temp_new_i64();
    TCGv_i64 m0 = tcg_constant_i64(0x0000ff000000ff00ull);

    /* s = abcdefgh */
    tcg_gen_deposit_i64(x, s, s, 16, 48);
    /* x = cdefghgh */
    tcg_gen_and_i64(y, x, m);
    /* y = 00e000g0 */
    tcg_gen_andc_i64(x, x, m0);
    /* x = 000f000h */
    tcg_gen_shli_i64(y, y, 8);
    /* y = 0e000g00 */
    tcg_gen_or_i64(d, x, y);
    /* d = 0e0f0g0h */

    tcg_temp_free_i64(x);
    tcg_temp_free_i64(y);
}

/* 12 or 18 operations w/ or w/o deposit */
void gen_pextb(TCGv_i64 d, TCGv_i64 s, TCGv_i64 t)
{
    TCGv_i64 x = tcg_temp_new_i64();

    gen_widen_b(x, s);
    gen_widen_b(d, s);
    tcg_gen_shli_i64(x, x, 8);
    tcg_gen_or_i64(d, d, x);

    tcg_temp_free_i64(x);
}

then

    gen_read_gpr(s, a->rs);
    gen_read_gpr(t, a->rt);
    gen_pextb(cpu_gpr[a->rd], s, t);

    tcg_gen_shri_i64(s, s, 32);
    tcg_gen_shri_i64(t, t, 32);
    gen_pextb(cpu_gpr_hi[a->rd], s, t);

gives you the result in 26 or 38 operations.

Similarly

void gen_widen_h(TCGv_i64 d, TCGv_i64 s)
{
    TCGv_i64 x = tcg_temp_new_i64();

    /* s = abcd */
    tcg_gen_andi_i64(x, s, 0xffff0000u);
    /* x = 00c0 */
    tcg_gen_deposit_i64(d, s, x, 16, 48);
    /* d = 0c0d */

    tcg_temp_free_i64(x);
}


r~

[RFC PATCH 19/42] target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal)

[Philippe Mathieu-Daudé]

Introduce the 'Parallel Compare for Equal' opcodes:

 - PCEQB (Parallel Compare for Equal Byte)
 - PCEQH (Parallel Compare for Equal Halfword)
 - PCEQW (Parallel Compare for Equal Word)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tx79.decode      |  3 ++
 target/mips/tx79_translate.c | 66 ++++++++++++++++++++++++++++++++++++
 2 files changed, 69 insertions(+)

diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index 98f21d33e3f..cfe721755ca 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -40,6 +40,9 @@ PEXTLB          011100 ..... ..... ..... 11010 001000   @rs_rt_rd
 
 # MMI1
 
+PCEQW           011100 ..... ..... ..... 00010 101000   @rs_rt_rd
+PCEQH           011100 ..... ..... ..... 00110 101000   @rs_rt_rd
+PCEQB           011100 ..... ..... ..... 01010 101000   @rs_rt_rd
 PEXTUW          011100 ..... ..... ..... 10010 101000   @rs_rt_rd
 
 # MMI2
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index 11968d6edab..f084faa48a7 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -279,6 +279,72 @@ static bool trans_PNOR(DisasContext *ctx, arg_rtype *a)
  * PCEQW   rd, rs, rt        Parallel Compare for Equal Word
  */
 
+static bool trans_parallel_compare(DisasContext *ctx, arg_rtype *a,
+                                   TCGCond cond, unsigned wlen)
+{
+    TCGv_i64 c0, c1, ax, bx, t0, t1, t2;
+
+    if (a->rd == 0) {
+        /* nop */
+        return true;
+    }
+
+    c0 = tcg_const_tl(0);
+    c1 = tcg_const_tl(0xffffffff);
+    ax = tcg_temp_new_i64();
+    bx = tcg_temp_new_i64();
+    t0 = tcg_temp_new_i64();
+    t1 = tcg_temp_new_i64();
+    t2 = tcg_temp_new_i64();
+
+    /* Lower halve */
+    gen_load_gpr(ax, a->rs);
+    gen_load_gpr(bx, a->rt);
+    for (int i = 0; i < (64 / wlen); i++) {
+        tcg_gen_sextract_i64(t0, ax, wlen * i, wlen);
+        tcg_gen_sextract_i64(t1, bx, wlen * i, wlen);
+        tcg_gen_movcond_i64(cond, t2, t1, t0, c1, c0);
+        tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], t2, wlen * i, wlen);
+    }
+    /* Upper halve */
+    gen_load_gpr_hi(ax, a->rs);
+    gen_load_gpr_hi(bx, a->rt);
+    for (int i = 0; i < (64 / wlen); i++) {
+        tcg_gen_sextract_i64(t0, ax, wlen * i, wlen);
+        tcg_gen_sextract_i64(t1, bx, wlen * i, wlen);
+        tcg_gen_movcond_i64(cond, t2, t1, t0, c1, c0);
+        tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], t2, wlen * i, wlen);
+    }
+
+    tcg_temp_free(t2);
+    tcg_temp_free(t1);
+    tcg_temp_free(t0);
+    tcg_temp_free(bx);
+    tcg_temp_free(ax);
+    tcg_temp_free(c1);
+    tcg_temp_free(c0);
+
+    return true;
+}
+
+/* Parallel Compare for Equal Byte */
+static bool trans_PCEQB(DisasContext *ctx, arg_rtype *a)
+{
+    return trans_parallel_compare(ctx, a, TCG_COND_EQ, 8);
+}
+
+/* Parallel Compare for Equal Halfword */
+static bool trans_PCEQH(DisasContext *ctx, arg_rtype *a)
+{
+    return trans_parallel_compare(ctx, a, TCG_COND_EQ, 16);
+}
+
+/* Parallel Compare for Equal Word */
+static bool trans_PCEQW(DisasContext *ctx, arg_rtype *a)
+{
+    return trans_parallel_compare(ctx, a, TCG_COND_EQ, 32);
+}
+
 /*
  *     LZC (1 instruction)
  *     -------------------
-- 
2.26.2

Re: [RFC PATCH 19/42] target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal)

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> +static bool trans_parallel_compare(DisasContext *ctx, arg_rtype *a,
> +                                   TCGCond cond, unsigned wlen)
> +{
> +    TCGv_i64 c0, c1, ax, bx, t0, t1, t2;
> +
> +    if (a->rd == 0) {
> +        /* nop */
> +        return true;
> +    }
> +
> +    c0 = tcg_const_tl(0);
> +    c1 = tcg_const_tl(0xffffffff);

Cheaper for most hosts to load -1 than a 32-bit value zero-extended to 64 bits.
 That said, you could also use

  setcond(t0, t0, t1, cond);
  neg(t0, t0);

> +    for (int i = 0; i < (64 / wlen); i++) {
> +        tcg_gen_sextract_i64(t0, ax, wlen * i, wlen);
> +        tcg_gen_sextract_i64(t1, bx, wlen * i, wlen);
> +        tcg_gen_movcond_i64(cond, t2, t1, t0, c1, c0);
> +        tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], t2, wlen * i, wlen);
> +    }

For an accumulate loop like this, we'll get better results if the length of the
insert is the remaining length of the register.  That way, the first insert is
width 64, which turns into a move, so that the old value of rd is not used.
Further, we can use extract2 to replace the remaining length when deposit is
not available.

Also, while you will need this compare loop for GT, there's a cheaper way to
compute EQ, which we use in several places in QEMU.

void gen_pceq(TCGv_i64 d, TCGv_i64 s, TCGv_i64 t, MemOp esz)
{
  TCGv_i64 one = tcg_constant_i64(dup_const(esz, 1));
  TCGv_i64 x = tcg_temp_new_i64();

  /* Turn s == t into x == 0. */
  tcg_gen_xor_i64(x, s, t);

  /*
   * See hasless(v,1) from
   * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord
   * Shift the msb down, then use muli to replicate
   * the one bit across the vector element.
   */
  tcg_gen_sub_i64(d, x, one);
  tcg_gen_andc_i64(d, d, x);
  tcg_gen_shri_i64(d, d, (8 << esz) - 1);
  tcg_gen_and_i64(d, d, one);
  tcg_gen_muli_i64(d, d, MAKE_64BIT_MASK(0, 8 << esz));

  tcg_temp_free_i64(x);
}

In both cases, I think you should pull out helper functions and then use
trans_parallel_logic.


r~

[RFC PATCH 20/42] target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than)

[Philippe Mathieu-Daudé]

Introduce the 'Parallel Compare for Greater Than' opcodes:

 - PCGTB (Parallel Compare for Greater Than Byte)
 - PCGTH (Parallel Compare for Greater Than Halfword)
 - PCGTW (Parallel Compare for Greater Than Word)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tx79.decode      |  3 +++
 target/mips/tx79_translate.c | 18 ++++++++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index cfe721755ca..63fbe9694bb 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -32,8 +32,11 @@ MTLO1           011100 .....  0000000000 00000 010011   @rs
 # MMI0
 
 PSUBW           011100 ..... ..... ..... 00001 001000   @rs_rt_rd
+PCGTW           011100 ..... ..... ..... 00010 001000   @rs_rt_rd
 PSUBH           011100 ..... ..... ..... 00101 001000   @rs_rt_rd
+PCGTH           011100 ..... ..... ..... 00110 001000   @rs_rt_rd
 PSUBB           011100 ..... ..... ..... 01001 001000   @rs_rt_rd
+PCGTB           011100 ..... ..... ..... 01010 001000   @rs_rt_rd
 PEXTLW          011100 ..... ..... ..... 10010 001000   @rs_rt_rd
 PEXTLH          011100 ..... ..... ..... 10110 001000   @rs_rt_rd
 PEXTLB          011100 ..... ..... ..... 11010 001000   @rs_rt_rd
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index f084faa48a7..04249b0c20a 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -327,18 +327,36 @@ static bool trans_parallel_compare(DisasContext *ctx, arg_rtype *a,
     return true;
 }
 
+/* Parallel Compare for Greater Than Byte */
+static bool trans_PCGTB(DisasContext *ctx, arg_rtype *a)
+{
+    return trans_parallel_compare(ctx, a, TCG_COND_GE, 8);
+}
+
 /* Parallel Compare for Equal Byte */
 static bool trans_PCEQB(DisasContext *ctx, arg_rtype *a)
 {
     return trans_parallel_compare(ctx, a, TCG_COND_EQ, 8);
 }
 
+/* Parallel Compare for Greater Than Halfword */
+static bool trans_PCGTH(DisasContext *ctx, arg_rtype *a)
+{
+    return trans_parallel_compare(ctx, a, TCG_COND_GE, 16);
+}
+
 /* Parallel Compare for Equal Halfword */
 static bool trans_PCEQH(DisasContext *ctx, arg_rtype *a)
 {
     return trans_parallel_compare(ctx, a, TCG_COND_EQ, 16);
 }
 
+/* Parallel Compare for Greater Than Word */
+static bool trans_PCGTW(DisasContext *ctx, arg_rtype *a)
+{
+    return trans_parallel_compare(ctx, a, TCG_COND_GE, 32);
+}
+
 /* Parallel Compare for Equal Word */
 static bool trans_PCEQW(DisasContext *ctx, arg_rtype *a)
 {
-- 
2.26.2

[RFC PATCH 21/42] target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word)

[Philippe Mathieu-Daudé]

Introduce the PPACW opcode (Parallel Pack to Word).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tx79.decode      |  1 +
 target/mips/tx79_translate.c | 30 ++++++++++++++++++++++++++++++
 2 files changed, 31 insertions(+)

diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index 63fbe9694bb..653910371d2 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -38,6 +38,7 @@ PCGTH           011100 ..... ..... ..... 00110 001000   @rs_rt_rd
 PSUBB           011100 ..... ..... ..... 01001 001000   @rs_rt_rd
 PCGTB           011100 ..... ..... ..... 01010 001000   @rs_rt_rd
 PEXTLW          011100 ..... ..... ..... 10010 001000   @rs_rt_rd
+PPACW           011100 ..... ..... ..... 10011 001000   @rs_rt_rd
 PEXTLH          011100 ..... ..... ..... 10110 001000   @rs_rt_rd
 PEXTLB          011100 ..... ..... ..... 11010 001000   @rs_rt_rd
 
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index 04249b0c20a..ac75d95b82b 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -416,6 +416,36 @@ static bool trans_PCEQW(DisasContext *ctx, arg_rtype *a)
  * PEXTLW  rd, rs, rt        Parallel Extend Lower from Word
  */
 
+/* Parallel Pack to Word */
+static bool trans_PPACW(DisasContext *ctx, arg_rtype *a)
+{
+    TCGv_i64 a0, b0, t0;
+
+    if (a->rd == 0) {
+        /* nop */
+        return true;
+    }
+
+    a0 = tcg_temp_new_i64();
+    b0 = tcg_temp_new_i64();
+    t0 = tcg_temp_new_i64();
+
+    gen_load_gpr(a0, a->rs);
+    gen_load_gpr(b0, a->rt);
+
+    gen_load_gpr_hi(t0, a->rt); /* b1 */
+    tcg_gen_deposit_i64(cpu_gpr[a->rd], b0, t0, 32, 32);
+
+    gen_load_gpr_hi(t0, a->rs); /* a1 */
+    tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], a0, t0, 32, 32);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(b0);
+    tcg_temp_free(a0);
+
+    return true;
+}
+
 static bool trans_PEXTLx(DisasContext *ctx, arg_rtype *a, unsigned wlen)
 {
     TCGv_i64 ax, bx;
-- 
2.26.2

Re: [RFC PATCH 21/42] target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word)

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> Introduce the PPACW opcode (Parallel Pack to Word).
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/tx79.decode      |  1 +
>  target/mips/tx79_translate.c | 30 ++++++++++++++++++++++++++++++
>  2 files changed, 31 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

[RFC PATCH 22/42] target/mips/tx79: Introduce PINTEH (Parallel Interleave Even Halfword)

[Philippe Mathieu-Daudé]

Introduce the PINTEH opcode (Parallel Interleave Even Halfword).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tx79.decode      |  1 +
 target/mips/tx79_translate.c | 45 ++++++++++++++++++++++++++++++++++++
 2 files changed, 46 insertions(+)

diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index 653910371d2..fbd2be569ad 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -57,6 +57,7 @@ PXOR            011100 ..... ..... ..... 10011 001001   @rs_rt_rd
 
 # MMI3
 
+PINTEH          011100 ..... ..... ..... 01010 101001   @rs_rt_rd
 PCPYUD          011100 ..... ..... ..... 01110 101001   @rs_rt_rd
 POR             011100 ..... ..... ..... 10010 101001   @rs_rt_rd
 PNOR            011100 ..... ..... ..... 10011 101001   @rs_rt_rd
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index ac75d95b82b..47d84c465a2 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -638,3 +638,48 @@ static bool trans_PCPYUD(DisasContext *s, arg_rtype *a)
 
     return true;
 }
+
+/* Parallel Interleave Even Halfword */
+static bool trans_PINTEH(DisasContext *ctx, arg_rtype *a)
+{
+    TCGv_i64 ax, bx;
+
+    if (a->rd == 0) {
+        /* nop */
+        return true;
+    }
+
+    if (unlikely(a->rs == 0 && a->rt == 0)) {
+        tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
+        tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
+        return true;
+    }
+
+    ax = tcg_temp_new_i64();
+    bx = tcg_temp_new_i64();
+
+    /* Lower halve */
+    gen_load_gpr(ax, a->rs);
+    gen_load_gpr(bx, a->rt);
+    if (a->rd != a->rt) {
+        tcg_gen_mov_i64(cpu_gpr[a->rd], bx);
+    }
+    tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], ax, 16, 16);
+    tcg_gen_shri_i64(ax, ax, 32);
+    tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], ax, 48, 16);
+
+    /* Upper halve */
+    gen_load_gpr_hi(ax, a->rs);
+    gen_load_gpr_hi(bx, a->rt);
+    if (a->rd != a->rt) {
+        tcg_gen_mov_i64(cpu_gpr_hi[a->rd], bx);
+    }
+    tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], ax, 16, 16);
+    tcg_gen_shri_i64(ax, ax, 32);
+    tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], ax, 48, 16);
+
+    tcg_temp_free(bx);
+    tcg_temp_free(ax);
+
+    return true;
+}
-- 
2.26.2

Re: [RFC PATCH 22/42] target/mips/tx79: Introduce PINTEH (Parallel Interleave Even Halfword)

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> +    /* Lower halve */
> +    gen_load_gpr(ax, a->rs);
> +    gen_load_gpr(bx, a->rt);
> +    if (a->rd != a->rt) {
> +        tcg_gen_mov_i64(cpu_gpr[a->rd], bx);
> +    }
> +    tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], ax, 16, 16);
> +    tcg_gen_shri_i64(ax, ax, 32);
> +    tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], ax, 48, 16);

  mask = tcg_constant_i64(0x0000ffff0000ffffull);
  tcg_gen_shli_i64(x, a, 8);
  tcg_gen_and_i64(x, x, mask);
  tcg_gen_and_i64(y, b, mask);
  tcg_gen_or_i64(d, x, y);

and then you can use trans_parallel_logic.


r~

[RFC PATCH 23/42] target/mips/tx79: Introduce PEXE[HW] opcodes (Parallel Exchange Even)

[Philippe Mathieu-Daudé]

Introduce the PEXEH (Parallel Exchange Even Halfword) and PEXEW
(Parallel Exchange Even Word) opcodes.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tx79.decode      |  2 ++
 target/mips/tx79_translate.c | 70 ++++++++++++++++++++++++++++++++++++
 2 files changed, 72 insertions(+)

diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index fbd2be569ad..0ea9fc95568 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -54,6 +54,8 @@ PEXTUW          011100 ..... ..... ..... 10010 101000   @rs_rt_rd
 PCPYLD          011100 ..... ..... ..... 01110 001001   @rs_rt_rd
 PAND            011100 ..... ..... ..... 10010 001001   @rs_rt_rd
 PXOR            011100 ..... ..... ..... 10011 001001   @rs_rt_rd
+PEXEH           011100 00000 ..... ..... 11010 001001   @rt_rd
+PEXEW           011100 00000 ..... ..... 11110 001001   @rt_rd
 
 # MMI3
 
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index 47d84c465a2..59451a043a4 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -683,3 +683,73 @@ static bool trans_PINTEH(DisasContext *ctx, arg_rtype *a)
 
     return true;
 }
+
+/* Parallel Exchange Even Halfword */
+static bool trans_PEXEH(DisasContext *ctx, arg_rtype *a)
+{
+    TCGv_i64 ax;
+
+    if (a->rd == 0) {
+        /* nop */
+        return true;
+    }
+    if (a->rt == 0) {
+        tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
+        tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
+        return true;
+    }
+
+    ax = tcg_temp_new_i64();
+
+    /* Lower halve */
+    tcg_gen_mov_i64(ax, cpu_gpr[a->rt]);
+    if (a->rd != a->rt) {
+        tcg_gen_mov_i64(cpu_gpr[a->rd], cpu_gpr[a->rt]);
+    }
+    tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], ax, 32, 16);
+    tcg_gen_shri_i64(ax, ax, 32);
+    tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], ax, 0, 16);
+
+    /* Upper halve */
+    tcg_gen_mov_i64(ax, cpu_gpr_hi[a->rt]);
+    if (a->rd != a->rt) {
+        tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt]);
+    }
+    tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], ax, 32, 16);
+    tcg_gen_shri_i64(ax, ax, 32);
+    tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], ax, 0, 16);
+
+    tcg_temp_free(ax);
+
+    return true;
+}
+
+/* Parallel Exchange Even Word */
+static bool trans_PEXEW(DisasContext *ctx, arg_rtype *a)
+{
+    TCGv_i64 ah, al;
+
+    if (a->rd == 0) {
+        /* nop */
+        return true;
+    }
+    if (a->rt == 0) {
+        tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
+        tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
+        return true;
+    }
+
+    ah = tcg_temp_new_i64();
+    al = tcg_temp_new_i64();
+
+    gen_load_gpr(ah, a->rt);
+    gen_load_gpr_hi(al, a->rt);
+
+    tcg_gen_deposit_i64(cpu_gpr[a->rd], ah, al, 0, 32);
+    tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], al, ah, 0, 32);
+
+    tcg_temp_free(al);
+    tcg_temp_free(ah);
+
+    return true;
+}
-- 
2.26.2

Re: [RFC PATCH 23/42] target/mips/tx79: Introduce PEXE[HW] opcodes (Parallel Exchange Even)

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> +    tcg_gen_mov_i64(ax, cpu_gpr[a->rt]);
> +    if (a->rd != a->rt) {
> +        tcg_gen_mov_i64(cpu_gpr[a->rd], cpu_gpr[a->rt]);
> +    }
> +    tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], ax, 32, 16);
> +    tcg_gen_shri_i64(ax, ax, 32);
> +    tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], ax, 0, 16);

  mask = tcg_constant_i64(0x0000ffff0000ffffull);
  tcg_gen_rotli_i64(x, t, 32);
  tcg_gen_and_i64(d, t, mask);
  tcg_gen_and_i64(x, x, mask);
  tcg_gen_or_i64(d, d, x);


r~

[RFC PATCH 24/42] target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words)

[Philippe Mathieu-Daudé]

Introduce the PROT3W opcode (Parallel Rotate 3 Words).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tx79.decode      |  1 +
 target/mips/tx79_translate.c | 28 ++++++++++++++++++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index 0ea9fc95568..79001359242 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -56,6 +56,7 @@ PAND            011100 ..... ..... ..... 10010 001001   @rs_rt_rd
 PXOR            011100 ..... ..... ..... 10011 001001   @rs_rt_rd
 PEXEH           011100 00000 ..... ..... 11010 001001   @rt_rd
 PEXEW           011100 00000 ..... ..... 11110 001001   @rt_rd
+PROT3W          011100 00000 ..... ..... 11111 001001   @rt_rd
 
 # MMI3
 
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index 59451a043a4..c25f61d382c 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -753,3 +753,31 @@ static bool trans_PEXEW(DisasContext *ctx, arg_rtype *a)
 
     return true;
 }
+
+/* Parallel Rotate 3 Words Left */
+static bool trans_PROT3W(DisasContext *ctx, arg_rtype *a)
+{
+    TCGv_i64 ax;
+
+    if (a->rd == 0) {
+        /* nop */
+        return true;
+    }
+    if (a->rt == 0) {
+        tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
+        tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
+        return true;
+    }
+
+    ax = tcg_temp_new_i64();
+
+    tcg_gen_mov_i64(ax, cpu_gpr_hi[a->rt]);
+    tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], ax, cpu_gpr[a->rt], 0, 32);
+
+    tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], ax, 0, 32);
+    tcg_gen_rotri_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], 32);
+
+    tcg_temp_free(ax);
+
+    return true;
+}
-- 
2.26.2

Re: [RFC PATCH 24/42] target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words)

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> Introduce the PROT3W opcode (Parallel Rotate 3 Words).
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/tx79.decode      |  1 +
>  target/mips/tx79_translate.c | 28 ++++++++++++++++++++++++++++
>  2 files changed, 29 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

[RFC PATCH 25/42] target/mips/tx79: Introduce LQ opcode (Load Quadword)

[Philippe Mathieu-Daudé]

Introduce the LQ opcode (Load Quadword) and remove unreachable code.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tx79.decode      |  8 ++++++++
 target/mips/translate.c      | 16 ++--------------
 target/mips/tx79_translate.c | 35 +++++++++++++++++++++++++++++++++++
 3 files changed, 45 insertions(+), 14 deletions(-)

diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index 79001359242..b5396f48c2d 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -13,6 +13,8 @@
 
 &rtype           rs rt rd sa
 
+&itype           base rt offset
+
 ###########################################################################
 # Named instruction formats.  These are generally used to
 # reduce the amount of duplication between instruction patterns.
@@ -22,6 +24,8 @@
 @rs             ...... rs:5  ..... ..........  ......   &rtype rt=0 rd=0 sa=0
 @rd             ...... ..........  rd:5  ..... ......   &rtype rs=0 rt=0 sa=0
 
+@ldst            ...... base:5 rt:5 offset:16            &itype
+
 ###########################################################################
 
 MFHI1           011100 0000000000  ..... 00000 010000   @rd
@@ -65,3 +69,7 @@ PCPYUD          011100 ..... ..... ..... 01110 101001   @rs_rt_rd
 POR             011100 ..... ..... ..... 10010 101001   @rs_rt_rd
 PNOR            011100 ..... ..... ..... 10011 101001   @rs_rt_rd
 PCPYH           011100 00000 ..... ..... 11011 101001   @rt_rd
+
+# SPECIAL
+
+LQ              011110 ..... ..... ................     @ldst
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 109f7f80f3d..bed0489997a 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1780,7 +1780,6 @@ enum {
 
 enum {
     MMI_OPC_CLASS_MMI = 0x1C << 26,    /* Same as OPC_SPECIAL2 */
-    MMI_OPC_LQ        = 0x1E << 26,    /* Same as OPC_MSA */
     MMI_OPC_SQ        = 0x1F << 26,    /* Same as OPC_SPECIAL3 */
 };
 
@@ -27331,11 +27330,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
     }
 }
 
-static void gen_mmi_lq(CPUMIPSState *env, DisasContext *ctx)
-{
-    gen_reserved_instruction(ctx);    /* TODO: MMI_OPC_LQ */
-}
-
 static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset)
 {
     gen_reserved_instruction(ctx);    /* TODO: MMI_OPC_SQ */
@@ -28229,14 +28223,8 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
             gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
         }
         break;
-    case OPC_MDMX: /* MMI_OPC_LQ */
-        if (ctx->insn_flags & INSN_R5900) {
-#if defined(TARGET_MIPS64)
-            gen_mmi_lq(env, ctx);
-#endif
-        } else {
-            /* MDMX: Not implemented. */
-        }
+    case OPC_MDMX:
+        /* MDMX: Not implemented. */
         break;
     case OPC_PCREL:
         check_insn(ctx, ISA_MIPS_R6);
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index c25f61d382c..293efd7bd06 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -376,6 +376,41 @@ static bool trans_PCEQW(DisasContext *ctx, arg_rtype *a)
  * SQ      rt, offset(base)  Store Quadword
  */
 
+static bool trans_LQ(DisasContext *ctx, arg_itype *a)
+{
+    TCGv_i64 t0;
+    TCGv addr;
+
+    if (a->rt == 0) {
+        /* nop */
+        return true;
+    }
+
+    t0 = tcg_temp_new_i64();
+    addr = tcg_temp_new();
+
+    gen_base_offset_addr(ctx, addr, a->base, a->offset);
+    /*
+     * Clear least-significant four bits of the effective
+     * address, effectively creating an aligned address.
+     */
+    tcg_gen_andi_tl(addr, addr, ~0xf);
+
+    /* Lower halve */
+    tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEQ);
+    gen_store_gpr(t0, a->rt);
+
+    /* Upper halve */
+    tcg_gen_addi_i64(addr, addr, 8);
+    tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEQ);
+    gen_store_gpr_hi(t0, a->rt);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(addr);
+
+    return true;
+}
+
 /*
  *     Multiply and Divide (19 instructions)
  *     -------------------------------------
-- 
2.26.2

Re: [RFC PATCH 25/42] target/mips/tx79: Introduce LQ opcode (Load Quadword)

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> Introduce the LQ opcode (Load Quadword) and remove unreachable code.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/tx79.decode      |  8 ++++++++
>  target/mips/translate.c      | 16 ++--------------
>  target/mips/tx79_translate.c | 35 +++++++++++++++++++++++++++++++++++
>  3 files changed, 45 insertions(+), 14 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

[RFC PATCH 26/42] target/mips/tx79: Introduce SQ opcode (Store Quadword)

[Philippe Mathieu-Daudé]

Introduce the SQ opcode (Store Quadword).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tx79.decode      |  1 +
 target/mips/tx79_translate.c | 27 +++++++++++++++++++++++++++
 2 files changed, 28 insertions(+)

diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index b5396f48c2d..f1cb7ebfa3c 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -73,3 +73,4 @@ PCPYH           011100 00000 ..... ..... 11011 101001   @rt_rd
 # SPECIAL
 
 LQ              011110 ..... ..... ................     @ldst
+SQ              011111 ..... ..... ................     @ldst
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index 293efd7bd06..386bae7808b 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -411,6 +411,33 @@ static bool trans_LQ(DisasContext *ctx, arg_itype *a)
     return true;
 }
 
+static bool trans_SQ(DisasContext *ctx, arg_itype *a)
+{
+    TCGv_i64 t0 = tcg_temp_new_i64();
+    TCGv addr = tcg_temp_new();
+
+    gen_base_offset_addr(ctx, addr, a->base, a->offset);
+    /*
+     * Clear least-significant four bits of the effective
+     * address, effectively creating an aligned address.
+     */
+    tcg_gen_andi_tl(addr, addr, ~0xf);
+
+    /* Lower halve */
+    gen_load_gpr(t0, a->rt);
+    tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEQ);
+
+    /* Upper halve */
+    tcg_gen_addi_i64(addr, addr, 8);
+    gen_load_gpr_hi(t0, a->rt);
+    tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEQ);
+
+    tcg_temp_free(addr);
+    tcg_temp_free(t0);
+
+    return true;
+}
+
 /*
  *     Multiply and Divide (19 instructions)
  *     -------------------------------------
-- 
2.26.2

Re: [RFC PATCH 26/42] target/mips/tx79: Introduce SQ opcode (Store Quadword)

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> Introduce the SQ opcode (Store Quadword).
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/tx79.decode      |  1 +
>  target/mips/tx79_translate.c | 27 +++++++++++++++++++++++++++
>  2 files changed, 28 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

[RFC PATCH 27/42] target/mips/translate: Make gen_rdhwr() public

[Philippe Mathieu-Daudé]

We will use gen_rdhwr() outside of translate.c, make it public.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.h | 2 ++
 target/mips/translate.c | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/mips/translate.h b/target/mips/translate.h
index bc91ac4f53f..d2ba3524b51 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -148,6 +148,8 @@ void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1);
 bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
 bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
 
+void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel);
+
 extern TCGv cpu_gpr[32], cpu_PC;
 #if defined(TARGET_MIPS64)
 extern TCGv_i64 cpu_gpr_hi[32];
diff --git a/target/mips/translate.c b/target/mips/translate.c
index bed0489997a..c1d07a4591d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -12655,7 +12655,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
     }
 }
 
-static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
+void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
 {
     TCGv t0;
 
-- 
2.26.2

Re: [RFC PATCH 27/42] target/mips/translate: Make gen_rdhwr() public

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> We will use gen_rdhwr() outside of translate.c, make it public.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/translate.h | 2 ++
>  target/mips/translate.c | 2 +-
>  2 files changed, 3 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

[RFC PATCH 28/42] target/mips/tx79: Move RDHWR usermode kludge to trans_SQ()

[Philippe Mathieu-Daudé]

Now than SQ is properly implemented, we can move the RDHWR
kludge required to have usermode working with recent glibc.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.c      | 56 ------------------------------------
 target/mips/tx79_translate.c | 34 +++++++++++++++++++++-
 2 files changed, 33 insertions(+), 57 deletions(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index c1d07a4591d..0fa2b3bcc15 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1780,7 +1780,6 @@ enum {
 
 enum {
     MMI_OPC_CLASS_MMI = 0x1C << 26,    /* Same as OPC_SPECIAL2 */
-    MMI_OPC_SQ        = 0x1F << 26,    /* Same as OPC_SPECIAL3 */
 };
 
 /*
@@ -27330,53 +27329,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
     }
 }
 
-static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset)
-{
-    gen_reserved_instruction(ctx);    /* TODO: MMI_OPC_SQ */
-}
-
-/*
- * The TX79-specific instruction Store Quadword
- *
- * +--------+-------+-------+------------------------+
- * | 011111 |  base |   rt  |           offset       | SQ
- * +--------+-------+-------+------------------------+
- *      6       5       5                 16
- *
- * has the same opcode as the Read Hardware Register instruction
- *
- * +--------+-------+-------+-------+-------+--------+
- * | 011111 | 00000 |   rt  |   rd  | 00000 | 111011 | RDHWR
- * +--------+-------+-------+-------+-------+--------+
- *      6       5       5       5       5        6
- *
- * that is required, trapped and emulated by the Linux kernel. However, all
- * RDHWR encodings yield address error exceptions on the TX79 since the SQ
- * offset is odd. Therefore all valid SQ instructions can execute normally.
- * In user mode, QEMU must verify the upper and lower 11 bits to distinguish
- * between SQ and RDHWR, as the Linux kernel does.
- */
-static void decode_mmi_sq(CPUMIPSState *env, DisasContext *ctx)
-{
-    int base = extract32(ctx->opcode, 21, 5);
-    int rt = extract32(ctx->opcode, 16, 5);
-    int offset = extract32(ctx->opcode, 0, 16);
-
-#ifdef CONFIG_USER_ONLY
-    uint32_t op1 = MASK_SPECIAL3(ctx->opcode);
-    uint32_t op2 = extract32(ctx->opcode, 6, 5);
-
-    if (base == 0 && op2 == 0 && op1 == OPC_RDHWR) {
-        int rd = extract32(ctx->opcode, 11, 5);
-
-        gen_rdhwr(ctx, rt, rd, 0);
-        return;
-    }
-#endif
-
-    gen_mmi_sq(ctx, base, rt, offset);
-}
-
 #endif
 
 static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
@@ -27561,15 +27513,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
         }
         break;
     case OPC_SPECIAL3:
-#if defined(TARGET_MIPS64)
-        if (ctx->insn_flags & INSN_R5900) {
-            decode_mmi_sq(env, ctx);    /* MMI_OPC_SQ */
-        } else {
-            decode_opc_special3(env, ctx);
-        }
-#else
         decode_opc_special3(env, ctx);
-#endif
         break;
     case OPC_REGIMM:
         op1 = MASK_REGIMM(ctx->opcode);
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index 386bae7808b..2aa3182d21d 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -411,7 +411,7 @@ static bool trans_LQ(DisasContext *ctx, arg_itype *a)
     return true;
 }
 
-static bool trans_SQ(DisasContext *ctx, arg_itype *a)
+static bool trans_SQ_real(DisasContext *ctx, arg_itype *a)
 {
     TCGv_i64 t0 = tcg_temp_new_i64();
     TCGv addr = tcg_temp_new();
@@ -438,6 +438,38 @@ static bool trans_SQ(DisasContext *ctx, arg_itype *a)
     return true;
 }
 
+static bool trans_SQ(DisasContext *ctx, arg_itype *a)
+{
+    /*
+     * The TX79-specific instruction Store Quadword
+     *
+     * +--------+-------+-------+------------------------+
+     * | 011111 |  base |   rt  |           offset       | SQ
+     * +--------+-------+-------+------------------------+
+     *      6       5       5                 16
+     *
+     * has the same opcode as the Read Hardware Register instruction
+     *
+     * +--------+-------+-------+-------+-------+--------+
+     * | 011111 | 00000 |   rt  |   rd  | 00000 | 111011 | RDHWR
+     * +--------+-------+-------+-------+-------+--------+
+     *      6       5       5       5       5        6
+     *
+     * that is required, trapped and emulated by the Linux kernel. However, all
+     * RDHWR encodings yield address error exceptions on the TX79 since the SQ
+     * offset is odd. Therefore all valid SQ instructions can execute normally.
+     * In user mode, QEMU must verify the upper and lower 13 bits to distinguish
+     * between SQ and RDHWR, as the Linux kernel does.
+     */
+#if defined(CONFIG_USER_ONLY)
+    if (!a->base && extract32(a->offset, 0, 11) == 0b00000111011) {
+        gen_rdhwr(ctx, a->rt, extract32(ctx->opcode, 11, 5), 0);
+        return true;
+    }
+#endif
+    return trans_SQ_real(ctx, a);
+}
+
 /*
  *     Multiply and Divide (19 instructions)
  *     -------------------------------------
-- 
2.26.2

Re: [RFC PATCH 28/42] target/mips/tx79: Move RDHWR usermode kludge to trans_SQ()

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> Now than SQ is properly implemented, we can move the RDHWR
> kludge required to have usermode working with recent glibc.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/translate.c      | 56 ------------------------------------
>  target/mips/tx79_translate.c | 34 +++++++++++++++++++++-
>  2 files changed, 33 insertions(+), 57 deletions(-)
> 
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index c1d07a4591d..0fa2b3bcc15 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -1780,7 +1780,6 @@ enum {
>  
>  enum {
>      MMI_OPC_CLASS_MMI = 0x1C << 26,    /* Same as OPC_SPECIAL2 */
> -    MMI_OPC_SQ        = 0x1F << 26,    /* Same as OPC_SPECIAL3 */
>  };
>  
>  /*
> @@ -27330,53 +27329,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
>      }
>  }
>  
> -static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset)
> -{
> -    gen_reserved_instruction(ctx);    /* TODO: MMI_OPC_SQ */
> -}
> -
> -/*
> - * The TX79-specific instruction Store Quadword
> - *
> - * +--------+-------+-------+------------------------+
> - * | 011111 |  base |   rt  |           offset       | SQ
> - * +--------+-------+-------+------------------------+
> - *      6       5       5                 16
> - *
> - * has the same opcode as the Read Hardware Register instruction
> - *
> - * +--------+-------+-------+-------+-------+--------+
> - * | 011111 | 00000 |   rt  |   rd  | 00000 | 111011 | RDHWR
> - * +--------+-------+-------+-------+-------+--------+
> - *      6       5       5       5       5        6
> - *
> - * that is required, trapped and emulated by the Linux kernel. However, all
> - * RDHWR encodings yield address error exceptions on the TX79 since the SQ
> - * offset is odd. Therefore all valid SQ instructions can execute normally.
> - * In user mode, QEMU must verify the upper and lower 11 bits to distinguish
> - * between SQ and RDHWR, as the Linux kernel does.
> - */
> -static void decode_mmi_sq(CPUMIPSState *env, DisasContext *ctx)
> -{
> -    int base = extract32(ctx->opcode, 21, 5);
> -    int rt = extract32(ctx->opcode, 16, 5);
> -    int offset = extract32(ctx->opcode, 0, 16);
> -
> -#ifdef CONFIG_USER_ONLY
> -    uint32_t op1 = MASK_SPECIAL3(ctx->opcode);
> -    uint32_t op2 = extract32(ctx->opcode, 6, 5);
> -
> -    if (base == 0 && op2 == 0 && op1 == OPC_RDHWR) {
> -        int rd = extract32(ctx->opcode, 11, 5);
> -
> -        gen_rdhwr(ctx, rt, rd, 0);
> -        return;
> -    }
> -#endif
> -
> -    gen_mmi_sq(ctx, base, rt, offset);
> -}
> -
>  #endif
>  
>  static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
> @@ -27561,15 +27513,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
>          }
>          break;
>      case OPC_SPECIAL3:
> -#if defined(TARGET_MIPS64)
> -        if (ctx->insn_flags & INSN_R5900) {
> -            decode_mmi_sq(env, ctx);    /* MMI_OPC_SQ */
> -        } else {
> -            decode_opc_special3(env, ctx);
> -        }
> -#else
>          decode_opc_special3(env, ctx);
> -#endif
>          break;
>      case OPC_REGIMM:
>          op1 = MASK_REGIMM(ctx->opcode);
> diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
> index 386bae7808b..2aa3182d21d 100644
> --- a/target/mips/tx79_translate.c
> +++ b/target/mips/tx79_translate.c
> @@ -411,7 +411,7 @@ static bool trans_LQ(DisasContext *ctx, arg_itype *a)
>      return true;
>  }
>  
> -static bool trans_SQ(DisasContext *ctx, arg_itype *a)
> +static bool trans_SQ_real(DisasContext *ctx, arg_itype *a)
>  {
>      TCGv_i64 t0 = tcg_temp_new_i64();
>      TCGv addr = tcg_temp_new();
> @@ -438,6 +438,38 @@ static bool trans_SQ(DisasContext *ctx, arg_itype *a)
>      return true;
>  }
>  
> +static bool trans_SQ(DisasContext *ctx, arg_itype *a)
> +{
> +    /*
> +     * The TX79-specific instruction Store Quadword
> +     *
> +     * +--------+-------+-------+------------------------+
> +     * | 011111 |  base |   rt  |           offset       | SQ
> +     * +--------+-------+-------+------------------------+
> +     *      6       5       5                 16
> +     *
> +     * has the same opcode as the Read Hardware Register instruction
> +     *
> +     * +--------+-------+-------+-------+-------+--------+
> +     * | 011111 | 00000 |   rt  |   rd  | 00000 | 111011 | RDHWR
> +     * +--------+-------+-------+-------+-------+--------+
> +     *      6       5       5       5       5        6
> +     *
> +     * that is required, trapped and emulated by the Linux kernel. However, all
> +     * RDHWR encodings yield address error exceptions on the TX79 since the SQ
> +     * offset is odd.

Not that it's odd (the final address is masked, remember), but that it a store
to an address in the zero page.

> Therefore all valid SQ instructions can execute normally.
> +     * In user mode, QEMU must verify the upper and lower 13 bits to distinguish

11 bits.

> +     * between SQ and RDHWR, as the Linux kernel does.
> +     */
> +#if defined(CONFIG_USER_ONLY)
> +    if (!a->base && extract32(a->offset, 0, 11) == 0b00000111011) {
> +        gen_rdhwr(ctx, a->rt, extract32(ctx->opcode, 11, 5), 0);
> +        return true;
> +    }
> +#endif

I would do this as

{
  RDHWR_user  011111 00000 ..... ..... 00000 111011   @rd_rt
  SQ          011111 ..... ..... ................     @ldst
}

static bool trans_RDHWR_user(DisasContext *ctx, arg_rtype *a)
{
#ifdef CONFIG_USER_ONLY
    gen_rdhwr(ctx, a->rt, a->rd, 0);
    return true;
#else
    return false;
#endif
}


r~

Re: [RFC PATCH 28/42] target/mips/tx79: Move RDHWR usermode kludge to trans_SQ()

[Fredrik Noring]

On Mon, Feb 15, 2021 at 01:01:52PM -0800, Richard Henderson wrote:
> On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> > +    /*
> > +     * The TX79-specific instruction Store Quadword
> > +     *
> > +     * +--------+-------+-------+------------------------+
> > +     * | 011111 |  base |   rt  |           offset       | SQ
> > +     * +--------+-------+-------+------------------------+
> > +     *      6       5       5                 16
> > +     *
> > +     * has the same opcode as the Read Hardware Register instruction
> > +     *
> > +     * +--------+-------+-------+-------+-------+--------+
> > +     * | 011111 | 00000 |   rt  |   rd  | 00000 | 111011 | RDHWR
> > +     * +--------+-------+-------+-------+-------+--------+
> > +     *      6       5       5       5       5        6
> > +     *
> > +     * that is required, trapped and emulated by the Linux kernel. However, all
> > +     * RDHWR encodings yield address error exceptions on the TX79 since the SQ
> > +     * offset is odd.
> 
> Not that it's odd (the final address is masked, remember), but that it a store
> to an address in the zero page.

The address always resolves to 0xffffe83b (then masked) in 32-bit KSEG2,
because rt is always $3 and rd is always $29 so -6085(zero), hence the
last page (which is much better) rather than the first, as Maciej
discovered:

https://patchwork.kernel.org/comment/23824173/

Other possible RDHWR encodings are no longer used, and can therefore be
ignored and revert to SQ:

https://patchwork.kernel.org/comment/23842167/

Notice also the oddity of 32-bit R5900 addresses that doesn't matter here
but has implications for n32 and system emulation.

> I would do this as
> 
> {
>   RDHWR_user  011111 00000 ..... ..... 00000 111011   @rd_rt
>   SQ          011111 ..... ..... ................     @ldst
> }

Both rd and rt have fixed values, as mentioned.

For reference, RDHWR is currently done like this in the Linux kernel:

	if (IS_ENABLED(CONFIG_CPU_R5900)) {
		/*
		 * On the R5900, a valid RDHWR instruction
		 *
		 *     +--------+-------+----+----+-------+--------+
		 *     | 011111 | 00000 | rt | rd | 00000 | 111011 |
		 *     +--------+-------+----+----+-------+--------+
		 *          6       5      5    5     5        6
		 *
		 * having rt $3 (v1) and rd $29 (MIPS_HWR_ULR) is
		 * interpreted as the R5900 specific SQ instruction
		 *
		 *     +--------+-------+----+---------------------+
		 *     | 011111 |  base | rt |        offset       |
		 *     +--------+-------+----+---------------------+
		 *          6       5      5            16
		 *
		 * with
		 *
		 *     sq v1,-6085(zero)
		 *
		 * that asserts an address exception since -6085(zero)
		 * always resolves to 0xffffe83b in 32-bit KSEG2.
		 *
		 * Other legacy values of rd, such as MIPS_HWR_CPUNUM,
		 * are ignored.
		 */
		if (insn.r_format.func == rdhwr_op &&
		    insn.r_format.rd == MIPS_HWR_ULR &&
		    insn.r_format.rt == 3 &&
		    insn.r_format.rs == 0 &&
		    insn.r_format.re == 0) {
			if (compute_return_epc(regs) < 0 ||
			    simulate_rdhwr(regs, insn.r_format.rd,
					   insn.r_format.rt) < 0)
				goto sigill;
			return;
		}
		goto sigbus;
	} else ...

Fredrik

Re: [RFC PATCH 28/42] target/mips/tx79: Move RDHWR usermode kludge to trans_SQ()

[Maciej W. Rozycki]

On Tue, 16 Feb 2021, Fredrik Noring wrote:

> > Not that it's odd (the final address is masked, remember), but that it a store
> > to an address in the zero page.
> 
> The address always resolves to 0xffffe83b (then masked) in 32-bit KSEG2,
> because rt is always $3 and rd is always $29 so -6085(zero), hence the
> last page (which is much better) rather than the first, as Maciej
> discovered:
> 
> https://patchwork.kernel.org/comment/23824173/
> 
> Other possible RDHWR encodings are no longer used, and can therefore be
> ignored and revert to SQ:
> 
> https://patchwork.kernel.org/comment/23842167/

 Or rather were never used in the general case (I can't rule out someone 
using that stuff for something, but I wouldn't call it supported; I used 
some of it internally while evaluating the speed of RDHWR emulation before 
the use of $3 or indeed RDHWR was settled in the TLS psABI, though the 
actual code that ultimately went into Linux was developed independently).

> > I would do this as
> > 
> > {
> >   RDHWR_user  011111 00000 ..... ..... 00000 111011   @rd_rt
> >   SQ          011111 ..... ..... ................     @ldst
> > }
> 
> Both rd and rt have fixed values, as mentioned.

 I would suggest actually supporting variable `rt', see below.  Would it 
be a problem?

> For reference, RDHWR is currently done like this in the Linux kernel:
> 
> 	if (IS_ENABLED(CONFIG_CPU_R5900)) {
> 		/*
> 		 * On the R5900, a valid RDHWR instruction
> 		 *
> 		 *     +--------+-------+----+----+-------+--------+
> 		 *     | 011111 | 00000 | rt | rd | 00000 | 111011 |
> 		 *     +--------+-------+----+----+-------+--------+
> 		 *          6       5      5    5     5        6
> 		 *
> 		 * having rt $3 (v1) and rd $29 (MIPS_HWR_ULR) is
> 		 * interpreted as the R5900 specific SQ instruction
> 		 *
> 		 *     +--------+-------+----+---------------------+
> 		 *     | 011111 |  base | rt |        offset       |
> 		 *     +--------+-------+----+---------------------+
> 		 *          6       5      5            16
> 		 *
> 		 * with
> 		 *
> 		 *     sq v1,-6085(zero)
> 		 *
> 		 * that asserts an address exception since -6085(zero)
> 		 * always resolves to 0xffffe83b in 32-bit KSEG2.
> 		 *
> 		 * Other legacy values of rd, such as MIPS_HWR_CPUNUM,
> 		 * are ignored.
> 		 */
> 		if (insn.r_format.func == rdhwr_op &&
> 		    insn.r_format.rd == MIPS_HWR_ULR &&
> 		    insn.r_format.rt == 3 &&

 I suggest leaving the `rt' check out for consistency, as changing the 
register to read the value of UserLocal into from psABI-mandated $3 does 
not cause any issue with the R5900 (the `rt' field overlaps between both 
machine instructions, so the encoding placed there does not affect the 
KSEG2 access trap caused) and those encodings are also emulated in the 
slow path for other legacy ISA CPUs:

	case MIPS_HWR_ULR:		/* Read UserLocal register */
		regs->regs[rt] = ti->tp_value;
		return 0;


 So e.g. `rdhwr $25, $29' is interpreted as `sq $25,-6085($0)' by the 
R5900 => no issue, it still traps.

 I know I have previously written that we can ignore `rt' encodings other 
than $3, but they are harmless and handling them saves a couple of machine 
instructions needed to make the check, so I think while we can, we do not 
actually have to ignore them.

> 		    insn.r_format.rs == 0 &&
> 		    insn.r_format.re == 0) {
> 			if (compute_return_epc(regs) < 0 ||
> 			    simulate_rdhwr(regs, insn.r_format.rd,
> 					   insn.r_format.rt) < 0)
> 				goto sigill;
> 			return;
> 		}
> 		goto sigbus;
> 	} else ...

 Code continuation quoted left for reference.

  Maciej

Re: [RFC PATCH 28/42] target/mips/tx79: Move RDHWR usermode kludge to trans_SQ()

[Fredrik Noring]

On Tue, Feb 16, 2021 at 01:21:34PM +0100, Maciej W. Rozycki wrote:
> > > I would do this as
> > > 
> > > {
> > >   RDHWR_user  011111 00000 ..... ..... 00000 111011   @rd_rt
> > >   SQ          011111 ..... ..... ................     @ldst
> > > }
> > 
> > Both rd and rt have fixed values, as mentioned.
> 
>  I would suggest actually supporting variable `rt', see below.  Would it 
> be a problem?

No problem on my part, I'll update the kernel code!

Fredrik

[RFC PATCH 29/42] linux-user/mips64: Support the n32 ABI for the R5900

[Philippe Mathieu-Daudé]

From: Fredrik Noring <noring@nocrew.org>

Recognise the R5900, which reports itself as MIPS III, as a 64-bit CPU
supporting the n32 ABI.

Signed-off-by: Fredrik Noring <noring@nocrew.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <5bea109f0c140da6a821aa7f9705d4b3717e86dc.1541701393.git.noring@nocrew.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 linux-user/mips64/target_elf.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/linux-user/mips64/target_elf.h b/linux-user/mips64/target_elf.h
index ec55d8542ae..5f2f2df29f7 100644
--- a/linux-user/mips64/target_elf.h
+++ b/linux-user/mips64/target_elf.h
@@ -12,6 +12,9 @@ static inline const char *cpu_get_model(uint32_t eflags)
     if ((eflags & EF_MIPS_ARCH) == EF_MIPS_ARCH_64R6) {
         return "I6400";
     }
+    if ((eflags & EF_MIPS_MACH) == EF_MIPS_MACH_5900) {
+        return "R5900";
+    }
     return "5KEf";
 }
 #endif
-- 
2.26.2

Re: [RFC PATCH 29/42] linux-user/mips64: Support the n32 ABI for the R5900

[Richard Henderson]

On 2/14/21 9:58 AM, Philippe Mathieu-Daudé wrote:
> From: Fredrik Noring <noring@nocrew.org>
> 
> Recognise the R5900, which reports itself as MIPS III, as a 64-bit CPU
> supporting the n32 ABI.
> 
> Signed-off-by: Fredrik Noring <noring@nocrew.org>
> Reviewed-by: Laurent Vivier <laurent@vivier.eu>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Message-Id: <5bea109f0c140da6a821aa7f9705d4b3717e86dc.1541701393.git.noring@nocrew.org>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  linux-user/mips64/target_elf.h | 3 +++
>  1 file changed, 3 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[RFC PATCH 30/42] target/mips: Reintroduce the R5900 CPU

[Philippe Mathieu-Daudé]

Now that we have the minimum prerequisites to support the
R5900 CPU, we can reintroduce it.

While we are reverting commit 823f2897bdd ("Disable R5900
support"), we effectively cherry-pick commit ed4f49ba9bb
("target/mips: Define the R5900 CPU").

This reverts commit 823f2897bdd78185f3ba33292a25105ba8bad1b5.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/cpu-defs.c.inc | 59 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index e03b2a998cd..1a73b5409f0 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -411,6 +411,65 @@ const mips_def_t mips_defs[] =
         .insn_flags = CPU_MIPS32R5,
         .mmu_type = MMU_TYPE_R4000,
     },
+    {
+        /*
+         * The Toshiba TX System RISC TX79 Core Architecture manual
+         *
+         * https://wiki.qemu.org/File:C790.pdf
+         *
+         * describes the C790 processor that is a follow-up to the R5900.
+         * There are a few notable differences in that the R5900 FPU
+         *
+         * - is not IEEE 754-1985 compliant,
+         * - does not implement double format, and
+         * - its machine code is nonstandard.
+         */
+        .name = "R5900",
+        .CP0_PRid = 0x00002E00,
+        /* No L2 cache, icache size 32k, dcache size 32k, uncached coherency. */
+        .CP0_Config0 = (0x3 << 9) | (0x3 << 6) | (0x2 << CP0C0_K0),
+        .CP0_Status_rw_bitmask = 0xF4C79C1F,
+#ifdef CONFIG_USER_ONLY
+        /*
+         * R5900 hardware traps to the Linux kernel for IEEE 754-1985 and LL/SC
+         * emulation. For user only, QEMU is the kernel, so we emulate the traps
+         * by simply emulating the instructions directly.
+         *
+         * Note: Config1 is only used internally, the R5900 has only Config0.
+         */
+        .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
+        .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
+        .CP0_LLAddr_shift = 4,
+        .CP1_fcr0 = (0x38 << FCR0_PRID) | (0x0 << FCR0_REV),
+        .CP1_fcr31 = 0,
+        .CP1_fcr31_rw_bitmask = 0x0183FFFF,
+#else
+        /*
+         * The R5900 COP1 FPU implements single-precision floating-point
+         * operations but is not entirely IEEE 754-1985 compatible. In
+         * particular,
+         *
+         * - NaN (not a number) and +/- infinities are not supported;
+         * - exception mechanisms are not fully supported;
+         * - denormalized numbers are not supported;
+         * - rounding towards nearest and +/- infinities are not supported;
+         * - computed results usually differs in the least significant bit;
+         * - saturations can differ more than the least significant bit.
+         *
+         * Since only rounding towards zero is supported, the two least
+         * significant bits of FCR31 are hardwired to 01.
+         *
+         * FPU emulation is disabled here until it is implemented.
+         *
+         * Note: Config1 is only used internally, the R5900 has only Config0.
+         */
+        .CP0_Config1 = (47 << CP0C1_MMU),
+#endif /* !CONFIG_USER_ONLY */
+        .SEGBITS = 32,
+        .PABITS = 32,
+        .insn_flags = CPU_MIPS3 | INSN_R5900 | ASE_MMI,
+        .mmu_type = MMU_TYPE_R4000,
+    },
     {
         /* A generic CPU supporting MIPS32 Release 6 ISA.
            FIXME: Support IEEE 754-2008 FP.
-- 
2.26.2

Re: [RFC PATCH 30/42] target/mips: Reintroduce the R5900 CPU

[Richard Henderson]

On 2/14/21 9:59 AM, Philippe Mathieu-Daudé wrote:
> Now that we have the minimum prerequisites to support the
> R5900 CPU, we can reintroduce it.
> 
> While we are reverting commit 823f2897bdd ("Disable R5900
> support"), we effectively cherry-pick commit ed4f49ba9bb
> ("target/mips: Define the R5900 CPU").
> 
> This reverts commit 823f2897bdd78185f3ba33292a25105ba8bad1b5.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/cpu-defs.c.inc | 59 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 59 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[RFC PATCH 31/42] default-configs: Support o32 ABI with R5900 64-bit MIPS CPU

[Philippe Mathieu-Daudé]

MIPS o32 ABI on 64-bit CPUs looks like a ILP32-on-64bit data
model, allowing 64-bit arithmetic and data movement instructions.

Since this ABI seems to have only ever been used for the
development of the PS2 with the "Sony Linux Toolkit for
Playstation 2" targetting the R5900 CPU (little-endian),
we name this user-mode target 'r5900o32el'.

Inspired-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2: Rename qemu-mips64o32el -> qemu-r5900o32el (Fredrik)
---
 docs/user/main.rst                                | 3 +++
 default-configs/targets/r5900o32el-linux-user.mak | 7 +++++++
 2 files changed, 10 insertions(+)
 create mode 100644 default-configs/targets/r5900o32el-linux-user.mak

diff --git a/docs/user/main.rst b/docs/user/main.rst
index 8dfe232a3af..405acb8155e 100644
--- a/docs/user/main.rst
+++ b/docs/user/main.rst
@@ -221,6 +221,9 @@ Other binaries
    * ``qemu-mipsn32el`` executes 32-bit little endian MIPS binaries (MIPS N32
      ABI).
 
+   * ``qemu-r5900o32el`` executes 64-bit little endian MIPS R5900 binaries (MIPS
+     O32 ABI).
+
 -  user mode (NiosII)
 
    * ``qemu-nios2`` TODO.
diff --git a/default-configs/targets/r5900o32el-linux-user.mak b/default-configs/targets/r5900o32el-linux-user.mak
new file mode 100644
index 00000000000..ecd57ff949f
--- /dev/null
+++ b/default-configs/targets/r5900o32el-linux-user.mak
@@ -0,0 +1,7 @@
+TARGET_ARCH=mips64
+TARGET_BASE_ARCH=mips
+TARGET_ABI_MIPSO32=y
+TARGET_ABI32=y
+TARGET_SYSTBL_ABI=o32
+TARGET_SYSTBL=../mips/syscall_o32.tbl
+TARGET_ALIGNED_ONLY=y
-- 
2.26.2

Re: [RFC PATCH 31/42] default-configs: Support o32 ABI with R5900 64-bit MIPS CPU

[Richard Henderson]

On 2/14/21 9:59 AM, Philippe Mathieu-Daudé wrote:
> MIPS o32 ABI on 64-bit CPUs looks like a ILP32-on-64bit data
> model, allowing 64-bit arithmetic and data movement instructions.
> 
> Since this ABI seems to have only ever been used for the
> development of the PS2 with the "Sony Linux Toolkit for
> Playstation 2" targetting the R5900 CPU (little-endian),
> we name this user-mode target 'r5900o32el'.
> 
> Inspired-by: Richard Henderson <rth@twiddle.net>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> v2: Rename qemu-mips64o32el -> qemu-r5900o32el (Fredrik)
> ---
>  docs/user/main.rst                                | 3 +++
>  default-configs/targets/r5900o32el-linux-user.mak | 7 +++++++
>  2 files changed, 10 insertions(+)
>  create mode 100644 default-configs/targets/r5900o32el-linux-user.mak

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

[RFC PATCH 32/42] docker: Add gentoo-mipsr5900el-cross image

[Philippe Mathieu-Daudé]

Add a Docker image providing cross toolchain for the MIPS R5900 CPU
(used on the Sony PS2).

This image is based on Gentoo and the toolchain is built using crossdev.

Recipe from:
  https://lists.gnu.org/archive/html/qemu-devel/2018-09/msg03944.html

Suggested-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 tests/docker/Makefile.include                 |  3 ++
 .../gentoo-mipsr5900el-cross.docker           | 35 +++++++++++++++++++
 .../crossdev.conf                             |  5 +++
 3 files changed, 43 insertions(+)
 create mode 100644 tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker
 create mode 100644 tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker.d/crossdev.conf

diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include
index 93b29ad823e..3d6306c7728 100644
--- a/tests/docker/Makefile.include
+++ b/tests/docker/Makefile.include
@@ -146,6 +146,9 @@ docker-image-debian-riscv64-cross: docker-image-debian10
 docker-image-debian-s390x-cross: docker-image-debian10
 docker-image-debian-sh4-cross: docker-image-debian10
 docker-image-debian-sparc64-cross: docker-image-debian10
+docker-image-gentoo-mipsr5900el-cross: EXTRA_FILES:=$(addprefix \
+			$(SRC_PATH)/tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker.d/,\
+				crossdev.conf)
 
 docker-image-travis: NOUSER=1
 
diff --git a/tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker b/tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker
new file mode 100644
index 00000000000..88ada20623d
--- /dev/null
+++ b/tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker
@@ -0,0 +1,35 @@
+#
+# Docker mipsel (r5900) cross-compiler target
+#
+# Using multi-stage builds, this image requires docker-17.05.0 or later.
+# (See: https://github.com/gentoo/gentoo-docker-images)
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# name the portage image
+FROM gentoo/portage:20201121 as portage
+
+# image is based on stage3-amd64
+FROM gentoo/stage3:latest
+
+# copy the entire portage volume in
+COPY --from=portage /var/db/repos/gentoo /var/db/repos/gentoo
+
+MAINTAINER Philippe Mathieu-Daudé <f4bug@amsat.org>
+
+# set CROSSDEV_OVERLAY to /usr/local/portage-crossdev
+RUN mkdir -p /usr/local/portage-crossdev/{profiles,metadata} && \
+    echo 'crossdev' > /usr/local/portage-crossdev/profiles/repo_name && \
+    echo 'masters = gentoo' > /usr/local/portage-crossdev/metadata/layout.conf && \
+    chown -R portage:portage /usr/local/portage-crossdev && \
+    mkdir -p /etc/portage/repos.conf
+ADD crossdev.conf /etc/portage/repos.conf/crossdev.conf
+
+RUN emerge -qv \
+        dev-vcs/git ">=dev-libs/glib-2.0" \
+        sys-devel/crossdev \
+        sys-libs/zlib dev-lang/python
+
+RUN crossdev -s4 -t mipsr5900el-unknown-linux-gnu
+
+ENV QEMU_CONFIGURE_OPTS --cross-prefix=mipsr5900el-unknown-linux-gnu-
diff --git a/tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker.d/crossdev.conf b/tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker.d/crossdev.conf
new file mode 100644
index 00000000000..b8fa368c1c3
--- /dev/null
+++ b/tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker.d/crossdev.conf
@@ -0,0 +1,5 @@
+[crossdev]
+location = /usr/local/portage-crossdev
+priority = 10
+masters = gentoo
+auto-sync = no
-- 
2.26.2

Re: [RFC PATCH 32/42] docker: Add gentoo-mipsr5900el-cross image

[Daniel P. Berrangé]

On Sun, Feb 14, 2021 at 06:59:02PM +0100, Philippe Mathieu-Daudé wrote:
> Add a Docker image providing cross toolchain for the MIPS R5900 CPU
> (used on the Sony PS2).
> 
> This image is based on Gentoo and the toolchain is built using crossdev.

Is there any way we can do this with a distro that isn't Gentoo
so that we can get a container build that is fast enough to be
useful for CI ?

> 
> Recipe from:
>   https://lists.gnu.org/archive/html/qemu-devel/2018-09/msg03944.html
> 
> Suggested-by: Fredrik Noring <noring@nocrew.org>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  tests/docker/Makefile.include                 |  3 ++
>  .../gentoo-mipsr5900el-cross.docker           | 35 +++++++++++++++++++
>  .../crossdev.conf                             |  5 +++
>  3 files changed, 43 insertions(+)
>  create mode 100644 tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker
>  create mode 100644 tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker.d/crossdev.conf
> 
> diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include
> index 93b29ad823e..3d6306c7728 100644
> --- a/tests/docker/Makefile.include
> +++ b/tests/docker/Makefile.include
> @@ -146,6 +146,9 @@ docker-image-debian-riscv64-cross: docker-image-debian10
>  docker-image-debian-s390x-cross: docker-image-debian10
>  docker-image-debian-sh4-cross: docker-image-debian10
>  docker-image-debian-sparc64-cross: docker-image-debian10
> +docker-image-gentoo-mipsr5900el-cross: EXTRA_FILES:=$(addprefix \
> +			$(SRC_PATH)/tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker.d/,\
> +				crossdev.conf)
>  
>  docker-image-travis: NOUSER=1
>  
> diff --git a/tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker b/tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker
> new file mode 100644
> index 00000000000..88ada20623d
> --- /dev/null
> +++ b/tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker
> @@ -0,0 +1,35 @@
> +#
> +# Docker mipsel (r5900) cross-compiler target
> +#
> +# Using multi-stage builds, this image requires docker-17.05.0 or later.
> +# (See: https://github.com/gentoo/gentoo-docker-images)
> +#
> +# SPDX-License-Identifier: GPL-2.0-or-later
> +
> +# name the portage image
> +FROM gentoo/portage:20201121 as portage
> +
> +# image is based on stage3-amd64
> +FROM gentoo/stage3:latest
> +
> +# copy the entire portage volume in
> +COPY --from=portage /var/db/repos/gentoo /var/db/repos/gentoo
> +
> +MAINTAINER Philippe Mathieu-Daudé <f4bug@amsat.org>
> +
> +# set CROSSDEV_OVERLAY to /usr/local/portage-crossdev
> +RUN mkdir -p /usr/local/portage-crossdev/{profiles,metadata} && \
> +    echo 'crossdev' > /usr/local/portage-crossdev/profiles/repo_name && \
> +    echo 'masters = gentoo' > /usr/local/portage-crossdev/metadata/layout.conf && \
> +    chown -R portage:portage /usr/local/portage-crossdev && \
> +    mkdir -p /etc/portage/repos.conf
> +ADD crossdev.conf /etc/portage/repos.conf/crossdev.conf
> +
> +RUN emerge -qv \
> +        dev-vcs/git ">=dev-libs/glib-2.0" \
> +        sys-devel/crossdev \
> +        sys-libs/zlib dev-lang/python
> +
> +RUN crossdev -s4 -t mipsr5900el-unknown-linux-gnu
> +
> +ENV QEMU_CONFIGURE_OPTS --cross-prefix=mipsr5900el-unknown-linux-gnu-
> diff --git a/tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker.d/crossdev.conf b/tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker.d/crossdev.conf
> new file mode 100644
> index 00000000000..b8fa368c1c3
> --- /dev/null
> +++ b/tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker.d/crossdev.conf
> @@ -0,0 +1,5 @@
> +[crossdev]
> +location = /usr/local/portage-crossdev
> +priority = 10
> +masters = gentoo
> +auto-sync = no
> -- 
> 2.26.2
> 
> 

Regards,
Daniel
-- 
|: https://berrange.com      -o-    https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org         -o-            https://fstop138.berrange.com :|
|: https://entangle-photo.org    -o-    https://www.instagram.com/dberrange :|

Re: [RFC PATCH 32/42] docker: Add gentoo-mipsr5900el-cross image

[Fredrik Noring]

On Mon, Feb 15, 2021 at 11:59:57AM +0000, Daniel P. Berrangé wrote:
> On Sun, Feb 14, 2021 at 06:59:02PM +0100, Philippe Mathieu-Daudé wrote:
> > Add a Docker image providing cross toolchain for the MIPS R5900 CPU
> > (used on the Sony PS2).
> > 
> > This image is based on Gentoo and the toolchain is built using crossdev.
> 
> Is there any way we can do this with a distro that isn't Gentoo
> so that we can get a container build that is fast enough to be
> useful for CI ?

Is it necessary to rebuild the toolchain every time? Also, perhaps a
generic MIPS suite can be used; it shouldn't to necessary to have one
specifically made for the R5900 (except libc, if needed, I guess).

As an alternative, TobiX at Github made an R5900 Docker image last year
<https://github.com/frno7/linux/issues/33#issuecomment-632284209>,
perhaps it could be useful somehow?

Fredrik

Re: [RFC PATCH 32/42] docker: Add gentoo-mipsr5900el-cross image

[Philippe Mathieu-Daudé]

On 2/15/21 2:45 PM, Fredrik Noring wrote:
> On Mon, Feb 15, 2021 at 11:59:57AM +0000, Daniel P. Berrangé wrote:
>> On Sun, Feb 14, 2021 at 06:59:02PM +0100, Philippe Mathieu-Daudé wrote:
>>> Add a Docker image providing cross toolchain for the MIPS R5900 CPU
>>> (used on the Sony PS2).
>>>
>>> This image is based on Gentoo and the toolchain is built using crossdev.
>>
>> Is there any way we can do this with a distro that isn't Gentoo
>> so that we can get a container build that is fast enough to be
>> useful for CI ?
> 
> Is it necessary to rebuild the toolchain every time?

No.

> Also, perhaps a
> generic MIPS suite can be used; it shouldn't to necessary to have one
> specifically made for the R5900 (except libc, if needed, I guess).

We want it to build TCG tests. If we can link them, that should be OK.

> As an alternative, TobiX at Github made an R5900 Docker image last year
> <https://github.com/frno7/linux/issues/33#issuecomment-632284209>,
> perhaps it could be useful somehow?

Thanks, I'll have a look.

Regards,

Phil.

Re: [RFC PATCH 32/42] docker: Add gentoo-mipsr5900el-cross image

[Philippe Mathieu-Daudé]

On 2/20/21 9:01 PM, Philippe Mathieu-Daudé wrote:
> On 2/15/21 2:45 PM, Fredrik Noring wrote:
>> On Mon, Feb 15, 2021 at 11:59:57AM +0000, Daniel P. Berrangé wrote:
>>> On Sun, Feb 14, 2021 at 06:59:02PM +0100, Philippe Mathieu-Daudé wrote:
>>>> Add a Docker image providing cross toolchain for the MIPS R5900 CPU
>>>> (used on the Sony PS2).
>>>>
>>>> This image is based on Gentoo and the toolchain is built using crossdev.
>>>
>>> Is there any way we can do this with a distro that isn't Gentoo
>>> so that we can get a container build that is fast enough to be
>>> useful for CI ?

Using the Debian cross image I get:

/home/phil/source/qemu/tests/docker/docker.py --engine auto cc --cc
mips64el-linux-gnuabi64-gcc -i qemu/debian-mips64el-cross -s
/home/phil/source/qemu --   -Wall -Werror -O0 -g -fno-strict-aliasing
-mabi=n32 -march=r5900
/home/phil/source/qemu/tests/tcg/mips/test-r5900-dmult.c -o
test-r5900-dmult  -static
cc1: error: unsupported combination: -march=r5900 -mhard-float
-mdouble-float

No clue what is setting '-mhard-float -mdouble-float' yet.

>>
>> Is it necessary to rebuild the toolchain every time?
> 
> No.
> 
>> Also, perhaps a
>> generic MIPS suite can be used; it shouldn't to necessary to have one
>> specifically made for the R5900 (except libc, if needed, I guess).
> 
> We want it to build TCG tests. If we can link them, that should be OK.
> 
>> As an alternative, TobiX at Github made an R5900 Docker image last year
>> <https://github.com/frno7/linux/issues/33#issuecomment-632284209>,
>> perhaps it could be useful somehow?
> 
> Thanks, I'll have a look.
> 
> Regards,
> 
> Phil.
> 

Re: [RFC PATCH 32/42] docker: Add gentoo-mipsr5900el-cross image

[Maciej W. Rozycki]

On Fri, 12 Mar 2021, Philippe Mathieu-Daudé wrote:

> >>> Is there any way we can do this with a distro that isn't Gentoo
> >>> so that we can get a container build that is fast enough to be
> >>> useful for CI ?
> 
> Using the Debian cross image I get:
> 
> /home/phil/source/qemu/tests/docker/docker.py --engine auto cc --cc
> mips64el-linux-gnuabi64-gcc -i qemu/debian-mips64el-cross -s
> /home/phil/source/qemu --   -Wall -Werror -O0 -g -fno-strict-aliasing
> -mabi=n32 -march=r5900
> /home/phil/source/qemu/tests/tcg/mips/test-r5900-dmult.c -o
> test-r5900-dmult  -static
> cc1: error: unsupported combination: -march=r5900 -mhard-float
> -mdouble-float
> 
> No clue what is setting '-mhard-float -mdouble-float' yet.

 The R5900 has an FPU that only supports the single floating-point format.  
It's also not an IEEE 754 format.  The Linux kernel ABI does support the 
double and also the single floating-point format, both compliant with IEEE 
754.

 In the absence of a suitable FPU emulation code included with the kernel 
will handle the missing instructions (you can use the `nofpu' kernel 
parameter to force that in the presence of an FPU too).  Beware however 
that a recent change to the Linux kernel made FPU emulation code optional 
to suit some deeply embedded applications known never to use FPU machine 
instructions.

 NB the presence of emulation is always required for MIPS ISA compliance 
if FPU machine instructions are ever to be used in a given application, 
because operations are allowed to trap regardless and rely on emulation.

 I don't know what you are trying to achieve, but your two options to 
choose from are:

1. Build for the soft-float ABI (`-msoft-float') where any FP calculations 
   are compiled such as to be made by the CPU using integer arithmetic.

2. Build for a generic MIPS ISA, for the R5900/n32 that would be MIPS III
   (`-march=mips3'), and rely on the kernel FPU emulation.  Note that some 
   integer MIPS III operations are missing too from the R5900 and have to 
   be emulated by the kernel for MIPS/Linux n32 psABI compliance (an 
   implementation can be pinched from an old libgcc version that was still 
   under GNU GPLv2 or another algorithm reused, e.g. my `__div64_32' piece
   easily adapted).

 HTH,

  Maciej

Re: [RFC PATCH 32/42] docker: Add gentoo-mipsr5900el-cross image

[Philippe Mathieu-Daudé]

Hi Maciej,

On 3/12/21 6:05 PM, Maciej W. Rozycki wrote:
> On Fri, 12 Mar 2021, Philippe Mathieu-Daudé wrote:
> 
>>>>> Is there any way we can do this with a distro that isn't Gentoo
>>>>> so that we can get a container build that is fast enough to be
>>>>> useful for CI ?
>>
>> Using the Debian cross image I get:
>>
>> /home/phil/source/qemu/tests/docker/docker.py --engine auto cc --cc
>> mips64el-linux-gnuabi64-gcc -i qemu/debian-mips64el-cross -s
>> /home/phil/source/qemu --   -Wall -Werror -O0 -g -fno-strict-aliasing
>> -mabi=n32 -march=r5900
>> /home/phil/source/qemu/tests/tcg/mips/test-r5900-dmult.c -o
>> test-r5900-dmult  -static
>> cc1: error: unsupported combination: -march=r5900 -mhard-float
>> -mdouble-float
>>
>> No clue what is setting '-mhard-float -mdouble-float' yet.
> 
>  The R5900 has an FPU that only supports the single floating-point format.  
> It's also not an IEEE 754 format.  The Linux kernel ABI does support the 
> double and also the single floating-point format, both compliant with IEEE 
> 754.
> 
>  In the absence of a suitable FPU emulation code included with the kernel 
> will handle the missing instructions (you can use the `nofpu' kernel 
> parameter to force that in the presence of an FPU too).  Beware however 
> that a recent change to the Linux kernel made FPU emulation code optional 
> to suit some deeply embedded applications known never to use FPU machine 
> instructions.
> 
>  NB the presence of emulation is always required for MIPS ISA compliance 
> if FPU machine instructions are ever to be used in a given application, 
> because operations are allowed to trap regardless and rely on emulation.
> 
>  I don't know what you are trying to achieve,

The previous maintainer let the QEMU MIPS codebase with the R5900 code
unreachable. I'm trying to see if I can get a closure on Fredrik work
before removing it, because there is no point in maintaining unreachable
code.

QEMU uses Docker images of distributions to cross-compile its tests.

Currently all Linux cross-tests are built using Debian based images.
Daniel asked me to see if I can use our current Debian based image
to build the r5900 tests, instead of adding yet another one (based
on Gentoo).

> but your two options to 
> choose from are:
> 
> 1. Build for the soft-float ABI (`-msoft-float') where any FP calculations 
>    are compiled such as to be made by the CPU using integer arithmetic.

With the Debian toolchain I get:

/usr/include/stdio.h:27:10: fatal error: bits/libc-header-start.h: No
such file or directory
 #include <bits/libc-header-start.h>
          ^~~~~~~~~~~~~~~~~~~~~~~~~~

> 2. Build for a generic MIPS ISA, for the R5900/n32 that would be MIPS III
>    (`-march=mips3'), and rely on the kernel FPU emulation.

Shouldn't -march=r5900 imply -march=mips3?

>  Note that some 
>    integer MIPS III operations are missing too from the R5900 and have to 
>    be emulated by the kernel for MIPS/Linux n32 psABI compliance (an 
>    implementation can be pinched from an old libgcc version that was still 
>    under GNU GPLv2 or another algorithm reused, e.g. my `__div64_32' piece
>    easily adapted).

Regards,

Phil.

Re: [RFC PATCH 32/42] docker: Add gentoo-mipsr5900el-cross image

[Maciej W. Rozycki]

On Fri, 12 Mar 2021, Philippe Mathieu-Daudé wrote:

> > but your two options to 
> > choose from are:
> > 
> > 1. Build for the soft-float ABI (`-msoft-float') where any FP calculations 
> >    are compiled such as to be made by the CPU using integer arithmetic.
> 
> With the Debian toolchain I get:
> 
> /usr/include/stdio.h:27:10: fatal error: bits/libc-header-start.h: No
> such file or directory
>  #include <bits/libc-header-start.h>
>           ^~~~~~~~~~~~~~~~~~~~~~~~~~

 You need to have a soft-float multilib available.  You can use:

$ gcc -print-multi-lib

to see what multilibs are available.  You'd have to have one that includes 
`-msoft-float' and `-mabi=n32' both at a time.  If there's no such one, 
then you'll have to build your own cross-compiler (including soft-float 
libc).

> > 2. Build for a generic MIPS ISA, for the R5900/n32 that would be MIPS III
> >    (`-march=mips3'), and rely on the kernel FPU emulation.
> 
> Shouldn't -march=r5900 imply -march=mips3?

 It does:

MIPS_CPU ("r5900", PROCESSOR_R5900, 3, 0)

however it is a distinct architecture owing to the differences from plain 
MIPS III ISA, and obviously the compiler and the assembler both know that.

  Maciej

Re: [RFC PATCH 32/42] docker: Add gentoo-mipsr5900el-cross image

[Fredrik Noring]

On Friday, 12 March 2021, Maciej W. Rozycki wrote:
> On Fri, 12 Mar 2021, Philippe Mathieu-Daudé wrote:
> 
> > > but your two options to 
> > > choose from are:
> > > 
> > > 1. Build for the soft-float ABI (`-msoft-float') where any FP calculations 
> > >    are compiled such as to be made by the CPU using integer arithmetic.
> > 
> > With the Debian toolchain I get:
> > 
> > /usr/include/stdio.h:27:10: fatal error: bits/libc-header-start.h: No
> > such file or directory
> >  #include <bits/libc-header-start.h>
> >           ^~~~~~~~~~~~~~~~~~~~~~~~~~
> 
>  You need to have a soft-float multilib available.  You can use:
> 
> $ gcc -print-multi-lib
> 
> to see what multilibs are available.  You'd have to have one that includes 
> `-msoft-float' and `-mabi=n32' both at a time.  If there's no such one, 
> then you'll have to build your own cross-compiler (including soft-float 
> libc).

Perhaps, for the purpose of this test, if Debian doesn't have soft-float
and can't be recompiled, the -march=r5900 option could be omitted to
instead have objcopy (or even xxd) fix up the ELF to have it appear as
an R5900 program afterwards?

DMULT within an R5900 ELF would still be tested, as intended, even if
there might be some additional non-R5900 instructions in it as well (which
R5900/QEMU is supposed to accept anyway, no?).

On Friday, 12 March 2021, Philippe Mathieu-Daudé wrote:
> On 3/12/21 7:24 PM, Fredrik Noring wrote:
> > So qemu/tests/tcg/mips/Makefile.target is patched with
> > 
> > # r5900 is only 64 bit little-endian
> > ifneq ($(findstring 64el,$(TARGET_NAME)),)
> > MIPS_TESTS += test-r5900-dmult
> > test-r5900-dmult: CFLAGS += -mabi=n32 -march=r5900
> > endif
> > 
> > I didn't have issues with the -mhard-float -mdouble-float flags at the time,
> > and I didn't use mips64el-linux-gnuabi64-gcc for Debian.
> 
> Yes, this works with Gentoo. But building the Gentoo's r5900 toolchain
> container is too expensive for our CI, so I was trying with Debian, but
> with no luck so far.

Why rebuild the Gentoo toolchain so often, then? :) A couple of times per
year, and on special occasions (such as security updates or wanted feature
extensions), would be enough, I think. Gentoo has rolling releases, as
opposed to major releases, and old stuff (GCC in particular) can coexist
with modern counterparts via package slots, or in overlays, etc.

Of course, one might find it practical to use Debian for everything anyhow.

Fredrik

Re: [RFC PATCH 32/42] docker: Add gentoo-mipsr5900el-cross image

[Philippe Mathieu-Daudé]

Hi Maciej, Alex,

On 3/12/21 9:04 PM, Maciej W. Rozycki wrote:
> On Fri, 12 Mar 2021, Philippe Mathieu-Daudé wrote:
> 
>>> but your two options to 
>>> choose from are:
>>>
>>> 1. Build for the soft-float ABI (`-msoft-float') where any FP calculations 
>>>    are compiled such as to be made by the CPU using integer arithmetic.
>>
>> With the Debian toolchain I get:
>>
>> /usr/include/stdio.h:27:10: fatal error: bits/libc-header-start.h: No
>> such file or directory
>>  #include <bits/libc-header-start.h>
>>           ^~~~~~~~~~~~~~~~~~~~~~~~~~
> 
>  You need to have a soft-float multilib available.  You can use:
> 
> $ gcc -print-multi-lib
> 
> to see what multilibs are available.  You'd have to have one that includes 
> `-msoft-float' and `-mabi=n32' both at a time.  If there's no such one, 
> then you'll have to build your own cross-compiler (including soft-float 
> libc).

For Alex:

I tried Maciej suggestion using:

-- >8 --
diff --git a/tests/docker/dockerfiles/debian10.docker
b/tests/docker/dockerfiles/debian10.docker
index d034acbd256..42933538a49 100644
--- a/tests/docker/dockerfiles/debian10.docker
+++ b/tests/docker/dockerfiles/debian10.docker
@@ -23,6 +23,7 @@ RUN apt update && \
         ccache \
         clang \
         dbus \
+        gcc-multilib \
         gdb-multiarch \
         gettext \
         git \
---

Then used qemu/debian-mipsel-cross.

Maciej, I tried your suggestion as follow:

$ mipsel-linux-gnu-gcc --version
mipsel-linux-gnu-gcc (Debian 8.3.0-2) 8.3.0
Copyright (C) 2018 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

$ mipsel-linux-gnu-gcc -print-multi-lib
.;
n32;@mabi=n32
64;@mabi=64

soft-float is not listed, but:

$ touch a.c
$ mipsel-linux-gnu-gcc -mabi=n32 -march=r5900 -msoft-float -c a.c
$ file a.o
a.o: ELF 32-bit LSB relocatable, MIPS, N32 MIPS-III version 1 (SYSV),
not stripped
$ readelf -h a.o
ELF Header:
  Magic:   7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00
  Class:                             ELF32
  Data:                              2's complement, little endian
  Version:                           1 (current)
  OS/ABI:                            UNIX - System V
  ABI Version:                       0
  Type:                              REL (Relocatable file)
  Machine:                           MIPS R3000
  Version:                           0x1
  Entry point address:               0x0
  Start of program headers:          0 (bytes into file)
  Start of section headers:          456 (bytes into file)
  Flags:                             0x20920026, pic, cpic, abi2, 5900,
mips3
  Size of this header:               52 (bytes)
  Size of program headers:           0 (bytes)
  Number of program headers:         0
  Size of section headers:           40 (bytes)
  Number of section headers:         13
  Section header string table index: 12

So we can compile, but:

$ mipsel-linux-gnu-gcc -mabi=n32 -march=r5900 -msoft-float -L
/usr/lib/mipsel-linux-gnu tests/tcg/mips/test-r5900-dmult.c
/usr/lib/gcc-cross/mipsel-linux-gnu/8/../../../../mipsel-linux-gnu/bin/ld:
/usr/lib/../lib32/Scrt1.o: relocations in generic ELF (EM: 3)
/usr/lib/gcc-cross/mipsel-linux-gnu/8/../../../../mipsel-linux-gnu/bin/ld:
/usr/lib/../lib32/Scrt1.o: error adding symbols: file in wrong format
collect2: error: ld returned 1 exit status

$ mipsel-linux-gnu-readelf -h /usr/lib/mipsel-linux-gnu/Scrt1.o
ELF Header:
  Magic:   7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00
  Class:                             ELF32
  Data:                              2's complement, little endian
  Version:                           1 (current)
  OS/ABI:                            UNIX - System V
  ABI Version:                       0
  Type:                              REL (Relocatable file)
  Machine:                           MIPS R3000
  Version:                           0x1
  Entry point address:               0x0
  Start of program headers:          0 (bytes into file)
  Start of section headers:          908 (bytes into file)
  Flags:                             0x70001007, noreorder, pic, cpic,
o32, mips32r2
  Size of this header:               52 (bytes)
  Size of program headers:           0 (bytes)
  Number of program headers:         0
  Size of section headers:           40 (bytes)
  Number of section headers:         15
  Section header string table index: 14

The multilib documentation is scarce :)

Also I wondered if I could abuse the linker a bit, knowing the resulting
binary would be crap due to ABI mismatch, and got:

$ mipsel-linux-gnu-gcc -march=r5900 -msoft-float -o test-r5900-dmult
test-r5900-dmult.o
collect2: fatal error: ld terminated with signal 11 [Segmentation
fault], core dumped
compilation terminated.
/usr/lib/gcc-cross/mipsel-linux-gnu/8/../../../../mipsel-linux-gnu/bin/ld:
test-r5900-dmult.o: ABI is incompatible with that of the selected emulation
/usr/lib/gcc-cross/mipsel-linux-gnu/8/../../../../mipsel-linux-gnu/bin/ld:
failed to merge target specific data of file test-r5900-dmult.o
/usr/lib/gcc-cross/mipsel-linux-gnu/8/../../../../mipsel-linux-gnu/bin/ld:
BFD (GNU Binutils for Debian) 2.31.1 assertion fail
../../bfd/elfxx-mips.c:3566

It seems Debian default packages aren't ready for QEMU needs.

Alex, the other options I'm thinking of are:

- Have you build/upload the gentoo-mipsr5900el-cross container

- Commit the test-r5900-dmult binary to the repository

- Craft a test-r5900-dmult in assembler without libc:

$ mipsel-linux-gnu-gcc -mabi=n32 -march=r5900 -msoft-float -o a a.o
-nostdlib -emain
$ readelf -h a
ELF Header:
  Magic:   7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00
  Class:                             ELF32
  Data:                              2's complement, little endian
  Version:                           1 (current)
  OS/ABI:                            UNIX - System V
  ABI Version:                       0
  Type:                              DYN (Shared object file)
  Machine:                           MIPS R3000
  Version:                           0x1
  Entry point address:               0x102f0
  Start of program headers:          52 (bytes into file)
  Start of section headers:          1508 (bytes into file)
  Flags:                             0x20920026, pic, cpic, abi2, 5900,
mips3
  Size of this header:               52 (bytes)
  Size of program headers:           32 (bytes)
  Number of program headers:         9
  Size of section headers:           40 (bytes)
  Number of section headers:         17
  Section header string table index: 16

- Do not include r5900 test in mainstream QEMU

What do you think?

Phil.

Re: [RFC PATCH 32/42] docker: Add gentoo-mipsr5900el-cross image

[Maciej W. Rozycki]

On Wed, 17 Mar 2021, Philippe Mathieu-Daudé wrote:

> Maciej, I tried your suggestion as follow:
> 
> $ mipsel-linux-gnu-gcc --version
> mipsel-linux-gnu-gcc (Debian 8.3.0-2) 8.3.0
> Copyright (C) 2018 Free Software Foundation, Inc.
> This is free software; see the source for copying conditions.  There is NO
> warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
> 
> $ mipsel-linux-gnu-gcc -print-multi-lib
> .;
> n32;@mabi=n32
> 64;@mabi=64

 OK, so these are for the three ABIs Linux support, plain.  You'd have to 
bootstrap your own compiler and either reconfigure it at least for n32 
with a `-msoft-float' multilib, or build a non-multilib compiler for this 
ABI variant.  Either way including glibc which to the best of my knowledge 
does support soft-float MIPS configurations.

> soft-float is not listed, but:
> 
> $ touch a.c
> $ mipsel-linux-gnu-gcc -mabi=n32 -march=r5900 -msoft-float -c a.c
> $ file a.o
> a.o: ELF 32-bit LSB relocatable, MIPS, N32 MIPS-III version 1 (SYSV),
> not stripped
> $ readelf -h a.o
> ELF Header:
>   Magic:   7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00
>   Class:                             ELF32
>   Data:                              2's complement, little endian
>   Version:                           1 (current)
>   OS/ABI:                            UNIX - System V
>   ABI Version:                       0
>   Type:                              REL (Relocatable file)
>   Machine:                           MIPS R3000
>   Version:                           0x1
>   Entry point address:               0x0
>   Start of program headers:          0 (bytes into file)
>   Start of section headers:          456 (bytes into file)
>   Flags:                             0x20920026, pic, cpic, abi2, 5900,
> mips3
>   Size of this header:               52 (bytes)
>   Size of program headers:           0 (bytes)
>   Number of program headers:         0
>   Size of section headers:           40 (bytes)
>   Number of section headers:         13
>   Section header string table index: 12
> 
> So we can compile, but:

 Yes, all code models are always available for compilation (you can choose 
the default though).  We (ab)use this feature for instance to build the 
Linux kernel, which obviously uses the bare metal non-PIC model.

> $ mipsel-linux-gnu-gcc -mabi=n32 -march=r5900 -msoft-float -L
> /usr/lib/mipsel-linux-gnu tests/tcg/mips/test-r5900-dmult.c
> /usr/lib/gcc-cross/mipsel-linux-gnu/8/../../../../mipsel-linux-gnu/bin/ld:
> /usr/lib/../lib32/Scrt1.o: relocations in generic ELF (EM: 3)
> /usr/lib/gcc-cross/mipsel-linux-gnu/8/../../../../mipsel-linux-gnu/bin/ld:
> /usr/lib/../lib32/Scrt1.o: error adding symbols: file in wrong format
> collect2: error: ld returned 1 exit status

 Yes, the problem is in the missing runtime, and whatever GCC defaults to 
is not link-compatible.  The message from the linker indicates it couldn't 
have chosen a MIPS emulation at all even.

> $ mipsel-linux-gnu-readelf -h /usr/lib/mipsel-linux-gnu/Scrt1.o
> ELF Header:
>   Magic:   7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00
>   Class:                             ELF32
>   Data:                              2's complement, little endian
>   Version:                           1 (current)
>   OS/ABI:                            UNIX - System V
>   ABI Version:                       0
>   Type:                              REL (Relocatable file)
>   Machine:                           MIPS R3000
>   Version:                           0x1
>   Entry point address:               0x0
>   Start of program headers:          0 (bytes into file)
>   Start of section headers:          908 (bytes into file)
>   Flags:                             0x70001007, noreorder, pic, cpic,
> o32, mips32r2
>   Size of this header:               52 (bytes)
>   Size of program headers:           0 (bytes)
>   Number of program headers:         0
>   Size of section headers:           40 (bytes)
>   Number of section headers:         15
>   Section header string table index: 14

 That is a plain o32 ABI object.

> The multilib documentation is scarce :)

 Ask questions. :)

> Also I wondered if I could abuse the linker a bit, knowing the resulting
> binary would be crap due to ABI mismatch, and got:
> 
> $ mipsel-linux-gnu-gcc -march=r5900 -msoft-float -o test-r5900-dmult
> test-r5900-dmult.o
> collect2: fatal error: ld terminated with signal 11 [Segmentation
> fault], core dumped
> compilation terminated.
> /usr/lib/gcc-cross/mipsel-linux-gnu/8/../../../../mipsel-linux-gnu/bin/ld:
> test-r5900-dmult.o: ABI is incompatible with that of the selected emulation
> /usr/lib/gcc-cross/mipsel-linux-gnu/8/../../../../mipsel-linux-gnu/bin/ld:
> failed to merge target specific data of file test-r5900-dmult.o
> /usr/lib/gcc-cross/mipsel-linux-gnu/8/../../../../mipsel-linux-gnu/bin/ld:
> BFD (GNU Binutils for Debian) 2.31.1 assertion fail
> ../../bfd/elfxx-mips.c:3566

 This looks like a linker bug, it's not supposed to report assertion 
failures let alone crash even if fed with rubbish.  However version 2.31.1 
is very old for any kind of odd experiments.

 Would you be able to try the current trunk?  If that still shows the 
crash would you mind filing a bug with a full recipe to reproduce it at 
<https://sourceware.org/bugzilla/>?

 Regardless you can try fooling the linker by stripping the 
`.gnu.attributes' and `.MIPS.abiflags' sections from test-r5900-dmult.o 
with `objcopy'.  This will make the linker consider it a legacy object 
with no float mode annotation.

 This does not answer the question implied by the choice I have given as 
to whether you actually need to use `-march=r5900 -msoft-float' with these 
compilations or whether plain `-march=mips3' will suffice.

 I think it will do, as at this point we only have minimal R5900 support 
in the compiler and Linux is supposed to emulate the MIPS III instructions 
missing from the architecture, including full IEEE 754 FP.  So the use of 
`-march=r5900' does not appear to buy us anything.  And any R5900-specific 
assembly can be wrapped into an appropriate pseudo-op sequence involving 
`.set arch=r5900'.  I think this approach will enable forward progress.

  Maciej

Re: [RFC PATCH 32/42] docker: Add gentoo-mipsr5900el-cross image

[Fredrik Noring]

On Friday, 12 March 2021, Maciej W. Rozycki wrote:
> On Fri, 12 Mar 2021, Philippe Mathieu-Daudé wrote:
> 
> > >>> Is there any way we can do this with a distro that isn't Gentoo
> > >>> so that we can get a container build that is fast enough to be
> > >>> useful for CI ?
> > 
> > Using the Debian cross image I get:
> > 
> > /home/phil/source/qemu/tests/docker/docker.py --engine auto cc --cc
> > mips64el-linux-gnuabi64-gcc -i qemu/debian-mips64el-cross -s
> > /home/phil/source/qemu --   -Wall -Werror -O0 -g -fno-strict-aliasing
> > -mabi=n32 -march=r5900
> > /home/phil/source/qemu/tests/tcg/mips/test-r5900-dmult.c -o
> > test-r5900-dmult  -static
> > cc1: error: unsupported combination: -march=r5900 -mhard-float
> > -mdouble-float
> > 
> > No clue what is setting '-mhard-float -mdouble-float' yet.
> 
>  The R5900 has an FPU that only supports the single floating-point format.  
> It's also not an IEEE 754 format.  The Linux kernel ABI does support the 
> double and also the single floating-point format, both compliant with IEEE 
> 754.
> 
>  In the absence of a suitable FPU emulation code included with the kernel 
> will handle the missing instructions (you can use the `nofpu' kernel 
> parameter to force that in the presence of an FPU too).  Beware however 
> that a recent change to the Linux kernel made FPU emulation code optional 
> to suit some deeply embedded applications known never to use FPU machine 
> instructions.
> 
>  NB the presence of emulation is always required for MIPS ISA compliance 
> if FPU machine instructions are ever to be used in a given application, 
> because operations are allowed to trap regardless and rely on emulation.
> 
>  I don't know what you are trying to achieve,

I believe Philippe is trying to compile

https://lists.gnu.org/archive/html/qemu-devel/2021-03/msg04565.html

testing this:

	The R5900 reports itself as MIPS III but does not implement DMULT.
	Verify that DMULT is emulated properly in user mode by multiplying
	two 64-bit numbers to produce a 128-bit number.

with this piece of code (notice the mips3 ISA directive for DMULT):

/*
 * Test DMULT.
 */

#include <stdio.h>
#include <inttypes.h>
#include <assert.h>

struct hi_lo { int64_t hi; uint64_t lo; };

static struct hi_lo dmult(int64_t rs, int64_t rt)
{
    int64_t hi;
    uint64_t lo;

    /*
     * The R5900 reports itself as MIPS III but does not implement DMULT.
     * Verify that DMULT is emulated properly in user mode.
     */
    __asm__ __volatile__ (
            "    .set  mips3\n"
            "    dmult %2, %3\n"
            "    mfhi  %0\n"
            "    mflo  %1\n"
            : "=r" (hi), "=r" (lo)
            : "r" (rs), "r" (rt));

    return (struct hi_lo) { .hi = hi, .lo = lo };
}

int main()
{
    /* Verify that multiplying two 64-bit numbers yields a 128-bit number. */
    struct hi_lo r = dmult(2760727302517, 5665449960167);

    assert(r.hi == 847887);
    assert(r.lo == 7893651516417804947);

    return 0;
}

> but your two options to choose from are:
> 
> 1. Build for the soft-float ABI (`-msoft-float') where any FP calculations 
>    are compiled such as to be made by the CPU using integer arithmetic.
> 
> 2. Build for a generic MIPS ISA, for the R5900/n32 that would be MIPS III
>    (`-march=mips3'), and rely on the kernel FPU emulation.  Note that some 
>    integer MIPS III operations are missing too from the R5900 and have to 
>    be emulated by the kernel for MIPS/Linux n32 psABI compliance (an 
>    implementation can be pinched from an old libgcc version that was still 
>    under GNU GPLv2 or another algorithm reused, e.g. my `__div64_32' piece
>    easily adapted).

So qemu/tests/tcg/mips/Makefile.target is patched with

# r5900 is only 64 bit little-endian
ifneq ($(findstring 64el,$(TARGET_NAME)),)
MIPS_TESTS += test-r5900-dmult
test-r5900-dmult: CFLAGS += -mabi=n32 -march=r5900
endif

I didn't have issues with the -mhard-float -mdouble-float flags at the time,
and I didn't use mips64el-linux-gnuabi64-gcc for Debian.

Fredrik

Re: [RFC PATCH 32/42] docker: Add gentoo-mipsr5900el-cross image

[Philippe Mathieu-Daudé]

On 3/12/21 7:24 PM, Fredrik Noring wrote:
> On Friday, 12 March 2021, Maciej W. Rozycki wrote:
>> On Fri, 12 Mar 2021, Philippe Mathieu-Daudé wrote:
>>
>>>>>> Is there any way we can do this with a distro that isn't Gentoo
>>>>>> so that we can get a container build that is fast enough to be
>>>>>> useful for CI ?
>>>
>>> Using the Debian cross image I get:
>>>
>>> /home/phil/source/qemu/tests/docker/docker.py --engine auto cc --cc
>>> mips64el-linux-gnuabi64-gcc -i qemu/debian-mips64el-cross -s
>>> /home/phil/source/qemu --   -Wall -Werror -O0 -g -fno-strict-aliasing
>>> -mabi=n32 -march=r5900
>>> /home/phil/source/qemu/tests/tcg/mips/test-r5900-dmult.c -o
>>> test-r5900-dmult  -static
>>> cc1: error: unsupported combination: -march=r5900 -mhard-float
>>> -mdouble-float
>>>
>>> No clue what is setting '-mhard-float -mdouble-float' yet.
>>
>>  The R5900 has an FPU that only supports the single floating-point format.  
>> It's also not an IEEE 754 format.  The Linux kernel ABI does support the 
>> double and also the single floating-point format, both compliant with IEEE 
>> 754.
>>
>>  In the absence of a suitable FPU emulation code included with the kernel 
>> will handle the missing instructions (you can use the `nofpu' kernel 
>> parameter to force that in the presence of an FPU too).  Beware however 
>> that a recent change to the Linux kernel made FPU emulation code optional 
>> to suit some deeply embedded applications known never to use FPU machine 
>> instructions.
>>
>>  NB the presence of emulation is always required for MIPS ISA compliance 
>> if FPU machine instructions are ever to be used in a given application, 
>> because operations are allowed to trap regardless and rely on emulation.
>>
>>  I don't know what you are trying to achieve,
> 
> I believe Philippe is trying to compile
> 
> https://lists.gnu.org/archive/html/qemu-devel/2021-03/msg04565.html
> 
> testing this:
> 
> 	The R5900 reports itself as MIPS III but does not implement DMULT.
> 	Verify that DMULT is emulated properly in user mode by multiplying
> 	two 64-bit numbers to produce a 128-bit number.
> 
> with this piece of code (notice the mips3 ISA directive for DMULT):
> 
> /*
>  * Test DMULT.
>  */
> 
> #include <stdio.h>
> #include <inttypes.h>
> #include <assert.h>
> 
> struct hi_lo { int64_t hi; uint64_t lo; };
> 
> static struct hi_lo dmult(int64_t rs, int64_t rt)
> {
>     int64_t hi;
>     uint64_t lo;
> 
>     /*
>      * The R5900 reports itself as MIPS III but does not implement DMULT.
>      * Verify that DMULT is emulated properly in user mode.
>      */
>     __asm__ __volatile__ (
>             "    .set  mips3\n"
>             "    dmult %2, %3\n"
>             "    mfhi  %0\n"
>             "    mflo  %1\n"
>             : "=r" (hi), "=r" (lo)
>             : "r" (rs), "r" (rt));
> 
>     return (struct hi_lo) { .hi = hi, .lo = lo };
> }
> 
> int main()
> {
>     /* Verify that multiplying two 64-bit numbers yields a 128-bit number. */
>     struct hi_lo r = dmult(2760727302517, 5665449960167);
> 
>     assert(r.hi == 847887);
>     assert(r.lo == 7893651516417804947);
> 
>     return 0;
> }
> 
>> but your two options to choose from are:
>>
>> 1. Build for the soft-float ABI (`-msoft-float') where any FP calculations 
>>    are compiled such as to be made by the CPU using integer arithmetic.
>>
>> 2. Build for a generic MIPS ISA, for the R5900/n32 that would be MIPS III
>>    (`-march=mips3'), and rely on the kernel FPU emulation.  Note that some 
>>    integer MIPS III operations are missing too from the R5900 and have to 
>>    be emulated by the kernel for MIPS/Linux n32 psABI compliance (an 
>>    implementation can be pinched from an old libgcc version that was still 
>>    under GNU GPLv2 or another algorithm reused, e.g. my `__div64_32' piece
>>    easily adapted).
> 
> So qemu/tests/tcg/mips/Makefile.target is patched with
> 
> # r5900 is only 64 bit little-endian
> ifneq ($(findstring 64el,$(TARGET_NAME)),)
> MIPS_TESTS += test-r5900-dmult
> test-r5900-dmult: CFLAGS += -mabi=n32 -march=r5900
> endif
> 
> I didn't have issues with the -mhard-float -mdouble-float flags at the time,
> and I didn't use mips64el-linux-gnuabi64-gcc for Debian.

Yes, this works with Gentoo. But building the Gentoo's r5900 toolchain
container is too expensive for our CI, so I was trying with Debian, but
with no luck so far.

I'll test the other image your suggested elsewhere and see if Daniel is
OK with it (I doubt because this is not an "official" image).

Thanks,

Phil.

[RFC PATCH 33/42] gitlab-ci: Pass optional EXTRA_FILES when building docker images

[Philippe Mathieu-Daudé]

Pass EXTRA_FILES to tests/docker/docker.py to use its --extra-files
command line option.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 .gitlab-ci.d/containers.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.gitlab-ci.d/containers.yml b/.gitlab-ci.d/containers.yml
index 90fac85ce46..587bd4ba2e3 100644
--- a/.gitlab-ci.d/containers.yml
+++ b/.gitlab-ci.d/containers.yml
@@ -16,6 +16,7 @@
     - ./tests/docker/docker.py --engine docker build
           -t "qemu/$NAME" -f "tests/docker/dockerfiles/$NAME.docker"
           -r $CI_REGISTRY_IMAGE
+          $(test -n "$EXTRA_FILES" && echo "--extra-files $EXTRA_FILES")
     - docker tag "qemu/$NAME" "$TAG"
     - docker push "$TAG"
   after_script:
-- 
2.26.2

[RFC PATCH 34/42] gitlab-ci: Build MIPS R5900 cross-toolchain (Gentoo based)

[Philippe Mathieu-Daudé]

Add a job to build the Gentoo based MIPS R5900 cross-toolchain image.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 .gitlab-ci.d/containers.yml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/.gitlab-ci.d/containers.yml b/.gitlab-ci.d/containers.yml
index 587bd4ba2e3..f441e608446 100644
--- a/.gitlab-ci.d/containers.yml
+++ b/.gitlab-ci.d/containers.yml
@@ -152,6 +152,13 @@ mipsel-debian-cross-container:
   variables:
     NAME: debian-mipsel-cross
 
+mipsr5900el-gentoo-cross-container:
+  <<: *container_job_definition
+  variables:
+    NAME: gentoo-mipsr5900el-cross
+    EXTRA_FILES: tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker.d/crossdev.conf
+  timeout: 1h 30m
+
 powerpc-debian-cross-container:
   <<: *container_job_definition
   stage: containers-layer2
-- 
2.26.2

Re: [RFC PATCH 34/42] gitlab-ci: Build MIPS R5900 cross-toolchain (Gentoo based)

[Philippe Mathieu-Daudé]

On 2/14/21 6:59 PM, Philippe Mathieu-Daudé wrote:
> Add a job to build the Gentoo based MIPS R5900 cross-toolchain image.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  .gitlab-ci.d/containers.yml | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/.gitlab-ci.d/containers.yml b/.gitlab-ci.d/containers.yml
> index 587bd4ba2e3..f441e608446 100644
> --- a/.gitlab-ci.d/containers.yml
> +++ b/.gitlab-ci.d/containers.yml
> @@ -152,6 +152,13 @@ mipsel-debian-cross-container:
>    variables:
>      NAME: debian-mipsel-cross
>  
> +mipsr5900el-gentoo-cross-container:
> +  <<: *container_job_definition
> +  variables:
> +    NAME: gentoo-mipsr5900el-cross
> +    EXTRA_FILES: tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker.d/crossdev.conf
> +  timeout: 1h 30m

Well, depending of the runner hardware / load, this is not
enough:

Duration: 132 minutes 17 seconds
https://gitlab.com/philmd/qemu/-/jobs/1029975495

I'll use "2h 30" instead. I'm still looking how to make this job
optional (or manual).

Re: [RFC PATCH 34/42] gitlab-ci: Build MIPS R5900 cross-toolchain (Gentoo based)

[Daniel P. Berrangé]

On Mon, Feb 15, 2021 at 12:42:50PM +0100, Philippe Mathieu-Daudé wrote:
> On 2/14/21 6:59 PM, Philippe Mathieu-Daudé wrote:
> > Add a job to build the Gentoo based MIPS R5900 cross-toolchain image.
> > 
> > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> > ---
> >  .gitlab-ci.d/containers.yml | 7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/.gitlab-ci.d/containers.yml b/.gitlab-ci.d/containers.yml
> > index 587bd4ba2e3..f441e608446 100644
> > --- a/.gitlab-ci.d/containers.yml
> > +++ b/.gitlab-ci.d/containers.yml
> > @@ -152,6 +152,13 @@ mipsel-debian-cross-container:
> >    variables:
> >      NAME: debian-mipsel-cross
> >  
> > +mipsr5900el-gentoo-cross-container:
> > +  <<: *container_job_definition
> > +  variables:
> > +    NAME: gentoo-mipsr5900el-cross
> > +    EXTRA_FILES: tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker.d/crossdev.conf
> > +  timeout: 1h 30m
> 
> Well, depending of the runner hardware / load, this is not
> enough:
> 
> Duration: 132 minutes 17 seconds
> https://gitlab.com/philmd/qemu/-/jobs/1029975495

Yeah that's waaay too long to be part of standard CI.

> I'll use "2h 30" instead. I'm still looking how to make this job
> optional (or manual).

If it is manual who is ever going to run it and be willing to wait
2 hours for it. This just feels too long to be useful.

Regards,
Daniel
-- 
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[RFC PATCH 35/42] tests/tcg: Add MIPS R5900 to arches filter

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 tests/tcg/configure.sh | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh
index e1b70e25f23..64796ee11fc 100755
--- a/tests/tcg/configure.sh
+++ b/tests/tcg/configure.sh
@@ -57,6 +57,8 @@ fi
 : $(cross_cc_mips64="mips64-linux-gnuabi64-gcc")
 : $(cross_cc_mipsel="mipsel-linux-gnu-gcc")
 : $(cross_cc_mips="mips-linux-gnu-gcc")
+: $(cross_cc_r5900o32el="mipsr5900el-unknown-linux-gnu-gcc")
+: ${cross_cc_cflags_r5900o32el="-mabi=32 -march=r5900"}
 : ${cross_cc_ppc="powerpc-linux-gnu-gcc"}
 : ${cross_cc_cflags_ppc="-m32"}
 : ${cross_cc_ppc64="powerpc64-linux-gnu-gcc"}
@@ -79,7 +81,7 @@ for target in $target_list; do
     aarch64|aarch64_be)
       arches="aarch64 arm"
       ;;
-    mips*)
+    mips*|r5900o32el*)
       arches=mips
       ;;
     ppc*)
@@ -150,6 +152,10 @@ for target in $target_list; do
       container_image=debian-mips-cross
       container_cross_cc=mips-linux-gnu-gcc
       ;;
+    r5900o32el-*)
+      container_image=gentoo-mipsr5900el-cross
+      container_cross_cc=mipsr5900el-unknown-linux-gnu-gcc
+      ;;
     ppc-*|ppc64abi32-*)
       container_image=debian-powerpc-cross
       container_cross_cc=powerpc-linux-gnu-gcc
-- 
2.26.2

[RFC PATCH 36/42] tests/tcg/mips: Test user mode DMULT for the R5900

[Philippe Mathieu-Daudé]

From: Fredrik Noring <noring@nocrew.org>

The R5900 reports itself as MIPS III but does not implement DMULT.
Verify that DMULT is emulated properly in user mode by multiplying
two 64-bit numbers to produce a 128-bit number.

Signed-off-by: Fredrik Noring <noring@nocrew.org>
Message-Id: <b04427024562b10c852a5519b57033e094fcdc3b.1541701393.git.noring@nocrew.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 tests/tcg/mips/mipsn32r5900/dmult.c  | 40 ++++++++++++++++++++++++++++
 tests/tcg/mips/mipsn32r5900/Makefile | 25 +++++++++++++++++
 2 files changed, 65 insertions(+)
 create mode 100644 tests/tcg/mips/mipsn32r5900/dmult.c
 create mode 100644 tests/tcg/mips/mipsn32r5900/Makefile

diff --git a/tests/tcg/mips/mipsn32r5900/dmult.c b/tests/tcg/mips/mipsn32r5900/dmult.c
new file mode 100644
index 00000000000..2827ab5358f
--- /dev/null
+++ b/tests/tcg/mips/mipsn32r5900/dmult.c
@@ -0,0 +1,40 @@
+/*
+ * Test DMULT.
+ */
+
+#include <stdio.h>
+#include <inttypes.h>
+#include <assert.h>
+
+struct hi_lo { int64_t hi; uint64_t lo; };
+
+static struct hi_lo dmult(int64_t rs, int64_t rt)
+{
+    int64_t hi;
+    uint64_t lo;
+
+    /*
+     * The R5900 reports itself as MIPS III but does not implement DMULT.
+     * Verify that DMULT is emulated properly in user mode.
+     */
+    __asm__ __volatile__ (
+            "    .set  mips3\n"
+            "    dmult %2, %3\n"
+            "    mfhi  %0\n"
+            "    mflo  %1\n"
+            : "=r" (hi), "=r" (lo)
+            : "r" (rs), "r" (rt));
+
+    return (struct hi_lo) { .hi = hi, .lo = lo };
+}
+
+int main()
+{
+    /* Verify that multiplying two 64-bit numbers yields a 128-bit number. */
+    struct hi_lo r = dmult(2760727302517, 5665449960167);
+
+    assert(r.hi == 847887);
+    assert(r.lo == 7893651516417804947);
+
+    return 0;
+}
diff --git a/tests/tcg/mips/mipsn32r5900/Makefile b/tests/tcg/mips/mipsn32r5900/Makefile
new file mode 100644
index 00000000000..7dd16723fea
--- /dev/null
+++ b/tests/tcg/mips/mipsn32r5900/Makefile
@@ -0,0 +1,25 @@
+-include ../../config-host.mak
+
+CROSS=mips64r5900el-unknown-linux-gnu-
+
+SIM=qemu-mipsn32el
+SIM_FLAGS=-cpu R5900
+
+CC      = $(CROSS)gcc
+CFLAGS  = -Wall -mabi=n32 -march=r5900 -static
+
+TESTCASES = dmult.tst
+
+all: $(TESTCASES)
+
+%.tst: %.c
+	$(CC) $(CFLAGS) $< -o $@
+
+check: $(TESTCASES)
+	@for case in $(TESTCASES); do \
+        echo $(SIM) $(SIM_FLAGS) ./$$case;\
+        $(SIM) $(SIM_FLAGS) ./$$case; \
+	done
+
+clean:
+	$(RM) -rf $(TESTCASES)
-- 
2.26.2

[RFC PATCH 37/42] gitlab-ci: Add job to test the MIPS r5900o32el target

[Philippe Mathieu-Daudé]

Add a job to build the MIPS r5900o32el (linux-user) target
and run the TCG tests.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 .gitlab-ci.yml | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 28a83afb914..7d7559416e3 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -622,6 +622,18 @@ build-without-default-features:
         --target-list-exclude=arm-softmmu,i386-softmmu,mipsel-softmmu,mips64-softmmu,ppc-softmmu
     MAKE_CHECK_ARGS: check-unit
 
+build-r5900-user:
+  <<: *native_build_job_definition
+  variables:
+    IMAGE: fedora
+    CONFIGURE_ARGS: --disable-tools --disable-docs --disable-blobs --enable-debug-tcg
+    TARGETS: r5900o32el-linux-user
+    MAKE_CHECK_ARGS: run-tcg-tests-r5900o32el-linux-user
+  artifacts:
+    expire_in: 2 days
+    paths:
+      - build
+
 check-patch:
   stage: build
   image: $CI_REGISTRY_IMAGE/qemu/centos8:latest
-- 
2.26.2

Re: [RFC PATCH 37/42] gitlab-ci: Add job to test the MIPS r5900o32el target

[Thomas Huth]

On 14/02/2021 18.59, Philippe Mathieu-Daudé wrote:
> Add a job to build the MIPS r5900o32el (linux-user) target
> and run the TCG tests.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>   .gitlab-ci.yml | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
> 
> diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
> index 28a83afb914..7d7559416e3 100644
> --- a/.gitlab-ci.yml
> +++ b/.gitlab-ci.yml
> @@ -622,6 +622,18 @@ build-without-default-features:
>           --target-list-exclude=arm-softmmu,i386-softmmu,mipsel-softmmu,mips64-softmmu,ppc-softmmu
>       MAKE_CHECK_ARGS: check-unit
>   
> +build-r5900-user:
> +  <<: *native_build_job_definition
> +  variables:
> +    IMAGE: fedora

Don't you have to use the new gentoo-mipsr5900el-cross image to get the 
cross-compiler?

  Thomas

Re: [RFC PATCH 37/42] gitlab-ci: Add job to test the MIPS r5900o32el target

[Philippe Mathieu-Daudé]

On 2/15/21 6:31 AM, Thomas Huth wrote:
> On 14/02/2021 18.59, Philippe Mathieu-Daudé wrote:
>> Add a job to build the MIPS r5900o32el (linux-user) target
>> and run the TCG tests.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>>   .gitlab-ci.yml | 12 ++++++++++++
>>   1 file changed, 12 insertions(+)
>>
>> diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
>> index 28a83afb914..7d7559416e3 100644
>> --- a/.gitlab-ci.yml
>> +++ b/.gitlab-ci.yml
>> @@ -622,6 +622,18 @@ build-without-default-features:
>>          
>> --target-list-exclude=arm-softmmu,i386-softmmu,mipsel-softmmu,mips64-softmmu,ppc-softmmu
>>
>>       MAKE_CHECK_ARGS: check-unit
>>   +build-r5900-user:
>> +  <<: *native_build_job_definition
>> +  variables:
>> +    IMAGE: fedora
> 
> Don't you have to use the new gentoo-mipsr5900el-cross image to get the
> cross-compiler?

Yes you are right. I split this in 2 hoping [*] we can make the TCG
testing optional (as the gentoo cross container image):

build-user-r5900:
  <<: *native_build_job_definition
  variables:
    IMAGE: fedora
    CONFIGURE_ARGS: --disable-tools --disable-docs --disable-blobs
--enable-debug-tcg
    TARGETS: r5900o32el-linux-user
  artifacts:
    expire_in: 2 days
    paths:
      - build

check-user-r5900:
  <<: *native_test_job_definition
  needs:
    - job: build-user-r5900
      artifacts: true
    - job: mipsr5900el-gentoo-cross-container
  variables:
    IMAGE: fedora
    MAKE_CHECK_ARGS: run-tcg-tests-r5900o32el-linux-user

[*] currently 'needs' is limited:

  If "needs:" is set to point to a job that is not instantiated
  because of "only/except" rules or otherwise does not exist,
  the pipeline is not created and a YAML error is shown.

(See https://docs.gitlab.com/ee/ci/yaml/README.html#needs)

Regards,

Phil.

Re: [RFC PATCH 37/42] gitlab-ci: Add job to test the MIPS r5900o32el target

[Philippe Mathieu-Daudé]

On 2/15/21 9:07 AM, Philippe Mathieu-Daudé wrote:
> On 2/15/21 6:31 AM, Thomas Huth wrote:
>> On 14/02/2021 18.59, Philippe Mathieu-Daudé wrote:
>>> Add a job to build the MIPS r5900o32el (linux-user) target
>>> and run the TCG tests.
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>> ---
>>>   .gitlab-ci.yml | 12 ++++++++++++
>>>   1 file changed, 12 insertions(+)
>>>
>>> diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
>>> index 28a83afb914..7d7559416e3 100644
>>> --- a/.gitlab-ci.yml
>>> +++ b/.gitlab-ci.yml
>>> @@ -622,6 +622,18 @@ build-without-default-features:
>>>          
>>> --target-list-exclude=arm-softmmu,i386-softmmu,mipsel-softmmu,mips64-softmmu,ppc-softmmu
>>>
>>>       MAKE_CHECK_ARGS: check-unit
>>>   +build-r5900-user:
>>> +  <<: *native_build_job_definition
>>> +  variables:
>>> +    IMAGE: fedora
>>
>> Don't you have to use the new gentoo-mipsr5900el-cross image to get the
>> cross-compiler?
> 
> Yes you are right. I split this in 2 hoping [*] we can make the TCG
> testing optional (as the gentoo cross container image):
> 
> build-user-r5900:
>   <<: *native_build_job_definition
>   variables:
>     IMAGE: fedora
>     CONFIGURE_ARGS: --disable-tools --disable-docs --disable-blobs
> --enable-debug-tcg
>     TARGETS: r5900o32el-linux-user
>   artifacts:
>     expire_in: 2 days
>     paths:
>       - build
> 
> check-user-r5900:
>   <<: *native_test_job_definition
>   needs:
>     - job: build-user-r5900
>       artifacts: true
>     - job: mipsr5900el-gentoo-cross-container
>   variables:
>     IMAGE: fedora
>     MAKE_CHECK_ARGS: run-tcg-tests-r5900o32el-linux-user
> 
> [*] currently 'needs' is limited:
> 
>   If "needs:" is set to point to a job that is not instantiated
>   because of "only/except" rules or otherwise does not exist,
>   the pipeline is not created and a YAML error is shown.
> 
> (See https://docs.gitlab.com/ee/ci/yaml/README.html#needs)

I forgot to include the job results:

[build, Duration: 7 minutes 43 seconds]
https://gitlab.com/philmd/qemu/-/jobs/1029721393

[integration tests, Duration: 6 minutes 42 seconds]
https://gitlab.com/philmd/qemu/-/jobs/1029784692

[RFC PATCH 38/42] tests/acceptance: Extract QemuBaseTest from Test

[Philippe Mathieu-Daudé]

The Avocado Test::fetch_asset() is handy to download artifacts
before running tests. The current class is named Test but only
tests system emulation. As we want to test user emulation,
refactor the common code as QemuBaseTest.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 tests/acceptance/avocado_qemu/__init__.py | 35 +++++++++++++----------
 1 file changed, 20 insertions(+), 15 deletions(-)

diff --git a/tests/acceptance/avocado_qemu/__init__.py b/tests/acceptance/avocado_qemu/__init__.py
index bf54e419da2..31b7064c0e5 100644
--- a/tests/acceptance/avocado_qemu/__init__.py
+++ b/tests/acceptance/avocado_qemu/__init__.py
@@ -145,7 +145,7 @@ def exec_command_and_wait_for_pattern(test, command,
     """
     _console_interaction(test, success_message, failure_message, command + '\r')
 
-class Test(avocado.Test):
+class QemuBaseTest(avocado.Test):
     def _get_unique_tag_val(self, tag_name):
         """
         Gets a tag value, if unique for a key
@@ -156,8 +156,6 @@ def _get_unique_tag_val(self, tag_name):
         return None
 
     def setUp(self):
-        self._vms = {}
-
         self.arch = self.params.get('arch',
                                     default=self._get_unique_tag_val('arch'))
 
@@ -170,6 +168,25 @@ def setUp(self):
         if self.qemu_bin is None:
             self.cancel("No QEMU binary defined or found in the build tree")
 
+
+    def fetch_asset(self, name,
+                    asset_hash=None, algorithm=None,
+                    locations=None, expire=None,
+                    find_only=False, cancel_on_missing=True):
+        return super(QemuBaseTest, self).fetch_asset(name,
+                        asset_hash=asset_hash,
+                        algorithm=algorithm,
+                        locations=locations,
+                        expire=expire,
+                        find_only=find_only,
+                        cancel_on_missing=cancel_on_missing)
+
+# a.k.a. QemuSystemTest for system emulation...
+class Test(QemuBaseTest):
+    def setUp(self):
+        self._vms = {}
+        super(Test, self).setUp()
+
     def _new_vm(self, *args):
         self._sd = tempfile.TemporaryDirectory(prefix="avo_qemu_sock_")
         vm = QEMUMachine(self.qemu_bin, sock_dir=self._sd.name)
@@ -194,15 +211,3 @@ def tearDown(self):
         for vm in self._vms.values():
             vm.shutdown()
         self._sd = None
-
-    def fetch_asset(self, name,
-                    asset_hash=None, algorithm=None,
-                    locations=None, expire=None,
-                    find_only=False, cancel_on_missing=True):
-        return super(Test, self).fetch_asset(name,
-                        asset_hash=asset_hash,
-                        algorithm=algorithm,
-                        locations=locations,
-                        expire=expire,
-                        find_only=find_only,
-                        cancel_on_missing=cancel_on_missing)
-- 
2.26.2

[RFC PATCH 39/42] tests/acceptance: Make pick_default_qemu_bin() more generic

[Philippe Mathieu-Daudé]

Make pick_default_qemu_bin() generic to find qemu-system or
qemu-user binaries.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 tests/acceptance/avocado_qemu/__init__.py | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/tests/acceptance/avocado_qemu/__init__.py b/tests/acceptance/avocado_qemu/__init__.py
index 31b7064c0e5..e0067abca61 100644
--- a/tests/acceptance/avocado_qemu/__init__.py
+++ b/tests/acceptance/avocado_qemu/__init__.py
@@ -38,7 +38,7 @@ def is_readable_executable_file(path):
     return os.path.isfile(path) and os.access(path, os.R_OK | os.X_OK)
 
 
-def pick_default_qemu_bin(arch=None):
+def pick_default_qemu_bin(bin_fmt, arch=None):
     """
     Picks the path of a QEMU binary, starting either in the current working
     directory or in the source tree root directory.
@@ -57,7 +57,7 @@ def pick_default_qemu_bin(arch=None):
     # qemu binary path does not match arch for powerpc, handle it
     if 'ppc64le' in arch:
         arch = 'ppc64'
-    qemu_bin_relative_path = "./qemu-system-%s" % arch
+    qemu_bin_relative_path = os.path.join(".", bin_fmt % arch)
     if is_readable_executable_file(qemu_bin_relative_path):
         return qemu_bin_relative_path
 
@@ -155,14 +155,14 @@ def _get_unique_tag_val(self, tag_name):
             return vals.pop()
         return None
 
-    def setUp(self):
+    def setUp(self, bin_fmt):
         self.arch = self.params.get('arch',
                                     default=self._get_unique_tag_val('arch'))
 
         self.machine = self.params.get('machine',
                                        default=self._get_unique_tag_val('machine'))
 
-        default_qemu_bin = pick_default_qemu_bin(arch=self.arch)
+        default_qemu_bin = pick_default_qemu_bin(bin_fmt, arch=self.arch)
         self.qemu_bin = self.params.get('qemu_bin',
                                         default=default_qemu_bin)
         if self.qemu_bin is None:
@@ -185,7 +185,7 @@ def fetch_asset(self, name,
 class Test(QemuBaseTest):
     def setUp(self):
         self._vms = {}
-        super(Test, self).setUp()
+        super(Test, self).setUp("qemu-system-%s")
 
     def _new_vm(self, *args):
         self._sd = tempfile.TemporaryDirectory(prefix="avo_qemu_sock_")
-- 
2.26.2

[RFC PATCH 40/42] tests/acceptance: Introduce QemuUserTest base class

[Philippe Mathieu-Daudé]

Similarly to the 'System' Test base class with methods for testing
system emulation, the QemuUserTest class contains methods useful to
test user-mode emulation.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 tests/acceptance/avocado_qemu/__init__.py | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/tests/acceptance/avocado_qemu/__init__.py b/tests/acceptance/avocado_qemu/__init__.py
index e0067abca61..a293d228140 100644
--- a/tests/acceptance/avocado_qemu/__init__.py
+++ b/tests/acceptance/avocado_qemu/__init__.py
@@ -15,6 +15,7 @@
 import tempfile
 
 import avocado
+from avocado.utils import process
 
 #: The QEMU build root directory.  It may also be the source directory
 #: if building from the source dir, but it's safer to use BUILD_DIR for
@@ -211,3 +212,17 @@ def tearDown(self):
         for vm in self._vms.values():
             vm.shutdown()
         self._sd = None
+
+class QemuUserTest(QemuBaseTest):
+    def setUp(self):
+        self._ldpath = []
+        super(QemuUserTest, self).setUp("qemu-%s")
+
+    def add_ldpath(self, ldpath):
+        self._ldpath += [os.path.abspath(ldpath)]
+
+    def run(self, bin_path, args=[]):
+        qemu_args = " ".join(["-L %s" % ldpath for ldpath in self._ldpath])
+        bin_args = " ".join(args)
+        return process.run("%s %s %s %s" % (self.qemu_bin, qemu_args,
+                                            bin_path, bin_args))
-- 
2.26.2

[RFC PATCH 41/42] tests/acceptance: Test R5900 CPU with BusyBox from Sony PS2

[Philippe Mathieu-Daudé]

Test BusyBox on the R5900 CPU with 2 different binaries:

- o32 32-bit (statically linked)
- o32 64-bit (dynamically linked, uses multimedia instructions)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 MAINTAINERS                        |  1 +
 tests/acceptance/mips_r5900_ps2.py | 69 ++++++++++++++++++++++++++++++
 2 files changed, 70 insertions(+)
 create mode 100644 tests/acceptance/mips_r5900_ps2.py

diff --git a/MAINTAINERS b/MAINTAINERS
index de5fe1c65f5..1a23f471b0e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -242,6 +242,7 @@ F: include/hw/mips/
 F: include/hw/misc/mips_*
 F: include/hw/timer/mips_gictimer.h
 F: tests/tcg/mips/
+F: tests/acceptance/mips_r5900_ps2.py
 K: ^Subject:.*(?i)mips
 
 MIPS TCG CPUs (nanoMIPS ISA)
diff --git a/tests/acceptance/mips_r5900_ps2.py b/tests/acceptance/mips_r5900_ps2.py
new file mode 100644
index 00000000000..ff73f994e59
--- /dev/null
+++ b/tests/acceptance/mips_r5900_ps2.py
@@ -0,0 +1,69 @@
+# Test the MIPS R5900 CPU
+#
+# Copyright (C) 2021 Philippe Mathieu-Daudé <f4bug@amsat.org>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+import os
+import lzma
+import shutil
+
+from avocado import skipUnless
+
+from avocado.utils import archive
+from avocado_qemu import QemuUserTest
+
+class R5900(QemuUserTest):
+
+    @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code')
+    def test_gentoo_busybox_32bit(self):
+        """
+        :avocado: tags=arch:r5900o32el
+        :avocado: tags=linux_user
+        :avocado: tags=quick
+        """
+        busybox_url = ('https://raw.githubusercontent.com/philmd'
+                       '/qemu-testing-blob/bf6a300cf0bc56e4a2c5b'
+                       '/mips/ps2/busybox-gentoo-v1.32.0.xz')
+        busybox_hash = 'd2a0abc2c7c3adb6b2fdd63356be78bc5e99f324'
+        busybox_path_xz = self.fetch_asset(busybox_url, asset_hash=busybox_hash)
+
+        busybox_path = os.path.join(self.workdir, "busybox")
+        with lzma.open(busybox_path_xz, 'rb') as f_in:
+            with open(busybox_path, 'wb') as f_out:
+                shutil.copyfileobj(f_in, f_out)
+        os.chmod(busybox_path, 0o755)
+
+        res = self.run(busybox_path)
+        ver = 'BusyBox v1.32.0 (2021-02-09 15:13:23 -00) multi-call binary'
+        self.assertIn(ver, res.stdout_text)
+
+        res = self.run(busybox_path, ['uname', '-a'])
+        unm = 'mips64 mips64 mips64 GNU/Linux'
+        self.assertIn(unm, res.stdout_text)
+
+    @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code')
+    def test_ps2_busybox_64bit(self):
+        """
+        :avocado: tags=arch:r5900o32el
+        :avocado: tags=linux_user
+        :avocado: tags=quick
+        """
+        rootfs_url = ('https://raw.githubusercontent.com/philmd'
+                       '/qemu-testing-blob/bf6a300cf0bc56e4a2c5b/mips'
+                       '/ps2/ps2linux_live_v5_pal_netsurf_usb_busybox.tar.gz')
+        rootfs_hash = '9aa8fdd974cd3332c7167bceb6dd7137853d3a10'
+        rootfs_path_tgz = self.fetch_asset(rootfs_url, asset_hash=rootfs_hash)
+
+        archive.extract(rootfs_path_tgz, self.workdir)
+        busybox_path = self.workdir + "/bin/busybox"
+
+        self.add_ldpath(self.workdir)
+
+        res = self.run(busybox_path)
+        ver = 'BusyBox v0.60.5 (2010.06.06-16:16+0000) multi-call binary'
+        self.assertIn(ver, res.stderr_text)
+
+        res = self.run(busybox_path, ['uname', '-a'])
+        unm = 'mips64 unknown'
+        self.assertIn(unm, res.stdout_text)
-- 
2.26.2

Re: [RFC PATCH 41/42] tests/acceptance: Test R5900 CPU with BusyBox from Sony PS2

[Fredrik Noring]

On Sun, Feb 14, 2021 at 06:59:11PM +0100, Philippe Mathieu-Daudé wrote:
> Test BusyBox on the R5900 CPU with 2 different binaries:
> 
> - o32 32-bit (statically linked)
> - o32 64-bit (dynamically linked, uses multimedia instructions)

R5900/libc update:

Gnu libc for o32 was merged some time ago so any recent Gentoo etc. will
do fine without patches.

For n32, there's a provisional patch that needs reworking to get merged
(to have libc emulate DMULT etc. rather than the kernel/QEMU).[1]

Musl has a pending patch I posted[2] about a month ago. Musl is o32 only,
for all MIPS, but other than that it's got two significant advantages
over Gnu libc:

1. excellent support for static linking;

2. program sizes are often much smaller, more than 5x smaller observed.

An important detail is that since the R5900 FPU isn't compliant with
the IEEE 754 standard[3] it's normally wholly emulated by either libc or
the kernel, to comply with the MIPS psABI. The R5900 hardware FPU can
perhaps be enabled with a future R5900 ELF ABI annotation extension.[4]

Finally, the situation with the 128-bit R5900 general purpose registers
(GPRs) is not fully resolved with the Linux kernel. The best case
scenario, I believe, would be to have them available at all times.[5]

Fredrik

References:

[1] https://lists.gnu.org/archive/html/qemu-devel/2019-01/msg00974.html
[2] https://www.openwall.com/lists/musl/2020/12/24/2
[3] https://github.com/frno7/linux/wiki/R5900-floating-point-unit-(FPU)
[4] https://github.com/frno7/linux/issues/3
[5] https://github.com/frno7/linux/issues/5

Re: [RFC PATCH 41/42] tests/acceptance: Test R5900 CPU with BusyBox from Sony PS2

[Maciej W. Rozycki]

On Mon, 15 Feb 2021, Fredrik Noring wrote:

> For n32, there's a provisional patch that needs reworking to get merged
> (to have libc emulate DMULT etc. rather than the kernel/QEMU).[1]

 FWIW I think standard `-march=mips3' n32 Linux binaries need to work with 
the R5900, and therefore the kernel will have to emulate the missing part 
of the ABI (since years ago we chose to have it in the kernel rather than 
in a SIGILL handler).  The patch proposed only allows building GNU libc 
with `-march=r5900' which I find an optional feature (I don't know offhand
what advantages over `-march=mips3' would be there).

  Maciej

[RFC PATCH 42/42] gitlab-ci: Add job to run integration tests for the r5900o32el target

[Philippe Mathieu-Daudé]

Run some integration tests for the r5900o32el-linux-user target.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 .gitlab-ci.yml | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 7d7559416e3..ba2c9ac0b4d 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -634,6 +634,16 @@ build-r5900-user:
     paths:
       - build
 
+acceptance-r5900-user:
+  <<: *native_test_job_definition
+  needs:
+    - job: build-r5900-user
+      artifacts: true
+  variables:
+    IMAGE: fedora
+    MAKE_CHECK_ARGS: check-acceptance
+  <<: *acceptance_definition
+
 check-patch:
   stage: build
   image: $CI_REGISTRY_IMAGE/qemu/centos8:latest
-- 
2.26.2

Re: [RFC PATCH 00/42] target/mips: Reintroduce the R5900 CPU (with more testing)

[Philippe Mathieu-Daudé]

On 2/14/21 6:58 PM, Philippe Mathieu-Daudé wrote:
> The R5900 CPU was removed some time ago (frankly I don't remember
> why). This series add it back, but to prove it works, we also add
> testing at the end.
> 
> The main motivation is to have MIPS R5900 coverage, but to be able
> to run real world r5900 binaries, I had to implement more opcodes.
> 
> 42 patches are a lot, but 3 are already queued in linux-user-for-6.0,
> and the 11 last ones are pure testing. I suppose in next versions
> I'll split the testing patches, but to show the final objective I
> included them in here.
> 
> I tagged it RFC because some parts because:
> 
> - We'd rather not add yet another target, but we need the
>   ILP32-on-64bit ABI (o32 64-bit)
> 
> - RDHWR glibc kludge for user-mode
> 
> - Avocado patches are only here to show the final test.
>   They are useful for my set of tests, but not meant to
>   be merged in mainstream.
> 
> - gitlab jobs are only here to show the tests work.
>   If the target is ever accepted, it would go in an already
>   existing job.
> 
> I'm OK to maintain 64-bit o32 and the testing out of tree, but the
> TCG opcodes are worthwhile review for mainstream.
> 
> Note: there is a sign-extension bug somewhere but I can't find it:
> 
>  $ qemu-r5900o32el busybox free
>   =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
> =A0total =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0used =C2=A0=C2=A0=C2=
> =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0free =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0sha=
> red =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0buffers
>   =C2=A0Mem: =C2=A0=C2=A0=C2=A0=C2=A0=C2=A03682012 =C2=A0=C2=A0=C2=A0=C2=A0=
> =C2=A0=C2=A0812620 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A02869392 =C2=A0=C2=A0=C2=A0=
> =C2=A0=C2=A01367556 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0321136
>   Swap: =C2=A0=C2=A0=C2=A0=C2=A0=C2=A02095100 =C2=A0=C2=A0=C2=A0=C2=A0-149854=
> 4 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A03593644
>  Total: =C2=A0=C2=A0=C2=A0=C2=A0=C2=A05777112 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0-=
> 685924 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A06463036
> 
>  $ free # host
>   =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
> =A0total =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0used =C2=A0=C2=A0=C2=A0=C2=
> =A0=C2=A0=C2=A0=C2=A0free =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0shared =C2=A0buff/cac=
> he =C2=A0=C2=A0available
>  Mem: =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A016264924 =C2=A0=C2=A0=C2=A0=C2=A093=
> 23500 =C2=A0=C2=A0=C2=A0=C2=A02822500 =C2=A0=C2=A0=C2=A0=C2=A01377288 =C2=A0=
> =C2=A0=C2=A0=C2=A04118924 =C2=A0=C2=A0=C2=A0=C2=A05149548
>  Swap: =C2=A0=C2=A0=C2=A0=C2=A0=C2=A018872316 =C2=A0=C2=A0=C2=A011084368 =C2=
> =A0=C2=A0=C2=A0=C2=A07787948

[Same but unescaped]

Note: there is a sign-extension bug somewhere but I can't find it:

 $ qemu-r5900o32el busybox free
               total         used         free       shared      buffers
   Mem:      3682012       812620      2869392      1367556       321136
  Swap:      2095100     -1498544      3593644
 Total:      5777112      -685924      6463036

 $ free # host
               total        used        free      shared  buff/cache
  available
 Mem:       16264924     9323500     2822500     1377288     4118924
    5149548
 Swap:      18872316    11084368     7787948

See the used swap:

  11084368 = 0x00a92250
  -1498544 = 0xffe92250

Regards,

Phil.

Re: [RFC PATCH 00/42] target/mips: Reintroduce the R5900 CPU (with more testing)

[Philippe Mathieu-Daudé]

On 2/14/21 6:58 PM, Philippe Mathieu-Daudé wrote:
> The R5900 CPU was removed some time ago (frankly I don't remember
> why). This series add it back, but to prove it works, we also add
> testing at the end.
> 
> The main motivation is to have MIPS R5900 coverage, but to be able
> to run real world r5900 binaries, I had to implement more opcodes.
> 
> 42 patches are a lot, but 3 are already queued in linux-user-for-6.0,
> and the 11 last ones are pure testing. I suppose in next versions
> I'll split the testing patches, but to show the final objective I
> included them in here.
> 
> I tagged it RFC because some parts because:
> 
> - We'd rather not add yet another target, but we need the
>   ILP32-on-64bit ABI (o32 64-bit)
> 
> - RDHWR glibc kludge for user-mode
> 
> - Avocado patches are only here to show the final test.
>   They are useful for my set of tests, but not meant to
>   be merged in mainstream.
> 
> - gitlab jobs are only here to show the tests work.
>   If the target is ever accepted, it would go in an already
>   existing job.
> 
> I'm OK to maintain 64-bit o32 and the testing out of tree, but the
> TCG opcodes are worthwhile review for mainstream.

I forgot to mention, to debug this target with gdb (the various
multimedia opcodes are not recognized by QEMU disas).

I start QEMU listening for GDB with:

$ qemu-r5900o32el -g 1234 ...

Then start Debian's gdb-multiarch via Docker:

$ docker run -it --rm -v /tmp:/tmp -u $UID --network=host \
  registry.gitlab.com/qemu-project/qemu/qemu/debian10 \
  gdb-multiarch -q \
    --ex 'set architecture mips:5900' --ex 'set endian little'
The target architecture is assumed to be mips:5900
The target is assumed to be little endian
(gdb)

Connect to QEMU on host:

(gdb) target remote 172.17.0.1:1234

Opcodes are displayed properly:

(gdb) x/20i 0x0002553c
   0x2553c:     pcpyld  a1,a1,a1
   0x25540:     li      a2,255
   0x25544:     andi    t1,a0,0x7
   0x25548:     beqz    t1,0x255fc
   0x2554c:     andi    t1,a0,0xf
   0x25550:     lw      t0,0(a0)
   0x25554:     addiu   a0,a0,4
   0x25558:     pceqb   t2,t0,zero
   0x2555c:     pceqb   t3,t0,a1
   0x25560:     or      t4,t3,t2
   0x25564:     pextlw  t4,zero,t4
   0x25568:     beqz    t4,0x255fc

One limitation is we can not access the upper halves of
the 128-bit general purpose registers :(
[Maybe we can but I don't know how...]

Regards,

Phil.

Re: [RFC PATCH 00/42] target/mips: Reintroduce the R5900 CPU (with more testing)

[Philippe Mathieu-Daudé]

On 2/14/21 6:58 PM, Philippe Mathieu-Daudé wrote:
> The R5900 CPU was removed some time ago (frankly I don't remember
> why). This series add it back, but to prove it works, we also add
> testing at the end.
> 
> The main motivation is to have MIPS R5900 coverage, but to be able
> to run real world r5900 binaries, I had to implement more opcodes.

> Philippe Mathieu-Daud=C3=A9 (40):
>   linux-user/mips64: Restore setup_frame() for o32 ABI
>   linux-user/mips64: Support o32 ABI syscalls
>   target/mips/translate: Make cpu_HI/LO registers public
>   target/mips: Promote 128-bit multimedia registers as global ones
>   target/mips: Rename 128-bit upper halve GPR registers
>   target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers
>   target/mips/translate: Use GPR move functions in gen_HILO1_tx79()

Generic patches 3-7 applied to mips-next.