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From: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
To: Rob Herring <robh@kernel.org>
Cc: "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	"pawel.moll@arm.com" <pawel.moll@arm.com>,
	"ijc+devicetree@hellion.org.uk" <ijc+devicetree@hellion.org.uk>,
	"marc.zyngier@arm.com" <marc.zyngier@arm.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Michal Simek <michals@xilinx.com>,
	"Ravikiran Gummaluri" <rgummal@xilinx.com>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"galak@codeaurora.org" <galak@codeaurora.org>,
	Soren Brinkmann <sorenb@xilinx.com>
Subject: RE: [PATCH] PCI: Xilinx NWL PCIe: Updating device tree documentation with prefetchable memory space
Date: Tue, 30 Aug 2016 10:46:18 +0000	[thread overview]
Message-ID: <8520D5D51A55D047800579B094147198258D22D1@XAP-PVEXMBX01.xlnx.xilinx.com> (raw)
In-Reply-To: <20160810222251.GA31705@rob-hp-laptop>

> Subject: Re: [PATCH] PCI: Xilinx NWL PCIe: Updating device tree documentation
> with prefetchable memory space
>
> On Tue, Aug 09, 2016 at 07:30:09PM +0530, Bharat Kumar Gogada wrote:
> > Updating device tree documentation with prefetchable memory sapce.
> > Configuration space shifted to 64-bit address space.
> >
> > Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> > ---
> >  Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
>
> Acked-by: Rob Herring <robh@kernel.org>

Thanks Rob


This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.

WARNING: multiple messages have this Message-ID (diff)
From: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
To: Rob Herring <robh@kernel.org>
Cc: "mark.rutland@arm.com" <mark.rutland@arm.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"pawel.moll@arm.com" <pawel.moll@arm.com>,
	"ijc+devicetree@hellion.org.uk" <ijc+devicetree@hellion.org.uk>,
	"marc.zyngier@arm.com" <marc.zyngier@arm.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Michal Simek <michals@xilinx.com>,
	Soren Brinkmann <sorenb@xilinx.com>,
	"galak@codeaurora.org" <galak@codeaurora.org>,
	Ravikiran Gummaluri <rgummal@xilinx.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>
Subject: RE: [PATCH] PCI: Xilinx NWL PCIe: Updating device tree documentation with prefetchable memory space
Date: Tue, 30 Aug 2016 10:46:18 +0000	[thread overview]
Message-ID: <8520D5D51A55D047800579B094147198258D22D1@XAP-PVEXMBX01.xlnx.xilinx.com> (raw)
In-Reply-To: <20160810222251.GA31705@rob-hp-laptop>

> Subject: Re: [PATCH] PCI: Xilinx NWL PCIe: Updating device tree documentation
> with prefetchable memory space
>
> On Tue, Aug 09, 2016 at 07:30:09PM +0530, Bharat Kumar Gogada wrote:
> > Updating device tree documentation with prefetchable memory sapce.
> > Configuration space shifted to 64-bit address space.
> >
> > Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> > ---
> >  Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
>
> Acked-by: Rob Herring <robh@kernel.org>

Thanks Rob


This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.

WARNING: multiple messages have this Message-ID (diff)
From: bharat.kumar.gogada@xilinx.com (Bharat Kumar Gogada)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] PCI: Xilinx NWL PCIe: Updating device tree documentation with prefetchable memory space
Date: Tue, 30 Aug 2016 10:46:18 +0000	[thread overview]
Message-ID: <8520D5D51A55D047800579B094147198258D22D1@XAP-PVEXMBX01.xlnx.xilinx.com> (raw)
In-Reply-To: <20160810222251.GA31705@rob-hp-laptop>

> Subject: Re: [PATCH] PCI: Xilinx NWL PCIe: Updating device tree documentation
> with prefetchable memory space
>
> On Tue, Aug 09, 2016 at 07:30:09PM +0530, Bharat Kumar Gogada wrote:
> > Updating device tree documentation with prefetchable memory sapce.
> > Configuration space shifted to 64-bit address space.
> >
> > Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> > ---
> >  Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
>
> Acked-by: Rob Herring <robh@kernel.org>

Thanks Rob


This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.

  reply	other threads:[~2016-08-30 11:20 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-09 14:00 [PATCH] PCI: Xilinx NWL PCIe: Updating device tree documentation with prefetchable memory space Bharat Kumar Gogada
2016-08-09 14:00 ` Bharat Kumar Gogada
2016-08-09 14:00 ` Bharat Kumar Gogada
2016-08-10 22:22 ` Rob Herring
2016-08-10 22:22   ` Rob Herring
2016-08-30 10:46   ` Bharat Kumar Gogada [this message]
2016-08-30 10:46     ` Bharat Kumar Gogada
2016-08-30 10:46     ` Bharat Kumar Gogada

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