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* [PATCH] PCI: Xilinx NWL PCIe: Updating device tree documentation with prefetchable memory space
@ 2016-08-09 14:00 ` Bharat Kumar Gogada
  0 siblings, 0 replies; 8+ messages in thread
From: Bharat Kumar Gogada @ 2016-08-09 14:00 UTC (permalink / raw)
  To: robh+dt, devicetree
  Cc: pawel.moll, mark.rutland, ijc+devicetree, galak, soren.brinkmann,
	marc.zyngier, linux-arm-kernel, linux-kernel, michal.simek,
	rgummal, Bharat Kumar Gogada

Updating device tree documentation with prefetchable memory
sapce.
Configuration space shifted to 64-bit address space.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
---
 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
index 337fc97..3259798 100644
--- a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
@@ -55,9 +55,10 @@ nwl_pcie: pcie@fd0e0000 {
 	msi-parent = <&nwl_pcie>;
 	reg = <0x0 0xfd0e0000 0x0 0x1000>,
 	      <0x0 0xfd480000 0x0 0x1000>,
-	      <0x0 0xe0000000 0x0 0x1000000>;
+	      <0x80 0x00000000 0x0 0x1000000>;
 	reg-names = "breg", "pcireg", "cfg";
-	ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>;
+	ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000  /* non-prefetchable memory */
+		  0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
 
 	pcie_intc: legacy-interrupt-controller {
 		interrupt-controller;
-- 
2.1.1

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* [PATCH] PCI: Xilinx NWL PCIe: Updating device tree documentation with prefetchable memory space
@ 2016-08-09 14:00 ` Bharat Kumar Gogada
  0 siblings, 0 replies; 8+ messages in thread
From: Bharat Kumar Gogada @ 2016-08-09 14:00 UTC (permalink / raw)
  To: robh+dt, devicetree
  Cc: pawel.moll, mark.rutland, ijc+devicetree, galak, soren.brinkmann,
	marc.zyngier, linux-arm-kernel, linux-kernel, michal.simek,
	rgummal, Bharat Kumar Gogada

Updating device tree documentation with prefetchable memory
sapce.
Configuration space shifted to 64-bit address space.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
---
 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
index 337fc97..3259798 100644
--- a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
@@ -55,9 +55,10 @@ nwl_pcie: pcie@fd0e0000 {
 	msi-parent = <&nwl_pcie>;
 	reg = <0x0 0xfd0e0000 0x0 0x1000>,
 	      <0x0 0xfd480000 0x0 0x1000>,
-	      <0x0 0xe0000000 0x0 0x1000000>;
+	      <0x80 0x00000000 0x0 0x1000000>;
 	reg-names = "breg", "pcireg", "cfg";
-	ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>;
+	ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000  /* non-prefetchable memory */
+		  0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
 
 	pcie_intc: legacy-interrupt-controller {
 		interrupt-controller;
-- 
2.1.1

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* [PATCH] PCI: Xilinx NWL PCIe: Updating device tree documentation with prefetchable memory space
@ 2016-08-09 14:00 ` Bharat Kumar Gogada
  0 siblings, 0 replies; 8+ messages in thread
From: Bharat Kumar Gogada @ 2016-08-09 14:00 UTC (permalink / raw)
  To: linux-arm-kernel

Updating device tree documentation with prefetchable memory
sapce.
Configuration space shifted to 64-bit address space.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
---
 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
index 337fc97..3259798 100644
--- a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
@@ -55,9 +55,10 @@ nwl_pcie: pcie at fd0e0000 {
 	msi-parent = <&nwl_pcie>;
 	reg = <0x0 0xfd0e0000 0x0 0x1000>,
 	      <0x0 0xfd480000 0x0 0x1000>,
-	      <0x0 0xe0000000 0x0 0x1000000>;
+	      <0x80 0x00000000 0x0 0x1000000>;
 	reg-names = "breg", "pcireg", "cfg";
-	ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>;
+	ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000  /* non-prefetchable memory */
+		  0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
 
 	pcie_intc: legacy-interrupt-controller {
 		interrupt-controller;
-- 
2.1.1

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* Re: [PATCH] PCI: Xilinx NWL PCIe: Updating device tree documentation with prefetchable memory space
  2016-08-09 14:00 ` Bharat Kumar Gogada
@ 2016-08-10 22:22   ` Rob Herring
  -1 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2016-08-10 22:22 UTC (permalink / raw)
  To: Bharat Kumar Gogada
  Cc: devicetree, mark.rutland, pawel.moll, ijc+devicetree,
	marc.zyngier, linux-kernel, michal.simek, Bharat Kumar Gogada,
	rgummal, linux-arm-kernel, galak, soren.brinkmann

On Tue, Aug 09, 2016 at 07:30:09PM +0530, Bharat Kumar Gogada wrote:
> Updating device tree documentation with prefetchable memory
> sapce.
> Configuration space shifted to 64-bit address space.
> 
> Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> ---
>  Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 8+ messages in thread
* [PATCH] PCI: Xilinx NWL PCIe: Updating device tree documentation with prefetchable memory space
@ 2016-08-10 22:22   ` Rob Herring
  0 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2016-08-10 22:22 UTC (permalink / raw)
  To: linux-arm-kernel

On Tue, Aug 09, 2016 at 07:30:09PM +0530, Bharat Kumar Gogada wrote:
> Updating device tree documentation with prefetchable memory
> sapce.
> Configuration space shifted to 64-bit address space.
> 
> Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> ---
>  Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 8+ messages in thread
* RE: [PATCH] PCI: Xilinx NWL PCIe: Updating device tree documentation with prefetchable memory space
  2016-08-10 22:22   ` Rob Herring
  (?)
@ 2016-08-30 10:46     ` Bharat Kumar Gogada
  -1 siblings, 0 replies; 8+ messages in thread
From: Bharat Kumar Gogada @ 2016-08-30 10:46 UTC (permalink / raw)
  To: Rob Herring
  Cc: devicetree, mark.rutland, pawel.moll, ijc+devicetree,
	marc.zyngier, linux-kernel, Michal Simek, Ravikiran Gummaluri,
	linux-arm-kernel, galak, Soren Brinkmann

> Subject: Re: [PATCH] PCI: Xilinx NWL PCIe: Updating device tree documentation
> with prefetchable memory space
>
> On Tue, Aug 09, 2016 at 07:30:09PM +0530, Bharat Kumar Gogada wrote:
> > Updating device tree documentation with prefetchable memory sapce.
> > Configuration space shifted to 64-bit address space.
> >
> > Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> > ---
> >  Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
>
> Acked-by: Rob Herring <robh@kernel.org>

Thanks Rob


This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.

^ permalink raw reply	[flat|nested] 8+ messages in thread
* RE: [PATCH] PCI: Xilinx NWL PCIe: Updating device tree documentation with prefetchable memory space
@ 2016-08-30 10:46     ` Bharat Kumar Gogada
  0 siblings, 0 replies; 8+ messages in thread
From: Bharat Kumar Gogada @ 2016-08-30 10:46 UTC (permalink / raw)
  To: Rob Herring
  Cc: mark.rutland, devicetree, pawel.moll, ijc+devicetree,
	marc.zyngier, linux-kernel, Michal Simek, Soren Brinkmann, galak,
	Ravikiran Gummaluri, linux-arm-kernel

> Subject: Re: [PATCH] PCI: Xilinx NWL PCIe: Updating device tree documentation
> with prefetchable memory space
>
> On Tue, Aug 09, 2016 at 07:30:09PM +0530, Bharat Kumar Gogada wrote:
> > Updating device tree documentation with prefetchable memory sapce.
> > Configuration space shifted to 64-bit address space.
> >
> > Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> > ---
> >  Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
>
> Acked-by: Rob Herring <robh@kernel.org>

Thanks Rob


This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.

^ permalink raw reply	[flat|nested] 8+ messages in thread
* [PATCH] PCI: Xilinx NWL PCIe: Updating device tree documentation with prefetchable memory space
@ 2016-08-30 10:46     ` Bharat Kumar Gogada
  0 siblings, 0 replies; 8+ messages in thread
From: Bharat Kumar Gogada @ 2016-08-30 10:46 UTC (permalink / raw)
  To: linux-arm-kernel

> Subject: Re: [PATCH] PCI: Xilinx NWL PCIe: Updating device tree documentation
> with prefetchable memory space
>
> On Tue, Aug 09, 2016 at 07:30:09PM +0530, Bharat Kumar Gogada wrote:
> > Updating device tree documentation with prefetchable memory sapce.
> > Configuration space shifted to 64-bit address space.
> >
> > Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> > ---
> >  Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
>
> Acked-by: Rob Herring <robh@kernel.org>

Thanks Rob


This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.

^ permalink raw reply	[flat|nested] 8+ messages in thread
end of thread, other threads:[~2016-08-30 11:20 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-08-09 14:00 [PATCH] PCI: Xilinx NWL PCIe: Updating device tree documentation with prefetchable memory space Bharat Kumar Gogada
2016-08-09 14:00 ` Bharat Kumar Gogada
2016-08-09 14:00 ` Bharat Kumar Gogada
2016-08-10 22:22 ` Rob Herring
2016-08-10 22:22   ` Rob Herring
2016-08-30 10:46   ` Bharat Kumar Gogada
2016-08-30 10:46     ` Bharat Kumar Gogada
2016-08-30 10:46     ` Bharat Kumar Gogada

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