* [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig
@ 2022-05-05 15:54 Neal Frager via buildroot
2022-05-05 15:54 ` [Buildroot] [PATCH v1 2/2] DEVELOPERS update Neal Frager via buildroot
` (2 more replies)
0 siblings, 3 replies; 28+ messages in thread
From: Neal Frager via buildroot @ 2022-05-05 15:54 UTC (permalink / raw)
To: buildroot; +Cc: luca, giulio.benetti, michal.simek, Neal Frager
This patch adds support for Xilinx Kria KV260 starter kit.
KV260 features can be found here:
https://www.xilinx.com/products/boards-and-kits/kv260.html
While the Kria SOM is based on a ZynqMP SoC, there are some key
boot config differences from the other ZynqMP evaluation boards.
1. There are no boot switches on Kria SOMs. The boot mode is thus
hard configured for QSPI flash. A pre-programmed boot.bin comes
with every Starter Kit. U-Boot can then find the Linux kernel and
file system on the SD card.
Optional instructions for updating the boot.bin in the QSPI flash
can be found in the readme.txt file and the link below.
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM
2. Kria SOMs use UART1 for the console instead of UART0. For this
reason, Kria Starter Kits will use a separate extlinux.conf file
from other ZynqMP evaluation boards.
Signed-off-by: Neal Frager <neal.frager@amd.com>
---
board/zynqmp/kria/extlinux.conf | 4 +
board/zynqmp/kria/kv260/pm_cfg_obj.c | 556 +++++++++++++++++++++++++
board/zynqmp/kria/kv260/uboot.fragment | 1 +
board/zynqmp/kria/post-build.sh | 8 +
board/zynqmp/kria/readme.txt | 78 ++++
configs/zynqmp_kria_kv260_defconfig | 37 ++
6 files changed, 684 insertions(+)
create mode 100644 board/zynqmp/kria/extlinux.conf
create mode 100644 board/zynqmp/kria/kv260/pm_cfg_obj.c
create mode 100644 board/zynqmp/kria/kv260/uboot.fragment
create mode 100755 board/zynqmp/kria/post-build.sh
create mode 100644 board/zynqmp/kria/readme.txt
create mode 100644 configs/zynqmp_kria_kv260_defconfig
diff --git a/board/zynqmp/kria/extlinux.conf b/board/zynqmp/kria/extlinux.conf
new file mode 100644
index 0000000000..663aabb7c3
--- /dev/null
+++ b/board/zynqmp/kria/extlinux.conf
@@ -0,0 +1,4 @@
+label linux
+ kernel /Image
+ devicetree /system.dtb
+ append console=ttyPS1,115200 root=/dev/mmcblk1p2 rw rootwait
diff --git a/board/zynqmp/kria/kv260/pm_cfg_obj.c b/board/zynqmp/kria/kv260/pm_cfg_obj.c
new file mode 100644
index 0000000000..019df6e237
--- /dev/null
+++ b/board/zynqmp/kria/kv260/pm_cfg_obj.c
@@ -0,0 +1,556 @@
+/******************************************************************************
+* Copyright (c) 2017 - 2021 Xilinx, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+#include "xil_types.h"
+#include "pm_defs.h"
+
+#define PM_CONFIG_MASTER_SECTION_ID 0x101U
+#define PM_CONFIG_SLAVE_SECTION_ID 0x102U
+#define PM_CONFIG_PREALLOC_SECTION_ID 0x103U
+#define PM_CONFIG_POWER_SECTION_ID 0x104U
+#define PM_CONFIG_RESET_SECTION_ID 0x105U
+#define PM_CONFIG_SHUTDOWN_SECTION_ID 0x106U
+#define PM_CONFIG_SET_CONFIG_SECTION_ID 0x107U
+#define PM_CONFIG_GPO_SECTION_ID 0x108U
+
+#define PM_SLAVE_FLAG_IS_SHAREABLE 0x1U
+#define PM_MASTER_USING_SLAVE_MASK 0x2U
+
+#define PM_CONFIG_GPO1_MIO_PIN_34_MAP (1U << 10U)
+#define PM_CONFIG_GPO1_MIO_PIN_35_MAP (1U << 11U)
+#define PM_CONFIG_GPO1_MIO_PIN_36_MAP (1U << 12U)
+#define PM_CONFIG_GPO1_MIO_PIN_37_MAP (1U << 13U)
+
+#define PM_CONFIG_GPO1_BIT_2_MASK (1U << 2U)
+#define PM_CONFIG_GPO1_BIT_3_MASK (1U << 3U)
+#define PM_CONFIG_GPO1_BIT_4_MASK (1U << 4U)
+#define PM_CONFIG_GPO1_BIT_5_MASK (1U << 5U)
+
+#define SUSPEND_TIMEOUT 0xFFFFFFFFU
+
+#define PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK 0x00000001
+#define PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK 0x00000100
+#define PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK 0x00000200
+
+
+
+#if defined (__ICCARM__)
+#pragma language=save
+#pragma language=extended
+#endif
+#if defined (__GNUC__)
+ const u32 XPm_ConfigObject[] __attribute__((used, section(".sys_cfg_data"))) =
+#elif defined (__ICCARM__)
+#pragma location = ".sys_cfg_data"
+__root const u32 XPm_ConfigObject[] =
+#endif
+{
+ /**********************************************************************/
+ /* HEADER */
+ 2, /* Number of remaining words in the header */
+ 8, /* Number of sections included in config object */
+ 1U, /* Type of config object as base */
+ /**********************************************************************/
+ /* MASTER SECTION */
+ PM_CONFIG_MASTER_SECTION_ID, /* Master SectionID */
+ 3U, /* No. of Masters*/
+
+ NODE_APU, /* Master Node ID */
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK, /* IPI Mask of this master */
+ SUSPEND_TIMEOUT, /* Suspend timeout */
+ PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Suspend permissions */
+ PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Wake permissions */
+
+ NODE_RPU_0, /* Master Node ID */
+ PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask of this master */
+ SUSPEND_TIMEOUT, /* Suspend timeout */
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Suspend permissions */
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Wake permissions */
+
+ NODE_RPU_1, /* Master Node ID */
+ PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask of this master */
+ SUSPEND_TIMEOUT, /* Suspend timeout */
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* Suspend permissions */
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* Wake permissions */
+
+
+ /**********************************************************************/
+ /* SLAVE SECTION */
+
+
+ PM_CONFIG_SLAVE_SECTION_ID, /* Section ID */
+ 49, /* Number of slaves */
+
+ NODE_OCM_BANK_0,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_OCM_BANK_1,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_OCM_BANK_2,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_OCM_BANK_3,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_TCM_0_A,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask */
+
+ NODE_TCM_0_B,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask */
+
+ NODE_TCM_1_A,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_TCM_1_B,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_L2,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_GPU_PP_0,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_GPU_PP_1,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_USB_0,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_USB_1,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ 0U, /* IPI Mask */
+
+ NODE_TTC_0,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_TTC_1,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_TTC_2,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_TTC_3,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_SATA,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ 0U, /* IPI Mask */
+
+ NODE_ETH_0,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ 0U, /* IPI Mask */
+
+ NODE_ETH_1,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ 0U, /* IPI Mask */
+
+ NODE_ETH_2,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ 0U, /* IPI Mask */
+
+ NODE_ETH_3,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_UART_0,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ 0U, /* IPI Mask */
+
+ NODE_UART_1,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_SPI_0,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ 0U, /* IPI Mask */
+
+ NODE_SPI_1,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_I2C_0,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ 0U, /* IPI Mask */
+
+ NODE_I2C_1,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_SD_0,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ 0U, /* IPI Mask */
+
+ NODE_SD_1,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_DP,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_GDMA,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_ADMA,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_NAND,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ 0U, /* IPI Mask */
+
+ NODE_QSPI,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_GPIO,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_CAN_0,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ 0U, /* IPI Mask */
+
+ NODE_CAN_1,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ 0U, /* IPI Mask */
+
+ NODE_EXTERN,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_DDR,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_IPI_APU,
+ 0U,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK, /* IPI Mask */
+
+ NODE_IPI_RPU_0,
+ 0U,
+ PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask */
+
+ NODE_IPI_RPU_1,
+ 0U,
+ PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_GPU,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_PCIE,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ 0U, /* IPI Mask */
+
+ NODE_PCAP,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ 0U, /* IPI Mask */
+
+ NODE_RTC,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+ NODE_VCU,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ 0U, /* IPI Mask */
+
+ NODE_PL,
+ PM_SLAVE_FLAG_IS_SHAREABLE,
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+
+ /**********************************************************************/
+ /* PREALLOC SECTION */
+
+ PM_CONFIG_PREALLOC_SECTION_ID, /* Preallaoc SectionID */
+ 3U, /* No. of Masters*/
+
+/* Prealloc for psu_cortexa53_0 */
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK,
+ 11,
+ NODE_DDR,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+ NODE_L2,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+ NODE_OCM_BANK_0,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+ NODE_OCM_BANK_1,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+ NODE_OCM_BANK_2,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+ NODE_OCM_BANK_3,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+ NODE_I2C_1,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+ NODE_SD_1,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+ NODE_QSPI,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+ NODE_PL,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+ NODE_IPI_APU,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+
+ /* Prealloc for psu_cortexr5_0 */
+ PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK,
+ 3,
+ NODE_TCM_0_A,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+ NODE_TCM_0_B,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+ NODE_IPI_RPU_0,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+
+ /* Prealloc for psu_cortexr5_1 */
+ PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ 3,
+ NODE_TCM_1_A,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+ NODE_TCM_1_B,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+ NODE_IPI_RPU_1,
+ PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+ PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+
+
+ /**********************************************************************/
+ /* POWER SECTION */
+
+ PM_CONFIG_POWER_SECTION_ID, /* Power Section ID */
+ 4U, /* Number of power nodes */
+
+ NODE_APU, /* Power node ID */
+ PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */
+
+ NODE_RPU, /* Power node ID */
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */
+
+ NODE_FPD, /* Power node ID */
+ PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */
+
+ NODE_PLD, /* Power node ID */
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */
+
+
+ /**********************************************************************/
+ /* RESET SECTION */
+
+ PM_CONFIG_RESET_SECTION_ID, /* Reset Section ID */
+ 120U, /* Number of resets */
+
+ XILPM_RESET_PCIE_CFG, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_PCIE_BRIDGE, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_PCIE_CTRL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_DP, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_SWDT_CRF, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_AFI_FM5, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_AFI_FM4, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_AFI_FM3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_AFI_FM2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_AFI_FM1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_AFI_FM0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GDMA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPU_PP1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPU_PP0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPU, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GT, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_SATA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_ACPU3_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_ACPU2_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_ACPU1_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_ACPU0_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_APU_L2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_ACPU3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_ACPU2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_ACPU1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_ACPU0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_DDR, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_APM_FPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_SOFT, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GEM0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GEM1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GEM2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GEM3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_QSPI, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_UART0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_UART1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_SPI0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_SPI1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_SDIO0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_SDIO1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_CAN0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_CAN1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_I2C0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_I2C1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_TTC0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_TTC1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_TTC2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_TTC3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_SWDT_CRL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_NAND, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_ADMA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPIO, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_IOU_CC, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_TIMESTAMP, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_RPU_R50, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_RPU_R51, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_RPU_AMBA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_OCM, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_RPU_PGE, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_USB0_CORERESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_USB1_CORERESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_USB0_HIBERRESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_USB1_HIBERRESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_USB0_APB, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_USB1_APB, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_IPI, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_APM_LPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_RTC, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_SYSMON, 0,
+ XILPM_RESET_AFI_FM6, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_LPD_SWDT, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_FPD, PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK,
+ XILPM_RESET_RPU_DBG1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_RPU_DBG0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_DBG_LPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_DBG_FPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_APLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_DPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_VPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_IOPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_RPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_4, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_5, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_6, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_7, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_8, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_9, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_10, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_11, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_12, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_13, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_14, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_15, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_16, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_17, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_18, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_19, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_20, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_21, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_22, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_23, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_24, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_25, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_26, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_27, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_28, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_29, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_30, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPO3_PL_31, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_RPU_LS, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_PS_ONLY, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_PL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPIO5_EMIO_92, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPIO5_EMIO_93, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPIO5_EMIO_94, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+ XILPM_RESET_GPIO5_EMIO_95, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+
+ /**********************************************************************/
+ /* SET CONFIG SECTION */
+ PM_CONFIG_SET_CONFIG_SECTION_ID, /* Set Config Section ID */
+ 0U, /* Permissions to load base config object */
+ 0U, /* Permissions to load overlay config object */
+
+ /**********************************************************************/
+ /* SHUTDOWN SECTION */
+
+ PM_CONFIG_SHUTDOWN_SECTION_ID, /* Shutdown Section ID */
+ PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* System Shutdown/Restart Permission */
+
+ /**********************************************************************/
+ /* GPO SECTION */
+ PM_CONFIG_GPO_SECTION_ID, /* GPO Section ID */
+ PM_CONFIG_GPO1_BIT_2_MASK |
+ PM_CONFIG_GPO1_MIO_PIN_34_MAP |
+ PM_CONFIG_GPO1_MIO_PIN_35_MAP |
+ 0, /* State of GPO pins */
+};
+#if defined (__ICCARM__)
+#pragma language=restore
+#endif
+
diff --git a/board/zynqmp/kria/kv260/uboot.fragment b/board/zynqmp/kria/kv260/uboot.fragment
new file mode 100644
index 0000000000..e1aca68692
--- /dev/null
+++ b/board/zynqmp/kria/kv260/uboot.fragment
@@ -0,0 +1 @@
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-smk-k26-revA"
diff --git a/board/zynqmp/kria/post-build.sh b/board/zynqmp/kria/post-build.sh
new file mode 100755
index 0000000000..9fd8bbf2c8
--- /dev/null
+++ b/board/zynqmp/kria/post-build.sh
@@ -0,0 +1,8 @@
+#!/bin/sh
+
+# genimage will need to find the extlinux.conf
+# in the binaries directory
+
+BOARD_DIR="$(dirname $0)"
+
+install -m 0644 -D $BOARD_DIR/extlinux.conf $BINARIES_DIR/extlinux.conf
diff --git a/board/zynqmp/kria/readme.txt b/board/zynqmp/kria/readme.txt
new file mode 100644
index 0000000000..a3a4b5e65a
--- /dev/null
+++ b/board/zynqmp/kria/readme.txt
@@ -0,0 +1,78 @@
+**************************************************
+Xilinx Kria SOM Starter Kits - ZynqMP SoC
+**************************************************
+
+This document describes the Buildroot support for the Kria
+KV260 starter kit by Xilinx, based on Kria SOM including the
+Zynq UltraScale+ MPSoC (aka ZynqMP). It has been tested with
+the KV260 production board.
+
+Evaluation board features can be found here with the link below.
+
+KV260:
+https://www.xilinx.com/products/boards-and-kits/kv260.html
+
+How to build it
+===============
+
+Configure Buildroot:
+
+ $ make zynqmp_kria_kv260_defconfig
+
+Compile everything and build the rootfs image:
+
+ $ make
+
+Result of the build
+-------------------
+
+After building, you should get a tree like this:
+
+ output/images/
+ +-- atf-uboot.ub
+ +-- bl31.bin
+ +-- boot.bin
+ +-- boot.vfat
+ +-- Image
+ +-- rootfs.ext2
+ +-- rootfs.ext4 -> rootfs.ext2
+ +-- sdcard.img
+ +-- system.dtb -> smk-k26-revA-sck-kv-g-revB.dtb
+ +-- u-boot.itb
+ `-- smk-k26-revA-sck-kv-g-revB.dtb
+
+How to write the SD card
+========================
+
+WARNING! This will destroy all the card content. Use with care!
+
+The sdcard.img file is a complete bootable image ready to be written
+on the boot medium. To install it, simply copy the image to an SD
+card:
+
+ # dd if=output/images/sdcard.img of=/dev/sdX
+
+Where 'sdX' is the device node of the SD.
+
+Eject the SD card, insert it in the board, and power it up.
+
+How to write the boot.bn to QSPI boot flash
+===========================================
+
+The Kria SOMs are preconfigured to boot initially from QSPI.
+This makes these boards different from other ZynqMP boards
+in that the boot.bin needs to be flashed into the QSPI boot
+flash such that the U-Boot SPL can then load all of the
+remaining images from the SD card.
+
+In addition, the KV260 Starter Kit QSPI comes pre-flashed with
+a utility designed to make updating the QSPI flash memory
+easier.
+
+Instructions for using these utilities to update the boot.bin
+in QSPI flash can be found on the wiki link below.
+
+https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM#Boot-Firmware-Updates
+
+It is possible to boot the Buildroot generated SD card image without
+updating the QSPI boot.bin image, so this is an optional step.
diff --git a/configs/zynqmp_kria_kv260_defconfig b/configs/zynqmp_kria_kv260_defconfig
new file mode 100644
index 0000000000..d4a72a0d19
--- /dev/null
+++ b/configs/zynqmp_kria_kv260_defconfig
@@ -0,0 +1,37 @@
+BR2_aarch64=y
+BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_15=y
+BR2_ROOTFS_POST_BUILD_SCRIPT="board/zynqmp/kria/post-build.sh"
+BR2_ROOTFS_POST_IMAGE_SCRIPT="board/zynqmp/post-image.sh"
+BR2_LINUX_KERNEL=y
+BR2_LINUX_KERNEL_CUSTOM_TARBALL=y
+BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,linux-xlnx,xlnx_rebase_v5.15_LTS_2022.1)/xlnx_rebase_v5.15_LTS_2022.1.tar.gz"
+BR2_LINUX_KERNEL_DEFCONFIG="xilinx_zynqmp"
+BR2_LINUX_KERNEL_DTS_SUPPORT=y
+BR2_LINUX_KERNEL_INTREE_DTS_NAME="xilinx/smk-k26-revA-sck-kv-g-revB"
+BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y
+BR2_TARGET_ROOTFS_EXT2=y
+BR2_TARGET_ROOTFS_EXT2_4=y
+# BR2_TARGET_ROOTFS_TAR is not set
+BR2_TARGET_ARM_TRUSTED_FIRMWARE=y
+BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL=y
+BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,arm-trusted-firmware,xlnx_rebase_v2.6_2022.1)/xlnx_rebase_v2.6_2022.1.tar.gz"
+BR2_TARGET_ARM_TRUSTED_FIRMWARE_PLATFORM="zynqmp"
+BR2_TARGET_ARM_TRUSTED_FIRMWARE_BL31_UBOOT=y
+BR2_TARGET_UBOOT=y
+BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y
+BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
+BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,u-boot-xlnx,xlnx_rebase_v2022.01_2022.1)/xlnx_rebase_v2022.01_2022.1.tar.gz"
+BR2_TARGET_UBOOT_BOARD_DEFCONFIG="xilinx_zynqmp_virt"
+BR2_TARGET_UBOOT_CONFIG_FRAGMENT_FILES="board/zynqmp/kria/kv260/uboot.fragment"
+BR2_TARGET_UBOOT_NEEDS_DTC=y
+BR2_TARGET_UBOOT_NEEDS_OPENSSL=y
+BR2_TARGET_UBOOT_SPL=y
+BR2_TARGET_UBOOT_SPL_NAME="spl/boot.bin"
+BR2_TARGET_UBOOT_ZYNQMP=y
+BR2_TARGET_UBOOT_ZYNQMP_PMUFW="https://github.com/lucaceresoli/zynqmp-pmufw-binaries/raw/v2022.1/bin/pmufw-v2022.1.bin"
+BR2_TARGET_UBOOT_ZYNQMP_PM_CFG="board/zynqmp/kria/kv260/pm_cfg_obj.c"
+BR2_TARGET_UBOOT_FORMAT_ITB=y
+BR2_TARGET_UBOOT_NEEDS_ATF_BL31=y
+BR2_PACKAGE_HOST_DOSFSTOOLS=y
+BR2_PACKAGE_HOST_GENIMAGE=y
+BR2_PACKAGE_HOST_MTOOLS=y
--
2.17.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Buildroot] [PATCH v1 2/2] DEVELOPERS update
2022-05-05 15:54 [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig Neal Frager via buildroot
@ 2022-05-05 15:54 ` Neal Frager via buildroot
2022-05-05 19:49 ` Arnout Vandecappelle
2022-05-06 19:22 ` Peter Korsgaard
2022-05-06 11:17 ` [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig Wesley Revens
2022-05-06 19:22 ` Peter Korsgaard
2 siblings, 2 replies; 28+ messages in thread
From: Neal Frager via buildroot @ 2022-05-05 15:54 UTC (permalink / raw)
To: buildroot; +Cc: luca, giulio.benetti, michal.simek, Neal Frager
Updating Neal Frager in the DEVELOPERS file.
Signed-off-by: Neal Frager <neal.frager@amd.com>
---
DEVELOPERS | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/DEVELOPERS b/DEVELOPERS
index 292b919137..861496fb9d 100644
--- a/DEVELOPERS
+++ b/DEVELOPERS
@@ -2100,8 +2100,13 @@ F: package/pkg-qmake.mk
F: package/qt5/qt5opcua/
N: Neal Frager <neal.frager@amd.com>
+F: board/zynq/
F: board/zynqmp/
+F: board/zynqmp/kria/
+F: configs/zynq_zc706_defconfig
F: configs/zynqmp_zcu102_defconfig
+F: configs/zynqmp_zcu106_defconfig
+F: configs/zynqmp_kria_kv260_defconfig
N: Nicola Di Lieto <nicola.dilieto@gmail.com>
F: package/uacme/
--
2.17.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [Buildroot] [PATCH v1 2/2] DEVELOPERS update
2022-05-05 15:54 ` [Buildroot] [PATCH v1 2/2] DEVELOPERS update Neal Frager via buildroot
@ 2022-05-05 19:49 ` Arnout Vandecappelle
2022-05-06 19:22 ` Peter Korsgaard
1 sibling, 0 replies; 28+ messages in thread
From: Arnout Vandecappelle @ 2022-05-05 19:49 UTC (permalink / raw)
To: Neal Frager, buildroot; +Cc: luca, giulio.benetti, michal.simek
On 05/05/2022 17:54, Neal Frager via buildroot wrote:
> Updating Neal Frager in the DEVELOPERS file.
>
> Signed-off-by: Neal Frager <neal.frager@amd.com>
> ---
> DEVELOPERS | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/DEVELOPERS b/DEVELOPERS
> index 292b919137..861496fb9d 100644
> --- a/DEVELOPERS
> +++ b/DEVELOPERS
> @@ -2100,8 +2100,13 @@ F: package/pkg-qmake.mk
> F: package/qt5/qt5opcua/
>
> N: Neal Frager <neal.frager@amd.com>
> +F: board/zynq/
> F: board/zynqmp/
> +F: board/zynqmp/kria/
This is already comprised in board/zynqmp/ above, so no need.
Regards,
Arnout
> +F: configs/zynq_zc706_defconfig
> F: configs/zynqmp_zcu102_defconfig
> +F: configs/zynqmp_zcu106_defconfig
> +F: configs/zynqmp_kria_kv260_defconfig
>
> N: Nicola Di Lieto <nicola.dilieto@gmail.com>
> F: package/uacme/
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Buildroot] [PATCH v1 2/2] DEVELOPERS update
2022-05-05 15:54 ` [Buildroot] [PATCH v1 2/2] DEVELOPERS update Neal Frager via buildroot
2022-05-05 19:49 ` Arnout Vandecappelle
@ 2022-05-06 19:22 ` Peter Korsgaard
1 sibling, 0 replies; 28+ messages in thread
From: Peter Korsgaard @ 2022-05-06 19:22 UTC (permalink / raw)
To: Neal Frager; +Cc: luca, giulio.benetti, michal.simek, buildroot
>>>>> "Neal" == Neal Frager <neal.frager@amd.com> writes:
> Updating Neal Frager in the DEVELOPERS file.
> Signed-off-by: Neal Frager <neal.frager@amd.com>
Committed, thanks.
--
Bye, Peter Korsgaard
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig
2022-05-05 15:54 [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig Neal Frager via buildroot
2022-05-05 15:54 ` [Buildroot] [PATCH v1 2/2] DEVELOPERS update Neal Frager via buildroot
@ 2022-05-06 11:17 ` Wesley Revens
2022-05-06 11:30 ` Neal Frager
[not found] ` <51fb4a8c-cd8c-9db0-76e4-5461e72871f8@xilinx.com>
2022-05-06 19:22 ` Peter Korsgaard
2 siblings, 2 replies; 28+ messages in thread
From: Wesley Revens @ 2022-05-06 11:17 UTC (permalink / raw)
To: Neal Frager, buildroot; +Cc: luca, giulio.benetti, michal.simek
Hi Neal,
I have been working on a Buildroot image for the Kria recently so my
company can evaluate the K26 SOM.
I reached a similar position to what has been included in your patch
however I have not been able to
get the Kria to boot using the U-Boot SPL.
I have tried out your patch and found that the Linux kernel is booting
fine from the SD card using
the pre-programmed boot.bin that is already present on the Kria.
However, after building using your patch,
I tried uploading the boot.bin that appears in buildroot/output/images
to my Kria using the
"Boot Image Recovery Tool" web UI that runs on the Kria if you hold down
the FWUEN button
during reset of the board. On boot, I then get the following output from
U-Boot SPL:
U-Boot SPL 2022.01 (May 06 2022 - 11:21:55 +0100)
PMUFW: v1.1
Loading new PMUFW cfg obj (2016 bytes)
Silicon version: 3
EL Level: EL3
Chip ID: xck26
Multiboot: 64
Trying to boot from SPI
Then nothing else happens.
There is a big difference in the file sizes for the boot.bin from
buildroot/output/images and the BOOT.BIN
I downloaded from
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM#Boot-Firmware-Updates
so I am obviously missing something somewhere. I think all the
components are being built but I'm not sure
they are being packaged in a similar way to how the pre-loaded boot.bin
is laid out (or I am using the wrong output file!)
In my own testing I was able to test the u-boot.img produced by my
Buildroot build but I had to use the
Xilinx bootgen tools and use the Xilinx fsbl rather than the U-Boot SPL.
In future, we would like to be able to bypass this step and just use
whatever Buildroot produces.
I was wondering if you could point me in the right direction.
Regards,
Wesley
On 05/05/2022 16:54, Neal Frager via buildroot wrote:
> This patch adds support for Xilinx Kria KV260 starter kit.
>
> KV260 features can be found here:
> https://www.xilinx.com/products/boards-and-kits/kv260.html
>
> While the Kria SOM is based on a ZynqMP SoC, there are some key
> boot config differences from the other ZynqMP evaluation boards.
>
> 1. There are no boot switches on Kria SOMs. The boot mode is thus
> hard configured for QSPI flash. A pre-programmed boot.bin comes
> with every Starter Kit. U-Boot can then find the Linux kernel and
> file system on the SD card.
>
> Optional instructions for updating the boot.bin in the QSPI flash
> can be found in the readme.txt file and the link below.
>
> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM
>
> 2. Kria SOMs use UART1 for the console instead of UART0. For this
> reason, Kria Starter Kits will use a separate extlinux.conf file
> from other ZynqMP evaluation boards.
<snip>
To unsubscribe click: http://link.sonifex.co.uk/us/?e=1nXvxxPuEp2Zja.ddedfjkAKO6ol
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig
2022-05-06 11:17 ` [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig Wesley Revens
@ 2022-05-06 11:30 ` Neal Frager
[not found] ` <51fb4a8c-cd8c-9db0-76e4-5461e72871f8@xilinx.com>
1 sibling, 0 replies; 28+ messages in thread
From: Neal Frager @ 2022-05-06 11:30 UTC (permalink / raw)
To: Wesley Revens; +Cc: luca, giulio.benetti, buildroot, michal.simek, Neal Frager
Hi Wesley,
> Le 6 mai 2022 à 13:18, Wesley Revens <wesley@sonifex.co.uk> a écrit :
>
> CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or responding to this email.
>
>
> [CAUTION: External Email]
>
> Hi Neal,
>
> I have been working on a Buildroot image for the Kria recently so my
> company can evaluate the K26 SOM.
> I reached a similar position to what has been included in your patch
> however I have not been able to
> get the Kria to boot using the U-Boot SPL.
>
> I have tried out your patch and found that the Linux kernel is booting
> fine from the SD card using
> the pre-programmed boot.bin that is already present on the Kria.
> However, after building using your patch,
> I tried uploading the boot.bin that appears in buildroot/output/images
> to my Kria using the
> "Boot Image Recovery Tool" web UI that runs on the Kria if you hold down
> the FWUEN button
> during reset of the board. On boot, I then get the following output from
> U-Boot SPL:
>
> U-Boot SPL 2022.01 (May 06 2022 - 11:21:55 +0100)
> PMUFW: v1.1
> Loading new PMUFW cfg obj (2016 bytes)
> Silicon version: 3
> EL Level: EL3
> Chip ID: xck26
> Multiboot: 64
> Trying to boot from SPI
>
> Then nothing else happens.
>
> There is a big difference in the file sizes for the boot.bin from
> buildroot/output/images and the BOOT.BIN
> I downloaded from
> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM#Boot-Firmware-Updates
> so I am obviously missing something somewhere. I think all the
> components are being built but I'm not sure
> they are being packaged in a similar way to how the pre-loaded boot.bin
> is laid out (or I am using the wrong output file!)
>
> In my own testing I was able to test the u-boot.img produced by my
> Buildroot build but I had to use the
> Xilinx bootgen tools and use the Xilinx fsbl rather than the U-Boot SPL.
>
> In future, we would like to be able to bypass this step and just use
> whatever Buildroot produces.
> I was wondering if you could point me in the right direction.
>
> Regards,
>
> Wesley
I would be happy to help you here. One of the big differences between the preprogrammed boot.bin and the one built by buildroot is that it uses the FSBL instead of the SPL.
This means that u-boot itself gets packaged inside the boot.bin in the prepackaged version based on the FSBL.
In the SPL case, you need to write both the boot.bin and the u-boot.itb to the QSPI flash because u-boot is not included in the boot.bin, in this case.
To fix this better though, I may implement a patch for the SPL so that it looks for the u-boot.itb in the SD card instead of the QSPI flash. This would probably be a better solution.
>
>
>> On 05/05/2022 16:54, Neal Frager via buildroot wrote:
>> This patch adds support for Xilinx Kria KV260 starter kit.
>>
>> KV260 features can be found here:
>> https://www.xilinx.com/products/boards-and-kits/kv260.html
>>
>> While the Kria SOM is based on a ZynqMP SoC, there are some key
>> boot config differences from the other ZynqMP evaluation boards.
>>
>> 1. There are no boot switches on Kria SOMs. The boot mode is thus
>> hard configured for QSPI flash. A pre-programmed boot.bin comes
>> with every Starter Kit. U-Boot can then find the Linux kernel and
>> file system on the SD card.
>>
>> Optional instructions for updating the boot.bin in the QSPI flash
>> can be found in the readme.txt file and the link below.
>>
>> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM
>>
>> 2. Kria SOMs use UART1 for the console instead of UART0. For this
>> reason, Kria Starter Kits will use a separate extlinux.conf file
>> from other ZynqMP evaluation boards.
> <snip>
> To unsubscribe click: http://link.sonifex.co.uk/us/?e=1nXvxxPuEp2Zja.ddePfjkAnBV-Z
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^ permalink raw reply [flat|nested] 28+ messages in thread
[parent not found: <51fb4a8c-cd8c-9db0-76e4-5461e72871f8@xilinx.com>]
* Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig
[not found] ` <51fb4a8c-cd8c-9db0-76e4-5461e72871f8@xilinx.com>
@ 2022-05-09 6:23 ` Neal Frager
[not found] ` <dd608132-245a-32b7-7d27-f267c1524fee@xilinx.com>
0 siblings, 1 reply; 28+ messages in thread
From: Neal Frager @ 2022-05-09 6:23 UTC (permalink / raw)
To: Michal Simek, Wesley Revens, Neal Frager, buildroot
Cc: luca, giulio.benetti, michal.simek
Hi Michal,
>
> Hi Neal,
>
> I have been working on a Buildroot image for the Kria recently so my
> company can evaluate the K26 SOM.
> I reached a similar position to what has been included in your patch
> however I have not been able to get the Kria to boot using the U-Boot
> SPL.
>
> I have tried out your patch and found that the Linux kernel is booting
> fine from the SD card using the pre-programmed boot.bin that is
> already present on the Kria.
> However, after building using your patch, I tried uploading the
> boot.bin that appears in buildroot/output/images to my Kria using the
> "Boot Image Recovery Tool" web UI that runs on the Kria if you hold
> down the FWUEN button during reset of the board. On boot, I then get
> the following output from U-Boot SPL:
>
> U-Boot SPL 2022.01 (May 06 2022 - 11:21:55 +0100)
> PMUFW: v1.1
> Loading new PMUFW cfg obj (2016 bytes) Silicon version: 3 EL
> Level: EL3 Chip ID: xck26
> Multiboot: 64
> Trying to boot from SPI
>
> Then nothing else happens.
>
> There is a big difference in the file sizes for the boot.bin from
> buildroot/output/images and the BOOT.BIN I downloaded from
> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+
> K26+SOM#Boot-Firmware-Updates
>
> so I am obviously missing something somewhere. I think all the
> components are being built but I'm not sure they are being packaged in
> a similar way to how the pre-loaded boot.bin is laid out (or I am
> using the wrong output file!)
>
> In my own testing I was able to test the u-boot.img produced by my
> Buildroot build but I had to use the Xilinx bootgen tools and use the
> Xilinx fsbl rather than the U-Boot SPL.
>
> In future, we would like to be able to bypass this step and just use
> whatever Buildroot produces.
> I was wondering if you could point me in the right direction.
> Not quite sure what Neil is using but of course you can use SPL with Kria SOM and I am using it on daily basis.
> It really depends what exactly you want do and do some alignments to u-boot config.
> Let's assume you have starter kit with preinstalled A/B updates you need to say if you want to have this functionality or not.
> I personally didn't try to use A/B with SPL and using partition for image A for boot.bin (SPL only) and partition B for image.itb.
> That being said you need to tell SPL where u-boot.itb is placed in QSPI.
> It means you need to setup CONFIG_SYS_SPI_U_BOOT_OFFS=0xF80000 as offset to place image to this location.
> If you use update utility then write u-boot.itb (you need to rename it because gui expects *.bin filename) first to imageB and then boot.bin to Image A.
> Compare to the latest upstream version you need enable some configs.
> CONFIG_DEFAULT_DEVICE_TREE="zynqmp-smk-k26-revA"
> CONFIG_ENV_SIZE=0x40000
> CONFIG_SYS_SPI_U_BOOT_OFFS=0xF80000
These configs are clear and specific to the Kria SOM.
> CONFIG_DTB_RESELECT=y
> CONFIG_MULTI_DTB_FIT=y
> CONFIG_ENV_IS_NOWHERE=y (only)
> CONFIG_USE_DEFAULT_ENV_FILE=y
> CONFIG_DEFAULT_ENV_FILE="vars"
> CONFIG_DMA=y
> CONFIG_XILINX_DPDMA=y
> CONFIG_PHY=y
> CONFIG_PHY_XILINX_ZYNQMP=y
> CONFIG_PINCTRL=y
> CONFIG_PINCONF=y
> CONFIG_POWER_DOMAIN=y
> CONFIG_ZYNQMP_POWER_DOMAIN=y
> CONFIG_DM_RESET=y
> CONFIG_RESET_ZYNQMP=y
> CONFIG_VIDEO_ZYNQMP_DPSUB=y
These configs do not appear specific to Kria. Should we be using them for other zynqmp boards as well?
Such as the zcu102 and zcu106?
We are currently just using the xilinx_zynqmp_virt_defconfig with the CONFIG_DEFAULT_DEVICE_TREE
for each individual board. Is this sufficient for the zcu102 and zcu106 boards?
Best regards,
Neal Frager
AMD
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https://lists.buildroot.org/mailman/listinfo/buildroot
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig
2022-05-05 15:54 [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig Neal Frager via buildroot
2022-05-05 15:54 ` [Buildroot] [PATCH v1 2/2] DEVELOPERS update Neal Frager via buildroot
2022-05-06 11:17 ` [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig Wesley Revens
@ 2022-05-06 19:22 ` Peter Korsgaard
2022-05-07 6:26 ` Neal Frager
[not found] ` <32c2dc3c-10c1-cda7-219f-f3753940f294@xilinx.com>
2 siblings, 2 replies; 28+ messages in thread
From: Peter Korsgaard @ 2022-05-06 19:22 UTC (permalink / raw)
To: Neal Frager; +Cc: luca, giulio.benetti, michal.simek, buildroot
>>>>> "Neal" == Neal Frager <neal.frager@amd.com> writes:
> This patch adds support for Xilinx Kria KV260 starter kit.
> KV260 features can be found here:
> https://www.xilinx.com/products/boards-and-kits/kv260.html
> While the Kria SOM is based on a ZynqMP SoC, there are some key
> boot config differences from the other ZynqMP evaluation boards.
> 1. There are no boot switches on Kria SOMs. The boot mode is thus
> hard configured for QSPI flash. A pre-programmed boot.bin comes
> with every Starter Kit. U-Boot can then find the Linux kernel and
> file system on the SD card.
> Optional instructions for updating the boot.bin in the QSPI flash
> can be found in the readme.txt file and the link below.
> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM
> 2. Kria SOMs use UART1 for the console instead of UART0. For this
> reason, Kria Starter Kits will use a separate extlinux.conf file
> from other ZynqMP evaluation boards.
> Signed-off-by: Neal Frager <neal.frager@amd.com>
> ---
> board/zynqmp/kria/extlinux.conf | 4 +
> board/zynqmp/kria/kv260/pm_cfg_obj.c | 556 +++++++++++++++++++++++++
> board/zynqmp/kria/kv260/uboot.fragment | 1 +
Are you planning to also support other kria boards given the kria/
subdir?
> board/zynqmp/kria/post-build.sh | 8 +
The post-build.sh copy is not so nice, but ok.
Committed, thanks.
--
Bye, Peter Korsgaard
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig
2022-05-06 19:22 ` Peter Korsgaard
@ 2022-05-07 6:26 ` Neal Frager
2022-05-07 21:01 ` Peter Korsgaard
[not found] ` <32c2dc3c-10c1-cda7-219f-f3753940f294@xilinx.com>
1 sibling, 1 reply; 28+ messages in thread
From: Neal Frager @ 2022-05-07 6:26 UTC (permalink / raw)
To: Peter Korsgaard
Cc: luca, giulio.benetti, buildroot, michal.simek, Neal Frager
Hi Peter,
> Le 6 mai 2022 à 21:22, Peter Korsgaard <peter@korsgaard.com> a écrit :
>
> CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or responding to this email.
>
>
> [CAUTION: External Email]
>
>>>>>> "Neal" == Neal Frager <neal.frager@amd.com> writes:
>
>> This patch adds support for Xilinx Kria KV260 starter kit.
>> KV260 features can be found here:
>> https://www.xilinx.com/products/boards-and-kits/kv260.html
>
>> While the Kria SOM is based on a ZynqMP SoC, there are some key
>> boot config differences from the other ZynqMP evaluation boards.
>
>> 1. There are no boot switches on Kria SOMs. The boot mode is thus
>> hard configured for QSPI flash. A pre-programmed boot.bin comes
>> with every Starter Kit. U-Boot can then find the Linux kernel and
>> file system on the SD card.
>
>> Optional instructions for updating the boot.bin in the QSPI flash
>> can be found in the readme.txt file and the link below.
>
>> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM
>
>> 2. Kria SOMs use UART1 for the console instead of UART0. For this
>> reason, Kria Starter Kits will use a separate extlinux.conf file
>> from other ZynqMP evaluation boards.
>
>> Signed-off-by: Neal Frager <neal.frager@amd.com>
>> ---
>> board/zynqmp/kria/extlinux.conf | 4 +
>> board/zynqmp/kria/kv260/pm_cfg_obj.c | 556 +++++++++++++++++++++++++
>> board/zynqmp/kria/kv260/uboot.fragment | 1 +
>
> Are you planning to also support other kria boards given the kria/
> subdir?
Yes, there is another Kria carrier board we are about to announce. It is not public yet, but I setup the directories in planning for this.
>
>> board/zynqmp/kria/post-build.sh | 8 +
>
> The post-build.sh copy is not so nice, but ok.
I agree. If you have a better solution, I would be happy to have any suggestions.
>
> Committed, thanks.
>
> --
> Bye, Peter Korsgaard
Best regards,
Neal Frager
AMD
_______________________________________________
buildroot mailing list
buildroot@buildroot.org
https://lists.buildroot.org/mailman/listinfo/buildroot
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig
2022-05-07 6:26 ` Neal Frager
@ 2022-05-07 21:01 ` Peter Korsgaard
2022-05-08 6:46 ` Neal Frager
0 siblings, 1 reply; 28+ messages in thread
From: Peter Korsgaard @ 2022-05-07 21:01 UTC (permalink / raw)
To: Neal Frager; +Cc: luca, giulio.benetti, buildroot, michal.simek, Neal Frager
>>>>> "Neal" == Neal Frager <nealf@xilinx.com> writes:
Hi,
>> Are you planning to also support other kria boards given the kria/
>> subdir?
> Yes, there is another Kria carrier board we are about to announce. It
> is not public yet, but I setup the directories in planning for this.
Ahh, sounds interesting ;)
>>
>>> board/zynqmp/kria/post-build.sh | 8 +
>>
>> The post-build.sh copy is not so nice, but ok.
> I agree. If you have a better solution, I would be happy to have any suggestions.
There's a number of options, E.G. we could use a symlink to the existing
script or pass the file to copy as an argument in
BR2_ROOTFS_POST_SCRIPT_ARGS. U-Boot afaik also expands variable
references in the extlinux files, so if there is already a U-Boot
variable with the serial port name then that could be used.
--
Bye, Peter Korsgaard
_______________________________________________
buildroot mailing list
buildroot@buildroot.org
https://lists.buildroot.org/mailman/listinfo/buildroot
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig
2022-05-07 21:01 ` Peter Korsgaard
@ 2022-05-08 6:46 ` Neal Frager
2022-05-08 9:05 ` Peter Korsgaard
0 siblings, 1 reply; 28+ messages in thread
From: Neal Frager @ 2022-05-08 6:46 UTC (permalink / raw)
To: Peter Korsgaard
Cc: luca, giulio.benetti, buildroot, michal.simek, Neal Frager
Hi Peter,
> Le 7 mai 2022 à 23:01, Peter Korsgaard <peter@korsgaard.com> a écrit :
>
> CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or responding to this email.
>
>
>>>>>> "Neal" == Neal Frager <nealf@xilinx.com> writes:
>
> Hi,
>
>>> Are you planning to also support other kria boards given the kria/
>>> subdir?
>
>> Yes, there is another Kria carrier board we are about to announce. It
>> is not public yet, but I setup the directories in planning for this.
>
> Ahh, sounds interesting ;)
>
>>>
>>>> board/zynqmp/kria/post-build.sh | 8 +
>>>
>>> The post-build.sh copy is not so nice, but ok.
>
>> I agree. If you have a better solution, I would be happy to have any suggestions.
>
> There's a number of options, E.G. we could use a symlink to the existing
> script or pass the file to copy as an argument in
> BR2_ROOTFS_POST_SCRIPT_ARGS. U-Boot afaik also expands variable
> references in the extlinux files, so if there is already a U-Boot
> variable with the serial port name then that could be used.
Thank you for this idea. Do you have a solution for the SD card file system as well?
The Kria Starter kits use mmc1 instead of mmc0 for the SD card, so this is also different in the extllinux.conf files.
>
> --
> Bye, Peter Korsgaard
Thanks for your help!
Best regards,
Neal Frager
AMD
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig
2022-05-08 6:46 ` Neal Frager
@ 2022-05-08 9:05 ` Peter Korsgaard
2022-05-10 9:15 ` Neal Frager
0 siblings, 1 reply; 28+ messages in thread
From: Peter Korsgaard @ 2022-05-08 9:05 UTC (permalink / raw)
To: Neal Frager; +Cc: luca, giulio.benetti, buildroot, michal.simek, Neal Frager
>>>>> "Neal" == Neal Frager <nealf@xilinx.com> writes:
Hi,
> Thank you for this idea. Do you have a solution for the SD card file system as well?
> The Kria Starter kits use mmc1 instead of mmc0 for the SD card, so
> this is also different in the extllinux.conf files.
I believe you can use $devnum for that. Have a look at distro_bootcmd.
--
Bye, Peter Korsgaard
_______________________________________________
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buildroot@buildroot.org
https://lists.buildroot.org/mailman/listinfo/buildroot
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig
2022-05-08 9:05 ` Peter Korsgaard
@ 2022-05-10 9:15 ` Neal Frager
0 siblings, 0 replies; 28+ messages in thread
From: Neal Frager @ 2022-05-10 9:15 UTC (permalink / raw)
To: Peter Korsgaard
Cc: luca, giulio.benetti, buildroot, michal.simek, Neal Frager
Hi Peter,
> Thank you for this idea. Do you have a solution for the SD card file system as well?
> The Kria Starter kits use mmc1 instead of mmc0 for the SD card, so > this is also different in the extllinux.conf files.
> I believe you can use $devnum for that. Have a look at distro_bootcmd.
Just a note about this. I have not forgotten the plan to clean up the zynqmp directory structure and possibly combine
zynqmp and kria post-build.sh scripts and extlinux.conf files.
I was just focused on fixing the functional issues first.
Now that the functional issues are resolved, my next step will be working on cleaning up the directory structure.
However, it may be a few days before I can get to this, as I have some business travel coming up.
Thanks!
Neal Frager
AMD
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^ permalink raw reply [flat|nested] 28+ messages in thread
[parent not found: <32c2dc3c-10c1-cda7-219f-f3753940f294@xilinx.com>]
* Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig
[not found] ` <32c2dc3c-10c1-cda7-219f-f3753940f294@xilinx.com>
@ 2022-05-09 8:14 ` Neal Frager
0 siblings, 0 replies; 28+ messages in thread
From: Neal Frager @ 2022-05-09 8:14 UTC (permalink / raw)
To: Michal Simek, Peter Korsgaard, Neal Frager
Cc: luca, giulio.benetti, michal.simek, buildroot
Hi Michal,
>
>>>>>> "Neal" == Neal Frager <neal.frager@amd.com> writes:
>
> > This patch adds support for Xilinx Kria KV260 starter kit.
> > KV260 features can be found here:
> > https://www.xilinx.com/products/boards-and-kits/kv260.html
>
> > While the Kria SOM is based on a ZynqMP SoC, there are some key
> > boot config differences from the other ZynqMP evaluation boards.
>
> > 1. There are no boot switches on Kria SOMs. The boot mode is thus
> > hard configured for QSPI flash. A pre-programmed boot.bin comes
> > with every Starter Kit. U-Boot can then find the Linux kernel and
> > file system on the SD card.
>
> > Optional instructions for updating the boot.bin in the QSPI flash
> > can be found in the readme.txt file and the link below.
>
> >
> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+
> K26+SOM
>
> > 2. Kria SOMs use UART1 for the console instead of UART0. For this
> > reason, Kria Starter Kits will use a separate extlinux.conf file
> > from other ZynqMP evaluation boards.
>
> > Signed-off-by: Neal Frager <neal.frager@amd.com>
> > ---
> > board/zynqmp/kria/extlinux.conf | 4 +
> > board/zynqmp/kria/kv260/pm_cfg_obj.c | 556 +++++++++++++++++++++++++
> > board/zynqmp/kria/kv260/uboot.fragment | 1 +
>
> Are you planning to also support other kria boards given the kria/
> subdir?
> you should think about structure in a way that it is kria SOM program. kv260 is xilinx designed carrier card for k26 som. It means any user can take k26 som and create own carrier card and maybe push this to buildroot to support this product.
> And also k26 itself has multiple variants. K26 on starter kit doesn't have EMMC on it. k26 production has emmc on it. There are also C and I variants also with encryption enabled/disabled.
> I don't think you should cover C/I or ED variants but definitely you should think how to handle different SOM types especially in connection to populated EMMC.
> It means
> board/zynqmp/kria/k26/...
> board/zynqmp/kria/k26/kv260/..
> board/zynqmp/kria/k26/custom/..
> and
> board/zynqmp/kria/k26-prod/...
> board/zynqmp/kria/k26-prod/...
> board/zynqmp/kria/k26-prod/kv260/..
> board/zynqmp/kria/k26-prod/custom/..
My objective with the buildroot defconfigs is just to give the community examples for how to build and run buildroot on our evaluation boards.
Developers will then need to modify these configurations when developing for their own hardware.
So looking at your proposed directory structure, I was not planning to cover the production SOMs.
My focus is thus only on supporting the starter kit configurations to give the community working examples.
However, you do raise a good point about the possibility of new Kria SOMs in the future.
Not all starter kits will necessarily be based on a K26 SOM.
With this feedback in mind, I am thinking of the following example structure:
board/zynqmp/k26/kv260
board/zynqmp/k26/<future starter kit based on k26 som>
board/zynqmp/<future som>/<future starter kit based on future som>
In other words, I am going to replace the kria directory with k26 including files for the k26 som that work for the various k26 som based starter kits.
What does everyone think of this proposal?
Best regards,
Neal Frager
AMD
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^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2022-05-10 9:15 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-05 15:54 [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig Neal Frager via buildroot
2022-05-05 15:54 ` [Buildroot] [PATCH v1 2/2] DEVELOPERS update Neal Frager via buildroot
2022-05-05 19:49 ` Arnout Vandecappelle
2022-05-06 19:22 ` Peter Korsgaard
2022-05-06 11:17 ` [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig Wesley Revens
2022-05-06 11:30 ` Neal Frager
[not found] ` <51fb4a8c-cd8c-9db0-76e4-5461e72871f8@xilinx.com>
2022-05-09 6:23 ` Neal Frager
[not found] ` <dd608132-245a-32b7-7d27-f267c1524fee@xilinx.com>
2022-05-09 9:14 ` Wesley Revens
2022-05-09 9:22 ` Neal Frager
2022-05-09 10:54 ` Wesley Revens
2022-05-09 11:00 ` Neal Frager
2022-05-09 11:19 ` Wesley Revens
2022-05-09 13:46 ` Neal Frager
2022-05-09 14:33 ` Wesley Revens
2022-05-09 14:41 ` Neal Frager
2022-05-09 14:58 ` Wesley Revens
2022-05-09 19:01 ` Neal Frager
2022-05-10 4:29 ` Neal Frager
2022-05-10 4:36 ` Neal Frager
2022-05-10 8:22 ` Wesley Revens
2022-05-10 8:26 ` Neal Frager
2022-05-06 19:22 ` Peter Korsgaard
2022-05-07 6:26 ` Neal Frager
2022-05-07 21:01 ` Peter Korsgaard
2022-05-08 6:46 ` Neal Frager
2022-05-08 9:05 ` Peter Korsgaard
2022-05-10 9:15 ` Neal Frager
[not found] ` <32c2dc3c-10c1-cda7-219f-f3753940f294@xilinx.com>
2022-05-09 8:14 ` Neal Frager
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