[Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Neal Frager via buildroot]

This patch adds support for Xilinx Kria KV260 starter kit.

KV260 features can be found here:
https://www.xilinx.com/products/boards-and-kits/kv260.html

While the Kria SOM is based on a ZynqMP SoC, there are some key
boot config differences from the other ZynqMP evaluation boards.

1. There are no boot switches on Kria SOMs. The boot mode is thus
hard configured for QSPI flash. A pre-programmed boot.bin comes
with every Starter Kit. U-Boot can then find the Linux kernel and
file system on the SD card.

Optional instructions for updating the boot.bin in the QSPI flash
can be found in the readme.txt file and the link below.

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM

2. Kria SOMs use UART1 for the console instead of UART0. For this
reason, Kria Starter Kits will use a separate extlinux.conf file
from other ZynqMP evaluation boards.

Signed-off-by: Neal Frager <neal.frager@amd.com>
---
 board/zynqmp/kria/extlinux.conf        |   4 +
 board/zynqmp/kria/kv260/pm_cfg_obj.c   | 556 +++++++++++++++++++++++++
 board/zynqmp/kria/kv260/uboot.fragment |   1 +
 board/zynqmp/kria/post-build.sh        |   8 +
 board/zynqmp/kria/readme.txt           |  78 ++++
 configs/zynqmp_kria_kv260_defconfig    |  37 ++
 6 files changed, 684 insertions(+)
 create mode 100644 board/zynqmp/kria/extlinux.conf
 create mode 100644 board/zynqmp/kria/kv260/pm_cfg_obj.c
 create mode 100644 board/zynqmp/kria/kv260/uboot.fragment
 create mode 100755 board/zynqmp/kria/post-build.sh
 create mode 100644 board/zynqmp/kria/readme.txt
 create mode 100644 configs/zynqmp_kria_kv260_defconfig

diff --git a/board/zynqmp/kria/extlinux.conf b/board/zynqmp/kria/extlinux.conf
new file mode 100644
index 0000000000..663aabb7c3
--- /dev/null
+++ b/board/zynqmp/kria/extlinux.conf
@@ -0,0 +1,4 @@
+label linux
+  kernel /Image
+  devicetree /system.dtb
+  append console=ttyPS1,115200 root=/dev/mmcblk1p2 rw rootwait
diff --git a/board/zynqmp/kria/kv260/pm_cfg_obj.c b/board/zynqmp/kria/kv260/pm_cfg_obj.c
new file mode 100644
index 0000000000..019df6e237
--- /dev/null
+++ b/board/zynqmp/kria/kv260/pm_cfg_obj.c
@@ -0,0 +1,556 @@
+/******************************************************************************
+* Copyright (c) 2017 - 2021 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+#include "xil_types.h"
+#include "pm_defs.h"
+
+#define PM_CONFIG_MASTER_SECTION_ID	0x101U
+#define PM_CONFIG_SLAVE_SECTION_ID	0x102U
+#define PM_CONFIG_PREALLOC_SECTION_ID	0x103U
+#define PM_CONFIG_POWER_SECTION_ID	0x104U
+#define PM_CONFIG_RESET_SECTION_ID	0x105U
+#define PM_CONFIG_SHUTDOWN_SECTION_ID	0x106U
+#define PM_CONFIG_SET_CONFIG_SECTION_ID	0x107U
+#define PM_CONFIG_GPO_SECTION_ID	0x108U
+
+#define PM_SLAVE_FLAG_IS_SHAREABLE	0x1U
+#define PM_MASTER_USING_SLAVE_MASK	0x2U
+
+#define PM_CONFIG_GPO1_MIO_PIN_34_MAP	(1U << 10U)
+#define PM_CONFIG_GPO1_MIO_PIN_35_MAP	(1U << 11U)
+#define PM_CONFIG_GPO1_MIO_PIN_36_MAP	(1U << 12U)
+#define PM_CONFIG_GPO1_MIO_PIN_37_MAP	(1U << 13U)
+
+#define PM_CONFIG_GPO1_BIT_2_MASK	(1U << 2U)
+#define PM_CONFIG_GPO1_BIT_3_MASK	(1U << 3U)
+#define PM_CONFIG_GPO1_BIT_4_MASK	(1U << 4U)
+#define PM_CONFIG_GPO1_BIT_5_MASK	(1U << 5U)
+
+#define SUSPEND_TIMEOUT	0xFFFFFFFFU
+
+#define PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK    0x00000001
+#define PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK    0x00000100
+#define PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK    0x00000200
+
+
+
+#if defined (__ICCARM__)
+#pragma language=save
+#pragma language=extended
+#endif
+#if defined (__GNUC__)
+    const u32 XPm_ConfigObject[] __attribute__((used, section(".sys_cfg_data"))) =
+#elif defined (__ICCARM__)
+#pragma location = ".sys_cfg_data"
+__root const u32 XPm_ConfigObject[] =
+#endif
+{
+	/**********************************************************************/
+	/* HEADER */
+	2,	/* Number of remaining words in the header */
+	8,	/* Number of sections included in config object */
+	1U,	/* Type of config object as base */
+	/**********************************************************************/
+	/* MASTER SECTION */
+	PM_CONFIG_MASTER_SECTION_ID, /* Master SectionID */
+	3U, /* No. of Masters*/
+
+	NODE_APU, /* Master Node ID */
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK, /* IPI Mask of this master */
+	SUSPEND_TIMEOUT, /* Suspend timeout */
+	PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Suspend permissions */
+	PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Wake permissions */
+
+	NODE_RPU_0, /* Master Node ID */
+	PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask of this master */
+	SUSPEND_TIMEOUT, /* Suspend timeout */
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Suspend permissions */
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Wake permissions */
+
+	NODE_RPU_1, /* Master Node ID */
+	PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask of this master */
+	SUSPEND_TIMEOUT, /* Suspend timeout */
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* Suspend permissions */
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* Wake permissions */
+
+
+	/**********************************************************************/
+	/* SLAVE SECTION */
+
+
+	PM_CONFIG_SLAVE_SECTION_ID,	/* Section ID */
+	49,				/* Number of slaves */
+
+	NODE_OCM_BANK_0,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_OCM_BANK_1,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_OCM_BANK_2,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_OCM_BANK_3,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_TCM_0_A,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask */
+
+	NODE_TCM_0_B,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask */
+
+	NODE_TCM_1_A,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_TCM_1_B,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_L2,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_GPU_PP_0,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_GPU_PP_1,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_USB_0,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_USB_1,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_TTC_0,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_TTC_1,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_TTC_2,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_TTC_3,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_SATA,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_ETH_0,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_ETH_1,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_ETH_2,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_ETH_3,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_UART_0,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_UART_1,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_SPI_0,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_SPI_1,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_I2C_0,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_I2C_1,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_SD_0,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_SD_1,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_DP,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_GDMA,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_ADMA,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_NAND,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_QSPI,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_GPIO,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_CAN_0,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_CAN_1,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_EXTERN,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_DDR,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_IPI_APU,
+	0U,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK, /* IPI Mask */
+
+	NODE_IPI_RPU_0,
+	0U,
+	PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask */
+
+	NODE_IPI_RPU_1,
+	0U,
+	PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_GPU,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_PCIE,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_PCAP,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_RTC,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_VCU,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_PL,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+
+	/**********************************************************************/
+	/* PREALLOC SECTION */
+
+	PM_CONFIG_PREALLOC_SECTION_ID, /* Preallaoc SectionID */
+	3U, /* No. of Masters*/
+
+/* Prealloc for psu_cortexa53_0 */
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK,
+	11,
+	NODE_DDR,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_L2,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_OCM_BANK_0,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_OCM_BANK_1,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_OCM_BANK_2,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_OCM_BANK_3,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_I2C_1,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_SD_1,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_QSPI,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_PL,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_IPI_APU,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+
+	/* Prealloc for psu_cortexr5_0 */
+	PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK,
+	3,
+	NODE_TCM_0_A,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_TCM_0_B,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_IPI_RPU_0,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+
+	/* Prealloc for psu_cortexr5_1 */
+	PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	3,
+	NODE_TCM_1_A,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_TCM_1_B,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_IPI_RPU_1,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+
+	
+	/**********************************************************************/
+	/* POWER SECTION */
+
+	PM_CONFIG_POWER_SECTION_ID, /* Power Section ID */
+	4U, /* Number of power nodes */
+
+	NODE_APU, /* Power node ID */
+	PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */
+
+	NODE_RPU, /* Power node ID */
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */
+
+	NODE_FPD, /* Power node ID */
+	PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */
+
+	NODE_PLD, /* Power node ID */
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */
+
+
+	/**********************************************************************/
+	/* RESET SECTION */
+
+	PM_CONFIG_RESET_SECTION_ID, /* Reset Section ID */
+	120U, /* Number of resets */
+
+	XILPM_RESET_PCIE_CFG, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_PCIE_BRIDGE, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_PCIE_CTRL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_DP, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_SWDT_CRF, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_AFI_FM5, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_AFI_FM4, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_AFI_FM3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_AFI_FM2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_AFI_FM1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_AFI_FM0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GDMA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPU_PP1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPU_PP0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPU, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GT, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_SATA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_ACPU3_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_ACPU2_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_ACPU1_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_ACPU0_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_APU_L2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_ACPU3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_ACPU2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_ACPU1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_ACPU0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_DDR, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_APM_FPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_SOFT, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GEM0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GEM1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GEM2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GEM3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_QSPI, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_UART0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_UART1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_SPI0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_SPI1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_SDIO0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_SDIO1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_CAN0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_CAN1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_I2C0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_I2C1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_TTC0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_TTC1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_TTC2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_TTC3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_SWDT_CRL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_NAND, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_ADMA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPIO, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_IOU_CC, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_TIMESTAMP, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_RPU_R50, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_RPU_R51, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_RPU_AMBA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_OCM, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_RPU_PGE, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_USB0_CORERESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_USB1_CORERESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_USB0_HIBERRESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_USB1_HIBERRESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_USB0_APB, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_USB1_APB, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_IPI, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_APM_LPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_RTC, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_SYSMON, 0,
+	XILPM_RESET_AFI_FM6, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_LPD_SWDT, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_FPD, PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK,
+	XILPM_RESET_RPU_DBG1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_RPU_DBG0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_DBG_LPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_DBG_FPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_APLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_DPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_VPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_IOPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_RPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_4, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_5, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_6, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_7, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_8, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_9, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_10, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_11, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_12, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_13, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_14, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_15, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_16, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_17, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_18, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_19, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_20, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_21, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_22, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_23, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_24, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_25, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_26, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_27, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_28, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_29, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_30, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_31, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_RPU_LS, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_PS_ONLY, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_PL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPIO5_EMIO_92, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPIO5_EMIO_93, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPIO5_EMIO_94, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPIO5_EMIO_95, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+
+	/**********************************************************************/
+	/* SET CONFIG SECTION */
+	PM_CONFIG_SET_CONFIG_SECTION_ID,		/* Set Config Section ID */
+	0U, /* Permissions to load base config object */
+	0U, /* Permissions to load overlay config object */
+
+	/**********************************************************************/
+	/* SHUTDOWN SECTION */
+
+	PM_CONFIG_SHUTDOWN_SECTION_ID, /* Shutdown Section ID */
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* System Shutdown/Restart Permission */
+
+	/**********************************************************************/
+	/* GPO SECTION */
+	PM_CONFIG_GPO_SECTION_ID,		/* GPO Section ID */
+	PM_CONFIG_GPO1_BIT_2_MASK |
+	PM_CONFIG_GPO1_MIO_PIN_34_MAP |
+	PM_CONFIG_GPO1_MIO_PIN_35_MAP |
+	0,					/* State of GPO pins */
+};
+#if defined (__ICCARM__)
+#pragma language=restore
+#endif
+
diff --git a/board/zynqmp/kria/kv260/uboot.fragment b/board/zynqmp/kria/kv260/uboot.fragment
new file mode 100644
index 0000000000..e1aca68692
--- /dev/null
+++ b/board/zynqmp/kria/kv260/uboot.fragment
@@ -0,0 +1 @@
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-smk-k26-revA"
diff --git a/board/zynqmp/kria/post-build.sh b/board/zynqmp/kria/post-build.sh
new file mode 100755
index 0000000000..9fd8bbf2c8
--- /dev/null
+++ b/board/zynqmp/kria/post-build.sh
@@ -0,0 +1,8 @@
+#!/bin/sh
+
+# genimage will need to find the extlinux.conf
+# in the binaries directory
+
+BOARD_DIR="$(dirname $0)"
+
+install -m 0644 -D $BOARD_DIR/extlinux.conf $BINARIES_DIR/extlinux.conf
diff --git a/board/zynqmp/kria/readme.txt b/board/zynqmp/kria/readme.txt
new file mode 100644
index 0000000000..a3a4b5e65a
--- /dev/null
+++ b/board/zynqmp/kria/readme.txt
@@ -0,0 +1,78 @@
+**************************************************
+Xilinx Kria SOM Starter Kits - ZynqMP SoC
+**************************************************
+
+This document describes the Buildroot support for the Kria 
+KV260 starter kit by Xilinx, based on Kria SOM including the 
+Zynq UltraScale+ MPSoC (aka ZynqMP).  It has been tested with 
+the KV260 production board.
+
+Evaluation board features can be found here with the link below.
+
+KV260:
+https://www.xilinx.com/products/boards-and-kits/kv260.html
+
+How to build it
+===============
+
+Configure Buildroot:
+
+    $ make zynqmp_kria_kv260_defconfig
+
+Compile everything and build the rootfs image:
+
+    $ make
+
+Result of the build
+-------------------
+
+After building, you should get a tree like this:
+
+    output/images/
+    +-- atf-uboot.ub
+    +-- bl31.bin
+    +-- boot.bin
+    +-- boot.vfat
+    +-- Image
+    +-- rootfs.ext2
+    +-- rootfs.ext4 -> rootfs.ext2
+    +-- sdcard.img
+    +-- system.dtb -> smk-k26-revA-sck-kv-g-revB.dtb
+    +-- u-boot.itb
+    `-- smk-k26-revA-sck-kv-g-revB.dtb
+
+How to write the SD card
+========================
+
+WARNING! This will destroy all the card content. Use with care!
+
+The sdcard.img file is a complete bootable image ready to be written
+on the boot medium. To install it, simply copy the image to an SD
+card:
+
+    # dd if=output/images/sdcard.img of=/dev/sdX
+
+Where 'sdX' is the device node of the SD.
+
+Eject the SD card, insert it in the board, and power it up.
+
+How to write the boot.bn to QSPI boot flash
+===========================================
+
+The Kria SOMs are preconfigured to boot initially from QSPI.
+This makes these boards different from other ZynqMP boards
+in that the boot.bin needs to be flashed into the QSPI boot
+flash such that the U-Boot SPL can then load all of the
+remaining images from the SD card.
+
+In addition, the KV260 Starter Kit QSPI comes pre-flashed with
+a utility designed to make updating the QSPI flash memory
+easier.
+
+Instructions for using these utilities to update the boot.bin
+in QSPI flash can be found on the wiki link below.
+
+https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM#Boot-Firmware-Updates
+
+It is possible to boot the Buildroot generated SD card image without
+updating the QSPI boot.bin image, so this is an optional step.
diff --git a/configs/zynqmp_kria_kv260_defconfig b/configs/zynqmp_kria_kv260_defconfig
new file mode 100644
index 0000000000..d4a72a0d19
--- /dev/null
+++ b/configs/zynqmp_kria_kv260_defconfig
@@ -0,0 +1,37 @@
+BR2_aarch64=y
+BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_15=y
+BR2_ROOTFS_POST_BUILD_SCRIPT="board/zynqmp/kria/post-build.sh"
+BR2_ROOTFS_POST_IMAGE_SCRIPT="board/zynqmp/post-image.sh"
+BR2_LINUX_KERNEL=y
+BR2_LINUX_KERNEL_CUSTOM_TARBALL=y
+BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,linux-xlnx,xlnx_rebase_v5.15_LTS_2022.1)/xlnx_rebase_v5.15_LTS_2022.1.tar.gz"
+BR2_LINUX_KERNEL_DEFCONFIG="xilinx_zynqmp"
+BR2_LINUX_KERNEL_DTS_SUPPORT=y
+BR2_LINUX_KERNEL_INTREE_DTS_NAME="xilinx/smk-k26-revA-sck-kv-g-revB"
+BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y
+BR2_TARGET_ROOTFS_EXT2=y
+BR2_TARGET_ROOTFS_EXT2_4=y
+# BR2_TARGET_ROOTFS_TAR is not set
+BR2_TARGET_ARM_TRUSTED_FIRMWARE=y
+BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL=y
+BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,arm-trusted-firmware,xlnx_rebase_v2.6_2022.1)/xlnx_rebase_v2.6_2022.1.tar.gz"
+BR2_TARGET_ARM_TRUSTED_FIRMWARE_PLATFORM="zynqmp"
+BR2_TARGET_ARM_TRUSTED_FIRMWARE_BL31_UBOOT=y
+BR2_TARGET_UBOOT=y
+BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y
+BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
+BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,u-boot-xlnx,xlnx_rebase_v2022.01_2022.1)/xlnx_rebase_v2022.01_2022.1.tar.gz"
+BR2_TARGET_UBOOT_BOARD_DEFCONFIG="xilinx_zynqmp_virt"
+BR2_TARGET_UBOOT_CONFIG_FRAGMENT_FILES="board/zynqmp/kria/kv260/uboot.fragment"
+BR2_TARGET_UBOOT_NEEDS_DTC=y
+BR2_TARGET_UBOOT_NEEDS_OPENSSL=y
+BR2_TARGET_UBOOT_SPL=y
+BR2_TARGET_UBOOT_SPL_NAME="spl/boot.bin"
+BR2_TARGET_UBOOT_ZYNQMP=y
+BR2_TARGET_UBOOT_ZYNQMP_PMUFW="https://github.com/lucaceresoli/zynqmp-pmufw-binaries/raw/v2022.1/bin/pmufw-v2022.1.bin"
+BR2_TARGET_UBOOT_ZYNQMP_PM_CFG="board/zynqmp/kria/kv260/pm_cfg_obj.c"
+BR2_TARGET_UBOOT_FORMAT_ITB=y
+BR2_TARGET_UBOOT_NEEDS_ATF_BL31=y
+BR2_PACKAGE_HOST_DOSFSTOOLS=y
+BR2_PACKAGE_HOST_GENIMAGE=y
+BR2_PACKAGE_HOST_MTOOLS=y
-- 
2.17.1

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[Buildroot] [PATCH v1 2/2] DEVELOPERS update

[Neal Frager via buildroot]

Updating Neal Frager in the DEVELOPERS file.

Signed-off-by: Neal Frager <neal.frager@amd.com>
---
 DEVELOPERS | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/DEVELOPERS b/DEVELOPERS
index 292b919137..861496fb9d 100644
--- a/DEVELOPERS
+++ b/DEVELOPERS
@@ -2100,8 +2100,13 @@ F:	package/pkg-qmake.mk
 F:	package/qt5/qt5opcua/
 
 N:	Neal Frager <neal.frager@amd.com>
+F:	board/zynq/
 F:	board/zynqmp/
+F:	board/zynqmp/kria/
+F:	configs/zynq_zc706_defconfig
 F:	configs/zynqmp_zcu102_defconfig
+F:	configs/zynqmp_zcu106_defconfig
+F:	configs/zynqmp_kria_kv260_defconfig
 
 N:	Nicola Di Lieto <nicola.dilieto@gmail.com>
 F:	package/uacme/
-- 
2.17.1

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Re: [Buildroot] [PATCH v1 2/2] DEVELOPERS update

[Arnout Vandecappelle]

On 05/05/2022 17:54, Neal Frager via buildroot wrote:
> Updating Neal Frager in the DEVELOPERS file.
> 
> Signed-off-by: Neal Frager <neal.frager@amd.com>
> ---
>   DEVELOPERS | 5 +++++
>   1 file changed, 5 insertions(+)
> 
> diff --git a/DEVELOPERS b/DEVELOPERS
> index 292b919137..861496fb9d 100644
> --- a/DEVELOPERS
> +++ b/DEVELOPERS
> @@ -2100,8 +2100,13 @@ F:	package/pkg-qmake.mk
>   F:	package/qt5/qt5opcua/
>   
>   N:	Neal Frager <neal.frager@amd.com>
> +F:	board/zynq/
>   F:	board/zynqmp/
> +F:	board/zynqmp/kria/

  This is already comprised in board/zynqmp/ above, so no need.

  Regards,
  Arnout

> +F:	configs/zynq_zc706_defconfig
>   F:	configs/zynqmp_zcu102_defconfig
> +F:	configs/zynqmp_zcu106_defconfig
> +F:	configs/zynqmp_kria_kv260_defconfig
>   
>   N:	Nicola Di Lieto <nicola.dilieto@gmail.com>
>   F:	package/uacme/
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Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Wesley Revens]

Hi Neal,

I have been working on a Buildroot image for the Kria recently so my 
company can evaluate the K26 SOM.
I reached a similar position to what has been included in your patch 
however I have not been able to
get the Kria to boot using the U-Boot SPL.

I have tried out your patch and found that the Linux kernel is booting 
fine from the SD card using
the pre-programmed boot.bin that is already present on the Kria. 
However, after building using your patch,
I tried uploading the boot.bin that appears in buildroot/output/images 
to my Kria using the
"Boot Image Recovery Tool" web UI that runs on the Kria if you hold down 
the FWUEN button
during reset of the board. On boot, I then get the following output from 
U-Boot SPL:

U-Boot SPL 2022.01 (May 06 2022 - 11:21:55 +0100)
PMUFW:  v1.1
Loading new PMUFW cfg obj (2016 bytes)
Silicon version:        3
EL Level:       EL3
Chip ID:        xck26
Multiboot:      64
Trying to boot from SPI

Then nothing else happens.

There is a big difference in the file sizes for the boot.bin from 
buildroot/output/images and the BOOT.BIN
I downloaded from 
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM#Boot-Firmware-Updates
so I am obviously missing something somewhere. I think all the 
components are being built but I'm not sure
they are being packaged in a similar way to how the pre-loaded boot.bin 
is laid out (or I am using the wrong output file!)

In my own testing I was able to test the u-boot.img produced by my 
Buildroot build but I had to use the
Xilinx bootgen tools and use the Xilinx fsbl rather than the U-Boot SPL.

In future, we would like to be able to bypass this step and just use 
whatever Buildroot produces.
I was wondering if you could point me in the right direction.

Regards,

Wesley


On 05/05/2022 16:54, Neal Frager via buildroot wrote:
> This patch adds support for Xilinx Kria KV260 starter kit.
>
> KV260 features can be found here:
> https://www.xilinx.com/products/boards-and-kits/kv260.html
>
> While the Kria SOM is based on a ZynqMP SoC, there are some key
> boot config differences from the other ZynqMP evaluation boards.
>
> 1. There are no boot switches on Kria SOMs. The boot mode is thus
> hard configured for QSPI flash. A pre-programmed boot.bin comes
> with every Starter Kit. U-Boot can then find the Linux kernel and
> file system on the SD card.
>
> Optional instructions for updating the boot.bin in the QSPI flash
> can be found in the readme.txt file and the link below.
>
> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM
>
> 2. Kria SOMs use UART1 for the console instead of UART0. For this
> reason, Kria Starter Kits will use a separate extlinux.conf file
> from other ZynqMP evaluation boards.
<snip>
To unsubscribe click: http://link.sonifex.co.uk/us/?e=1nXvxxPuEp2Zja.ddedfjkAKO6ol
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Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Neal Frager]

Hi Wesley,


> Le 6 mai 2022 à 13:18, Wesley Revens <wesley@sonifex.co.uk> a écrit :
> 
> CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or responding to this email.
> 
> 
> [CAUTION: External Email]
> 
> Hi Neal,
> 
> I have been working on a Buildroot image for the Kria recently so my
> company can evaluate the K26 SOM.
> I reached a similar position to what has been included in your patch
> however I have not been able to
> get the Kria to boot using the U-Boot SPL.
> 
> I have tried out your patch and found that the Linux kernel is booting
> fine from the SD card using
> the pre-programmed boot.bin that is already present on the Kria.
> However, after building using your patch,
> I tried uploading the boot.bin that appears in buildroot/output/images
> to my Kria using the
> "Boot Image Recovery Tool" web UI that runs on the Kria if you hold down
> the FWUEN button
> during reset of the board. On boot, I then get the following output from
> U-Boot SPL:
> 
> U-Boot SPL 2022.01 (May 06 2022 - 11:21:55 +0100)
> PMUFW:  v1.1
> Loading new PMUFW cfg obj (2016 bytes)
> Silicon version:        3
> EL Level:       EL3
> Chip ID:        xck26
> Multiboot:      64
> Trying to boot from SPI
> 
> Then nothing else happens.
> 
> There is a big difference in the file sizes for the boot.bin from
> buildroot/output/images and the BOOT.BIN
> I downloaded from
> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM#Boot-Firmware-Updates
> so I am obviously missing something somewhere. I think all the
> components are being built but I'm not sure
> they are being packaged in a similar way to how the pre-loaded boot.bin
> is laid out (or I am using the wrong output file!)
> 
> In my own testing I was able to test the u-boot.img produced by my
> Buildroot build but I had to use the
> Xilinx bootgen tools and use the Xilinx fsbl rather than the U-Boot SPL.
> 
> In future, we would like to be able to bypass this step and just use
> whatever Buildroot produces.
> I was wondering if you could point me in the right direction.
> 
> Regards,
> 
> Wesley

I would be happy to help you here.  One of the big differences between the preprogrammed boot.bin and the one built by buildroot is that it uses the FSBL instead of the SPL.

This means that u-boot itself gets packaged inside the boot.bin in the prepackaged version based on the FSBL.

In the SPL case, you need to write both the boot.bin and the u-boot.itb to the QSPI flash because u-boot is not included in the boot.bin, in this case.

To fix this better though, I may implement a patch for the SPL so that it looks for the u-boot.itb in the SD card instead of the QSPI flash.  This would probably be a better solution.

> 
> 
>> On 05/05/2022 16:54, Neal Frager via buildroot wrote:
>> This patch adds support for Xilinx Kria KV260 starter kit.
>> 
>> KV260 features can be found here:
>> https://www.xilinx.com/products/boards-and-kits/kv260.html
>> 
>> While the Kria SOM is based on a ZynqMP SoC, there are some key
>> boot config differences from the other ZynqMP evaluation boards.
>> 
>> 1. There are no boot switches on Kria SOMs. The boot mode is thus
>> hard configured for QSPI flash. A pre-programmed boot.bin comes
>> with every Starter Kit. U-Boot can then find the Linux kernel and
>> file system on the SD card.
>> 
>> Optional instructions for updating the boot.bin in the QSPI flash
>> can be found in the readme.txt file and the link below.
>> 
>> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM
>> 
>> 2. Kria SOMs use UART1 for the console instead of UART0. For this
>> reason, Kria Starter Kits will use a separate extlinux.conf file
>> from other ZynqMP evaluation boards.
> <snip>
> To unsubscribe click: http://link.sonifex.co.uk/us/?e=1nXvxxPuEp2Zja.ddePfjkAnBV-Z
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Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Peter Korsgaard]

>>>>> "Neal" == Neal Frager <neal.frager@amd.com> writes:

 > This patch adds support for Xilinx Kria KV260 starter kit.
 > KV260 features can be found here:
 > https://www.xilinx.com/products/boards-and-kits/kv260.html

 > While the Kria SOM is based on a ZynqMP SoC, there are some key
 > boot config differences from the other ZynqMP evaluation boards.

 > 1. There are no boot switches on Kria SOMs. The boot mode is thus
 > hard configured for QSPI flash. A pre-programmed boot.bin comes
 > with every Starter Kit. U-Boot can then find the Linux kernel and
 > file system on the SD card.

 > Optional instructions for updating the boot.bin in the QSPI flash
 > can be found in the readme.txt file and the link below.

 > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM

 > 2. Kria SOMs use UART1 for the console instead of UART0. For this
 > reason, Kria Starter Kits will use a separate extlinux.conf file
 > from other ZynqMP evaluation boards.

 > Signed-off-by: Neal Frager <neal.frager@amd.com>
 > ---
 >  board/zynqmp/kria/extlinux.conf        |   4 +
 >  board/zynqmp/kria/kv260/pm_cfg_obj.c   | 556 +++++++++++++++++++++++++
 >  board/zynqmp/kria/kv260/uboot.fragment |   1 +

Are you planning to also support other kria boards given the kria/
subdir?

>  board/zynqmp/kria/post-build.sh        |   8 +

The post-build.sh copy is not so nice, but ok.

Committed, thanks.

-- 
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Re: [Buildroot] [PATCH v1 2/2] DEVELOPERS update

[Peter Korsgaard]

>>>>> "Neal" == Neal Frager <neal.frager@amd.com> writes:

 > Updating Neal Frager in the DEVELOPERS file.
 > Signed-off-by: Neal Frager <neal.frager@amd.com>

Committed, thanks.

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Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Neal Frager]

Hi Peter,


> Le 6 mai 2022 à 21:22, Peter Korsgaard <peter@korsgaard.com> a écrit :
> 
> CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or responding to this email.
> 
> 
> [CAUTION: External Email]
> 
>>>>>> "Neal" == Neal Frager <neal.frager@amd.com> writes:
> 
>> This patch adds support for Xilinx Kria KV260 starter kit.
>> KV260 features can be found here:
>> https://www.xilinx.com/products/boards-and-kits/kv260.html
> 
>> While the Kria SOM is based on a ZynqMP SoC, there are some key
>> boot config differences from the other ZynqMP evaluation boards.
> 
>> 1. There are no boot switches on Kria SOMs. The boot mode is thus
>> hard configured for QSPI flash. A pre-programmed boot.bin comes
>> with every Starter Kit. U-Boot can then find the Linux kernel and
>> file system on the SD card.
> 
>> Optional instructions for updating the boot.bin in the QSPI flash
>> can be found in the readme.txt file and the link below.
> 
>> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM
> 
>> 2. Kria SOMs use UART1 for the console instead of UART0. For this
>> reason, Kria Starter Kits will use a separate extlinux.conf file
>> from other ZynqMP evaluation boards.
> 
>> Signed-off-by: Neal Frager <neal.frager@amd.com>
>> ---
>> board/zynqmp/kria/extlinux.conf        |   4 +
>> board/zynqmp/kria/kv260/pm_cfg_obj.c   | 556 +++++++++++++++++++++++++
>> board/zynqmp/kria/kv260/uboot.fragment |   1 +
> 
> Are you planning to also support other kria boards given the kria/
> subdir?

Yes, there is another Kria carrier board we are about to announce.  It is not public yet, but I setup the directories in planning for this.

> 
>> board/zynqmp/kria/post-build.sh        |   8 +
> 
> The post-build.sh copy is not so nice, but ok.

I agree.  If you have a better solution, I would be happy to have any suggestions.

> 
> Committed, thanks.
> 
> --
> Bye, Peter Korsgaard

Best regards,
Neal Frager
AMD
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Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Peter Korsgaard]

>>>>> "Neal" == Neal Frager <nealf@xilinx.com> writes:

Hi,

 >> Are you planning to also support other kria boards given the kria/
 >> subdir?

 > Yes, there is another Kria carrier board we are about to announce.  It
 > is not public yet, but I setup the directories in planning for this.

Ahh, sounds interesting ;)

 >> 
 >>> board/zynqmp/kria/post-build.sh        |   8 +
 >> 
 >> The post-build.sh copy is not so nice, but ok.

 > I agree.  If you have a better solution, I would be happy to have any suggestions.

There's a number of options, E.G. we could use a symlink to the existing
script or pass the file to copy as an argument in
BR2_ROOTFS_POST_SCRIPT_ARGS. U-Boot afaik also expands variable
references in the extlinux files, so if there is already a U-Boot
variable with the serial port name then that could be used.

-- 
Bye, Peter Korsgaard
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Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Neal Frager]

Hi Peter,


> Le 7 mai 2022 à 23:01, Peter Korsgaard <peter@korsgaard.com> a écrit :
> 
> CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or responding to this email.
> 
> 
>>>>>> "Neal" == Neal Frager <nealf@xilinx.com> writes:
> 
> Hi,
> 
>>> Are you planning to also support other kria boards given the kria/
>>> subdir?
> 
>> Yes, there is another Kria carrier board we are about to announce.  It
>> is not public yet, but I setup the directories in planning for this.
> 
> Ahh, sounds interesting ;)
> 
>>> 
>>>> board/zynqmp/kria/post-build.sh        |   8 +
>>> 
>>> The post-build.sh copy is not so nice, but ok.
> 
>> I agree.  If you have a better solution, I would be happy to have any suggestions.
> 
> There's a number of options, E.G. we could use a symlink to the existing
> script or pass the file to copy as an argument in
> BR2_ROOTFS_POST_SCRIPT_ARGS. U-Boot afaik also expands variable
> references in the extlinux files, so if there is already a U-Boot
> variable with the serial port name then that could be used.

Thank you for this idea.  Do you have a solution for the SD card file system as well?

The Kria Starter kits use mmc1 instead of mmc0 for the SD card, so this is also different in the extllinux.conf files.

> 
> --
> Bye, Peter Korsgaard

Thanks for your help!

Best regards,
Neal Frager
AMD
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Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Peter Korsgaard]

>>>>> "Neal" == Neal Frager <nealf@xilinx.com> writes:

Hi,

 > Thank you for this idea.  Do you have a solution for the SD card file system as well?

 > The Kria Starter kits use mmc1 instead of mmc0 for the SD card, so
 > this is also different in the extllinux.conf files.

I believe you can use $devnum for that. Have a look at distro_bootcmd.

-- 
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Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Neal Frager]

Hi Michal,

> 
> Hi Neal,
> 
> I have been working on a Buildroot image for the Kria recently so my 
> company can evaluate the K26 SOM.
> I reached a similar position to what has been included in your patch 
> however I have not been able to get the Kria to boot using the U-Boot 
> SPL.
> 
> I have tried out your patch and found that the Linux kernel is booting 
> fine from the SD card using the pre-programmed boot.bin that is 
> already present on the Kria.
> However, after building using your patch, I tried uploading the 
> boot.bin that appears in buildroot/output/images to my Kria using the 
> "Boot Image Recovery Tool" web UI that runs on the Kria if you hold 
> down the FWUEN button during reset of the board. On boot, I then get 
> the following output from U-Boot SPL:
> 
> U-Boot SPL 2022.01 (May 06 2022 - 11:21:55 +0100)
> PMUFW:  v1.1
> Loading new PMUFW cfg obj (2016 bytes) Silicon version:        3 EL 
> Level:       EL3 Chip ID:        xck26
> Multiboot:      64
> Trying to boot from SPI
> 
> Then nothing else happens.
> 
> There is a big difference in the file sizes for the boot.bin from 
> buildroot/output/images and the BOOT.BIN I downloaded from 
> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+
> K26+SOM#Boot-Firmware-Updates
> 
> so I am obviously missing something somewhere. I think all the 
> components are being built but I'm not sure they are being packaged in 
> a similar way to how the pre-loaded boot.bin is laid out (or I am 
> using the wrong output file!)
> 
> In my own testing I was able to test the u-boot.img produced by my 
> Buildroot build but I had to use the Xilinx bootgen tools and use the 
> Xilinx fsbl rather than the U-Boot SPL.
> 
> In future, we would like to be able to bypass this step and just use 
> whatever Buildroot produces.
> I was wondering if you could point me in the right direction.

> Not quite sure what Neil is using but of course you can use SPL with Kria SOM and I am using it on daily basis.
> It really depends what exactly you want do and do some alignments to u-boot config.
> Let's assume you have starter kit with preinstalled A/B updates you need to say if you want to have this functionality or not.
> I personally didn't try to use A/B with SPL and using partition for image A for boot.bin (SPL only) and partition B for image.itb.
> That being said you need to tell SPL where u-boot.itb is placed in QSPI.

> It means you need to setup CONFIG_SYS_SPI_U_BOOT_OFFS=0xF80000 as offset to place image to this location.

> If you use update utility then write u-boot.itb (you need to rename it because gui expects *.bin filename) first to imageB and then boot.bin to Image A.

> Compare to the latest upstream version you need enable some configs.
> CONFIG_DEFAULT_DEVICE_TREE="zynqmp-smk-k26-revA"
> CONFIG_ENV_SIZE=0x40000
> CONFIG_SYS_SPI_U_BOOT_OFFS=0xF80000

These configs are clear and specific to the Kria SOM.

> CONFIG_DTB_RESELECT=y
> CONFIG_MULTI_DTB_FIT=y
> CONFIG_ENV_IS_NOWHERE=y (only)
> CONFIG_USE_DEFAULT_ENV_FILE=y
> CONFIG_DEFAULT_ENV_FILE="vars"
> CONFIG_DMA=y
> CONFIG_XILINX_DPDMA=y
> CONFIG_PHY=y
> CONFIG_PHY_XILINX_ZYNQMP=y
> CONFIG_PINCTRL=y
> CONFIG_PINCONF=y
> CONFIG_POWER_DOMAIN=y
> CONFIG_ZYNQMP_POWER_DOMAIN=y
> CONFIG_DM_RESET=y
> CONFIG_RESET_ZYNQMP=y
> CONFIG_VIDEO_ZYNQMP_DPSUB=y

These configs do not appear specific to Kria.  Should we be using them for other zynqmp boards as well?
Such as the zcu102 and zcu106?

We are currently just using the xilinx_zynqmp_virt_defconfig with the CONFIG_DEFAULT_DEVICE_TREE
for each individual board.  Is this sufficient for the zcu102 and zcu106 boards?

Best regards,
Neal Frager
AMD
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Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Neal Frager]

Hi Michal,

> 
>>>>>> "Neal" == Neal Frager <neal.frager@amd.com> writes:
> 
>   > This patch adds support for Xilinx Kria KV260 starter kit.
>   > KV260 features can be found here:
>   > https://www.xilinx.com/products/boards-and-kits/kv260.html
> 
>   > While the Kria SOM is based on a ZynqMP SoC, there are some key
>   > boot config differences from the other ZynqMP evaluation boards.
> 
>   > 1. There are no boot switches on Kria SOMs. The boot mode is thus
>   > hard configured for QSPI flash. A pre-programmed boot.bin comes
>   > with every Starter Kit. U-Boot can then find the Linux kernel and
>   > file system on the SD card.
> 
>   > Optional instructions for updating the boot.bin in the QSPI flash
>   > can be found in the readme.txt file and the link below.
> 
>   > 
> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+
> K26+SOM
> 
>   > 2. Kria SOMs use UART1 for the console instead of UART0. For this
>   > reason, Kria Starter Kits will use a separate extlinux.conf file
>   > from other ZynqMP evaluation boards.
> 
>   > Signed-off-by: Neal Frager <neal.frager@amd.com>
>   > ---
>   >  board/zynqmp/kria/extlinux.conf        |   4 +
>   >  board/zynqmp/kria/kv260/pm_cfg_obj.c   | 556 +++++++++++++++++++++++++
>   >  board/zynqmp/kria/kv260/uboot.fragment |   1 +
> 
> Are you planning to also support other kria boards given the kria/ 
> subdir?

> you should think about structure in a way that it is kria SOM program. kv260 is xilinx designed carrier card for k26 som. It means any user can take k26 som and create own carrier card and maybe push this to buildroot to support this product.
> And also k26 itself has multiple variants. K26 on starter kit doesn't have EMMC on it. k26 production has emmc on it. There are also C and I variants also with encryption enabled/disabled.
> I don't think you should cover C/I or ED variants but definitely you should think how to handle different SOM types especially in connection to populated EMMC.

> It means
> board/zynqmp/kria/k26/...
> board/zynqmp/kria/k26/kv260/..
> board/zynqmp/kria/k26/custom/..

> and
> board/zynqmp/kria/k26-prod/...
> board/zynqmp/kria/k26-prod/...
> board/zynqmp/kria/k26-prod/kv260/..
> board/zynqmp/kria/k26-prod/custom/..

My objective with the buildroot defconfigs is just to give the community examples for how to build and run buildroot on our evaluation boards.
Developers will then need to modify these configurations when developing for their own hardware.

So looking at your proposed directory structure, I was not planning to cover the production SOMs.
My focus is thus only on supporting the starter kit configurations to give the community working examples.

However, you do raise a good point about the possibility of new Kria SOMs in the future.
Not all starter kits will necessarily be based on a K26 SOM.

With this feedback in mind, I am thinking of the following example structure:
board/zynqmp/k26/kv260
board/zynqmp/k26/<future starter kit based on k26 som>
board/zynqmp/<future som>/<future starter kit based on future som>

In other words, I am going to replace the kria directory with k26 including files for the k26 som that work for the various k26 som based starter kits.

What does everyone think of this proposal?

Best regards,
Neal Frager
AMD

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Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Wesley Revens]

Hi,

On 09/05/2022 08:27, Michal Simek wrote:
> Hi,
>
> On 5/9/22 08:23, Neal Frager wrote:
>> Hi Michal,
>>
>>>
>>> Hi Neal,
>>>
>>> I have been working on a Buildroot image for the Kria recently so my
>>> company can evaluate the K26 SOM.
>>> I reached a similar position to what has been included in your patch
>>> however I have not been able to get the Kria to boot using the U-Boot
>>> SPL.
>>>
>>> I have tried out your patch and found that the Linux kernel is booting
>>> fine from the SD card using the pre-programmed boot.bin that is
>>> already present on the Kria.
>>> However, after building using your patch, I tried uploading the
>>> boot.bin that appears in buildroot/output/images to my Kria using the
>>> "Boot Image Recovery Tool" web UI that runs on the Kria if you hold
>>> down the FWUEN button during reset of the board. On boot, I then get
>>> the following output from U-Boot SPL:
>>>
>>> U-Boot SPL 2022.01 (May 06 2022 - 11:21:55 +0100)
>>> PMUFW:  v1.1
>>> Loading new PMUFW cfg obj (2016 bytes) Silicon version: 3 EL
>>> Level:       EL3 Chip ID:        xck26
>>> Multiboot:      64
>>> Trying to boot from SPI
>>>
>>> Then nothing else happens.
>>>
>>> There is a big difference in the file sizes for the boot.bin from
>>> buildroot/output/images and the BOOT.BIN I downloaded from
>>> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+
>>> K26+SOM#Boot-Firmware-Updates
>>>
>>> so I am obviously missing something somewhere. I think all the
>>> components are being built but I'm not sure they are being packaged in
>>> a similar way to how the pre-loaded boot.bin is laid out (or I am
>>> using the wrong output file!)
>>>
>>> In my own testing I was able to test the u-boot.img produced by my
>>> Buildroot build but I had to use the Xilinx bootgen tools and use the
>>> Xilinx fsbl rather than the U-Boot SPL.
>>>
>>> In future, we would like to be able to bypass this step and just use
>>> whatever Buildroot produces.
>>> I was wondering if you could point me in the right direction.
>>
>>> Not quite sure what Neil is using but of course you can use SPL with 
>>> Kria SOM and I am using it on daily basis.
>>> It really depends what exactly you want do and do some alignments to 
>>> u-boot config.
>>> Let's assume you have starter kit with preinstalled A/B updates you 
>>> need to say if you want to have this functionality or not.
>>> I personally didn't try to use A/B with SPL and using partition for 
>>> image A for boot.bin (SPL only) and partition B for image.itb.
>>> That being said you need to tell SPL where u-boot.itb is placed in 
>>> QSPI.
>>
>>> It means you need to setup CONFIG_SYS_SPI_U_BOOT_OFFS=0xF80000 as 
>>> offset to place image to this location.
>>
>>> If you use update utility then write u-boot.itb (you need to rename 
>>> it because gui expects *.bin filename) first to imageB and then 
>>> boot.bin to Image A.
>>
>>> Compare to the latest upstream version you need enable some configs.
>>> CONFIG_DEFAULT_DEVICE_TREE="zynqmp-smk-k26-revA"
>>> CONFIG_ENV_SIZE=0x40000
>>> CONFIG_SYS_SPI_U_BOOT_OFFS=0xF80000
>>
>> These configs are clear and specific to the Kria SOM.
>>
>>> CONFIG_DTB_RESELECT=y
>>> CONFIG_MULTI_DTB_FIT=y
>>> CONFIG_ENV_IS_NOWHERE=y (only)
>>> CONFIG_USE_DEFAULT_ENV_FILE=y
>>> CONFIG_DEFAULT_ENV_FILE="vars"
>>> CONFIG_DMA=y
>>> CONFIG_XILINX_DPDMA=y
>>> CONFIG_PHY=y
>>> CONFIG_PHY_XILINX_ZYNQMP=y
>>> CONFIG_PINCTRL=y
>>> CONFIG_PINCONF=y
>>> CONFIG_POWER_DOMAIN=y
>>> CONFIG_ZYNQMP_POWER_DOMAIN=y
>>> CONFIG_DM_RESET=y
>>> CONFIG_RESET_ZYNQMP=y
>>> CONFIG_VIDEO_ZYNQMP_DPSUB=y
>>
>> These configs do not appear specific to Kria.  Should we be using 
>> them for other zynqmp boards as well?
>> Such as the zcu102 and zcu106?
>
> These features were developed for Kria and as we always do we will try 
> to enable it for all zynqmp boards but we need to make sure that it 
> will work with other configurations. It means we are planning to 
> enable the most of options by default for all platforms after checking.
>
> Thanks,
> Michal
>
>
Thanks for the help. I have been able to make some progress by putting 
boot.bin
in QSPI partition A and u-boot.itb in partition B using the boot image 
recovery tool.

I tried using the boot.bin and u-boot.itb from a tree using the official 
patch with CONFIG_SYS_SPI_U_BOOT_OFFS=0xF80000
and I got the same result with the console being stuck at "Trying to 
boot from SPI"

Using a different tree with my own attempt that I was working on to get 
a buildroot
kria build working I got a little further - ATF was not running in the 
version built
from Neal's patch. Comparing the configs I think the following line in 
missing Neal's patch:

BR2_TARGET_ARM_TRUSTED_FIRMWARE_ADDITIONAL_VARIABLES="ZYNQMP_CONSOLE=cadence1 
PRELOADED_BL33_BASE=0x800000"

Adding this config allowed me to progress further now I get the 
following but it is still not
booting into Linux after this and I can't get a uboot command prompt 
here either.

U-Boot SPL 2022.01 (May 09 2022 - 09:51:43 +0100)
PMUFW:  v1.1
Loading new PMUFW cfg obj (2016 bytes)
Silicon version:        3
EL Level:       EL3
Chip ID:        xck26
Multiboot:      64
Trying to boot from SPI
NOTICE:  BL31: v2.6(release):
NOTICE:  BL31: Built : 09:51:09, May  9 2022


U-Boot 2022.01 (May 09 2022 - 09:51:43 +0100)

CPU:   ZynqMP
Silicon: v3
PMUFW no permission to change config object
Detected name: zynqmp-smk-k26-xcl2g-rev1-sck-kv-g-rev1
Model: Avnet Ultra96 Rev1
Board: Xilinx ZynqMP
DRAM:  2 GiB
PMUFW:  v1.1
EL Level:       EL2
Chip ID:        xck26
PMUFW no permission to change config object
NAND:  0 MiB
MMC:   PMUFW no permission to change config object

Is there some device tree setting that needs tweaking in uboot to get it 
to continue booting from the MMC?

Regards,

Wesley

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Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Neal Frager]

Hi Wesley,

> U-Boot 2022.01 (May 09 2022 - 09:51:43 +0100)

> CPU:   ZynqMP
>Silicon: v3
> PMUFW no permission to change config object Detected name: zynqmp-smk-k26-xcl2g-rev1-sck-kv-g-rev1

I am working on this in parallel with you.  I believe your remaining issue is due to the pmu firmware.

I was not aware that we had changed the build options for the pmu firmware for kria, so using a standard zynqmp pmu firmware will fail.

This is what I currently have included as it is downloading a pre-build standard zynqmp pmu firmware.

Instead, if you take the pmu firmware from petalinux, convert it to a bin using objcopy and place this pmufw.bin in your buildroot dl/uboot directory, 
this will enable the correct pmufw getting included with your spl in your boot.bin generation.

Could you give this a try and let me know how you progress?

Best regards,
Neal Frager
AMD
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Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Wesley Revens]

Hi Neal,

On 09/05/2022 10:22, Neal Frager wrote:
> Hi Wesley,
>
>> U-Boot 2022.01 (May 09 2022 - 09:51:43 +0100)
>> CPU:   ZynqMP
>> Silicon: v3
>> PMUFW no permission to change config object Detected name: zynqmp-smk-k26-xcl2g-rev1-sck-kv-g-rev1
> I am working on this in parallel with you.  I believe your remaining issue is due to the pmu firmware.
>
> I was not aware that we had changed the build options for the pmu firmware for kria, so using a standard zynqmp pmu firmware will fail.
>
> This is what I currently have included as it is downloading a pre-build standard zynqmp pmu firmware.
>
> Instead, if you take the pmu firmware from petalinux, convert it to a bin using objcopy and place this pmufw.bin in your buildroot dl/uboot directory,
> this will enable the correct pmufw getting included with your spl in your boot.bin generation.
>
> Could you give this a try and let me know how you progress?
>
> Best regards,
> Neal Frager
> AMD
> _______________________________________________
> buildroot mailing list
> buildroot@buildroot.org
> https://lists.buildroot.org/mailman/listinfo/buildroot
I initially tried using pmufw from the xilinx-k26-starterkit-2021.1 
petalinux BSP
but that failed. So I tried the pmufw from the 2022.1 BSP instead and 
have now made some more progress.

My board is booting to a u-boot prompt now but not continuing into Linux 
from the SD card.

Here is my console output:

U-Boot SPL 2022.01 (May 09 2022 - 11:47:58 +0100)
PMUFW:  v1.1
Loading new PMUFW cfg obj (2016 bytes)
Silicon version:        3
EL Level:       EL3
Chip ID:        xck26
Multiboot:      64
Trying to boot from SPI
NOTICE:  BL31: v2.6(release):
NOTICE:  BL31: Built : 09:51:09, May  9 2022


U-Boot 2022.01 (May 09 2022 - 11:47:58 +0100)

CPU:   ZynqMP
Silicon: v3
PMUFW no permission to change config object
Detected name: zynqmp-smk-k26-xcl2g-rev1-sck-kv-g-rev1
Model: Avnet Ultra96 Rev1
Board: Xilinx ZynqMP
DRAM:  2 GiB
PMUFW:  v1.1
EL Level:       EL2
Chip ID:        xck26
PMUFW no permission to change config object
NAND:  0 MiB
MMC:   PMUFW no permission to change config object
PMUFW no permission to change config object
mmc@ff160000: 0, mmc@ff170000: 1
Loading Environment from SPIFlash... PMUFW no permission to change 
config object
spi_xfer: Timeout! TX FIFO not full
*** Warning - spi_flash_probe_bus_cs() failed, using default environment

In:    serial
Out:   serial
Err:   serial
PMUFW no permission to change config object
Bootmode: QSPI_MODE
Reset reason:   SOFT
Net:   No ethernet found.
scanning bus for devices...
Hit any key to stop autoboot:  0
spi_xfer: Timeout! TX FIFO not full
Failed to initialize SPI flash at 0:0 (error -2)
QSPI: SCRIPT FAILED: continuing...
JTAG: Trying to boot script at 20000000
## Executing script at 20000000
Wrong image format for "source" command
JTAG: SCRIPT FAILED: continuing...
Card did not respond to voltage select! : -110
failed to set vqmmc-voltage to 3.3V
failed to set vqmmc-voltage to 3.3V
failed to set vqmmc-voltage to 3.3V
failed to set vqmmc-voltage to 3.3V
failed to set vqmmc-voltage to 3.3V
failed to set vqmmc-voltage to 3.3V
Card did not respond to voltage select! : -110
spi_xfer: Timeout! TX FIFO not full
Failed to initialize SPI flash at 0:0 (error -2)
QSPI: SCRIPT FAILED: continuing...


no devices available
NAND: SCRIPT FAILED: continuing...
starting USB...
Bus usb@fe300000: PMUFW no permission to change config object
psgtr_phy phy@fd400000: lane 3 (type 1, protocol 3): PLL lock timeout
psgtr_phy phy@fd400000: PHY: Failed to power on phy@fd400000: -110.
probe failed, error -110
No working controllers found
USB is stopped. Please issue 'usb start' first.
starting USB...
Bus usb@fe300000: PMUFW no permission to change config object
psgtr_phy phy@fd400000: lane 3 (type 1, protocol 3): PLL lock timeout
psgtr_phy phy@fd400000: PHY: Failed to power on phy@fd400000: -110.
probe failed, error -110
No working controllers found
USB is stopped. Please issue 'usb start' first.

Device 0: unknown device
starting USB...
Bus usb@fe300000: PMUFW no permission to change config object
psgtr_phy phy@fd400000: lane 3 (type 1, protocol 3): PLL lock timeout
psgtr_phy phy@fd400000: PHY: Failed to power on phy@fd400000: -110.
probe failed, error -110
No working controllers found
No ethernet found.
missing environment variable: pxeuuid
Retrieving file: pxelinux.cfg/00000000
No ethernet found.
Retrieving file: pxelinux.cfg/0000000
No ethernet found.
Retrieving file: pxelinux.cfg/000000
No ethernet found.
Retrieving file: pxelinux.cfg/00000
No ethernet found.
Retrieving file: pxelinux.cfg/0000
No ethernet found.
Retrieving file: pxelinux.cfg/000
No ethernet found.
Retrieving file: pxelinux.cfg/00
No ethernet found.
Retrieving file: pxelinux.cfg/0
No ethernet found.
Retrieving file: pxelinux.cfg/default-arm-zynqmp-zynqmp
No ethernet found.
Retrieving file: pxelinux.cfg/default-arm-zynqmp
No ethernet found.
Retrieving file: pxelinux.cfg/default-arm
No ethernet found.
Retrieving file: pxelinux.cfg/default
No ethernet found.
Config file not found
starting USB...
Bus usb@fe300000: PMUFW no permission to change config object
psgtr_phy phy@fd400000: lane 3 (type 1, protocol 3): PLL lock timeout
psgtr_phy phy@fd400000: PHY: Failed to power on phy@fd400000: -110.
probe failed, error -110
No working controllers found
No ethernet found.
No ethernet found.
ZynqMP>
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Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Neal Frager]

Hi Wesley,

> I initially tried using pmufw from the xilinx-k26-starterkit-2021.1 petalinux BSP but that failed. So I tried the pmufw from the 2022.1 BSP instead and have now made some more progress.

> My board is booting to a u-boot prompt now but not continuing into Linux from the SD card.

Have you added the following to your board/zynqmp/kria/kv260/uboot.fragment as recommended by Michal?

CONFIG_DEFAULT_DEVICE_TREE="zynqmp-smk-k26-revA"
CONFIG_SYS_SPI_U_BOOT_OFFS=0xF80000
CONFIG_DTB_RESELECT=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_DMA=y
CONFIG_XILINX_DPDMA=y
CONFIG_PHY=y
CONFIG_PHY_XILINX_ZYNQMP=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_POWER_DOMAIN=y
CONFIG_ZYNQMP_POWER_DOMAIN=y
CONFIG_DM_RESET=y
CONFIG_RESET_ZYNQMP=y
CONFIG_VIDEO_ZYNQMP_DPSUB=y

Best regards,
Neal Frager
AMD
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Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Wesley Revens]

Hi Neal,

On 09/05/2022 12:00, Neal Frager wrote:
> Hi Wesley,
>
>> I initially tried using pmufw from the xilinx-k26-starterkit-2021.1 petalinux BSP but that failed. So I tried the pmufw from the 2022.1 BSP instead and have now made some more progress.
>> My board is booting to a u-boot prompt now but not continuing into Linux from the SD card.
> Have you added the following to your board/zynqmp/kria/kv260/uboot.fragment as recommended by Michal?
>
> CONFIG_DEFAULT_DEVICE_TREE="zynqmp-smk-k26-revA"
> CONFIG_SYS_SPI_U_BOOT_OFFS=0xF80000
> CONFIG_DTB_RESELECT=y
> CONFIG_MULTI_DTB_FIT=y
> CONFIG_ENV_IS_NOWHERE=y
> CONFIG_DMA=y
> CONFIG_XILINX_DPDMA=y
> CONFIG_PHY=y
> CONFIG_PHY_XILINX_ZYNQMP=y
> CONFIG_PINCTRL=y
> CONFIG_PINCONF=y
> CONFIG_POWER_DOMAIN=y
> CONFIG_ZYNQMP_POWER_DOMAIN=y
> CONFIG_DM_RESET=y
> CONFIG_RESET_ZYNQMP=y
> CONFIG_VIDEO_ZYNQMP_DPSUB=y
>
> Best regards,
> Neal Frager
> AMD
> _______________________________________________
> buildroot mailing list
> buildroot@buildroot.org
> https://lists.buildroot.org/mailman/listinfo/buildroot

Yes I have those configs set - the only ones from Michal's list that I 
don't have are:

CONFIG_ENV_IS_NOWHERE=y (only)
CONFIG_USE_DEFAULT_ENV_FILE=y
CONFIG_DEFAULT_ENV_FILE="vars"

When I was using the pre-loaded QSPI bootloader to boot my Linux image I 
had to enable some peripherals in the Linux device tree to get Linux to 
start correctly (e.g. disabling write protection on sdhci1 and enabling 
the phy) Are any changed like that going to be required in the u-boot 
device trees?

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Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Neal Frager]

Hi Wesley,

> When I was using the pre-loaded QSPI bootloader to boot my Linux image I had to enable some peripherals in the Linux device tree to get Linux to start correctly (e.g. disabling write protection on sdhci1 and enabling the phy) Are any changed like that going to be required in the u-boot device trees?

Could you try replacing your u-boot board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c file with the original commit below?

https://github.com/u-boot/u-boot/commit/02ac1553b8329f866c1761f5d9fe66972817782c

Please let me know if this version of the file resolves your SD card issue.

Best regards,
Neal Frager
AMD
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Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Wesley Revens]

Hi Neal,

On 09/05/2022 14:46, Neal Frager wrote:
> Hi Wesley,
>
>> When I was using the pre-loaded QSPI bootloader to boot my Linux image I had to enable some peripherals in the Linux device tree to get Linux to start correctly (e.g. disabling write protection on sdhci1 and enabling the phy) Are any changed like that going to be required in the u-boot device trees?
> Could you try replacing your u-boot board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c file with the original commit below?
>
> https://github.com/u-boot/u-boot/commit/02ac1553b8329f866c1761f5d9fe66972817782c
>
> Please let me know if this version of the file resolves your SD card issue.
>
> Best regards,
> Neal Frager
> AMD
> _______________________________________________
> buildroot mailing list
> buildroot@buildroot.org
> https://lists.buildroot.org/mailman/listinfo/buildroot

No change with the updated psu_init_gpl.c.

When using the pmufw from the 2022.1 BSP is there a different 
pm_cfg_obj.c also required?

I am still using the original in buildroot/board/zynqmp/kria/kv260

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Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Neal Frager]

Hi Wesley,

> No change with the updated psu_init_gpl.c.

> When using the pmufw from the 2022.1 BSP is there a different pm_cfg_obj.c also required?

> I am still using the original in buildroot/board/zynqmp/kria/kv260

I am currently stuck in the same place as you with the exact same boot log.  

I generated the buildroot/board/zynqmp/kria/kv260/pm_cfg_obj.c with Vitis 2022.1, so this file should not be the issue.

Also, for completeness, only the zynqmp_console needed to be correctly defined for the atf as the zynqmp uses uart1.
BR2_TARGET_ARM_TRUSTED_FIRMWARE_ADDITIONAL_VARIABLES="ZYNQMP_CONSOLE=cadence1"

The PRELOADED_BL33_BASE parameter was already correct by default when using the zynqmp platform.

Once we get this working properly, I will patch buildroot, so other users will have a working solution.

Thank you for your patience and let me know if you make any progress on your side.

Best regards,
Neal Frager
AMD

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Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Wesley Revens]

Hi Neal,

On 09/05/2022 15:41, Neal Frager wrote:
> Hi Wesley,
>
>> No change with the updated psu_init_gpl.c.
>> When using the pmufw from the 2022.1 BSP is there a different pm_cfg_obj.c also required?
>> I am still using the original in buildroot/board/zynqmp/kria/kv260
> I am currently stuck in the same place as you with the exact same boot log.
Glad I'm not the only one!
>
> I generated the buildroot/board/zynqmp/kria/kv260/pm_cfg_obj.c with Vitis 2022.1, so this file should not be the issue.
>
> Also, for completeness, only the zynqmp_console needed to be correctly defined for the atf as the zynqmp uses uart1.
> BR2_TARGET_ARM_TRUSTED_FIRMWARE_ADDITIONAL_VARIABLES="ZYNQMP_CONSOLE=cadence1"
>
> The PRELOADED_BL33_BASE parameter was already correct by default when using the zynqmp platform.
If I leave out the PRELOADED_BL33_BASE setting, my ATF does not run and 
I get stuck at the end of U-Boot SPL with "Trying to boot from SPI"
>
> Once we get this working properly, I will patch buildroot, so other users will have a working solution.
>
> Thank you for your patience and let me know if you make any progress on your side.
No problem, It will be good to get it all working
> Best regards,
> Neal Frager
> AMD
>
Regards,
Wesley
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Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Neal Frager]

Hi Wesley,

On 09/05/2022 15:41, Neal Frager wrote:
> Hi Wesley,
>
>> No change with the updated psu_init_gpl.c.
>> When using the pmufw from the 2022.1 BSP is there a different pm_cfg_obj.c also required?
>> I am still using the original in buildroot/board/zynqmp/kria/kv260
> I am currently stuck in the same place as you with the exact same boot log.
> Glad I'm not the only one!
>
> I generated the buildroot/board/zynqmp/kria/kv260/pm_cfg_obj.c with Vitis 2022.1, so this file should not be the issue.
>
> Also, for completeness, only the zynqmp_console needed to be correctly defined for the atf as the zynqmp uses uart1.
> BR2_TARGET_ARM_TRUSTED_FIRMWARE_ADDITIONAL_VARIABLES="ZYNQMP_CONSOLE=cadence1"
>
> The PRELOADED_BL33_BASE parameter was already correct by default when using the zynqmp platform.
> If I leave out the PRELOADED_BL33_BASE setting, my ATF does not run and I get stuck at the end of U-Boot SPL with "Trying to boot from SPI"

Not sure why.  When we have a working version, I would suggest testing a clean build.

>
> Once we get this working properly, I will patch buildroot, so other users will have a working solution.
>
> Thank you for your patience and let me know if you make any progress on your side.
> No problem, It will be good to get it all working
> Best regards,
> Neal Frager
> AMD
>

I am getting farther along by doing the following:

fdtoverlay -o dtb/zynqmp-smk-k26-xcl2g-ed-rev1-sck-kv-g-rev1.dtb -i arch/arm/dts/zynqmp-smk-k26-revA.dtb arch/arm/dts/zynqmp-sck-kv-g-revB.dtbo

modification of u-boot.its:
		fdt_1 {
			description = "Multi DTB fit image";
-			data = /incbin/("fit-dtb.blob");
+			data = /incbin/("dtb/zynqmp-smk-k26-xcl2g-ed-rev1-sck-kv-g-rev1.dtb");
			type = "flat_dt";
			arch = "arm64";
			compression = "none";
			load = <0x0 0x100000>;
			hash {
				algo = "md5";
			};
		};

./tools/mkimage -E -f u-boot.its -B 0x8  u-boot.itb

Using this u-boot.itb at qspi address 0xF80000, I am able to detect the sd card and boot the Linux kernel.

Could you give it a try on your end?

Best regards,
Neal Frager
AMD
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Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Neal Frager]

Hi Wesley,

Simplifying the steps, here is what you need to do to get this working.

1. Make sure you are using the psu_init_gpl.c which is the latest commit, not the original one that I told you to try yesterday.

2. After build, run the following two lines from your u-boot-custom directory.

fdtoverlay -o fit-dtb.blob -i arch/arm/dts/zynqmp-smk-k26-revA.dtb arch/arm/dts/zynqmp-sck-kv-g-revB.dtbo
./tools/mkimage -E -f u-boot.its -B 0x8 u-boot.itb

3. Optional: if you use the Boot Image Recovery Tool, rename the u-boot.itb to u-boot.itb.bin.

4. Flash the u-boot.itb to QSPI address 0xF80000 and boot.bin to 0x200000.

My boot log: (there is still some funny stuff in the kernel boot text, but perhaps @Michal Simek can help us with this)

U-Boot SPL 2022.01 (May 10 2022 - 05:13:31 +0100)
PMUFW:  v1.1
Loading new PMUFW cfg obj (2016 bytes)
Silicon version:        3
EL Level:       EL3
Chip ID:        xck26
Multiboot:      64
Trying to boot from SPI
NOTICE:  BL31: v2.6(release):2022.02-858-gcdcacf770b-dirty
NOTICE:  BL31: Built : 12:07:21, May  9 2022


U-Boot 2022.01 (May 10 2022 - 05:13:31 +0100)

CPU:   ZynqMP
Silicon: v3
PMUFW no permission to change config object
Detected name: zynqmp-smk-k26-xcl2g-ed-rev1-sck-kv-g-rev1
Model: ZynqMP SMK-K26 Rev1/B/A
Board: Xilinx ZynqMP
DRAM:  4 GiB
PMUFW:  v1.1
PMUFW no permission to change config object
Xilinx I2C FRU format at nvmem0:
 Manufacturer Name: XILINX
 Product Name: SMK-K26-XCL2G-ED
 Serial No: XFL1CUZFT4MS
 Part Number: 5057-01ED
 File ID: 0x0
 Revision Number: 1
Xilinx I2C FRU format at nvmem1:
 Manufacturer Name: XILINX
 Product Name: SCK-KV-G
 Serial No: XFL1I21C5KSA
 Part Number: 5066-01ED
 File ID: 0x0
 Revision Number: 1
EL Level:       EL2
Chip ID:        xck26
PMUFW no permission to change config object
NAND:  0 MiB
MMC:   PMUFW no permission to change config object
mmc@ff170000: 1
Loading Environment from SPIFlash... PMUFW no permission to change config object
SF: Detected mt25qu512a with page size 256 Bytes, erase size 64 KiB, total 64 MiB
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
PMUFW no permission to change config object
PMUFW no permission to change config object
Bootmode: QSPI_MODE
Reset reason:   SOFT
Net:
ZYNQ GEM: ff0e0000, mdio bus ff0e0000, phyaddr 1, interface rgmii-id
PMUFW no permission to change config object
PHY reset timed out
eth0: ethernet@ff0e0000
scanning bus for devices...
Hit any key to stop autoboot:  0
SF: Detected mt25qu512a with page size 256 Bytes, erase size 64 KiB, total 64 MiB
device 0 offset 0x3e80000, size 0x80000
SF: 524288 bytes @ 0x3e80000 Read: OK
QSPI: Trying to boot script at 20000000
## Executing script at 20000000
Wrong image format for "source" command
QSPI: SCRIPT FAILED: continuing...
JTAG: Trying to boot script at 20000000
## Executing script at 20000000
Wrong image format for "source" command
JTAG: SCRIPT FAILED: continuing...
MMC Device 0 not found
no mmc device at slot 0
switch to partitions #0, OK
mmc1 is current device
Scanning mmc 1:1...
Found /extlinux/extlinux.conf
Retrieving file: /extlinux/extlinux.conf
1:      linux
Retrieving file: /Image
append: console=ttyPS1,115200 root=/dev/mmcblk1p2 rw rootwait
Retrieving file: /system.dtb
## Flattened Device Tree blob at 40000000
   Booting using the fdt blob at 0x40000000
   Loading Device Tree to 000000007b910000, end 000000007b91d4c4 ... OK

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[    0.000000] Linux version 5.15.19 (nealf@xirengwts08) (aarch64-buildroot-linux-uclibc-gcc.br_real (Buildroot 2022.02-475-gb8cfbf144e) 10.3.0, GNU ld (GNU Binutils) 2.36.1) #1 SMP Tue Apr 12 14:50:17 IST 2022
[    0.000000] Machine model: ZynqMP SMK-K26 Rev1/B/A
[    0.000000] efi: UEFI not found.
[    0.000000] Zone ranges:
[    0.000000]   DMA32    [mem 0x0000000000000000-0x00000000ffffffff]
[    0.000000]   Normal   [mem 0x0000000100000000-0x000000087fffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000000000000-0x000000007fffffff]
[    0.000000]   node   0: [mem 0x0000000800000000-0x000000087fffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x000000087fffffff]
[    0.000000] cma: Reserved 256 MiB at 0x000000006b800000
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: MIGRATE_INFO_TYPE not supported.
[    0.000000] psci: SMC Calling Convention v1.2
[    0.000000] percpu: Embedded 18 pages/cpu s33048 r8192 d32488 u73728
[    0.000000] Detected VIPT I-cache on CPU0
[    0.000000] CPU features: detected: ARM erratum 845719
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 1034240
[    0.000000] Kernel command line: console=ttyPS1,115200 root=/dev/mmcblk1p2 rw rootwait
[    0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
[    0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[    0.000000] software IO TLB: mapped [mem 0x000000007c000000-0x0000000080000000] (64MB)
[    0.000000] Memory: 3772552K/4194304K available (13824K kernel code, 900K rwdata, 3872K rodata, 1984K init, 328K bss, 159608K reserved, 262144K cma-reserved)
[    0.000000] rcu: Hierarchical RCU implementation.
[    0.000000] rcu:     RCU event tracing is enabled.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GIC: Adjusting CPU interface base to 0x00000000f902f000
[    0.000000] Root IRQ handler: gic_handle_irq
[    0.000000] GIC: Using split EOI/Deactivate mode
[    0.000000] random: get_random_bytes called from start_kernel+0x470/0x6f8 with crng_init=0
[    0.000000] arch_timer: cp15 timer(s) running at 99.99MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x171015c90f, max_idle_ns: 440795203080 ns
[    0.000000] sched_clock: 56 bits at 99MHz, resolution 10ns, wraps every 4398046511101ns
[    0.000266] Console: colour dummy device 80x25
[    0.000296] Calibrating delay loop (skipped), value calculated using timer frequency.. 199.99 BogoMIPS (lpj=399996)
[    0.000307] pid_max: default: 32768 minimum: 301
[    0.000410] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
[    0.000428] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
[    0.001208] rcu: Hierarchical SRCU implementation.
[    0.001429] EFI services will not be available.
[    0.001544] smp: Bringing up secondary CPUs ...
[    0.002103] Detected VIPT I-cache on CPU1
[    0.002140] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
[    0.002614] Detected VIPT I-cache on CPU2
[    0.002635] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
[    0.003070] Detected VIPT I-cache on CPU3
[    0.003091] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
[    0.003129] smp: Brought up 1 node, 4 CPUs
[    0.003144] SMP: Total of 4 processors activated.
[    0.003150] CPU features: detected: 32-bit EL0 Support
[    0.003154] CPU features: detected: CRC32 instructions
[    0.003191] CPU: All CPU(s) started at EL2
[    0.003206] alternatives: patching kernel code
[    0.004254] devtmpfs: initialized
[    0.009102] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.009119] futex hash table entries: 1024 (order: 4, 65536 bytes, linear)
[    0.016581] pinctrl core: initialized pinctrl subsystem
[    0.017191] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[    0.018109] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
[    0.018196] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
[    0.018232] audit: initializing netlink subsys (disabled)
[    0.018304] audit: type=2000 audit(0.016:1): state=initialized audit_enabled=0 res=1
[    0.018598] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.018652] ASID allocator initialised with 65536 entries
[    0.034892] HugeTLB registered 1.00 GiB page size, pre-allocated 0 pages
[    0.034906] HugeTLB registered 32.0 MiB page size, pre-allocated 0 pages
[    0.034911] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[    0.034917] HugeTLB registered 64.0 KiB page size, pre-allocated 0 pages
[    0.992657] DRBG: Continuing without Jitter RNG
[    1.092615] raid6: neonx8   gen()  2374 MB/s
[    1.160658] raid6: neonx8   xor()  1770 MB/s
[    1.228718] raid6: neonx4   gen()  2419 MB/s
[    1.296756] raid6: neonx4   xor()  1749 MB/s
[    1.364815] raid6: neonx2   gen()  2297 MB/s
[    1.432862] raid6: neonx2   xor()  1605 MB/s
[    1.500923] raid6: neonx1   gen()  1992 MB/s
[    1.568963] raid6: neonx1   xor()  1378 MB/s
[    1.637021] raid6: int64x8  gen()  1634 MB/s
[    1.705061] raid6: int64x8  xor()   872 MB/s
[    1.773113] raid6: int64x4  gen()  1786 MB/s
[    1.841161] raid6: int64x4  xor()   935 MB/s
[    1.909222] raid6: int64x2  gen()  1552 MB/s
[    1.977265] raid6: int64x2  xor()   832 MB/s
[    2.045328] raid6: int64x1  gen()  1319 MB/s
[    2.113369] raid6: int64x1  xor()   662 MB/s
[    2.113374] raid6: using algorithm neonx4 gen() 2419 MB/s
[    2.113379] raid6: .... xor() 1749 MB/s, rmw enabled
[    2.113383] raid6: using neon recovery algorithm
[    2.113818] iommu: Default domain type: Translated
[    2.113825] iommu: DMA domain TLB invalidation policy: strict mode
[    2.114020] SCSI subsystem initialized
[    2.114154] usbcore: registered new interface driver usbfs
[    2.114180] usbcore: registered new interface driver hub
[    2.114202] usbcore: registered new device driver usb
[    2.114251] mc: Linux media interface: v0.10
[    2.114270] videodev: Linux video capture interface: v2.00
[    2.114302] pps_core: LinuxPPS API ver. 1 registered
[    2.114307] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    2.114318] PTP clock support registered
[    2.114343] EDAC MC: Ver: 3.0.0
[    2.114601] zynqmp-ipi-mbox mailbox@ff990400: Registered ZynqMP IPI mbox with TX/RX channels.
[    2.114783] FPGA manager framework
[    2.114876] Advanced Linux Sound Architecture Driver Initialized.
[    2.115161] Bluetooth: Core ver 2.22
[    2.115183] NET: Registered PF_BLUETOOTH protocol family
[    2.115188] Bluetooth: HCI device and connection manager initialized
[    2.115196] Bluetooth: HCI socket layer initialized
[    2.115202] Bluetooth: L2CAP socket layer initialized
[    2.115212] Bluetooth: SCO socket layer initialized
[    2.115501] clocksource: Switched to clocksource arch_sys_counter
[    2.115597] VFS: Disk quotas dquot_6.6.0
[    2.115632] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    2.119292] NET: Registered PF_INET protocol family
[    2.119417] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
[    2.120831] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
[    2.120873] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
[    2.121059] TCP bind hash table entries: 32768 (order: 7, 524288 bytes, linear)
[    2.121417] TCP: Hash tables configured (established 32768 bind 32768)
[    2.121485] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
[    2.121554] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
[    2.121681] NET: Registered PF_UNIX/PF_LOCAL protocol family
[    2.122030] RPC: Registered named UNIX socket transport module.
[    2.122037] RPC: Registered udp transport module.
[    2.122041] RPC: Registered tcp transport module.
[    2.122045] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    2.122606] PCI: CLS 0 bytes, default 64
[    2.123001] armv8-pmu pmu: hw perfevents: no interrupt-affinity property, guessing.
[    2.123148] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
[    2.123865] Initialise system trusted keyrings
[    2.123944] workingset: timestamp_bits=62 max_order=20 bucket_order=0
[    2.124451] NFS: Registering the id_resolver key type
[    2.124463] Key type id_resolver registered
[    2.124467] Key type id_legacy registered
[    2.124484] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[    2.124490] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
[    2.124506] jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
[    2.156276] NET: Registered PF_ALG protocol family
[    2.156286] xor: measuring software checksum speed
[    2.159931]    8regs           :  2709 MB/sec
[    2.163096]    32regs          :  3112 MB/sec
[    2.166940]    arm64_neon      :  2565 MB/sec
[    2.166945] xor: using function: 32regs (3112 MB/sec)
[    2.166952] Key type asymmetric registered
[    2.166958] Asymmetric key parser 'x509' registered
[    2.166992] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
[    2.166999] io scheduler mq-deadline registered
[    2.167004] io scheduler kyber registered
[    2.190839] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    2.192453] cacheinfo: Unable to detect cache hierarchy for CPU 0
[    2.196113] brd: module loaded
[    2.199046] loop: module loaded
[    2.199711] mtdoops: mtd device (mtddev=name/number) must be supplied
[    2.201860] tun: Universal TUN/TAP device driver, 1.6
[    2.201943] CAN device driver interface
[    2.202444] SPI driver wl1271_spi has no spi_device_id for ti,wl1271
[    2.202450] SPI driver wl1271_spi has no spi_device_id for ti,wl1273
[    2.202455] SPI driver wl1271_spi has no spi_device_id for ti,wl1281
[    2.202459] SPI driver wl1271_spi has no spi_device_id for ti,wl1283
[    2.202464] SPI driver wl1271_spi has no spi_device_id for ti,wl1285
[    2.202468] SPI driver wl1271_spi has no spi_device_id for ti,wl1801
[    2.202472] SPI driver wl1271_spi has no spi_device_id for ti,wl1805
[    2.202476] SPI driver wl1271_spi has no spi_device_id for ti,wl1807
[    2.202481] SPI driver wl1271_spi has no spi_device_id for ti,wl1831
[    2.202485] SPI driver wl1271_spi has no spi_device_id for ti,wl1835
[    2.202489] SPI driver wl1271_spi has no spi_device_id for ti,wl1837
[    2.202567] usbcore: registered new interface driver asix
[    2.202607] usbcore: registered new interface driver ax88179_178a
[    2.202628] usbcore: registered new interface driver cdc_ether
[    2.202647] usbcore: registered new interface driver net1080
[    2.202669] usbcore: registered new interface driver cdc_subset
[    2.202689] usbcore: registered new interface driver zaurus
[    2.202718] usbcore: registered new interface driver cdc_ncm
[    2.203315] usbcore: registered new interface driver uas
[    2.203346] usbcore: registered new interface driver usb-storage
[    2.203958] rtc_zynqmp ffa60000.rtc: registered as rtc0
[    2.203975] rtc_zynqmp ffa60000.rtc: setting system clock to 1970-01-01T00:01:19 UTC (79)
[    2.204029] i2c_dev: i2c /dev entries driver
[    2.205321] usbcore: registered new interface driver uvcvideo
[    2.206000] Bluetooth: HCI UART driver ver 2.3
[    2.206006] Bluetooth: HCI UART protocol H4 registered
[    2.206012] Bluetooth: HCI UART protocol BCSP registered
[    2.206028] Bluetooth: HCI UART protocol LL registered
[    2.206033] Bluetooth: HCI UART protocol ATH3K registered
[    2.206047] Bluetooth: HCI UART protocol Three-wire (H5) registered
[    2.206079] Bluetooth: HCI UART protocol Intel registered
[    2.206094] Bluetooth: HCI UART protocol QCA registered
[    2.206120] usbcore: registered new interface driver bcm203x
[    2.206145] usbcore: registered new interface driver bpa10x
[    2.206168] usbcore: registered new interface driver bfusb
[    2.206192] usbcore: registered new interface driver btusb
[    2.206228] usbcore: registered new interface driver ath3k
[    2.206299] EDAC MC: ECC not enabled
[    2.206410] EDAC DEVICE0: Giving out device to module edac controller cache_err: DEV edac (POLLED)
[    2.206552] EDAC DEVICE1: Giving out device to module zynqmp-ocm-edac controller zynqmp_ocm: DEV ff960000.memory-controller (INTERRUPT)
[    2.206843] sdhci: Secure Digital Host Controller Interface driver
[    2.206848] sdhci: Copyright(c) Pierre Ossman
[    2.206852] sdhci-pltfm: SDHCI platform and OF driver helper
[    2.207161] ledtrig-cpu: registered to indicate activity on CPUs
[    2.207276] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....
[    2.207416] zynqmp_firmware_probe Platform Management API v1.1
[    2.207427] zynqmp_firmware_probe Trustzone version v1.0
[    2.242772] securefw securefw: securefw probed
[    2.243008] alg: No test for xilinx-zynqmp-aes (zynqmp-aes)
[    2.243028] zynqmp_aes firmware:zynqmp-firmware:zynqmp-aes: AES Successfully Registered
[    2.243183] alg: No test for xilinx-keccak-384 (zynqmp-keccak-384)
[    2.243339] alg: No test for xilinx-zynqmp-rsa (zynqmp-rsa)
[    2.243471] usbcore: registered new interface driver usbhid
[    2.243477] usbhid: USB HID core driver
[    2.246616] fpga_manager fpga0: Xilinx ZynqMP FPGA Manager registered
[    2.246909] usbcore: registered new interface driver snd-usb-audio
[    2.247600] pktgen: Packet Generator for packet performance testing. Version: 2.75
[    2.247968] Initializing XFRM netlink socket
[    2.248041] NET: Registered PF_INET6 protocol family
[    2.248463] Segment Routing with IPv6
[    2.248481] In-situ OAM (IOAM) with IPv6
[    2.248529] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[    2.248829] NET: Registered PF_PACKET protocol family
[    2.248844] NET: Registered PF_KEY protocol family
[    2.248865] can: controller area network core
[    2.248889] NET: Registered PF_CAN protocol family
[    2.248895] can: raw protocol
[    2.248901] can: broadcast manager protocol
[    2.248908] can: netlink gateway - max_hops=1
[    2.248985] Bluetooth: RFCOMM TTY layer initialized
[    2.248995] Bluetooth: RFCOMM socket layer initialized
[    2.249007] Bluetooth: RFCOMM ver 1.11
[    2.249016] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[    2.249020] Bluetooth: BNEP filters: protocol multicast
[    2.249026] Bluetooth: BNEP socket layer initialized
[    2.249031] Bluetooth: HIDP (Human Interface Emulation) ver 1.2
[    2.249037] Bluetooth: HIDP socket layer initialized
[    2.249065] 8021q: 802.1Q VLAN Support v1.8
[    2.249148] 9pnet: Installing 9P2000 support
[    2.249168] Key type dns_resolver registered
[    2.249270] registered taskstats version 1
[    2.249275] Loading compiled-in X.509 certificates
[    2.250219] Btrfs loaded, crc32c=crc32c-generic, zoned=no, fsverity=no
[    2.258617] ff010000.serial: ttyPS1 at MMIO 0xff010000 (irq = 51, base_baud = 6249999) is a xuartps
[    3.629663] printk: console [ttyPS1] enabled
[    3.634347] of-fpga-region fpga-full: FPGA Region probed
[    3.640717] xilinx-zynqmp-dma fd500000.dma-controller: ZynqMP DMA driver Probe success
[    3.648793] xilinx-zynqmp-dma fd510000.dma-controller: ZynqMP DMA driver Probe success
[    3.656853] xilinx-zynqmp-dma fd520000.dma-controller: ZynqMP DMA driver Probe success
[    3.664918] xilinx-zynqmp-dma fd530000.dma-controller: ZynqMP DMA driver Probe success
[    3.672973] xilinx-zynqmp-dma fd540000.dma-controller: ZynqMP DMA driver Probe success
[    3.681031] xilinx-zynqmp-dma fd550000.dma-controller: ZynqMP DMA driver Probe success
[    3.689092] xilinx-zynqmp-dma fd560000.dma-controller: ZynqMP DMA driver Probe success
[    3.697165] xilinx-zynqmp-dma fd570000.dma-controller: ZynqMP DMA driver Probe success
[    3.705354] xilinx-zynqmp-dma ffa80000.dma-controller: ZynqMP DMA driver Probe success
[    3.713438] xilinx-zynqmp-dma ffa90000.dma-controller: ZynqMP DMA driver Probe success
[    3.721498] xilinx-zynqmp-dma ffaa0000.dma-controller: ZynqMP DMA driver Probe success
[    3.729566] xilinx-zynqmp-dma ffab0000.dma-controller: ZynqMP DMA driver Probe success
[    3.737625] xilinx-zynqmp-dma ffac0000.dma-controller: ZynqMP DMA driver Probe success
[    3.745692] xilinx-zynqmp-dma ffad0000.dma-controller: ZynqMP DMA driver Probe success
[    3.753752] xilinx-zynqmp-dma ffae0000.dma-controller: ZynqMP DMA driver Probe success
[    3.761825] xilinx-zynqmp-dma ffaf0000.dma-controller: ZynqMP DMA driver Probe success
[    3.769928] zynqmp_clk_divider_set_rate() set divider failed for dpdma_ref_div1, ret = -13
[    3.778621] xilinx-zynqmp-dpdma fd4c0000.dma-controller: Xilinx DPDMA engine is probed
[    3.788560] ------------[ cut here ]------------
[    3.793176] More than allowed devices are using the vpll_int, which is forbidden
[    3.800598] WARNING: CPU: 0 PID: 7 at drivers/clk/zynqmp/pll.c:200 zynqmp_pll_set_rate+0x198/0x200
[    3.809558] Modules linked in:
[    3.812606] CPU: 0 PID: 7 Comm: kworker/u8:0 Not tainted 5.15.19 #1
[    3.818863] Hardware name: ZynqMP SMK-K26 Rev1/B/A (DT)
[    3.824081] Workqueue: events_unbound deferred_probe_work_func
[    3.829913] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[    3.836865] pc : zynqmp_pll_set_rate+0x198/0x200
[    3.841474] lr : zynqmp_pll_set_rate+0x198/0x200
[    3.846083] sp : ffffffc0095239b0
[    3.849390] x29: ffffffc0095239b0 x28: 0000000000000000 x27: fffffffdfdd174e4
[    3.856526] x26: 000000000000ffff x25: ffffff88016de180 x24: 0000000000000060
[    3.863652] x23: 0000000001fca055 x22: ffffff88016de180 x21: ffffff88016de200
[    3.870778] x20: 0000000001fc9e58 x19: 00000000b0d3bd8d x18: 0000000000000030
[    3.877904] x17: 6962726f66207369 x16: 206863696877202c x15: 746e695f6c6c7076
[    3.885031] x14: 2065687420676e69 x13: 6e6564646962726f x12: ffffffc00936b9b0
[    3.892157] x11: 000000000000010d x10: 6c6c707620656874 x9 : 00000000fffff7ff
[    3.899284] x8 : ffffffc0093979b0 x7 : 000000000000bfe8 x6 : 80000000fffff800
[    3.906410] x5 : 0000000000000000 x4 : 0000000000000000 x3 : 0000000000000000
[    3.913536] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffffff880009cd80
[    3.920663] Call trace:
[    3.923102]  zynqmp_pll_set_rate+0x198/0x200
[    3.927364]  clk_change_rate+0x148/0x2c0
[    3.931278]  clk_core_set_rate_nolock+0x154/0x240
[    3.935974]  clk_set_rate+0x38/0x150
[    3.939542]  of_clk_set_defaults+0x244/0x3a0
[    3.943804]  platform_probe+0x3c/0xe0
[    3.947458]  really_probe.part.0+0x9c/0x310
[    3.951633]  __driver_probe_device+0x98/0x150
[    3.955982]  driver_probe_device+0x44/0x120
[    3.960157]  __device_attach_driver+0xb4/0x120
[    3.964592]  bus_for_each_drv+0x78/0xd0
[    3.968420]  __device_attach+0xdc/0x190
[    3.972248]  device_initial_probe+0x14/0x20
[    3.976423]  bus_probe_device+0x9c/0xb0
[    3.980251]  deferred_probe_work_func+0x88/0xc0
[    3.984774]  process_one_work+0x1d4/0x390
[    3.988775]  worker_thread+0x298/0x4e0
[    3.992516]  kthread+0x120/0x130
[    3.995737]  ret_from_fork+0x10/0x20
[    3.999304] ---[ end trace 438bcf53a978d694 ]---
[    4.005681] zynqmp_pll_disable() clock disable failed for dpll_int, ret = -13
[    4.013544] zynqmp-display fd4a0000.display: vtc bridge property not present
[    4.022757] ------------[ cut here ]------------
[    4.027375] More than allowed devices are using the vpll_int, which is forbidden
[    4.034794] WARNING: CPU: 2 PID: 7 at drivers/clk/zynqmp/pll.c:200 zynqmp_pll_set_rate+0x198/0x200
[    4.043746] Modules linked in:
[    4.046795] CPU: 2 PID: 7 Comm: kworker/u8:0 Tainted: G        W         5.15.19 #1
[    4.054440] Hardware name: ZynqMP SMK-K26 Rev1/B/A (DT)
[    4.059658] Workqueue: events_unbound deferred_probe_work_func
[    4.065482] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[    4.072434] pc : zynqmp_pll_set_rate+0x198/0x200
[    4.077043] lr : zynqmp_pll_set_rate+0x198/0x200
[    4.081652] sp : ffffffc009523660
[    4.084959] x29: ffffffc009523660 x28: ffffff887f7f5550 x27: ffffff88016fac10
[    4.092094] x26: 000000000000b61b x25: ffffff88016de180 x24: 0000000000000060
[    4.099220] x23: 0000000001fca055 x22: ffffff88016de180 x21: ffffff88016de200
[    4.106347] x20: 000000000169cfa1 x19: 0000000059682ef1 x18: 0000000000000030
[    4.113473] x17: 6962726f66207369 x16: 206863696877202c x15: 746e695f6c6c7076
[    4.120599] x14: 2065687420676e69 x13: 6e6564646962726f x12: ffffffc00936b9b0
[    4.127726] x11: 0000000000000139 x10: 6c6c707620656874 x9 : 00000000fffff7ff
[    4.134853] x8 : ffffffc0093979b0 x7 : 000000000000bfe8 x6 : 80000000fffff800
[    4.141979] x5 : 0000000000000000 x4 : 0000000000000000 x3 : 0000000000000000
[    4.149105] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffffff880009cd80
[    4.156231] Call trace:
[    4.158671]  zynqmp_pll_set_rate+0x198/0x200
[    4.162932]  clk_change_rate+0x148/0x2c0
[    4.166847]  clk_core_set_rate_nolock+0x154/0x240
[    4.171543]  clk_set_rate+0x38/0x150
[    4.175111]  xilinx_dp_codec_probe+0xd4/0x1f0
[    4.179459]  platform_probe+0x68/0xe0
[    4.183114]  really_probe.part.0+0x9c/0x310
[    4.187289]  __driver_probe_device+0x98/0x150
[    4.191638]  driver_probe_device+0x44/0x120
[    4.195813]  __device_attach_driver+0xb4/0x120
[    4.200248]  bus_for_each_drv+0x78/0xd0
[    4.204076]  __device_attach+0xdc/0x190
[    4.207904]  device_initial_probe+0x14/0x20
[    4.212079]  bus_probe_device+0x9c/0xb0
[    4.215907]  device_add+0x36c/0x860
[    4.219388]  of_device_add+0x58/0x70
[    4.222956]  of_platform_device_create_pdata+0xc0/0x100
[    4.228172]  of_platform_bus_create+0x178/0x390
[    4.232694]  of_platform_populate+0x58/0xf0
[    4.236869]  zynqmp_dpsub_probe+0xe8/0x170
[    4.240958]  platform_probe+0x68/0xe0
[    4.244612]  really_probe.part.0+0x9c/0x310
[    4.248787]  __driver_probe_device+0x98/0x150
[    4.253136]  driver_probe_device+0x44/0x120
[    4.257311]  __device_attach_driver+0xb4/0x120
[    4.261747]  bus_for_each_drv+0x78/0xd0
[    4.265574]  __device_attach+0xdc/0x190
[    4.269402]  device_initial_probe+0x14/0x20
[    4.273578]  bus_probe_device+0x9c/0xb0
[    4.277405]  deferred_probe_work_func+0x88/0xc0
[    4.281928]  process_one_work+0x1d4/0x390
[    4.285929]  worker_thread+0x298/0x4e0
[    4.289671]  kthread+0x120/0x130
[    4.292891]  ret_from_fork+0x10/0x20
[    4.296458] ---[ end trace 438bcf53a978d695 ]---
[    4.303417] ------------[ cut here ]------------
[    4.308027] More than allowed devices are using the vpll_int, which is forbidden
[    4.315443] WARNING: CPU: 2 PID: 7 at drivers/clk/zynqmp/pll.c:200 zynqmp_pll_set_rate+0x198/0x200
[    4.324400] Modules linked in:
[    4.327446] CPU: 2 PID: 7 Comm: kworker/u8:0 Tainted: G        W         5.15.19 #1
[    4.335093] Hardware name: ZynqMP SMK-K26 Rev1/B/A (DT)
[    4.340311] Workqueue: events_unbound deferred_probe_work_func
[    4.346135] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[    4.353087] pc : zynqmp_pll_set_rate+0x198/0x200
[    4.357696] lr : zynqmp_pll_set_rate+0x198/0x200
[    4.362305] sp : ffffffc009523660
[    4.365613] x29: ffffffc009523660 x28: ffffff887f7f5550 x27: ffffff88016fac10
[    4.372748] x26: 0000000000000fc2 x25: ffffff88016de180 x24: 0000000000000060
[    4.379874] x23: 0000000001fca055 x22: ffffff88016de180 x21: ffffff88016de200
[    4.387000] x20: 00000000001f4ed6 x19: 000000005b64cf46 x18: 0000000000000030
[    4.394126] x17: 6962726f66207369 x16: 206863696877202c x15: 746e695f6c6c7076
[    4.401253] x14: 2065687420676e69 x13: 6e6564646962726f x12: ffffffc00936b9b0
[    4.408379] x11: 0000000000000172 x10: 6c6c707620656874 x9 : 00000000fffff7ff
[    4.415506] x8 : ffffffc0093979b0 x7 : 000000000000bfe8 x6 : 80000000fffff800
[    4.422632] x5 : 0000000000000000 x4 : 0000000000000000 x3 : 0000000000000000
[    4.429758] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffffff880009cd80
[    4.436884] Call trace:
[    4.439325]  zynqmp_pll_set_rate+0x198/0x200
[    4.443586]  clk_change_rate+0x148/0x2c0
[    4.447501]  clk_core_set_rate_nolock+0x154/0x240
[    4.452197]  clk_set_rate+0x38/0x150
[    4.455764]  xilinx_dp_codec_probe+0xd4/0x1f0
[    4.460113]  platform_probe+0x68/0xe0
[    4.463767]  really_probe.part.0+0x9c/0x310
[    4.467942]  __driver_probe_device+0x98/0x150
[    4.472291]  driver_probe_device+0x44/0x120
[    4.476466]  __device_attach_driver+0xb4/0x120
[    4.480901]  bus_for_each_drv+0x78/0xd0
[    4.484729]  __device_attach+0xdc/0x190
[    4.488557]  device_initial_probe+0x14/0x20
[    4.492733]  bus_probe_device+0x9c/0xb0
[    4.496560]  device_add+0x36c/0x860
[    4.500041]  of_device_add+0x58/0x70
[    4.503608]  of_platform_device_create_pdata+0xc0/0x100
[    4.508825]  of_platform_bus_create+0x178/0x390
[    4.513348]  of_platform_populate+0x58/0xf0
[    4.517523]  zynqmp_dpsub_probe+0xe8/0x170
[    4.521611]  platform_probe+0x68/0xe0
[    4.525266]  really_probe.part.0+0x9c/0x310
[    4.529441]  __driver_probe_device+0x98/0x150
[    4.533789]  driver_probe_device+0x44/0x120
[    4.537965]  __device_attach_driver+0xb4/0x120
[    4.542400]  bus_for_each_drv+0x78/0xd0
[    4.546228]  __device_attach+0xdc/0x190
[    4.550056]  device_initial_probe+0x14/0x20
[    4.554231]  bus_probe_device+0x9c/0xb0
[    4.558059]  deferred_probe_work_func+0x88/0xc0
[    4.562581]  process_one_work+0x1d4/0x390
[    4.566583]  worker_thread+0x298/0x4e0
[    4.570324]  kthread+0x120/0x130
[    4.573544]  ret_from_fork+0x10/0x20
[    4.577112] ---[ end trace 438bcf53a978d696 ]---
[    4.582450] xilinx-dp-snd-codec fd4a0000.display:zynqmp_dp_snd_codec0: Failed to get required clock freq
[    4.592031] xilinx-dp-snd-codec: probe of fd4a0000.display:zynqmp_dp_snd_codec0 failed with error -22
[    4.601479] xilinx-dp-snd-pcm zynqmp_dp_snd_pcm0: Xilinx DisplayPort Sound PCM probed
[    4.609500] xilinx-dp-snd-pcm zynqmp_dp_snd_pcm1: Xilinx DisplayPort Sound PCM probed
[    4.617583] OF: graph: no port node found in /axi/display@fd4a0000
[    4.624070] xlnx-drm xlnx-drm.0: bound fd4a0000.display (ops 0xffffffc008e4bbb0)
[    5.707520] zynqmp-display fd4a0000.display: [drm] Cannot find any crtc or sizes
[    5.715132] [drm] Initialized xlnx 1.0.0 20130509 for fd4a0000.display on minor 0
[    5.722629] zynqmp-display fd4a0000.display: ZynqMP DisplayPort Subsystem driver probed
[    5.732673] spi-nor spi0.0: mt25qu512a (65536 Kbytes)
[    5.734623] tpm_tis_spi spi2.0: 2.0 TPM (device-id 0x1B, rev-id 22)
[    5.737780] 16 fixed-partitions partitions found on MTD device spi0.0
[    5.746724] tpm tpm0: A TPM error (256) occurred attempting the self test
[    5.750421] Creating 16 MTD partitions on "spi0.0":
[    5.757200] tpm tpm0: starting up the TPM manually
[    5.762072] 0x000000000000-0x000000080000 : "Image Selector"
[    5.773244] 0x000000080000-0x000000100000 : "Image Selector Golden"
[    5.780118] 0x000000100000-0x000000120000 : "Persistent Register"
[    5.786838] 0x000000120000-0x000000140000 : "Persistent Register Backup"
[    5.794236] 0x000000140000-0x000000200000 : "Open_1"
[    5.799813] 0x000000200000-0x000000f00000 : "Image A (FSBL, PMU, ATF, U-Boot)"
[    5.800451] random: fast init done
[    5.807664] 0x000000f00000-0x000000f80000 : "ImgSel Image A Catch"
[    5.817203] 0x000000f80000-0x000001c80000 : "Image B (FSBL, PMU, ATF, U-Boot)"
[    5.825040] 0x000001c80000-0x000001d00000 : "ImgSel Image B Catch"
[    5.831840] 0x000001d00000-0x000001e00000 : "Open_2"
[    5.837409] 0x000001e00000-0x000002000000 : "Recovery Image"
[    5.843698] 0x000002000000-0x000002200000 : "Recovery Image Backup"
[    5.850586] 0x000002200000-0x000002220000 : "U-Boot storage variables"
[    5.857712] 0x000002220000-0x000002240000 : "U-Boot storage variables backup"
[    5.865453] 0x000002240000-0x000002250000 : "SHA256"
[    5.871038] 0x000002250000-0x000004000000 : "User"
[    5.879759] macb ff0e0000.ethernet: Not enabling partial store and forward
[    5.889390] macb ff0e0000.ethernet eth0: Cadence GEM rev 0x50070106 at 0xff0e0000 irq 37 (00:0a:35:0c:f3:8d)
[    5.899572] xilinx-axipmon ffa00000.perf-monitor: Probed Xilinx APM
[    5.906112] xilinx-axipmon fd0b0000.perf-monitor: Probed Xilinx APM
[    5.912565] xilinx-axipmon fd490000.perf-monitor: Probed Xilinx APM
[    5.919021] xilinx-axipmon ffa10000.perf-monitor: Probed Xilinx APM
[    5.949871] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller
[    5.955374] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 1
[    5.963132] xhci-hcd xhci-hcd.1.auto: hcc params 0x0238f625 hci version 0x100 quirks 0x0000000002010810
[    5.972539] xhci-hcd xhci-hcd.1.auto: irq 57, io mem 0xfe200000
[    5.978656] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.15
[    5.986920] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    5.994147] usb usb1: Product: xHCI Host Controller
[    5.999021] usb usb1: Manufacturer: Linux 5.15.19 xhci-hcd
[    6.004506] usb usb1: SerialNumber: xhci-hcd.1.auto
[    6.009633] hub 1-0:1.0: USB hub found
[    6.013399] hub 1-0:1.0: 1 port detected
[    6.017494] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller
[    6.022982] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 2
[    6.030640] xhci-hcd xhci-hcd.1.auto: Host supports USB 3.0 SuperSpeed
[    6.037447] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 5.15
[    6.045716] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    6.052932] usb usb2: Product: xHCI Host Controller
[    6.057809] usb usb2: Manufacturer: Linux 5.15.19 xhci-hcd
[    6.063287] usb usb2: SerialNumber: xhci-hcd.1.auto
[    6.068391] hub 2-0:1.0: USB hub found
[    6.072160] hub 2-0:1.0: 1 port detected
[    6.078057] at24 1-0050: supply vcc not found, using dummy regulator
[    6.084715] at24 1-0050: 8192 byte 24c64 EEPROM, writable, 1 bytes/write
[    6.091545] at24 1-0051: supply vcc not found, using dummy regulator
[    6.098191] at24 1-0051: 8192 byte 24c64 EEPROM, writable, 1 bytes/write
[    6.105077] cdns-i2c ff030000.i2c: 400 kHz mmio ff030000 irq 39
[    6.112305] cdns-wdt fd4d0000.watchdog: Xilinx Watchdog Timer with timeout 60s
[    6.119724] cdns-wdt ff150000.watchdog: Xilinx Watchdog Timer with timeout 10s
[    6.130620] gpio-keys gpio-keys: Button without keycode
[    6.131385] clk: couldn't set sdio1_ref clk rate to 187498123 (-16), current rate: 199999998
[    6.135872] gpio-keys: probe of gpio-keys failed with error -22
[    6.144733] clk: couldn't set sdio1_ref clk rate to 187498123 (-16), current rate: 199999998
[    6.150295] of_cfs_init
[    6.161132] of_cfs_init: OK
[    6.164067] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[    6.191505] mmc1: SDHCI controller on ff170000.mmc [ff170000.mmc] using ADMA 64-bit
[    6.286131] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[    6.294744] ALSA device list:
[    6.297719]   No soundcards found.
[    6.301381] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
[    6.310011] cfg80211: failed to load regulatory.db
[    6.351316] Waiting for root device /dev/mmcblk1p2...
[    6.411538] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
[    6.435886] usb 2-1: New USB device found, idVendor=0424, idProduct=5744, bcdDevice= 2.21
[    6.444061] usb 2-1: New USB device strings: Mfr=2, Product=3, SerialNumber=0
[    6.451194] usb 2-1: Product: USB5744
[    6.454855] usb 2-1: Manufacturer: Microchip Tech
[    6.517289] hub 2-1:1.0: USB hub found
[    6.521191] hub 2-1:1.0: 4 ports detected
[    6.803524] zynqmp-display fd4a0000.display: [drm] Cannot find any crtc or sizes
[    7.455379] mmc1: new high speed SDHC card at address aaaa
[    7.461216] mmcblk1: mmc1:aaaa SC16G 14.8 GiB
[    7.470082]  mmcblk1: p1 p2
[    7.539623] EXT4-fs (mmcblk1p2): recovery complete
[    7.545811] EXT4-fs (mmcblk1p2): mounted filesystem with ordered data mode. Opts: (null). Quota mode: none.
[    7.555576] VFS: Mounted root (ext4 filesystem) on device 179:2.
[    7.564441] devtmpfs: mounted
[    7.567930] Freeing unused kernel memory: 1984K
[    7.572565] Run /sbin/init as init process
[    7.676516] EXT4-fs (mmcblk1p2): re-mounted. Opts: (null). Quota mode: none.
Starting syslogd: OK
Starting klogd: OK
Running sysctl: OK
Initializing random number generator: OK
Saving random seed: [    7.727999] random: dd: uninitialized urandom read (512 bytes read)
OK
Starting network: OK

Welcome to Buildroot
buildroot login: root
#

Best regards,
Neal Frager
AMD
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Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Neal Frager]

Hi Peter, Luca,

> 2. After build, run the following two lines from your u-boot-custom directory.

> fdtoverlay -o fit-dtb.blob -i arch/arm/dts/zynqmp-smk-k26-revA.dtb arch/arm/dts/zynqmp-sck-kv-g-revB.dtbo
> ./tools/mkimage -E -f u-boot.its -B 0x8 u-boot.itb

For the kv260 starter kit, u-boot does not automatically generate the correct dtb to be included in the u-boot.itb.
Above are the two post-build instructions I need to run from the u-boot directory in order to get a correct u-boot.itb file.

Could you point me to the best way to get this into the automated build flow, such that buildroot generates the correct u-boot.itb
without any manual build steps?

Thank you for any ideas and support!

Best regards,
Neal Frager
AMD
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Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Wesley Revens]

Hi Neal,

On 10/05/2022 05:29, Neal Frager wrote:
> Hi Wesley,
>
> Simplifying the steps, here is what you need to do to get this working.

Success! - Following your instructions, my board is now booting into 
Linux from the SD card. My Linux image is not fully booting to a login 
prompt however but I have made some device tree changes so it is likely 
that I have broken something in there so will investigate that. I 
suspect a clean build will sort that.

Thanks for your help with the u-boot side of things.

Kind regards,

Wesley

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Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Neal Frager]

Hi Wesley,

On 10/05/2022 05:29, Neal Frager wrote:
> Hi Wesley,
>
> Simplifying the steps, here is what you need to do to get this working.

> Success! - Following your instructions, my board is now booting into Linux from the SD card. My Linux image is not fully booting to a login prompt however but I have made some device tree changes so it is likely that I have broken something in there so will investigate that. I suspect a clean build will sort that.

> Thanks for your help with the u-boot side of things.

Great news!  Just so you know, I have a patch coming that will remove the manual fit-dtb.blob steps.

With my next patch to buildroot, the whole build process will be automated.

Stay tuned!

Best regards,
Neal Frager
AMD
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Re: [Buildroot] [PATCH v1 1/2] add configs/zynqmp_kria_kv260_defconfig

[Neal Frager]

Hi Peter,

 > Thank you for this idea.  Do you have a solution for the SD card file system as well?

 > The Kria Starter kits use mmc1 instead of mmc0 for the SD card, so  > this is also different in the extllinux.conf files.

> I believe you can use $devnum for that. Have a look at distro_bootcmd.

Just a note about this.  I have not forgotten the plan to clean up the zynqmp directory structure and possibly combine 
zynqmp and kria post-build.sh scripts and extlinux.conf files.  

I was just focused on fixing the functional issues first.

Now that the functional issues are resolved, my next step will be working on cleaning up the directory structure.
However, it may be a few days before I can get to this, as I have some business travel coming up.

Thanks!
Neal Frager
AMD

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