* [PATCH 1/2] pinctrl: sh-pfc: r8a77990: Add SDHI pins, groups and functions
@ 2018-11-05 21:40 Marek Vasut
2018-11-05 21:40 ` [PATCH 2/2] pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHI Marek Vasut
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Marek Vasut @ 2018-11-05 21:40 UTC (permalink / raw)
To: linux-gpio
Cc: Takeshi Kihara, Marek Vasut, Geert Uytterhoeven, Simon Horman,
Wolfram Sang, Yoshihiro Shimoda, linux-renesas-soc
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
This patch adds SDHI{0,1,3} pins, groups and functions to the R8A77990
SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Simon Horman <horms+renesas@verge.net.au>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: linux-renesas-soc@vger.kernel.org
---
drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 218 +++++++++++++++++++++++++-
1 file changed, 216 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 1fdafa48479c..97aba270a515 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -2386,6 +2386,174 @@ static const unsigned int scif_clk_b_mux[] = {
SCIF_CLK_B_MARK,
};
+/* - SDHI0 ------------------------------------------------------------------ */
+static const unsigned int sdhi0_data1_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(3, 2),
+};
+
+static const unsigned int sdhi0_data1_mux[] = {
+ SD0_DAT0_MARK,
+};
+
+static const unsigned int sdhi0_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+};
+
+static const unsigned int sdhi0_data4_mux[] = {
+ SD0_DAT0_MARK, SD0_DAT1_MARK,
+ SD0_DAT2_MARK, SD0_DAT3_MARK,
+};
+
+static const unsigned int sdhi0_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
+};
+
+static const unsigned int sdhi0_ctrl_mux[] = {
+ SD0_CLK_MARK, SD0_CMD_MARK,
+};
+
+static const unsigned int sdhi0_cd_pins[] = {
+ /* CD */
+ RCAR_GP_PIN(3, 12),
+};
+
+static const unsigned int sdhi0_cd_mux[] = {
+ SD0_CD_MARK,
+};
+
+static const unsigned int sdhi0_wp_pins[] = {
+ /* WP */
+ RCAR_GP_PIN(3, 13),
+};
+
+static const unsigned int sdhi0_wp_mux[] = {
+ SD0_WP_MARK,
+};
+
+/* - SDHI1 ------------------------------------------------------------------ */
+static const unsigned int sdhi1_data1_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(3, 8),
+};
+
+static const unsigned int sdhi1_data1_mux[] = {
+ SD1_DAT0_MARK,
+};
+
+static const unsigned int sdhi1_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+
+static const unsigned int sdhi1_data4_mux[] = {
+ SD1_DAT0_MARK, SD1_DAT1_MARK,
+ SD1_DAT2_MARK, SD1_DAT3_MARK,
+};
+
+static const unsigned int sdhi1_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+};
+
+static const unsigned int sdhi1_ctrl_mux[] = {
+ SD1_CLK_MARK, SD1_CMD_MARK,
+};
+
+static const unsigned int sdhi1_cd_pins[] = {
+ /* CD */
+ RCAR_GP_PIN(3, 14),
+};
+
+static const unsigned int sdhi1_cd_mux[] = {
+ SD1_CD_MARK,
+};
+
+static const unsigned int sdhi1_wp_pins[] = {
+ /* WP */
+ RCAR_GP_PIN(3, 15),
+};
+
+static const unsigned int sdhi1_wp_mux[] = {
+ SD1_WP_MARK,
+};
+
+/* - SDHI3 ------------------------------------------------------------------ */
+static const unsigned int sdhi3_data1_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(4, 2),
+};
+
+static const unsigned int sdhi3_data1_mux[] = {
+ SD3_DAT0_MARK,
+};
+
+static const unsigned int sdhi3_data4_pins[] = {
+ /* D[0:3] */
+ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
+ RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
+};
+
+static const unsigned int sdhi3_data4_mux[] = {
+ SD3_DAT0_MARK, SD3_DAT1_MARK,
+ SD3_DAT2_MARK, SD3_DAT3_MARK,
+};
+
+static const unsigned int sdhi3_data8_pins[] = {
+ /* D[0:7] */
+ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
+ RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
+ RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
+ RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
+};
+
+static const unsigned int sdhi3_data8_mux[] = {
+ SD3_DAT0_MARK, SD3_DAT1_MARK,
+ SD3_DAT2_MARK, SD3_DAT3_MARK,
+ SD3_DAT4_MARK, SD3_DAT5_MARK,
+ SD3_DAT6_MARK, SD3_DAT7_MARK,
+};
+
+static const unsigned int sdhi3_ctrl_pins[] = {
+ /* CLK, CMD */
+ RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
+};
+
+static const unsigned int sdhi3_ctrl_mux[] = {
+ SD3_CLK_MARK, SD3_CMD_MARK,
+};
+
+static const unsigned int sdhi3_cd_pins[] = {
+ /* CD */
+ RCAR_GP_PIN(3, 12),
+};
+
+static const unsigned int sdhi3_cd_mux[] = {
+ SD3_CD_MARK,
+};
+
+static const unsigned int sdhi3_wp_pins[] = {
+ /* WP */
+ RCAR_GP_PIN(3, 13),
+};
+
+static const unsigned int sdhi3_wp_mux[] = {
+ SD3_WP_MARK,
+};
+
+static const unsigned int sdhi3_ds_pins[] = {
+ /* DS */
+ RCAR_GP_PIN(4, 10),
+};
+
+static const unsigned int sdhi3_ds_mux[] = {
+ SD3_DS_MARK,
+};
+
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_a_pins[] = {
/* PWEN, OVC */
@@ -2434,7 +2602,7 @@ static const unsigned int usb30_id_mux[] = {
};
static const struct {
- struct sh_pfc_pin_group common[123];
+ struct sh_pfc_pin_group common[140];
struct sh_pfc_pin_group automotive[0];
} pinmux_groups = {
.common = {
@@ -2556,6 +2724,23 @@ static const struct {
SH_PFC_PIN_GROUP(scif5_data_c),
SH_PFC_PIN_GROUP(scif_clk_a),
SH_PFC_PIN_GROUP(scif_clk_b),
+ SH_PFC_PIN_GROUP(sdhi0_data1),
+ SH_PFC_PIN_GROUP(sdhi0_data4),
+ SH_PFC_PIN_GROUP(sdhi0_ctrl),
+ SH_PFC_PIN_GROUP(sdhi0_cd),
+ SH_PFC_PIN_GROUP(sdhi0_wp),
+ SH_PFC_PIN_GROUP(sdhi1_data1),
+ SH_PFC_PIN_GROUP(sdhi1_data4),
+ SH_PFC_PIN_GROUP(sdhi1_ctrl),
+ SH_PFC_PIN_GROUP(sdhi1_cd),
+ SH_PFC_PIN_GROUP(sdhi1_wp),
+ SH_PFC_PIN_GROUP(sdhi3_data1),
+ SH_PFC_PIN_GROUP(sdhi3_data4),
+ SH_PFC_PIN_GROUP(sdhi3_data8),
+ SH_PFC_PIN_GROUP(sdhi3_ctrl),
+ SH_PFC_PIN_GROUP(sdhi3_cd),
+ SH_PFC_PIN_GROUP(sdhi3_wp),
+ SH_PFC_PIN_GROUP(sdhi3_ds),
SH_PFC_PIN_GROUP(usb0_a),
SH_PFC_PIN_GROUP(usb0_b),
SH_PFC_PIN_GROUP(usb0_id),
@@ -2763,6 +2948,32 @@ static const char * const scif_clk_groups[] = {
"scif_clk_b",
};
+static const char * const sdhi0_groups[] = {
+ "sdhi0_data1",
+ "sdhi0_data4",
+ "sdhi0_ctrl",
+ "sdhi0_cd",
+ "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+ "sdhi1_data1",
+ "sdhi1_data4",
+ "sdhi1_ctrl",
+ "sdhi1_cd",
+ "sdhi1_wp",
+};
+
+static const char * const sdhi3_groups[] = {
+ "sdhi3_data1",
+ "sdhi3_data4",
+ "sdhi3_data8",
+ "sdhi3_ctrl",
+ "sdhi3_cd",
+ "sdhi3_wp",
+ "sdhi3_ds",
+};
+
static const char * const usb0_groups[] = {
"usb0_a",
"usb0_b",
@@ -2775,7 +2986,7 @@ static const char * const usb30_groups[] = {
};
static const struct {
- struct sh_pfc_function common[29];
+ struct sh_pfc_function common[32];
struct sh_pfc_function automotive[0];
} pinmux_functions = {
.common = {
@@ -2806,6 +3017,9 @@ static const struct {
SH_PFC_FUNCTION(scif4),
SH_PFC_FUNCTION(scif5),
SH_PFC_FUNCTION(scif_clk),
+ SH_PFC_FUNCTION(sdhi0),
+ SH_PFC_FUNCTION(sdhi1),
+ SH_PFC_FUNCTION(sdhi3),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb30),
}
--
2.18.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 2/2] pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHI
2018-11-05 21:40 [PATCH 1/2] pinctrl: sh-pfc: r8a77990: Add SDHI pins, groups and functions Marek Vasut
@ 2018-11-05 21:40 ` Marek Vasut
2018-11-06 5:24 ` Yoshihiro Shimoda
` (2 more replies)
2018-11-06 5:23 ` [PATCH 1/2] pinctrl: sh-pfc: r8a77990: Add SDHI pins, groups and functions Yoshihiro Shimoda
` (2 subsequent siblings)
3 siblings, 3 replies; 10+ messages in thread
From: Marek Vasut @ 2018-11-05 21:40 UTC (permalink / raw)
To: linux-gpio
Cc: Takeshi Kihara, Marek Vasut, Geert Uytterhoeven, Simon Horman,
Wolfram Sang, Yoshihiro Shimoda, linux-renesas-soc
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
This patch supports the {get,set}_io_voltage operations of SDHI.
This operates the IOCTRL30 register on the R8A77990 SoC and makes
1.8V/3.3V signal voltage switch possible.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Simon Horman <horms+renesas@verge.net.au>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: linux-renesas-soc@vger.kernel.org
---
drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 35 +++++++++++++++++++++++++--
1 file changed, 33 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 97aba270a515..95d478353627 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -23,8 +23,12 @@
PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_16(3, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
+ PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_18(6, fn, sfx, CFG_FLAGS)
/*
@@ -3494,6 +3498,31 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
+enum ioctrl_regs {
+ IOCTRL30,
+};
+
+static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
+ [IOCTRL30] = { 0xe6060380, },
+ { /* sentinel */ },
+};
+
+static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
+ u32 *pocctrl)
+{
+ int bit = -EINVAL;
+
+ *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg;
+
+ if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
+ bit = pin & 0x1f;
+
+ if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10))
+ bit = (pin & 0x1f) + 19;
+
+ return bit;
+}
+
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
[0] = RCAR_GP_PIN(2, 23), /* RD# */
@@ -3744,6 +3773,7 @@ static void r8a77990_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
}
static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = {
+ .pin_to_pocctrl = r8a77990_pin_to_pocctrl,
.get_bias = r8a77990_pinmux_get_bias,
.set_bias = r8a77990_pinmux_set_bias,
};
@@ -3790,6 +3820,7 @@ const struct sh_pfc_soc_info r8a77990_pinmux_info = {
.cfg_regs = pinmux_config_regs,
.bias_regs = pinmux_bias_regs,
+ .ioctrl_regs = pinmux_ioctrl_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
--
2.18.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* RE: [PATCH 2/2] pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHI
2018-11-05 21:40 ` [PATCH 2/2] pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHI Marek Vasut
@ 2018-11-06 5:24 ` Yoshihiro Shimoda
2018-11-06 11:15 ` Wolfram Sang
2018-11-08 13:04 ` Geert Uytterhoeven
2 siblings, 0 replies; 10+ messages in thread
From: Yoshihiro Shimoda @ 2018-11-06 5:24 UTC (permalink / raw)
To: Marek Vasut, linux-gpio
Cc: TAKESHI KIHARA, Marek Vasut, Geert Uytterhoeven, Simon Horman,
Wolfram Sang, linux-renesas-soc
Hello Marek-san,
> From: Marek Vasut, Sent: Tuesday, November 6, 2018 6:40 AM
>
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> This patch supports the {get,set}_io_voltage operations of SDHI.
>
> This operates the IOCTRL30 register on the R8A77990 SoC and makes
> 1.8V/3.3V signal voltage switch possible.
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> Cc: Simon Horman <horms+renesas@verge.net.au>
> Cc: Wolfram Sang <wsa@the-dreams.de>
> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> Cc: linux-renesas-soc@vger.kernel.org
> ---
Thank you for the patch!
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Best regards,
Yoshihiro Shimoda
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 2/2] pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHI
2018-11-05 21:40 ` [PATCH 2/2] pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHI Marek Vasut
2018-11-06 5:24 ` Yoshihiro Shimoda
@ 2018-11-06 11:15 ` Wolfram Sang
2018-11-06 11:33 ` Marek Vasut
2018-11-08 13:04 ` Geert Uytterhoeven
2 siblings, 1 reply; 10+ messages in thread
From: Wolfram Sang @ 2018-11-06 11:15 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-gpio, Takeshi Kihara, Marek Vasut, Geert Uytterhoeven,
Simon Horman, Yoshihiro Shimoda, linux-renesas-soc
[-- Attachment #1: Type: text/plain, Size: 864 bytes --]
On Mon, Nov 05, 2018 at 10:40:12PM +0100, Marek Vasut wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> This patch supports the {get,set}_io_voltage operations of SDHI.
>
> This operates the IOCTRL30 register on the R8A77990 SoC and makes
> 1.8V/3.3V signal voltage switch possible.
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> Cc: Simon Horman <horms+renesas@verge.net.au>
> Cc: Wolfram Sang <wsa@the-dreams.de>
> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> Cc: linux-renesas-soc@vger.kernel.org
Looks good from a high-level point of view. Didn't check the actual
values. I trust Shimoda-san and Geert for that:
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 2/2] pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHI
2018-11-06 11:15 ` Wolfram Sang
@ 2018-11-06 11:33 ` Marek Vasut
0 siblings, 0 replies; 10+ messages in thread
From: Marek Vasut @ 2018-11-06 11:33 UTC (permalink / raw)
To: Wolfram Sang
Cc: linux-gpio, Takeshi Kihara, Marek Vasut, Geert Uytterhoeven,
Simon Horman, Yoshihiro Shimoda, linux-renesas-soc
On 11/06/2018 12:15 PM, Wolfram Sang wrote:
> On Mon, Nov 05, 2018 at 10:40:12PM +0100, Marek Vasut wrote:
>> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>>
>> This patch supports the {get,set}_io_voltage operations of SDHI.
>>
>> This operates the IOCTRL30 register on the R8A77990 SoC and makes
>> 1.8V/3.3V signal voltage switch possible.
>>
>> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
>> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
>> Cc: Simon Horman <horms+renesas@verge.net.au>
>> Cc: Wolfram Sang <wsa@the-dreams.de>
>> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>> Cc: linux-renesas-soc@vger.kernel.org
>
> Looks good from a high-level point of view. Didn't check the actual
> values. I trust Shimoda-san and Geert for that:
>
> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
>
I also checked them in U-Boot :)
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHI
2018-11-05 21:40 ` [PATCH 2/2] pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHI Marek Vasut
2018-11-06 5:24 ` Yoshihiro Shimoda
2018-11-06 11:15 ` Wolfram Sang
@ 2018-11-08 13:04 ` Geert Uytterhoeven
2 siblings, 0 replies; 10+ messages in thread
From: Geert Uytterhoeven @ 2018-11-08 13:04 UTC (permalink / raw)
To: Marek Vasut
Cc: open list:GPIO SUBSYSTEM, Takeshi Kihara, Marek Vasut,
Geert Uytterhoeven, Simon Horman, Wolfram Sang,
Yoshihiro Shimoda, Linux-Renesas
On Mon, Nov 5, 2018 at 10:40 PM Marek Vasut <marek.vasut@gmail.com> wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> This patch supports the {get,set}_io_voltage operations of SDHI.
>
> This operates the IOCTRL30 register on the R8A77990 SoC and makes
> 1.8V/3.3V signal voltage switch possible.
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in sh-pfc-for-v4.21.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [PATCH 1/2] pinctrl: sh-pfc: r8a77990: Add SDHI pins, groups and functions
2018-11-05 21:40 [PATCH 1/2] pinctrl: sh-pfc: r8a77990: Add SDHI pins, groups and functions Marek Vasut
2018-11-05 21:40 ` [PATCH 2/2] pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHI Marek Vasut
@ 2018-11-06 5:23 ` Yoshihiro Shimoda
2018-11-06 11:14 ` Wolfram Sang
2018-11-08 12:58 ` Geert Uytterhoeven
3 siblings, 0 replies; 10+ messages in thread
From: Yoshihiro Shimoda @ 2018-11-06 5:23 UTC (permalink / raw)
To: Marek Vasut, linux-gpio
Cc: TAKESHI KIHARA, Marek Vasut, Geert Uytterhoeven, Simon Horman,
Wolfram Sang, linux-renesas-soc
Hello Marek-san,
> From: Marek Vasut, Sent: Tuesday, November 6, 2018 6:40 AM
>
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> This patch adds SDHI{0,1,3} pins, groups and functions to the R8A77990
> SoC.
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> Cc: Simon Horman <horms+renesas@verge.net.au>
> Cc: Wolfram Sang <wsa@the-dreams.de>
> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> Cc: linux-renesas-soc@vger.kernel.org
> ---
Thank you for the patch!
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Best regards,
Yoshihiro Shimoda
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 1/2] pinctrl: sh-pfc: r8a77990: Add SDHI pins, groups and functions
2018-11-05 21:40 [PATCH 1/2] pinctrl: sh-pfc: r8a77990: Add SDHI pins, groups and functions Marek Vasut
2018-11-05 21:40 ` [PATCH 2/2] pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHI Marek Vasut
2018-11-06 5:23 ` [PATCH 1/2] pinctrl: sh-pfc: r8a77990: Add SDHI pins, groups and functions Yoshihiro Shimoda
@ 2018-11-06 11:14 ` Wolfram Sang
2018-11-06 11:35 ` Marek Vasut
2018-11-08 12:58 ` Geert Uytterhoeven
3 siblings, 1 reply; 10+ messages in thread
From: Wolfram Sang @ 2018-11-06 11:14 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-gpio, Takeshi Kihara, Marek Vasut, Geert Uytterhoeven,
Simon Horman, Yoshihiro Shimoda, linux-renesas-soc
[-- Attachment #1: Type: text/plain, Size: 412 bytes --]
> static const struct {
> - struct sh_pfc_pin_group common[123];
> + struct sh_pfc_pin_group common[140];
> struct sh_pfc_pin_group automotive[0];
> } pinmux_groups = {
...
> static const struct {
> - struct sh_pfc_function common[29];
> + struct sh_pfc_function common[32];
> struct sh_pfc_function automotive[0];
> } pinmux_functions = {
It is Geert's call, but maybe those are a seperate patch?
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^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 1/2] pinctrl: sh-pfc: r8a77990: Add SDHI pins, groups and functions
2018-11-06 11:14 ` Wolfram Sang
@ 2018-11-06 11:35 ` Marek Vasut
0 siblings, 0 replies; 10+ messages in thread
From: Marek Vasut @ 2018-11-06 11:35 UTC (permalink / raw)
To: Wolfram Sang
Cc: linux-gpio, Takeshi Kihara, Marek Vasut, Geert Uytterhoeven,
Simon Horman, Yoshihiro Shimoda, linux-renesas-soc
On 11/06/2018 12:14 PM, Wolfram Sang wrote:
>
>> static const struct {
>> - struct sh_pfc_pin_group common[123];
>> + struct sh_pfc_pin_group common[140];
>> struct sh_pfc_pin_group automotive[0];
>> } pinmux_groups = {
>
> ...
>
>> static const struct {
>> - struct sh_pfc_function common[29];
>> + struct sh_pfc_function common[32];
>> struct sh_pfc_function automotive[0];
>> } pinmux_functions = {
>
>
> It is Geert's call, but maybe those are a seperate patch?
These must be part of this patch, since adding
+ SH_PFC_PIN_GROUP(sdhi0_data1),
entries grows the size of the array. If you were to split this patch,
the PFC driver would break, as the size of the array won't match the
size of the content.
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] pinctrl: sh-pfc: r8a77990: Add SDHI pins, groups and functions
2018-11-05 21:40 [PATCH 1/2] pinctrl: sh-pfc: r8a77990: Add SDHI pins, groups and functions Marek Vasut
` (2 preceding siblings ...)
2018-11-06 11:14 ` Wolfram Sang
@ 2018-11-08 12:58 ` Geert Uytterhoeven
3 siblings, 0 replies; 10+ messages in thread
From: Geert Uytterhoeven @ 2018-11-08 12:58 UTC (permalink / raw)
To: Marek Vasut
Cc: open list:GPIO SUBSYSTEM, Takeshi Kihara, Marek Vasut,
Geert Uytterhoeven, Simon Horman, Wolfram Sang,
Yoshihiro Shimoda, Linux-Renesas
On Mon, Nov 5, 2018 at 10:40 PM Marek Vasut <marek.vasut@gmail.com> wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> This patch adds SDHI{0,1,3} pins, groups and functions to the R8A77990
> SoC.
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in sh-pfc-for-v4.21.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2018-11-08 22:39 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-11-05 21:40 [PATCH 1/2] pinctrl: sh-pfc: r8a77990: Add SDHI pins, groups and functions Marek Vasut
2018-11-05 21:40 ` [PATCH 2/2] pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHI Marek Vasut
2018-11-06 5:24 ` Yoshihiro Shimoda
2018-11-06 11:15 ` Wolfram Sang
2018-11-06 11:33 ` Marek Vasut
2018-11-08 13:04 ` Geert Uytterhoeven
2018-11-06 5:23 ` [PATCH 1/2] pinctrl: sh-pfc: r8a77990: Add SDHI pins, groups and functions Yoshihiro Shimoda
2018-11-06 11:14 ` Wolfram Sang
2018-11-06 11:35 ` Marek Vasut
2018-11-08 12:58 ` Geert Uytterhoeven
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