* [Intel-gfx] [RFC-v3 01/13] drm/i915/pxp: Introduce Intel PXP component
2020-12-09 7:02 [Intel-gfx] [RFC-v3 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
@ 2020-12-09 7:02 ` Huang, Sean Z
2020-12-09 18:05 ` Rodrigo Vivi
` (2 more replies)
2020-12-09 7:02 ` [Intel-gfx] [RFC-v3 02/13] drm/i915/pxp: set KCR reg init during the boot time Huang, Sean Z
` (14 subsequent siblings)
15 siblings, 3 replies; 34+ messages in thread
From: Huang, Sean Z @ 2020-12-09 7:02 UTC (permalink / raw)
To: Intel-gfx
PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
that helps to establish the hardware protected session and manage
the status of the alive software session, as well as its life cycle.
This patch series is to allow the kernel space to create and
manage a single hardware session (a.k.a default session or
arbitrary session). So Mesa can allocate the protected buffer,
which is encrypted with the leverage of the arbitrary hardware
session.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Kconfig | 19 +++++++++++++
drivers/gpu/drm/i915/Makefile | 5 ++++
drivers/gpu/drm/i915/gt/intel_gt.c | 7 +++++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 27 ++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 29 ++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 27 ++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 22 +++++++++++++++
8 files changed, 139 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 1e1cb245fca7..a42b9b031455 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -130,6 +130,25 @@ config DRM_I915_GVT_KVMGT
Choose this option if you want to enable KVMGT support for
Intel GVT-g.
+config DRM_I915_PXP
+ bool "Enable Intel PXP support for Intel Gen12+ platform"
+ depends on DRM_I915
+ select INTEL_MEI_PXP
+ default n
+ help
+ This option selects INTEL_MEI_ME if it isn't already selected to
+ enabled full PXP Services on Intel platforms.
+
+ PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
+ that helps to establish the hardware protected session and manage
+ the status of the alive software session, as well as its life cycle.
+
+ This patch series is to allow the kernel space to create and
+ manage a single hardware session (a.k.a default session or
+ arbitrary session). So Mesa can allocate the protected buffer,
+ which is encrypted with the leverage of the arbitrary hardware
+ session.
+
menu "drm/i915 Debugging"
depends on DRM_I915
depends on EXPERT
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e5574e506a5c..99efac469cc2 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -254,6 +254,11 @@ i915-y += \
i915-y += i915_perf.o
+# Protected execution platform (PXP) support
+i915-$(CONFIG_DRM_I915_PXP) += \
+ pxp/intel_pxp.o \
+ pxp/intel_pxp_context.o
+
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
i915-$(CONFIG_DRM_I915_SELFTEST) += \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 44f1d51e5ae5..d8e20ede7326 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -584,6 +584,12 @@ int intel_gt_init(struct intel_gt *gt)
if (err)
goto err_gt;
+ if (INTEL_GEN(gt->i915) >= 12) {
+ err = intel_pxp_init(>->pxp);
+ if (err)
+ goto err_gt;
+ }
+
goto out_fw;
err_gt:
__intel_gt_disable(gt);
@@ -638,6 +644,7 @@ void intel_gt_driver_release(struct intel_gt *gt)
if (vm) /* FIXME being called twice on error paths :( */
i915_vm_put(vm);
+ intel_pxp_uninit(>->pxp);
intel_gt_pm_fini(gt);
intel_gt_fini_scratch(gt);
intel_gt_fini_buffer_pool(gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 6d39a4a11bf3..05255632c2c0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -23,6 +23,7 @@
#include "intel_rc6_types.h"
#include "intel_rps_types.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp.h"
struct drm_i915_private;
struct i915_ggtt;
@@ -120,6 +121,8 @@ struct intel_gt {
/* Slice/subslice/EU info */
struct sseu_dev_info sseu;
} info;
+
+ struct intel_pxp pxp;
};
enum intel_gt_scratch_field {
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
new file mode 100644
index 000000000000..ba43b2c923c7
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+#include "i915_drv.h"
+#include "intel_pxp.h"
+#include "intel_pxp_context.h"
+
+int intel_pxp_init(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ /* PXP only available for GEN12+ */
+ if (INTEL_GEN(gt->i915) < 12)
+ return -ENODEV;
+
+ intel_pxp_ctx_init(&pxp->ctx);
+
+ drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
+
+ return 0;
+}
+
+void intel_pxp_uninit(struct intel_pxp *pxp)
+{
+ intel_pxp_ctx_fini(&pxp->ctx);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
new file mode 100644
index 000000000000..7c3d49a6a3ab
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_H__
+#define __INTEL_PXP_H__
+
+#include "intel_pxp_context.h"
+
+struct intel_pxp {
+ struct pxp_context ctx;
+};
+
+#ifdef CONFIG_DRM_I915_PXP
+int intel_pxp_init(struct intel_pxp *pxp);
+void intel_pxp_uninit(struct intel_pxp *pxp);
+#else
+static inline int intel_pxp_init(struct intel_pxp *pxp)
+{
+ return 0;
+}
+
+static inline void intel_pxp_uninit(struct intel_pxp *pxp)
+{
+}
+#endif
+
+#endif /* __INTEL_PXP_PM_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
new file mode 100644
index 000000000000..5ffaf55dc7df
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "intel_pxp_context.h"
+#include <linux/random.h>
+
+/**
+ * intel_pxp_ctx_init - To init a pxp context.
+ * @ctx: pointer to ctx structure.
+ */
+void intel_pxp_ctx_init(struct pxp_context *ctx)
+{
+ get_random_bytes(&ctx->id, sizeof(ctx->id));
+
+ mutex_init(&ctx->mutex);
+}
+
+/**
+ * intel_pxp_ctx_fini - To finish the pxp context.
+ * @ctx: pointer to ctx structure.
+ */
+void intel_pxp_ctx_fini(struct pxp_context *ctx)
+{
+ ctx->id = 0;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
new file mode 100644
index 000000000000..953a2e700931
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_CONTEXT_H__
+#define __INTEL_PXP_CONTEXT_H__
+
+#include <linux/mutex.h>
+
+/* struct pxp_context - Represents combined view of driver and logical HW states. */
+struct pxp_context {
+ /** @mutex: mutex to protect the pxp context */
+ struct mutex mutex;
+
+ int id;
+};
+
+void intel_pxp_ctx_init(struct pxp_context *ctx);
+void intel_pxp_ctx_fini(struct pxp_context *ctx);
+
+#endif /* __INTEL_PXP_CONTEXT_H__ */
--
2.17.1
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [Intel-gfx] [RFC-v3 01/13] drm/i915/pxp: Introduce Intel PXP component
2020-12-09 7:02 ` [Intel-gfx] [RFC-v3 01/13] drm/i915/pxp: Introduce Intel PXP component Huang, Sean Z
@ 2020-12-09 18:05 ` Rodrigo Vivi
2020-12-09 18:42 ` Huang, Sean Z
2020-12-10 9:36 ` Joonas Lahtinen
2020-12-10 16:53 ` Jani Nikula
2 siblings, 1 reply; 34+ messages in thread
From: Rodrigo Vivi @ 2020-12-09 18:05 UTC (permalink / raw)
To: Huang, Sean Z; +Cc: Intel-gfx
On Tue, Dec 08, 2020 at 11:02:55PM -0800, Huang, Sean Z wrote:
> PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
> that helps to establish the hardware protected session and manage
> the status of the alive software session, as well as its life cycle.
>
> This patch series is to allow the kernel space to create and
> manage a single hardware session (a.k.a default session or
> arbitrary session). So Mesa can allocate the protected buffer,
> which is encrypted with the leverage of the arbitrary hardware
> session.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/Kconfig | 19 +++++++++++++
> drivers/gpu/drm/i915/Makefile | 5 ++++
> drivers/gpu/drm/i915/gt/intel_gt.c | 7 +++++
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 27 ++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 29 ++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 27 ++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 22 +++++++++++++++
> 8 files changed, 139 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
>
> diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
> index 1e1cb245fca7..a42b9b031455 100644
> --- a/drivers/gpu/drm/i915/Kconfig
> +++ b/drivers/gpu/drm/i915/Kconfig
> @@ -130,6 +130,25 @@ config DRM_I915_GVT_KVMGT
> Choose this option if you want to enable KVMGT support for
> Intel GVT-g.
>
> +config DRM_I915_PXP
> + bool "Enable Intel PXP support for Intel Gen12+ platform"
> + depends on DRM_I915
> + select INTEL_MEI_PXP
> + default n
> + help
> + This option selects INTEL_MEI_ME if it isn't already selected to
> + enabled full PXP Services on Intel platforms.
> +
> + PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
> + that helps to establish the hardware protected session and manage
> + the status of the alive software session, as well as its life cycle.
> +
> + This patch series is to allow the kernel space to create and
> + manage a single hardware session (a.k.a default session or
> + arbitrary session). So Mesa can allocate the protected buffer,
> + which is encrypted with the leverage of the arbitrary hardware
> + session.
> +
> menu "drm/i915 Debugging"
> depends on DRM_I915
> depends on EXPERT
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index e5574e506a5c..99efac469cc2 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -254,6 +254,11 @@ i915-y += \
>
> i915-y += i915_perf.o
>
> +# Protected execution platform (PXP) support
> +i915-$(CONFIG_DRM_I915_PXP) += \
> + pxp/intel_pxp.o \
> + pxp/intel_pxp_context.o
> +
> # Post-mortem debug and GPU hang state capture
> i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
> i915-$(CONFIG_DRM_I915_SELFTEST) += \
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 44f1d51e5ae5..d8e20ede7326 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -584,6 +584,12 @@ int intel_gt_init(struct intel_gt *gt)
> if (err)
> goto err_gt;
>
> + if (INTEL_GEN(gt->i915) >= 12) {
> + err = intel_pxp_init(>->pxp);
> + if (err)
> + goto err_gt;
> + }
> +
> goto out_fw;
> err_gt:
> __intel_gt_disable(gt);
> @@ -638,6 +644,7 @@ void intel_gt_driver_release(struct intel_gt *gt)
> if (vm) /* FIXME being called twice on error paths :( */
> i915_vm_put(vm);
>
> + intel_pxp_uninit(>->pxp);
> intel_gt_pm_fini(gt);
> intel_gt_fini_scratch(gt);
> intel_gt_fini_buffer_pool(gt);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index 6d39a4a11bf3..05255632c2c0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -23,6 +23,7 @@
> #include "intel_rc6_types.h"
> #include "intel_rps_types.h"
> #include "intel_wakeref.h"
> +#include "pxp/intel_pxp.h"
>
> struct drm_i915_private;
> struct i915_ggtt;
> @@ -120,6 +121,8 @@ struct intel_gt {
> /* Slice/subslice/EU info */
> struct sseu_dev_info sseu;
> } info;
> +
> + struct intel_pxp pxp;
> };
>
> enum intel_gt_scratch_field {
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> new file mode 100644
> index 000000000000..ba43b2c923c7
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +#include "i915_drv.h"
> +#include "intel_pxp.h"
> +#include "intel_pxp_context.h"
> +
> +int intel_pxp_init(struct intel_pxp *pxp)
> +{
> + struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
> +
> + /* PXP only available for GEN12+ */
> + if (INTEL_GEN(gt->i915) < 12)
> + return -ENODEV;
> +
> + intel_pxp_ctx_init(&pxp->ctx);
> +
> + drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
> +
> + return 0;
> +}
> +
> +void intel_pxp_uninit(struct intel_pxp *pxp)
> +{
> + intel_pxp_ctx_fini(&pxp->ctx);
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> new file mode 100644
> index 000000000000..7c3d49a6a3ab
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -0,0 +1,29 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_H__
> +#define __INTEL_PXP_H__
> +
> +#include "intel_pxp_context.h"
> +
> +struct intel_pxp {
> + struct pxp_context ctx;
> +};
> +
> +#ifdef CONFIG_DRM_I915_PXP
> +int intel_pxp_init(struct intel_pxp *pxp);
> +void intel_pxp_uninit(struct intel_pxp *pxp);
> +#else
> +static inline int intel_pxp_init(struct intel_pxp *pxp)
> +{
> + return 0;
> +}
> +
> +static inline void intel_pxp_uninit(struct intel_pxp *pxp)
> +{
> +}
> +#endif
> +
> +#endif /* __INTEL_PXP_PM_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> new file mode 100644
> index 000000000000..5ffaf55dc7df
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#include "intel_pxp_context.h"
> +#include <linux/random.h>
> +
> +/**
> + * intel_pxp_ctx_init - To init a pxp context.
> + * @ctx: pointer to ctx structure.
> + */
> +void intel_pxp_ctx_init(struct pxp_context *ctx)
> +{
> + get_random_bytes(&ctx->id, sizeof(ctx->id));
why do you need random bytes?
why couldn't the default session be simply "1".
> +
> + mutex_init(&ctx->mutex);
> +}
> +
> +/**
> + * intel_pxp_ctx_fini - To finish the pxp context.
> + * @ctx: pointer to ctx structure.
> + */
> +void intel_pxp_ctx_fini(struct pxp_context *ctx)
> +{
> + ctx->id = 0;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> new file mode 100644
> index 000000000000..953a2e700931
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_CONTEXT_H__
> +#define __INTEL_PXP_CONTEXT_H__
> +
> +#include <linux/mutex.h>
> +
> +/* struct pxp_context - Represents combined view of driver and logical HW states. */
> +struct pxp_context {
> + /** @mutex: mutex to protect the pxp context */
> + struct mutex mutex;
> +
> + int id;
> +};
> +
> +void intel_pxp_ctx_init(struct pxp_context *ctx);
> +void intel_pxp_ctx_fini(struct pxp_context *ctx);
> +
> +#endif /* __INTEL_PXP_CONTEXT_H__ */
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [Intel-gfx] [RFC-v3 01/13] drm/i915/pxp: Introduce Intel PXP component
2020-12-09 18:05 ` Rodrigo Vivi
@ 2020-12-09 18:42 ` Huang, Sean Z
0 siblings, 0 replies; 34+ messages in thread
From: Huang, Sean Z @ 2020-12-09 18:42 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: Intel-gfx
Hi Rodrigo,
> why do you need random bytes?
> why couldn't the default session be simply "1".
By the architecture design. It would like to keep some flexibility in the future, so maybe we could have multiple ctx later.
Best regards,
Sean
-----Original Message-----
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Sent: Wednesday, December 9, 2020 10:06 AM
To: Huang, Sean Z <sean.z.huang@intel.com>
Cc: Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFC-v3 01/13] drm/i915/pxp: Introduce Intel PXP component
On Tue, Dec 08, 2020 at 11:02:55PM -0800, Huang, Sean Z wrote:
> PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
> that helps to establish the hardware protected session and manage the
> status of the alive software session, as well as its life cycle.
>
> This patch series is to allow the kernel space to create and manage a
> single hardware session (a.k.a default session or arbitrary session).
> So Mesa can allocate the protected buffer, which is encrypted with the
> leverage of the arbitrary hardware session.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/Kconfig | 19 +++++++++++++
> drivers/gpu/drm/i915/Makefile | 5 ++++
> drivers/gpu/drm/i915/gt/intel_gt.c | 7 +++++
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 27 ++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 29 ++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 27 ++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 22 +++++++++++++++
> 8 files changed, 139 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
>
> diff --git a/drivers/gpu/drm/i915/Kconfig
> b/drivers/gpu/drm/i915/Kconfig index 1e1cb245fca7..a42b9b031455 100644
> --- a/drivers/gpu/drm/i915/Kconfig
> +++ b/drivers/gpu/drm/i915/Kconfig
> @@ -130,6 +130,25 @@ config DRM_I915_GVT_KVMGT
> Choose this option if you want to enable KVMGT support for
> Intel GVT-g.
>
> +config DRM_I915_PXP
> + bool "Enable Intel PXP support for Intel Gen12+ platform"
> + depends on DRM_I915
> + select INTEL_MEI_PXP
> + default n
> + help
> + This option selects INTEL_MEI_ME if it isn't already selected to
> + enabled full PXP Services on Intel platforms.
> +
> + PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
> + that helps to establish the hardware protected session and manage
> + the status of the alive software session, as well as its life cycle.
> +
> + This patch series is to allow the kernel space to create and
> + manage a single hardware session (a.k.a default session or
> + arbitrary session). So Mesa can allocate the protected buffer,
> + which is encrypted with the leverage of the arbitrary hardware
> + session.
> +
> menu "drm/i915 Debugging"
> depends on DRM_I915
> depends on EXPERT
> diff --git a/drivers/gpu/drm/i915/Makefile
> b/drivers/gpu/drm/i915/Makefile index e5574e506a5c..99efac469cc2
> 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -254,6 +254,11 @@ i915-y += \
>
> i915-y += i915_perf.o
>
> +# Protected execution platform (PXP) support
> +i915-$(CONFIG_DRM_I915_PXP) += \
> + pxp/intel_pxp.o \
> + pxp/intel_pxp_context.o
> +
> # Post-mortem debug and GPU hang state capture
> i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
> i915-$(CONFIG_DRM_I915_SELFTEST) += \ diff --git
> a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 44f1d51e5ae5..d8e20ede7326 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -584,6 +584,12 @@ int intel_gt_init(struct intel_gt *gt)
> if (err)
> goto err_gt;
>
> + if (INTEL_GEN(gt->i915) >= 12) {
> + err = intel_pxp_init(>->pxp);
> + if (err)
> + goto err_gt;
> + }
> +
> goto out_fw;
> err_gt:
> __intel_gt_disable(gt);
> @@ -638,6 +644,7 @@ void intel_gt_driver_release(struct intel_gt *gt)
> if (vm) /* FIXME being called twice on error paths :( */
> i915_vm_put(vm);
>
> + intel_pxp_uninit(>->pxp);
> intel_gt_pm_fini(gt);
> intel_gt_fini_scratch(gt);
> intel_gt_fini_buffer_pool(gt);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index 6d39a4a11bf3..05255632c2c0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -23,6 +23,7 @@
> #include "intel_rc6_types.h"
> #include "intel_rps_types.h"
> #include "intel_wakeref.h"
> +#include "pxp/intel_pxp.h"
>
> struct drm_i915_private;
> struct i915_ggtt;
> @@ -120,6 +121,8 @@ struct intel_gt {
> /* Slice/subslice/EU info */
> struct sseu_dev_info sseu;
> } info;
> +
> + struct intel_pxp pxp;
> };
>
> enum intel_gt_scratch_field {
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> new file mode 100644
> index 000000000000..ba43b2c923c7
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +#include "i915_drv.h"
> +#include "intel_pxp.h"
> +#include "intel_pxp_context.h"
> +
> +int intel_pxp_init(struct intel_pxp *pxp) {
> + struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
> +
> + /* PXP only available for GEN12+ */
> + if (INTEL_GEN(gt->i915) < 12)
> + return -ENODEV;
> +
> + intel_pxp_ctx_init(&pxp->ctx);
> +
> + drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content
> +support initialized\n");
> +
> + return 0;
> +}
> +
> +void intel_pxp_uninit(struct intel_pxp *pxp) {
> + intel_pxp_ctx_fini(&pxp->ctx);
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> new file mode 100644
> index 000000000000..7c3d49a6a3ab
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -0,0 +1,29 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_H__
> +#define __INTEL_PXP_H__
> +
> +#include "intel_pxp_context.h"
> +
> +struct intel_pxp {
> + struct pxp_context ctx;
> +};
> +
> +#ifdef CONFIG_DRM_I915_PXP
> +int intel_pxp_init(struct intel_pxp *pxp); void
> +intel_pxp_uninit(struct intel_pxp *pxp); #else static inline int
> +intel_pxp_init(struct intel_pxp *pxp) {
> + return 0;
> +}
> +
> +static inline void intel_pxp_uninit(struct intel_pxp *pxp) { } #endif
> +
> +#endif /* __INTEL_PXP_PM_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> new file mode 100644
> index 000000000000..5ffaf55dc7df
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#include "intel_pxp_context.h"
> +#include <linux/random.h>
> +
> +/**
> + * intel_pxp_ctx_init - To init a pxp context.
> + * @ctx: pointer to ctx structure.
> + */
> +void intel_pxp_ctx_init(struct pxp_context *ctx) {
> + get_random_bytes(&ctx->id, sizeof(ctx->id));
why do you need random bytes?
why couldn't the default session be simply "1".
> +
> + mutex_init(&ctx->mutex);
> +}
> +
> +/**
> + * intel_pxp_ctx_fini - To finish the pxp context.
> + * @ctx: pointer to ctx structure.
> + */
> +void intel_pxp_ctx_fini(struct pxp_context *ctx) {
> + ctx->id = 0;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> new file mode 100644
> index 000000000000..953a2e700931
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_CONTEXT_H__
> +#define __INTEL_PXP_CONTEXT_H__
> +
> +#include <linux/mutex.h>
> +
> +/* struct pxp_context - Represents combined view of driver and
> +logical HW states. */ struct pxp_context {
> + /** @mutex: mutex to protect the pxp context */
> + struct mutex mutex;
> +
> + int id;
> +};
> +
> +void intel_pxp_ctx_init(struct pxp_context *ctx); void
> +intel_pxp_ctx_fini(struct pxp_context *ctx);
> +
> +#endif /* __INTEL_PXP_CONTEXT_H__ */
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Intel-gfx] [RFC-v3 01/13] drm/i915/pxp: Introduce Intel PXP component
2020-12-09 7:02 ` [Intel-gfx] [RFC-v3 01/13] drm/i915/pxp: Introduce Intel PXP component Huang, Sean Z
2020-12-09 18:05 ` Rodrigo Vivi
@ 2020-12-10 9:36 ` Joonas Lahtinen
2020-12-10 16:53 ` Jani Nikula
2 siblings, 0 replies; 34+ messages in thread
From: Joonas Lahtinen @ 2020-12-10 9:36 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
Quoting Huang, Sean Z (2020-12-09 09:02:55)
> PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
> that helps to establish the hardware protected session and manage
> the status of the alive software session, as well as its life cycle.
>
> This patch series is to allow the kernel space to create and
> manage a single hardware session (a.k.a default session or
> arbitrary session). So Mesa can allocate the protected buffer,
> which is encrypted with the leverage of the arbitrary hardware
> session.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
<SNIP>
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -254,6 +254,11 @@ i915-y += \
>
> i915-y += i915_perf.o
>
> +# Protected execution platform (PXP) support
> +i915-$(CONFIG_DRM_I915_PXP) += \
> + pxp/intel_pxp.o \
> + pxp/intel_pxp_context.o
> +
> # Post-mortem debug and GPU hang state capture
> i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
> i915-$(CONFIG_DRM_I915_SELFTEST) += \
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 44f1d51e5ae5..d8e20ede7326 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -584,6 +584,12 @@ int intel_gt_init(struct intel_gt *gt)
> if (err)
> goto err_gt;
>
> + if (INTEL_GEN(gt->i915) >= 12) {
This check should be moved into intel_pxp_init() to avoid cluttering the
top level init flow.
Inside init, we should record the pxp initialization status and fail
the attempted use of PXP from uAPI or from MEI driver with -ENODEV.
> + err = intel_pxp_init(>->pxp);
> + if (err)
> + goto err_gt;
> + }
> +
> goto out_fw;
> err_gt:
> __intel_gt_disable(gt);
> @@ -638,6 +644,7 @@ void intel_gt_driver_release(struct intel_gt *gt)
> if (vm) /* FIXME being called twice on error paths :( */
> i915_vm_put(vm);
>
> + intel_pxp_uninit(>->pxp);
intel_pxp_fini()
> intel_gt_pm_fini(gt);
> intel_gt_fini_scratch(gt);
> intel_gt_fini_buffer_pool(gt);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index 6d39a4a11bf3..05255632c2c0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -23,6 +23,7 @@
> #include "intel_rc6_types.h"
> #include "intel_rps_types.h"
> #include "intel_wakeref.h"
> +#include "pxp/intel_pxp.h"
This should include just intel_pxp_types.h.
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +#include "i915_drv.h"
> +#include "intel_pxp.h"
> +#include "intel_pxp_context.h"
> +
> +int intel_pxp_init(struct intel_pxp *pxp)
> +{
> + struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
> +
> + /* PXP only available for GEN12+ */
Comment is spurious, just describes what the next line of code reads, so can
be dropped.
> + if (INTEL_GEN(gt->i915) < 12)
We probably better introduce HAS_PXP() macro (I think it was previously
suggested, too).
> + return -ENODEV;
This is top-level initialization function, we should record the
initialization status somewhere at the end of successful init sequence.
Then in whatever entrypoints we have to the code from userspace we want
to differentiate between failure to initialize and not supported by HW.
Based on what I'm reading here, this could be made into void function as
I don't see anything that would potentially fail.
So above would look like
if (!HAS_PXP(i915))
return;
As the top level intel_gt init sequence is not impacted by the lack of
PXP or even the init failure.
> + intel_pxp_ctx_init(&pxp->ctx);
I think we could use the pxp->ctx.id being nonzero as a check for successful
initialization in the entrypoints to code.
> + drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
> +
> + return 0;
> +}
> +
> +void intel_pxp_uninit(struct intel_pxp *pxp)
intel_pxp_fini()
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -0,0 +1,29 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_H__
> +#define __INTEL_PXP_H__
> +
> +#include "intel_pxp_context.h"
This should only include intel_pxp_context_types.h file.
> +
> +struct intel_pxp {
> + struct pxp_context ctx;
> +};
These should too go into separate intel_pxp_types.h file.
> +#ifdef CONFIG_DRM_I915_PXP
> +int intel_pxp_init(struct intel_pxp *pxp);
> +void intel_pxp_uninit(struct intel_pxp *pxp);
intel_pxp_fini()
> +#else
> +static inline int intel_pxp_init(struct intel_pxp *pxp)
This could become void.
> +{
> + return 0;
> +}
> +
> +static inline void intel_pxp_uninit(struct intel_pxp *pxp)
intel_pxp_fini()
> index 000000000000..5ffaf55dc7df
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#include "intel_pxp_context.h"
> +#include <linux/random.h>
> +
> +/**
> + * intel_pxp_ctx_init - To init a pxp context.
> + * @ctx: pointer to ctx structure.
> + */
> +void intel_pxp_ctx_init(struct pxp_context *ctx)
> +{
> + get_random_bytes(&ctx->id, sizeof(ctx->id));
Agreeing with Rodrigo. We should be fine just using the arbitary
session id here, too.
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_CONTEXT_H__
> +#define __INTEL_PXP_CONTEXT_H__
> +
> +#include <linux/mutex.h>
> +
> +/* struct pxp_context - Represents combined view of driver and logical HW states. */
> +struct pxp_context {
> + /** @mutex: mutex to protect the pxp context */
> + struct mutex mutex;
> +
> + int id;
> +};
Again, a split into _types.h file as described above.
Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [Intel-gfx] [RFC-v3 01/13] drm/i915/pxp: Introduce Intel PXP component
2020-12-09 7:02 ` [Intel-gfx] [RFC-v3 01/13] drm/i915/pxp: Introduce Intel PXP component Huang, Sean Z
2020-12-09 18:05 ` Rodrigo Vivi
2020-12-10 9:36 ` Joonas Lahtinen
@ 2020-12-10 16:53 ` Jani Nikula
2 siblings, 0 replies; 34+ messages in thread
From: Jani Nikula @ 2020-12-10 16:53 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
On Tue, 08 Dec 2020, "Huang, Sean Z" <sean.z.huang@intel.com> wrote:
> PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
> that helps to establish the hardware protected session and manage
> the status of the alive software session, as well as its life cycle.
>
> This patch series is to allow the kernel space to create and
> manage a single hardware session (a.k.a default session or
> arbitrary session). So Mesa can allocate the protected buffer,
> which is encrypted with the leverage of the arbitrary hardware
> session.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/Kconfig | 19 +++++++++++++
> drivers/gpu/drm/i915/Makefile | 5 ++++
> drivers/gpu/drm/i915/gt/intel_gt.c | 7 +++++
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 27 ++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 29 ++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 27 ++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 22 +++++++++++++++
> 8 files changed, 139 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
>
> diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
> index 1e1cb245fca7..a42b9b031455 100644
> --- a/drivers/gpu/drm/i915/Kconfig
> +++ b/drivers/gpu/drm/i915/Kconfig
> @@ -130,6 +130,25 @@ config DRM_I915_GVT_KVMGT
> Choose this option if you want to enable KVMGT support for
> Intel GVT-g.
>
> +config DRM_I915_PXP
> + bool "Enable Intel PXP support for Intel Gen12+ platform"
> + depends on DRM_I915
> + select INTEL_MEI_PXP
INTEL_MEI_PXP does not exist at this point. It gets added much later.
I think the select/depends usage looks suspicious, and prone to create
configuration problems.
See Documentation/kbuild/kconfig-language.rst:
Note:
select should be used with care. select will force
a symbol to a value without visiting the dependencies.
By abusing select you are able to select a symbol FOO even
if FOO depends on BAR that is not set.
In general use select only for non-visible symbols
(no prompts anywhere) and for symbols with no dependencies.
That will limit the usefulness but on the other hand avoid
the illegal configurations all over.
BR,
Jani.
> + default n
> + help
> + This option selects INTEL_MEI_ME if it isn't already selected to
> + enabled full PXP Services on Intel platforms.
> +
> + PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
> + that helps to establish the hardware protected session and manage
> + the status of the alive software session, as well as its life cycle.
> +
> + This patch series is to allow the kernel space to create and
> + manage a single hardware session (a.k.a default session or
> + arbitrary session). So Mesa can allocate the protected buffer,
> + which is encrypted with the leverage of the arbitrary hardware
> + session.
> +
> menu "drm/i915 Debugging"
> depends on DRM_I915
> depends on EXPERT
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index e5574e506a5c..99efac469cc2 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -254,6 +254,11 @@ i915-y += \
>
> i915-y += i915_perf.o
>
> +# Protected execution platform (PXP) support
> +i915-$(CONFIG_DRM_I915_PXP) += \
> + pxp/intel_pxp.o \
> + pxp/intel_pxp_context.o
> +
> # Post-mortem debug and GPU hang state capture
> i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
> i915-$(CONFIG_DRM_I915_SELFTEST) += \
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 44f1d51e5ae5..d8e20ede7326 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -584,6 +584,12 @@ int intel_gt_init(struct intel_gt *gt)
> if (err)
> goto err_gt;
>
> + if (INTEL_GEN(gt->i915) >= 12) {
> + err = intel_pxp_init(>->pxp);
> + if (err)
> + goto err_gt;
> + }
> +
> goto out_fw;
> err_gt:
> __intel_gt_disable(gt);
> @@ -638,6 +644,7 @@ void intel_gt_driver_release(struct intel_gt *gt)
> if (vm) /* FIXME being called twice on error paths :( */
> i915_vm_put(vm);
>
> + intel_pxp_uninit(>->pxp);
> intel_gt_pm_fini(gt);
> intel_gt_fini_scratch(gt);
> intel_gt_fini_buffer_pool(gt);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index 6d39a4a11bf3..05255632c2c0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -23,6 +23,7 @@
> #include "intel_rc6_types.h"
> #include "intel_rps_types.h"
> #include "intel_wakeref.h"
> +#include "pxp/intel_pxp.h"
>
> struct drm_i915_private;
> struct i915_ggtt;
> @@ -120,6 +121,8 @@ struct intel_gt {
> /* Slice/subslice/EU info */
> struct sseu_dev_info sseu;
> } info;
> +
> + struct intel_pxp pxp;
> };
>
> enum intel_gt_scratch_field {
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> new file mode 100644
> index 000000000000..ba43b2c923c7
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +#include "i915_drv.h"
> +#include "intel_pxp.h"
> +#include "intel_pxp_context.h"
> +
> +int intel_pxp_init(struct intel_pxp *pxp)
> +{
> + struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
> +
> + /* PXP only available for GEN12+ */
> + if (INTEL_GEN(gt->i915) < 12)
> + return -ENODEV;
> +
> + intel_pxp_ctx_init(&pxp->ctx);
> +
> + drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
> +
> + return 0;
> +}
> +
> +void intel_pxp_uninit(struct intel_pxp *pxp)
> +{
> + intel_pxp_ctx_fini(&pxp->ctx);
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> new file mode 100644
> index 000000000000..7c3d49a6a3ab
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -0,0 +1,29 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_H__
> +#define __INTEL_PXP_H__
> +
> +#include "intel_pxp_context.h"
> +
> +struct intel_pxp {
> + struct pxp_context ctx;
> +};
> +
> +#ifdef CONFIG_DRM_I915_PXP
> +int intel_pxp_init(struct intel_pxp *pxp);
> +void intel_pxp_uninit(struct intel_pxp *pxp);
> +#else
> +static inline int intel_pxp_init(struct intel_pxp *pxp)
> +{
> + return 0;
> +}
> +
> +static inline void intel_pxp_uninit(struct intel_pxp *pxp)
> +{
> +}
> +#endif
> +
> +#endif /* __INTEL_PXP_PM_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> new file mode 100644
> index 000000000000..5ffaf55dc7df
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#include "intel_pxp_context.h"
> +#include <linux/random.h>
> +
> +/**
> + * intel_pxp_ctx_init - To init a pxp context.
> + * @ctx: pointer to ctx structure.
> + */
> +void intel_pxp_ctx_init(struct pxp_context *ctx)
> +{
> + get_random_bytes(&ctx->id, sizeof(ctx->id));
> +
> + mutex_init(&ctx->mutex);
> +}
> +
> +/**
> + * intel_pxp_ctx_fini - To finish the pxp context.
> + * @ctx: pointer to ctx structure.
> + */
> +void intel_pxp_ctx_fini(struct pxp_context *ctx)
> +{
> + ctx->id = 0;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> new file mode 100644
> index 000000000000..953a2e700931
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_CONTEXT_H__
> +#define __INTEL_PXP_CONTEXT_H__
> +
> +#include <linux/mutex.h>
> +
> +/* struct pxp_context - Represents combined view of driver and logical HW states. */
> +struct pxp_context {
> + /** @mutex: mutex to protect the pxp context */
> + struct mutex mutex;
> +
> + int id;
> +};
> +
> +void intel_pxp_ctx_init(struct pxp_context *ctx);
> +void intel_pxp_ctx_fini(struct pxp_context *ctx);
> +
> +#endif /* __INTEL_PXP_CONTEXT_H__ */
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* [Intel-gfx] [RFC-v3 02/13] drm/i915/pxp: set KCR reg init during the boot time
2020-12-09 7:02 [Intel-gfx] [RFC-v3 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
2020-12-09 7:02 ` [Intel-gfx] [RFC-v3 01/13] drm/i915/pxp: Introduce Intel PXP component Huang, Sean Z
@ 2020-12-09 7:02 ` Huang, Sean Z
2020-12-09 18:07 ` Rodrigo Vivi
2020-12-10 16:55 ` Jani Nikula
2020-12-09 7:02 ` [Intel-gfx] [RFC-v3 03/13] drm/i915/pxp: Implement funcs to create the TEE channel Huang, Sean Z
` (13 subsequent siblings)
15 siblings, 2 replies; 34+ messages in thread
From: Huang, Sean Z @ 2020-12-09 7:02 UTC (permalink / raw)
To: Intel-gfx
Set the KCR init during the boot time, which is
required by hardware, to allow us doing further
protection operation such as sending commands to
GPU or TEE.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 8 ++++++++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 6 ++++++
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index ba43b2c923c7..c4815950567d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,12 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
+/* KCR register definitions */
+#define KCR_INIT _MMIO(0x320f0)
+#define KCR_INIT_MASK_SHIFT (16)
+/* Setting KCR Init bit is required after system boot */
+#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << KCR_INIT_MASK_SHIFT))
+
int intel_pxp_init(struct intel_pxp *pxp)
{
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
@@ -16,6 +22,8 @@ int intel_pxp_init(struct intel_pxp *pxp)
intel_pxp_ctx_init(&pxp->ctx);
+ intel_uncore_write(gt->uncore, KCR_INIT, KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
+
drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
return 0;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 7c3d49a6a3ab..b906bf7dea90 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -15,6 +15,7 @@ struct intel_pxp {
#ifdef CONFIG_DRM_I915_PXP
int intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_uninit(struct intel_pxp *pxp);
+int intel_pxp_reg_read(struct intel_pxp *pxp, u32 offset, u32 *regval);
#else
static inline int intel_pxp_init(struct intel_pxp *pxp)
{
@@ -24,6 +25,11 @@ static inline int intel_pxp_init(struct intel_pxp *pxp)
static inline void intel_pxp_uninit(struct intel_pxp *pxp)
{
}
+
+static inline int intel_pxp_reg_read(struct intel_pxp *pxp, u32 offset, u32 *regval)
+{
+ return 0;
+}
#endif
#endif /* __INTEL_PXP_PM_H__ */
--
2.17.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [Intel-gfx] [RFC-v3 02/13] drm/i915/pxp: set KCR reg init during the boot time
2020-12-09 7:02 ` [Intel-gfx] [RFC-v3 02/13] drm/i915/pxp: set KCR reg init during the boot time Huang, Sean Z
@ 2020-12-09 18:07 ` Rodrigo Vivi
2020-12-09 18:48 ` Huang, Sean Z
2020-12-10 16:55 ` Jani Nikula
1 sibling, 1 reply; 34+ messages in thread
From: Rodrigo Vivi @ 2020-12-09 18:07 UTC (permalink / raw)
To: Huang, Sean Z; +Cc: Intel-gfx
On Tue, Dec 08, 2020 at 11:02:56PM -0800, Huang, Sean Z wrote:
> Set the KCR init during the boot time, which is
> required by hardware, to allow us doing further
> protection operation such as sending commands to
> GPU or TEE.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 8 ++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 6 ++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index ba43b2c923c7..c4815950567d 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -6,6 +6,12 @@
> #include "intel_pxp.h"
> #include "intel_pxp_context.h"
>
> +/* KCR register definitions */
> +#define KCR_INIT _MMIO(0x320f0)
> +#define KCR_INIT_MASK_SHIFT (16)
> +/* Setting KCR Init bit is required after system boot */
> +#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << KCR_INIT_MASK_SHIFT))
> +
> int intel_pxp_init(struct intel_pxp *pxp)
> {
> struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
> @@ -16,6 +22,8 @@ int intel_pxp_init(struct intel_pxp *pxp)
>
> intel_pxp_ctx_init(&pxp->ctx);
>
> + intel_uncore_write(gt->uncore, KCR_INIT, KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
> +
> drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index 7c3d49a6a3ab..b906bf7dea90 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -15,6 +15,7 @@ struct intel_pxp {
> #ifdef CONFIG_DRM_I915_PXP
> int intel_pxp_init(struct intel_pxp *pxp);
> void intel_pxp_uninit(struct intel_pxp *pxp);
> +int intel_pxp_reg_read(struct intel_pxp *pxp, u32 offset, u32 *regval);
> #else
> static inline int intel_pxp_init(struct intel_pxp *pxp)
> {
> @@ -24,6 +25,11 @@ static inline int intel_pxp_init(struct intel_pxp *pxp)
> static inline void intel_pxp_uninit(struct intel_pxp *pxp)
> {
> }
> +
> +static inline int intel_pxp_reg_read(struct intel_pxp *pxp, u32 offset, u32 *regval)
> +{
> + return 0;
> +}
I'm wondering if some other patch in this series will explain the need for this,
but as is right now, this shouldn't be here on this patch... and maybe not even at all.
Let's minimize the wraps and use the already provided read/write functions.
> #endif
>
> #endif /* __INTEL_PXP_PM_H__ */
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [Intel-gfx] [RFC-v3 02/13] drm/i915/pxp: set KCR reg init during the boot time
2020-12-09 18:07 ` Rodrigo Vivi
@ 2020-12-09 18:48 ` Huang, Sean Z
0 siblings, 0 replies; 34+ messages in thread
From: Huang, Sean Z @ 2020-12-09 18:48 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: Intel-gfx
> I'm wondering if some other patch in this series will explain the need for this, but as is right now, this shouldn't be here on this patch... and maybe not even at all.
> Let's minimize the wraps and use the already provided read/write functions.
Thanks for pointing it out. Yes, you're correct. I missed this one and it should be removed from this commit.
Best regards,
Sean
-----Original Message-----
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Sent: Wednesday, December 9, 2020 10:08 AM
To: Huang, Sean Z <sean.z.huang@intel.com>
Cc: Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFC-v3 02/13] drm/i915/pxp: set KCR reg init during the boot time
On Tue, Dec 08, 2020 at 11:02:56PM -0800, Huang, Sean Z wrote:
> Set the KCR init during the boot time, which is required by hardware,
> to allow us doing further protection operation such as sending
> commands to GPU or TEE.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 8 ++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 6 ++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index ba43b2c923c7..c4815950567d 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -6,6 +6,12 @@
> #include "intel_pxp.h"
> #include "intel_pxp_context.h"
>
> +/* KCR register definitions */
> +#define KCR_INIT _MMIO(0x320f0)
> +#define KCR_INIT_MASK_SHIFT (16)
> +/* Setting KCR Init bit is required after system boot */ #define
> +KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
> +KCR_INIT_MASK_SHIFT))
> +
> int intel_pxp_init(struct intel_pxp *pxp) {
> struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp); @@
> -16,6 +22,8 @@ int intel_pxp_init(struct intel_pxp *pxp)
>
> intel_pxp_ctx_init(&pxp->ctx);
>
> + intel_uncore_write(gt->uncore, KCR_INIT,
> +KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
> +
> drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content
> support initialized\n");
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index 7c3d49a6a3ab..b906bf7dea90 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -15,6 +15,7 @@ struct intel_pxp {
> #ifdef CONFIG_DRM_I915_PXP
> int intel_pxp_init(struct intel_pxp *pxp); void
> intel_pxp_uninit(struct intel_pxp *pxp);
> +int intel_pxp_reg_read(struct intel_pxp *pxp, u32 offset, u32
> +*regval);
> #else
> static inline int intel_pxp_init(struct intel_pxp *pxp) { @@ -24,6
> +25,11 @@ static inline int intel_pxp_init(struct intel_pxp *pxp)
> static inline void intel_pxp_uninit(struct intel_pxp *pxp) { }
> +
> +static inline int intel_pxp_reg_read(struct intel_pxp *pxp, u32
> +offset, u32 *regval) {
> + return 0;
> +}
I'm wondering if some other patch in this series will explain the need for this, but as is right now, this shouldn't be here on this patch... and maybe not even at all.
Let's minimize the wraps and use the already provided read/write functions.
> #endif
>
> #endif /* __INTEL_PXP_PM_H__ */
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Intel-gfx] [RFC-v3 02/13] drm/i915/pxp: set KCR reg init during the boot time
2020-12-09 7:02 ` [Intel-gfx] [RFC-v3 02/13] drm/i915/pxp: set KCR reg init during the boot time Huang, Sean Z
2020-12-09 18:07 ` Rodrigo Vivi
@ 2020-12-10 16:55 ` Jani Nikula
1 sibling, 0 replies; 34+ messages in thread
From: Jani Nikula @ 2020-12-10 16:55 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
On Tue, 08 Dec 2020, "Huang, Sean Z" <sean.z.huang@intel.com> wrote:
> Set the KCR init during the boot time, which is
> required by hardware, to allow us doing further
> protection operation such as sending commands to
> GPU or TEE.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 8 ++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 6 ++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index ba43b2c923c7..c4815950567d 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -6,6 +6,12 @@
> #include "intel_pxp.h"
> #include "intel_pxp_context.h"
>
> +/* KCR register definitions */
> +#define KCR_INIT _MMIO(0x320f0)
> +#define KCR_INIT_MASK_SHIFT (16)
> +/* Setting KCR Init bit is required after system boot */
> +#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << KCR_INIT_MASK_SHIFT))
> +
Why here instead of i915_reg.h?
Please at least follow the style described at the top of that file.
BR,
Jani.
> int intel_pxp_init(struct intel_pxp *pxp)
> {
> struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
> @@ -16,6 +22,8 @@ int intel_pxp_init(struct intel_pxp *pxp)
>
> intel_pxp_ctx_init(&pxp->ctx);
>
> + intel_uncore_write(gt->uncore, KCR_INIT, KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
> +
> drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index 7c3d49a6a3ab..b906bf7dea90 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -15,6 +15,7 @@ struct intel_pxp {
> #ifdef CONFIG_DRM_I915_PXP
> int intel_pxp_init(struct intel_pxp *pxp);
> void intel_pxp_uninit(struct intel_pxp *pxp);
> +int intel_pxp_reg_read(struct intel_pxp *pxp, u32 offset, u32 *regval);
> #else
> static inline int intel_pxp_init(struct intel_pxp *pxp)
> {
> @@ -24,6 +25,11 @@ static inline int intel_pxp_init(struct intel_pxp *pxp)
> static inline void intel_pxp_uninit(struct intel_pxp *pxp)
> {
> }
> +
> +static inline int intel_pxp_reg_read(struct intel_pxp *pxp, u32 offset, u32 *regval)
> +{
> + return 0;
> +}
> #endif
>
> #endif /* __INTEL_PXP_PM_H__ */
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* [Intel-gfx] [RFC-v3 03/13] drm/i915/pxp: Implement funcs to create the TEE channel
2020-12-09 7:02 [Intel-gfx] [RFC-v3 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
2020-12-09 7:02 ` [Intel-gfx] [RFC-v3 01/13] drm/i915/pxp: Introduce Intel PXP component Huang, Sean Z
2020-12-09 7:02 ` [Intel-gfx] [RFC-v3 02/13] drm/i915/pxp: set KCR reg init during the boot time Huang, Sean Z
@ 2020-12-09 7:02 ` Huang, Sean Z
2020-12-10 10:12 ` Joonas Lahtinen
2020-12-10 17:00 ` Jani Nikula
2020-12-09 7:02 ` [Intel-gfx] [RFC-v3 04/13] drm/i915/pxp: Create the arbitrary session after boot Huang, Sean Z
` (12 subsequent siblings)
15 siblings, 2 replies; 34+ messages in thread
From: Huang, Sean Z @ 2020-12-09 7:02 UTC (permalink / raw)
To: Intel-gfx
Implement the funcs to create the TEE channel, so kernel can
send the TEE commands directly to TEE for creating the arbitrary
(defualt) session.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 5 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 132 +++++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14 +++
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 45 ++++++++
8 files changed, 206 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
create mode 100644 include/drm/i915_pxp_tee_interface.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 99efac469cc2..c703dbd91158 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -257,7 +257,8 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
- pxp/intel_pxp_context.o
+ pxp/intel_pxp_context.o \
+ pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5708e11d917b..9299a456adb0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -322,6 +322,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
mutex_init(&dev_priv->wm.wm_mutex);
mutex_init(&dev_priv->pps_mutex);
mutex_init(&dev_priv->hdcp_comp_mutex);
+ mutex_init(&dev_priv->pxp_tee_comp_mutex);
i915_memcpy_init_early(dev_priv);
intel_runtime_pm_init_early(&dev_priv->runtime_pm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fc1090c6889c..66f91d8a575b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1216,6 +1216,12 @@ struct drm_i915_private {
/* Mutex to protect the above hdcp component related values. */
struct mutex hdcp_comp_mutex;
+ struct i915_pxp_comp_master *pxp_tee_master;
+ bool pxp_tee_comp_added;
+
+ /* Mutex to protect the above pxp_tee component related values. */
+ struct mutex pxp_tee_comp_mutex;
+
I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
/*
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index c4815950567d..4104dd89ca7f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -5,6 +5,7 @@
#include "i915_drv.h"
#include "intel_pxp.h"
#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
/* KCR register definitions */
#define KCR_INIT _MMIO(0x320f0)
@@ -24,6 +25,8 @@ int intel_pxp_init(struct intel_pxp *pxp)
intel_uncore_write(gt->uncore, KCR_INIT, KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
+ intel_pxp_tee_component_init(pxp);
+
drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
return 0;
@@ -31,5 +34,7 @@ int intel_pxp_init(struct intel_pxp *pxp)
void intel_pxp_uninit(struct intel_pxp *pxp)
{
+ intel_pxp_tee_component_fini(pxp);
+
intel_pxp_ctx_fini(&pxp->ctx);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
new file mode 100644
index 000000000000..ca6b61099aee
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include <linux/component.h>
+#include "drm/i915_pxp_tee_interface.h"
+#include "drm/i915_component.h"
+#include "i915_drv.h"
+#include "intel_pxp.h"
+#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
+
+static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
+ void *msg_in, u32 msg_in_size,
+ void *msg_out, u32 *msg_out_size_ptr,
+ u32 msg_out_buf_size)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ struct drm_i915_private *i915 = gt->i915;
+ struct i915_pxp_comp_master *pxp_tee_master = i915->pxp_tee_master;
+
+ if (!pxp_tee_master || !msg_in || !msg_out || !msg_out_size_ptr)
+ return -EINVAL;
+
+ lockdep_assert_held(&i915->pxp_tee_comp_mutex);
+
+ if (drm_debug_enabled(DRM_UT_DRIVER))
+ print_hex_dump(KERN_DEBUG, "TEE input message binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, msg_in, msg_in_size, true);
+
+ ret = pxp_tee_master->ops->send(pxp_tee_master->tee_dev, msg_in, msg_in_size);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to send TEE message\n");
+ return -EFAULT;
+ }
+
+ ret = pxp_tee_master->ops->receive(pxp_tee_master->tee_dev, msg_out, msg_out_buf_size);
+ if (ret < 0) {
+ drm_err(&i915->drm, "Failed to receive TEE message\n");
+ return -EFAULT;
+ }
+
+ if (ret > msg_out_buf_size) {
+ drm_err(&i915->drm, "Failed to receive TEE message due to unexpected output size\n");
+ return -EFAULT;
+ }
+
+ *msg_out_size_ptr = ret;
+ ret = 0;
+
+ if (drm_debug_enabled(DRM_UT_DRIVER))
+ print_hex_dump(KERN_DEBUG, "TEE output message binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, msg_out, *msg_out_size_ptr, true);
+
+ return ret;
+}
+
+/**
+ * i915_pxp_tee_component_bind - bind funciton to pass the function pointers to pxp_tee
+ * @i915_kdev: pointer to i915 kernel device
+ * @tee_kdev: pointer to tee kernel device
+ * @data: pointer to pxp_tee_master containing the function pointers
+ *
+ * This bind function is called during the system boot or resume from system sleep.
+ *
+ * Return: return 0 if successful.
+ */
+static int i915_pxp_tee_component_bind(struct device *i915_kdev,
+ struct device *tee_kdev, void *data)
+{
+ struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
+
+ if (!i915 || !tee_kdev || !data)
+ return -EPERM;
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+ i915->pxp_tee_master = (struct i915_pxp_comp_master *)data;
+ i915->pxp_tee_master->tee_dev = tee_kdev;
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+
+ return 0;
+}
+
+static void i915_pxp_tee_component_unbind(struct device *i915_kdev,
+ struct device *tee_kdev, void *data)
+{
+ struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
+
+ if (!i915 || !tee_kdev || !data)
+ return;
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+ i915->pxp_tee_master = NULL;
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+}
+
+static const struct component_ops i915_pxp_tee_component_ops = {
+ .bind = i915_pxp_tee_component_bind,
+ .unbind = i915_pxp_tee_component_unbind,
+};
+
+void intel_pxp_tee_component_init(struct intel_pxp *pxp)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ struct drm_i915_private *i915 = gt->i915;
+
+ ret = component_add_typed(i915->drm.dev, &i915_pxp_tee_component_ops,
+ I915_COMPONENT_PXP);
+ if (ret < 0) {
+ drm_err(&i915->drm, "Failed at component add(%d)\n", ret);
+ return;
+ }
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+ i915->pxp_tee_comp_added = true;
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+}
+
+void intel_pxp_tee_component_fini(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ struct drm_i915_private *i915 = gt->i915;
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+ i915->pxp_tee_comp_added = false;
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+
+ component_del(i915->drm.dev, &i915_pxp_tee_component_ops);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
new file mode 100644
index 000000000000..4b5e3edb1d9b
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_TEE_H__
+#define __INTEL_PXP_TEE_H__
+
+#include "intel_pxp.h"
+
+void intel_pxp_tee_component_init(struct intel_pxp *pxp);
+void intel_pxp_tee_component_fini(struct intel_pxp *pxp);
+
+#endif /* __INTEL_PXP_TEE_H__ */
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index 55c3b123581b..c1e2a43d2d1e 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -29,6 +29,7 @@
enum i915_component_type {
I915_COMPONENT_AUDIO = 1,
I915_COMPONENT_HDCP,
+ I915_COMPONENT_PXP
};
/* MAX_PORT is the number of port
diff --git a/include/drm/i915_pxp_tee_interface.h b/include/drm/i915_pxp_tee_interface.h
new file mode 100644
index 000000000000..3999e255e145
--- /dev/null
+++ b/include/drm/i915_pxp_tee_interface.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Authors:
+ * Vitaly Lubart <vitaly.lubart@intel.com>
+ */
+
+#ifndef _I915_PXP_TEE_INTERFACE_H_
+#define _I915_PXP_TEE_INTERFACE_H_
+
+#include <linux/mutex.h>
+#include <linux/device.h>
+
+/**
+ * struct i915_pxp_component_ops - ops for PXP services.
+ * @owner: Module providing the ops
+ * @send: sends data to PXP
+ * @receive: receives data from PXP
+ */
+struct i915_pxp_component_ops {
+ /**
+ * @owner: owner of the module provding the ops
+ */
+ struct module *owner;
+
+ int (*send)(struct device *dev, const void *message, size_t size);
+ int (*receive)(struct device *dev, void *buffer, size_t size);
+};
+
+/**
+ * struct i915_pxp_component_master - Used for communication between i915
+ * and TEE drivers for the PXP services
+ * @tee_dev: device that provide the PXP service from TEE Bus.
+ * @pxp_ops: Ops implemented by TEE driver, used by i915 driver.
+ */
+struct i915_pxp_comp_master {
+ struct device *tee_dev;
+ const struct i915_pxp_component_ops *ops;
+
+ /* To protect the above members. */
+ struct mutex mutex;
+};
+
+#endif /* _I915_TEE_PXP_INTERFACE_H_ */
--
2.17.1
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^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [Intel-gfx] [RFC-v3 03/13] drm/i915/pxp: Implement funcs to create the TEE channel
2020-12-09 7:02 ` [Intel-gfx] [RFC-v3 03/13] drm/i915/pxp: Implement funcs to create the TEE channel Huang, Sean Z
@ 2020-12-10 10:12 ` Joonas Lahtinen
2020-12-10 17:00 ` Jani Nikula
1 sibling, 0 replies; 34+ messages in thread
From: Joonas Lahtinen @ 2020-12-10 10:12 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
Please not that in the middle section of the review I noticed that we're
creating i915_component which is injected with the send/recv functions
from MEI subsystem, so the component naming conventions seem to be
reversed to me.
Quoting Huang, Sean Z (2020-12-09 09:02:57)
> Implement the funcs to create the TEE channel, so kernel can
> send the TEE commands directly to TEE for creating the arbitrary
> (defualt) session.
This TEE channel should be described in more detail. Now it
is hard to assess if the placement is correct. Is it related to the GT
only, or is it also related to display?
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
<SNIP>
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1216,6 +1216,12 @@ struct drm_i915_private {
> /* Mutex to protect the above hdcp component related values. */
> struct mutex hdcp_comp_mutex;
>
> + struct i915_pxp_comp_master *pxp_tee_master;
The struct and variable names don't relate. No need to add "_master"
here (or "_primary") as we don't seem to have other than one.
struct i915_pxp_tee_component *pxp_tee_comp;
I can't assess if this belongs to intel_gt or here.
> + bool pxp_tee_comp_added;
Why can't we just check for non-zero pxp_tee; ?
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -5,6 +5,7 @@
> #include "i915_drv.h"
> #include "intel_pxp.h"
> #include "intel_pxp_context.h"
> +#include "intel_pxp_tee.h"
>
> /* KCR register definitions */
> #define KCR_INIT _MMIO(0x320f0)
> @@ -24,6 +25,8 @@ int intel_pxp_init(struct intel_pxp *pxp)
>
> intel_uncore_write(gt->uncore, KCR_INIT, KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
>
> + intel_pxp_tee_component_init(pxp);
I don't think this is the right location. This is for early hardware
init.
This should be a call named i915_pxp_tee_component_init();
And as it is related to exposing the component it should be much later
in init, probably near the audio component.
> @@ -31,5 +34,7 @@ int intel_pxp_init(struct intel_pxp *pxp)
>
> void intel_pxp_uninit(struct intel_pxp *pxp)
> {
> + intel_pxp_tee_component_fini(pxp);
Same here.
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> @@ -0,0 +1,132 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +
> +#include <linux/component.h>
> +#include "drm/i915_pxp_tee_interface.h"
> +#include "drm/i915_component.h"
> +#include "i915_drv.h"
> +#include "intel_pxp.h"
> +#include "intel_pxp_context.h"
> +#include "intel_pxp_tee.h"
> +
> +static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
For .c local static functions, the prefixes should be dropped.
This should take struct intel_pxp_tee *tee as first parameter
> + void *msg_in, u32 msg_in_size,
void* is no good, doesn't give impression of unit of size (pages?)
> + void *msg_out, u32 *msg_out_size_ptr,
_ptr is tautology
> + u32 msg_out_buf_size)
We can use the same variable for in and out
static int do_io(struct intel_pxp_tee *tee,
u8 *in, size_t in_nbytes,
u8 *out, size_t *out_nbytes)
> +{
> + int ret;
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> + struct drm_i915_private *i915 = gt->i915;
> + struct i915_pxp_comp_master *pxp_tee_master = i915->pxp_tee_master;
> +
> + if (!pxp_tee_master || !msg_in || !msg_out || !msg_out_size_ptr)
> + return -EINVAL;
GEM_BUG_ON() should be sufficient.
> + lockdep_assert_held(&i915->pxp_tee_comp_mutex);
> +
> + if (drm_debug_enabled(DRM_UT_DRIVER))
> + print_hex_dump(KERN_DEBUG, "TEE input message binaries:",
> + DUMP_PREFIX_OFFSET, 4, 4, msg_in, msg_in_size, true);
> +
> + ret = pxp_tee_master->ops->send(pxp_tee_master->tee_dev, msg_in, msg_in_size);
> + if (ret) {
> + drm_err(&i915->drm, "Failed to send TEE message\n");
> + return -EFAULT;
> + }
> +
> + ret = pxp_tee_master->ops->receive(pxp_tee_master->tee_dev, msg_out, msg_out_buf_size);
> + if (ret < 0) {
> + drm_err(&i915->drm, "Failed to receive TEE message\n");
> + return -EFAULT;
> + }
Ok, this got confusing. It seems that we're importing the TEE hardware
to use from MEI subsystem? And not exposing it from i915.
I think the whole component mechanism is then the wrong way around. It
should be us importing the tee dev from MEI subsystem to communicate.
Also, why are we having separate send/receive callbacks but we stuff
everything under single function, we should not do that. So this should
be split into send() and recv() functions here.
<SKIPPING REVIEW HERE>
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_TEE_H__
> +#define __INTEL_PXP_TEE_H__
> +
> +#include "intel_pxp.h"
We should not do this, but only include the _types.h files required.
But in this case it would only be intel_pxp_tee_types.h as that should
be the parameter.
> +void intel_pxp_tee_component_init(struct intel_pxp *pxp);
> +void intel_pxp_tee_component_fini(struct intel_pxp *pxp);
We should be consistent with <struct>_<verb>, the "component" is extra
here.
void intel_pxp_tee_init(struct intel_pxp_tee *tee);
And same for _fini().
> +
> +#endif /* __INTEL_PXP_TEE_H__ */
> diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
> index 55c3b123581b..c1e2a43d2d1e 100644
> --- a/include/drm/i915_component.h
> +++ b/include/drm/i915_component.h
> @@ -29,6 +29,7 @@
> enum i915_component_type {
> I915_COMPONENT_AUDIO = 1,
> I915_COMPONENT_HDCP,
> + I915_COMPONENT_PXP
I think I915_COMPONENT_PXP_TEE here, too. Otherwise it's easy to lose
track of what is passed onwards.
> +++ b/include/drm/i915_pxp_tee_interface.h
I think the file should be i915_pxp_tee_component.h for clarity.
> @@ -0,0 +1,45 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2020 Intel Corporation
> + *
> + * Authors:
> + * Vitaly Lubart <vitaly.lubart@intel.com>
> + */
> +
> +#ifndef _I915_PXP_TEE_INTERFACE_H_
> +#define _I915_PXP_TEE_INTERFACE_H_
"PXP_TEE_COMPONENT"
> +
> +#include <linux/mutex.h>
> +#include <linux/device.h>
> +
> +/**
> + * struct i915_pxp_component_ops - ops for PXP services.
> + * @owner: Module providing the ops
> + * @send: sends data to PXP
> + * @receive: receives data from PXP
> + */
> +struct i915_pxp_component_ops {
i915_pxp_tee_component_ops
Regards, Joonas
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^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [Intel-gfx] [RFC-v3 03/13] drm/i915/pxp: Implement funcs to create the TEE channel
2020-12-09 7:02 ` [Intel-gfx] [RFC-v3 03/13] drm/i915/pxp: Implement funcs to create the TEE channel Huang, Sean Z
2020-12-10 10:12 ` Joonas Lahtinen
@ 2020-12-10 17:00 ` Jani Nikula
1 sibling, 0 replies; 34+ messages in thread
From: Jani Nikula @ 2020-12-10 17:00 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
On Tue, 08 Dec 2020, "Huang, Sean Z" <sean.z.huang@intel.com> wrote:
> Implement the funcs to create the TEE channel, so kernel can
> send the TEE commands directly to TEE for creating the arbitrary
> (defualt) session.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 3 +-
> drivers/gpu/drm/i915/i915_drv.c | 1 +
> drivers/gpu/drm/i915/i915_drv.h | 6 ++
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 5 +
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 132 +++++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14 +++
> include/drm/i915_component.h | 1 +
> include/drm/i915_pxp_tee_interface.h | 45 ++++++++
> 8 files changed, 206 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> create mode 100644 include/drm/i915_pxp_tee_interface.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 99efac469cc2..c703dbd91158 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -257,7 +257,8 @@ i915-y += i915_perf.o
> # Protected execution platform (PXP) support
> i915-$(CONFIG_DRM_I915_PXP) += \
> pxp/intel_pxp.o \
> - pxp/intel_pxp_context.o
> + pxp/intel_pxp_context.o \
> + pxp/intel_pxp_tee.o
>
> # Post-mortem debug and GPU hang state capture
> i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 5708e11d917b..9299a456adb0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -322,6 +322,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
> mutex_init(&dev_priv->wm.wm_mutex);
> mutex_init(&dev_priv->pps_mutex);
> mutex_init(&dev_priv->hdcp_comp_mutex);
> + mutex_init(&dev_priv->pxp_tee_comp_mutex);
>
> i915_memcpy_init_early(dev_priv);
> intel_runtime_pm_init_early(&dev_priv->runtime_pm);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fc1090c6889c..66f91d8a575b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1216,6 +1216,12 @@ struct drm_i915_private {
> /* Mutex to protect the above hdcp component related values. */
> struct mutex hdcp_comp_mutex;
>
> + struct i915_pxp_comp_master *pxp_tee_master;
> + bool pxp_tee_comp_added;
> +
> + /* Mutex to protect the above pxp_tee component related values. */
> + struct mutex pxp_tee_comp_mutex;
> +
Please wrap the above in
struct {
...
} pxp;
and drop the pxp_ prefixes.
> I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
>
> /*
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index c4815950567d..4104dd89ca7f 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -5,6 +5,7 @@
> #include "i915_drv.h"
> #include "intel_pxp.h"
> #include "intel_pxp_context.h"
> +#include "intel_pxp_tee.h"
>
> /* KCR register definitions */
> #define KCR_INIT _MMIO(0x320f0)
> @@ -24,6 +25,8 @@ int intel_pxp_init(struct intel_pxp *pxp)
>
> intel_uncore_write(gt->uncore, KCR_INIT, KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
>
> + intel_pxp_tee_component_init(pxp);
> +
> drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
>
> return 0;
> @@ -31,5 +34,7 @@ int intel_pxp_init(struct intel_pxp *pxp)
>
> void intel_pxp_uninit(struct intel_pxp *pxp)
> {
> + intel_pxp_tee_component_fini(pxp);
> +
> intel_pxp_ctx_fini(&pxp->ctx);
> }
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> new file mode 100644
> index 000000000000..ca6b61099aee
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> @@ -0,0 +1,132 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +
> +#include <linux/component.h>
> +#include "drm/i915_pxp_tee_interface.h"
> +#include "drm/i915_component.h"
> +#include "i915_drv.h"
> +#include "intel_pxp.h"
> +#include "intel_pxp_context.h"
> +#include "intel_pxp_tee.h"
> +
> +static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
> + void *msg_in, u32 msg_in_size,
> + void *msg_out, u32 *msg_out_size_ptr,
> + u32 msg_out_buf_size)
> +{
> + int ret;
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> + struct drm_i915_private *i915 = gt->i915;
> + struct i915_pxp_comp_master *pxp_tee_master = i915->pxp_tee_master;
> +
> + if (!pxp_tee_master || !msg_in || !msg_out || !msg_out_size_ptr)
> + return -EINVAL;
> +
> + lockdep_assert_held(&i915->pxp_tee_comp_mutex);
> +
> + if (drm_debug_enabled(DRM_UT_DRIVER))
> + print_hex_dump(KERN_DEBUG, "TEE input message binaries:",
> + DUMP_PREFIX_OFFSET, 4, 4, msg_in, msg_in_size, true);
> +
> + ret = pxp_tee_master->ops->send(pxp_tee_master->tee_dev, msg_in, msg_in_size);
> + if (ret) {
> + drm_err(&i915->drm, "Failed to send TEE message\n");
> + return -EFAULT;
> + }
> +
> + ret = pxp_tee_master->ops->receive(pxp_tee_master->tee_dev, msg_out, msg_out_buf_size);
> + if (ret < 0) {
> + drm_err(&i915->drm, "Failed to receive TEE message\n");
> + return -EFAULT;
> + }
> +
> + if (ret > msg_out_buf_size) {
> + drm_err(&i915->drm, "Failed to receive TEE message due to unexpected output size\n");
> + return -EFAULT;
> + }
> +
> + *msg_out_size_ptr = ret;
> + ret = 0;
> +
> + if (drm_debug_enabled(DRM_UT_DRIVER))
> + print_hex_dump(KERN_DEBUG, "TEE output message binaries:",
> + DUMP_PREFIX_OFFSET, 4, 4, msg_out, *msg_out_size_ptr, true);
> +
> + return ret;
> +}
> +
> +/**
> + * i915_pxp_tee_component_bind - bind funciton to pass the function pointers to pxp_tee
> + * @i915_kdev: pointer to i915 kernel device
> + * @tee_kdev: pointer to tee kernel device
> + * @data: pointer to pxp_tee_master containing the function pointers
> + *
> + * This bind function is called during the system boot or resume from system sleep.
> + *
> + * Return: return 0 if successful.
> + */
> +static int i915_pxp_tee_component_bind(struct device *i915_kdev,
> + struct device *tee_kdev, void *data)
> +{
> + struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
> +
> + if (!i915 || !tee_kdev || !data)
> + return -EPERM;
> +
> + mutex_lock(&i915->pxp_tee_comp_mutex);
> + i915->pxp_tee_master = (struct i915_pxp_comp_master *)data;
> + i915->pxp_tee_master->tee_dev = tee_kdev;
> + mutex_unlock(&i915->pxp_tee_comp_mutex);
> +
> + return 0;
> +}
> +
> +static void i915_pxp_tee_component_unbind(struct device *i915_kdev,
> + struct device *tee_kdev, void *data)
> +{
> + struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
> +
> + if (!i915 || !tee_kdev || !data)
> + return;
> +
> + mutex_lock(&i915->pxp_tee_comp_mutex);
> + i915->pxp_tee_master = NULL;
> + mutex_unlock(&i915->pxp_tee_comp_mutex);
> +}
> +
> +static const struct component_ops i915_pxp_tee_component_ops = {
> + .bind = i915_pxp_tee_component_bind,
> + .unbind = i915_pxp_tee_component_unbind,
> +};
> +
> +void intel_pxp_tee_component_init(struct intel_pxp *pxp)
> +{
> + int ret;
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> + struct drm_i915_private *i915 = gt->i915;
> +
> + ret = component_add_typed(i915->drm.dev, &i915_pxp_tee_component_ops,
> + I915_COMPONENT_PXP);
> + if (ret < 0) {
> + drm_err(&i915->drm, "Failed at component add(%d)\n", ret);
> + return;
> + }
> +
> + mutex_lock(&i915->pxp_tee_comp_mutex);
> + i915->pxp_tee_comp_added = true;
> + mutex_unlock(&i915->pxp_tee_comp_mutex);
> +}
> +
> +void intel_pxp_tee_component_fini(struct intel_pxp *pxp)
> +{
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> + struct drm_i915_private *i915 = gt->i915;
> +
> + mutex_lock(&i915->pxp_tee_comp_mutex);
> + i915->pxp_tee_comp_added = false;
> + mutex_unlock(&i915->pxp_tee_comp_mutex);
> +
> + component_del(i915->drm.dev, &i915_pxp_tee_component_ops);
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> new file mode 100644
> index 000000000000..4b5e3edb1d9b
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_TEE_H__
> +#define __INTEL_PXP_TEE_H__
> +
> +#include "intel_pxp.h"
> +
> +void intel_pxp_tee_component_init(struct intel_pxp *pxp);
> +void intel_pxp_tee_component_fini(struct intel_pxp *pxp);
> +
> +#endif /* __INTEL_PXP_TEE_H__ */
> diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
> index 55c3b123581b..c1e2a43d2d1e 100644
> --- a/include/drm/i915_component.h
> +++ b/include/drm/i915_component.h
> @@ -29,6 +29,7 @@
> enum i915_component_type {
> I915_COMPONENT_AUDIO = 1,
> I915_COMPONENT_HDCP,
> + I915_COMPONENT_PXP
> };
>
> /* MAX_PORT is the number of port
> diff --git a/include/drm/i915_pxp_tee_interface.h b/include/drm/i915_pxp_tee_interface.h
> new file mode 100644
> index 000000000000..3999e255e145
> --- /dev/null
> +++ b/include/drm/i915_pxp_tee_interface.h
> @@ -0,0 +1,45 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2020 Intel Corporation
> + *
> + * Authors:
> + * Vitaly Lubart <vitaly.lubart@intel.com>
Do we need the author lines? I'd prefer phasing them all out, because
it'll be stale almost immediately after merging. Also, it's just 40
lines of definitions.
BR,
Jani.
> + */
> +
> +#ifndef _I915_PXP_TEE_INTERFACE_H_
> +#define _I915_PXP_TEE_INTERFACE_H_
> +
> +#include <linux/mutex.h>
> +#include <linux/device.h>
> +
> +/**
> + * struct i915_pxp_component_ops - ops for PXP services.
> + * @owner: Module providing the ops
> + * @send: sends data to PXP
> + * @receive: receives data from PXP
> + */
> +struct i915_pxp_component_ops {
> + /**
> + * @owner: owner of the module provding the ops
> + */
> + struct module *owner;
> +
> + int (*send)(struct device *dev, const void *message, size_t size);
> + int (*receive)(struct device *dev, void *buffer, size_t size);
> +};
> +
> +/**
> + * struct i915_pxp_component_master - Used for communication between i915
> + * and TEE drivers for the PXP services
> + * @tee_dev: device that provide the PXP service from TEE Bus.
> + * @pxp_ops: Ops implemented by TEE driver, used by i915 driver.
> + */
> +struct i915_pxp_comp_master {
> + struct device *tee_dev;
> + const struct i915_pxp_component_ops *ops;
> +
> + /* To protect the above members. */
> + struct mutex mutex;
> +};
> +
> +#endif /* _I915_TEE_PXP_INTERFACE_H_ */
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* [Intel-gfx] [RFC-v3 04/13] drm/i915/pxp: Create the arbitrary session after boot
2020-12-09 7:02 [Intel-gfx] [RFC-v3 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (2 preceding siblings ...)
2020-12-09 7:02 ` [Intel-gfx] [RFC-v3 03/13] drm/i915/pxp: Implement funcs to create the TEE channel Huang, Sean Z
@ 2020-12-09 7:02 ` Huang, Sean Z
2020-12-09 9:58 ` kernel test robot
2020-12-10 10:42 ` Joonas Lahtinen
2020-12-09 7:02 ` [Intel-gfx] [RFC-v3 05/13] drm/i915/pxp: Func to send hardware session termination Huang, Sean Z
` (11 subsequent siblings)
15 siblings, 2 replies; 34+ messages in thread
From: Huang, Sean Z @ 2020-12-09 7:02 UTC (permalink / raw)
To: Intel-gfx
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation. This arbitrary session needs to be re-created after
teardown or power event because hardware encryption key won't be
valid after such cases.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.h | 16 ++
drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 152 +++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 36 +++++
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 5 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 38 +++++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 11 ++
8 files changed, 260 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index c703dbd91158..0710cc522f38 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -257,6 +257,7 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
+ pxp/intel_pxp_arb.o \
pxp/intel_pxp_context.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 4104dd89ca7f..67bdaeb79b40 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,7 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
#include "intel_pxp_tee.h"
+#include "intel_pxp_arb.h"
/* KCR register definitions */
#define KCR_INIT _MMIO(0x320f0)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index b906bf7dea90..406d35f402a6 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -8,6 +8,22 @@
#include "intel_pxp_context.h"
+enum pxp_session_types {
+ SESSION_TYPE_TYPE0 = 0,
+ SESSION_TYPE_TYPE1 = 1,
+
+ SESSION_TYPE_MAX
+};
+
+enum pxp_protection_modes {
+ PROTECTION_MODE_NONE = 0,
+ PROTECTION_MODE_LM = 2,
+ PROTECTION_MODE_HM = 3,
+ PROTECTION_MODE_SM = 6,
+
+ PROTECTION_MODE_ALL
+};
+
struct intel_pxp {
struct pxp_context ctx;
};
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
new file mode 100644
index 000000000000..c1ad45b83478
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+
+#include "intel_pxp_arb.h"
+#include "intel_pxp.h"
+#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
+
+#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-31 */
+
+/* Arbitrary session */
+#define ARB_SESSION_INDEX 0xf
+#define ARB_SESSION_TYPE SESSION_TYPE_TYPE0
+#define ARB_PROTECTION_MODE PROTECTION_MODE_HM
+
+static bool is_hw_arb_session_in_play(struct intel_pxp *pxp)
+{
+ u32 regval_sip = 0;
+ intel_wakeref_t wakeref;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ with_intel_runtime_pm(>->i915->runtime_pm, wakeref) {
+ regval_sip = intel_uncore_read(gt->uncore, GEN12_KCR_SIP);
+ }
+
+ return regval_sip & BIT(ARB_SESSION_INDEX);
+}
+
+/* wait hw session_in_play reg to match the current sw state */
+static int wait_arb_hw_sw_state(struct intel_pxp *pxp)
+{
+ const int max_retry = 10;
+ const int ms_delay = 10;
+ int retry = 0;
+ int ret;
+ struct pxp_protected_session *arb = pxp->ctx.arb_session;
+
+ ret = -EINVAL;
+ for (retry = 0; retry < max_retry; retry++) {
+ if (is_hw_arb_session_in_play(pxp) ==
+ arb->is_in_play) {
+ ret = 0;
+ break;
+ }
+
+ msleep(ms_delay);
+ }
+
+ return ret;
+}
+
+/**
+ * create_session_entry - Create a new session entry with provided info.
+ * @pxp: pointer to pxp struct.
+ *
+ * Return: the pointer to the created session.
+ */
+static struct pxp_protected_session *create_session_entry(struct intel_pxp *pxp)
+{
+ struct pxp_protected_session *session;
+
+ session = kzalloc(sizeof(*session), GFP_KERNEL);
+ if (!session)
+ return NULL;
+
+ session->context_id = pxp->ctx.id;
+ session->type = ARB_SESSION_TYPE;
+ session->protection_mode = ARB_PROTECTION_MODE;
+ session->index = ARB_SESSION_INDEX;
+ session->is_in_play = false;
+
+ return session;
+}
+
+int intel_pxp_arb_reserve_session(struct intel_pxp *pxp)
+{
+ int ret;
+ struct pxp_protected_session *session = NULL;
+
+ lockdep_assert_held(&pxp->ctx.mutex);
+
+ ret = wait_arb_hw_sw_state(pxp);
+ if (ret)
+ return ret;
+
+ session = create_session_entry(pxp);
+ if (!session)
+ return -ENOMEM;
+
+ return ret;
+}
+
+/**
+ * intel_pxp_arb_mark_session_in_play - To put an reserved protected session to "in_play" state
+ * @pxp: pointer to pxp struct.
+ *
+ * Return: status. 0 means update is successful.
+ */
+static int intel_pxp_arb_mark_session_in_play(struct intel_pxp *pxp)
+{
+ struct pxp_protected_session *arb = pxp->ctx.arb_session;
+
+ lockdep_assert_held(&pxp->ctx.mutex);
+
+ if (arb->is_in_play)
+ return -EINVAL;
+
+ arb->is_in_play = true;
+ return 0;
+}
+
+int intel_pxp_arb_create_session(struct intel_pxp *pxp)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ lockdep_assert_held(&pxp->ctx.mutex);
+
+ if (pxp->ctx.flag_display_hm_surface_keys) {
+ drm_err(>->i915->drm, "%s: arb session is alive so skipping the creation\n",
+ __func__);
+ return 0;
+ }
+
+ ret = intel_pxp_arb_reserve_session(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to reserve arb session\n");
+ goto end;
+ }
+
+ ret = intel_pxp_tee_cmd_create_arb_session(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to send tee cmd for arb session creation\n");
+ goto end;
+ }
+
+ ret = intel_pxp_arb_mark_session_in_play(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to mark arb session status in play\n");
+ goto end;
+ }
+
+ pxp->ctx.flag_display_hm_surface_keys = true;
+
+end:
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
new file mode 100644
index 000000000000..e410c0bbdcc3
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_SM_H__
+#define __INTEL_PXP_SM_H__
+
+#include "intel_pxp.h"
+
+/**
+ * struct pxp_protected_session - structure to track all active sessions.
+ */
+struct pxp_protected_session {
+ /** @index: Numeric identifier for this protected session */
+ int index;
+ /** @type: Type of session */
+ int type;
+ /** @protection_mode: mode of protection requested */
+ int protection_mode;
+ /** @context_id: context identifier of the protected session requestor */
+ int context_id;
+
+ /**
+ * @is_in_play: indicates whether the session has been established
+ * in the HW root of trust if this flag is false, it
+ * indicates an application has reserved this session,
+ * but has not * established the session in the
+ * hardware yet.
+ */
+ bool is_in_play;
+};
+
+int intel_pxp_arb_create_session(struct intel_pxp *pxp);
+
+#endif /* __INTEL_PXP_SM_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
index 953a2e700931..e37125ed7434 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
@@ -13,7 +13,12 @@ struct pxp_context {
/** @mutex: mutex to protect the pxp context */
struct mutex mutex;
+ void *arb_session;
+ u32 arb_session_pxp_tag;
+
int id;
+
+ bool flag_display_hm_surface_keys;
};
void intel_pxp_ctx_init(struct pxp_context *ctx);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index ca6b61099aee..816a6d5a54e4 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -10,6 +10,7 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
#include "intel_pxp_tee.h"
+#include "intel_pxp_arb.h"
static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
void *msg_in, u32 msg_in_size,
@@ -70,7 +71,9 @@ static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
static int i915_pxp_tee_component_bind(struct device *i915_kdev,
struct device *tee_kdev, void *data)
{
+ int ret;
struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
+ struct intel_pxp *pxp = &i915->gt.pxp;
if (!i915 || !tee_kdev || !data)
return -EPERM;
@@ -80,6 +83,16 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev,
i915->pxp_tee_master->tee_dev = tee_kdev;
mutex_unlock(&i915->pxp_tee_comp_mutex);
+ mutex_lock(&pxp->ctx.mutex);
+ /* Create arb session only if tee is ready, during system boot or sleep/resume */
+ ret = intel_pxp_arb_create_session(pxp);
+ mutex_unlock(&pxp->ctx.mutex);
+
+ if (ret) {
+ drm_err(&i915->drm, "Failed to create arb session ret=[%d]\n", ret);
+ return ret;
+ }
+
return 0;
}
@@ -130,3 +143,28 @@ void intel_pxp_tee_component_fini(struct intel_pxp *pxp)
component_del(i915->drm.dev, &i915_pxp_tee_component_ops);
}
+
+int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp)
+{
+ int ret;
+ u32 msg_out_size_received = 0;
+ u32 msg_in[PXP_TEE_ARB_CMD_DW_LEN] = PXP_TEE_ARB_CMD_BIN;
+ u32 msg_out[PXP_TEE_ARB_CMD_DW_LEN] = {0};
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ struct drm_i915_private *i915 = gt->i915;
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+
+ ret = intel_pxp_tee_io_message(pxp,
+ &msg_in,
+ sizeof(msg_in),
+ &msg_out, &msg_out_size_received,
+ sizeof(msg_out));
+
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+
+ if (ret)
+ drm_err(&i915->drm, "Failed to send/receive tee message\n");
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
index 4b5e3edb1d9b..292fd2993a9a 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
@@ -11,4 +11,15 @@
void intel_pxp_tee_component_init(struct intel_pxp *pxp);
void intel_pxp_tee_component_fini(struct intel_pxp *pxp);
+int pxp_tee_ioctl_io_message(struct intel_pxp *pxp,
+ void __user *msg_in_user_ptr, u32 msg_in_size,
+ void __user *msg_out_user_ptr, u32 *msg_out_size_ptr,
+ u32 msg_out_buf_size);
+
+int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp);
+
+/* TEE command to create the arbitrary session */
+#define PXP_TEE_ARB_CMD_BIN {0x00040000, 0x0000001e, 0x00000000, 0x00000008, 0x00000002, 0x0000000f}
+#define PXP_TEE_ARB_CMD_DW_LEN (6)
+
#endif /* __INTEL_PXP_TEE_H__ */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [Intel-gfx] [RFC-v3 04/13] drm/i915/pxp: Create the arbitrary session after boot
2020-12-09 7:02 ` [Intel-gfx] [RFC-v3 04/13] drm/i915/pxp: Create the arbitrary session after boot Huang, Sean Z
@ 2020-12-09 9:58 ` kernel test robot
2020-12-10 10:42 ` Joonas Lahtinen
1 sibling, 0 replies; 34+ messages in thread
From: kernel test robot @ 2020-12-09 9:58 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 2261 bytes --]
Hi Sean,
[FYI, it's a private test report for your RFC patch.]
[auto build test WARNING on next-20201208]
[also build test WARNING on v5.10-rc7]
[cannot apply to drm-intel/for-linux-next char-misc/char-misc-testing v5.10-rc7 v5.10-rc6 v5.10-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Huang-Sean-Z/Introduce-Intel-PXP-component-Mesa-single-session/20201209-150546
base: a9e26cb5f2615cd638f911ea96d4fff5b4d93690
config: x86_64-allyesconfig (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce (this is a W=1 build):
# https://github.com/0day-ci/linux/commit/b7688bb5d268b7777bfef3a17d5cbde5e843e215
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Huang-Sean-Z/Introduce-Intel-PXP-component-Mesa-single-session/20201209-150546
git checkout b7688bb5d268b7777bfef3a17d5cbde5e843e215
# save the attached .config to linux build tree
make W=1 ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/pxp/intel_pxp_arb.c:80:5: warning: no previous prototype for 'intel_pxp_arb_reserve_session' [-Wmissing-prototypes]
80 | int intel_pxp_arb_reserve_session(struct intel_pxp *pxp)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
vim +/intel_pxp_arb_reserve_session +80 drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
79
> 80 int intel_pxp_arb_reserve_session(struct intel_pxp *pxp)
81 {
82 int ret;
83 struct pxp_protected_session *session = NULL;
84
85 lockdep_assert_held(&pxp->ctx.mutex);
86
87 ret = wait_arb_hw_sw_state(pxp);
88 if (ret)
89 return ret;
90
91 session = create_session_entry(pxp);
92 if (!session)
93 return -ENOMEM;
94
95 return ret;
96 }
97
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 78033 bytes --]
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [Intel-gfx] [RFC-v3 04/13] drm/i915/pxp: Create the arbitrary session after boot
2020-12-09 7:02 ` [Intel-gfx] [RFC-v3 04/13] drm/i915/pxp: Create the arbitrary session after boot Huang, Sean Z
2020-12-09 9:58 ` kernel test robot
@ 2020-12-10 10:42 ` Joonas Lahtinen
1 sibling, 0 replies; 34+ messages in thread
From: Joonas Lahtinen @ 2020-12-10 10:42 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
Quoting Huang, Sean Z (2020-12-09 09:02:58)
> Create the arbitrary session, with the fixed session id 0xf, after
> system boot, for the case that application allocates the protected
> buffer without establishing any protection session. Because the
> hardware requires at least one alive session for protected buffer
> creation. This arbitrary session needs to be re-created after
> teardown or power event because hardware encryption key won't be
> valid after such cases.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
<SNIP>
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -8,6 +8,22 @@
>
> #include "intel_pxp_context.h"
Again, needs split between _types.h for both included types and declared
types.
>
> +enum pxp_session_types {
> + SESSION_TYPE_TYPE0 = 0,
> + SESSION_TYPE_TYPE1 = 1,
> +
> + SESSION_TYPE_MAX
> +};
> +
> +enum pxp_protection_modes {
> + PROTECTION_MODE_NONE = 0,
> + PROTECTION_MODE_LM = 2,
> + PROTECTION_MODE_HM = 3,
> + PROTECTION_MODE_SM = 6,
> +
> + PROTECTION_MODE_ALL
> +};
> +
None of this should be relevant for the single-session operation.
> +static bool is_hw_arb_session_in_play(struct intel_pxp *pxp)
> +{
> + u32 regval_sip = 0;
No need to initialize.
> + intel_wakeref_t wakeref;
Should not be needed here.
> + struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
This would be at the top of the function ususally.
> +
> + with_intel_runtime_pm(>->i915->runtime_pm, wakeref) {
Repeating from previous review, these runtime checks should be hoisted to upper
level functions.
> + regval_sip = intel_uncore_read(gt->uncore, GEN12_KCR_SIP);
> + }
> +
> + return regval_sip & BIT(ARB_SESSION_INDEX);
This function should literally just be
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
u32 kcr_sip;
kcr_sip = intel_uncore_read(gt->uncore, GEN12_KCR_SIP);
return kcr_sip & BIT(ARB_SESSION_INDEX);
> +/* wait hw session_in_play reg to match the current sw state */
> +static int wait_arb_hw_sw_state(struct intel_pxp *pxp)
> +{
> + const int max_retry = 10;
> + const int ms_delay = 10;
> + int retry = 0;
> + int ret;
> + struct pxp_protected_session *arb = pxp->ctx.arb_session;
> +
> + ret = -EINVAL;
> + for (retry = 0; retry < max_retry; retry++) {
> + if (is_hw_arb_session_in_play(pxp) ==
> + arb->is_in_play) {
> + ret = 0;
> + break;
> + }
> +
> + msleep(ms_delay);
> + }
Again, this function should be rewritten utilize wait_for_* utils for
the single register we're checking.
So I think both of the above will then get merged into a single
local function:
static int wait_for_arb_session_in_play(struct intel_pxp *pxp)
> +/**
> + * create_session_entry - Create a new session entry with provided info.
> + * @pxp: pointer to pxp struct.
> + *
> + * Return: the pointer to the created session.
> + */
> +static struct pxp_protected_session *create_session_entry(struct intel_pxp *pxp)
> +{
> + struct pxp_protected_session *session;
> +
> + session = kzalloc(sizeof(*session), GFP_KERNEL);
> + if (!session)
> + return NULL;
We only have single session, we can embed it and avoid dynamic
allocation.
>>> FROM HERE
> + session->context_id = pxp->ctx.id;
> + session->type = ARB_SESSION_TYPE;
> + session->protection_mode = ARB_PROTECTION_MODE;
> + session->index = ARB_SESSION_INDEX;
> + session->is_in_play = false;
> +
> + return session;
> +}
> +
> +int intel_pxp_arb_reserve_session(struct intel_pxp *pxp)
> +{
> + int ret;
> + struct pxp_protected_session *session = NULL;
> +
> + lockdep_assert_held(&pxp->ctx.mutex);
> +
> + ret = wait_arb_hw_sw_state(pxp);
> + if (ret)
> + return ret;
> +
> + session = create_session_entry(pxp);
> + if (!session)
> + return -ENOMEM;
> +
> + return ret;
> +}
> +
> +/**
> + * intel_pxp_arb_mark_session_in_play - To put an reserved protected session to "in_play" state
> + * @pxp: pointer to pxp struct.
> + *
> + * Return: status. 0 means update is successful.
> + */
> +static int intel_pxp_arb_mark_session_in_play(struct intel_pxp *pxp)
> +{
> + struct pxp_protected_session *arb = pxp->ctx.arb_session;
> +
> + lockdep_assert_held(&pxp->ctx.mutex);
> +
> + if (arb->is_in_play)
> + return -EINVAL;
> +
> + arb->is_in_play = true;
> + return 0;
> +}
<<< UNTIL HERE
This is all just software tracking which we don't need for a single
session.
> +
> +int intel_pxp_arb_create_session(struct intel_pxp *pxp)
intel_pxp_arb_session()
> +{
> + int ret;
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> +
> + lockdep_assert_held(&pxp->ctx.mutex);
> +
> + if (pxp->ctx.flag_display_hm_surface_keys) {
> + drm_err(>->i915->drm, "%s: arb session is alive so skipping the creation\n",
> + __func__);
Wrong message level, this would be debug at most.
> + return 0;
> + }
> +
> + ret = intel_pxp_arb_reserve_session(pxp);
> + if (ret) {
> + drm_err(>->i915->drm, "Failed to reserve arb session\n");
> + goto end;
> + }
> +
> + ret = intel_pxp_tee_cmd_create_arb_session(pxp);
> + if (ret) {
> + drm_err(>->i915->drm, "Failed to send tee cmd for arb session creation\n");
> + goto end;
> + }
> +
> + ret = intel_pxp_arb_mark_session_in_play(pxp);
> + if (ret) {
> + drm_err(>->i915->drm, "Failed to mark arb session status in play\n");
> + goto end;
> + }
> +
> + pxp->ctx.flag_display_hm_surface_keys = true;
flag is tautology for bool variable, also this directly modifies ctx,
which should not be done from this level.
All I'm seeing for the init sequence is we send commands (currently in
binary BLOB) to the TEE hardware and wait for a bit to appear in
register.
So we should be able to do it as part of this function so that it's very
clear what is happening.
> +
> +end:
> + return ret;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
> new file mode 100644
> index 000000000000..e410c0bbdcc3
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
> @@ -0,0 +1,36 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_SM_H__
> +#define __INTEL_PXP_SM_H__
> +
> +#include "intel_pxp.h"
> +
> +/**
> + * struct pxp_protected_session - structure to track all active sessions.
> + */
> +struct pxp_protected_session {
> + /** @index: Numeric identifier for this protected session */
> + int index;
> + /** @type: Type of session */
> + int type;
> + /** @protection_mode: mode of protection requested */
> + int protection_mode;
> + /** @context_id: context identifier of the protected session requestor */
> + int context_id;
> +
> + /**
> + * @is_in_play: indicates whether the session has been established
> + * in the HW root of trust if this flag is false, it
> + * indicates an application has reserved this session,
> + * but has not * established the session in the
> + * hardware yet.
> + */
> + bool is_in_play;
None of this is needed.
We have the single session, and a way to check from hardware if that is
alive. No software tracking needed.
> +};
> +
> +int intel_pxp_arb_create_session(struct intel_pxp *pxp);
> +
> +#endif /* __INTEL_PXP_SM_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> index 953a2e700931..e37125ed7434 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> @@ -13,7 +13,12 @@ struct pxp_context {
> /** @mutex: mutex to protect the pxp context */
> struct mutex mutex;
>
> + void *arb_session;
void must not be used. I don't think this is needed.
> + u32 arb_session_pxp_tag;
This should not be needed either.
> +
> int id;
> +
> + bool flag_display_hm_surface_keys;
Same for this.
> };
>
> void intel_pxp_ctx_init(struct pxp_context *ctx);
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> index ca6b61099aee..816a6d5a54e4 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> @@ -10,6 +10,7 @@
> #include "intel_pxp.h"
> #include "intel_pxp_context.h"
> #include "intel_pxp_tee.h"
> +#include "intel_pxp_arb.h"
>
> static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
> void *msg_in, u32 msg_in_size,
> @@ -70,7 +71,9 @@ static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
> static int i915_pxp_tee_component_bind(struct device *i915_kdev,
> struct device *tee_kdev, void *data)
> {
> + int ret;
> struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
> + struct intel_pxp *pxp = &i915->gt.pxp;
>
> if (!i915 || !tee_kdev || !data)
> return -EPERM;
> @@ -80,6 +83,16 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev,
> i915->pxp_tee_master->tee_dev = tee_kdev;
> mutex_unlock(&i915->pxp_tee_comp_mutex);
>
> + mutex_lock(&pxp->ctx.mutex);
> + /* Create arb session only if tee is ready, during system boot or sleep/resume */
> + ret = intel_pxp_arb_create_session(pxp);
I don't think this is the right place to create the session. Especially
as with this series the component exposing was happening during early HW
init. So there is place for race conditions.
We should create the hardware session in i915 init sequences, otherwise
it might not be available to userspace and they would break.
> + mutex_unlock(&pxp->ctx.mutex);
> +
> + if (ret) {
> + drm_err(&i915->drm, "Failed to create arb session ret=[%d]\n", ret);
> + return ret;
> + }
> +
> return 0;
> }
>
> @@ -130,3 +143,28 @@ void intel_pxp_tee_component_fini(struct intel_pxp *pxp)
>
> component_del(i915->drm.dev, &i915_pxp_tee_component_ops);
> }
> +
> +int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp)
> +{
> + int ret;
> + u32 msg_out_size_received = 0;
> + u32 msg_in[PXP_TEE_ARB_CMD_DW_LEN] = PXP_TEE_ARB_CMD_BIN;
> + u32 msg_out[PXP_TEE_ARB_CMD_DW_LEN] = {0};
Looks like I guessed it wrong, it should have been u32 *in/out above.
That's exactly why void should be avoided.
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> + struct drm_i915_private *i915 = gt->i915;
> +
> + mutex_lock(&i915->pxp_tee_comp_mutex);
> +
> + ret = intel_pxp_tee_io_message(pxp,
> + &msg_in,
> + sizeof(msg_in),
> + &msg_out, &msg_out_size_received,
> + sizeof(msg_out));
The output seems to be completely discarded, but mandatory to recv. Is
there a return value of some sorts to know if there was something
preventing the creation?
Or is the expectation that we send these commands and then wait until
the hardware session is available according to the status register?
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> @@ -11,4 +11,15 @@
> void intel_pxp_tee_component_init(struct intel_pxp *pxp);
> void intel_pxp_tee_component_fini(struct intel_pxp *pxp);
>
> +int pxp_tee_ioctl_io_message(struct intel_pxp *pxp,
> + void __user *msg_in_user_ptr, u32 msg_in_size,
> + void __user *msg_out_user_ptr, u32 *msg_out_size_ptr,
> + u32 msg_out_buf_size);
I think this is misplaced hunk, we don't have IOCTL here.
> +
> +int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp);
This function is misplaced, it should be part of the intel_pxp_init
sequence to create the arb session. intel_pxp_tee is just the component
through which the communication happens.
> +/* TEE command to create the arbitrary session */
> +#define PXP_TEE_ARB_CMD_BIN {0x00040000, 0x0000001e, 0x00000000, 0x00000008, 0x00000002, 0x0000000f}
> +#define PXP_TEE_ARB_CMD_DW_LEN (6)
This is a binary BLOB and should not be in the kernel source code. This
either needs to be documented or moved elsewhere.
Regards, Joonas
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* [Intel-gfx] [RFC-v3 05/13] drm/i915/pxp: Func to send hardware session termination
2020-12-09 7:02 [Intel-gfx] [RFC-v3 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (3 preceding siblings ...)
2020-12-09 7:02 ` [Intel-gfx] [RFC-v3 04/13] drm/i915/pxp: Create the arbitrary session after boot Huang, Sean Z
@ 2020-12-09 7:02 ` Huang, Sean Z
2020-12-10 10:47 ` Joonas Lahtinen
2020-12-10 17:05 ` Jani Nikula
2020-12-09 7:03 ` [Intel-gfx] [RFC-v3 06/13] drm/i915/pxp: Enable PXP irq worker and callback stub Huang, Sean Z
` (10 subsequent siblings)
15 siblings, 2 replies; 34+ messages in thread
From: Huang, Sean Z @ 2020-12-09 7:02 UTC (permalink / raw)
To: Intel-gfx
Implement the functions to allow PXP to send a GPU command, in
order to terminate the hardware session, so hardware can recycle
this session slot for the next usage.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 156 +++++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 18 +++
3 files changed, 175 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0710cc522f38..2da904cda49f 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -258,6 +258,7 @@ i915-y += i915_perf.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_arb.o \
+ pxp/intel_pxp_cmd.o \
pxp/intel_pxp_context.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
new file mode 100644
index 000000000000..e531ea9f3cdc
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "intel_pxp_cmd.h"
+#include "i915_drv.h"
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+
+struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
+ struct intel_context *ce,
+ struct intel_gt_buffer_pool_node *pool,
+ u32 *cmd_buf, int cmd_size_in_dw)
+{
+ struct i915_vma *batch = ERR_PTR(-EINVAL);
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ u32 *cmd;
+
+ if (!ce || !ce->engine || !cmd_buf)
+ return ERR_PTR(-EINVAL);
+
+ if (cmd_size_in_dw * 4 > PAGE_SIZE) {
+ drm_err(>->i915->drm, "Failed to %s, invalid cmd_size_id_dw=[%d]\n",
+ __func__, cmd_size_in_dw);
+ return ERR_PTR(-EINVAL);
+ }
+
+ cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC);
+ if (IS_ERR(cmd)) {
+ drm_err(>->i915->drm, "Failed to i915_gem_object_pin_map()\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ memcpy(cmd, cmd_buf, cmd_size_in_dw * 4);
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw * 4, true);
+ }
+
+ i915_gem_object_unpin_map(pool->obj);
+
+ batch = i915_vma_instance(pool->obj, ce->vm, NULL);
+ if (IS_ERR(batch)) {
+ drm_err(>->i915->drm, "Failed to i915_vma_instance()\n");
+ return batch;
+ }
+
+ return batch;
+}
+
+int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw)
+{
+ int err = -EINVAL;
+ struct i915_vma *batch;
+ struct i915_request *rq;
+ struct intel_context *ce = NULL;
+ bool is_engine_pm_get = false;
+ bool is_batch_vma_pin = false;
+ bool is_skip_req_on_err = false;
+ bool is_engine_get_pool = false;
+ struct intel_gt_buffer_pool_node *pool = NULL;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+
+ if (!HAS_ENGINE(gt, VCS0) ||
+ !gt->engine[VCS0]->kernel_context) {
+ err = -EINVAL;
+ goto end;
+ }
+
+ if (!cmd || (cmd_size_in_dw * 4) > PAGE_SIZE) {
+ drm_err(>->i915->drm, "Failed to %s bad params\n", __func__);
+ return -EINVAL;
+ }
+
+ ce = gt->engine[VCS0]->kernel_context;
+
+ intel_engine_pm_get(ce->engine);
+ is_engine_pm_get = true;
+
+ pool = intel_gt_get_buffer_pool(gt, PAGE_SIZE);
+ if (IS_ERR(pool)) {
+ drm_err(>->i915->drm, "Failed to intel_engine_get_pool()\n");
+ goto end;
+ }
+ is_engine_get_pool = true;
+
+ batch = intel_pxp_cmd_get_batch(pxp, ce, pool, cmd, cmd_size_in_dw);
+ if (IS_ERR(batch)) {
+ drm_err(>->i915->drm, "Failed to intel_pxp_cmd_get_batch()\n");
+ goto end;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (err) {
+ drm_err(>->i915->drm, "Failed to i915_vma_pin()\n");
+ goto end;
+ }
+ is_batch_vma_pin = true;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ drm_err(>->i915->drm, "Failed to intel_context_create_request()\n");
+ goto end;
+ }
+ is_skip_req_on_err = true;
+
+ err = intel_gt_buffer_pool_mark_active(pool, rq);
+ if (err) {
+ drm_err(>->i915->drm, "Failed to intel_engine_pool_mark_active()\n");
+ goto end;
+ }
+
+ i915_vma_lock(batch);
+ err = i915_request_await_object(rq, batch->obj, false);
+ if (!err)
+ err = i915_vma_move_to_active(batch, rq, 0);
+ i915_vma_unlock(batch);
+ if (err) {
+ drm_err(>->i915->drm, "Failed to i915_request_await_object()\n");
+ goto end;
+ }
+
+ if (ce->engine->emit_init_breadcrumb) {
+ err = ce->engine->emit_init_breadcrumb(rq);
+ if (err) {
+ drm_err(>->i915->drm, "Failed to emit_init_breadcrumb()\n");
+ goto end;
+ }
+ }
+
+ err = ce->engine->emit_bb_start(rq, batch->node.start,
+ batch->node.size, 0);
+ if (err) {
+ drm_err(>->i915->drm, "Failed to emit_bb_start()\n");
+ goto end;
+ }
+
+ i915_request_add(rq);
+
+end:
+ if (unlikely(err) && is_skip_req_on_err)
+ i915_request_set_error_once(rq, err);
+
+ if (is_batch_vma_pin)
+ i915_vma_unpin(batch);
+
+ if (is_engine_get_pool)
+ intel_gt_buffer_pool_put(pool);
+
+ if (is_engine_pm_get)
+ intel_engine_pm_put(ce->engine);
+
+ return err;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
new file mode 100644
index 000000000000..d04463962421
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_CMD_H__
+#define __INTEL_PXP_CMD_H__
+
+#include "gt/intel_gt_buffer_pool.h"
+#include "intel_pxp.h"
+
+struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
+ struct intel_context *ce,
+ struct intel_gt_buffer_pool_node *pool,
+ u32 *cmd_buf, int cmd_size_in_dw);
+
+int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw);
+#endif /* __INTEL_PXP_SM_H__ */
--
2.17.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [Intel-gfx] [RFC-v3 05/13] drm/i915/pxp: Func to send hardware session termination
2020-12-09 7:02 ` [Intel-gfx] [RFC-v3 05/13] drm/i915/pxp: Func to send hardware session termination Huang, Sean Z
@ 2020-12-10 10:47 ` Joonas Lahtinen
2020-12-10 17:05 ` Jani Nikula
1 sibling, 0 replies; 34+ messages in thread
From: Joonas Lahtinen @ 2020-12-10 10:47 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
Quoting Huang, Sean Z (2020-12-09 09:02:59)
> Implement the functions to allow PXP to send a GPU command, in
> order to terminate the hardware session, so hardware can recycle
> this session slot for the next usage.
Just like for the ARB session creation must happen during i915
initialization in order to guarantee being available for userspace, we
must detect the corruption from i915 and i915 must be able to recreate
the session.
We already initiate the TEE commands to create the session, so I assume
we have to repeat those to recreate the session? Should not we
invalidate the previous session as part of that flow.
Any command to be sent to the command streamers that i915 is also
submitting to, should definitely happen under strict i915 control.
So we should include the session termination command in here, inside
i915 source.
Regards, Joonas
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 156 +++++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 18 +++
> 3 files changed, 175 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 0710cc522f38..2da904cda49f 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -258,6 +258,7 @@ i915-y += i915_perf.o
> i915-$(CONFIG_DRM_I915_PXP) += \
> pxp/intel_pxp.o \
> pxp/intel_pxp_arb.o \
> + pxp/intel_pxp_cmd.o \
> pxp/intel_pxp_context.o \
> pxp/intel_pxp_tee.o
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> new file mode 100644
> index 000000000000..e531ea9f3cdc
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> @@ -0,0 +1,156 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#include "intel_pxp_cmd.h"
> +#include "i915_drv.h"
> +#include "gt/intel_context.h"
> +#include "gt/intel_engine_pm.h"
> +
> +struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
> + struct intel_context *ce,
> + struct intel_gt_buffer_pool_node *pool,
> + u32 *cmd_buf, int cmd_size_in_dw)
> +{
> + struct i915_vma *batch = ERR_PTR(-EINVAL);
> + struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
> + u32 *cmd;
> +
> + if (!ce || !ce->engine || !cmd_buf)
> + return ERR_PTR(-EINVAL);
> +
> + if (cmd_size_in_dw * 4 > PAGE_SIZE) {
> + drm_err(>->i915->drm, "Failed to %s, invalid cmd_size_id_dw=[%d]\n",
> + __func__, cmd_size_in_dw);
> + return ERR_PTR(-EINVAL);
> + }
> +
> + cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC);
> + if (IS_ERR(cmd)) {
> + drm_err(>->i915->drm, "Failed to i915_gem_object_pin_map()\n");
> + return ERR_PTR(-EINVAL);
> + }
> +
> + memcpy(cmd, cmd_buf, cmd_size_in_dw * 4);
> +
> + if (drm_debug_enabled(DRM_UT_DRIVER)) {
> + print_hex_dump(KERN_DEBUG, "cmd binaries:",
> + DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw * 4, true);
> + }
> +
> + i915_gem_object_unpin_map(pool->obj);
> +
> + batch = i915_vma_instance(pool->obj, ce->vm, NULL);
> + if (IS_ERR(batch)) {
> + drm_err(>->i915->drm, "Failed to i915_vma_instance()\n");
> + return batch;
> + }
> +
> + return batch;
> +}
> +
> +int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw)
> +{
> + int err = -EINVAL;
> + struct i915_vma *batch;
> + struct i915_request *rq;
> + struct intel_context *ce = NULL;
> + bool is_engine_pm_get = false;
> + bool is_batch_vma_pin = false;
> + bool is_skip_req_on_err = false;
> + bool is_engine_get_pool = false;
> + struct intel_gt_buffer_pool_node *pool = NULL;
> + struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
> +
> + if (!HAS_ENGINE(gt, VCS0) ||
> + !gt->engine[VCS0]->kernel_context) {
> + err = -EINVAL;
> + goto end;
> + }
> +
> + if (!cmd || (cmd_size_in_dw * 4) > PAGE_SIZE) {
> + drm_err(>->i915->drm, "Failed to %s bad params\n", __func__);
> + return -EINVAL;
> + }
> +
> + ce = gt->engine[VCS0]->kernel_context;
> +
> + intel_engine_pm_get(ce->engine);
> + is_engine_pm_get = true;
> +
> + pool = intel_gt_get_buffer_pool(gt, PAGE_SIZE);
> + if (IS_ERR(pool)) {
> + drm_err(>->i915->drm, "Failed to intel_engine_get_pool()\n");
> + goto end;
> + }
> + is_engine_get_pool = true;
> +
> + batch = intel_pxp_cmd_get_batch(pxp, ce, pool, cmd, cmd_size_in_dw);
> + if (IS_ERR(batch)) {
> + drm_err(>->i915->drm, "Failed to intel_pxp_cmd_get_batch()\n");
> + goto end;
> + }
> +
> + err = i915_vma_pin(batch, 0, 0, PIN_USER);
> + if (err) {
> + drm_err(>->i915->drm, "Failed to i915_vma_pin()\n");
> + goto end;
> + }
> + is_batch_vma_pin = true;
> +
> + rq = intel_context_create_request(ce);
> + if (IS_ERR(rq)) {
> + drm_err(>->i915->drm, "Failed to intel_context_create_request()\n");
> + goto end;
> + }
> + is_skip_req_on_err = true;
> +
> + err = intel_gt_buffer_pool_mark_active(pool, rq);
> + if (err) {
> + drm_err(>->i915->drm, "Failed to intel_engine_pool_mark_active()\n");
> + goto end;
> + }
> +
> + i915_vma_lock(batch);
> + err = i915_request_await_object(rq, batch->obj, false);
> + if (!err)
> + err = i915_vma_move_to_active(batch, rq, 0);
> + i915_vma_unlock(batch);
> + if (err) {
> + drm_err(>->i915->drm, "Failed to i915_request_await_object()\n");
> + goto end;
> + }
> +
> + if (ce->engine->emit_init_breadcrumb) {
> + err = ce->engine->emit_init_breadcrumb(rq);
> + if (err) {
> + drm_err(>->i915->drm, "Failed to emit_init_breadcrumb()\n");
> + goto end;
> + }
> + }
> +
> + err = ce->engine->emit_bb_start(rq, batch->node.start,
> + batch->node.size, 0);
> + if (err) {
> + drm_err(>->i915->drm, "Failed to emit_bb_start()\n");
> + goto end;
> + }
> +
> + i915_request_add(rq);
> +
> +end:
> + if (unlikely(err) && is_skip_req_on_err)
> + i915_request_set_error_once(rq, err);
> +
> + if (is_batch_vma_pin)
> + i915_vma_unpin(batch);
> +
> + if (is_engine_get_pool)
> + intel_gt_buffer_pool_put(pool);
> +
> + if (is_engine_pm_get)
> + intel_engine_pm_put(ce->engine);
> +
> + return err;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
> new file mode 100644
> index 000000000000..d04463962421
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
> @@ -0,0 +1,18 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_CMD_H__
> +#define __INTEL_PXP_CMD_H__
> +
> +#include "gt/intel_gt_buffer_pool.h"
> +#include "intel_pxp.h"
> +
> +struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
> + struct intel_context *ce,
> + struct intel_gt_buffer_pool_node *pool,
> + u32 *cmd_buf, int cmd_size_in_dw);
> +
> +int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw);
> +#endif /* __INTEL_PXP_SM_H__ */
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [Intel-gfx] [RFC-v3 05/13] drm/i915/pxp: Func to send hardware session termination
2020-12-09 7:02 ` [Intel-gfx] [RFC-v3 05/13] drm/i915/pxp: Func to send hardware session termination Huang, Sean Z
2020-12-10 10:47 ` Joonas Lahtinen
@ 2020-12-10 17:05 ` Jani Nikula
1 sibling, 0 replies; 34+ messages in thread
From: Jani Nikula @ 2020-12-10 17:05 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
On Tue, 08 Dec 2020, "Huang, Sean Z" <sean.z.huang@intel.com> wrote:
> Implement the functions to allow PXP to send a GPU command, in
> order to terminate the hardware session, so hardware can recycle
> this session slot for the next usage.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 156 +++++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 18 +++
> 3 files changed, 175 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 0710cc522f38..2da904cda49f 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -258,6 +258,7 @@ i915-y += i915_perf.o
> i915-$(CONFIG_DRM_I915_PXP) += \
> pxp/intel_pxp.o \
> pxp/intel_pxp_arb.o \
> + pxp/intel_pxp_cmd.o \
> pxp/intel_pxp_context.o \
> pxp/intel_pxp_tee.o
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> new file mode 100644
> index 000000000000..e531ea9f3cdc
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> @@ -0,0 +1,156 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#include "intel_pxp_cmd.h"
> +#include "i915_drv.h"
> +#include "gt/intel_context.h"
> +#include "gt/intel_engine_pm.h"
> +
> +struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
> + struct intel_context *ce,
> + struct intel_gt_buffer_pool_node *pool,
> + u32 *cmd_buf, int cmd_size_in_dw)
> +{
> + struct i915_vma *batch = ERR_PTR(-EINVAL);
> + struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
> + u32 *cmd;
> +
> + if (!ce || !ce->engine || !cmd_buf)
> + return ERR_PTR(-EINVAL);
> +
> + if (cmd_size_in_dw * 4 > PAGE_SIZE) {
> + drm_err(>->i915->drm, "Failed to %s, invalid cmd_size_id_dw=[%d]\n",
> + __func__, cmd_size_in_dw);
> + return ERR_PTR(-EINVAL);
> + }
> +
> + cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC);
> + if (IS_ERR(cmd)) {
> + drm_err(>->i915->drm, "Failed to i915_gem_object_pin_map()\n");
> + return ERR_PTR(-EINVAL);
> + }
> +
> + memcpy(cmd, cmd_buf, cmd_size_in_dw * 4);
> +
> + if (drm_debug_enabled(DRM_UT_DRIVER)) {
> + print_hex_dump(KERN_DEBUG, "cmd binaries:",
> + DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw * 4, true);
> + }
> +
> + i915_gem_object_unpin_map(pool->obj);
> +
> + batch = i915_vma_instance(pool->obj, ce->vm, NULL);
> + if (IS_ERR(batch)) {
> + drm_err(>->i915->drm, "Failed to i915_vma_instance()\n");
> + return batch;
> + }
> +
> + return batch;
> +}
> +
> +int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw)
> +{
> + int err = -EINVAL;
> + struct i915_vma *batch;
> + struct i915_request *rq;
> + struct intel_context *ce = NULL;
> + bool is_engine_pm_get = false;
> + bool is_batch_vma_pin = false;
> + bool is_skip_req_on_err = false;
> + bool is_engine_get_pool = false;
> + struct intel_gt_buffer_pool_node *pool = NULL;
> + struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
> +
> + if (!HAS_ENGINE(gt, VCS0) ||
> + !gt->engine[VCS0]->kernel_context) {
> + err = -EINVAL;
> + goto end;
> + }
> +
> + if (!cmd || (cmd_size_in_dw * 4) > PAGE_SIZE) {
> + drm_err(>->i915->drm, "Failed to %s bad params\n", __func__);
> + return -EINVAL;
> + }
> +
> + ce = gt->engine[VCS0]->kernel_context;
> +
> + intel_engine_pm_get(ce->engine);
> + is_engine_pm_get = true;
> +
> + pool = intel_gt_get_buffer_pool(gt, PAGE_SIZE);
> + if (IS_ERR(pool)) {
> + drm_err(>->i915->drm, "Failed to intel_engine_get_pool()\n");
> + goto end;
> + }
> + is_engine_get_pool = true;
> +
> + batch = intel_pxp_cmd_get_batch(pxp, ce, pool, cmd, cmd_size_in_dw);
> + if (IS_ERR(batch)) {
> + drm_err(>->i915->drm, "Failed to intel_pxp_cmd_get_batch()\n");
> + goto end;
> + }
> +
> + err = i915_vma_pin(batch, 0, 0, PIN_USER);
> + if (err) {
> + drm_err(>->i915->drm, "Failed to i915_vma_pin()\n");
> + goto end;
> + }
> + is_batch_vma_pin = true;
> +
> + rq = intel_context_create_request(ce);
> + if (IS_ERR(rq)) {
> + drm_err(>->i915->drm, "Failed to intel_context_create_request()\n");
> + goto end;
> + }
> + is_skip_req_on_err = true;
> +
> + err = intel_gt_buffer_pool_mark_active(pool, rq);
> + if (err) {
> + drm_err(>->i915->drm, "Failed to intel_engine_pool_mark_active()\n");
> + goto end;
> + }
> +
> + i915_vma_lock(batch);
> + err = i915_request_await_object(rq, batch->obj, false);
> + if (!err)
> + err = i915_vma_move_to_active(batch, rq, 0);
> + i915_vma_unlock(batch);
> + if (err) {
> + drm_err(>->i915->drm, "Failed to i915_request_await_object()\n");
> + goto end;
> + }
> +
> + if (ce->engine->emit_init_breadcrumb) {
> + err = ce->engine->emit_init_breadcrumb(rq);
> + if (err) {
> + drm_err(>->i915->drm, "Failed to emit_init_breadcrumb()\n");
> + goto end;
> + }
> + }
> +
> + err = ce->engine->emit_bb_start(rq, batch->node.start,
> + batch->node.size, 0);
> + if (err) {
> + drm_err(>->i915->drm, "Failed to emit_bb_start()\n");
> + goto end;
> + }
> +
> + i915_request_add(rq);
> +
> +end:
> + if (unlikely(err) && is_skip_req_on_err)
Please avoid using likely/unlikely unless performance really matters
*and* you know it matters.
Usually error handling is done via labels where you goto, not via a
plethora of booleans.
BR,
Jani.
> + i915_request_set_error_once(rq, err);
> +
> + if (is_batch_vma_pin)
> + i915_vma_unpin(batch);
> +
> + if (is_engine_get_pool)
> + intel_gt_buffer_pool_put(pool);
> +
> + if (is_engine_pm_get)
> + intel_engine_pm_put(ce->engine);
> +
> + return err;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
> new file mode 100644
> index 000000000000..d04463962421
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
> @@ -0,0 +1,18 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_CMD_H__
> +#define __INTEL_PXP_CMD_H__
> +
> +#include "gt/intel_gt_buffer_pool.h"
> +#include "intel_pxp.h"
> +
> +struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
> + struct intel_context *ce,
> + struct intel_gt_buffer_pool_node *pool,
> + u32 *cmd_buf, int cmd_size_in_dw);
> +
> +int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw);
> +#endif /* __INTEL_PXP_SM_H__ */
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* [Intel-gfx] [RFC-v3 06/13] drm/i915/pxp: Enable PXP irq worker and callback stub
2020-12-09 7:02 [Intel-gfx] [RFC-v3 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (4 preceding siblings ...)
2020-12-09 7:02 ` [Intel-gfx] [RFC-v3 05/13] drm/i915/pxp: Func to send hardware session termination Huang, Sean Z
@ 2020-12-09 7:03 ` Huang, Sean Z
2020-12-10 11:02 ` Joonas Lahtinen
2020-12-10 17:06 ` Jani Nikula
2020-12-09 7:03 ` [Intel-gfx] [RFC-v3 07/13] drm/i915/pxp: Destroy arb session upon teardown Huang, Sean Z
` (9 subsequent siblings)
15 siblings, 2 replies; 34+ messages in thread
From: Huang, Sean Z @ 2020-12-09 7:03 UTC (permalink / raw)
To: Intel-gfx
Create the irq worker that serves as callback handler, those
callback stubs should be called while the hardware key teardown
occurs.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 4 +
drivers/gpu/drm/i915/i915_reg.h | 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 101 +++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 27 +++++
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 2 +
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 +
6 files changed, 137 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 257063a57101..fbe9ef88b905 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -13,6 +13,7 @@
#include "intel_gt_irq.h"
#include "intel_uncore.h"
#include "intel_rps.h"
+#include "pxp/intel_pxp.h"
static void guc_irq_handler(struct intel_guc *guc, u16 iir)
{
@@ -106,6 +107,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(>->rps, iir);
+ if (instance == OTHER_KCR_INSTANCE)
+ return intel_pxp_irq_handler(>->pxp, iir);
+
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0023c023f472..1e8dfe435ca8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7944,6 +7944,7 @@ enum {
/* irq instances for OTHER_CLASS */
#define OTHER_GUC_INSTANCE 0
#define OTHER_GTPM_INSTANCE 1
+#define OTHER_KCR_INSTANCE 4
#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
@@ -7966,7 +7967,7 @@ enum {
#define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
#define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
-#define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
+#define GEN11_CRYPTO_INTR_MASK _MMIO(0x1900f0) /* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */
#define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
#define ENGINE1_MASK REG_GENMASK(31, 16)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 67bdaeb79b40..9bcb170b34f1 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -14,6 +14,70 @@
/* Setting KCR Init bit is required after system boot */
#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << KCR_INIT_MASK_SHIFT))
+static void intel_pxp_write_irq_mask_reg(struct intel_gt *gt, u32 mask)
+{
+ lockdep_assert_held(>->irq_lock);
+
+ intel_uncore_write(gt->uncore, GEN11_CRYPTO_INTR_MASK, mask << 16);
+}
+
+static int intel_pxp_teardown_required_callback(struct intel_pxp *pxp)
+{
+ int ret;
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ pxp->ctx.global_state_attacked = true;
+
+ mutex_unlock(&pxp->ctx.mutex);
+
+ return ret;
+}
+
+static int intel_pxp_global_terminate_complete_callback(struct intel_pxp *pxp)
+{
+ int ret = 0;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ if (pxp->ctx.global_state_attacked) {
+ pxp->ctx.global_state_attacked = false;
+
+ /* Re-create the arb session after teardown handle complete */
+ ret = intel_pxp_arb_create_session(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to create arb session\n");
+ goto end;
+ }
+ }
+end:
+ mutex_unlock(&pxp->ctx.mutex);
+ return ret;
+}
+
+static void intel_pxp_irq_work(struct work_struct *work)
+{
+ struct intel_pxp *pxp = container_of(work, typeof(*pxp), irq_work);
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+ u32 events = 0;
+
+ spin_lock_irq(>->irq_lock);
+ events = fetch_and_zero(&pxp->current_events);
+ spin_unlock_irq(>->irq_lock);
+
+ if (events & PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED ||
+ events & PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ)
+ intel_pxp_teardown_required_callback(pxp);
+
+ if (events & PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE)
+ intel_pxp_global_terminate_complete_callback(pxp);
+
+ spin_lock_irq(>->irq_lock);
+ intel_pxp_write_irq_mask_reg(gt, 0);
+ spin_unlock_irq(>->irq_lock);
+}
+
int intel_pxp_init(struct intel_pxp *pxp)
{
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
@@ -28,6 +92,12 @@ int intel_pxp_init(struct intel_pxp *pxp)
intel_pxp_tee_component_init(pxp);
+ INIT_WORK(&pxp->irq_work, intel_pxp_irq_work);
+
+ pxp->handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
+ PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ |
+ PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE);
+
drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
return 0;
@@ -39,3 +109,34 @@ void intel_pxp_uninit(struct intel_pxp *pxp)
intel_pxp_ctx_fini(&pxp->ctx);
}
+
+/**
+ * intel_pxp_irq_handler - Proxies KCR interrupts to PXP.
+ * @pxp: pointer to pxp struct
+ * @iir: GT interrupt vector associated with the interrupt
+ *
+ * Dispatches each vector element into an IRQ to PXP.
+ */
+void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
+{
+ struct drm_i915_private *i915;
+ const u32 events = iir & pxp->handled_irr;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ if (!gt || !gt->i915 || INTEL_GEN(i915) < 12)
+ return;
+
+ i915 = gt->i915;
+
+ lockdep_assert_held(>->irq_lock);
+
+ if (unlikely(!events)) {
+ drm_err(&i915->drm, "%s returned due to iir=[0x%04x]\n", __func__, iir);
+ return;
+ }
+
+ intel_pxp_write_irq_mask_reg(gt, pxp->handled_irr);
+
+ pxp->current_events |= events;
+ schedule_work(&pxp->irq_work);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 406d35f402a6..c8c580cee5bc 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -6,8 +6,13 @@
#ifndef __INTEL_PXP_H__
#define __INTEL_PXP_H__
+#include <linux/workqueue.h>
#include "intel_pxp_context.h"
+#define PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED BIT(1)
+#define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2)
+#define PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
+
enum pxp_session_types {
SESSION_TYPE_TYPE0 = 0,
SESSION_TYPE_TYPE1 = 1,
@@ -25,14 +30,36 @@ enum pxp_protection_modes {
};
struct intel_pxp {
+ struct work_struct irq_work;
+ u32 handled_irr;
+ u32 current_events;
+
struct pxp_context ctx;
};
#ifdef CONFIG_DRM_I915_PXP
+void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir);
+int i915_pxp_teardown_required_callback(struct intel_pxp *pxp);
+int i915_pxp_global_terminate_complete_callback(struct intel_pxp *pxp);
+
int intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_uninit(struct intel_pxp *pxp);
int intel_pxp_reg_read(struct intel_pxp *pxp, u32 offset, u32 *regval);
#else
+static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
+{
+}
+
+static inline int i915_pxp_teardown_required_callback(struct intel_pxp *pxp)
+{
+ return 0;
+}
+
+static inline int i915_pxp_global_terminate_complete_callback(struct intel_pxp *pxp)
+{
+ return 0;
+}
+
static inline int intel_pxp_init(struct intel_pxp *pxp)
{
return 0;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
index 5ffaf55dc7df..d00f4e0b88ba 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
@@ -14,6 +14,8 @@ void intel_pxp_ctx_init(struct pxp_context *ctx)
{
get_random_bytes(&ctx->id, sizeof(ctx->id));
+ ctx->global_state_attacked = false;
+
mutex_init(&ctx->mutex);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
index e37125ed7434..62a2504b33bf 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
@@ -18,6 +18,7 @@ struct pxp_context {
int id;
+ bool global_state_attacked;
bool flag_display_hm_surface_keys;
};
--
2.17.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [Intel-gfx] [RFC-v3 06/13] drm/i915/pxp: Enable PXP irq worker and callback stub
2020-12-09 7:03 ` [Intel-gfx] [RFC-v3 06/13] drm/i915/pxp: Enable PXP irq worker and callback stub Huang, Sean Z
@ 2020-12-10 11:02 ` Joonas Lahtinen
2020-12-10 17:06 ` Jani Nikula
1 sibling, 0 replies; 34+ messages in thread
From: Joonas Lahtinen @ 2020-12-10 11:02 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
Quoting Huang, Sean Z (2020-12-09 09:03:00)
> Create the irq worker that serves as callback handler, those
> callback stubs should be called while the hardware key teardown
> occurs.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
<SNIP>
> +static int intel_pxp_global_terminate_complete_callback(struct intel_pxp *pxp)
> +{
> + int ret = 0;
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> +
> + mutex_lock(&pxp->ctx.mutex);
> +
> + if (pxp->ctx.global_state_attacked) {
> + pxp->ctx.global_state_attacked = false;
This software tracking should not be needed.
> +
> + /* Re-create the arb session after teardown handle complete */
> + ret = intel_pxp_arb_create_session(pxp);
> + if (ret) {
> + drm_err(>->i915->drm, "Failed to create arb session\n");
> + goto end;
> + }
> + }
> +end:
> + mutex_unlock(&pxp->ctx.mutex);
> + return ret;
> +}
> +
> +static void intel_pxp_irq_work(struct work_struct *work)
> +{
> + struct intel_pxp *pxp = container_of(work, typeof(*pxp), irq_work);
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> + u32 events = 0;
> +
> + spin_lock_irq(>->irq_lock);
> + events = fetch_and_zero(&pxp->current_events);
"current_events" is not a great name for variable to be handled by
irq_work function.
> + spin_unlock_irq(>->irq_lock);
> +
> + if (events & PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED ||
> + events & PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ)
> + intel_pxp_teardown_required_callback(pxp);
On this path we should go and invalidate all contexts and buffer objects
that are created with PROTECTED_CONTENT flag.
We should only track the lack of the single session, and hold off from
submitting any newly created contexts until the next event.
> +
> + if (events & PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE)
> + intel_pxp_global_terminate_complete_callback(pxp);
After this, we should be able to proceed with creation/usage of
PROTECTED_CONTENT flagged items as the session is available.
I only see the session being created and other software tracking I'm not
following exactly.
So the only boolean state we should track is if the arb_session is valid
or is "in play" as the terminology seems to be.
Regards, Joonas
> +
> + spin_lock_irq(>->irq_lock);
> + intel_pxp_write_irq_mask_reg(gt, 0);
> + spin_unlock_irq(>->irq_lock);
> +}
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [Intel-gfx] [RFC-v3 06/13] drm/i915/pxp: Enable PXP irq worker and callback stub
2020-12-09 7:03 ` [Intel-gfx] [RFC-v3 06/13] drm/i915/pxp: Enable PXP irq worker and callback stub Huang, Sean Z
2020-12-10 11:02 ` Joonas Lahtinen
@ 2020-12-10 17:06 ` Jani Nikula
1 sibling, 0 replies; 34+ messages in thread
From: Jani Nikula @ 2020-12-10 17:06 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
On Tue, 08 Dec 2020, "Huang, Sean Z" <sean.z.huang@intel.com> wrote:
> Create the irq worker that serves as callback handler, those
> callback stubs should be called while the hardware key teardown
> occurs.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 4 +
> drivers/gpu/drm/i915/i915_reg.h | 3 +-
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 101 +++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 27 +++++
> drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 2 +
> drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 +
> 6 files changed, 137 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index 257063a57101..fbe9ef88b905 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -13,6 +13,7 @@
> #include "intel_gt_irq.h"
> #include "intel_uncore.h"
> #include "intel_rps.h"
> +#include "pxp/intel_pxp.h"
>
> static void guc_irq_handler(struct intel_guc *guc, u16 iir)
> {
> @@ -106,6 +107,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
> if (instance == OTHER_GTPM_INSTANCE)
> return gen11_rps_irq_handler(>->rps, iir);
>
> + if (instance == OTHER_KCR_INSTANCE)
> + return intel_pxp_irq_handler(>->pxp, iir);
> +
> WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
> instance, iir);
> }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0023c023f472..1e8dfe435ca8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7944,6 +7944,7 @@ enum {
> /* irq instances for OTHER_CLASS */
> #define OTHER_GUC_INSTANCE 0
> #define OTHER_GTPM_INSTANCE 1
> +#define OTHER_KCR_INSTANCE 4
>
> #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
>
> @@ -7966,7 +7967,7 @@ enum {
> #define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
> #define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
> #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
> -#define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
> +#define GEN11_CRYPTO_INTR_MASK _MMIO(0x1900f0) /* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */
> #define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
>
> #define ENGINE1_MASK REG_GENMASK(31, 16)
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 67bdaeb79b40..9bcb170b34f1 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -14,6 +14,70 @@
> /* Setting KCR Init bit is required after system boot */
> #define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << KCR_INIT_MASK_SHIFT))
>
> +static void intel_pxp_write_irq_mask_reg(struct intel_gt *gt, u32 mask)
> +{
> + lockdep_assert_held(>->irq_lock);
> +
> + intel_uncore_write(gt->uncore, GEN11_CRYPTO_INTR_MASK, mask << 16);
> +}
> +
> +static int intel_pxp_teardown_required_callback(struct intel_pxp *pxp)
> +{
> + int ret;
> +
> + mutex_lock(&pxp->ctx.mutex);
> +
> + pxp->ctx.global_state_attacked = true;
> +
> + mutex_unlock(&pxp->ctx.mutex);
> +
> + return ret;
ret is uninitialized here, please just return 0.
BR,
Jani
> +}
> +
> +static int intel_pxp_global_terminate_complete_callback(struct intel_pxp *pxp)
> +{
> + int ret = 0;
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> +
> + mutex_lock(&pxp->ctx.mutex);
> +
> + if (pxp->ctx.global_state_attacked) {
> + pxp->ctx.global_state_attacked = false;
> +
> + /* Re-create the arb session after teardown handle complete */
> + ret = intel_pxp_arb_create_session(pxp);
> + if (ret) {
> + drm_err(>->i915->drm, "Failed to create arb session\n");
> + goto end;
> + }
> + }
> +end:
> + mutex_unlock(&pxp->ctx.mutex);
> + return ret;
> +}
> +
> +static void intel_pxp_irq_work(struct work_struct *work)
> +{
> + struct intel_pxp *pxp = container_of(work, typeof(*pxp), irq_work);
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> + u32 events = 0;
> +
> + spin_lock_irq(>->irq_lock);
> + events = fetch_and_zero(&pxp->current_events);
> + spin_unlock_irq(>->irq_lock);
> +
> + if (events & PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED ||
> + events & PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ)
> + intel_pxp_teardown_required_callback(pxp);
> +
> + if (events & PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE)
> + intel_pxp_global_terminate_complete_callback(pxp);
> +
> + spin_lock_irq(>->irq_lock);
> + intel_pxp_write_irq_mask_reg(gt, 0);
> + spin_unlock_irq(>->irq_lock);
> +}
> +
> int intel_pxp_init(struct intel_pxp *pxp)
> {
> struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
> @@ -28,6 +92,12 @@ int intel_pxp_init(struct intel_pxp *pxp)
>
> intel_pxp_tee_component_init(pxp);
>
> + INIT_WORK(&pxp->irq_work, intel_pxp_irq_work);
> +
> + pxp->handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
> + PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ |
> + PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE);
> +
> drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
>
> return 0;
> @@ -39,3 +109,34 @@ void intel_pxp_uninit(struct intel_pxp *pxp)
>
> intel_pxp_ctx_fini(&pxp->ctx);
> }
> +
> +/**
> + * intel_pxp_irq_handler - Proxies KCR interrupts to PXP.
> + * @pxp: pointer to pxp struct
> + * @iir: GT interrupt vector associated with the interrupt
> + *
> + * Dispatches each vector element into an IRQ to PXP.
> + */
> +void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
> +{
> + struct drm_i915_private *i915;
> + const u32 events = iir & pxp->handled_irr;
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> +
> + if (!gt || !gt->i915 || INTEL_GEN(i915) < 12)
> + return;
> +
> + i915 = gt->i915;
> +
> + lockdep_assert_held(>->irq_lock);
> +
> + if (unlikely(!events)) {
> + drm_err(&i915->drm, "%s returned due to iir=[0x%04x]\n", __func__, iir);
> + return;
> + }
> +
> + intel_pxp_write_irq_mask_reg(gt, pxp->handled_irr);
> +
> + pxp->current_events |= events;
> + schedule_work(&pxp->irq_work);
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index 406d35f402a6..c8c580cee5bc 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -6,8 +6,13 @@
> #ifndef __INTEL_PXP_H__
> #define __INTEL_PXP_H__
>
> +#include <linux/workqueue.h>
> #include "intel_pxp_context.h"
>
> +#define PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED BIT(1)
> +#define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2)
> +#define PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
> +
> enum pxp_session_types {
> SESSION_TYPE_TYPE0 = 0,
> SESSION_TYPE_TYPE1 = 1,
> @@ -25,14 +30,36 @@ enum pxp_protection_modes {
> };
>
> struct intel_pxp {
> + struct work_struct irq_work;
> + u32 handled_irr;
> + u32 current_events;
> +
> struct pxp_context ctx;
> };
>
> #ifdef CONFIG_DRM_I915_PXP
> +void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir);
> +int i915_pxp_teardown_required_callback(struct intel_pxp *pxp);
> +int i915_pxp_global_terminate_complete_callback(struct intel_pxp *pxp);
> +
> int intel_pxp_init(struct intel_pxp *pxp);
> void intel_pxp_uninit(struct intel_pxp *pxp);
> int intel_pxp_reg_read(struct intel_pxp *pxp, u32 offset, u32 *regval);
> #else
> +static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
> +{
> +}
> +
> +static inline int i915_pxp_teardown_required_callback(struct intel_pxp *pxp)
> +{
> + return 0;
> +}
> +
> +static inline int i915_pxp_global_terminate_complete_callback(struct intel_pxp *pxp)
> +{
> + return 0;
> +}
> +
> static inline int intel_pxp_init(struct intel_pxp *pxp)
> {
> return 0;
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> index 5ffaf55dc7df..d00f4e0b88ba 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> @@ -14,6 +14,8 @@ void intel_pxp_ctx_init(struct pxp_context *ctx)
> {
> get_random_bytes(&ctx->id, sizeof(ctx->id));
>
> + ctx->global_state_attacked = false;
> +
> mutex_init(&ctx->mutex);
> }
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> index e37125ed7434..62a2504b33bf 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> @@ -18,6 +18,7 @@ struct pxp_context {
>
> int id;
>
> + bool global_state_attacked;
> bool flag_display_hm_surface_keys;
> };
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* [Intel-gfx] [RFC-v3 07/13] drm/i915/pxp: Destroy arb session upon teardown
2020-12-09 7:02 [Intel-gfx] [RFC-v3 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (5 preceding siblings ...)
2020-12-09 7:03 ` [Intel-gfx] [RFC-v3 06/13] drm/i915/pxp: Enable PXP irq worker and callback stub Huang, Sean Z
@ 2020-12-09 7:03 ` Huang, Sean Z
2020-12-10 10:51 ` Joonas Lahtinen
2020-12-09 7:03 ` [Intel-gfx] [RFC-v3 08/13] drm/i915/pxp: Enable PXP power management Huang, Sean Z
` (8 subsequent siblings)
15 siblings, 1 reply; 34+ messages in thread
From: Huang, Sean Z @ 2020-12-09 7:03 UTC (permalink / raw)
To: Intel-gfx
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. So as a result, PXP should
handle such case and terminate the type0 sessions, which including
arb session
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 76 +++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 129 ++++++++++++++++++++++-
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 12 ++-
5 files changed, 211 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 9bcb170b34f1..48e926363696 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -28,6 +28,9 @@ static int intel_pxp_teardown_required_callback(struct intel_pxp *pxp)
mutex_lock(&pxp->ctx.mutex);
pxp->ctx.global_state_attacked = true;
+ pxp->ctx.flag_display_hm_surface_keys = false;
+
+ ret = intel_pxp_arb_terminate_session(pxp);
mutex_unlock(&pxp->ctx.mutex);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
index c1ad45b83478..09148ca9035c 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
@@ -10,6 +10,7 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
#include "intel_pxp_tee.h"
+#include "intel_pxp_cmd.h"
#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-31 */
@@ -150,3 +151,78 @@ int intel_pxp_arb_create_session(struct intel_pxp *pxp)
end:
return ret;
}
+
+static int intel_pxp_arb_session_with_global_termination(struct intel_pxp *pxp)
+{
+ u32 *cmd = NULL;
+ u32 *cmd_ptr = NULL;
+ int cmd_size_in_dw = 0;
+ int ret;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ /* Calculate how many bytes need to be alloc */
+ cmd_size_in_dw += intel_pxp_cmd_add_prolog(pxp, NULL, ARB_SESSION_TYPE, ARB_SESSION_INDEX);
+ cmd_size_in_dw += intel_pxp_cmd_add_inline_termination(NULL);
+ cmd_size_in_dw += intel_pxp_cmd_add_epilog(NULL);
+
+ cmd = kzalloc(cmd_size_in_dw * 4, GFP_KERNEL);
+ if (!cmd)
+ return -ENOMEM;
+
+ /* Program the command */
+ cmd_ptr = cmd;
+ cmd_ptr += intel_pxp_cmd_add_prolog(pxp, cmd_ptr, ARB_SESSION_TYPE, ARB_SESSION_INDEX);
+ cmd_ptr += intel_pxp_cmd_add_inline_termination(cmd_ptr);
+ cmd_ptr += intel_pxp_cmd_add_epilog(cmd_ptr);
+
+ if (cmd_size_in_dw != (cmd_ptr - cmd)) {
+ ret = -EINVAL;
+ drm_err(>->i915->drm, "Failed to %s\n", __func__);
+ goto end;
+ }
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "global termination cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw * 4, true);
+ }
+
+ ret = intel_pxp_cmd_submit(pxp, cmd, cmd_size_in_dw);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to intel_pxp_cmd_submit()\n");
+ goto end;
+ }
+
+end:
+ kfree(cmd);
+ return ret;
+}
+
+/**
+ * intel_pxp_arb_terminate_session - Terminate the arb hw session and its entries.
+ * @pxp: pointer to pxp struct.
+ *
+ * This function is NOT intended to be called from the ioctl, and need to be protected by
+ * ctx.mutex to ensure no SIP change during the call.
+ *
+ * Return: status. 0 means terminate is successful.
+ */
+int intel_pxp_arb_terminate_session(struct intel_pxp *pxp)
+{
+ int ret;
+ struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
+ struct pxp_protected_session *arb = pxp->ctx.arb_session;
+
+ lockdep_assert_held(&pxp->ctx.mutex);
+
+ /* terminate the hw sessions */
+ ret = intel_pxp_arb_session_with_global_termination(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to intel_pxp_arb_session_with_global_termination\n");
+ return ret;
+ }
+
+ kfree(arb);
+
+ return ret;
+}
+
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
index e410c0bbdcc3..d7b3b05a4314 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
@@ -32,5 +32,6 @@ struct pxp_protected_session {
};
int intel_pxp_arb_create_session(struct intel_pxp *pxp);
+int intel_pxp_arb_terminate_session(struct intel_pxp *pxp);
#endif /* __INTEL_PXP_SM_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
index e531ea9f3cdc..f122c9a1f78e 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -8,10 +8,29 @@
#include "gt/intel_context.h"
#include "gt/intel_engine_pm.h"
-struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
- struct intel_context *ce,
- struct intel_gt_buffer_pool_node *pool,
- u32 *cmd_buf, int cmd_size_in_dw)
+/* PXP GPU command definitions */
+
+/* MI_SET_APPID */
+#define MI_SET_APPID_TYPE1_APP BIT(7)
+#define MI_SET_APPID_SESSION_ID(x) ((x) << 0)
+
+/* MI_FLUSH_DW */
+#define MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE BIT(22)
+
+/* MI_WAIT */
+#define MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG BIT(9)
+#define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG BIT(8)
+
+/* CRYPTO_KEY_EXCHANGE */
+#define CRYPTO_KEY_EXCHANGE ((0x3 << 29) | (0x01609 << 16))
+
+#define MAX_TYPE0_SESSIONS 16
+#define MAX_TYPE1_SESSIONS 6
+
+static struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
+ struct intel_context *ce,
+ struct intel_gt_buffer_pool_node *pool,
+ u32 *cmd_buf, int cmd_size_in_dw)
{
struct i915_vma *batch = ERR_PTR(-EINVAL);
struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
@@ -50,7 +69,8 @@ struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
return batch;
}
-int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw)
+int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd,
+ int cmd_size_in_dw)
{
int err = -EINVAL;
struct i915_vma *batch;
@@ -154,3 +174,102 @@ int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw)
return err;
}
+
+int intel_pxp_cmd_add_prolog(struct intel_pxp *pxp, u32 *cmd,
+ int session_type,
+ int session_index)
+{
+ u32 increased_size_in_dw = 0;
+ u32 *cmd_prolog = cmd;
+ const int cmd_prolog_size_in_dw = 10;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ if (!cmd)
+ return cmd_prolog_size_in_dw;
+
+ /* MFX_WAIT - stall until prior PXP and MFX/HCP/HUC objects are cmopleted */
+ *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
+
+ /* MI_FLUSH_DW - pxp off */
+ *cmd_prolog++ = MI_FLUSH_DW; /* DW0 */
+ *cmd_prolog++ = 0; /* DW1 */
+ *cmd_prolog++ = 0; /* DW2 */
+
+ /* MI_SET_APPID */
+ if (session_type == SESSION_TYPE_TYPE1) {
+ if (session_index >= MAX_TYPE1_SESSIONS) {
+ drm_err(>->i915->drm, "Failed to %s invalid session_index\n", __func__);
+ goto end;
+ }
+
+ *cmd_prolog++ = (MI_SET_APPID | MI_SET_APPID_TYPE1_APP |
+ MI_SET_APPID_SESSION_ID(session_index));
+ } else {
+ if (session_index >= MAX_TYPE0_SESSIONS) {
+ drm_err(>->i915->drm, "Failed to %s invalid session_index\n", __func__);
+ goto end;
+ }
+
+ *cmd_prolog++ = (MI_SET_APPID | MI_SET_APPID_SESSION_ID(session_index));
+ }
+
+ /* MFX_WAIT */
+ *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
+
+ /* MI_FLUSH_DW - pxp on */
+ *cmd_prolog++ = (MI_FLUSH_DW | MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE); /* DW0 */
+ *cmd_prolog++ = 0; /* DW1 */
+ *cmd_prolog++ = 0; /* DW2 */
+
+ /* MFX_WAIT */
+ *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
+
+ increased_size_in_dw = (cmd_prolog - cmd);
+end:
+ return increased_size_in_dw;
+}
+
+int intel_pxp_cmd_add_epilog(u32 *cmd)
+{
+ u32 increased_size_in_dw = 0;
+ u32 *cmd_epilog = cmd;
+ const int cmd_epilog_size_in_dw = 5;
+
+ if (!cmd)
+ return cmd_epilog_size_in_dw;
+
+ /* MI_FLUSH_DW - pxp off */
+ *cmd_epilog++ = MI_FLUSH_DW; /* DW0 */
+ *cmd_epilog++ = 0; /* DW1 */
+ *cmd_epilog++ = 0; /* DW2 */
+
+ /* MFX_WAIT - stall until prior PXP and MFX/HCP/HUC objects are cmopleted */
+ *cmd_epilog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
+
+ /* MI_BATCH_BUFFER_END */
+ *cmd_epilog++ = MI_BATCH_BUFFER_END;
+
+ increased_size_in_dw = (cmd_epilog - cmd);
+ return increased_size_in_dw;
+}
+
+int intel_pxp_cmd_add_inline_termination(u32 *cmd)
+{
+ u32 increased_size_in_dw = 0;
+ u32 *cmd_termin = cmd;
+ const int cmd_termin_size_in_dw = 2;
+
+ if (!cmd)
+ return cmd_termin_size_in_dw;
+
+ /* CRYPTO_KEY_EXCHANGE - session inline termination */
+ *cmd_termin++ = CRYPTO_KEY_EXCHANGE; /* DW0 */
+ *cmd_termin++ = 0; /* DW1 */
+
+ increased_size_in_dw = (cmd_termin - cmd);
+ return increased_size_in_dw;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
index d04463962421..087f260034c4 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
@@ -9,10 +9,12 @@
#include "gt/intel_gt_buffer_pool.h"
#include "intel_pxp.h"
-struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
- struct intel_context *ce,
- struct intel_gt_buffer_pool_node *pool,
- u32 *cmd_buf, int cmd_size_in_dw);
+int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd,
+ int cmd_size_in_dw);
+int intel_pxp_cmd_add_prolog(struct intel_pxp *pxp, u32 *cmd,
+ int session_type,
+ int session_index);
+int intel_pxp_cmd_add_epilog(u32 *cmd);
+int intel_pxp_cmd_add_inline_termination(u32 *cmd);
-int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw);
#endif /* __INTEL_PXP_SM_H__ */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [Intel-gfx] [RFC-v3 07/13] drm/i915/pxp: Destroy arb session upon teardown
2020-12-09 7:03 ` [Intel-gfx] [RFC-v3 07/13] drm/i915/pxp: Destroy arb session upon teardown Huang, Sean Z
@ 2020-12-10 10:51 ` Joonas Lahtinen
0 siblings, 0 replies; 34+ messages in thread
From: Joonas Lahtinen @ 2020-12-10 10:51 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
Quoting Huang, Sean Z (2020-12-09 09:03:01)
> Teardown is triggered when the display topology changes and no
> long meets the secure playback requirement, and hardware trashes
> all the encryption keys for display. So as a result, PXP should
> handle such case and terminate the type0 sessions, which including
> arb session
We have only a single session, so this should be simplified to exactly
tear down that single session.
No need for any of the type0/type1 differentiation.
Regards, Joonas
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 3 +
> drivers/gpu/drm/i915/pxp/intel_pxp_arb.c | 76 +++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_arb.h | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 129 ++++++++++++++++++++++-
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 12 ++-
> 5 files changed, 211 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 9bcb170b34f1..48e926363696 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -28,6 +28,9 @@ static int intel_pxp_teardown_required_callback(struct intel_pxp *pxp)
> mutex_lock(&pxp->ctx.mutex);
>
> pxp->ctx.global_state_attacked = true;
> + pxp->ctx.flag_display_hm_surface_keys = false;
> +
> + ret = intel_pxp_arb_terminate_session(pxp);
>
> mutex_unlock(&pxp->ctx.mutex);
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
> index c1ad45b83478..09148ca9035c 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.c
> @@ -10,6 +10,7 @@
> #include "intel_pxp.h"
> #include "intel_pxp_context.h"
> #include "intel_pxp_tee.h"
> +#include "intel_pxp_cmd.h"
>
> #define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-31 */
>
> @@ -150,3 +151,78 @@ int intel_pxp_arb_create_session(struct intel_pxp *pxp)
> end:
> return ret;
> }
> +
> +static int intel_pxp_arb_session_with_global_termination(struct intel_pxp *pxp)
> +{
> + u32 *cmd = NULL;
> + u32 *cmd_ptr = NULL;
> + int cmd_size_in_dw = 0;
> + int ret;
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> +
> + /* Calculate how many bytes need to be alloc */
> + cmd_size_in_dw += intel_pxp_cmd_add_prolog(pxp, NULL, ARB_SESSION_TYPE, ARB_SESSION_INDEX);
> + cmd_size_in_dw += intel_pxp_cmd_add_inline_termination(NULL);
> + cmd_size_in_dw += intel_pxp_cmd_add_epilog(NULL);
> +
> + cmd = kzalloc(cmd_size_in_dw * 4, GFP_KERNEL);
> + if (!cmd)
> + return -ENOMEM;
> +
> + /* Program the command */
> + cmd_ptr = cmd;
> + cmd_ptr += intel_pxp_cmd_add_prolog(pxp, cmd_ptr, ARB_SESSION_TYPE, ARB_SESSION_INDEX);
> + cmd_ptr += intel_pxp_cmd_add_inline_termination(cmd_ptr);
> + cmd_ptr += intel_pxp_cmd_add_epilog(cmd_ptr);
> +
> + if (cmd_size_in_dw != (cmd_ptr - cmd)) {
> + ret = -EINVAL;
> + drm_err(>->i915->drm, "Failed to %s\n", __func__);
> + goto end;
> + }
> +
> + if (drm_debug_enabled(DRM_UT_DRIVER)) {
> + print_hex_dump(KERN_DEBUG, "global termination cmd binaries:",
> + DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw * 4, true);
> + }
> +
> + ret = intel_pxp_cmd_submit(pxp, cmd, cmd_size_in_dw);
> + if (ret) {
> + drm_err(>->i915->drm, "Failed to intel_pxp_cmd_submit()\n");
> + goto end;
> + }
> +
> +end:
> + kfree(cmd);
> + return ret;
> +}
> +
> +/**
> + * intel_pxp_arb_terminate_session - Terminate the arb hw session and its entries.
> + * @pxp: pointer to pxp struct.
> + *
> + * This function is NOT intended to be called from the ioctl, and need to be protected by
> + * ctx.mutex to ensure no SIP change during the call.
> + *
> + * Return: status. 0 means terminate is successful.
> + */
> +int intel_pxp_arb_terminate_session(struct intel_pxp *pxp)
> +{
> + int ret;
> + struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
> + struct pxp_protected_session *arb = pxp->ctx.arb_session;
> +
> + lockdep_assert_held(&pxp->ctx.mutex);
> +
> + /* terminate the hw sessions */
> + ret = intel_pxp_arb_session_with_global_termination(pxp);
> + if (ret) {
> + drm_err(>->i915->drm, "Failed to intel_pxp_arb_session_with_global_termination\n");
> + return ret;
> + }
> +
> + kfree(arb);
> +
> + return ret;
> +}
> +
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
> index e410c0bbdcc3..d7b3b05a4314 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_arb.h
> @@ -32,5 +32,6 @@ struct pxp_protected_session {
> };
>
> int intel_pxp_arb_create_session(struct intel_pxp *pxp);
> +int intel_pxp_arb_terminate_session(struct intel_pxp *pxp);
>
> #endif /* __INTEL_PXP_SM_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> index e531ea9f3cdc..f122c9a1f78e 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> @@ -8,10 +8,29 @@
> #include "gt/intel_context.h"
> #include "gt/intel_engine_pm.h"
>
> -struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
> - struct intel_context *ce,
> - struct intel_gt_buffer_pool_node *pool,
> - u32 *cmd_buf, int cmd_size_in_dw)
> +/* PXP GPU command definitions */
> +
> +/* MI_SET_APPID */
> +#define MI_SET_APPID_TYPE1_APP BIT(7)
> +#define MI_SET_APPID_SESSION_ID(x) ((x) << 0)
> +
> +/* MI_FLUSH_DW */
> +#define MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE BIT(22)
> +
> +/* MI_WAIT */
> +#define MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG BIT(9)
> +#define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG BIT(8)
> +
> +/* CRYPTO_KEY_EXCHANGE */
> +#define CRYPTO_KEY_EXCHANGE ((0x3 << 29) | (0x01609 << 16))
> +
> +#define MAX_TYPE0_SESSIONS 16
> +#define MAX_TYPE1_SESSIONS 6
> +
> +static struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
> + struct intel_context *ce,
> + struct intel_gt_buffer_pool_node *pool,
> + u32 *cmd_buf, int cmd_size_in_dw)
> {
> struct i915_vma *batch = ERR_PTR(-EINVAL);
> struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
> @@ -50,7 +69,8 @@ struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
> return batch;
> }
>
> -int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw)
> +int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd,
> + int cmd_size_in_dw)
> {
> int err = -EINVAL;
> struct i915_vma *batch;
> @@ -154,3 +174,102 @@ int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw)
>
> return err;
> }
> +
> +int intel_pxp_cmd_add_prolog(struct intel_pxp *pxp, u32 *cmd,
> + int session_type,
> + int session_index)
> +{
> + u32 increased_size_in_dw = 0;
> + u32 *cmd_prolog = cmd;
> + const int cmd_prolog_size_in_dw = 10;
> + struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
> +
> + if (!cmd)
> + return cmd_prolog_size_in_dw;
> +
> + /* MFX_WAIT - stall until prior PXP and MFX/HCP/HUC objects are cmopleted */
> + *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
> + MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
> +
> + /* MI_FLUSH_DW - pxp off */
> + *cmd_prolog++ = MI_FLUSH_DW; /* DW0 */
> + *cmd_prolog++ = 0; /* DW1 */
> + *cmd_prolog++ = 0; /* DW2 */
> +
> + /* MI_SET_APPID */
> + if (session_type == SESSION_TYPE_TYPE1) {
> + if (session_index >= MAX_TYPE1_SESSIONS) {
> + drm_err(>->i915->drm, "Failed to %s invalid session_index\n", __func__);
> + goto end;
> + }
> +
> + *cmd_prolog++ = (MI_SET_APPID | MI_SET_APPID_TYPE1_APP |
> + MI_SET_APPID_SESSION_ID(session_index));
> + } else {
> + if (session_index >= MAX_TYPE0_SESSIONS) {
> + drm_err(>->i915->drm, "Failed to %s invalid session_index\n", __func__);
> + goto end;
> + }
> +
> + *cmd_prolog++ = (MI_SET_APPID | MI_SET_APPID_SESSION_ID(session_index));
> + }
> +
> + /* MFX_WAIT */
> + *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
> + MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
> +
> + /* MI_FLUSH_DW - pxp on */
> + *cmd_prolog++ = (MI_FLUSH_DW | MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE); /* DW0 */
> + *cmd_prolog++ = 0; /* DW1 */
> + *cmd_prolog++ = 0; /* DW2 */
> +
> + /* MFX_WAIT */
> + *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
> + MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
> +
> + increased_size_in_dw = (cmd_prolog - cmd);
> +end:
> + return increased_size_in_dw;
> +}
> +
> +int intel_pxp_cmd_add_epilog(u32 *cmd)
> +{
> + u32 increased_size_in_dw = 0;
> + u32 *cmd_epilog = cmd;
> + const int cmd_epilog_size_in_dw = 5;
> +
> + if (!cmd)
> + return cmd_epilog_size_in_dw;
> +
> + /* MI_FLUSH_DW - pxp off */
> + *cmd_epilog++ = MI_FLUSH_DW; /* DW0 */
> + *cmd_epilog++ = 0; /* DW1 */
> + *cmd_epilog++ = 0; /* DW2 */
> +
> + /* MFX_WAIT - stall until prior PXP and MFX/HCP/HUC objects are cmopleted */
> + *cmd_epilog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
> + MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
> +
> + /* MI_BATCH_BUFFER_END */
> + *cmd_epilog++ = MI_BATCH_BUFFER_END;
> +
> + increased_size_in_dw = (cmd_epilog - cmd);
> + return increased_size_in_dw;
> +}
> +
> +int intel_pxp_cmd_add_inline_termination(u32 *cmd)
> +{
> + u32 increased_size_in_dw = 0;
> + u32 *cmd_termin = cmd;
> + const int cmd_termin_size_in_dw = 2;
> +
> + if (!cmd)
> + return cmd_termin_size_in_dw;
> +
> + /* CRYPTO_KEY_EXCHANGE - session inline termination */
> + *cmd_termin++ = CRYPTO_KEY_EXCHANGE; /* DW0 */
> + *cmd_termin++ = 0; /* DW1 */
> +
> + increased_size_in_dw = (cmd_termin - cmd);
> + return increased_size_in_dw;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
> index d04463962421..087f260034c4 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
> @@ -9,10 +9,12 @@
> #include "gt/intel_gt_buffer_pool.h"
> #include "intel_pxp.h"
>
> -struct i915_vma *intel_pxp_cmd_get_batch(struct intel_pxp *pxp,
> - struct intel_context *ce,
> - struct intel_gt_buffer_pool_node *pool,
> - u32 *cmd_buf, int cmd_size_in_dw);
> +int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd,
> + int cmd_size_in_dw);
> +int intel_pxp_cmd_add_prolog(struct intel_pxp *pxp, u32 *cmd,
> + int session_type,
> + int session_index);
> +int intel_pxp_cmd_add_epilog(u32 *cmd);
> +int intel_pxp_cmd_add_inline_termination(u32 *cmd);
>
> -int intel_pxp_cmd_submit(struct intel_pxp *pxp, u32 *cmd, int cmd_size_in_dw);
> #endif /* __INTEL_PXP_SM_H__ */
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* [Intel-gfx] [RFC-v3 08/13] drm/i915/pxp: Enable PXP power management
2020-12-09 7:02 [Intel-gfx] [RFC-v3 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (6 preceding siblings ...)
2020-12-09 7:03 ` [Intel-gfx] [RFC-v3 07/13] drm/i915/pxp: Destroy arb session upon teardown Huang, Sean Z
@ 2020-12-09 7:03 ` Huang, Sean Z
2020-12-09 7:03 ` [Intel-gfx] [RFC-v3 09/13] drm/i915/pxp: Expose session state for display protection flip Huang, Sean Z
` (7 subsequent siblings)
15 siblings, 0 replies; 34+ messages in thread
From: Huang, Sean Z @ 2020-12-09 7:03 UTC (permalink / raw)
To: Intel-gfx
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
software session state was marked as alive after resume. So to
handle such case, PXP should terminate all the hardware sessions
and cleanup all the software states after the power cycle.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++
drivers/gpu/drm/i915/i915_drv.c | 4 ++
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 65 ++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 ++++++++++
6 files changed, 106 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 2da904cda49f..2545b59fa4f2 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -260,6 +260,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp_arb.o \
pxp/intel_pxp_cmd.o \
pxp/intel_pxp_context.o \
+ pxp/intel_pxp_pm.o \
pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 274aa0dd7050..09a64d0feafe 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -20,6 +20,7 @@
#include "intel_rc6.h"
#include "intel_rps.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp_pm.h"
static void user_forcewake(struct intel_gt *gt, bool suspend)
{
@@ -241,6 +242,8 @@ int intel_gt_resume(struct intel_gt *gt)
intel_uc_resume(>->uc);
+ intel_pxp_pm_resume(>->pxp);
+
user_forcewake(gt, false);
out_fw:
@@ -275,6 +278,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt)
user_forcewake(gt, true);
wait_for_suspend(gt);
+ intel_pxp_pm_prepare_suspend(>->pxp);
intel_uc_suspend(>->uc);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9299a456adb0..af06c85e6ba7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -68,6 +68,8 @@
#include "gt/intel_gt_pm.h"
#include "gt/intel_rc6.h"
+#include "pxp/intel_pxp_pm.h"
+
#include "i915_debugfs.h"
#include "i915_drv.h"
#include "i915_ioc32.h"
@@ -1344,6 +1346,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
intel_power_domains_resume(dev_priv);
+ intel_pxp_pm_resume_early(&dev_priv->gt.pxp);
+
enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
return ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
index 62a2504b33bf..f03cba187c75 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
@@ -19,6 +19,7 @@ struct pxp_context {
int id;
bool global_state_attacked;
+ bool global_state_in_suspend;
bool flag_display_hm_surface_keys;
};
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
new file mode 100644
index 000000000000..0da2ecbf3b4d
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include "intel_pxp_context.h"
+#include "intel_pxp_arb.h"
+#include "intel_pxp_pm.h"
+
+void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp)
+{
+ if (pxp->ctx.id == 0)
+ return;
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ /* Disable PXP-IOCTLs */
+ pxp->ctx.global_state_in_suspend = true;
+
+ mutex_unlock(&pxp->ctx.mutex);
+}
+
+void intel_pxp_pm_resume_early(struct intel_pxp *pxp)
+{
+ if (pxp->ctx.id == 0)
+ return;
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ if (pxp->ctx.global_state_in_suspend) {
+ /* reset the attacked flag even there was a pending */
+ pxp->ctx.global_state_attacked = false;
+
+ pxp->ctx.flag_display_hm_surface_keys = false;
+ }
+
+ mutex_unlock(&pxp->ctx.mutex);
+}
+
+int intel_pxp_pm_resume(struct intel_pxp *pxp)
+{
+ int ret = 0;
+ struct intel_gt *gt = container_of(pxp, typeof(*gt), pxp);
+
+ if (pxp->ctx.id == 0)
+ return 0;
+
+ mutex_lock(&pxp->ctx.mutex);
+
+ /* Re-enable PXP-IOCTLs */
+ if (pxp->ctx.global_state_in_suspend) {
+ ret = intel_pxp_arb_terminate_session(pxp);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to terminate the arb session\n");
+ goto end;
+ }
+
+ pxp->ctx.global_state_in_suspend = false;
+ }
+
+end:
+ mutex_unlock(&pxp->ctx.mutex);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
new file mode 100644
index 000000000000..135bfb59aaf7
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_PM_H__
+#define __INTEL_PXP_PM_H__
+
+#include "i915_drv.h"
+
+#ifdef CONFIG_DRM_I915_PXP
+void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp);
+
+void intel_pxp_pm_resume_early(struct intel_pxp *pxp);
+int intel_pxp_pm_resume(struct intel_pxp *pxp);
+#else
+static inline void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp)
+{
+}
+
+static inline void intel_pxp_pm_resume_early(struct intel_pxp *pxp)
+{
+}
+
+static inline int intel_pxp_pm_resume(struct intel_pxp *pxp)
+{
+ return 0;
+}
+#endif
+
+#endif /* __INTEL_PXP_PM_H__ */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* [Intel-gfx] [RFC-v3 09/13] drm/i915/pxp: Expose session state for display protection flip
2020-12-09 7:02 [Intel-gfx] [RFC-v3 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (7 preceding siblings ...)
2020-12-09 7:03 ` [Intel-gfx] [RFC-v3 08/13] drm/i915/pxp: Enable PXP power management Huang, Sean Z
@ 2020-12-09 7:03 ` Huang, Sean Z
2020-12-09 7:03 ` [Intel-gfx] [RFC-v3 10/13] mei: pxp: export pavp client to me client bus Huang, Sean Z
` (6 subsequent siblings)
15 siblings, 0 replies; 34+ messages in thread
From: Huang, Sean Z @ 2020-12-09 7:03 UTC (permalink / raw)
To: Intel-gfx
Implement the intel_pxp_gem_object_status() to allow i915 display
querying the current PXP session state. In the design, display
should not perform protection flip on the protected buffers if
there is no PXP session alive.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 9 +++++++++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 8 ++++++++
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 48e926363696..ce3760206b76 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -143,3 +143,12 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
pxp->current_events |= events;
schedule_work(&pxp->irq_work);
}
+
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
+{
+ if (i915->gt.pxp.ctx.id != 0 &&
+ i915->gt.pxp.ctx.flag_display_hm_surface_keys)
+ return true;
+ else
+ return false;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index c8c580cee5bc..1e8b7ec47877 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -37,6 +37,8 @@ struct intel_pxp {
struct pxp_context ctx;
};
+struct drm_i915_private;
+
#ifdef CONFIG_DRM_I915_PXP
void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir);
int i915_pxp_teardown_required_callback(struct intel_pxp *pxp);
@@ -45,6 +47,7 @@ int i915_pxp_global_terminate_complete_callback(struct intel_pxp *pxp);
int intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_uninit(struct intel_pxp *pxp);
int intel_pxp_reg_read(struct intel_pxp *pxp, u32 offset, u32 *regval);
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915);
#else
static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
{
@@ -73,6 +76,11 @@ static inline int intel_pxp_reg_read(struct intel_pxp *pxp, u32 offset, u32 *reg
{
return 0;
}
+
+static inline bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
+{
+ return false;
+}
#endif
#endif /* __INTEL_PXP_PM_H__ */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* [Intel-gfx] [RFC-v3 10/13] mei: pxp: export pavp client to me client bus
2020-12-09 7:02 [Intel-gfx] [RFC-v3 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (8 preceding siblings ...)
2020-12-09 7:03 ` [Intel-gfx] [RFC-v3 09/13] drm/i915/pxp: Expose session state for display protection flip Huang, Sean Z
@ 2020-12-09 7:03 ` Huang, Sean Z
2020-12-09 7:03 ` [Intel-gfx] [RFC-v3 11/13] drm/i915/uapi: introduce drm_i915_gem_create_ext Huang, Sean Z
` (5 subsequent siblings)
15 siblings, 0 replies; 34+ messages in thread
From: Huang, Sean Z @ 2020-12-09 7:03 UTC (permalink / raw)
To: Intel-gfx; +Cc: Vitaly Lubart
From: Vitaly Lubart <vitaly.lubart@intel.com>
Export PAVP client to work with i915_cp driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig | 13 ++
drivers/misc/mei/pxp/Makefile | 7 +
drivers/misc/mei/pxp/mei_pxp.c | 230 +++++++++++++++++++++++++++++++++
drivers/misc/mei/pxp/mei_pxp.h | 18 +++
6 files changed, 271 insertions(+)
create mode 100644 drivers/misc/mei/pxp/Kconfig
create mode 100644 drivers/misc/mei/pxp/Makefile
create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index f5fd5b786607..0e0bcd0da852 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -47,3 +47,5 @@ config INTEL_MEI_TXE
Intel Bay Trail
source "drivers/misc/mei/hdcp/Kconfig"
+source "drivers/misc/mei/pxp/Kconfig"
+
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index f1c76f7ee804..d8e5165917f2 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -26,3 +26,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o
CFLAGS_mei-trace.o = -I$(src)
obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
+obj-$(CONFIG_INTEL_MEI_PXP) += pxp/
diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig
new file mode 100644
index 000000000000..4029b96afc04
--- /dev/null
+++ b/drivers/misc/mei/pxp/Kconfig
@@ -0,0 +1,13 @@
+
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+config INTEL_MEI_PXP
+ tristate "Intel PXP services of ME Interface"
+ select INTEL_MEI_ME
+ depends on DRM_I915
+ help
+ MEI Support for PXP Services on Intel platforms.
+
+ Enables the ME FW services required for PXP support through
+ I915 display driver of Intel.
diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile
new file mode 100644
index 000000000000..0329950d5794
--- /dev/null
+++ b/drivers/misc/mei/pxp/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+# Makefile - PXP client driver for Intel MEI Bus Driver.
+
+obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
new file mode 100644
index 000000000000..5bd61fe445e3
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+/**
+ * DOC: MEI_PXP Client Driver
+ *
+ * The mei_pxp driver acts as a translation layer between PXP
+ * protocol implementer (I915) and ME FW by translating PXP
+ * negotiation messages to ME FW command payloads and vice versa.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/uuid.h>
+#include <linux/mei_cl_bus.h>
+#include <linux/component.h>
+#include <drm/drm_connector.h>
+#include <drm/i915_component.h>
+#include <drm/i915_pxp_tee_interface.h>
+
+#include "mei_pxp.h"
+
+/**
+ * mei_pxp_send_message() - Sends a PXP message to ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @message: a message buffer to send
+ * @size: size of the message
+ * Return: 0 on Success, <0 on Failure
+ */
+static int
+mei_pxp_send_message(struct device *dev, const void *message, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !message)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ /* temporary drop const qualifier till the API is fixed */
+ byte = mei_cldev_send(cldev, (u8 *)message, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ return 0;
+}
+
+/**
+ * mei_pxp_receive_message() - Receives a PXP message from ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @buffer: a message buffer to contain the received message
+ * @size: size of the buffer
+ * Return: bytes sent on Success, <0 on Failure
+ */
+static int
+mei_pxp_receive_message(struct device *dev, void *buffer, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !buffer)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ byte = mei_cldev_recv(cldev, buffer, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ return byte;
+}
+
+static const struct i915_pxp_component_ops mei_pxp_ops = {
+ .owner = THIS_MODULE,
+ .send = mei_pxp_send_message,
+ .receive = mei_pxp_receive_message,
+};
+
+static int mei_component_master_bind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+ comp_master->ops = &mei_pxp_ops;
+ comp_master->tee_dev = dev;
+ ret = component_bind_all(dev, comp_master);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static void mei_component_master_unbind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+
+ dev_dbg(dev, "%s\n", __func__);
+ component_unbind_all(dev, comp_master);
+}
+
+static const struct component_master_ops mei_component_master_ops = {
+ .bind = mei_component_master_bind,
+ .unbind = mei_component_master_unbind,
+};
+
+/**
+ * mei_pxp_component_match - compare function for matching mei pxp.
+ *
+ * The function checks if the driver is i915, the subcomponent is PXP
+ * and the grand parent of pxp and the parent of i915 are the same
+ * PCH device.
+ *
+ * @dev: master device
+ * @subcomponent: subcomponent to match (I915_COMPONENT_PXP)
+ * @data: compare data (mei pxp device)
+ *
+ * Return:
+ * * 1 - if components match
+ * * 0 - otherwise
+ */
+static int mei_pxp_component_match(struct device *dev, int subcomponent,
+ void *data)
+{
+ struct device *base = data;
+
+ if (subcomponent != I915_COMPONENT_PXP)
+ return 0;
+
+ if (strcmp(dev->driver->name, "i915") == 0) {
+ base = base->parent;
+ if (!base)
+ return 0;
+
+ base = base->parent;
+ dev = dev->parent;
+ return (base && dev && dev == base);
+ }
+
+ return 0;
+}
+
+static int mei_pxp_probe(struct mei_cl_device *cldev,
+ const struct mei_cl_device_id *id)
+{
+ struct i915_pxp_comp_master *comp_master;
+ struct component_match *master_match;
+ int ret;
+
+ ret = mei_cldev_enable(cldev);
+ if (ret < 0) {
+ dev_err(&cldev->dev, "mei_cldev_enable Failed. %d\n", ret);
+ goto enable_err_exit;
+ }
+
+ comp_master = kzalloc(sizeof(*comp_master), GFP_KERNEL);
+ if (!comp_master) {
+ ret = -ENOMEM;
+ goto err_exit;
+ }
+
+ master_match = NULL;
+ component_match_add_typed(&cldev->dev, &master_match,
+ mei_pxp_component_match, &cldev->dev);
+ if (IS_ERR_OR_NULL(master_match)) {
+ ret = -ENOMEM;
+ goto err_exit;
+ }
+
+ mei_cldev_set_drvdata(cldev, comp_master);
+ ret = component_master_add_with_match(&cldev->dev,
+ &mei_component_master_ops,
+ master_match);
+ if (ret < 0) {
+ dev_err(&cldev->dev, "Master comp add failed %d\n", ret);
+ goto err_exit;
+ }
+
+ return 0;
+
+err_exit:
+ mei_cldev_set_drvdata(cldev, NULL);
+ kfree(comp_master);
+ mei_cldev_disable(cldev);
+enable_err_exit:
+ return ret;
+}
+
+static int mei_pxp_remove(struct mei_cl_device *cldev)
+{
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+
+ component_master_del(&cldev->dev, &mei_component_master_ops);
+ kfree(comp_master);
+ mei_cldev_set_drvdata(cldev, NULL);
+
+ return mei_cldev_disable(cldev);
+}
+
+/* fbf6fcf1-96cf-4e2e-a6a6-1bab8cbe36b1 : PAVP GUID*/
+#define MEI_GUID_PXP GUID_INIT(0xfbf6fcf1, 0x96cf, 0x4e2e, 0xA6, \
+ 0xa6, 0x1b, 0xab, 0x8c, 0xbe, 0x36, 0xb1)
+
+static struct mei_cl_device_id mei_pxp_tbl[] = {
+ { .uuid = MEI_GUID_PXP, .version = MEI_CL_VERSION_ANY },
+ { }
+};
+MODULE_DEVICE_TABLE(mei, mei_pxp_tbl);
+
+static struct mei_cl_driver mei_pxp_driver = {
+ .id_table = mei_pxp_tbl,
+ .name = KBUILD_MODNAME,
+ .probe = mei_pxp_probe,
+ .remove = mei_pxp_remove,
+};
+
+module_mei_cl_driver(mei_pxp_driver);
+
+MODULE_AUTHOR("Intel Corporation");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MEI PXP");
diff --git a/drivers/misc/mei/pxp/mei_pxp.h b/drivers/misc/mei/pxp/mei_pxp.h
new file mode 100644
index 000000000000..e7b15373fefd
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Authors:
+ * Vitaly Lubart <vitaly.lubart@intel.com>
+ */
+
+#ifndef __MEI_PXP_H__
+#define __MEI_PXP_H__
+
+/* me_pxp_status: Enumeration of all PXP Status Codes */
+enum me_pxp_status {
+ ME_PXP_STATUS_SUCCESS = 0x0000,
+
+};
+
+#endif /* __MEI_PXP_H__ */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* [Intel-gfx] [RFC-v3 11/13] drm/i915/uapi: introduce drm_i915_gem_create_ext
2020-12-09 7:02 [Intel-gfx] [RFC-v3 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (9 preceding siblings ...)
2020-12-09 7:03 ` [Intel-gfx] [RFC-v3 10/13] mei: pxp: export pavp client to me client bus Huang, Sean Z
@ 2020-12-09 7:03 ` Huang, Sean Z
2020-12-10 9:13 ` Joonas Lahtinen
2020-12-09 7:03 ` [Intel-gfx] [RFC-v3 12/13] drm/i915/pxp: User interface for Protected buffer Huang, Sean Z
` (4 subsequent siblings)
15 siblings, 1 reply; 34+ messages in thread
From: Huang, Sean Z @ 2020-12-09 7:03 UTC (permalink / raw)
To: Intel-gfx; +Cc: Joonas, Bommu Krishnaiah, Matthew
From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen joonas.lahtinen@linux.intel.com
Cc: Matthew Auld matthew.auld@intel.com
Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 42 ++++++++++++++++++++++++++++-
include/uapi/drm/i915_drm.h | 47 +++++++++++++++++++++++++++++++++
3 files changed, 89 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index af06c85e6ba7..3dbda949bf71 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1733,7 +1733,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 58276694c848..41698a823737 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -53,6 +53,7 @@
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
+#include "i915_user_extensions.h"
#include "intel_pm.h"
@@ -260,6 +261,35 @@ i915_gem_dumb_create(struct drm_file *file,
&args->size, &args->handle);
}
+struct create_ext {
+ struct drm_i915_private *i915;
+};
+
+static int __create_setparam(struct drm_i915_gem_object_param *args,
+ struct create_ext *ext_data)
+{
+ if (!(args->param & I915_OBJECT_PARAM)) {
+ DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n");
+ return -EINVAL;
+ }
+
+ return -EINVAL;
+}
+
+static int create_setparam(struct i915_user_extension __user *base, void *data)
+{
+ struct drm_i915_gem_create_ext_setparam ext;
+
+ if (copy_from_user(&ext, base, sizeof(ext)))
+ return -EFAULT;
+
+ return __create_setparam(&ext.param, data);
+}
+
+static const i915_user_extension_fn create_extensions[] = {
+ [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam,
+};
+
/**
* Creates a new mm object and returns a handle to it.
* @dev: drm device pointer
@@ -271,10 +301,20 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
struct drm_i915_private *i915 = to_i915(dev);
- struct drm_i915_gem_create *args = data;
+ struct create_ext ext_data = { .i915 = i915 };
+ struct drm_i915_gem_create_ext *args = data;
+ int ret;
i915_gem_flush_free_objects(i915);
+ ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
+ create_extensions,
+ ARRAY_SIZE(create_extensions),
+ &ext_data);
+ if (ret)
+ return ret;
+
+
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 6edcb2b6c708..e918ccc81c74 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -391,6 +391,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
@@ -728,6 +729,27 @@ struct drm_i915_gem_create {
__u32 pad;
};
+struct drm_i915_gem_create_ext {
+ /**
+ * Requested size for the object.
+ *
+ * The (page-aligned) allocated size for the object will be returned.
+ */
+ __u64 size;
+ /**
+ * Returned handle for the object.
+ *
+ * Object handles are nonzero.
+ */
+ __u32 handle;
+ __u32 pad;
+#define I915_GEM_CREATE_EXT_SETPARAM (1u << 0)
+#define I915_GEM_CREATE_EXT_FLAGS_UNKNOWN \
+ (-(I915_GEM_CREATE_EXT_SETPARAM << 1))
+ __u64 extensions;
+
+};
+
struct drm_i915_gem_pread {
/** Handle for the object being read. */
__u32 handle;
@@ -1698,6 +1720,31 @@ struct drm_i915_gem_context_param {
__u64 value;
};
+struct drm_i915_gem_object_param {
+ /* Object handle (0 for I915_GEM_CREATE_EXT_SETPARAM) */
+ __u32 handle;
+
+ /* Data pointer size */
+ __u32 size;
+
+/*
+ * I915_OBJECT_PARAM:
+ *
+ * Select object namespace for the param.
+ */
+#define I915_OBJECT_PARAM (1ull<<32)
+
+ __u64 param;
+
+ /* Data value or pointer */
+ __u64 data;
+};
+
+struct drm_i915_gem_create_ext_setparam {
+ struct i915_user_extension base;
+ struct drm_i915_gem_object_param param;
+};
+
/**
* Context SSEU programming
*
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [Intel-gfx] [RFC-v3 11/13] drm/i915/uapi: introduce drm_i915_gem_create_ext
2020-12-09 7:03 ` [Intel-gfx] [RFC-v3 11/13] drm/i915/uapi: introduce drm_i915_gem_create_ext Huang, Sean Z
@ 2020-12-10 9:13 ` Joonas Lahtinen
0 siblings, 0 replies; 34+ messages in thread
From: Joonas Lahtinen @ 2020-12-10 9:13 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx; +Cc: Bommu Krishnaiah, Joonas, Matthew
Quoting Huang, Sean Z (2020-12-09 09:03:05)
> From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
The patch authorship is still recorded wrong.
'git am' should always be used for importing patches to retain the
correct authorship.
Regards, Joonas
> Same old gem_create but with now with extensions support. This is needed
> to support various upcoming usecases. For now we use the extensions
> mechanism to support PAVP.
>
> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Joonas Lahtinen joonas.lahtinen@linux.intel.com
> Cc: Matthew Auld matthew.auld@intel.com
> Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_gem.c | 42 ++++++++++++++++++++++++++++-
> include/uapi/drm/i915_drm.h | 47 +++++++++++++++++++++++++++++++++
> 3 files changed, 89 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index af06c85e6ba7..3dbda949bf71 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1733,7 +1733,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
> DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
> DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
> - DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
> + DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
> DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 58276694c848..41698a823737 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -53,6 +53,7 @@
> #include "i915_drv.h"
> #include "i915_trace.h"
> #include "i915_vgpu.h"
> +#include "i915_user_extensions.h"
>
> #include "intel_pm.h"
>
> @@ -260,6 +261,35 @@ i915_gem_dumb_create(struct drm_file *file,
> &args->size, &args->handle);
> }
>
> +struct create_ext {
> + struct drm_i915_private *i915;
> +};
> +
> +static int __create_setparam(struct drm_i915_gem_object_param *args,
> + struct create_ext *ext_data)
> +{
> + if (!(args->param & I915_OBJECT_PARAM)) {
> + DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n");
> + return -EINVAL;
> + }
> +
> + return -EINVAL;
> +}
> +
> +static int create_setparam(struct i915_user_extension __user *base, void *data)
> +{
> + struct drm_i915_gem_create_ext_setparam ext;
> +
> + if (copy_from_user(&ext, base, sizeof(ext)))
> + return -EFAULT;
> +
> + return __create_setparam(&ext.param, data);
> +}
> +
> +static const i915_user_extension_fn create_extensions[] = {
> + [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam,
> +};
> +
> /**
> * Creates a new mm object and returns a handle to it.
> * @dev: drm device pointer
> @@ -271,10 +301,20 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file)
> {
> struct drm_i915_private *i915 = to_i915(dev);
> - struct drm_i915_gem_create *args = data;
> + struct create_ext ext_data = { .i915 = i915 };
> + struct drm_i915_gem_create_ext *args = data;
> + int ret;
>
> i915_gem_flush_free_objects(i915);
>
> + ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
> + create_extensions,
> + ARRAY_SIZE(create_extensions),
> + &ext_data);
> + if (ret)
> + return ret;
> +
> +
> return i915_gem_create(file,
> intel_memory_region_by_type(i915,
> INTEL_MEMORY_SYSTEM),
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 6edcb2b6c708..e918ccc81c74 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -391,6 +391,7 @@ typedef struct _drm_i915_sarea {
> #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
> #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
> #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
> +#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
> #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
> #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
> #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
> @@ -728,6 +729,27 @@ struct drm_i915_gem_create {
> __u32 pad;
> };
>
> +struct drm_i915_gem_create_ext {
> + /**
> + * Requested size for the object.
> + *
> + * The (page-aligned) allocated size for the object will be returned.
> + */
> + __u64 size;
> + /**
> + * Returned handle for the object.
> + *
> + * Object handles are nonzero.
> + */
> + __u32 handle;
> + __u32 pad;
> +#define I915_GEM_CREATE_EXT_SETPARAM (1u << 0)
> +#define I915_GEM_CREATE_EXT_FLAGS_UNKNOWN \
> + (-(I915_GEM_CREATE_EXT_SETPARAM << 1))
> + __u64 extensions;
> +
> +};
> +
> struct drm_i915_gem_pread {
> /** Handle for the object being read. */
> __u32 handle;
> @@ -1698,6 +1720,31 @@ struct drm_i915_gem_context_param {
> __u64 value;
> };
>
> +struct drm_i915_gem_object_param {
> + /* Object handle (0 for I915_GEM_CREATE_EXT_SETPARAM) */
> + __u32 handle;
> +
> + /* Data pointer size */
> + __u32 size;
> +
> +/*
> + * I915_OBJECT_PARAM:
> + *
> + * Select object namespace for the param.
> + */
> +#define I915_OBJECT_PARAM (1ull<<32)
> +
> + __u64 param;
> +
> + /* Data value or pointer */
> + __u64 data;
> +};
> +
> +struct drm_i915_gem_create_ext_setparam {
> + struct i915_user_extension base;
> + struct drm_i915_gem_object_param param;
> +};
> +
> /**
> * Context SSEU programming
> *
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread
* [Intel-gfx] [RFC-v3 12/13] drm/i915/pxp: User interface for Protected buffer
2020-12-09 7:02 [Intel-gfx] [RFC-v3 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (10 preceding siblings ...)
2020-12-09 7:03 ` [Intel-gfx] [RFC-v3 11/13] drm/i915/uapi: introduce drm_i915_gem_create_ext Huang, Sean Z
@ 2020-12-09 7:03 ` Huang, Sean Z
2020-12-09 7:03 ` [Intel-gfx] [RFC-v3 13/13] drm/i915/pxp: Add plane decryption support Huang, Sean Z
` (3 subsequent siblings)
15 siblings, 0 replies; 34+ messages in thread
From: Huang, Sean Z @ 2020-12-09 7:03 UTC (permalink / raw)
To: Intel-gfx; +Cc: Bommu Krishnaiah, Huang Sean Z, Kondapally Kalyan
From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
This api allow user mode to create Protected buffer and context creation.
Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
Cc: Kondapally Kalyan <kalyan.kondapally@intel.com>
Cc: Gupta Anshuman <Anshuman.Gupta@intel.com>
Cc: Huang Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 ++++++++++--
drivers/gpu/drm/i915/gem/i915_gem_context.h | 10 ++++++++
.../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 5 ++++
drivers/gpu/drm/i915/i915_gem.c | 23 +++++++++++++++----
include/uapi/drm/i915_drm.h | 19 +++++++++++++++
6 files changed, 67 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index a6299da64de4..dd5d24a13cb9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -2060,12 +2060,23 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
case I915_CONTEXT_PARAM_RECOVERABLE:
if (args->size)
ret = -EINVAL;
- else if (args->value)
- i915_gem_context_set_recoverable(ctx);
+ else if (args->value) {
+ if (!i915_gem_context_is_protected(ctx))
+ i915_gem_context_set_recoverable(ctx);
+ else
+ ret = -EPERM;
+ }
else
i915_gem_context_clear_recoverable(ctx);
break;
+ case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ if (args->size)
+ ret = -EINVAL;
+ else if (args->value)
+ i915_gem_context_set_protected(ctx);
+ break;
+
case I915_CONTEXT_PARAM_PRIORITY:
ret = set_priority(ctx, args);
break;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index a133f92bbedb..5897e7ca11a8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -70,6 +70,16 @@ static inline void i915_gem_context_set_recoverable(struct i915_gem_context *ctx
set_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags);
}
+static inline void i915_gem_context_set_protected(struct i915_gem_context *ctx)
+{
+ set_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+}
+
+static inline bool i915_gem_context_is_protected(struct i915_gem_context *ctx)
+{
+ return test_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+}
+
static inline void i915_gem_context_clear_recoverable(struct i915_gem_context *ctx)
{
clear_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index ae14ca24a11f..81ae94c2be86 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -135,7 +135,7 @@ struct i915_gem_context {
#define UCONTEXT_BANNABLE 2
#define UCONTEXT_RECOVERABLE 3
#define UCONTEXT_PERSISTENCE 4
-
+#define UCONTEXT_PROTECTED 5
/**
* @flags: small set of booleans
*/
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index e2d9b7e1e152..90ac955463f4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -161,6 +161,11 @@ struct drm_i915_gem_object {
} mmo;
I915_SELFTEST_DECLARE(struct list_head st_link);
+ /**
+ * @user_flags: small set of booleans set by the user
+ */
+ unsigned long user_flags;
+#define I915_BO_PROTECTED BIT(0)
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 41698a823737..6a791fd24eaa 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -184,7 +184,8 @@ static int
i915_gem_create(struct drm_file *file,
struct intel_memory_region *mr,
u64 *size_p,
- u32 *handle_p)
+ u32 *handle_p,
+ u64 user_flags)
{
struct drm_i915_gem_object *obj;
u32 handle;
@@ -204,6 +205,8 @@ i915_gem_create(struct drm_file *file,
if (IS_ERR(obj))
return PTR_ERR(obj);
+ obj->user_flags = user_flags;
+
ret = drm_gem_handle_create(file, &obj->base, &handle);
/* drop reference from allocate - handle holds it now */
i915_gem_object_put(obj);
@@ -258,11 +261,12 @@ i915_gem_dumb_create(struct drm_file *file,
return i915_gem_create(file,
intel_memory_region_by_type(to_i915(dev),
mem_type),
- &args->size, &args->handle);
+ &args->size, &args->handle, 0);
}
struct create_ext {
- struct drm_i915_private *i915;
+ struct drm_i915_private *i915;
+ unsigned long user_flags;
};
static int __create_setparam(struct drm_i915_gem_object_param *args,
@@ -273,6 +277,17 @@ static int __create_setparam(struct drm_i915_gem_object_param *args,
return -EINVAL;
}
+ switch (lower_32_bits(args->param)) {
+ case I915_PARAM_PROTECTED_CONTENT:
+ if (args->size) {
+ return -EINVAL;
+ } else if (args->data) {
+ ext_data->user_flags = args->data;
+ return 0;
+ }
+ break;
+ }
+
return -EINVAL;
}
@@ -318,7 +333,7 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
- &args->size, &args->handle);
+ &args->size, &args->handle, ext_data.user_flags);
}
static int
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index e918ccc81c74..d6085a328b2c 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1715,6 +1715,15 @@ struct drm_i915_gem_context_param {
* Default is 16 KiB.
*/
#define I915_CONTEXT_PARAM_RINGSIZE 0xc
+
+/*
+ * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ *
+ * If set to true (1) PAVP content protection is enabled.
+ * When enabled, the context is marked unrecoverable and may
+ * become invalid due to PAVP teardown event or other error.
+ */
+#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd
/* Must be kept compact -- no holes and well documented */
__u64 value;
@@ -1734,6 +1743,16 @@ struct drm_i915_gem_object_param {
*/
#define I915_OBJECT_PARAM (1ull<<32)
+/*
+ * I915_PARAM_PROTECTED_CONTENT:
+ *
+ * If set to true (1) buffer contents is expected to be protected by
+ * PAVP encryption and requires decryption for scan out and processing.
+ * Protected buffers can only be used in PAVP protected contexts.
+ * A protected buffer may become invalid as a result of PAVP teardown.
+ */
+#define I915_PARAM_PROTECTED_CONTENT 0x1
+
__u64 param;
/* Data value or pointer */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* [Intel-gfx] [RFC-v3 13/13] drm/i915/pxp: Add plane decryption support
2020-12-09 7:02 [Intel-gfx] [RFC-v3 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (11 preceding siblings ...)
2020-12-09 7:03 ` [Intel-gfx] [RFC-v3 12/13] drm/i915/pxp: User interface for Protected buffer Huang, Sean Z
@ 2020-12-09 7:03 ` Huang, Sean Z
2020-12-09 7:27 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP component - Mesa single session (rev3) Patchwork
` (2 subsequent siblings)
15 siblings, 0 replies; 34+ messages in thread
From: Huang, Sean Z @ 2020-12-09 7:03 UTC (permalink / raw)
To: Intel-gfx; +Cc: Bommu Krishnaiah
From: Anshuman Gupta <anshuman.gupta@intel.com>
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PAVP session is enabled.
2. Buffer object is protected.
v2:
- Rebased to libva_cp-drm-tip_tgl_cp tree.
- Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Huang, Sean Z <sean.z.huang@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index b7e208816074..273bdc031e8d 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -39,6 +39,8 @@
#include <drm/drm_plane_helper.h>
#include <drm/drm_rect.h>
+#include "pxp/intel_pxp.h"
+
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
@@ -767,6 +769,11 @@ icl_program_input_csc(struct intel_plane *plane,
PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
}
+static bool intel_fb_obj_protected(const struct drm_i915_gem_object *obj)
+{
+ return obj->user_flags & I915_BO_PROTECTED ? true : false;
+}
+
static void
skl_plane_async_flip(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -803,6 +810,7 @@ skl_program_plane(struct intel_plane *plane,
u32 surf_addr = plane_state->color_plane[color_plane].offset;
u32 stride = skl_plane_stride(plane_state, color_plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
+ const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
int aux_plane = intel_main_to_aux_plane(fb, color_plane);
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
@@ -813,7 +821,7 @@ skl_program_plane(struct intel_plane *plane,
u8 alpha = plane_state->hw.alpha >> 8;
u32 plane_color_ctl = 0, aux_dist = 0;
unsigned long irqflags;
- u32 keymsk, keymax;
+ u32 keymsk, keymax, plane_surf;
u32 plane_ctl = plane_state->ctl;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -889,8 +897,15 @@ skl_program_plane(struct intel_plane *plane,
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
- intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + surf_addr);
+ plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
+
+ if (intel_pxp_gem_object_status(dev_priv) &&
+ intel_fb_obj_protected(obj))
+ plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
+ else
+ plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
+
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
if (plane_state->scaler_id >= 0)
skl_program_scaler(plane, crtc_state, plane_state);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1e8dfe435ca8..0ea7e2a402ae 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7209,6 +7209,7 @@ enum {
#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
#define PLANE_SURF(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
+#define PLANE_SURF_DECRYPTION_ENABLED REG_BIT(2)
#define _PLANE_OFFSET_1_B 0x711a4
#define _PLANE_OFFSET_2_B 0x712a4
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 34+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP component - Mesa single session (rev3)
2020-12-09 7:02 [Intel-gfx] [RFC-v3 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (12 preceding siblings ...)
2020-12-09 7:03 ` [Intel-gfx] [RFC-v3 13/13] drm/i915/pxp: Add plane decryption support Huang, Sean Z
@ 2020-12-09 7:27 ` Patchwork
2020-12-09 7:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-12-09 9:11 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
15 siblings, 0 replies; 34+ messages in thread
From: Patchwork @ 2020-12-09 7:27 UTC (permalink / raw)
To: Huang, Sean Z; +Cc: intel-gfx
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev3)
URL : https://patchwork.freedesktop.org/series/84620/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9ae32f4f2eb1 drm/i915/pxp: Introduce Intel PXP component
-:111: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#111:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 175 lines checked
2dab19aab08d drm/i915/pxp: set KCR reg init during the boot time
b7d165163cc9 drm/i915/pxp: Implement funcs to create the TEE channel
-:8: WARNING:TYPO_SPELLING: 'defualt' may be misspelled - perhaps 'default'?
#8:
(defualt) session.
-:85: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#85:
new file mode 100644
total: 0 errors, 2 warnings, 0 checks, 248 lines checked
5fba41ef381a drm/i915/pxp: Create the arbitrary session after boot
-:68: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#68:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 311 lines checked
99a4cb2946c9 drm/i915/pxp: Func to send hardware session termination
-:25: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#25:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 181 lines checked
bebe24b4735c drm/i915/pxp: Enable PXP irq worker and callback stub
-:51: WARNING:LONG_LINE_COMMENT: line length of 113 exceeds 100 columns
#51: FILE: drivers/gpu/drm/i915/i915_reg.h:7970:
+#define GEN11_CRYPTO_INTR_MASK _MMIO(0x1900f0) /* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */
total: 0 errors, 1 warnings, 0 checks, 211 lines checked
b9b9d9b3d000 drm/i915/pxp: Destroy arb session upon teardown
8a8a945349b3 drm/i915/pxp: Enable PXP power management
-:90: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#90:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 148 lines checked
3073cbf15fe1 drm/i915/pxp: Expose session state for display protection flip
9d59c789c491 mei: pxp: export pavp client to me client bus
-:32: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#32:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 277 lines checked
020fc05af9bc drm/i915/uapi: introduce drm_i915_gem_create_ext
-:12: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Joonas Lahtinen joonas.lahtinen@linux.intel.com'
#12:
Cc: Joonas Lahtinen joonas.lahtinen@linux.intel.com
-:13: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Matthew Auld matthew.auld@intel.com'
#13:
Cc: Matthew Auld matthew.auld@intel.com
-:46: ERROR:CODE_INDENT: code indent should use tabs where possible
#46: FILE: drivers/gpu/drm/i915/i915_gem.c:265:
+ struct drm_i915_private *i915;$
-:46: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#46: FILE: drivers/gpu/drm/i915/i915_gem.c:265:
+ struct drm_i915_private *i915;$
-:50: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#50: FILE: drivers/gpu/drm/i915/i915_gem.c:269:
+static int __create_setparam(struct drm_i915_gem_object_param *args,
+ struct create_ext *ext_data)
-:95: CHECK:LINE_SPACING: Please don't use multiple blank lines
#95: FILE: drivers/gpu/drm/i915/i915_gem.c:317:
+
+
-:107: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#107: FILE: include/uapi/drm/i915_drm.h:394:
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
-:155: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#155: FILE: include/uapi/drm/i915_drm.h:1735:
+#define I915_OBJECT_PARAM (1ull<<32)
^
total: 3 errors, 2 warnings, 3 checks, 136 lines checked
6122eeb602ea drm/i915/pxp: User interface for Protected buffer
b8913e83d4cc drm/i915/pxp: Add plane decryption support
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for Introduce Intel PXP component - Mesa single session (rev3)
2020-12-09 7:02 [Intel-gfx] [RFC-v3 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (13 preceding siblings ...)
2020-12-09 7:27 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP component - Mesa single session (rev3) Patchwork
@ 2020-12-09 7:57 ` Patchwork
2020-12-09 9:11 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
15 siblings, 0 replies; 34+ messages in thread
From: Patchwork @ 2020-12-09 7:57 UTC (permalink / raw)
To: Huang, Sean Z; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 3829 bytes --]
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev3)
URL : https://patchwork.freedesktop.org/series/84620/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9463 -> Patchwork_19089
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/index.html
New tests
---------
New tests have been introduced between CI_DRM_9463 and Patchwork_19089:
### New CI tests (1) ###
* boot:
- Statuses : 1 fail(s) 39 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_19089 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@semaphore:
- fi-icl-y: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/fi-icl-y/igt@amdgpu/amd_basic@semaphore.html
* igt@debugfs_test@read_all_entries:
- fi-tgl-y: [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +2 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/fi-tgl-y/igt@debugfs_test@read_all_entries.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/fi-tgl-y/igt@debugfs_test@read_all_entries.html
#### Possible fixes ####
* igt@gem_flink_basic@double-flink:
- fi-tgl-y: [DMESG-WARN][4] ([i915#402]) -> [PASS][5] +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/fi-tgl-y/igt@gem_flink_basic@double-flink.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/fi-tgl-y/igt@gem_flink_basic@double-flink.html
* igt@i915_selftest@live@execlists:
- fi-icl-y: [INCOMPLETE][6] ([i915#1037] / [i915#2276]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/fi-icl-y/igt@i915_selftest@live@execlists.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/fi-icl-y/igt@i915_selftest@live@execlists.html
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#1037]: https://gitlab.freedesktop.org/drm/intel/issues/1037
[i915#2276]: https://gitlab.freedesktop.org/drm/intel/issues/2276
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (43 -> 40)
------------------------------
Missing (3): fi-ilk-m540 fi-bdw-samus fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_9463 -> Patchwork_19089
CI-20190529: 20190529
CI_DRM_9463: 1c64d5d72bcd4e6ccf2d0ba6e6ab3644497846b5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5885: d99f644b1868b9c92435b05ebfafa230721cd677 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19089: b8913e83d4cc32dd0dffdf00aa4d506ac36496b2 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b8913e83d4cc drm/i915/pxp: Add plane decryption support
6122eeb602ea drm/i915/pxp: User interface for Protected buffer
020fc05af9bc drm/i915/uapi: introduce drm_i915_gem_create_ext
9d59c789c491 mei: pxp: export pavp client to me client bus
3073cbf15fe1 drm/i915/pxp: Expose session state for display protection flip
8a8a945349b3 drm/i915/pxp: Enable PXP power management
b9b9d9b3d000 drm/i915/pxp: Destroy arb session upon teardown
bebe24b4735c drm/i915/pxp: Enable PXP irq worker and callback stub
99a4cb2946c9 drm/i915/pxp: Func to send hardware session termination
5fba41ef381a drm/i915/pxp: Create the arbitrary session after boot
b7d165163cc9 drm/i915/pxp: Implement funcs to create the TEE channel
2dab19aab08d drm/i915/pxp: set KCR reg init during the boot time
9ae32f4f2eb1 drm/i915/pxp: Introduce Intel PXP component
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/index.html
[-- Attachment #1.2: Type: text/html, Size: 4688 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 34+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for Introduce Intel PXP component - Mesa single session (rev3)
2020-12-09 7:02 [Intel-gfx] [RFC-v3 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (14 preceding siblings ...)
2020-12-09 7:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-12-09 9:11 ` Patchwork
15 siblings, 0 replies; 34+ messages in thread
From: Patchwork @ 2020-12-09 9:11 UTC (permalink / raw)
To: Huang, Sean Z; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 18552 bytes --]
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev3)
URL : https://patchwork.freedesktop.org/series/84620/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9463_full -> Patchwork_19089_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
New tests
---------
New tests have been introduced between CI_DRM_9463_full and Patchwork_19089_full:
### New CI tests (1) ###
* boot:
- Statuses : 200 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_19089_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_reloc@basic-wide-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][1] ([i915#2389])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-iclb2/igt@gem_exec_reloc@basic-wide-active@vcs1.html
* igt@gem_workarounds@suspend-resume-context:
- shard-skl: [PASS][2] -> [INCOMPLETE][3] ([i915#198] / [i915#2295])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-skl2/igt@gem_workarounds@suspend-resume-context.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-skl6/igt@gem_workarounds@suspend-resume-context.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][4] -> [DMESG-WARN][5] ([i915#1436] / [i915#716])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-skl10/igt@gen9_exec_parse@allowed-single.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-skl8/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_rpm@cursor:
- shard-glk: [PASS][6] -> [DMESG-WARN][7] ([i915#118] / [i915#95]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-glk1/igt@i915_pm_rpm@cursor.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-glk4/igt@i915_pm_rpm@cursor.html
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-hsw: NOTRUN -> [SKIP][8] ([fdo#109271]) +53 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-hsw6/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-skl: [PASS][9] -> [INCOMPLETE][10] ([i915#151])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-skl10/igt@i915_pm_rpm@system-suspend-execbuf.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-skl9/igt@i915_pm_rpm@system-suspend-execbuf.html
* igt@kms_chamelium@hdmi-crc-nonplanar-formats:
- shard-hsw: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-hsw6/igt@kms_chamelium@hdmi-crc-nonplanar-formats.html
* igt@kms_color@pipe-a-ctm-green-to-red:
- shard-skl: [PASS][12] -> [DMESG-WARN][13] ([i915#1982]) +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-skl5/igt@kms_color@pipe-a-ctm-green-to-red.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-skl2/igt@kms_color@pipe-a-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-a-gamma:
- shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-skl4/igt@kms_color_chamelium@pipe-a-gamma.html
* igt@kms_cursor_crc@pipe-a-cursor-64x21-random:
- shard-skl: [PASS][15] -> [FAIL][16] ([i915#54]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-skl8/igt@kms_cursor_crc@pipe-a-cursor-64x21-random.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-64x21-random.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: NOTRUN -> [FAIL][17] ([i915#96])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* igt@kms_draw_crc@draw-method-xrgb8888-pwrite-ytiled:
- shard-glk: [PASS][18] -> [FAIL][19] ([i915#52] / [i915#54])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-glk1/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-ytiled.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-glk4/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-ytiled.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-tglb: [PASS][20] -> [FAIL][21] ([i915#2598]) +1 similar issue
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-tglb6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-tglb2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
- shard-skl: [PASS][22] -> [FAIL][23] ([i915#2122]) +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-skl: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#2672])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-skl9/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-render:
- shard-skl: NOTRUN -> [SKIP][25] ([fdo#109271]) +23 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-skl3/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-render.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][26] -> [FAIL][27] ([fdo#108145] / [i915#265])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-skl: NOTRUN -> [FAIL][28] ([fdo#108145] / [i915#265])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) +2 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-iclb4/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@perf@polling-parameterized:
- shard-glk: [PASS][31] -> [FAIL][32] ([i915#1542])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-glk8/igt@perf@polling-parameterized.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-glk5/igt@perf@polling-parameterized.html
#### Possible fixes ####
* igt@gem_exec_whisper@basic-contexts:
- shard-glk: [DMESG-WARN][33] ([i915#118] / [i915#95]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-glk3/igt@gem_exec_whisper@basic-contexts.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-glk9/igt@gem_exec_whisper@basic-contexts.html
* igt@gem_userptr_blits@huge-split:
- shard-hsw: [FAIL][35] ([i915#2784]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-hsw2/igt@gem_userptr_blits@huge-split.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-hsw6/igt@gem_userptr_blits@huge-split.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen:
- shard-skl: [FAIL][37] ([i915#54]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [FAIL][39] ([i915#96]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-hsw4/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][41] ([i915#79]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-vga1-hdmi-a1:
- shard-hsw: [FAIL][43] ([i915#2122]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-hsw6/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-vga1-hdmi-a1.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-hsw4/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-vga1-hdmi-a1.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-skl: [INCOMPLETE][45] ([i915#198]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-skl9/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-skl9/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][47] ([fdo#108145] / [i915#265]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [SKIP][49] ([fdo#109441]) -> [PASS][50] +2 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-iclb4/igt@kms_psr@psr2_primary_page_flip.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][51] ([i915#588]) -> [SKIP][52] ([i915#658])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-iclb3/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][53] ([i915#1804] / [i915#2684]) -> [FAIL][54] ([i915#2680])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-iclb6/igt@i915_pm_rc6_residency@rc6-idle.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-iclb5/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [DMESG-WARN][55] ([i915#1226]) -> [SKIP][56] ([fdo#109349])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-iclb4/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-kbl: [DMESG-WARN][57] ([i915#1602]) -> [INCOMPLETE][58] ([i915#155] / [i915#2405])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-kbl7/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-kbl2/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
- shard-glk: [DMESG-WARN][59] ([i915#2635]) -> [DMESG-WARN][60] ([i915#1602] / [i915#2635])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-glk3/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-glk9/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
- shard-apl: [DMESG-WARN][61] ([i915#2635]) -> [DMESG-WARN][62] ([i915#1602] / [i915#2635])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-apl1/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-apl3/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][63], [FAIL][64]) ([i915#1814] / [i915#2295] / [i915#2722] / [i915#483] / [i915#602]) -> [FAIL][65] ([i915#2295] / [i915#2722] / [i915#483])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-kbl1/igt@runner@aborted.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-kbl7/igt@runner@aborted.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-kbl3/igt@runner@aborted.html
- shard-iclb: ([FAIL][66], [FAIL][67]) ([i915#1814] / [i915#2295] / [i915#2722] / [i915#483]) -> ([FAIL][68], [FAIL][69]) ([i915#1814] / [i915#2295] / [i915#2722] / [i915#2724] / [i915#483])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-iclb1/igt@runner@aborted.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-iclb3/igt@runner@aborted.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-iclb1/igt@runner@aborted.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-iclb8/igt@runner@aborted.html
- shard-glk: ([FAIL][70], [FAIL][71]) ([i915#1814] / [i915#2295] / [i915#2722] / [i915#483] / [k.org#202321]) -> ([FAIL][72], [FAIL][73]) ([i915#1814] / [i915#2295] / [i915#2722] / [k.org#202321])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-glk2/igt@runner@aborted.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-glk3/igt@runner@aborted.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-glk9/igt@runner@aborted.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-glk1/igt@runner@aborted.html
- shard-skl: [FAIL][74] ([i915#2295] / [i915#2722]) -> ([FAIL][75], [FAIL][76]) ([i915#1436] / [i915#2295] / [i915#2722] / [i915#483])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9463/shard-skl4/igt@runner@aborted.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-skl8/igt@runner@aborted.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/shard-skl3/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
[i915#2598]: https://gitlab.freedesktop.org/drm/intel/issues/2598
[i915#2635]: https://gitlab.freedesktop.org/drm/intel/issues/2635
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2680]: https://gitlab.freedesktop.org/drm/intel/issues/2680
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724
[i915#2784]: https://gitlab.freedesktop.org/drm/intel/issues/2784
[i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483
[i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#602]: https://gitlab.freedesktop.org/drm/intel/issues/602
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9463 -> Patchwork_19089
CI-20190529: 20190529
CI_DRM_9463: 1c64d5d72bcd4e6ccf2d0ba6e6ab3644497846b5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5885: d99f644b1868b9c92435b05ebfafa230721cd677 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19089: b8913e83d4cc32dd0dffdf00aa4d506ac36496b2 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19089/index.html
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