* [PATCH] drm/i915/cnp: Wa 1181: Fix Backlight issue
@ 2017-08-29 5:07 Rodrigo Vivi
2017-08-29 5:28 ` ✓ Fi.CI.BAT: success for " Patchwork
` (4 more replies)
0 siblings, 5 replies; 10+ messages in thread
From: Rodrigo Vivi @ 2017-08-29 5:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Arthur J Runyan, Dhinakaran Pandiyan, Rodrigo Vivi
This workaround fixes a CNL PCH bug when changing
backlight from a lower frequency to a higher frequency.
During random reboot cycles, display backlight seems to
be off/ dim for 2-3 mins.
The only functional change on this patch is to
set bit 13 of 0xC2020 for CNL PCH.
The rest of patch is organizing identation around
those bits definitions and re-organizing CFL workarounds.
Cc: Arthur J Runyan <arthur.j.runyan@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 11 ++++++-----
drivers/gpu/drm/i915/intel_pm.c | 27 +++++++++++++++++++++++++--
2 files changed, 31 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c59c590e45c4..31b1b1dfb754 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7474,11 +7474,12 @@ enum {
#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
#define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
-#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
-#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
-#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
-#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
-#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
+#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
+#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
+#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
+#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
+#define CNP_PWM_CGE_GATING_DISABLE (1<<13)
+#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
/* CPU: FDI_TX */
#define _FDI_TXA_CTL 0x60100
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 88bbbc44c00d..5a4b41ea0c3a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8264,8 +8264,19 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
I915_WRITE(GEN7_MISCCPCTL, misccpctl);
}
+static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+ if (!HAS_PCH_CNP(dev_priv))
+ return;
+
+ /* Wa #1181 */
+ I915_WRITE(SOUTH_DSPCLK_GATE_D, CNP_PWM_CGE_GATING_DISABLE);
+}
+
static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
{
+ cnp_init_clock_gating(dev_priv);
+
/* This is not an Wa. Enable for better image quality */
I915_WRITE(_3D_CHICKEN3,
_MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
@@ -8285,6 +8296,16 @@ static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
SARBUNIT_CLKGATE_DIS);
}
+static void coffeelake_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+ cnp_init_clock_gating(dev_priv);
+ gen9_init_clock_gating(dev_priv);
+
+ /* WaFbcNukeOnHostModify:cfl */
+ I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+ ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
+}
+
static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
{
gen9_init_clock_gating(dev_priv);
@@ -8299,7 +8320,7 @@ static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
- /* WaFbcNukeOnHostModify:kbl,cfl */
+ /* WaFbcNukeOnHostModify:kbl */
I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
}
@@ -8767,9 +8788,11 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
if (IS_CANNONLAKE(dev_priv))
dev_priv->display.init_clock_gating = cannonlake_init_clock_gating;
+ else if (IS_COFFEELAKE(dev_priv))
+ dev_priv->display.init_clock_gating = coffeelake_init_clock_gating;
else if (IS_SKYLAKE(dev_priv))
dev_priv->display.init_clock_gating = skylake_init_clock_gating;
- else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
+ else if (IS_KABYLAKE(dev_priv))
dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
else if (IS_BROXTON(dev_priv))
dev_priv->display.init_clock_gating = bxt_init_clock_gating;
--
2.13.2
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/cnp: Wa 1181: Fix Backlight issue
2017-08-29 5:07 [PATCH] drm/i915/cnp: Wa 1181: Fix Backlight issue Rodrigo Vivi
@ 2017-08-29 5:28 ` Patchwork
2017-08-29 6:34 ` ✓ Fi.CI.IGT: " Patchwork
` (3 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2017-08-29 5:28 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnp: Wa 1181: Fix Backlight issue
URL : https://patchwork.freedesktop.org/series/29452/
State : success
== Summary ==
Series 29452v1 drm/i915/cnp: Wa 1181: Fix Backlight issue
https://patchwork.freedesktop.org/api/1.0/series/29452/revisions/1/mbox/
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
fail -> PASS (fi-snb-2600) fdo#100215
Subgroup basic-flip-after-cursor-varying-size:
fail -> PASS (fi-hsw-4770) fdo#102402 +1
Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip -> PASS (fi-skl-x1585l) fdo#101781
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:453s
fi-bdw-gvtdvm total:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:442s
fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:362s
fi-bsw-n3050 total:279 pass:243 dwarn:0 dfail:0 fail:0 skip:36 time:555s
fi-bwr-2160 total:279 pass:184 dwarn:0 dfail:0 fail:0 skip:95 time:251s
fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:523s
fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:527s
fi-byt-n2820 total:279 pass:250 dwarn:1 dfail:0 fail:0 skip:28 time:519s
fi-elk-e7500 total:279 pass:230 dwarn:0 dfail:0 fail:0 skip:49 time:441s
fi-glk-2a total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:614s
fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:444s
fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:426s
fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:428s
fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:510s
fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:473s
fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:478s
fi-kbl-7560u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:597s
fi-kbl-r total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:598s
fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:524s
fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:472s
fi-skl-6700k total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:478s
fi-skl-6770hq total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:490s
fi-skl-gvtdvm total:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:444s
fi-skl-x1585l total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:506s
fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:546s
fi-snb-2600 total:279 pass:249 dwarn:0 dfail:0 fail:1 skip:29 time:402s
ee53909d971df42daac0b870cf7c091f45f1f6b9 drm-tip: 2017y-08m-28d-15h-03m-59s UTC integration manifest
7bf9c172e305 drm/i915/cnp: Wa 1181: Fix Backlight issue
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5514/
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/cnp: Wa 1181: Fix Backlight issue
2017-08-29 5:07 [PATCH] drm/i915/cnp: Wa 1181: Fix Backlight issue Rodrigo Vivi
2017-08-29 5:28 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-08-29 6:34 ` Patchwork
2017-08-29 6:42 ` [PATCH] " Jani Nikula
` (2 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2017-08-29 6:34 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnp: Wa 1181: Fix Backlight issue
URL : https://patchwork.freedesktop.org/series/29452/
State : success
== Summary ==
Test kms_flip:
Subgroup plain-flip-ts-check:
fail -> PASS (shard-hsw)
shard-hsw total:2230 pass:1231 dwarn:0 dfail:0 fail:17 skip:982 time:9611s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5514/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/i915/cnp: Wa 1181: Fix Backlight issue
2017-08-29 5:07 [PATCH] drm/i915/cnp: Wa 1181: Fix Backlight issue Rodrigo Vivi
2017-08-29 5:28 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-08-29 6:34 ` ✓ Fi.CI.IGT: " Patchwork
@ 2017-08-29 6:42 ` Jani Nikula
2017-08-29 17:14 ` Vivi, Rodrigo
2017-08-31 4:52 ` Rodrigo Vivi
2017-08-31 11:55 ` ✓ Fi.CI.BAT: success for drm/i915/cnp: Wa 1181: Fix Backlight issue (rev2) Patchwork
2017-08-31 16:47 ` ✓ Fi.CI.IGT: " Patchwork
4 siblings, 2 replies; 10+ messages in thread
From: Jani Nikula @ 2017-08-29 6:42 UTC (permalink / raw)
To: intel-gfx; +Cc: Arthur J Runyan, Dhinakaran Pandiyan, Rodrigo Vivi
On Tue, 29 Aug 2017, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> This workaround fixes a CNL PCH bug when changing
> backlight from a lower frequency to a higher frequency.
>
> During random reboot cycles, display backlight seems to
> be off/ dim for 2-3 mins.
>
> The only functional change on this patch is to
> set bit 13 of 0xC2020 for CNL PCH.
>
> The rest of patch is organizing identation around
> those bits definitions and re-organizing CFL workarounds.
>
> Cc: Arthur J Runyan <arthur.j.runyan@intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 11 ++++++-----
> drivers/gpu/drm/i915/intel_pm.c | 27 +++++++++++++++++++++++++--
> 2 files changed, 31 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c59c590e45c4..31b1b1dfb754 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7474,11 +7474,12 @@ enum {
> #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
> #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
>
> -#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
> -#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
> -#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
> -#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
> -#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
> +#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
> +#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
> +#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
> +#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
> +#define CNP_PWM_CGE_GATING_DISABLE (1<<13)
Only add this one line, please don't reshuffle the rest.
> +#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
>
> /* CPU: FDI_TX */
> #define _FDI_TXA_CTL 0x60100
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 88bbbc44c00d..5a4b41ea0c3a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8264,8 +8264,19 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
> I915_WRITE(GEN7_MISCCPCTL, misccpctl);
> }
>
> +static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
> +{
> + if (!HAS_PCH_CNP(dev_priv))
> + return;
Is this for CFL without CNP?
BR,
Jani.
> +
> + /* Wa #1181 */
> + I915_WRITE(SOUTH_DSPCLK_GATE_D, CNP_PWM_CGE_GATING_DISABLE);
> +}
> +
> static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> + cnp_init_clock_gating(dev_priv);
> +
> /* This is not an Wa. Enable for better image quality */
> I915_WRITE(_3D_CHICKEN3,
> _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
> @@ -8285,6 +8296,16 @@ static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
> SARBUNIT_CLKGATE_DIS);
> }
>
> +static void coffeelake_init_clock_gating(struct drm_i915_private *dev_priv)
> +{
> + cnp_init_clock_gating(dev_priv);
> + gen9_init_clock_gating(dev_priv);
> +
> + /* WaFbcNukeOnHostModify:cfl */
> + I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> + ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
> +}
> +
> static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> gen9_init_clock_gating(dev_priv);
> @@ -8299,7 +8320,7 @@ static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
> I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
>
> - /* WaFbcNukeOnHostModify:kbl,cfl */
> + /* WaFbcNukeOnHostModify:kbl */
> I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
> }
> @@ -8767,9 +8788,11 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
> {
> if (IS_CANNONLAKE(dev_priv))
> dev_priv->display.init_clock_gating = cannonlake_init_clock_gating;
> + else if (IS_COFFEELAKE(dev_priv))
> + dev_priv->display.init_clock_gating = coffeelake_init_clock_gating;
> else if (IS_SKYLAKE(dev_priv))
> dev_priv->display.init_clock_gating = skylake_init_clock_gating;
> - else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
> + else if (IS_KABYLAKE(dev_priv))
> dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
> else if (IS_BROXTON(dev_priv))
> dev_priv->display.init_clock_gating = bxt_init_clock_gating;
--
Jani Nikula, Intel Open Source Technology Center
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/i915/cnp: Wa 1181: Fix Backlight issue
2017-08-29 6:42 ` [PATCH] " Jani Nikula
@ 2017-08-29 17:14 ` Vivi, Rodrigo
2017-08-31 4:52 ` Rodrigo Vivi
1 sibling, 0 replies; 10+ messages in thread
From: Vivi, Rodrigo @ 2017-08-29 17:14 UTC (permalink / raw)
To: jani.nikula; +Cc: intel-gfx, Runyan, Arthur J, Pandiyan, Dhinakaran
On Tue, 2017-08-29 at 09:42 +0300, Jani Nikula wrote:
> On Tue, 29 Aug 2017, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> > This workaround fixes a CNL PCH bug when changing
> > backlight from a lower frequency to a higher frequency.
> >
> > During random reboot cycles, display backlight seems to
> > be off/ dim for 2-3 mins.
> >
> > The only functional change on this patch is to
> > set bit 13 of 0xC2020 for CNL PCH.
> >
> > The rest of patch is organizing identation around
> > those bits definitions and re-organizing CFL workarounds.
> >
> > Cc: Arthur J Runyan <arthur.j.runyan@intel.com>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 11 ++++++-----
> > drivers/gpu/drm/i915/intel_pm.c | 27 +++++++++++++++++++++++++--
> > 2 files changed, 31 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index c59c590e45c4..31b1b1dfb754 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7474,11 +7474,12 @@ enum {
> > #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
> > #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
> >
> > -#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
> > -#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
> > -#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
> > -#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
> > -#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
> > +#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
> > +#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
> > +#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
> > +#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
> > +#define CNP_PWM_CGE_GATING_DISABLE (1<<13)
>
> Only add this one line, please don't reshuffle the rest.
yep... my momentary OCD took over and fixed indentation around what I
was touching to avoid extra patch...
>
> > +#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
> >
> > /* CPU: FDI_TX */
> > #define _FDI_TXA_CTL 0x60100
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 88bbbc44c00d..5a4b41ea0c3a 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -8264,8 +8264,19 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
> > I915_WRITE(GEN7_MISCCPCTL, misccpctl);
> > }
> >
> > +static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
> > +{
> > + if (!HAS_PCH_CNP(dev_priv))
> > + return;
>
> Is this for CFL without CNP?
Nope. CNP only.
So far we have CFL with KBP and CNP
and we have CNL with CNP but who know what we might have in the future,
so I preferred to skip inside the function instead of adding 2 ifs
outside and/or have to fix it later.
>
> BR,
> Jani.
>
> > +
> > + /* Wa #1181 */
> > + I915_WRITE(SOUTH_DSPCLK_GATE_D, CNP_PWM_CGE_GATING_DISABLE);
> > +}
> > +
> > static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
> > {
> > + cnp_init_clock_gating(dev_priv);
> > +
> > /* This is not an Wa. Enable for better image quality */
> > I915_WRITE(_3D_CHICKEN3,
> > _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
> > @@ -8285,6 +8296,16 @@ static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
> > SARBUNIT_CLKGATE_DIS);
> > }
> >
> > +static void coffeelake_init_clock_gating(struct drm_i915_private *dev_priv)
> > +{
> > + cnp_init_clock_gating(dev_priv);
> > + gen9_init_clock_gating(dev_priv);
> > +
> > + /* WaFbcNukeOnHostModify:cfl */
> > + I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> > + ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
> > +}
> > +
> > static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
> > {
> > gen9_init_clock_gating(dev_priv);
> > @@ -8299,7 +8320,7 @@ static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
> > I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> > GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
> >
> > - /* WaFbcNukeOnHostModify:kbl,cfl */
> > + /* WaFbcNukeOnHostModify:kbl */
> > I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> > ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
> > }
> > @@ -8767,9 +8788,11 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
> > {
> > if (IS_CANNONLAKE(dev_priv))
> > dev_priv->display.init_clock_gating = cannonlake_init_clock_gating;
> > + else if (IS_COFFEELAKE(dev_priv))
> > + dev_priv->display.init_clock_gating = coffeelake_init_clock_gating;
> > else if (IS_SKYLAKE(dev_priv))
> > dev_priv->display.init_clock_gating = skylake_init_clock_gating;
> > - else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
> > + else if (IS_KABYLAKE(dev_priv))
> > dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
> > else if (IS_BROXTON(dev_priv))
> > dev_priv->display.init_clock_gating = bxt_init_clock_gating;
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH] drm/i915/cnp: Wa 1181: Fix Backlight issue
2017-08-29 6:42 ` [PATCH] " Jani Nikula
2017-08-29 17:14 ` Vivi, Rodrigo
@ 2017-08-31 4:52 ` Rodrigo Vivi
2017-09-05 18:42 ` Pandiyan, Dhinakaran
1 sibling, 1 reply; 10+ messages in thread
From: Rodrigo Vivi @ 2017-08-31 4:52 UTC (permalink / raw)
To: intel-gfx
Cc: Jani Nikula, Arthur J Runyan, Dhinakaran Pandiyan, Vivi, Rodrigo
From: "Vivi, Rodrigo" <rodrigo.vivi@intel.com>
This workaround fixes a CNL PCH bug when changing
backlight from a lower frequency to a higher frequency.
During random reboot cycles, display backlight seems to
be off/ dim for 2-3 mins.
The only functional change on this patch is to
set bit 13 of 0xC2020 for CNL PCH.
The rest of patch is organizing identation around
those bits definitions and re-organizing CFL workarounds.
v2: Only add the bit that matters without touching others
around (Jani).
Rebase on top of clock gating functions rename.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Arthur J Runyan <arthur.j.runyan@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 27 +++++++++++++++++++++++++--
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e2908ae34004..bb3df56e447f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7482,6 +7482,7 @@ enum {
#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
+#define CNP_PWM_CGE_GATING_DISABLE (1<<13)
#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
/* CPU: FDI_TX */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4bdf1fb1df7e..3473b327519d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8264,8 +8264,19 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
I915_WRITE(GEN7_MISCCPCTL, misccpctl);
}
+static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+ if (!HAS_PCH_CNP(dev_priv))
+ return;
+
+ /* Wa #1181 */
+ I915_WRITE(SOUTH_DSPCLK_GATE_D, CNP_PWM_CGE_GATING_DISABLE);
+}
+
static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
{
+ cnp_init_clock_gating(dev_priv);
+
/* This is not an Wa. Enable for better image quality */
I915_WRITE(_3D_CHICKEN3,
_MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
@@ -8285,6 +8296,16 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
SARBUNIT_CLKGATE_DIS);
}
+static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+ cnp_init_clock_gating(dev_priv);
+ gen9_init_clock_gating(dev_priv);
+
+ /* WaFbcNukeOnHostModify:cfl */
+ I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+ ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
+}
+
static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
{
gen9_init_clock_gating(dev_priv);
@@ -8299,7 +8320,7 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
- /* WaFbcNukeOnHostModify:kbl,cfl */
+ /* WaFbcNukeOnHostModify:kbl */
I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
}
@@ -8767,9 +8788,11 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
if (IS_CANNONLAKE(dev_priv))
dev_priv->display.init_clock_gating = cnl_init_clock_gating;
+ else if (IS_COFFEELAKE(dev_priv))
+ dev_priv->display.init_clock_gating = cfl_init_clock_gating;
else if (IS_SKYLAKE(dev_priv))
dev_priv->display.init_clock_gating = skl_init_clock_gating;
- else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
+ else if (IS_KABYLAKE(dev_priv))
dev_priv->display.init_clock_gating = kbl_init_clock_gating;
else if (IS_BROXTON(dev_priv))
dev_priv->display.init_clock_gating = bxt_init_clock_gating;
--
2.13.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/i915/cnp: Wa 1181: Fix Backlight issue
2017-08-31 4:52 ` Rodrigo Vivi
@ 2017-09-05 18:42 ` Pandiyan, Dhinakaran
2017-09-05 19:16 ` Rodrigo Vivi
0 siblings, 1 reply; 10+ messages in thread
From: Pandiyan, Dhinakaran @ 2017-09-05 18:42 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: Nikula, Jani, intel-gfx, Runyan, Arthur J
On Wed, 2017-08-30 at 21:52 -0700, Rodrigo Vivi wrote:
> From: "Vivi, Rodrigo" <rodrigo.vivi@intel.com>
>
> This workaround fixes a CNL PCH bug when changing
> backlight from a lower frequency to a higher frequency.
>
> During random reboot cycles, display backlight seems to
> be off/ dim for 2-3 mins.
>
> The only functional change on this patch is to
> set bit 13 of 0xC2020 for CNL PCH.
>
> The rest of patch is organizing identation around
> those bits definitions and re-organizing CFL workarounds.
>
> v2: Only add the bit that matters without touching others
> around (Jani).
> Rebase on top of clock gating functions rename.
>
Checked against Bspec, patch looks correct.
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Arthur J Runyan <arthur.j.runyan@intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 27 +++++++++++++++++++++++++--
> 2 files changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e2908ae34004..bb3df56e447f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7482,6 +7482,7 @@ enum {
> #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
> #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
> #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
> +#define CNP_PWM_CGE_GATING_DISABLE (1<<13)
> #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
>
> /* CPU: FDI_TX */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4bdf1fb1df7e..3473b327519d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8264,8 +8264,19 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
> I915_WRITE(GEN7_MISCCPCTL, misccpctl);
> }
>
> +static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
> +{
> + if (!HAS_PCH_CNP(dev_priv))
> + return;
> +
> + /* Wa #1181 */
> + I915_WRITE(SOUTH_DSPCLK_GATE_D, CNP_PWM_CGE_GATING_DISABLE);
> +}
> +
> static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> + cnp_init_clock_gating(dev_priv);
> +
> /* This is not an Wa. Enable for better image quality */
> I915_WRITE(_3D_CHICKEN3,
> _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
> @@ -8285,6 +8296,16 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
> SARBUNIT_CLKGATE_DIS);
> }
>
> +static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
> +{
> + cnp_init_clock_gating(dev_priv);
> + gen9_init_clock_gating(dev_priv);
> +
> + /* WaFbcNukeOnHostModify:cfl */
> + I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> + ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
> +}
> +
> static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> gen9_init_clock_gating(dev_priv);
> @@ -8299,7 +8320,7 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
> I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
> GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
>
> - /* WaFbcNukeOnHostModify:kbl,cfl */
> + /* WaFbcNukeOnHostModify:kbl */
> I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
> }
> @@ -8767,9 +8788,11 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
> {
> if (IS_CANNONLAKE(dev_priv))
> dev_priv->display.init_clock_gating = cnl_init_clock_gating;
> + else if (IS_COFFEELAKE(dev_priv))
> + dev_priv->display.init_clock_gating = cfl_init_clock_gating;
> else if (IS_SKYLAKE(dev_priv))
> dev_priv->display.init_clock_gating = skl_init_clock_gating;
> - else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
> + else if (IS_KABYLAKE(dev_priv))
> dev_priv->display.init_clock_gating = kbl_init_clock_gating;
> else if (IS_BROXTON(dev_priv))
> dev_priv->display.init_clock_gating = bxt_init_clock_gating;
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/i915/cnp: Wa 1181: Fix Backlight issue
2017-09-05 18:42 ` Pandiyan, Dhinakaran
@ 2017-09-05 19:16 ` Rodrigo Vivi
0 siblings, 0 replies; 10+ messages in thread
From: Rodrigo Vivi @ 2017-09-05 19:16 UTC (permalink / raw)
To: Pandiyan, Dhinakaran
Cc: Nikula, Jani, intel-gfx, Runyan, Arthur J, Vivi, Rodrigo
On Tue, Sep 5, 2017 at 11:42 AM, Pandiyan, Dhinakaran
<dhinakaran.pandiyan@intel.com> wrote:
> On Wed, 2017-08-30 at 21:52 -0700, Rodrigo Vivi wrote:
>> From: "Vivi, Rodrigo" <rodrigo.vivi@intel.com>
>>
>> This workaround fixes a CNL PCH bug when changing
>> backlight from a lower frequency to a higher frequency.
>>
>> During random reboot cycles, display backlight seems to
>> be off/ dim for 2-3 mins.
>>
>> The only functional change on this patch is to
>> set bit 13 of 0xC2020 for CNL PCH.
>>
>> The rest of patch is organizing identation around
>> those bits definitions and re-organizing CFL workarounds.
>>
>> v2: Only add the bit that matters without touching others
>> around (Jani).
>> Rebase on top of clock gating functions rename.
>>
>
> Checked against Bspec, patch looks correct.
> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
merged to dinq. thanks for reviews and suggestions.
>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Arthur J Runyan <arthur.j.runyan@intel.com>
>> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 1 +
>> drivers/gpu/drm/i915/intel_pm.c | 27 +++++++++++++++++++++++++--
>> 2 files changed, 26 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index e2908ae34004..bb3df56e447f 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7482,6 +7482,7 @@ enum {
>> #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
>> #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
>> #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
>> +#define CNP_PWM_CGE_GATING_DISABLE (1<<13)
>> #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
>>
>> /* CPU: FDI_TX */
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 4bdf1fb1df7e..3473b327519d 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -8264,8 +8264,19 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
>> I915_WRITE(GEN7_MISCCPCTL, misccpctl);
>> }
>>
>> +static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
>> +{
>> + if (!HAS_PCH_CNP(dev_priv))
>> + return;
>> +
>> + /* Wa #1181 */
>> + I915_WRITE(SOUTH_DSPCLK_GATE_D, CNP_PWM_CGE_GATING_DISABLE);
>> +}
>> +
>> static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
>> {
>> + cnp_init_clock_gating(dev_priv);
>> +
>> /* This is not an Wa. Enable for better image quality */
>> I915_WRITE(_3D_CHICKEN3,
>> _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
>> @@ -8285,6 +8296,16 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
>> SARBUNIT_CLKGATE_DIS);
>> }
>>
>> +static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
>> +{
>> + cnp_init_clock_gating(dev_priv);
>> + gen9_init_clock_gating(dev_priv);
>> +
>> + /* WaFbcNukeOnHostModify:cfl */
>> + I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>> + ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
>> +}
>> +
>> static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
>> {
>> gen9_init_clock_gating(dev_priv);
>> @@ -8299,7 +8320,7 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
>> I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
>> GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
>>
>> - /* WaFbcNukeOnHostModify:kbl,cfl */
>> + /* WaFbcNukeOnHostModify:kbl */
>> I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>> ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
>> }
>> @@ -8767,9 +8788,11 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>> {
>> if (IS_CANNONLAKE(dev_priv))
>> dev_priv->display.init_clock_gating = cnl_init_clock_gating;
>> + else if (IS_COFFEELAKE(dev_priv))
>> + dev_priv->display.init_clock_gating = cfl_init_clock_gating;
>> else if (IS_SKYLAKE(dev_priv))
>> dev_priv->display.init_clock_gating = skl_init_clock_gating;
>> - else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
>> + else if (IS_KABYLAKE(dev_priv))
>> dev_priv->display.init_clock_gating = kbl_init_clock_gating;
>> else if (IS_BROXTON(dev_priv))
>> dev_priv->display.init_clock_gating = bxt_init_clock_gating;
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/cnp: Wa 1181: Fix Backlight issue (rev2)
2017-08-29 5:07 [PATCH] drm/i915/cnp: Wa 1181: Fix Backlight issue Rodrigo Vivi
` (2 preceding siblings ...)
2017-08-29 6:42 ` [PATCH] " Jani Nikula
@ 2017-08-31 11:55 ` Patchwork
2017-08-31 16:47 ` ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2017-08-31 11:55 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnp: Wa 1181: Fix Backlight issue (rev2)
URL : https://patchwork.freedesktop.org/series/29452/
State : success
== Summary ==
Series 29452v2 drm/i915/cnp: Wa 1181: Fix Backlight issue
https://patchwork.freedesktop.org/api/1.0/series/29452/revisions/2/mbox/
Test kms_cursor_legacy:
Subgroup basic-flip-after-cursor-varying-size:
pass -> FAIL (fi-hsw-4770) fdo#102402 +1
Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip -> PASS (fi-skl-x1585l) fdo#101781
fdo#102402 https://bugs.freedesktop.org/show_bug.cgi?id=102402
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
fi-bdw-5557u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:461s
fi-bdw-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:442s
fi-blb-e6850 total:288 pass:224 dwarn:1 dfail:0 fail:0 skip:63 time:365s
fi-bsw-n3050 total:288 pass:243 dwarn:0 dfail:0 fail:0 skip:45 time:558s
fi-bwr-2160 total:288 pass:184 dwarn:0 dfail:0 fail:0 skip:104 time:255s
fi-bxt-j4205 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:522s
fi-byt-j1900 total:288 pass:254 dwarn:1 dfail:0 fail:0 skip:33 time:524s
fi-byt-n2820 total:288 pass:250 dwarn:1 dfail:0 fail:0 skip:37 time:514s
fi-elk-e7500 total:288 pass:230 dwarn:0 dfail:0 fail:0 skip:58 time:437s
fi-glk-2a total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:613s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:2 skip:25 time:461s
fi-hsw-4770r total:288 pass:263 dwarn:0 dfail:0 fail:0 skip:25 time:426s
fi-ilk-650 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:424s
fi-ivb-3520m total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:499s
fi-ivb-3770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:474s
fi-kbl-7500u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:480s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:597s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:597s
fi-pnv-d510 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:524s
fi-skl-6260u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:471s
fi-skl-6700k total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:534s
fi-skl-6770hq total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:491s
fi-skl-gvtdvm total:288 pass:266 dwarn:0 dfail:0 fail:0 skip:22 time:445s
fi-skl-x1585l total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:505s
fi-snb-2520m total:288 pass:251 dwarn:0 dfail:0 fail:0 skip:37 time:553s
fi-snb-2600 total:288 pass:249 dwarn:0 dfail:0 fail:1 skip:38 time:403s
c399d43adc55a49d028d24ce7cdacc1823a4f159 drm-tip: 2017y-08m-31d-07h-25m-28s UTC integration manifest
c1ab2232cf79 drm/i915/cnp: Wa 1181: Fix Backlight issue
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5547/
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^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/cnp: Wa 1181: Fix Backlight issue (rev2)
2017-08-29 5:07 [PATCH] drm/i915/cnp: Wa 1181: Fix Backlight issue Rodrigo Vivi
` (3 preceding siblings ...)
2017-08-31 11:55 ` ✓ Fi.CI.BAT: success for drm/i915/cnp: Wa 1181: Fix Backlight issue (rev2) Patchwork
@ 2017-08-31 16:47 ` Patchwork
4 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2017-08-31 16:47 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnp: Wa 1181: Fix Backlight issue (rev2)
URL : https://patchwork.freedesktop.org/series/29452/
State : success
== Summary ==
Test perf:
Subgroup blocking:
pass -> FAIL (shard-hsw) fdo#102252
Test kms_setmode:
Subgroup basic:
pass -> FAIL (shard-hsw) fdo#99912
Test kms_flip:
Subgroup plain-flip-fb-recreate:
fail -> PASS (shard-hsw)
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
shard-hsw total:2265 pass:1230 dwarn:0 dfail:0 fail:19 skip:1016 time:9632s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5547/shards.html
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^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2017-09-05 19:16 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-08-29 5:07 [PATCH] drm/i915/cnp: Wa 1181: Fix Backlight issue Rodrigo Vivi
2017-08-29 5:28 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-08-29 6:34 ` ✓ Fi.CI.IGT: " Patchwork
2017-08-29 6:42 ` [PATCH] " Jani Nikula
2017-08-29 17:14 ` Vivi, Rodrigo
2017-08-31 4:52 ` Rodrigo Vivi
2017-09-05 18:42 ` Pandiyan, Dhinakaran
2017-09-05 19:16 ` Rodrigo Vivi
2017-08-31 11:55 ` ✓ Fi.CI.BAT: success for drm/i915/cnp: Wa 1181: Fix Backlight issue (rev2) Patchwork
2017-08-31 16:47 ` ✓ Fi.CI.IGT: " Patchwork
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