* [PATCH v8 01/38] drm/i915/icl: Move dsi host init code to common file
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-30 11:56 ` [PATCH v8 02/38] drm/i915/dsi: move connector mode functions " Jani Nikula
` (41 subsequent siblings)
42 siblings, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch moves intl_dsi_host_init() code to intel_dsi.c so that legacy
and gen11 DSI code can share this code.
v2 by Jani:
- Move the shared stuff to intel_dsi.c
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c | 34 ++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_dsi.h | 3 +++
drivers/gpu/drm/i915/vlv_dsi.c | 36 ++----------------------------------
3 files changed, 39 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index a32cc1f4b384..97e04c272612 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -28,3 +28,37 @@ int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi)
return 200;
}
}
+
+struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
+ const struct mipi_dsi_host_ops *funcs,
+ enum port port)
+{
+ struct intel_dsi_host *host;
+ struct mipi_dsi_device *device;
+
+ host = kzalloc(sizeof(*host), GFP_KERNEL);
+ if (!host)
+ return NULL;
+
+ host->base.ops = funcs;
+ host->intel_dsi = intel_dsi;
+ host->port = port;
+
+ /*
+ * We should call mipi_dsi_host_register(&host->base) here, but we don't
+ * have a host->dev, and we don't have OF stuff either. So just use the
+ * dsi framework as a library and hope for the best. Create the dsi
+ * devices by ourselves here too. Need to be careful though, because we
+ * don't initialize any of the driver model devices here.
+ */
+ device = kzalloc(sizeof(*device), GFP_KERNEL);
+ if (!device) {
+ kfree(host);
+ return NULL;
+ }
+
+ device->host = &host->base;
+ host->device = device;
+
+ return host;
+}
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 14567929de9a..09f0fa9ccc7d 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -152,6 +152,9 @@ int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi);
/* vlv_dsi.c */
void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
+struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
+ const struct mipi_dsi_host_ops *funcs,
+ enum port port);
/* vlv_dsi_pll.c */
int vlv_dsi_pll_compute(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
index ee0cd5d0bf91..cbb935a9acf3 100644
--- a/drivers/gpu/drm/i915/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/vlv_dsi.c
@@ -206,39 +206,6 @@ static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
.transfer = intel_dsi_host_transfer,
};
-static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
- enum port port)
-{
- struct intel_dsi_host *host;
- struct mipi_dsi_device *device;
-
- host = kzalloc(sizeof(*host), GFP_KERNEL);
- if (!host)
- return NULL;
-
- host->base.ops = &intel_dsi_host_ops;
- host->intel_dsi = intel_dsi;
- host->port = port;
-
- /*
- * We should call mipi_dsi_host_register(&host->base) here, but we don't
- * have a host->dev, and we don't have OF stuff either. So just use the
- * dsi framework as a library and hope for the best. Create the dsi
- * devices by ourselves here too. Need to be careful though, because we
- * don't initialize any of the driver model devices here.
- */
- device = kzalloc(sizeof(*device), GFP_KERNEL);
- if (!device) {
- kfree(host);
- return NULL;
- }
-
- device->host = &host->base;
- host->device = device;
-
- return host;
-}
-
/*
* send a video mode command
*
@@ -1768,7 +1735,8 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
for_each_dsi_port(port, intel_dsi->ports) {
struct intel_dsi_host *host;
- host = intel_dsi_host_init(intel_dsi, port);
+ host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops,
+ port);
if (!host)
goto err;
--
2.11.0
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 75+ messages in thread* [PATCH v8 02/38] drm/i915/dsi: move connector mode functions to common file
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
2018-10-30 11:56 ` [PATCH v8 01/38] drm/i915/icl: Move dsi host init code to common file Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-31 9:20 ` Madhav Chauhan
2018-10-30 11:56 ` [PATCH v8 03/38] drm/i915/icl: Set max return packet size for DSI panel Jani Nikula
` (40 subsequent siblings)
42 siblings, 1 reply; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
Move DSI connector functions to intel_dsi.c and make them available to
both legacy and ICL DSI.
v2 by Jani:
- Move the functions to intel_dsi.c
- Don't reuse intel_dsi_connector_destroy()
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c | 47 +++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_dsi.h | 3 +++
drivers/gpu/drm/i915/vlv_dsi.c | 48 ----------------------------------------
3 files changed, 50 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 97e04c272612..b9d5ef79015e 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -29,6 +29,53 @@ int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi)
}
}
+int intel_dsi_get_modes(struct drm_connector *connector)
+{
+ struct intel_connector *intel_connector = to_intel_connector(connector);
+ struct drm_display_mode *mode;
+
+ DRM_DEBUG_KMS("\n");
+
+ if (!intel_connector->panel.fixed_mode) {
+ DRM_DEBUG_KMS("no fixed mode\n");
+ return 0;
+ }
+
+ mode = drm_mode_duplicate(connector->dev,
+ intel_connector->panel.fixed_mode);
+ if (!mode) {
+ DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
+ return 0;
+ }
+
+ drm_mode_probed_add(connector, mode);
+ return 1;
+}
+
+enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+{
+ struct intel_connector *intel_connector = to_intel_connector(connector);
+ const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
+ int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
+
+ DRM_DEBUG_KMS("\n");
+
+ if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
+ return MODE_NO_DBLESCAN;
+
+ if (fixed_mode) {
+ if (mode->hdisplay > fixed_mode->hdisplay)
+ return MODE_PANEL;
+ if (mode->vdisplay > fixed_mode->vdisplay)
+ return MODE_PANEL;
+ if (fixed_mode->clock > max_dotclk)
+ return MODE_CLOCK_HIGH;
+ }
+
+ return MODE_OK;
+}
+
struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
const struct mipi_dsi_host_ops *funcs,
enum port port)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 09f0fa9ccc7d..10fd1582a8e2 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -152,6 +152,9 @@ int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi);
/* vlv_dsi.c */
void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
+int intel_dsi_get_modes(struct drm_connector *connector);
+enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode);
struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
const struct mipi_dsi_host_ops *funcs,
enum port port);
diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
index cbb935a9acf3..bab87b62bc2d 100644
--- a/drivers/gpu/drm/i915/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/vlv_dsi.c
@@ -1212,31 +1212,6 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
}
}
-static enum drm_mode_status
-intel_dsi_mode_valid(struct drm_connector *connector,
- struct drm_display_mode *mode)
-{
- struct intel_connector *intel_connector = to_intel_connector(connector);
- const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
- int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
-
- DRM_DEBUG_KMS("\n");
-
- if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
- return MODE_NO_DBLESCAN;
-
- if (fixed_mode) {
- if (mode->hdisplay > fixed_mode->hdisplay)
- return MODE_PANEL;
- if (mode->vdisplay > fixed_mode->vdisplay)
- return MODE_PANEL;
- if (fixed_mode->clock > max_dotclk)
- return MODE_CLOCK_HIGH;
- }
-
- return MODE_OK;
-}
-
/* return txclkesc cycles in terms of divider and duration in us */
static u16 txclkesc(u32 divider, unsigned int us)
{
@@ -1559,29 +1534,6 @@ static void intel_dsi_unprepare(struct intel_encoder *encoder)
}
}
-static int intel_dsi_get_modes(struct drm_connector *connector)
-{
- struct intel_connector *intel_connector = to_intel_connector(connector);
- struct drm_display_mode *mode;
-
- DRM_DEBUG_KMS("\n");
-
- if (!intel_connector->panel.fixed_mode) {
- DRM_DEBUG_KMS("no fixed mode\n");
- return 0;
- }
-
- mode = drm_mode_duplicate(connector->dev,
- intel_connector->panel.fixed_mode);
- if (!mode) {
- DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
- return 0;
- }
-
- drm_mode_probed_add(connector, mode);
- return 1;
-}
-
static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
{
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
--
2.11.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [PATCH v8 02/38] drm/i915/dsi: move connector mode functions to common file
2018-10-30 11:56 ` [PATCH v8 02/38] drm/i915/dsi: move connector mode functions " Jani Nikula
@ 2018-10-31 9:20 ` Madhav Chauhan
0 siblings, 0 replies; 75+ messages in thread
From: Madhav Chauhan @ 2018-10-31 9:20 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 10/30/2018 5:26 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> Move DSI connector functions to intel_dsi.c and make them available to
> both legacy and ICL DSI.
>
> v2 by Jani:
> - Move the functions to intel_dsi.c
> - Don't reuse intel_dsi_connector_destroy()
Patch 1 & 2 v2 changes, i.e. code movement to intel_dsi.c
looks fine to me.
Regards,
Madhav
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 47 +++++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_dsi.h | 3 +++
> drivers/gpu/drm/i915/vlv_dsi.c | 48 ----------------------------------------
> 3 files changed, 50 insertions(+), 48 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 97e04c272612..b9d5ef79015e 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -29,6 +29,53 @@ int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi)
> }
> }
>
> +int intel_dsi_get_modes(struct drm_connector *connector)
> +{
> + struct intel_connector *intel_connector = to_intel_connector(connector);
> + struct drm_display_mode *mode;
> +
> + DRM_DEBUG_KMS("\n");
> +
> + if (!intel_connector->panel.fixed_mode) {
> + DRM_DEBUG_KMS("no fixed mode\n");
> + return 0;
> + }
> +
> + mode = drm_mode_duplicate(connector->dev,
> + intel_connector->panel.fixed_mode);
> + if (!mode) {
> + DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
> + return 0;
> + }
> +
> + drm_mode_probed_add(connector, mode);
> + return 1;
> +}
> +
> +enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
> + struct drm_display_mode *mode)
> +{
> + struct intel_connector *intel_connector = to_intel_connector(connector);
> + const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
> + int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
> +
> + DRM_DEBUG_KMS("\n");
> +
> + if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
> + return MODE_NO_DBLESCAN;
> +
> + if (fixed_mode) {
> + if (mode->hdisplay > fixed_mode->hdisplay)
> + return MODE_PANEL;
> + if (mode->vdisplay > fixed_mode->vdisplay)
> + return MODE_PANEL;
> + if (fixed_mode->clock > max_dotclk)
> + return MODE_CLOCK_HIGH;
> + }
> +
> + return MODE_OK;
> +}
> +
> struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
> const struct mipi_dsi_host_ops *funcs,
> enum port port)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index 09f0fa9ccc7d..10fd1582a8e2 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -152,6 +152,9 @@ int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi);
> /* vlv_dsi.c */
> void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
> enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
> +int intel_dsi_get_modes(struct drm_connector *connector);
> +enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
> + struct drm_display_mode *mode);
> struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
> const struct mipi_dsi_host_ops *funcs,
> enum port port);
> diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
> index cbb935a9acf3..bab87b62bc2d 100644
> --- a/drivers/gpu/drm/i915/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/vlv_dsi.c
> @@ -1212,31 +1212,6 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
> }
> }
>
> -static enum drm_mode_status
> -intel_dsi_mode_valid(struct drm_connector *connector,
> - struct drm_display_mode *mode)
> -{
> - struct intel_connector *intel_connector = to_intel_connector(connector);
> - const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
> - int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
> -
> - DRM_DEBUG_KMS("\n");
> -
> - if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
> - return MODE_NO_DBLESCAN;
> -
> - if (fixed_mode) {
> - if (mode->hdisplay > fixed_mode->hdisplay)
> - return MODE_PANEL;
> - if (mode->vdisplay > fixed_mode->vdisplay)
> - return MODE_PANEL;
> - if (fixed_mode->clock > max_dotclk)
> - return MODE_CLOCK_HIGH;
> - }
> -
> - return MODE_OK;
> -}
> -
> /* return txclkesc cycles in terms of divider and duration in us */
> static u16 txclkesc(u32 divider, unsigned int us)
> {
> @@ -1559,29 +1534,6 @@ static void intel_dsi_unprepare(struct intel_encoder *encoder)
> }
> }
>
> -static int intel_dsi_get_modes(struct drm_connector *connector)
> -{
> - struct intel_connector *intel_connector = to_intel_connector(connector);
> - struct drm_display_mode *mode;
> -
> - DRM_DEBUG_KMS("\n");
> -
> - if (!intel_connector->panel.fixed_mode) {
> - DRM_DEBUG_KMS("no fixed mode\n");
> - return 0;
> - }
> -
> - mode = drm_mode_duplicate(connector->dev,
> - intel_connector->panel.fixed_mode);
> - if (!mode) {
> - DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
> - return 0;
> - }
> -
> - drm_mode_probed_add(connector, mode);
> - return 1;
> -}
> -
> static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
> {
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v8 03/38] drm/i915/icl: Set max return packet size for DSI panel
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
2018-10-30 11:56 ` [PATCH v8 01/38] drm/i915/icl: Move dsi host init code to common file Jani Nikula
2018-10-30 11:56 ` [PATCH v8 02/38] drm/i915/dsi: move connector mode functions " Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-31 9:24 ` Madhav Chauhan
2018-10-30 11:56 ` [PATCH v8 04/38] drm/i915/icl: Power on " Jani Nikula
` (39 subsequent siblings)
42 siblings, 1 reply; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch programs maximum size of the payload transmitted
from peripheral back to the host processor using short packet
as a part of panel programming.
v2: Rebase
v3 by Jani:
- Add FIXME note.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 216a1753d246..9c424adc8b75 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -25,6 +25,7 @@
* Jani Nikula <jani.nikula@intel.com>
*/
+#include <drm/drm_mipi_dsi.h>
#include "intel_dsi.h"
static enum transcoder dsi_port_to_transcoder(enum port port)
@@ -636,6 +637,35 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
gen11_dsi_configure_transcoder(encoder, pipe_config);
}
+static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ struct mipi_dsi_device *dsi;
+ enum port port;
+ enum transcoder dsi_trans;
+ u32 tmp;
+ int ret;
+
+ /* set maximum return packet size */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+
+ /*
+ * FIXME: This uses the number of DW's currently in the payload
+ * receive queue. This is probably not what we want here.
+ */
+ tmp = I915_READ(DSI_CMD_RXCTL(dsi_trans));
+ tmp &= NUMBER_RX_PLOAD_DW_MASK;
+ /* multiply "Number Rx Payload DW" by 4 to get max value */
+ tmp = tmp * 4;
+ dsi = intel_dsi->dsi_hosts[port]->device;
+ ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
+ if (ret < 0)
+ DRM_ERROR("error setting max return pkt size%d\n", tmp);
+ }
+}
+
static void __attribute__((unused))
gen11_dsi_pre_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config,
@@ -650,6 +680,9 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
/* step4: enable DSI port and DPHY */
gen11_dsi_enable_port_and_phy(encoder, pipe_config);
+ /* step5: program and powerup panel */
+ gen11_dsi_powerup_panel(encoder);
+
/* step6c: configure transcoder timings */
gen11_dsi_set_transcoder_timings(encoder, pipe_config);
--
2.11.0
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^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [PATCH v8 03/38] drm/i915/icl: Set max return packet size for DSI panel
2018-10-30 11:56 ` [PATCH v8 03/38] drm/i915/icl: Set max return packet size for DSI panel Jani Nikula
@ 2018-10-31 9:24 ` Madhav Chauhan
2018-10-31 9:40 ` Jani Nikula
0 siblings, 1 reply; 75+ messages in thread
From: Madhav Chauhan @ 2018-10-31 9:24 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 10/30/2018 5:26 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch programs maximum size of the payload transmitted
> from peripheral back to the host processor using short packet
> as a part of panel programming.
>
> v2: Rebase
>
> v3 by Jani:
> - Add FIXME note.
Looks OK to me.
Regards,
Madhav
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 33 +++++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index 216a1753d246..9c424adc8b75 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -25,6 +25,7 @@
> * Jani Nikula <jani.nikula@intel.com>
> */
>
> +#include <drm/drm_mipi_dsi.h>
> #include "intel_dsi.h"
>
> static enum transcoder dsi_port_to_transcoder(enum port port)
> @@ -636,6 +637,35 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> gen11_dsi_configure_transcoder(encoder, pipe_config);
> }
>
> +static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + struct mipi_dsi_device *dsi;
> + enum port port;
> + enum transcoder dsi_trans;
> + u32 tmp;
> + int ret;
> +
> + /* set maximum return packet size */
> + for_each_dsi_port(port, intel_dsi->ports) {
> + dsi_trans = dsi_port_to_transcoder(port);
> +
> + /*
> + * FIXME: This uses the number of DW's currently in the payload
> + * receive queue. This is probably not what we want here.
> + */
> + tmp = I915_READ(DSI_CMD_RXCTL(dsi_trans));
> + tmp &= NUMBER_RX_PLOAD_DW_MASK;
> + /* multiply "Number Rx Payload DW" by 4 to get max value */
> + tmp = tmp * 4;
> + dsi = intel_dsi->dsi_hosts[port]->device;
> + ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
> + if (ret < 0)
> + DRM_ERROR("error setting max return pkt size%d\n", tmp);
> + }
> +}
> +
> static void __attribute__((unused))
> gen11_dsi_pre_enable(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config,
> @@ -650,6 +680,9 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
> /* step4: enable DSI port and DPHY */
> gen11_dsi_enable_port_and_phy(encoder, pipe_config);
>
> + /* step5: program and powerup panel */
> + gen11_dsi_powerup_panel(encoder);
> +
> /* step6c: configure transcoder timings */
> gen11_dsi_set_transcoder_timings(encoder, pipe_config);
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [PATCH v8 03/38] drm/i915/icl: Set max return packet size for DSI panel
2018-10-31 9:24 ` Madhav Chauhan
@ 2018-10-31 9:40 ` Jani Nikula
0 siblings, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-10-31 9:40 UTC (permalink / raw)
To: Madhav Chauhan, intel-gfx
On Wed, 31 Oct 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> On 10/30/2018 5:26 PM, Jani Nikula wrote:
>> From: Madhav Chauhan <madhav.chauhan@intel.com>
>>
>> This patch programs maximum size of the payload transmitted
>> from peripheral back to the host processor using short packet
>> as a part of panel programming.
>>
>> v2: Rebase
>>
>> v3 by Jani:
>> - Add FIXME note.
>
> Looks OK to me.
Thanks, pushed patches 1-3 to dinq.
BR,
Jani.
>
> Regards,
> Madhav
>
>>
>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/icl_dsi.c | 33 +++++++++++++++++++++++++++++++++
>> 1 file changed, 33 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
>> index 216a1753d246..9c424adc8b75 100644
>> --- a/drivers/gpu/drm/i915/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>> @@ -25,6 +25,7 @@
>> * Jani Nikula <jani.nikula@intel.com>
>> */
>>
>> +#include <drm/drm_mipi_dsi.h>
>> #include "intel_dsi.h"
>>
>> static enum transcoder dsi_port_to_transcoder(enum port port)
>> @@ -636,6 +637,35 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
>> gen11_dsi_configure_transcoder(encoder, pipe_config);
>> }
>>
>> +static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
>> +{
>> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>> + struct mipi_dsi_device *dsi;
>> + enum port port;
>> + enum transcoder dsi_trans;
>> + u32 tmp;
>> + int ret;
>> +
>> + /* set maximum return packet size */
>> + for_each_dsi_port(port, intel_dsi->ports) {
>> + dsi_trans = dsi_port_to_transcoder(port);
>> +
>> + /*
>> + * FIXME: This uses the number of DW's currently in the payload
>> + * receive queue. This is probably not what we want here.
>> + */
>> + tmp = I915_READ(DSI_CMD_RXCTL(dsi_trans));
>> + tmp &= NUMBER_RX_PLOAD_DW_MASK;
>> + /* multiply "Number Rx Payload DW" by 4 to get max value */
>> + tmp = tmp * 4;
>> + dsi = intel_dsi->dsi_hosts[port]->device;
>> + ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
>> + if (ret < 0)
>> + DRM_ERROR("error setting max return pkt size%d\n", tmp);
>> + }
>> +}
>> +
>> static void __attribute__((unused))
>> gen11_dsi_pre_enable(struct intel_encoder *encoder,
>> const struct intel_crtc_state *pipe_config,
>> @@ -650,6 +680,9 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
>> /* step4: enable DSI port and DPHY */
>> gen11_dsi_enable_port_and_phy(encoder, pipe_config);
>>
>> + /* step5: program and powerup panel */
>> + gen11_dsi_powerup_panel(encoder);
>> +
>> /* step6c: configure transcoder timings */
>> gen11_dsi_set_transcoder_timings(encoder, pipe_config);
>>
>
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v8 04/38] drm/i915/icl: Power on DSI panel
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (2 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 03/38] drm/i915/icl: Set max return packet size for DSI panel Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-31 9:42 ` Jani Nikula
2018-10-30 11:56 ` [PATCH v8 05/38] drm/i915/icl: Wait for header/payload credits release Jani Nikula
` (38 subsequent siblings)
42 siblings, 1 reply; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch execute poweron, deassert reset, display on
VBT sequences and send TURN_ON DSI command to panel for
powering it up.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 9c424adc8b75..d9c91001f107 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -664,6 +664,13 @@ static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
if (ret < 0)
DRM_ERROR("error setting max return pkt size%d\n", tmp);
}
+
+ /* panel power on related mipi dsi vbt sequences */
+ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
+ intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
+ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
+ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
+ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
}
static void __attribute__((unused))
--
2.11.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [PATCH v8 04/38] drm/i915/icl: Power on DSI panel
2018-10-30 11:56 ` [PATCH v8 04/38] drm/i915/icl: Power on " Jani Nikula
@ 2018-10-31 9:42 ` Jani Nikula
0 siblings, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-10-31 9:42 UTC (permalink / raw)
To: intel-gfx
On Tue, 30 Oct 2018, Jani Nikula <jani.nikula@intel.com> wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch execute poweron, deassert reset, display on
> VBT sequences and send TURN_ON DSI command to panel for
> powering it up.
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Pushed to dinq.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index 9c424adc8b75..d9c91001f107 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -664,6 +664,13 @@ static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
> if (ret < 0)
> DRM_ERROR("error setting max return pkt size%d\n", tmp);
> }
> +
> + /* panel power on related mipi dsi vbt sequences */
> + intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
> + intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
> + intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
> + intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
> + intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
> }
>
> static void __attribute__((unused))
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v8 05/38] drm/i915/icl: Wait for header/payload credits release
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (3 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 04/38] drm/i915/icl: Power on " Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-31 10:06 ` Madhav Chauhan
2018-10-30 11:56 ` [PATCH v8 06/38] drm/i915/icl: Turn ON panel backlight Jani Nikula
` (37 subsequent siblings)
42 siblings, 1 reply; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
Driver needs payload/header credits for sending any command
and data over DSI link. These credits are released once command
or data sent to link. This patch adds functions to wait for releasing
of payload and header credits.
As per BSPEC, driver needs to ensure that all of commands/data
has been dispatched to panel before the transcoder is enabled.
This patch implement those steps i.e. sending NOP DCS command,
wait for header/payload credit to be released etc.
v2 by Jani:
- squash the credit wait helpers patch with the first user
- pass dev_priv to the credit wait helpers
- bikeshed credit helper names
- wait for *at least* the current maximum number of credits
- indentation fix
- add helpers for credits available
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 74 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index d9c91001f107..0f0447b6b1be 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -28,6 +28,36 @@
#include <drm/drm_mipi_dsi.h>
#include "intel_dsi.h"
+static inline int header_credits_available(struct drm_i915_private *dev_priv,
+ enum transcoder dsi_trans)
+{
+ return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
+ >> FREE_HEADER_CREDIT_SHIFT;
+}
+
+static inline int payload_credits_available(struct drm_i915_private *dev_priv,
+ enum transcoder dsi_trans)
+{
+ return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
+ >> FREE_PLOAD_CREDIT_SHIFT;
+}
+
+static void wait_for_header_credits(struct drm_i915_private *dev_priv,
+ enum transcoder dsi_trans)
+{
+ if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
+ MAX_HEADER_CREDIT, 100))
+ DRM_ERROR("DSI header credits not released\n");
+}
+
+static void wait_for_payload_credits(struct drm_i915_private *dev_priv,
+ enum transcoder dsi_trans)
+{
+ if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
+ MAX_PLOAD_CREDIT, 100))
+ DRM_ERROR("DSI payload credits not released\n");
+}
+
static enum transcoder dsi_port_to_transcoder(enum port port)
{
if (port == PORT_A)
@@ -36,6 +66,47 @@ static enum transcoder dsi_port_to_transcoder(enum port port)
return TRANSCODER_DSI_1;
}
+static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ struct mipi_dsi_device *dsi;
+ enum port port;
+ enum transcoder dsi_trans;
+ int ret;
+
+ /* wait for header/payload credits to be released */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ wait_for_header_credits(dev_priv, dsi_trans);
+ wait_for_payload_credits(dev_priv, dsi_trans);
+ }
+
+ /* send nop DCS command */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi = intel_dsi->dsi_hosts[port]->device;
+ dsi->mode_flags |= MIPI_DSI_MODE_LPM;
+ dsi->channel = 0;
+ ret = mipi_dsi_dcs_nop(dsi);
+ if (ret < 0)
+ DRM_ERROR("error sending DCS NOP command\n");
+ }
+
+ /* wait for header credits to be released */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ wait_for_header_credits(dev_priv, dsi_trans);
+ }
+
+ /* wait for LP TX in progress bit to be cleared */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ if (wait_for_us(!(I915_READ(DSI_LP_MSG(dsi_trans)) &
+ LPTX_IN_PROGRESS), 20))
+ DRM_ERROR("LPTX bit not cleared\n");
+ }
+}
+
static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -671,6 +742,9 @@ static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
+
+ /* ensure all panel commands dispatched before enabling transcoder */
+ wait_for_cmds_dispatched_to_panel(encoder);
}
static void __attribute__((unused))
--
2.11.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [PATCH v8 05/38] drm/i915/icl: Wait for header/payload credits release
2018-10-30 11:56 ` [PATCH v8 05/38] drm/i915/icl: Wait for header/payload credits release Jani Nikula
@ 2018-10-31 10:06 ` Madhav Chauhan
0 siblings, 0 replies; 75+ messages in thread
From: Madhav Chauhan @ 2018-10-31 10:06 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 10/30/2018 5:26 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> Driver needs payload/header credits for sending any command
> and data over DSI link. These credits are released once command
> or data sent to link. This patch adds functions to wait for releasing
> of payload and header credits.
>
> As per BSPEC, driver needs to ensure that all of commands/data
> has been dispatched to panel before the transcoder is enabled.
> This patch implement those steps i.e. sending NOP DCS command,
> wait for header/payload credit to be released etc.
>
> v2 by Jani:
> - squash the credit wait helpers patch with the first user
> - pass dev_priv to the credit wait helpers
> - bikeshed credit helper names
> - wait for *at least* the current maximum number of credits
> - indentation fix
> - add helpers for credits available
This is good optimization, thanks. Looks good.
Regards,
Madhav
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 74 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 74 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index d9c91001f107..0f0447b6b1be 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -28,6 +28,36 @@
> #include <drm/drm_mipi_dsi.h>
> #include "intel_dsi.h"
>
> +static inline int header_credits_available(struct drm_i915_private *dev_priv,
> + enum transcoder dsi_trans)
> +{
> + return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
> + >> FREE_HEADER_CREDIT_SHIFT;
> +}
> +
> +static inline int payload_credits_available(struct drm_i915_private *dev_priv,
> + enum transcoder dsi_trans)
> +{
> + return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
> + >> FREE_PLOAD_CREDIT_SHIFT;
> +}
> +
> +static void wait_for_header_credits(struct drm_i915_private *dev_priv,
> + enum transcoder dsi_trans)
> +{
> + if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
> + MAX_HEADER_CREDIT, 100))
> + DRM_ERROR("DSI header credits not released\n");
> +}
> +
> +static void wait_for_payload_credits(struct drm_i915_private *dev_priv,
> + enum transcoder dsi_trans)
> +{
> + if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
> + MAX_PLOAD_CREDIT, 100))
> + DRM_ERROR("DSI payload credits not released\n");
> +}
> +
> static enum transcoder dsi_port_to_transcoder(enum port port)
> {
> if (port == PORT_A)
> @@ -36,6 +66,47 @@ static enum transcoder dsi_port_to_transcoder(enum port port)
> return TRANSCODER_DSI_1;
> }
>
> +static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + struct mipi_dsi_device *dsi;
> + enum port port;
> + enum transcoder dsi_trans;
> + int ret;
> +
> + /* wait for header/payload credits to be released */
> + for_each_dsi_port(port, intel_dsi->ports) {
> + dsi_trans = dsi_port_to_transcoder(port);
> + wait_for_header_credits(dev_priv, dsi_trans);
> + wait_for_payload_credits(dev_priv, dsi_trans);
> + }
> +
> + /* send nop DCS command */
> + for_each_dsi_port(port, intel_dsi->ports) {
> + dsi = intel_dsi->dsi_hosts[port]->device;
> + dsi->mode_flags |= MIPI_DSI_MODE_LPM;
> + dsi->channel = 0;
> + ret = mipi_dsi_dcs_nop(dsi);
> + if (ret < 0)
> + DRM_ERROR("error sending DCS NOP command\n");
> + }
> +
> + /* wait for header credits to be released */
> + for_each_dsi_port(port, intel_dsi->ports) {
> + dsi_trans = dsi_port_to_transcoder(port);
> + wait_for_header_credits(dev_priv, dsi_trans);
> + }
> +
> + /* wait for LP TX in progress bit to be cleared */
> + for_each_dsi_port(port, intel_dsi->ports) {
> + dsi_trans = dsi_port_to_transcoder(port);
> + if (wait_for_us(!(I915_READ(DSI_LP_MSG(dsi_trans)) &
> + LPTX_IN_PROGRESS), 20))
> + DRM_ERROR("LPTX bit not cleared\n");
> + }
> +}
> +
> static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> @@ -671,6 +742,9 @@ static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
> intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
> intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
> intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
> +
> + /* ensure all panel commands dispatched before enabling transcoder */
> + wait_for_cmds_dispatched_to_panel(encoder);
> }
>
> static void __attribute__((unused))
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^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v8 06/38] drm/i915/icl: Turn ON panel backlight
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (4 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 05/38] drm/i915/icl: Wait for header/payload credits release Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-30 11:56 ` [PATCH v8 07/38] drm/i915/icl: Turn OFF " Jani Nikula
` (36 subsequent siblings)
42 siblings, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch enables backlight of DSI panel by using VBT
BACKLIGHT_ON sequence and panel specific functions.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 0f0447b6b1be..bffbb40cc0bc 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -752,6 +752,8 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config,
const struct drm_connector_state *conn_state)
{
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+
/* step2: enable IO power */
gen11_dsi_enable_io_power(encoder);
@@ -769,4 +771,8 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
/* step6d: enable dsi transcoder */
gen11_dsi_enable_transcoder(encoder);
+
+ /* step7: enable backlight */
+ intel_panel_enable_backlight(pipe_config, conn_state);
+ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
}
--
2.11.0
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^ permalink raw reply related [flat|nested] 75+ messages in thread* [PATCH v8 07/38] drm/i915/icl: Turn OFF panel backlight
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (5 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 06/38] drm/i915/icl: Turn ON panel backlight Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-30 11:56 ` [PATCH v8 08/38] drm/i915/icl: Disable DSI transcoders Jani Nikula
` (35 subsequent siblings)
42 siblings, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch disbles backlight of DSI panel by using VBT
BACKLIGHT_OFF sequence and panel specific disable functions.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index bffbb40cc0bc..f7f48ff147d0 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -776,3 +776,15 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
intel_panel_enable_backlight(pipe_config, conn_state);
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
}
+
+static void __attribute__((unused)) gen11_dsi_disable(
+ struct intel_encoder *encoder,
+ const struct intel_crtc_state *old_crtc_state,
+ const struct drm_connector_state *old_conn_state)
+{
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+
+ /* step1: turn off backlight */
+ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
+ intel_panel_disable_backlight(old_conn_state);
+}
--
2.11.0
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^ permalink raw reply related [flat|nested] 75+ messages in thread* [PATCH v8 08/38] drm/i915/icl: Disable DSI transcoders
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (6 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 07/38] drm/i915/icl: Turn OFF " Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-31 10:10 ` Madhav Chauhan
2018-10-30 11:56 ` [PATCH v8 09/38] drm/i915/icl: Power down DSI panel Jani Nikula
` (34 subsequent siblings)
42 siblings, 1 reply; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch disables transcoders by writing to TRANS_CONF
registers for each DSI ports.
v2 by Jani:
- Wait for pipeconf active to go low
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index f7f48ff147d0..644ad7475920 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -777,6 +777,29 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
}
+static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
+ enum transcoder dsi_trans;
+ u32 tmp;
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+
+ /* disable transcoder */
+ tmp = I915_READ(PIPECONF(dsi_trans));
+ tmp &= ~PIPECONF_ENABLE;
+ I915_WRITE(PIPECONF(dsi_trans), tmp);
+
+ /* wait for transcoder to be disabled */
+ if (intel_wait_for_register(dev_priv, PIPECONF(dsi_trans),
+ I965_PIPECONF_ACTIVE, 0, 50))
+ DRM_ERROR("DSI trancoder not disabled\n");
+ }
+}
+
static void __attribute__((unused)) gen11_dsi_disable(
struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state,
@@ -787,4 +810,7 @@ static void __attribute__((unused)) gen11_dsi_disable(
/* step1: turn off backlight */
intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
intel_panel_disable_backlight(old_conn_state);
+
+ /* step2d,e: disable transcoder and wait */
+ gen11_dsi_disable_transcoder(encoder);
}
--
2.11.0
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^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [PATCH v8 08/38] drm/i915/icl: Disable DSI transcoders
2018-10-30 11:56 ` [PATCH v8 08/38] drm/i915/icl: Disable DSI transcoders Jani Nikula
@ 2018-10-31 10:10 ` Madhav Chauhan
0 siblings, 0 replies; 75+ messages in thread
From: Madhav Chauhan @ 2018-10-31 10:10 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 10/30/2018 5:26 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch disables transcoders by writing to TRANS_CONF
> registers for each DSI ports.
>
> v2 by Jani:
> - Wait for pipeconf active to go low
Thanks for catching this, it has to be low.
Regards,
Madhav
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index f7f48ff147d0..644ad7475920 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -777,6 +777,29 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder,
> intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
> }
>
> +static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + enum port port;
> + enum transcoder dsi_trans;
> + u32 tmp;
> +
> + for_each_dsi_port(port, intel_dsi->ports) {
> + dsi_trans = dsi_port_to_transcoder(port);
> +
> + /* disable transcoder */
> + tmp = I915_READ(PIPECONF(dsi_trans));
> + tmp &= ~PIPECONF_ENABLE;
> + I915_WRITE(PIPECONF(dsi_trans), tmp);
> +
> + /* wait for transcoder to be disabled */
> + if (intel_wait_for_register(dev_priv, PIPECONF(dsi_trans),
> + I965_PIPECONF_ACTIVE, 0, 50))
> + DRM_ERROR("DSI trancoder not disabled\n");
> + }
> +}
> +
> static void __attribute__((unused)) gen11_dsi_disable(
> struct intel_encoder *encoder,
> const struct intel_crtc_state *old_crtc_state,
> @@ -787,4 +810,7 @@ static void __attribute__((unused)) gen11_dsi_disable(
> /* step1: turn off backlight */
> intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
> intel_panel_disable_backlight(old_conn_state);
> +
> + /* step2d,e: disable transcoder and wait */
> + gen11_dsi_disable_transcoder(encoder);
> }
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^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v8 09/38] drm/i915/icl: Power down DSI panel
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (7 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 08/38] drm/i915/icl: Disable DSI transcoders Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-30 11:56 ` [PATCH v8 10/38] drm/i915/icl: Put DSI link in ULPS Jani Nikula
` (33 subsequent siblings)
42 siblings, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch sends command and executes display off,
assert reset, power off VBT seqeuences to power
down DSI panel. Patch also adds high level function
to wrap all the panel sepcific programming during
DSI disabling.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 644ad7475920..a7b1a9eae04b 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -800,6 +800,18 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
}
}
+static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder)
+{
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+
+ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
+ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
+ intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
+
+ /* ensure cmds dispatched to panel */
+ wait_for_cmds_dispatched_to_panel(encoder);
+}
+
static void __attribute__((unused)) gen11_dsi_disable(
struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state,
@@ -813,4 +825,7 @@ static void __attribute__((unused)) gen11_dsi_disable(
/* step2d,e: disable transcoder and wait */
gen11_dsi_disable_transcoder(encoder);
+
+ /* step2f,g: powerdown panel */
+ gen11_dsi_powerdown_panel(encoder);
}
--
2.11.0
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^ permalink raw reply related [flat|nested] 75+ messages in thread* [PATCH v8 10/38] drm/i915/icl: Put DSI link in ULPS
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (8 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 09/38] drm/i915/icl: Power down DSI panel Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-30 11:56 ` [PATCH v8 11/38] drm/i915/icl: Disable DDI function Jani Nikula
` (32 subsequent siblings)
42 siblings, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
As part of DSI disabling sequence, DSI link need to enter
in ULPS by writing into DSI_LP_MSG register. This patch
does the same using a wrapper function.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index a7b1a9eae04b..83c422d5976c 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -812,6 +812,29 @@ static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder)
wait_for_cmds_dispatched_to_panel(encoder);
}
+static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
+ enum transcoder dsi_trans;
+ u32 tmp;
+
+ /* put dsi link in ULPS */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ tmp = I915_READ(DSI_LP_MSG(dsi_trans));
+ tmp |= LINK_ENTER_ULPS;
+ tmp &= ~LINK_ULPS_TYPE_LP11;
+ I915_WRITE(DSI_LP_MSG(dsi_trans), tmp);
+
+ if (wait_for_us((I915_READ(DSI_LP_MSG(dsi_trans)) &
+ LINK_IN_ULPS),
+ 10))
+ DRM_ERROR("DSI link not in ULPS\n");
+ }
+}
+
static void __attribute__((unused)) gen11_dsi_disable(
struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state,
@@ -828,4 +851,7 @@ static void __attribute__((unused)) gen11_dsi_disable(
/* step2f,g: powerdown panel */
gen11_dsi_powerdown_panel(encoder);
+
+ /* step2h,i,j: deconfig trancoder */
+ gen11_dsi_deconfigure_trancoder(encoder);
}
--
2.11.0
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^ permalink raw reply related [flat|nested] 75+ messages in thread* [PATCH v8 11/38] drm/i915/icl: Disable DDI function
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (9 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 10/38] drm/i915/icl: Put DSI link in ULPS Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-30 11:56 ` [PATCH v8 12/38] drm/i915/icl: Disable portsync mode Jani Nikula
` (31 subsequent siblings)
42 siblings, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch disables DDI function by writing to
TRANS_DDI_FUNC_CTL registers of DSI ports as part
of DSI disable sequence.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 83c422d5976c..0041f57d3c0b 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -833,6 +833,14 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
10))
DRM_ERROR("DSI link not in ULPS\n");
}
+
+ /* disable ddi function */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
+ tmp &= ~TRANS_DDI_FUNC_ENABLE;
+ I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
+ }
}
static void __attribute__((unused)) gen11_dsi_disable(
--
2.11.0
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^ permalink raw reply related [flat|nested] 75+ messages in thread* [PATCH v8 12/38] drm/i915/icl: Disable portsync mode
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (10 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 11/38] drm/i915/icl: Disable DDI function Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-30 11:56 ` [PATCH v8 13/38] drm/i915/icl: Disable DSI ports Jani Nikula
` (30 subsequent siblings)
42 siblings, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch disables portsync mode if DSI link
is operating in dual link mode by writing to
TRANS_DDI_FUNC_CTL2 registers.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 0041f57d3c0b..71092f116170 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -841,6 +841,16 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
tmp &= ~TRANS_DDI_FUNC_ENABLE;
I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
}
+
+ /* disable port sync mode if dual link */
+ if (intel_dsi->dual_link) {
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans));
+ tmp &= ~PORT_SYNC_MODE_ENABLE;
+ I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
+ }
+ }
}
static void __attribute__((unused)) gen11_dsi_disable(
--
2.11.0
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^ permalink raw reply related [flat|nested] 75+ messages in thread* [PATCH v8 13/38] drm/i915/icl: Disable DSI ports
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (11 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 12/38] drm/i915/icl: Disable portsync mode Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-30 11:56 ` [PATCH v8 14/38] drm/i915/icl: Disable DSI IO power Jani Nikula
` (29 subsequent siblings)
42 siblings, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch disables both DSI ports by writing to
DDI_BUF_CTL registers as part of DSI encoder disable
sequence.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 71092f116170..44696848ffd7 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -853,6 +853,26 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
}
}
+static void gen11_dsi_disable_port(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ u32 tmp;
+ enum port port;
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ tmp = I915_READ(DDI_BUF_CTL(port));
+ tmp &= ~DDI_BUF_CTL_ENABLE;
+ I915_WRITE(DDI_BUF_CTL(port), tmp);
+
+ if (wait_for_us((I915_READ(DDI_BUF_CTL(port)) &
+ DDI_BUF_IS_IDLE),
+ 8))
+ DRM_ERROR("DDI port:%c buffer not idle\n",
+ port_name(port));
+ }
+}
+
static void __attribute__((unused)) gen11_dsi_disable(
struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state,
@@ -872,4 +892,7 @@ static void __attribute__((unused)) gen11_dsi_disable(
/* step2h,i,j: deconfig trancoder */
gen11_dsi_deconfigure_trancoder(encoder);
+
+ /* step3: disable port */
+ gen11_dsi_disable_port(encoder);
}
--
2.11.0
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^ permalink raw reply related [flat|nested] 75+ messages in thread* [PATCH v8 14/38] drm/i915/icl: Disable DSI IO power
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (12 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 13/38] drm/i915/icl: Disable DSI ports Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-30 11:56 ` [PATCH v8 15/38] drm/i915/icl: Define DSI timeout registers Jani Nikula
` (28 subsequent siblings)
42 siblings, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch configures mode of combo phy as DDI and
disable IO power for DDI ports used by DSI.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 44696848ffd7..ac22c74ae146 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -873,6 +873,26 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder)
}
}
+static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
+ u32 tmp;
+
+ intel_display_power_put(dev_priv, POWER_DOMAIN_PORT_DDI_A_IO);
+
+ if (intel_dsi->dual_link)
+ intel_display_power_put(dev_priv, POWER_DOMAIN_PORT_DDI_B_IO);
+
+ /* set mode to DDI */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ tmp = I915_READ(ICL_DSI_IO_MODECTL(port));
+ tmp &= ~COMBO_PHY_MODE_DSI;
+ I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp);
+ }
+}
+
static void __attribute__((unused)) gen11_dsi_disable(
struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state,
@@ -895,4 +915,7 @@ static void __attribute__((unused)) gen11_dsi_disable(
/* step3: disable port */
gen11_dsi_disable_port(encoder);
+
+ /* step4: disable IO power */
+ gen11_dsi_disable_io_power(encoder);
}
--
2.11.0
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^ permalink raw reply related [flat|nested] 75+ messages in thread* [PATCH v8 15/38] drm/i915/icl: Define DSI timeout registers
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (13 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 14/38] drm/i915/icl: Disable DSI IO power Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-31 10:29 ` Madhav Chauhan
2018-10-30 11:56 ` [PATCH v8 16/38] drm/i915/icl: Program HS_TX_TIMEOUT/LP_RX_TIMEOUT/TA_TIMEOUT registers Jani Nikula
` (27 subsequent siblings)
42 siblings, 1 reply; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch defines DSI_HTX_TO, DSI_LRX_H_TO, DSI_PWAIT_TO
and DSI_TA_TO registers for DSI transcoders '0' and '1'.
They are used for contention recovery on DPHY.
v2: Define SHIFT for bitfields.
v3 by Jani:
- Fix timeout bit definitions
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 43 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bcee91bcfba6..8d089ef848b2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10533,6 +10533,49 @@ enum skl_power_gate {
#define LINK_ULPS_TYPE_LP11 (1 << 8)
#define LINK_ENTER_ULPS (1 << 0)
+/* DSI timeout registers */
+#define _DSI_HSTX_TO_0 0x6b044
+#define _DSI_HSTX_TO_1 0x6b844
+#define DSI_HSTX_TO(tc) _MMIO_DSI(tc, \
+ _DSI_HSTX_TO_0,\
+ _DSI_HSTX_TO_1)
+#define HSTX_TIMEOUT_VALUE_MASK (0xffff << 16)
+#define HSTX_TIMEOUT_VALUE_SHIFT 16
+#define HSTX_TIMEOUT_VALUE(x) ((x) << 16)
+#define HSTX_TIMED_OUT (1 << 0)
+
+#define _DSI_LPRX_HOST_TO_0 0x6b048
+#define _DSI_LPRX_HOST_TO_1 0x6b848
+#define DSI_LPRX_HOST_TO(tc) _MMIO_DSI(tc, \
+ _DSI_LPRX_HOST_TO_0,\
+ _DSI_LPRX_HOST_TO_1)
+#define LPRX_TIMED_OUT (1 << 16)
+#define LPRX_TIMEOUT_VALUE_MASK (0xffff << 0)
+#define LPRX_TIMEOUT_VALUE_SHIFT 0
+#define LPRX_TIMEOUT_VALUE(x) ((x) << 0)
+
+#define _DSI_PWAIT_TO_0 0x6b040
+#define _DSI_PWAIT_TO_1 0x6b840
+#define DSI_PWAIT_TO(tc) _MMIO_DSI(tc, \
+ _DSI_PWAIT_TO_0,\
+ _DSI_PWAIT_TO_1)
+#define PRESET_TIMEOUT_VALUE_MASK (0xffff << 16)
+#define PRESET_TIMEOUT_VALUE_SHIFT 16
+#define PRESET_TIMEOUT_VALUE(x) ((x) << 16)
+#define PRESPONSE_TIMEOUT_VALUE_MASK (0xffff << 0)
+#define PRESPONSE_TIMEOUT_VALUE_SHIFT 0
+#define PRESPONSE_TIMEOUT_VALUE(x) ((x) << 0)
+
+#define _DSI_TA_TO_0 0x6b04c
+#define _DSI_TA_TO_1 0x6b84c
+#define DSI_TA_TO(tc) _MMIO_DSI(tc, \
+ _DSI_TA_TO_0,\
+ _DSI_TA_TO_1)
+#define TA_TIMED_OUT (1 << 16)
+#define TA_TIMEOUT_VALUE_MASK (0xffff << 0)
+#define TA_TIMEOUT_VALUE_SHIFT 0
+#define TA_TIMEOUT_VALUE(x) ((x) << 0)
+
/* bits 31:0 */
#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
--
2.11.0
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^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [PATCH v8 15/38] drm/i915/icl: Define DSI timeout registers
2018-10-30 11:56 ` [PATCH v8 15/38] drm/i915/icl: Define DSI timeout registers Jani Nikula
@ 2018-10-31 10:29 ` Madhav Chauhan
0 siblings, 0 replies; 75+ messages in thread
From: Madhav Chauhan @ 2018-10-31 10:29 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 10/30/2018 5:26 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch defines DSI_HTX_TO, DSI_LRX_H_TO, DSI_PWAIT_TO
> and DSI_TA_TO registers for DSI transcoders '0' and '1'.
> They are used for contention recovery on DPHY.
>
> v2: Define SHIFT for bitfields.
>
> v3 by Jani:
> - Fix timeout bit definitions
Ok. I was little confused with BSPEC description "HW will set this bit,
SW must clear it with a write of 1b"
meaning timeout will happen (reverse behavior) when bit is '0' :).
Regards,
Madhav
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 43 +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bcee91bcfba6..8d089ef848b2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10533,6 +10533,49 @@ enum skl_power_gate {
> #define LINK_ULPS_TYPE_LP11 (1 << 8)
> #define LINK_ENTER_ULPS (1 << 0)
>
> +/* DSI timeout registers */
> +#define _DSI_HSTX_TO_0 0x6b044
> +#define _DSI_HSTX_TO_1 0x6b844
> +#define DSI_HSTX_TO(tc) _MMIO_DSI(tc, \
> + _DSI_HSTX_TO_0,\
> + _DSI_HSTX_TO_1)
> +#define HSTX_TIMEOUT_VALUE_MASK (0xffff << 16)
> +#define HSTX_TIMEOUT_VALUE_SHIFT 16
> +#define HSTX_TIMEOUT_VALUE(x) ((x) << 16)
> +#define HSTX_TIMED_OUT (1 << 0)
> +
> +#define _DSI_LPRX_HOST_TO_0 0x6b048
> +#define _DSI_LPRX_HOST_TO_1 0x6b848
> +#define DSI_LPRX_HOST_TO(tc) _MMIO_DSI(tc, \
> + _DSI_LPRX_HOST_TO_0,\
> + _DSI_LPRX_HOST_TO_1)
> +#define LPRX_TIMED_OUT (1 << 16)
> +#define LPRX_TIMEOUT_VALUE_MASK (0xffff << 0)
> +#define LPRX_TIMEOUT_VALUE_SHIFT 0
> +#define LPRX_TIMEOUT_VALUE(x) ((x) << 0)
> +
> +#define _DSI_PWAIT_TO_0 0x6b040
> +#define _DSI_PWAIT_TO_1 0x6b840
> +#define DSI_PWAIT_TO(tc) _MMIO_DSI(tc, \
> + _DSI_PWAIT_TO_0,\
> + _DSI_PWAIT_TO_1)
> +#define PRESET_TIMEOUT_VALUE_MASK (0xffff << 16)
> +#define PRESET_TIMEOUT_VALUE_SHIFT 16
> +#define PRESET_TIMEOUT_VALUE(x) ((x) << 16)
> +#define PRESPONSE_TIMEOUT_VALUE_MASK (0xffff << 0)
> +#define PRESPONSE_TIMEOUT_VALUE_SHIFT 0
> +#define PRESPONSE_TIMEOUT_VALUE(x) ((x) << 0)
> +
> +#define _DSI_TA_TO_0 0x6b04c
> +#define _DSI_TA_TO_1 0x6b84c
> +#define DSI_TA_TO(tc) _MMIO_DSI(tc, \
> + _DSI_TA_TO_0,\
> + _DSI_TA_TO_1)
> +#define TA_TIMED_OUT (1 << 16)
> +#define TA_TIMEOUT_VALUE_MASK (0xffff << 0)
> +#define TA_TIMEOUT_VALUE_SHIFT 0
> +#define TA_TIMEOUT_VALUE(x) ((x) << 0)
> +
> /* bits 31:0 */
> #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
> #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
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^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v8 16/38] drm/i915/icl: Program HS_TX_TIMEOUT/LP_RX_TIMEOUT/TA_TIMEOUT registers
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (14 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 15/38] drm/i915/icl: Define DSI timeout registers Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-31 11:01 ` Madhav Chauhan
2018-10-30 11:56 ` [PATCH v8 17/38] drm/i915/icl: Find DSI presence for ICL Jani Nikula
` (26 subsequent siblings)
42 siblings, 1 reply; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
Program the timeout values (in escape clock) for HS TX, LP RX and TA
timeout.
HX TX: Ensure that host does not continuously transmit in the HS
state. If this timer expires, then host will gracefully end its HS
transmission and allow the link to enter into LP state.
LP RX: Monitor the length of LP receptions from Peripheral. If timeout
happens then host will drive the stop state onto all data lanes (only
Data Lane 0 should be receiving anything from the Peripheral). This
effectively takes back ownership of the bus transmit in the HS state.
TA timeout: Timeout valuefor monitoring Bus Turn-Around (BTA) sequence.
BTA sequence should complete within a bounded amount of time, with
peripheral acknowledging BTA by driving the stop state.
v2 by Jani:
- Rebase
- Use intel_dsi_bitrate() and intel_dsi_tlpx_ns(intel_dsi)
- Squash HX TX, LP RX and TA timeout into one patch
- Fix bspec mode set sequence reference
- Add FIXME about two timeouts
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 52 ++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_dsi.h | 1 +
drivers/gpu/drm/i915/intel_dsi_vbt.c | 1 +
3 files changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index ac22c74ae146..fd82f349ced9 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -685,6 +685,55 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
}
}
+static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
+ enum transcoder dsi_trans;
+ u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul;
+
+ /*
+ * escape clock count calculation:
+ * BYTE_CLK_COUNT = TIME_NS/(8 * UI)
+ * UI (nsec) = (10^6)/Bitrate
+ * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
+ * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS
+ */
+ divisor = intel_dsi_tlpx_ns(intel_dsi) * intel_dsi_bitrate(intel_dsi) * 1000;
+ mul = 8 * 1000000;
+ hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
+ divisor);
+ lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor);
+ ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor);
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+
+ /* program hst_tx_timeout */
+ tmp = I915_READ(DSI_HSTX_TO(dsi_trans));
+ tmp &= ~HSTX_TIMEOUT_VALUE_MASK;
+ tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout);
+ I915_WRITE(DSI_HSTX_TO(dsi_trans), tmp);
+
+ /* FIXME: DSI_CALIB_TO */
+
+ /* program lp_rx_host timeout */
+ tmp = I915_READ(DSI_LPRX_HOST_TO(dsi_trans));
+ tmp &= ~LPRX_TIMEOUT_VALUE_MASK;
+ tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout);
+ I915_WRITE(DSI_LPRX_HOST_TO(dsi_trans), tmp);
+
+ /* FIXME: DSI_PWAIT_TO */
+
+ /* program turn around timeout */
+ tmp = I915_READ(DSI_TA_TO(dsi_trans));
+ tmp &= ~TA_TIMEOUT_VALUE_MASK;
+ tmp |= TA_TIMEOUT_VALUE(ta_timeout);
+ I915_WRITE(DSI_TA_TO(dsi_trans), tmp);
+ }
+}
+
static void
gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
@@ -704,6 +753,9 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
/* setup D-PHY timings */
gen11_dsi_setup_dphy_timings(encoder);
+ /* step 4h: setup DSI protocol timeouts */
+ gen11_dsi_setup_timeouts(encoder);
+
/* Step (4h, 4i, 4j, 4k): Configure transcoder */
gen11_dsi_configure_transcoder(encoder, pipe_config);
}
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 10fd1582a8e2..f2a3ddedcc5d 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -95,6 +95,7 @@ struct intel_dsi {
u16 lp_byte_clk;
/* timeouts in byte clocks */
+ u16 hs_tx_timeout;
u16 lp_rx_timeout;
u16 turn_arnd_val;
u16 rst_timer_val;
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index cca071406c25..80bd56e96143 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -799,6 +799,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
+ intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout;
intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
intel_dsi->init_count = mipi_config->master_init_timer;
--
2.11.0
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^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [PATCH v8 16/38] drm/i915/icl: Program HS_TX_TIMEOUT/LP_RX_TIMEOUT/TA_TIMEOUT registers
2018-10-30 11:56 ` [PATCH v8 16/38] drm/i915/icl: Program HS_TX_TIMEOUT/LP_RX_TIMEOUT/TA_TIMEOUT registers Jani Nikula
@ 2018-10-31 11:01 ` Madhav Chauhan
2018-10-31 11:18 ` Jani Nikula
0 siblings, 1 reply; 75+ messages in thread
From: Madhav Chauhan @ 2018-10-31 11:01 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 10/30/2018 5:26 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> Program the timeout values (in escape clock) for HS TX, LP RX and TA
> timeout.
>
> HX TX: Ensure that host does not continuously transmit in the HS
> state. If this timer expires, then host will gracefully end its HS
> transmission and allow the link to enter into LP state.
>
> LP RX: Monitor the length of LP receptions from Peripheral. If timeout
> happens then host will drive the stop state onto all data lanes (only
> Data Lane 0 should be receiving anything from the Peripheral). This
> effectively takes back ownership of the bus transmit in the HS state.
>
> TA timeout: Timeout valuefor monitoring Bus Turn-Around (BTA) sequence.
> BTA sequence should complete within a bounded amount of time, with
> peripheral acknowledging BTA by driving the stop state.
>
> v2 by Jani:
> - Rebase
> - Use intel_dsi_bitrate() and intel_dsi_tlpx_ns(intel_dsi)
> - Squash HX TX, LP RX and TA timeout into one patch
> - Fix bspec mode set sequence reference
> - Add FIXME about two timeouts
Looks fine.
Regards,
Madhav
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 52 ++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_dsi.h | 1 +
> drivers/gpu/drm/i915/intel_dsi_vbt.c | 1 +
> 3 files changed, 54 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index ac22c74ae146..fd82f349ced9 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -685,6 +685,55 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
> }
> }
>
> +static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + enum port port;
> + enum transcoder dsi_trans;
> + u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul;
> +
> + /*
> + * escape clock count calculation:
> + * BYTE_CLK_COUNT = TIME_NS/(8 * UI)
> + * UI (nsec) = (10^6)/Bitrate
> + * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
> + * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS
> + */
> + divisor = intel_dsi_tlpx_ns(intel_dsi) * intel_dsi_bitrate(intel_dsi) * 1000;
> + mul = 8 * 1000000;
> + hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
> + divisor);
> + lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor);
> + ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor);
> +
> + for_each_dsi_port(port, intel_dsi->ports) {
> + dsi_trans = dsi_port_to_transcoder(port);
> +
> + /* program hst_tx_timeout */
> + tmp = I915_READ(DSI_HSTX_TO(dsi_trans));
> + tmp &= ~HSTX_TIMEOUT_VALUE_MASK;
> + tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout);
> + I915_WRITE(DSI_HSTX_TO(dsi_trans), tmp);
> +
> + /* FIXME: DSI_CALIB_TO */
> +
> + /* program lp_rx_host timeout */
> + tmp = I915_READ(DSI_LPRX_HOST_TO(dsi_trans));
> + tmp &= ~LPRX_TIMEOUT_VALUE_MASK;
> + tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout);
> + I915_WRITE(DSI_LPRX_HOST_TO(dsi_trans), tmp);
> +
> + /* FIXME: DSI_PWAIT_TO */
> +
> + /* program turn around timeout */
> + tmp = I915_READ(DSI_TA_TO(dsi_trans));
> + tmp &= ~TA_TIMEOUT_VALUE_MASK;
> + tmp |= TA_TIMEOUT_VALUE(ta_timeout);
> + I915_WRITE(DSI_TA_TO(dsi_trans), tmp);
> + }
> +}
> +
> static void
> gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config)
> @@ -704,6 +753,9 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> /* setup D-PHY timings */
> gen11_dsi_setup_dphy_timings(encoder);
>
> + /* step 4h: setup DSI protocol timeouts */
> + gen11_dsi_setup_timeouts(encoder);
> +
> /* Step (4h, 4i, 4j, 4k): Configure transcoder */
> gen11_dsi_configure_transcoder(encoder, pipe_config);
> }
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index 10fd1582a8e2..f2a3ddedcc5d 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -95,6 +95,7 @@ struct intel_dsi {
> u16 lp_byte_clk;
>
> /* timeouts in byte clocks */
> + u16 hs_tx_timeout;
> u16 lp_rx_timeout;
> u16 turn_arnd_val;
> u16 rst_timer_val;
> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> index cca071406c25..80bd56e96143 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> @@ -799,6 +799,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
> intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
> intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
> intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
> + intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout;
> intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
> intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
> intel_dsi->init_count = mipi_config->master_init_timer;
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [PATCH v8 16/38] drm/i915/icl: Program HS_TX_TIMEOUT/LP_RX_TIMEOUT/TA_TIMEOUT registers
2018-10-31 11:01 ` Madhav Chauhan
@ 2018-10-31 11:18 ` Jani Nikula
0 siblings, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-10-31 11:18 UTC (permalink / raw)
To: Madhav Chauhan, intel-gfx
On Wed, 31 Oct 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> On 10/30/2018 5:26 PM, Jani Nikula wrote:
>> From: Madhav Chauhan <madhav.chauhan@intel.com>
>>
>> Program the timeout values (in escape clock) for HS TX, LP RX and TA
>> timeout.
>>
>> HX TX: Ensure that host does not continuously transmit in the HS
>> state. If this timer expires, then host will gracefully end its HS
>> transmission and allow the link to enter into LP state.
>>
>> LP RX: Monitor the length of LP receptions from Peripheral. If timeout
>> happens then host will drive the stop state onto all data lanes (only
>> Data Lane 0 should be receiving anything from the Peripheral). This
>> effectively takes back ownership of the bus transmit in the HS state.
>>
>> TA timeout: Timeout valuefor monitoring Bus Turn-Around (BTA) sequence.
>> BTA sequence should complete within a bounded amount of time, with
>> peripheral acknowledging BTA by driving the stop state.
>>
>> v2 by Jani:
>> - Rebase
>> - Use intel_dsi_bitrate() and intel_dsi_tlpx_ns(intel_dsi)
>> - Squash HX TX, LP RX and TA timeout into one patch
>> - Fix bspec mode set sequence reference
>> - Add FIXME about two timeouts
>
> Looks fine.
Thanks, pushed up to and including this patch.
BR,
Jani.
>
> Regards,
> Madhav
>
>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/icl_dsi.c | 52 ++++++++++++++++++++++++++++++++++++
>> drivers/gpu/drm/i915/intel_dsi.h | 1 +
>> drivers/gpu/drm/i915/intel_dsi_vbt.c | 1 +
>> 3 files changed, 54 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
>> index ac22c74ae146..fd82f349ced9 100644
>> --- a/drivers/gpu/drm/i915/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>> @@ -685,6 +685,55 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
>> }
>> }
>>
>> +static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
>> +{
>> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>> + enum port port;
>> + enum transcoder dsi_trans;
>> + u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul;
>> +
>> + /*
>> + * escape clock count calculation:
>> + * BYTE_CLK_COUNT = TIME_NS/(8 * UI)
>> + * UI (nsec) = (10^6)/Bitrate
>> + * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
>> + * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS
>> + */
>> + divisor = intel_dsi_tlpx_ns(intel_dsi) * intel_dsi_bitrate(intel_dsi) * 1000;
>> + mul = 8 * 1000000;
>> + hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
>> + divisor);
>> + lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor);
>> + ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor);
>> +
>> + for_each_dsi_port(port, intel_dsi->ports) {
>> + dsi_trans = dsi_port_to_transcoder(port);
>> +
>> + /* program hst_tx_timeout */
>> + tmp = I915_READ(DSI_HSTX_TO(dsi_trans));
>> + tmp &= ~HSTX_TIMEOUT_VALUE_MASK;
>> + tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout);
>> + I915_WRITE(DSI_HSTX_TO(dsi_trans), tmp);
>> +
>> + /* FIXME: DSI_CALIB_TO */
>> +
>> + /* program lp_rx_host timeout */
>> + tmp = I915_READ(DSI_LPRX_HOST_TO(dsi_trans));
>> + tmp &= ~LPRX_TIMEOUT_VALUE_MASK;
>> + tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout);
>> + I915_WRITE(DSI_LPRX_HOST_TO(dsi_trans), tmp);
>> +
>> + /* FIXME: DSI_PWAIT_TO */
>> +
>> + /* program turn around timeout */
>> + tmp = I915_READ(DSI_TA_TO(dsi_trans));
>> + tmp &= ~TA_TIMEOUT_VALUE_MASK;
>> + tmp |= TA_TIMEOUT_VALUE(ta_timeout);
>> + I915_WRITE(DSI_TA_TO(dsi_trans), tmp);
>> + }
>> +}
>> +
>> static void
>> gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
>> const struct intel_crtc_state *pipe_config)
>> @@ -704,6 +753,9 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
>> /* setup D-PHY timings */
>> gen11_dsi_setup_dphy_timings(encoder);
>>
>> + /* step 4h: setup DSI protocol timeouts */
>> + gen11_dsi_setup_timeouts(encoder);
>> +
>> /* Step (4h, 4i, 4j, 4k): Configure transcoder */
>> gen11_dsi_configure_transcoder(encoder, pipe_config);
>> }
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
>> index 10fd1582a8e2..f2a3ddedcc5d 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.h
>> +++ b/drivers/gpu/drm/i915/intel_dsi.h
>> @@ -95,6 +95,7 @@ struct intel_dsi {
>> u16 lp_byte_clk;
>>
>> /* timeouts in byte clocks */
>> + u16 hs_tx_timeout;
>> u16 lp_rx_timeout;
>> u16 turn_arnd_val;
>> u16 rst_timer_val;
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> index cca071406c25..80bd56e96143 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> @@ -799,6 +799,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
>> intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
>> intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
>> intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
>> + intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout;
>> intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
>> intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
>> intel_dsi->init_count = mipi_config->master_init_timer;
>
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
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^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v8 17/38] drm/i915/icl: Find DSI presence for ICL
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (15 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 16/38] drm/i915/icl: Program HS_TX_TIMEOUT/LP_RX_TIMEOUT/TA_TIMEOUT registers Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-31 11:19 ` Madhav Chauhan
2018-11-01 11:09 ` Jani Nikula
2018-10-30 11:56 ` [PATCH v8 18/38] drm/i915/icl: Allocate DSI encoder/connector Jani Nikula
` (25 subsequent siblings)
42 siblings, 2 replies; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch detects DSI presence for ICL platform
by reading VBT. DSI detection is done while initializing
DSI using newly added function intel_gen11_dsi_init.
v2 by Jani:
- Preserve old behavour of intel_bios_is_dsi_present()
- s/intel_gen11_dsi_init/icl_dsi_init/g
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 8 ++++++++
drivers/gpu/drm/i915/intel_bios.c | 12 ++++++------
drivers/gpu/drm/i915/intel_display.c | 1 +
drivers/gpu/drm/i915/intel_drv.h | 3 +++
4 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index fd82f349ced9..01f422df8c23 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -971,3 +971,11 @@ static void __attribute__((unused)) gen11_dsi_disable(
/* step4: disable IO power */
gen11_dsi_disable_io_power(encoder);
}
+
+void icl_dsi_init(struct drm_i915_private *dev_priv)
+{
+ enum port port;
+
+ if (!intel_bios_is_dsi_present(dev_priv, &port))
+ return;
+}
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 1faa494e2bc9..5fa2133f801d 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -2039,17 +2039,17 @@ bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv,
dvo_port = child->dvo_port;
- switch (dvo_port) {
- case DVO_PORT_MIPIA:
- case DVO_PORT_MIPIC:
+ if (dvo_port == DVO_PORT_MIPIA ||
+ (dvo_port == DVO_PORT_MIPIB && IS_ICELAKE(dev_priv)) ||
+ (dvo_port == DVO_PORT_MIPIC && !IS_ICELAKE(dev_priv))) {
if (port)
*port = dvo_port - DVO_PORT_MIPIA;
return true;
- case DVO_PORT_MIPIB:
- case DVO_PORT_MIPID:
+ } else if (dvo_port == DVO_PORT_MIPIB ||
+ dvo_port == DVO_PORT_MIPIC ||
+ dvo_port == DVO_PORT_MIPID) {
DRM_DEBUG_KMS("VBT has unsupported DSI port %c\n",
port_name(dvo_port - DVO_PORT_MIPIA));
- break;
}
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c3cadc09f859..1d46f06ede37 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14128,6 +14128,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
intel_ddi_init(dev_priv, PORT_D);
intel_ddi_init(dev_priv, PORT_E);
intel_ddi_init(dev_priv, PORT_F);
+ icl_dsi_init(dev_priv);
} else if (IS_GEN9_LP(dev_priv)) {
/*
* FIXME: Broxton doesn't support port detection via the
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 268afb6d2746..3081cca1a151 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1854,6 +1854,9 @@ void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
/* vlv_dsi.c */
void vlv_dsi_init(struct drm_i915_private *dev_priv);
+/* icl_dsi.c */
+void icl_dsi_init(struct drm_i915_private *dev_priv);
+
/* intel_dsi_dcs_backlight.c */
int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
--
2.11.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [PATCH v8 17/38] drm/i915/icl: Find DSI presence for ICL
2018-10-30 11:56 ` [PATCH v8 17/38] drm/i915/icl: Find DSI presence for ICL Jani Nikula
@ 2018-10-31 11:19 ` Madhav Chauhan
2018-11-01 15:39 ` Jani Nikula
2018-11-01 11:09 ` Jani Nikula
1 sibling, 1 reply; 75+ messages in thread
From: Madhav Chauhan @ 2018-10-31 11:19 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 10/30/2018 5:26 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch detects DSI presence for ICL platform
> by reading VBT. DSI detection is done while initializing
> DSI using newly added function intel_gen11_dsi_init.
>
> v2 by Jani:
> - Preserve old behavour of intel_bios_is_dsi_present()
> - s/intel_gen11_dsi_init/icl_dsi_init/g
Changes looks fine.
Regards,
Madhav
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 8 ++++++++
> drivers/gpu/drm/i915/intel_bios.c | 12 ++++++------
> drivers/gpu/drm/i915/intel_display.c | 1 +
> drivers/gpu/drm/i915/intel_drv.h | 3 +++
> 4 files changed, 18 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index fd82f349ced9..01f422df8c23 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -971,3 +971,11 @@ static void __attribute__((unused)) gen11_dsi_disable(
> /* step4: disable IO power */
> gen11_dsi_disable_io_power(encoder);
> }
> +
> +void icl_dsi_init(struct drm_i915_private *dev_priv)
> +{
> + enum port port;
> +
> + if (!intel_bios_is_dsi_present(dev_priv, &port))
> + return;
> +}
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 1faa494e2bc9..5fa2133f801d 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -2039,17 +2039,17 @@ bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv,
>
> dvo_port = child->dvo_port;
>
> - switch (dvo_port) {
> - case DVO_PORT_MIPIA:
> - case DVO_PORT_MIPIC:
> + if (dvo_port == DVO_PORT_MIPIA ||
> + (dvo_port == DVO_PORT_MIPIB && IS_ICELAKE(dev_priv)) ||
> + (dvo_port == DVO_PORT_MIPIC && !IS_ICELAKE(dev_priv))) {
> if (port)
> *port = dvo_port - DVO_PORT_MIPIA;
> return true;
> - case DVO_PORT_MIPIB:
> - case DVO_PORT_MIPID:
> + } else if (dvo_port == DVO_PORT_MIPIB ||
> + dvo_port == DVO_PORT_MIPIC ||
> + dvo_port == DVO_PORT_MIPID) {
> DRM_DEBUG_KMS("VBT has unsupported DSI port %c\n",
> port_name(dvo_port - DVO_PORT_MIPIA));
> - break;
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c3cadc09f859..1d46f06ede37 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -14128,6 +14128,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> intel_ddi_init(dev_priv, PORT_D);
> intel_ddi_init(dev_priv, PORT_E);
> intel_ddi_init(dev_priv, PORT_F);
> + icl_dsi_init(dev_priv);
> } else if (IS_GEN9_LP(dev_priv)) {
> /*
> * FIXME: Broxton doesn't support port detection via the
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 268afb6d2746..3081cca1a151 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1854,6 +1854,9 @@ void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
> /* vlv_dsi.c */
> void vlv_dsi_init(struct drm_i915_private *dev_priv);
>
> +/* icl_dsi.c */
> +void icl_dsi_init(struct drm_i915_private *dev_priv);
> +
> /* intel_dsi_dcs_backlight.c */
> int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [PATCH v8 17/38] drm/i915/icl: Find DSI presence for ICL
2018-10-31 11:19 ` Madhav Chauhan
@ 2018-11-01 15:39 ` Jani Nikula
0 siblings, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-11-01 15:39 UTC (permalink / raw)
To: Madhav Chauhan, intel-gfx
On Wed, 31 Oct 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> On 10/30/2018 5:26 PM, Jani Nikula wrote:
>> From: Madhav Chauhan <madhav.chauhan@intel.com>
>>
>> This patch detects DSI presence for ICL platform
>> by reading VBT. DSI detection is done while initializing
>> DSI using newly added function intel_gen11_dsi_init.
>>
>> v2 by Jani:
>> - Preserve old behavour of intel_bios_is_dsi_present()
>> - s/intel_gen11_dsi_init/icl_dsi_init/g
>
> Changes looks fine.
I'm afraid I felt I needed to squash and reorder the patches a bit. I
didn't really do functional changes compared to the remaining patches in
this series apart from the power domain change spotted by Imre.
BR,
Jani.
>
> Regards,
> Madhav
>
>>
>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/icl_dsi.c | 8 ++++++++
>> drivers/gpu/drm/i915/intel_bios.c | 12 ++++++------
>> drivers/gpu/drm/i915/intel_display.c | 1 +
>> drivers/gpu/drm/i915/intel_drv.h | 3 +++
>> 4 files changed, 18 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
>> index fd82f349ced9..01f422df8c23 100644
>> --- a/drivers/gpu/drm/i915/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/icl_dsi.c
>> @@ -971,3 +971,11 @@ static void __attribute__((unused)) gen11_dsi_disable(
>> /* step4: disable IO power */
>> gen11_dsi_disable_io_power(encoder);
>> }
>> +
>> +void icl_dsi_init(struct drm_i915_private *dev_priv)
>> +{
>> + enum port port;
>> +
>> + if (!intel_bios_is_dsi_present(dev_priv, &port))
>> + return;
>> +}
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
>> index 1faa494e2bc9..5fa2133f801d 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -2039,17 +2039,17 @@ bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv,
>>
>> dvo_port = child->dvo_port;
>>
>> - switch (dvo_port) {
>> - case DVO_PORT_MIPIA:
>> - case DVO_PORT_MIPIC:
>> + if (dvo_port == DVO_PORT_MIPIA ||
>> + (dvo_port == DVO_PORT_MIPIB && IS_ICELAKE(dev_priv)) ||
>> + (dvo_port == DVO_PORT_MIPIC && !IS_ICELAKE(dev_priv))) {
>> if (port)
>> *port = dvo_port - DVO_PORT_MIPIA;
>> return true;
>> - case DVO_PORT_MIPIB:
>> - case DVO_PORT_MIPID:
>> + } else if (dvo_port == DVO_PORT_MIPIB ||
>> + dvo_port == DVO_PORT_MIPIC ||
>> + dvo_port == DVO_PORT_MIPID) {
>> DRM_DEBUG_KMS("VBT has unsupported DSI port %c\n",
>> port_name(dvo_port - DVO_PORT_MIPIA));
>> - break;
>> }
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index c3cadc09f859..1d46f06ede37 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -14128,6 +14128,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
>> intel_ddi_init(dev_priv, PORT_D);
>> intel_ddi_init(dev_priv, PORT_E);
>> intel_ddi_init(dev_priv, PORT_F);
>> + icl_dsi_init(dev_priv);
>> } else if (IS_GEN9_LP(dev_priv)) {
>> /*
>> * FIXME: Broxton doesn't support port detection via the
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index 268afb6d2746..3081cca1a151 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -1854,6 +1854,9 @@ void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
>> /* vlv_dsi.c */
>> void vlv_dsi_init(struct drm_i915_private *dev_priv);
>>
>> +/* icl_dsi.c */
>> +void icl_dsi_init(struct drm_i915_private *dev_priv);
>> +
>> /* intel_dsi_dcs_backlight.c */
>> int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
>>
>
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v8 17/38] drm/i915/icl: Find DSI presence for ICL
2018-10-30 11:56 ` [PATCH v8 17/38] drm/i915/icl: Find DSI presence for ICL Jani Nikula
2018-10-31 11:19 ` Madhav Chauhan
@ 2018-11-01 11:09 ` Jani Nikula
1 sibling, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-11-01 11:09 UTC (permalink / raw)
To: intel-gfx
On Tue, 30 Oct 2018, Jani Nikula <jani.nikula@intel.com> wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch detects DSI presence for ICL platform
> by reading VBT. DSI detection is done while initializing
> DSI using newly added function intel_gen11_dsi_init.
>
> v2 by Jani:
> - Preserve old behavour of intel_bios_is_dsi_present()
> - s/intel_gen11_dsi_init/icl_dsi_init/g
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Pushed.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 8 ++++++++
> drivers/gpu/drm/i915/intel_bios.c | 12 ++++++------
> drivers/gpu/drm/i915/intel_display.c | 1 +
> drivers/gpu/drm/i915/intel_drv.h | 3 +++
> 4 files changed, 18 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index fd82f349ced9..01f422df8c23 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -971,3 +971,11 @@ static void __attribute__((unused)) gen11_dsi_disable(
> /* step4: disable IO power */
> gen11_dsi_disable_io_power(encoder);
> }
> +
> +void icl_dsi_init(struct drm_i915_private *dev_priv)
> +{
> + enum port port;
> +
> + if (!intel_bios_is_dsi_present(dev_priv, &port))
> + return;
> +}
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 1faa494e2bc9..5fa2133f801d 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -2039,17 +2039,17 @@ bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv,
>
> dvo_port = child->dvo_port;
>
> - switch (dvo_port) {
> - case DVO_PORT_MIPIA:
> - case DVO_PORT_MIPIC:
> + if (dvo_port == DVO_PORT_MIPIA ||
> + (dvo_port == DVO_PORT_MIPIB && IS_ICELAKE(dev_priv)) ||
> + (dvo_port == DVO_PORT_MIPIC && !IS_ICELAKE(dev_priv))) {
> if (port)
> *port = dvo_port - DVO_PORT_MIPIA;
> return true;
> - case DVO_PORT_MIPIB:
> - case DVO_PORT_MIPID:
> + } else if (dvo_port == DVO_PORT_MIPIB ||
> + dvo_port == DVO_PORT_MIPIC ||
> + dvo_port == DVO_PORT_MIPID) {
> DRM_DEBUG_KMS("VBT has unsupported DSI port %c\n",
> port_name(dvo_port - DVO_PORT_MIPIA));
> - break;
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c3cadc09f859..1d46f06ede37 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -14128,6 +14128,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> intel_ddi_init(dev_priv, PORT_D);
> intel_ddi_init(dev_priv, PORT_E);
> intel_ddi_init(dev_priv, PORT_F);
> + icl_dsi_init(dev_priv);
> } else if (IS_GEN9_LP(dev_priv)) {
> /*
> * FIXME: Broxton doesn't support port detection via the
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 268afb6d2746..3081cca1a151 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1854,6 +1854,9 @@ void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
> /* vlv_dsi.c */
> void vlv_dsi_init(struct drm_i915_private *dev_priv);
>
> +/* icl_dsi.c */
> +void icl_dsi_init(struct drm_i915_private *dev_priv);
> +
> /* intel_dsi_dcs_backlight.c */
> int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v8 18/38] drm/i915/icl: Allocate DSI encoder/connector
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (16 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 17/38] drm/i915/icl: Find DSI presence for ICL Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-31 11:24 ` Madhav Chauhan
2018-10-30 11:56 ` [PATCH v8 19/38] drm/i915/icl: Allocate hosts for DSI ports Jani Nikula
` (24 subsequent siblings)
42 siblings, 1 reply; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
This patch allocates memory for DSI encoder and connector
which will be used for various DSI encoder/connector operations
and attaching the same to DRM subsystem. This patch also extracts
DSI modes info from VBT and save the desired mode info to connector.
v2 by Jani:
- Drop GEN11 prefix from encoder name
- Drop extra parenthesis
- Drop extra local variable
- Squash encoder power domain here
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 96 ++++++++++++++++++++++++++++++++++++++----
1 file changed, 88 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 01f422df8c23..a117ecc6c5a3 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -799,10 +799,9 @@ static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
wait_for_cmds_dispatched_to_panel(encoder);
}
-static void __attribute__((unused))
-gen11_dsi_pre_enable(struct intel_encoder *encoder,
- const struct intel_crtc_state *pipe_config,
- const struct drm_connector_state *conn_state)
+static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *pipe_config,
+ const struct drm_connector_state *conn_state)
{
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -945,10 +944,9 @@ static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
}
}
-static void __attribute__((unused)) gen11_dsi_disable(
- struct intel_encoder *encoder,
- const struct intel_crtc_state *old_crtc_state,
- const struct drm_connector_state *old_conn_state)
+static void gen11_dsi_disable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *old_crtc_state,
+ const struct drm_connector_state *old_conn_state)
{
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -972,10 +970,92 @@ static void __attribute__((unused)) gen11_dsi_disable(
gen11_dsi_disable_io_power(encoder);
}
+static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
+{
+ intel_encoder_destroy(encoder);
+}
+
+static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
+ .destroy = gen11_dsi_encoder_destroy,
+};
+
+static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
+};
+
void icl_dsi_init(struct drm_i915_private *dev_priv)
{
+ struct drm_device *dev = &dev_priv->drm;
+ struct intel_dsi *intel_dsi;
+ struct intel_encoder *encoder;
+ struct intel_connector *intel_connector;
+ struct drm_connector *connector;
+ struct drm_display_mode *scan, *fixed_mode = NULL;
enum port port;
if (!intel_bios_is_dsi_present(dev_priv, &port))
return;
+
+ intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
+ if (!intel_dsi)
+ return;
+
+ intel_connector = intel_connector_alloc();
+ if (!intel_connector) {
+ kfree(intel_dsi);
+ return;
+ }
+
+ encoder = &intel_dsi->base;
+ intel_dsi->attached_connector = intel_connector;
+ connector = &intel_connector->base;
+
+ /* register DSI encoder with DRM subsystem */
+ drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs,
+ DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
+
+ encoder->pre_enable = gen11_dsi_pre_enable;
+ encoder->disable = gen11_dsi_disable;
+ encoder->port = port;
+ encoder->type = INTEL_OUTPUT_DSI;
+ encoder->cloneable = 0;
+ encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
+ encoder->power_domain = POWER_DOMAIN_PORT_DSI;
+
+ /* register DSI connector with DRM subsystem */
+ drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
+ DRM_MODE_CONNECTOR_DSI);
+ connector->display_info.subpixel_order = SubPixelHorizontalRGB;
+ connector->interlace_allowed = false;
+ connector->doublescan_allowed = false;
+
+ /* attach connector to encoder */
+ intel_connector_attach_encoder(intel_connector, encoder);
+
+ /* fill mode info from VBT */
+ mutex_lock(&dev->mode_config.mutex);
+ intel_dsi_vbt_get_modes(intel_dsi);
+ list_for_each_entry(scan, &connector->probed_modes, head) {
+ if (scan->type & DRM_MODE_TYPE_PREFERRED) {
+ fixed_mode = drm_mode_duplicate(dev, scan);
+ break;
+ }
+ }
+ mutex_unlock(&dev->mode_config.mutex);
+
+ if (!fixed_mode) {
+ DRM_ERROR("DSI fixed mode info missing\n");
+ goto err;
+ }
+
+ connector->display_info.width_mm = fixed_mode->width_mm;
+ connector->display_info.height_mm = fixed_mode->height_mm;
+ intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
+ intel_panel_setup_backlight(connector, INVALID_PIPE);
+
+ return;
+
+err:
+ drm_encoder_cleanup(&encoder->base);
+ kfree(intel_dsi);
+ kfree(intel_connector);
}
--
2.11.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [PATCH v8 18/38] drm/i915/icl: Allocate DSI encoder/connector
2018-10-30 11:56 ` [PATCH v8 18/38] drm/i915/icl: Allocate DSI encoder/connector Jani Nikula
@ 2018-10-31 11:24 ` Madhav Chauhan
0 siblings, 0 replies; 75+ messages in thread
From: Madhav Chauhan @ 2018-10-31 11:24 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 10/30/2018 5:26 PM, Jani Nikula wrote:
> This patch allocates memory for DSI encoder and connector
> which will be used for various DSI encoder/connector operations
> and attaching the same to DRM subsystem. This patch also extracts
> DSI modes info from VBT and save the desired mode info to connector.
>
> v2 by Jani:
> - Drop GEN11 prefix from encoder name
> - Drop extra parenthesis
> - Drop extra local variable
> - Squash encoder power domain here
Looks good to me.
Regards,
Madhav
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 96 ++++++++++++++++++++++++++++++++++++++----
> 1 file changed, 88 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index 01f422df8c23..a117ecc6c5a3 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -799,10 +799,9 @@ static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
> wait_for_cmds_dispatched_to_panel(encoder);
> }
>
> -static void __attribute__((unused))
> -gen11_dsi_pre_enable(struct intel_encoder *encoder,
> - const struct intel_crtc_state *pipe_config,
> - const struct drm_connector_state *conn_state)
> +static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
> + const struct intel_crtc_state *pipe_config,
> + const struct drm_connector_state *conn_state)
> {
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>
> @@ -945,10 +944,9 @@ static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
> }
> }
>
> -static void __attribute__((unused)) gen11_dsi_disable(
> - struct intel_encoder *encoder,
> - const struct intel_crtc_state *old_crtc_state,
> - const struct drm_connector_state *old_conn_state)
> +static void gen11_dsi_disable(struct intel_encoder *encoder,
> + const struct intel_crtc_state *old_crtc_state,
> + const struct drm_connector_state *old_conn_state)
> {
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>
> @@ -972,10 +970,92 @@ static void __attribute__((unused)) gen11_dsi_disable(
> gen11_dsi_disable_io_power(encoder);
> }
>
> +static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
> +{
> + intel_encoder_destroy(encoder);
> +}
> +
> +static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
> + .destroy = gen11_dsi_encoder_destroy,
> +};
> +
> +static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
> +};
> +
> void icl_dsi_init(struct drm_i915_private *dev_priv)
> {
> + struct drm_device *dev = &dev_priv->drm;
> + struct intel_dsi *intel_dsi;
> + struct intel_encoder *encoder;
> + struct intel_connector *intel_connector;
> + struct drm_connector *connector;
> + struct drm_display_mode *scan, *fixed_mode = NULL;
> enum port port;
>
> if (!intel_bios_is_dsi_present(dev_priv, &port))
> return;
> +
> + intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
> + if (!intel_dsi)
> + return;
> +
> + intel_connector = intel_connector_alloc();
> + if (!intel_connector) {
> + kfree(intel_dsi);
> + return;
> + }
> +
> + encoder = &intel_dsi->base;
> + intel_dsi->attached_connector = intel_connector;
> + connector = &intel_connector->base;
> +
> + /* register DSI encoder with DRM subsystem */
> + drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs,
> + DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
> +
> + encoder->pre_enable = gen11_dsi_pre_enable;
> + encoder->disable = gen11_dsi_disable;
> + encoder->port = port;
> + encoder->type = INTEL_OUTPUT_DSI;
> + encoder->cloneable = 0;
> + encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
> + encoder->power_domain = POWER_DOMAIN_PORT_DSI;
> +
> + /* register DSI connector with DRM subsystem */
> + drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
> + DRM_MODE_CONNECTOR_DSI);
> + connector->display_info.subpixel_order = SubPixelHorizontalRGB;
> + connector->interlace_allowed = false;
> + connector->doublescan_allowed = false;
> +
> + /* attach connector to encoder */
> + intel_connector_attach_encoder(intel_connector, encoder);
> +
> + /* fill mode info from VBT */
> + mutex_lock(&dev->mode_config.mutex);
> + intel_dsi_vbt_get_modes(intel_dsi);
> + list_for_each_entry(scan, &connector->probed_modes, head) {
> + if (scan->type & DRM_MODE_TYPE_PREFERRED) {
> + fixed_mode = drm_mode_duplicate(dev, scan);
> + break;
> + }
> + }
> + mutex_unlock(&dev->mode_config.mutex);
> +
> + if (!fixed_mode) {
> + DRM_ERROR("DSI fixed mode info missing\n");
> + goto err;
> + }
> +
> + connector->display_info.width_mm = fixed_mode->width_mm;
> + connector->display_info.height_mm = fixed_mode->height_mm;
> + intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
> + intel_panel_setup_backlight(connector, INVALID_PIPE);
> +
> + return;
> +
> +err:
> + drm_encoder_cleanup(&encoder->base);
> + kfree(intel_dsi);
> + kfree(intel_connector);
> }
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v8 19/38] drm/i915/icl: Allocate hosts for DSI ports
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (17 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 18/38] drm/i915/icl: Allocate DSI encoder/connector Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-31 11:26 ` Madhav Chauhan
2018-10-30 11:56 ` [PATCH v8 20/38] drm/i915/icl: Add DSI packet payload/header registers Jani Nikula
` (23 subsequent siblings)
42 siblings, 1 reply; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
This patch allocates DSI host structure for each
DSI port available on gen11 and register them with
DSI fwk of DRM. Some of the DSI host operations are
also registered as part of this. This patch also fills
MIPI config block info from VBT to local structure.
v2 by Jani:
- indentation
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index a117ecc6c5a3..d0c60d402dfe 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -982,6 +982,23 @@ static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
};
+static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
+ struct mipi_dsi_device *dsi)
+{
+ return 0;
+}
+
+static int gen11_dsi_host_detach(struct mipi_dsi_host *host,
+ struct mipi_dsi_device *dsi)
+{
+ return 0;
+}
+
+static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
+ .attach = gen11_dsi_host_attach,
+ .detach = gen11_dsi_host_detach,
+};
+
void icl_dsi_init(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = &dev_priv->drm;
@@ -1052,6 +1069,21 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
intel_panel_setup_backlight(connector, INVALID_PIPE);
+ for_each_dsi_port(port, intel_dsi->ports) {
+ struct intel_dsi_host *host;
+
+ host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port);
+ if (!host)
+ goto err;
+
+ intel_dsi->dsi_hosts[port] = host;
+ }
+
+ if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
+ DRM_DEBUG_KMS("no device found\n");
+ goto err;
+ }
+
return;
err:
--
2.11.0
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^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [PATCH v8 19/38] drm/i915/icl: Allocate hosts for DSI ports
2018-10-30 11:56 ` [PATCH v8 19/38] drm/i915/icl: Allocate hosts for DSI ports Jani Nikula
@ 2018-10-31 11:26 ` Madhav Chauhan
0 siblings, 0 replies; 75+ messages in thread
From: Madhav Chauhan @ 2018-10-31 11:26 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 10/30/2018 5:26 PM, Jani Nikula wrote:
> This patch allocates DSI host structure for each
> DSI port available on gen11 and register them with
> DSI fwk of DRM. Some of the DSI host operations are
> also registered as part of this. This patch also fills
> MIPI config block info from VBT to local structure.
>
> v2 by Jani:
> - indentation
Looks fine.
Regards,
Madhav
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 32 ++++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index a117ecc6c5a3..d0c60d402dfe 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -982,6 +982,23 @@ static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
> static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
> };
>
> +static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
> + struct mipi_dsi_device *dsi)
> +{
> + return 0;
> +}
> +
> +static int gen11_dsi_host_detach(struct mipi_dsi_host *host,
> + struct mipi_dsi_device *dsi)
> +{
> + return 0;
> +}
> +
> +static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
> + .attach = gen11_dsi_host_attach,
> + .detach = gen11_dsi_host_detach,
> +};
> +
> void icl_dsi_init(struct drm_i915_private *dev_priv)
> {
> struct drm_device *dev = &dev_priv->drm;
> @@ -1052,6 +1069,21 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
> intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
> intel_panel_setup_backlight(connector, INVALID_PIPE);
>
> + for_each_dsi_port(port, intel_dsi->ports) {
> + struct intel_dsi_host *host;
> +
> + host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port);
> + if (!host)
> + goto err;
> +
> + intel_dsi->dsi_hosts[port] = host;
> + }
> +
> + if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
> + DRM_DEBUG_KMS("no device found\n");
> + goto err;
> + }
> +
> return;
>
> err:
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^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v8 20/38] drm/i915/icl: Add DSI packet payload/header registers
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (18 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 19/38] drm/i915/icl: Allocate hosts for DSI ports Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-31 11:43 ` Madhav Chauhan
2018-10-30 11:56 ` [PATCH v8 21/38] drm/i915/icl: Fetch DSI pkt to be transferred Jani Nikula
` (22 subsequent siblings)
42 siblings, 1 reply; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch defines payload/header registers for each DSI
transcoder used for transmitting DSI packets.
v2 by Jani:
- Drop full register mask and shift for payload
- Use lower case for hex 0x
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8d089ef848b2..639667d0fb00 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10523,6 +10523,28 @@ enum skl_power_gate {
#define MAX_HEADER_CREDIT 0x10
#define MAX_PLOAD_CREDIT 0x40
+#define _DSI_CMD_TXHDR_0 0x6b100
+#define _DSI_CMD_TXHDR_1 0x6b900
+#define DSI_CMD_TXHDR(tc) _MMIO_DSI(tc, \
+ _DSI_CMD_TXHDR_0,\
+ _DSI_CMD_TXHDR_1)
+#define PAYLOAD_PRESENT (1 << 31)
+#define LP_DATA_TRANSFER (1 << 30)
+#define VBLANK_FENCE (1 << 29)
+#define PARAM_WC_MASK (0xffff << 8)
+#define PARAM_WC_LOWER_SHIFT 8
+#define PARAM_WC_UPPER_SHIFT 16
+#define VC_MASK (0x3 << 6)
+#define VC_SHIFT 6
+#define DT_MASK (0x3f << 0)
+#define DT_SHIFT 0
+
+#define _DSI_CMD_TXPYLD_0 0x6b104
+#define _DSI_CMD_TXPYLD_1 0x6b904
+#define DSI_CMD_TXPYLD(tc) _MMIO_DSI(tc, \
+ _DSI_CMD_TXPYLD_0,\
+ _DSI_CMD_TXPYLD_1)
+
#define _DSI_LP_MSG_0 0x6b0d8
#define _DSI_LP_MSG_1 0x6b8d8
#define DSI_LP_MSG(tc) _MMIO_DSI(tc, \
--
2.11.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [PATCH v8 20/38] drm/i915/icl: Add DSI packet payload/header registers
2018-10-30 11:56 ` [PATCH v8 20/38] drm/i915/icl: Add DSI packet payload/header registers Jani Nikula
@ 2018-10-31 11:43 ` Madhav Chauhan
2018-11-01 11:10 ` Jani Nikula
0 siblings, 1 reply; 75+ messages in thread
From: Madhav Chauhan @ 2018-10-31 11:43 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 10/30/2018 5:26 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch defines payload/header registers for each DSI
> transcoder used for transmitting DSI packets.
>
> v2 by Jani:
> - Drop full register mask and shift for payload
> - Use lower case for hex 0x
v2 change are fine.
Regards,
Madhav
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8d089ef848b2..639667d0fb00 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10523,6 +10523,28 @@ enum skl_power_gate {
> #define MAX_HEADER_CREDIT 0x10
> #define MAX_PLOAD_CREDIT 0x40
>
> +#define _DSI_CMD_TXHDR_0 0x6b100
> +#define _DSI_CMD_TXHDR_1 0x6b900
> +#define DSI_CMD_TXHDR(tc) _MMIO_DSI(tc, \
> + _DSI_CMD_TXHDR_0,\
> + _DSI_CMD_TXHDR_1)
> +#define PAYLOAD_PRESENT (1 << 31)
> +#define LP_DATA_TRANSFER (1 << 30)
> +#define VBLANK_FENCE (1 << 29)
> +#define PARAM_WC_MASK (0xffff << 8)
> +#define PARAM_WC_LOWER_SHIFT 8
> +#define PARAM_WC_UPPER_SHIFT 16
> +#define VC_MASK (0x3 << 6)
> +#define VC_SHIFT 6
> +#define DT_MASK (0x3f << 0)
> +#define DT_SHIFT 0
> +
> +#define _DSI_CMD_TXPYLD_0 0x6b104
> +#define _DSI_CMD_TXPYLD_1 0x6b904
> +#define DSI_CMD_TXPYLD(tc) _MMIO_DSI(tc, \
> + _DSI_CMD_TXPYLD_0,\
> + _DSI_CMD_TXPYLD_1)
> +
> #define _DSI_LP_MSG_0 0x6b0d8
> #define _DSI_LP_MSG_1 0x6b8d8
> #define DSI_LP_MSG(tc) _MMIO_DSI(tc, \
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [PATCH v8 20/38] drm/i915/icl: Add DSI packet payload/header registers
2018-10-31 11:43 ` Madhav Chauhan
@ 2018-11-01 11:10 ` Jani Nikula
0 siblings, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-11-01 11:10 UTC (permalink / raw)
To: Madhav Chauhan, intel-gfx
On Wed, 31 Oct 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> On 10/30/2018 5:26 PM, Jani Nikula wrote:
>> From: Madhav Chauhan <madhav.chauhan@intel.com>
>>
>> This patch defines payload/header registers for each DSI
>> transcoder used for transmitting DSI packets.
>>
>> v2 by Jani:
>> - Drop full register mask and shift for payload
>> - Use lower case for hex 0x
>
> v2 change are fine.
Thanks, pushed.
BR,
Jani.
>
> Regards,
> Madhav
>
>>
>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++++++++++++++
>> 1 file changed, 22 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 8d089ef848b2..639667d0fb00 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -10523,6 +10523,28 @@ enum skl_power_gate {
>> #define MAX_HEADER_CREDIT 0x10
>> #define MAX_PLOAD_CREDIT 0x40
>>
>> +#define _DSI_CMD_TXHDR_0 0x6b100
>> +#define _DSI_CMD_TXHDR_1 0x6b900
>> +#define DSI_CMD_TXHDR(tc) _MMIO_DSI(tc, \
>> + _DSI_CMD_TXHDR_0,\
>> + _DSI_CMD_TXHDR_1)
>> +#define PAYLOAD_PRESENT (1 << 31)
>> +#define LP_DATA_TRANSFER (1 << 30)
>> +#define VBLANK_FENCE (1 << 29)
>> +#define PARAM_WC_MASK (0xffff << 8)
>> +#define PARAM_WC_LOWER_SHIFT 8
>> +#define PARAM_WC_UPPER_SHIFT 16
>> +#define VC_MASK (0x3 << 6)
>> +#define VC_SHIFT 6
>> +#define DT_MASK (0x3f << 0)
>> +#define DT_SHIFT 0
>> +
>> +#define _DSI_CMD_TXPYLD_0 0x6b104
>> +#define _DSI_CMD_TXPYLD_1 0x6b904
>> +#define DSI_CMD_TXPYLD(tc) _MMIO_DSI(tc, \
>> + _DSI_CMD_TXPYLD_0,\
>> + _DSI_CMD_TXPYLD_1)
>> +
>> #define _DSI_LP_MSG_0 0x6b0d8
>> #define _DSI_LP_MSG_1 0x6b8d8
>> #define DSI_LP_MSG(tc) _MMIO_DSI(tc, \
>
--
Jani Nikula, Intel Open Source Graphics Center
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v8 21/38] drm/i915/icl: Fetch DSI pkt to be transferred
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (19 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 20/38] drm/i915/icl: Add DSI packet payload/header registers Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-31 11:45 ` Madhav Chauhan
2018-10-30 11:56 ` [PATCH v8 22/38] drm/i915/icl: Load DSI packet payload to queue Jani Nikula
` (21 subsequent siblings)
42 siblings, 1 reply; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch retrieves DSI pkt (from DSI msg) to be
sent over DSI link using DRM DSI exported functions.
A wrapper function is also added as "DSI host transfer"
for sending DSI data/cmd.
v2 by Jani:
- Use the new credit available helper
- Use int for free_credits
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 62 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index d0c60d402dfe..c7b77cd81e45 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -107,6 +107,44 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
}
}
+static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
+ struct mipi_dsi_packet pkt, bool enable_lpdt)
+{
+ struct intel_dsi *intel_dsi = host->intel_dsi;
+ struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
+ enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
+ u32 tmp;
+ int free_credits;
+
+ /* check if header credit available */
+ free_credits = header_credits_available(dev_priv, dsi_trans);
+ if (free_credits < 1) {
+ DRM_ERROR("send pkt header failed, not enough hdr credits\n");
+ return -1;
+ }
+
+ tmp = I915_READ(DSI_CMD_TXHDR(dsi_trans));
+
+ if (pkt.payload)
+ tmp |= PAYLOAD_PRESENT;
+ else
+ tmp &= ~PAYLOAD_PRESENT;
+
+ tmp &= ~VBLANK_FENCE;
+
+ if (enable_lpdt)
+ tmp |= LP_DATA_TRANSFER;
+
+ tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
+ tmp |= ((pkt.header[0] & VC_MASK) << VC_SHIFT);
+ tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT);
+ tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT);
+ tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT);
+ I915_WRITE(DSI_CMD_TXHDR(dsi_trans), tmp);
+
+ return 0;
+}
+
static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -994,9 +1032,33 @@ static int gen11_dsi_host_detach(struct mipi_dsi_host *host,
return 0;
}
+static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
+ const struct mipi_dsi_msg *msg)
+{
+ struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
+ struct mipi_dsi_packet dsi_pkt;
+ ssize_t ret;
+ bool enable_lpdt = false;
+
+ ret = mipi_dsi_create_packet(&dsi_pkt, msg);
+ if (ret < 0)
+ return ret;
+
+ if (msg->flags & MIPI_DSI_MSG_USE_LPM)
+ enable_lpdt = true;
+
+ /* send packet header */
+ ret = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt);
+ if (ret < 0)
+ return ret;
+
+ return ret;
+}
+
static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
.attach = gen11_dsi_host_attach,
.detach = gen11_dsi_host_detach,
+ .transfer = gen11_dsi_host_transfer,
};
void icl_dsi_init(struct drm_i915_private *dev_priv)
--
2.11.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [PATCH v8 21/38] drm/i915/icl: Fetch DSI pkt to be transferred
2018-10-30 11:56 ` [PATCH v8 21/38] drm/i915/icl: Fetch DSI pkt to be transferred Jani Nikula
@ 2018-10-31 11:45 ` Madhav Chauhan
0 siblings, 0 replies; 75+ messages in thread
From: Madhav Chauhan @ 2018-10-31 11:45 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 10/30/2018 5:26 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch retrieves DSI pkt (from DSI msg) to be
> sent over DSI link using DRM DSI exported functions.
> A wrapper function is also added as "DSI host transfer"
> for sending DSI data/cmd.
>
> v2 by Jani:
> - Use the new credit available helper
> - Use int for free_credits
Changes looks fine, this also has squashing of some of the patches
for sending packet header. That info can be added in "v2 details"
Regards,
Madhav
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 62 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 62 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index d0c60d402dfe..c7b77cd81e45 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -107,6 +107,44 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
> }
> }
>
> +static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
> + struct mipi_dsi_packet pkt, bool enable_lpdt)
> +{
> + struct intel_dsi *intel_dsi = host->intel_dsi;
> + struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
> + enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
> + u32 tmp;
> + int free_credits;
> +
> + /* check if header credit available */
> + free_credits = header_credits_available(dev_priv, dsi_trans);
> + if (free_credits < 1) {
> + DRM_ERROR("send pkt header failed, not enough hdr credits\n");
> + return -1;
> + }
> +
> + tmp = I915_READ(DSI_CMD_TXHDR(dsi_trans));
> +
> + if (pkt.payload)
> + tmp |= PAYLOAD_PRESENT;
> + else
> + tmp &= ~PAYLOAD_PRESENT;
> +
> + tmp &= ~VBLANK_FENCE;
> +
> + if (enable_lpdt)
> + tmp |= LP_DATA_TRANSFER;
> +
> + tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
> + tmp |= ((pkt.header[0] & VC_MASK) << VC_SHIFT);
> + tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT);
> + tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT);
> + tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT);
> + I915_WRITE(DSI_CMD_TXHDR(dsi_trans), tmp);
> +
> + return 0;
> +}
> +
> static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> @@ -994,9 +1032,33 @@ static int gen11_dsi_host_detach(struct mipi_dsi_host *host,
> return 0;
> }
>
> +static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
> + const struct mipi_dsi_msg *msg)
> +{
> + struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
> + struct mipi_dsi_packet dsi_pkt;
> + ssize_t ret;
> + bool enable_lpdt = false;
> +
> + ret = mipi_dsi_create_packet(&dsi_pkt, msg);
> + if (ret < 0)
> + return ret;
> +
> + if (msg->flags & MIPI_DSI_MSG_USE_LPM)
> + enable_lpdt = true;
> +
> + /* send packet header */
> + ret = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt);
> + if (ret < 0)
> + return ret;
> +
> + return ret;
> +}
> +
> static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
> .attach = gen11_dsi_host_attach,
> .detach = gen11_dsi_host_detach,
> + .transfer = gen11_dsi_host_transfer,
> };
>
> void icl_dsi_init(struct drm_i915_private *dev_priv)
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^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v8 22/38] drm/i915/icl: Load DSI packet payload to queue
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (20 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 21/38] drm/i915/icl: Fetch DSI pkt to be transferred Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-31 11:51 ` Madhav Chauhan
2018-10-30 11:56 ` [PATCH v8 23/38] drm/i915/icl: Add get config functionality for DSI Jani Nikula
` (20 subsequent siblings)
42 siblings, 1 reply; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
This patch adds DSI packet payload to command payload
queue using credit based mechanism for *long* packets.
v2 by Jani:
- Add intel_dsi local variable for better code flow
- Use the new credit available helper
- Use int for free_credits, i, and j
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 57 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index c7b77cd81e45..58774a1ac84b 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -107,6 +107,33 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
}
}
+static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data,
+ u32 len)
+{
+ struct intel_dsi *intel_dsi = host->intel_dsi;
+ struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
+ enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
+ int free_credits;
+ int i, j;
+
+ for (i = 0; i < len; i += 4) {
+ u32 tmp = 0;
+
+ free_credits = payload_credits_available(dev_priv, dsi_trans);
+ if (free_credits < 1) {
+ DRM_ERROR("Payload credit not available\n");
+ return false;
+ }
+
+ for (j = 0; j < min_t(u32, len - i, 4); j++)
+ tmp |= *data++ << 8 * j;
+
+ I915_WRITE(DSI_CMD_TXPYLD(dsi_trans), tmp);
+ }
+
+ return true;
+}
+
static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
struct mipi_dsi_packet pkt, bool enable_lpdt)
{
@@ -145,6 +172,25 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
return 0;
}
+static int dsi_send_pkt_payld(struct intel_dsi_host *host,
+ struct mipi_dsi_packet pkt)
+{
+ /* payload queue can accept *256 bytes*, check limit */
+ if (pkt.payload_length > MAX_PLOAD_CREDIT * 4) {
+ DRM_ERROR("payload size exceeds max queue limit\n");
+ return -1;
+ }
+
+ /* load data into command payload queue */
+ if (!add_payld_to_queue(host, pkt.payload,
+ pkt.payload_length)) {
+ DRM_ERROR("adding payload to queue failed\n");
+ return -1;
+ }
+
+ return 0;
+}
+
static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -1052,6 +1098,17 @@ static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
if (ret < 0)
return ret;
+ /* only long packet contains payload */
+ if (mipi_dsi_packet_format_is_long(msg->type)) {
+ ret = dsi_send_pkt_payld(intel_dsi_host, dsi_pkt);
+ if (ret < 0)
+ return ret;
+ }
+
+ //TODO: add payload receive code if needed
+
+ ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length;
+
return ret;
}
--
2.11.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [PATCH v8 22/38] drm/i915/icl: Load DSI packet payload to queue
2018-10-30 11:56 ` [PATCH v8 22/38] drm/i915/icl: Load DSI packet payload to queue Jani Nikula
@ 2018-10-31 11:51 ` Madhav Chauhan
0 siblings, 0 replies; 75+ messages in thread
From: Madhav Chauhan @ 2018-10-31 11:51 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 10/30/2018 5:26 PM, Jani Nikula wrote:
> This patch adds DSI packet payload to command payload
> queue using credit based mechanism for *long* packets.
>
> v2 by Jani:
> - Add intel_dsi local variable for better code flow
> - Use the new credit available helper
> - Use int for free_credits, i, and j
v2 changes are fine.
Regards,
Madhav
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 57 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 57 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index c7b77cd81e45..58774a1ac84b 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -107,6 +107,33 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
> }
> }
>
> +static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data,
> + u32 len)
> +{
> + struct intel_dsi *intel_dsi = host->intel_dsi;
> + struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
> + enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
> + int free_credits;
> + int i, j;
> +
> + for (i = 0; i < len; i += 4) {
> + u32 tmp = 0;
> +
> + free_credits = payload_credits_available(dev_priv, dsi_trans);
> + if (free_credits < 1) {
> + DRM_ERROR("Payload credit not available\n");
> + return false;
> + }
> +
> + for (j = 0; j < min_t(u32, len - i, 4); j++)
> + tmp |= *data++ << 8 * j;
> +
> + I915_WRITE(DSI_CMD_TXPYLD(dsi_trans), tmp);
> + }
> +
> + return true;
> +}
> +
> static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
> struct mipi_dsi_packet pkt, bool enable_lpdt)
> {
> @@ -145,6 +172,25 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
> return 0;
> }
>
> +static int dsi_send_pkt_payld(struct intel_dsi_host *host,
> + struct mipi_dsi_packet pkt)
> +{
> + /* payload queue can accept *256 bytes*, check limit */
> + if (pkt.payload_length > MAX_PLOAD_CREDIT * 4) {
> + DRM_ERROR("payload size exceeds max queue limit\n");
> + return -1;
> + }
> +
> + /* load data into command payload queue */
> + if (!add_payld_to_queue(host, pkt.payload,
> + pkt.payload_length)) {
> + DRM_ERROR("adding payload to queue failed\n");
> + return -1;
> + }
> +
> + return 0;
> +}
> +
> static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> @@ -1052,6 +1098,17 @@ static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
> if (ret < 0)
> return ret;
>
> + /* only long packet contains payload */
> + if (mipi_dsi_packet_format_is_long(msg->type)) {
> + ret = dsi_send_pkt_payld(intel_dsi_host, dsi_pkt);
> + if (ret < 0)
> + return ret;
> + }
> +
> + //TODO: add payload receive code if needed
> +
> + ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length;
> +
> return ret;
> }
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v8 23/38] drm/i915/icl: Add get config functionality for DSI
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (21 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 22/38] drm/i915/icl: Load DSI packet payload to queue Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-30 11:56 ` [PATCH v8 24/38] drm/i915/icl: Get HW state for DSI encoder Jani Nikula
` (19 subsequent siblings)
42 siblings, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch implements the functionality for getting PIPE
configuration to which DSI encoder is connected. Used during
the atomic modeset.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 58774a1ac84b..83612c444eab 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1054,6 +1054,19 @@ static void gen11_dsi_disable(struct intel_encoder *encoder,
gen11_dsi_disable_io_power(encoder);
}
+static void gen11_dsi_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config)
+{
+ struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
+ base);
+ u32 pixel_clk;
+
+ //FIXME: Calculate pixel clock using PLL functions once implemented.
+ pixel_clk = intel_dsi->pclk;
+ pipe_config->base.adjusted_mode.crtc_clock = pixel_clk;
+ pipe_config->port_clock = pixel_clk;
+}
+
static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
{
intel_encoder_destroy(encoder);
@@ -1152,6 +1165,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
encoder->pre_enable = gen11_dsi_pre_enable;
encoder->disable = gen11_dsi_disable;
encoder->port = port;
+ encoder->get_config = gen11_dsi_get_config;
encoder->type = INTEL_OUTPUT_DSI;
encoder->cloneable = 0;
encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
--
2.11.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 75+ messages in thread* [PATCH v8 24/38] drm/i915/icl: Get HW state for DSI encoder
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (22 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 23/38] drm/i915/icl: Add get config functionality for DSI Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-31 11:57 ` Madhav Chauhan
2018-11-01 14:24 ` Imre Deak
2018-10-30 11:56 ` [PATCH v8 25/38] drm/i915/icl: Add DSI connector functions Jani Nikula
` (18 subsequent siblings)
42 siblings, 2 replies; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch read out the current hw state for DSI and
return true if encoder is active.
v2 by Jani:
- Squash connector get hw state hook here
- Squash encode get hw state fix here
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 42 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 83612c444eab..0c1f84cca16e 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1067,6 +1067,46 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
pipe_config->port_clock = pixel_clk;
}
+static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
+ enum pipe *pipe)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ u32 tmp;
+ enum port port;
+ enum transcoder dsi_trans;
+ bool ret = false;
+
+ if (!intel_display_power_get_if_enabled(dev_priv,
+ encoder->power_domain))
+ return false;
+
+ for_each_dsi_port(port, intel_dsi->ports) {
+ dsi_trans = dsi_port_to_transcoder(port);
+ tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
+ switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
+ case TRANS_DDI_EDP_INPUT_A_ON:
+ *pipe = PIPE_A;
+ break;
+ case TRANS_DDI_EDP_INPUT_B_ONOFF:
+ *pipe = PIPE_B;
+ break;
+ case TRANS_DDI_EDP_INPUT_C_ONOFF:
+ *pipe = PIPE_C;
+ break;
+ default:
+ DRM_ERROR("Invalid PIPE input\n");
+ goto out;
+ }
+
+ tmp = I915_READ(PIPECONF(dsi_trans));
+ ret = tmp & PIPECONF_ENABLE;
+ }
+out:
+ intel_display_power_put(dev_priv, encoder->power_domain);
+ return ret;
+}
+
static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
{
intel_encoder_destroy(encoder);
@@ -1166,6 +1206,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
encoder->disable = gen11_dsi_disable;
encoder->port = port;
encoder->get_config = gen11_dsi_get_config;
+ encoder->get_hw_state = gen11_dsi_get_hw_state;
encoder->type = INTEL_OUTPUT_DSI;
encoder->cloneable = 0;
encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
@@ -1177,6 +1218,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
connector->display_info.subpixel_order = SubPixelHorizontalRGB;
connector->interlace_allowed = false;
connector->doublescan_allowed = false;
+ intel_connector->get_hw_state = intel_connector_get_hw_state;
/* attach connector to encoder */
intel_connector_attach_encoder(intel_connector, encoder);
--
2.11.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [PATCH v8 24/38] drm/i915/icl: Get HW state for DSI encoder
2018-10-30 11:56 ` [PATCH v8 24/38] drm/i915/icl: Get HW state for DSI encoder Jani Nikula
@ 2018-10-31 11:57 ` Madhav Chauhan
2018-11-01 14:24 ` Imre Deak
1 sibling, 0 replies; 75+ messages in thread
From: Madhav Chauhan @ 2018-10-31 11:57 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 10/30/2018 5:26 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch read out the current hw state for DSI and
> return true if encoder is active.
>
> v2 by Jani:
> - Squash connector get hw state hook here
> - Squash encode get hw state fix here
Looks fine to me.
Regards,
Madhav
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 42 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 42 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index 83612c444eab..0c1f84cca16e 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -1067,6 +1067,46 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
> pipe_config->port_clock = pixel_clk;
> }
>
> +static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
> + enum pipe *pipe)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + u32 tmp;
> + enum port port;
> + enum transcoder dsi_trans;
> + bool ret = false;
> +
> + if (!intel_display_power_get_if_enabled(dev_priv,
> + encoder->power_domain))
> + return false;
> +
> + for_each_dsi_port(port, intel_dsi->ports) {
> + dsi_trans = dsi_port_to_transcoder(port);
> + tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
> + switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
> + case TRANS_DDI_EDP_INPUT_A_ON:
> + *pipe = PIPE_A;
> + break;
> + case TRANS_DDI_EDP_INPUT_B_ONOFF:
> + *pipe = PIPE_B;
> + break;
> + case TRANS_DDI_EDP_INPUT_C_ONOFF:
> + *pipe = PIPE_C;
> + break;
> + default:
> + DRM_ERROR("Invalid PIPE input\n");
> + goto out;
> + }
> +
> + tmp = I915_READ(PIPECONF(dsi_trans));
> + ret = tmp & PIPECONF_ENABLE;
> + }
> +out:
> + intel_display_power_put(dev_priv, encoder->power_domain);
> + return ret;
> +}
> +
> static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
> {
> intel_encoder_destroy(encoder);
> @@ -1166,6 +1206,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
> encoder->disable = gen11_dsi_disable;
> encoder->port = port;
> encoder->get_config = gen11_dsi_get_config;
> + encoder->get_hw_state = gen11_dsi_get_hw_state;
> encoder->type = INTEL_OUTPUT_DSI;
> encoder->cloneable = 0;
> encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
> @@ -1177,6 +1218,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
> connector->display_info.subpixel_order = SubPixelHorizontalRGB;
> connector->interlace_allowed = false;
> connector->doublescan_allowed = false;
> + intel_connector->get_hw_state = intel_connector_get_hw_state;
>
> /* attach connector to encoder */
> intel_connector_attach_encoder(intel_connector, encoder);
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [PATCH v8 24/38] drm/i915/icl: Get HW state for DSI encoder
2018-10-30 11:56 ` [PATCH v8 24/38] drm/i915/icl: Get HW state for DSI encoder Jani Nikula
2018-10-31 11:57 ` Madhav Chauhan
@ 2018-11-01 14:24 ` Imre Deak
1 sibling, 0 replies; 75+ messages in thread
From: Imre Deak @ 2018-11-01 14:24 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Oct 30, 2018 at 01:56:30PM +0200, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch read out the current hw state for DSI and
> return true if encoder is active.
>
> v2 by Jani:
> - Squash connector get hw state hook here
> - Squash encode get hw state fix here
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 42 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 42 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index 83612c444eab..0c1f84cca16e 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -1067,6 +1067,46 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
> pipe_config->port_clock = pixel_clk;
> }
>
> +static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
> + enum pipe *pipe)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + u32 tmp;
> + enum port port;
> + enum transcoder dsi_trans;
> + bool ret = false;
> +
> + if (!intel_display_power_get_if_enabled(dev_priv,
> + encoder->power_domain))
> + return false;
> +
> + for_each_dsi_port(port, intel_dsi->ports) {
> + dsi_trans = dsi_port_to_transcoder(port);
> + tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
> + switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
> + case TRANS_DDI_EDP_INPUT_A_ON:
> + *pipe = PIPE_A;
> + break;
> + case TRANS_DDI_EDP_INPUT_B_ONOFF:
> + *pipe = PIPE_B;
> + break;
> + case TRANS_DDI_EDP_INPUT_C_ONOFF:
> + *pipe = PIPE_C;
> + break;
> + default:
> + DRM_ERROR("Invalid PIPE input\n");
> + goto out;
> + }
> +
> + tmp = I915_READ(PIPECONF(dsi_trans));
> + ret = tmp & PIPECONF_ENABLE;
> + }
> +out:
> + intel_display_power_put(dev_priv, encoder->power_domain);
> + return ret;
> +}
> +
> static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
> {
> intel_encoder_destroy(encoder);
> @@ -1166,6 +1206,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
> encoder->disable = gen11_dsi_disable;
> encoder->port = port;
> encoder->get_config = gen11_dsi_get_config;
> + encoder->get_hw_state = gen11_dsi_get_hw_state;
Since the encoder enable hook gets a power domain reference, we have to
make sure we take this reference during HW readout, if the encoder was
enabled. That can be done by defining the encoder->get_power_domains
hook returning those references, similarly to
intel_ddi_get_power_domains().
> encoder->type = INTEL_OUTPUT_DSI;
> encoder->cloneable = 0;
> encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
> @@ -1177,6 +1218,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
> connector->display_info.subpixel_order = SubPixelHorizontalRGB;
> connector->interlace_allowed = false;
> connector->doublescan_allowed = false;
> + intel_connector->get_hw_state = intel_connector_get_hw_state;
>
> /* attach connector to encoder */
> intel_connector_attach_encoder(intel_connector, encoder);
> --
> 2.11.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v8 25/38] drm/i915/icl: Add DSI connector functions
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (23 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 24/38] drm/i915/icl: Get HW state for DSI encoder Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-11-01 14:03 ` Madhav Chauhan
2018-10-30 11:56 ` [PATCH v8 26/38] drm/i915/icl: Add DSI connector helper functions Jani Nikula
` (17 subsequent siblings)
42 siblings, 1 reply; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch assigns connector functions for DSI to
DRM connector structure.
v2 by Jani:
- use common connector destroy hook
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 0c1f84cca16e..5b33b7ac8e8f 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -26,6 +26,7 @@
*/
#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_atomic_helper.h>
#include "intel_dsi.h"
static inline int header_credits_available(struct drm_i915_private *dev_priv,
@@ -1117,6 +1118,14 @@ static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
};
static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
+ .late_register = intel_connector_register,
+ .early_unregister = intel_connector_unregister,
+ .destroy = intel_connector_destroy,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .atomic_get_property = intel_digital_connector_atomic_get_property,
+ .atomic_set_property = intel_digital_connector_atomic_set_property,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+ .atomic_duplicate_state = intel_digital_connector_duplicate_state,
};
static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
--
2.11.0
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^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [PATCH v8 25/38] drm/i915/icl: Add DSI connector functions
2018-10-30 11:56 ` [PATCH v8 25/38] drm/i915/icl: Add DSI connector functions Jani Nikula
@ 2018-11-01 14:03 ` Madhav Chauhan
0 siblings, 0 replies; 75+ messages in thread
From: Madhav Chauhan @ 2018-11-01 14:03 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 10/30/2018 5:26 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch assigns connector functions for DSI to
> DRM connector structure.
>
> v2 by Jani:
> - use common connector destroy hook
Looks OK to me.
Regards,
Madhav
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index 0c1f84cca16e..5b33b7ac8e8f 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -26,6 +26,7 @@
> */
>
> #include <drm/drm_mipi_dsi.h>
> +#include <drm/drm_atomic_helper.h>
> #include "intel_dsi.h"
>
> static inline int header_credits_available(struct drm_i915_private *dev_priv,
> @@ -1117,6 +1118,14 @@ static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
> };
>
> static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
> + .late_register = intel_connector_register,
> + .early_unregister = intel_connector_unregister,
> + .destroy = intel_connector_destroy,
> + .fill_modes = drm_helper_probe_single_connector_modes,
> + .atomic_get_property = intel_digital_connector_atomic_get_property,
> + .atomic_set_property = intel_digital_connector_atomic_set_property,
> + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> + .atomic_duplicate_state = intel_digital_connector_duplicate_state,
> };
>
> static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
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^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v8 26/38] drm/i915/icl: Add DSI connector helper functions
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (24 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 25/38] drm/i915/icl: Add DSI connector functions Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-11-01 14:03 ` Madhav Chauhan
2018-10-30 11:56 ` [PATCH v8 27/38] drm/i915/icl: Add DSI encoder remaining functions Jani Nikula
` (16 subsequent siblings)
42 siblings, 1 reply; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch registers DSI connectors helper functions
with DRM driver.
v2 by Jani:
- Indentation change
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 5b33b7ac8e8f..c12c7d53bcff 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1128,6 +1128,12 @@ static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
.atomic_duplicate_state = intel_digital_connector_duplicate_state,
};
+static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = {
+ .get_modes = intel_dsi_get_modes,
+ .mode_valid = intel_dsi_mode_valid,
+ .atomic_check = intel_digital_connector_atomic_check,
+};
+
static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
struct mipi_dsi_device *dsi)
{
@@ -1224,6 +1230,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
/* register DSI connector with DRM subsystem */
drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
DRM_MODE_CONNECTOR_DSI);
+ drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs);
connector->display_info.subpixel_order = SubPixelHorizontalRGB;
connector->interlace_allowed = false;
connector->doublescan_allowed = false;
--
2.11.0
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^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [PATCH v8 26/38] drm/i915/icl: Add DSI connector helper functions
2018-10-30 11:56 ` [PATCH v8 26/38] drm/i915/icl: Add DSI connector helper functions Jani Nikula
@ 2018-11-01 14:03 ` Madhav Chauhan
0 siblings, 0 replies; 75+ messages in thread
From: Madhav Chauhan @ 2018-11-01 14:03 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 10/30/2018 5:26 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch registers DSI connectors helper functions
> with DRM driver.
>
> v2 by Jani:
> - Indentation change
Ok.
Regards,
Madhav
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index 5b33b7ac8e8f..c12c7d53bcff 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -1128,6 +1128,12 @@ static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
> .atomic_duplicate_state = intel_digital_connector_duplicate_state,
> };
>
> +static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = {
> + .get_modes = intel_dsi_get_modes,
> + .mode_valid = intel_dsi_mode_valid,
> + .atomic_check = intel_digital_connector_atomic_check,
> +};
> +
> static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
> struct mipi_dsi_device *dsi)
> {
> @@ -1224,6 +1230,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
> /* register DSI connector with DRM subsystem */
> drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,
> DRM_MODE_CONNECTOR_DSI);
> + drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs);
> connector->display_info.subpixel_order = SubPixelHorizontalRGB;
> connector->interlace_allowed = false;
> connector->doublescan_allowed = false;
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^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v8 27/38] drm/i915/icl: Add DSI encoder remaining functions
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (25 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 26/38] drm/i915/icl: Add DSI connector helper functions Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-11-01 14:08 ` Madhav Chauhan
2018-10-30 11:56 ` [PATCH v8 28/38] drm/i915/icl: Fill DSI ports info Jani Nikula
` (15 subsequent siblings)
42 siblings, 1 reply; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch implements compute config and enable function
for Gen11 DSI encoder which is required at the time of
modeset. Enable function is empty as functionality is
implemented inside pre-enable function but still needed
otherwise null pointer dereference during modeset.
v2 by Jani:
- drop the enable nop hook
- fixed_mode is always true
- HAS_GMCH_DISPLAY() is always false
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index c12c7d53bcff..7a000a660c12 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1068,6 +1068,37 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
pipe_config->port_clock = pixel_clk;
}
+static bool gen11_dsi_compute_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config,
+ struct drm_connector_state *conn_state)
+{
+ struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
+ base);
+ struct intel_connector *intel_connector = intel_dsi->attached_connector;
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
+ const struct drm_display_mode *fixed_mode =
+ intel_connector->panel.fixed_mode;
+ struct drm_display_mode *adjusted_mode =
+ &pipe_config->base.adjusted_mode;
+
+ intel_fixed_panel_mode(fixed_mode, adjusted_mode);
+ intel_pch_panel_fitting(crtc, pipe_config, conn_state->scaling_mode);
+
+ adjusted_mode->flags = 0;
+
+ /* Dual link goes to trancoder DSI'0' */
+ if (intel_dsi->ports == BIT(PORT_B))
+ pipe_config->cpu_transcoder = TRANSCODER_DSI_1;
+ else
+ pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
+
+ pipe_config->clock_set = true;
+
+ //TODO: Add check if DSI PLL calculation is done
+
+ return true;
+}
+
static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
enum pipe *pipe)
{
@@ -1221,6 +1252,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
encoder->disable = gen11_dsi_disable;
encoder->port = port;
encoder->get_config = gen11_dsi_get_config;
+ encoder->compute_config = gen11_dsi_compute_config;
encoder->get_hw_state = gen11_dsi_get_hw_state;
encoder->type = INTEL_OUTPUT_DSI;
encoder->cloneable = 0;
--
2.11.0
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^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [PATCH v8 27/38] drm/i915/icl: Add DSI encoder remaining functions
2018-10-30 11:56 ` [PATCH v8 27/38] drm/i915/icl: Add DSI encoder remaining functions Jani Nikula
@ 2018-11-01 14:08 ` Madhav Chauhan
0 siblings, 0 replies; 75+ messages in thread
From: Madhav Chauhan @ 2018-11-01 14:08 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 10/30/2018 5:26 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch implements compute config and enable function
> for Gen11 DSI encoder which is required at the time of
> modeset. Enable function is empty as functionality is
> implemented inside pre-enable function but still needed
> otherwise null pointer dereference during modeset.
>
> v2 by Jani:
> - drop the enable nop hook
> - fixed_mode is always true
> - HAS_GMCH_DISPLAY() is always false
Changes looks fine.
Regards,
Madhav
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 32 ++++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index c12c7d53bcff..7a000a660c12 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -1068,6 +1068,37 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
> pipe_config->port_clock = pixel_clk;
> }
>
> +static bool gen11_dsi_compute_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config,
> + struct drm_connector_state *conn_state)
> +{
> + struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
> + base);
> + struct intel_connector *intel_connector = intel_dsi->attached_connector;
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
> + const struct drm_display_mode *fixed_mode =
> + intel_connector->panel.fixed_mode;
> + struct drm_display_mode *adjusted_mode =
> + &pipe_config->base.adjusted_mode;
> +
> + intel_fixed_panel_mode(fixed_mode, adjusted_mode);
> + intel_pch_panel_fitting(crtc, pipe_config, conn_state->scaling_mode);
> +
> + adjusted_mode->flags = 0;
> +
> + /* Dual link goes to trancoder DSI'0' */
> + if (intel_dsi->ports == BIT(PORT_B))
> + pipe_config->cpu_transcoder = TRANSCODER_DSI_1;
> + else
> + pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
> +
> + pipe_config->clock_set = true;
> +
> + //TODO: Add check if DSI PLL calculation is done
> +
> + return true;
> +}
> +
> static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
> enum pipe *pipe)
> {
> @@ -1221,6 +1252,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
> encoder->disable = gen11_dsi_disable;
> encoder->port = port;
> encoder->get_config = gen11_dsi_get_config;
> + encoder->compute_config = gen11_dsi_compute_config;
> encoder->get_hw_state = gen11_dsi_get_hw_state;
> encoder->type = INTEL_OUTPUT_DSI;
> encoder->cloneable = 0;
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^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v8 28/38] drm/i915/icl: Fill DSI ports info
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (26 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 27/38] drm/i915/icl: Add DSI encoder remaining functions Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-30 11:56 ` [PATCH v8 29/38] drm/i915/icl: Add DSS_CTL Registers Jani Nikula
` (14 subsequent siblings)
42 siblings, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch fills backlight, CABC and general port
info for Gen11 DSI.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 7a000a660c12..b2897281d42c 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1292,6 +1292,14 @@ void icl_dsi_init(struct drm_i915_private *dev_priv)
intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
intel_panel_setup_backlight(connector, INVALID_PIPE);
+ if (dev_priv->vbt.dsi.config->dual_link)
+ intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
+ else
+ intel_dsi->ports = BIT(port);
+
+ intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
+ intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
+
for_each_dsi_port(port, intel_dsi->ports) {
struct intel_dsi_host *host;
--
2.11.0
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^ permalink raw reply related [flat|nested] 75+ messages in thread* [PATCH v8 29/38] drm/i915/icl: Add DSS_CTL Registers
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (27 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 28/38] drm/i915/icl: Fill DSI ports info Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-11-01 15:27 ` Jani Nikula
2018-10-30 11:56 ` [PATCH v8 30/38] drm/i915/icl: Configure DSI Dual link mode Jani Nikula
` (13 subsequent siblings)
42 siblings, 1 reply; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, Rodrigo Vivi
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
Add defines for DSS_CTL registers.
These registers specify the big joiner, splitter,
overlap pixels and info regarding
compression enabled on left or right branch.
v2:
- rebase. Remove overlapping defines(James Ausmus)
- Rename the register to ICL_DSS_CTL1/2_PIPE_ (manasi)
- take pixels as an argument for overlap.(Manasi)
v3:
- rebase. merge DSS_CTL1/2 introduced in Madhav's patch
to avoid confusion (madhav chauhan)
- Rename registers in accordance to BSpec (Madhav, Rodrigo)
- Add define to conditionally check the buffer target depth (James Ausmus)
v4:
- remove redundant definitions.(madhav)
v5:
- Add mask for overlap pixels.
- Code Style changes.(Madhav)
v6:
- Code style changes. (Madhav)
Suggested-by: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Cc: Gaurav Singh <gaurav.k.singh@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 639667d0fb00..b9aaa71dabe2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10033,6 +10033,39 @@ enum skl_power_gate {
_ICL_DSI_IO_MODECTL_1)
#define COMBO_PHY_MODE_DSI (1 << 0)
+/* Display Stream Splitter Control */
+#define DSS_CTL1 _MMIO(0x67400)
+#define SPLITTER_ENABLE (1 << 31)
+#define JOINER_ENABLE (1 << 30)
+#define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
+#define DUAL_LINK_MODE_FRONTBACK (0 << 24)
+#define OVERLAP_PIXELS_MASK (0xf << 16)
+#define OVERLAP_PIXELS(pixels) ((pixels) << 16)
+#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
+#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
+#define MAX_DL_BUFFER_TARGET_DEPTH 0x5A0
+
+#define DSS_CTL2 _MMIO(0x67404)
+#define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
+#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
+#define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
+#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
+
+#define _PIPE_DSS_CTL1_PB 0x78200
+#define _PIPE_DSS_CTL1_PC 0x78400
+#define PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _PIPE_DSS_CTL1_PB, \
+ _PIPE_DSS_CTL1_PC)
+#define BIG_JOINER_ENABLE (1 << 29)
+#define MASTER_BIG_JOINER_ENABLE (1 << 28)
+#define VGA_CENTERING_ENABLE (1 << 27)
+
+#define _PIPE_DSS_CTL2_PB 0x78204
+#define _PIPE_DSS_CTL2_PC 0x78404
+#define PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _PIPE_DSS_CTL2_PB, \
+ _PIPE_DSS_CTL2_PC)
+
#define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
#define STAP_SELECT (1 << 0)
--
2.11.0
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^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [PATCH v8 29/38] drm/i915/icl: Add DSS_CTL Registers
2018-10-30 11:56 ` [PATCH v8 29/38] drm/i915/icl: Add DSS_CTL Registers Jani Nikula
@ 2018-11-01 15:27 ` Jani Nikula
2018-11-01 18:12 ` Manasi Navare
0 siblings, 1 reply; 75+ messages in thread
From: Jani Nikula @ 2018-11-01 15:27 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
On Tue, 30 Oct 2018, Jani Nikula <jani.nikula@intel.com> wrote:
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> Add defines for DSS_CTL registers.
> These registers specify the big joiner, splitter,
> overlap pixels and info regarding
> compression enabled on left or right branch.
>
> v2:
> - rebase. Remove overlapping defines(James Ausmus)
> - Rename the register to ICL_DSS_CTL1/2_PIPE_ (manasi)
> - take pixels as an argument for overlap.(Manasi)
>
> v3:
> - rebase. merge DSS_CTL1/2 introduced in Madhav's patch
> to avoid confusion (madhav chauhan)
> - Rename registers in accordance to BSpec (Madhav, Rodrigo)
> - Add define to conditionally check the buffer target depth (James Ausmus)
>
> v4:
> - remove redundant definitions.(madhav)
>
> v5:
> - Add mask for overlap pixels.
> - Code Style changes.(Madhav)
> v6:
> - Code style changes. (Madhav)
>
> Suggested-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> Cc: Gaurav Singh <gaurav.k.singh@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Pushed to dinq.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/i915_reg.h | 33 +++++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 639667d0fb00..b9aaa71dabe2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10033,6 +10033,39 @@ enum skl_power_gate {
> _ICL_DSI_IO_MODECTL_1)
> #define COMBO_PHY_MODE_DSI (1 << 0)
>
> +/* Display Stream Splitter Control */
> +#define DSS_CTL1 _MMIO(0x67400)
> +#define SPLITTER_ENABLE (1 << 31)
> +#define JOINER_ENABLE (1 << 30)
> +#define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
> +#define DUAL_LINK_MODE_FRONTBACK (0 << 24)
> +#define OVERLAP_PIXELS_MASK (0xf << 16)
> +#define OVERLAP_PIXELS(pixels) ((pixels) << 16)
> +#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
> +#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
> +#define MAX_DL_BUFFER_TARGET_DEPTH 0x5A0
> +
> +#define DSS_CTL2 _MMIO(0x67404)
> +#define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
> +#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
> +#define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
> +#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
> +
> +#define _PIPE_DSS_CTL1_PB 0x78200
> +#define _PIPE_DSS_CTL1_PC 0x78400
> +#define PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _PIPE_DSS_CTL1_PB, \
> + _PIPE_DSS_CTL1_PC)
> +#define BIG_JOINER_ENABLE (1 << 29)
> +#define MASTER_BIG_JOINER_ENABLE (1 << 28)
> +#define VGA_CENTERING_ENABLE (1 << 27)
> +
> +#define _PIPE_DSS_CTL2_PB 0x78204
> +#define _PIPE_DSS_CTL2_PC 0x78404
> +#define PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _PIPE_DSS_CTL2_PB, \
> + _PIPE_DSS_CTL2_PC)
> +
> #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
> #define STAP_SELECT (1 << 0)
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
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^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [PATCH v8 29/38] drm/i915/icl: Add DSS_CTL Registers
2018-11-01 15:27 ` Jani Nikula
@ 2018-11-01 18:12 ` Manasi Navare
0 siblings, 0 replies; 75+ messages in thread
From: Manasi Navare @ 2018-11-01 18:12 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, Rodrigo Vivi
On Thu, Nov 01, 2018 at 05:27:47PM +0200, Jani Nikula wrote:
> On Tue, 30 Oct 2018, Jani Nikula <jani.nikula@intel.com> wrote:
> > From: Anusha Srivatsa <anusha.srivatsa@intel.com>
> >
> > Add defines for DSS_CTL registers.
> > These registers specify the big joiner, splitter,
> > overlap pixels and info regarding
> > compression enabled on left or right branch.
> >
> > v2:
> > - rebase. Remove overlapping defines(James Ausmus)
> > - Rename the register to ICL_DSS_CTL1/2_PIPE_ (manasi)
> > - take pixels as an argument for overlap.(Manasi)
> >
> > v3:
> > - rebase. merge DSS_CTL1/2 introduced in Madhav's patch
> > to avoid confusion (madhav chauhan)
> > - Rename registers in accordance to BSpec (Madhav, Rodrigo)
> > - Add define to conditionally check the buffer target depth (James Ausmus)
> >
> > v4:
> > - remove redundant definitions.(madhav)
> >
> > v5:
> > - Add mask for overlap pixels.
> > - Code Style changes.(Madhav)
> > v6:
> > - Code style changes. (Madhav)
> >
> > Suggested-by: Madhav Chauhan <madhav.chauhan@intel.com>
> > Cc: Madhav Chauhan <madhav.chauhan@intel.com>
> > cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: James Ausmus <james.ausmus@intel.com>
> > Cc: Gaurav Singh <gaurav.k.singh@intel.com>
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Pushed to dinq.
This does not have changes mentioned in v3, not the latest patch.
Latest patch is this one:
https://patchwork.freedesktop.org/patch/258331/
>
> BR,
> Jani.
>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 33 +++++++++++++++++++++++++++++++++
> > 1 file changed, 33 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 639667d0fb00..b9aaa71dabe2 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -10033,6 +10033,39 @@ enum skl_power_gate {
> > _ICL_DSI_IO_MODECTL_1)
> > #define COMBO_PHY_MODE_DSI (1 << 0)
> >
> > +/* Display Stream Splitter Control */
> > +#define DSS_CTL1 _MMIO(0x67400)
> > +#define SPLITTER_ENABLE (1 << 31)
> > +#define JOINER_ENABLE (1 << 30)
> > +#define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
> > +#define DUAL_LINK_MODE_FRONTBACK (0 << 24)
> > +#define OVERLAP_PIXELS_MASK (0xf << 16)
> > +#define OVERLAP_PIXELS(pixels) ((pixels) << 16)
> > +#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
> > +#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
> > +#define MAX_DL_BUFFER_TARGET_DEPTH 0x5A0
> > +
> > +#define DSS_CTL2 _MMIO(0x67404)
> > +#define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
> > +#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
> > +#define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
> > +#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
> > +
> > +#define _PIPE_DSS_CTL1_PB 0x78200
> > +#define _PIPE_DSS_CTL1_PC 0x78400
This should have been _ICL_PIPE_DSS_CTL1_PB/PC as per the latest patch
Manasi
> > +#define PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> > + _PIPE_DSS_CTL1_PB, \
> > + _PIPE_DSS_CTL1_PC)
> > +#define BIG_JOINER_ENABLE (1 << 29)
> > +#define MASTER_BIG_JOINER_ENABLE (1 << 28)
> > +#define VGA_CENTERING_ENABLE (1 << 27)
> > +
> > +#define _PIPE_DSS_CTL2_PB 0x78204
> > +#define _PIPE_DSS_CTL2_PC 0x78404
> > +#define PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> > + _PIPE_DSS_CTL2_PB, \
> > + _PIPE_DSS_CTL2_PC)
> > +
> > #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
> > #define STAP_SELECT (1 << 0)
>
> --
> Jani Nikula, Intel Open Source Graphics Center
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^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v8 30/38] drm/i915/icl: Configure DSI Dual link mode
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (28 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 29/38] drm/i915/icl: Add DSS_CTL Registers Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-11-01 14:11 ` Madhav Chauhan
2018-10-30 11:56 ` [PATCH v8 31/38] drm/i915/icl: Define Panel power ctrl register Jani Nikula
` (12 subsequent siblings)
42 siblings, 1 reply; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch configures DSI video mode dual link by
programming DSS_CTL registers.
v2: Use new bitfield definitions from Anusha's patch
Correct register to be programmed and use max
depth buffer value (James)
v3 by Jani:
- checkpatch fixes
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/icl_dsi.c | 42 +++++++++++++++++++++++++++++++++++++++++-
1 file changed, 41 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index b2897281d42c..f2609e36dd1d 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -257,6 +257,45 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
}
}
+static void configure_dual_link_mode(struct intel_encoder *encoder,
+ const struct intel_crtc_state *pipe_config)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ u32 dss_ctl1;
+
+ dss_ctl1 = I915_READ(DSS_CTL1);
+ dss_ctl1 |= SPLITTER_ENABLE;
+ dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
+ dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
+
+ if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
+ const struct drm_display_mode *adjusted_mode =
+ &pipe_config->base.adjusted_mode;
+ u32 dss_ctl2;
+ u16 hactive = adjusted_mode->crtc_hdisplay;
+ u16 dl_buffer_depth;
+
+ dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
+ dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
+
+ if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
+ DRM_ERROR("DL buffer depth exceed max value\n");
+
+ dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
+ dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
+ dss_ctl2 = I915_READ(DSS_CTL2);
+ dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK;
+ dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
+ I915_WRITE(DSS_CTL2, dss_ctl2);
+ } else {
+ /* Interleave */
+ dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
+ }
+
+ I915_WRITE(DSS_CTL1, dss_ctl1);
+}
+
static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -591,7 +630,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
}
- //TODO: configure DSS_CTL1
+ /* configure stream splitting */
+ configure_dual_link_mode(encoder, pipe_config);
}
for_each_dsi_port(port, intel_dsi->ports) {
--
2.11.0
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^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [PATCH v8 30/38] drm/i915/icl: Configure DSI Dual link mode
2018-10-30 11:56 ` [PATCH v8 30/38] drm/i915/icl: Configure DSI Dual link mode Jani Nikula
@ 2018-11-01 14:11 ` Madhav Chauhan
0 siblings, 0 replies; 75+ messages in thread
From: Madhav Chauhan @ 2018-11-01 14:11 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 10/30/2018 5:26 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> This patch configures DSI video mode dual link by
> programming DSS_CTL registers.
>
> v2: Use new bitfield definitions from Anusha's patch
> Correct register to be programmed and use max
> depth buffer value (James)
>
> v3 by Jani:
> - checkpatch fixes
Ok.
Regards,
Madhav
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 42 +++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 41 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index b2897281d42c..f2609e36dd1d 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -257,6 +257,45 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
> }
> }
>
> +static void configure_dual_link_mode(struct intel_encoder *encoder,
> + const struct intel_crtc_state *pipe_config)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + u32 dss_ctl1;
> +
> + dss_ctl1 = I915_READ(DSS_CTL1);
> + dss_ctl1 |= SPLITTER_ENABLE;
> + dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
> + dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
> +
> + if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
> + const struct drm_display_mode *adjusted_mode =
> + &pipe_config->base.adjusted_mode;
> + u32 dss_ctl2;
> + u16 hactive = adjusted_mode->crtc_hdisplay;
> + u16 dl_buffer_depth;
> +
> + dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
> + dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
> +
> + if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
> + DRM_ERROR("DL buffer depth exceed max value\n");
> +
> + dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
> + dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
> + dss_ctl2 = I915_READ(DSS_CTL2);
> + dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK;
> + dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
> + I915_WRITE(DSS_CTL2, dss_ctl2);
> + } else {
> + /* Interleave */
> + dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
> + }
> +
> + I915_WRITE(DSS_CTL1, dss_ctl1);
> +}
> +
> static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> @@ -591,7 +630,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
> I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
> }
>
> - //TODO: configure DSS_CTL1
> + /* configure stream splitting */
> + configure_dual_link_mode(encoder, pipe_config);
> }
>
> for_each_dsi_port(port, intel_dsi->ports) {
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^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v8 31/38] drm/i915/icl: Define Panel power ctrl register
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (29 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 30/38] drm/i915/icl: Configure DSI Dual link mode Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-30 11:56 ` [PATCH v8 32/38] drm/i915/icl: Define missing bitfield for shortplug reg Jani Nikula
` (11 subsequent siblings)
42 siblings, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
There are two panel power sequencers. Each register
has two addressable instances. This patch defines
both the instances of Panel power control register
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b9aaa71dabe2..5f51a258d87b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4592,6 +4592,17 @@ enum {
#define _PP_STATUS 0x61200
#define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
#define PP_ON (1 << 31)
+
+#define _PP_CONTROL_1 0xc7204
+#define _PP_CONTROL_2 0xc7304
+#define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
+ _PP_CONTROL_2)
+#define POWER_CYCLE_DELAY_MASK (0x1f << 4)
+#define POWER_CYCLE_DELAY_SHIFT 4
+#define VDD_OVERRIDE_FORCE (1 << 3)
+#define BACKLIGHT_ENABLE (1 << 2)
+#define PWR_DOWN_ON_RESET (1 << 1)
+#define PWR_STATE_TARGET (1 << 0)
/*
* Indicates that all dependencies of the panel are on:
*
--
2.11.0
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^ permalink raw reply related [flat|nested] 75+ messages in thread* [PATCH v8 32/38] drm/i915/icl: Define missing bitfield for shortplug reg
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (30 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 31/38] drm/i915/icl: Define Panel power ctrl register Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-30 11:56 ` [PATCH v8 33/38] drm/i915/icl: Define display GPIO pins for DSI Jani Nikula
` (10 subsequent siblings)
42 siblings, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
This patch define missing bitfield for shortplug ctl ddi
register which will be used for ICL DSI GPIO programming.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5f51a258d87b..8380fab06b97 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7693,6 +7693,7 @@ enum {
#define ICP_DDIB_HPD_LONG_DETECT (2 << 4)
#define ICP_DDIB_HPD_SHORT_LONG_DETECT (3 << 4)
#define ICP_DDIA_HPD_ENABLE (1 << 3)
+#define ICP_DDIA_HPD_OP_DRIVE_1 (1 << 2)
#define ICP_DDIA_HPD_STATUS_MASK (3 << 0)
#define ICP_DDIA_HPD_NO_DETECT (0 << 0)
#define ICP_DDIA_HPD_SHORT_DETECT (1 << 0)
--
2.11.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 75+ messages in thread* [PATCH v8 33/38] drm/i915/icl: Define display GPIO pins for DSI
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (31 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 32/38] drm/i915/icl: Define missing bitfield for shortplug reg Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-30 11:56 ` [PATCH v8 34/38] drm/i915/icl: Add changes to program DSI panel GPIOs Jani Nikula
` (9 subsequent siblings)
42 siblings, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
Display Pins are the only GPIOs that need to be used by
driver for DSI panels. So driver should now have its own
implementation to toggle these pins based on GPIO info
received from VBT sequences.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dsi_vbt.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 80bd56e96143..8177305b9c87 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -103,6 +103,18 @@ static struct gpio_map vlv_gpio_table[] = {
#define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4)
#define CHV_GPIO_CFGLOCK (1 << 31)
+/* ICL DSI Display GPIO Pins */
+#define ICL_GPIO_DDSP_HPD_A 0
+#define ICL_GPIO_L_VDDEN_1 1
+#define ICL_GPIO_L_BKLTEN_1 2
+#define ICL_GPIO_DDPA_CTRLCLK_1 3
+#define ICL_GPIO_DDPA_CTRLDATA_1 4
+#define ICL_GPIO_DDSP_HPD_B 5
+#define ICL_GPIO_L_VDDEN_2 6
+#define ICL_GPIO_L_BKLTEN_2 7
+#define ICL_GPIO_DDPA_CTRLCLK_2 8
+#define ICL_GPIO_DDPA_CTRLDATA_2 9
+
static inline enum port intel_dsi_seq_port_to_port(u8 port)
{
return port ? PORT_C : PORT_A;
--
2.11.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 75+ messages in thread* [PATCH v8 34/38] drm/i915/icl: Add changes to program DSI panel GPIOs
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (32 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 33/38] drm/i915/icl: Define display GPIO pins for DSI Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-30 14:01 ` Ville Syrjälä
2018-10-30 11:56 ` [PATCH v8 35/38] HACK: drm/i915/icl: Configure backlight functions for DSI Jani Nikula
` (8 subsequent siblings)
42 siblings, 1 reply; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
For ICELAKE DSI, Display Pins are the only GPIOs
that need to be programmed. So DSI driver should have
its own implementation to toggle these pins based on
GPIO info coming from VBT sequences instead of using
platform specific GPIO driver.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dsi_vbt.c | 46 +++++++++++++++++++++++++++++++++++-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 8177305b9c87..04423248bbd7 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -334,6 +334,48 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
gpiod_set_value(gpio_desc, value);
}
+static void icl_exec_gpio(struct drm_i915_private *dev_priv,
+ u8 gpio_source, u8 gpio_index, bool value)
+{
+ u32 val;
+
+ switch (gpio_index) {
+ case ICL_GPIO_DDSP_HPD_A:
+ val = I915_READ(SHOTPLUG_CTL_DDI);
+ val &= ~ICP_DDIA_HPD_ENABLE;
+ I915_WRITE(SHOTPLUG_CTL_DDI, val);
+ val = I915_READ(SHOTPLUG_CTL_DDI);
+
+ if (value)
+ val |= ICP_DDIA_HPD_OP_DRIVE_1;
+ else
+ val &= ~ICP_DDIA_HPD_OP_DRIVE_1;
+
+ I915_WRITE(SHOTPLUG_CTL_DDI, val);
+ break;
+ case ICL_GPIO_L_VDDEN_1:
+ val = I915_READ(ICP_PP_CONTROL(1));
+ if (value)
+ val |= PWR_STATE_TARGET;
+ else
+ val &= ~PWR_STATE_TARGET;
+ I915_WRITE(ICP_PP_CONTROL(1), val);
+ break;
+ case ICL_GPIO_L_BKLTEN_1:
+ val = I915_READ(ICP_PP_CONTROL(1));
+ if (value)
+ val |= BACKLIGHT_ENABLE;
+ else
+ val &= ~BACKLIGHT_ENABLE;
+ I915_WRITE(ICP_PP_CONTROL(1), val);
+ break;
+ default:
+ /* TODO: Add support for remaining GPIOs */
+ DRM_ERROR("Invalid GPIO no from VBT\n");
+ break;
+ }
+}
+
static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
{
struct drm_device *dev = intel_dsi->base.base.dev;
@@ -357,7 +399,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
/* pull up/down */
value = *data++ & 1;
- if (IS_VALLEYVIEW(dev_priv))
+ if (IS_ICELAKE(dev_priv))
+ icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
+ else if (IS_VALLEYVIEW(dev_priv))
vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
else if (IS_CHERRYVIEW(dev_priv))
chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
--
2.11.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [PATCH v8 34/38] drm/i915/icl: Add changes to program DSI panel GPIOs
2018-10-30 11:56 ` [PATCH v8 34/38] drm/i915/icl: Add changes to program DSI panel GPIOs Jani Nikula
@ 2018-10-30 14:01 ` Ville Syrjälä
2018-10-30 14:08 ` Jani Nikula
2018-11-01 14:56 ` Madhav Chauhan
0 siblings, 2 replies; 75+ messages in thread
From: Ville Syrjälä @ 2018-10-30 14:01 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Oct 30, 2018 at 01:56:40PM +0200, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> For ICELAKE DSI, Display Pins are the only GPIOs
> that need to be programmed. So DSI driver should have
> its own implementation to toggle these pins based on
> GPIO info coming from VBT sequences instead of using
> platform specific GPIO driver.
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi_vbt.c | 46 +++++++++++++++++++++++++++++++++++-
> 1 file changed, 45 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> index 8177305b9c87..04423248bbd7 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> @@ -334,6 +334,48 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
> gpiod_set_value(gpio_desc, value);
> }
>
> +static void icl_exec_gpio(struct drm_i915_private *dev_priv,
> + u8 gpio_source, u8 gpio_index, bool value)
> +{
> + u32 val;
> +
> + switch (gpio_index) {
> + case ICL_GPIO_DDSP_HPD_A:
> + val = I915_READ(SHOTPLUG_CTL_DDI);
> + val &= ~ICP_DDIA_HPD_ENABLE;
> + I915_WRITE(SHOTPLUG_CTL_DDI, val);
> + val = I915_READ(SHOTPLUG_CTL_DDI);
> + if (value)
> + val |= ICP_DDIA_HPD_OP_DRIVE_1;
> + else
> + val &= ~ICP_DDIA_HPD_OP_DRIVE_1;
> +
> + I915_WRITE(SHOTPLUG_CTL_DDI, val);
How badly is this thing going to race with the hotplug irq handler?
> + break;
> + case ICL_GPIO_L_VDDEN_1:
> + val = I915_READ(ICP_PP_CONTROL(1));
> + if (value)
> + val |= PWR_STATE_TARGET;
> + else
> + val &= ~PWR_STATE_TARGET;
> + I915_WRITE(ICP_PP_CONTROL(1), val);
> + break;
> + case ICL_GPIO_L_BKLTEN_1:
> + val = I915_READ(ICP_PP_CONTROL(1));
> + if (value)
> + val |= BACKLIGHT_ENABLE;
> + else
> + val &= ~BACKLIGHT_ENABLE;
> + I915_WRITE(ICP_PP_CONTROL(1), val);
:( What a horror show. So basically we're trying to pretend the power
sequencer state machine doesn't even exist. Is there some bit somewhere
we can actually use to disable the state machine? If not I think this
thing needs much more care.
> + break;
> + default:
> + /* TODO: Add support for remaining GPIOs */
> + DRM_ERROR("Invalid GPIO no from VBT\n");
> + break;
> + }
> +}
> +
> static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> {
> struct drm_device *dev = intel_dsi->base.base.dev;
> @@ -357,7 +399,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
> /* pull up/down */
> value = *data++ & 1;
>
> - if (IS_VALLEYVIEW(dev_priv))
> + if (IS_ICELAKE(dev_priv))
> + icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
> + else if (IS_VALLEYVIEW(dev_priv))
> vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
> else if (IS_CHERRYVIEW(dev_priv))
> chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
> --
> 2.11.0
--
Ville Syrjälä
Intel
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [PATCH v8 34/38] drm/i915/icl: Add changes to program DSI panel GPIOs
2018-10-30 14:01 ` Ville Syrjälä
@ 2018-10-30 14:08 ` Jani Nikula
2018-11-01 14:56 ` Madhav Chauhan
1 sibling, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 14:08 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, 30 Oct 2018, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, Oct 30, 2018 at 01:56:40PM +0200, Jani Nikula wrote:
>> From: Madhav Chauhan <madhav.chauhan@intel.com>
>>
>> For ICELAKE DSI, Display Pins are the only GPIOs
>> that need to be programmed. So DSI driver should have
>> its own implementation to toggle these pins based on
>> GPIO info coming from VBT sequences instead of using
>> platform specific GPIO driver.
>>
>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_dsi_vbt.c | 46 +++++++++++++++++++++++++++++++++++-
>> 1 file changed, 45 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> index 8177305b9c87..04423248bbd7 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> @@ -334,6 +334,48 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
>> gpiod_set_value(gpio_desc, value);
>> }
>>
>> +static void icl_exec_gpio(struct drm_i915_private *dev_priv,
>> + u8 gpio_source, u8 gpio_index, bool value)
>> +{
>> + u32 val;
>> +
>> + switch (gpio_index) {
>> + case ICL_GPIO_DDSP_HPD_A:
>> + val = I915_READ(SHOTPLUG_CTL_DDI);
>> + val &= ~ICP_DDIA_HPD_ENABLE;
>> + I915_WRITE(SHOTPLUG_CTL_DDI, val);
>> + val = I915_READ(SHOTPLUG_CTL_DDI);
>> + if (value)
>> + val |= ICP_DDIA_HPD_OP_DRIVE_1;
>> + else
>> + val &= ~ICP_DDIA_HPD_OP_DRIVE_1;
>> +
>> + I915_WRITE(SHOTPLUG_CTL_DDI, val);
>
> How badly is this thing going to race with the hotplug irq handler?
>
>> + break;
>> + case ICL_GPIO_L_VDDEN_1:
>> + val = I915_READ(ICP_PP_CONTROL(1));
>> + if (value)
>> + val |= PWR_STATE_TARGET;
>> + else
>> + val &= ~PWR_STATE_TARGET;
>> + I915_WRITE(ICP_PP_CONTROL(1), val);
>> + break;
>> + case ICL_GPIO_L_BKLTEN_1:
>> + val = I915_READ(ICP_PP_CONTROL(1));
>> + if (value)
>> + val |= BACKLIGHT_ENABLE;
>> + else
>> + val &= ~BACKLIGHT_ENABLE;
>> + I915_WRITE(ICP_PP_CONTROL(1), val);
>
> :( What a horror show. So basically we're trying to pretend the power
> sequencer state machine doesn't even exist. Is there some bit somewhere
> we can actually use to disable the state machine? If not I think this
> thing needs much more care.
Frankly I didn't look at the patches towards the end of the series all
that much. Just included them all for completeness.
Agreed, looks pretty bad. :(
BR,
Jani.
>
>> + break;
>> + default:
>> + /* TODO: Add support for remaining GPIOs */
>> + DRM_ERROR("Invalid GPIO no from VBT\n");
>> + break;
>> + }
>> +}
>> +
>> static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>> {
>> struct drm_device *dev = intel_dsi->base.base.dev;
>> @@ -357,7 +399,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>> /* pull up/down */
>> value = *data++ & 1;
>>
>> - if (IS_VALLEYVIEW(dev_priv))
>> + if (IS_ICELAKE(dev_priv))
>> + icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
>> + else if (IS_VALLEYVIEW(dev_priv))
>> vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
>> else if (IS_CHERRYVIEW(dev_priv))
>> chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
>> --
>> 2.11.0
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [PATCH v8 34/38] drm/i915/icl: Add changes to program DSI panel GPIOs
2018-10-30 14:01 ` Ville Syrjälä
2018-10-30 14:08 ` Jani Nikula
@ 2018-11-01 14:56 ` Madhav Chauhan
1 sibling, 0 replies; 75+ messages in thread
From: Madhav Chauhan @ 2018-11-01 14:56 UTC (permalink / raw)
To: Ville Syrjälä, Jani Nikula; +Cc: intel-gfx
On 10/30/2018 7:31 PM, Ville Syrjälä wrote:
> On Tue, Oct 30, 2018 at 01:56:40PM +0200, Jani Nikula wrote:
>> From: Madhav Chauhan <madhav.chauhan@intel.com>
>>
>> For ICELAKE DSI, Display Pins are the only GPIOs
>> that need to be programmed. So DSI driver should have
>> its own implementation to toggle these pins based on
>> GPIO info coming from VBT sequences instead of using
>> platform specific GPIO driver.
>>
>> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_dsi_vbt.c | 46 +++++++++++++++++++++++++++++++++++-
>> 1 file changed, 45 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> index 8177305b9c87..04423248bbd7 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
>> @@ -334,6 +334,48 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
>> gpiod_set_value(gpio_desc, value);
>> }
>>
>> +static void icl_exec_gpio(struct drm_i915_private *dev_priv,
>> + u8 gpio_source, u8 gpio_index, bool value)
>> +{
>> + u32 val;
>> +
>> + switch (gpio_index) {
>> + case ICL_GPIO_DDSP_HPD_A:
>> + val = I915_READ(SHOTPLUG_CTL_DDI);
>> + val &= ~ICP_DDIA_HPD_ENABLE;
>> + I915_WRITE(SHOTPLUG_CTL_DDI, val);
>> + val = I915_READ(SHOTPLUG_CTL_DDI);
>> + if (value)
>> + val |= ICP_DDIA_HPD_OP_DRIVE_1;
>> + else
>> + val &= ~ICP_DDIA_HPD_OP_DRIVE_1;
>> +
>> + I915_WRITE(SHOTPLUG_CTL_DDI, val);
> How badly is this thing going to race with the hotplug irq handler?
Agree, icp_irq_handler will create race condition here (was aware).
Actually, behavior of GPIO pin like what to do for a particular
GPIO was not available in BSPEC during power-on.
So just added this patch(tmp method) to complete power ON.
My bad, should have added that info in patch description.
>
>> + break;
>> + case ICL_GPIO_L_VDDEN_1:
>> + val = I915_READ(ICP_PP_CONTROL(1));
>> + if (value)
>> + val |= PWR_STATE_TARGET;
>> + else
>> + val &= ~PWR_STATE_TARGET;
>> + I915_WRITE(ICP_PP_CONTROL(1), val);
>> + break;
>> + case ICL_GPIO_L_BKLTEN_1:
>> + val = I915_READ(ICP_PP_CONTROL(1));
>> + if (value)
>> + val |= BACKLIGHT_ENABLE;
>> + else
>> + val &= ~BACKLIGHT_ENABLE;
>> + I915_WRITE(ICP_PP_CONTROL(1), val);
> :( What a horror show. So basically we're trying to pretend the power
> sequencer state machine doesn't even exist. Is there some bit somewhere
> we can actually use to disable the state machine? If not I think this
> thing needs much more care.
Yes :(, We need to definitely think about if we can achieve this using
existing panel backlight
framework functions.
Need discussion to have more clarity on BITS and behavior with VBT team
and then decide
final approach.
Regards,
Madhav
>
>> + break;
>> + default:
>> + /* TODO: Add support for remaining GPIOs */
>> + DRM_ERROR("Invalid GPIO no from VBT\n");
>> + break;
>> + }
>> +}
>> +
>> static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>> {
>> struct drm_device *dev = intel_dsi->base.base.dev;
>> @@ -357,7 +399,9 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>> /* pull up/down */
>> value = *data++ & 1;
>>
>> - if (IS_VALLEYVIEW(dev_priv))
>> + if (IS_ICELAKE(dev_priv))
>> + icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
>> + else if (IS_VALLEYVIEW(dev_priv))
>> vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
>> else if (IS_CHERRYVIEW(dev_priv))
>> chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
>> --
>> 2.11.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v8 35/38] HACK: drm/i915/icl: Configure backlight functions for DSI
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (33 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 34/38] drm/i915/icl: Add changes to program DSI panel GPIOs Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-30 11:56 ` [PATCH v8 36/38] drm/i915/icl: Don't wait for empty FIFO Jani Nikula
` (7 subsequent siblings)
42 siblings, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
Gen11 DSI doesn't use DCS commands based functionality
for enabling/disabling backlight but uses PWM based
functions similar to eDP.
Note by Jani: This should be decided by VBT, not hard coded. DCS
brightness control is still a thing.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_panel.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index ad88008f8dd0..60ccae68b27a 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1835,7 +1835,8 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
intel_dp_aux_init_backlight_funcs(connector) == 0)
return;
- if (connector->base.connector_type == DRM_MODE_CONNECTOR_DSI &&
+ if (IS_GEN9_LP(dev_priv) &&
+ connector->base.connector_type == DRM_MODE_CONNECTOR_DSI &&
intel_dsi_dcs_init_backlight_funcs(connector) == 0)
return;
--
2.11.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 75+ messages in thread* [PATCH v8 36/38] drm/i915/icl: Don't wait for empty FIFO
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (34 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 35/38] HACK: drm/i915/icl: Configure backlight functions for DSI Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-11-01 11:10 ` Jani Nikula
2018-10-30 11:56 ` [PATCH v8 37/38] drm/i915/icl: Consider DSI for getting transcoder state Jani Nikula
` (6 subsequent siblings)
42 siblings, 1 reply; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
For Gen11 DSI, we don't need to wait for getting
DSI FIFO empty after sending DCS commands.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dsi_vbt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 04423248bbd7..e6686dbdf462 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -123,6 +123,7 @@ static inline enum port intel_dsi_seq_port_to_port(u8 port)
static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
const u8 *data)
{
+ struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
struct mipi_dsi_device *dsi_device;
u8 type, flags, seq_port;
u16 len;
@@ -193,7 +194,8 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
break;
}
- vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
+ if (!IS_ICELAKE(dev_priv))
+ vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
out:
data += len;
--
2.11.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [PATCH v8 36/38] drm/i915/icl: Don't wait for empty FIFO
2018-10-30 11:56 ` [PATCH v8 36/38] drm/i915/icl: Don't wait for empty FIFO Jani Nikula
@ 2018-11-01 11:10 ` Jani Nikula
0 siblings, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-11-01 11:10 UTC (permalink / raw)
To: intel-gfx
On Tue, 30 Oct 2018, Jani Nikula <jani.nikula@intel.com> wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> For Gen11 DSI, we don't need to wait for getting
> DSI FIFO empty after sending DCS commands.
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Pushed to dinq.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/intel_dsi_vbt.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> index 04423248bbd7..e6686dbdf462 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> @@ -123,6 +123,7 @@ static inline enum port intel_dsi_seq_port_to_port(u8 port)
> static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
> const u8 *data)
> {
> + struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
> struct mipi_dsi_device *dsi_device;
> u8 type, flags, seq_port;
> u16 len;
> @@ -193,7 +194,8 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
> break;
> }
>
> - vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
> + if (!IS_ICELAKE(dev_priv))
> + vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
>
> out:
> data += len;
--
Jani Nikula, Intel Open Source Graphics Center
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v8 37/38] drm/i915/icl: Consider DSI for getting transcoder state
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (35 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 36/38] drm/i915/icl: Don't wait for empty FIFO Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-30 14:04 ` Ville Syrjälä
2018-10-30 11:56 ` [PATCH v8 38/38] drm/i915/icl: Get pipe timings for DSI Jani Nikula
` (5 subsequent siblings)
42 siblings, 1 reply; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
For Gen11 DSI, we use similar registers like for eDP
to find if DSI encoder is connected or not to a pipe.
This patch refactors existing hsw_get_transcoder_state()
to handle this.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 29 ++++++++++++++++++++++-------
1 file changed, 22 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1d46f06ede37..1670646240ba 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9366,6 +9366,8 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(dev);
enum intel_display_power_domain power_domain;
u32 tmp;
+ bool is_dsi = false;
+ bool is_edp = false;
/*
* The pipe->transcoder mapping is fixed with the exception of the eDP
@@ -9378,26 +9380,39 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
* consistency and less surprising code; it's in always on power).
*/
tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
- if (tmp & TRANS_DDI_FUNC_ENABLE) {
- enum pipe trans_edp_pipe;
+ if (tmp & TRANS_DDI_FUNC_ENABLE)
+ is_edp = true;
+
+ if (IS_ICELAKE(dev_priv)) {
+ tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_DSI_0));
+ if (tmp & TRANS_DDI_FUNC_ENABLE)
+ is_dsi = true;
+ }
+
+ if (is_edp || is_dsi) {
+ enum pipe trans_pipe;
switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
default:
WARN(1, "unknown pipe linked to edp transcoder\n");
/* fall through */
case TRANS_DDI_EDP_INPUT_A_ONOFF:
case TRANS_DDI_EDP_INPUT_A_ON:
- trans_edp_pipe = PIPE_A;
+ trans_pipe = PIPE_A;
break;
case TRANS_DDI_EDP_INPUT_B_ONOFF:
- trans_edp_pipe = PIPE_B;
+ trans_pipe = PIPE_B;
break;
case TRANS_DDI_EDP_INPUT_C_ONOFF:
- trans_edp_pipe = PIPE_C;
+ trans_pipe = PIPE_C;
break;
}
- if (trans_edp_pipe == crtc->pipe)
- pipe_config->cpu_transcoder = TRANSCODER_EDP;
+ if (trans_pipe == crtc->pipe) {
+ if (is_edp)
+ pipe_config->cpu_transcoder = TRANSCODER_EDP;
+ else if (is_dsi)
+ pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
+ }
}
power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
--
2.11.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 75+ messages in thread* Re: [PATCH v8 37/38] drm/i915/icl: Consider DSI for getting transcoder state
2018-10-30 11:56 ` [PATCH v8 37/38] drm/i915/icl: Consider DSI for getting transcoder state Jani Nikula
@ 2018-10-30 14:04 ` Ville Syrjälä
0 siblings, 0 replies; 75+ messages in thread
From: Ville Syrjälä @ 2018-10-30 14:04 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Oct 30, 2018 at 01:56:43PM +0200, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
>
> For Gen11 DSI, we use similar registers like for eDP
> to find if DSI encoder is connected or not to a pipe.
> This patch refactors existing hsw_get_transcoder_state()
> to handle this.
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 29 ++++++++++++++++++++++-------
> 1 file changed, 22 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 1d46f06ede37..1670646240ba 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9366,6 +9366,8 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
> struct drm_i915_private *dev_priv = to_i915(dev);
> enum intel_display_power_domain power_domain;
> u32 tmp;
> + bool is_dsi = false;
> + bool is_edp = false;
>
> /*
> * The pipe->transcoder mapping is fixed with the exception of the eDP
> @@ -9378,26 +9380,39 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
> * consistency and less surprising code; it's in always on power).
> */
> tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
> - if (tmp & TRANS_DDI_FUNC_ENABLE) {
> - enum pipe trans_edp_pipe;
> + if (tmp & TRANS_DDI_FUNC_ENABLE)
> + is_edp = true;
> +
> + if (IS_ICELAKE(dev_priv)) {
> + tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_DSI_0));
> + if (tmp & TRANS_DDI_FUNC_ENABLE)
> + is_dsi = true;
> + }
> +
WARN_ON(is_edp && is_dsi) ?
> + if (is_edp || is_dsi) {
> + enum pipe trans_pipe;
> switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
> default:
> WARN(1, "unknown pipe linked to edp transcoder\n");
> /* fall through */
> case TRANS_DDI_EDP_INPUT_A_ONOFF:
> case TRANS_DDI_EDP_INPUT_A_ON:
> - trans_edp_pipe = PIPE_A;
> + trans_pipe = PIPE_A;
> break;
> case TRANS_DDI_EDP_INPUT_B_ONOFF:
> - trans_edp_pipe = PIPE_B;
> + trans_pipe = PIPE_B;
> break;
> case TRANS_DDI_EDP_INPUT_C_ONOFF:
> - trans_edp_pipe = PIPE_C;
> + trans_pipe = PIPE_C;
> break;
> }
>
> - if (trans_edp_pipe == crtc->pipe)
> - pipe_config->cpu_transcoder = TRANSCODER_EDP;
> + if (trans_pipe == crtc->pipe) {
> + if (is_edp)
> + pipe_config->cpu_transcoder = TRANSCODER_EDP;
> + else if (is_dsi)
> + pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
> + }
> }
>
> power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
> --
> 2.11.0
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v8 38/38] drm/i915/icl: Get pipe timings for DSI
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (36 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 37/38] drm/i915/icl: Consider DSI for getting transcoder state Jani Nikula
@ 2018-10-30 11:56 ` Jani Nikula
2018-10-30 12:17 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: dsi enabling (rev3) Patchwork
` (4 subsequent siblings)
42 siblings, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 11:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
From: Madhav Chauhan <madhav.chauhan@intel.com>
Transcoder timings for Gen11 DSI encoder
is available at pipe level unlike in older platform
where port specific registers need to be accessed.
v2 by Jani:
- get timings for (!dsi || icl) instead of (dsi && icl).
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1670646240ba..126aa79b8746 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9547,7 +9547,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
if (!active)
goto out;
- if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
+ if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
+ IS_ICELAKE(dev_priv)) {
haswell_get_ddi_port_state(crtc, pipe_config);
intel_get_pipe_timings(crtc, pipe_config);
}
--
2.11.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 75+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: dsi enabling (rev3)
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (37 preceding siblings ...)
2018-10-30 11:56 ` [PATCH v8 38/38] drm/i915/icl: Get pipe timings for DSI Jani Nikula
@ 2018-10-30 12:17 ` Patchwork
2018-10-30 12:26 ` ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
42 siblings, 0 replies; 75+ messages in thread
From: Patchwork @ 2018-10-30 12:17 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/icl: dsi enabling (rev3)
URL : https://patchwork.freedesktop.org/series/51011/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b251037fd588 drm/i915/icl: Move dsi host init code to common file
a43a103a8a44 drm/i915/dsi: move connector mode functions to common file
d122a34905d5 drm/i915/icl: Set max return packet size for DSI panel
3c73fd0e759d drm/i915/icl: Power on DSI panel
23539e8ed054 drm/i915/icl: Wait for header/payload credits release
8dd7cb7cd9f4 drm/i915/icl: Turn ON panel backlight
22cfa12e43d3 drm/i915/icl: Turn OFF panel backlight
-:22: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#22: FILE: drivers/gpu/drm/i915/icl_dsi.c:780:
+static void __attribute__((unused)) gen11_dsi_disable(
total: 0 errors, 0 warnings, 1 checks, 15 lines checked
e3b83d15858b drm/i915/icl: Disable DSI transcoders
496f9c431181 drm/i915/icl: Power down DSI panel
f92b349c0578 drm/i915/icl: Put DSI link in ULPS
32ebc3e760a5 drm/i915/icl: Disable DDI function
389528d1498d drm/i915/icl: Disable portsync mode
3dd8ac3bdc51 drm/i915/icl: Disable DSI ports
ffd539172104 drm/i915/icl: Disable DSI IO power
8f96cf43f453 drm/i915/icl: Define DSI timeout registers
71f90c5344a2 drm/i915/icl: Program HS_TX_TIMEOUT/LP_RX_TIMEOUT/TA_TIMEOUT registers
f6c4ae07a154 drm/i915/icl: Find DSI presence for ICL
9447a71cdb6b drm/i915/icl: Allocate DSI encoder/connector
-:110: CHECK:CAMELCASE: Avoid CamelCase: <SubPixelHorizontalRGB>
#110: FILE: drivers/gpu/drm/i915/icl_dsi.c:1027:
+ connector->display_info.subpixel_order = SubPixelHorizontalRGB;
total: 0 errors, 0 warnings, 1 checks, 118 lines checked
95614818e50b drm/i915/icl: Allocate hosts for DSI ports
6f27802c08aa drm/i915/icl: Add DSI packet payload/header registers
b28670b244e0 drm/i915/icl: Fetch DSI pkt to be transferred
e109cc511eb7 drm/i915/icl: Load DSI packet payload to queue
93032ef7347e drm/i915/icl: Add get config functionality for DSI
c90986451421 drm/i915/icl: Get HW state for DSI encoder
b70c25327649 drm/i915/icl: Add DSI connector functions
35cf407b3008 drm/i915/icl: Add DSI connector helper functions
2b52d7d72d09 drm/i915/icl: Add DSI encoder remaining functions
d4823e7ae09f drm/i915/icl: Fill DSI ports info
ac7d3b7155c4 drm/i915/icl: Add DSS_CTL Registers
89a7e3eca6a0 drm/i915/icl: Configure DSI Dual link mode
1c9fdd4762a5 drm/i915/icl: Define Panel power ctrl register
5a3ef42cc519 drm/i915/icl: Define missing bitfield for shortplug reg
67a18f5eec36 drm/i915/icl: Define display GPIO pins for DSI
6670c2df2ab4 drm/i915/icl: Add changes to program DSI panel GPIOs
bbfcade0770f HACK: drm/i915/icl: Configure backlight functions for DSI
ac08a6bf18b1 drm/i915/icl: Don't wait for empty FIFO
3e15da186132 drm/i915/icl: Consider DSI for getting transcoder state
5c1e98162a65 drm/i915/icl: Get pipe timings for DSI
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 75+ messages in thread* ✗ Fi.CI.SPARSE: warning for drm/i915/icl: dsi enabling (rev3)
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (38 preceding siblings ...)
2018-10-30 12:17 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: dsi enabling (rev3) Patchwork
@ 2018-10-30 12:26 ` Patchwork
2018-10-30 12:51 ` ✗ Fi.CI.BAT: failure " Patchwork
` (2 subsequent siblings)
42 siblings, 0 replies; 75+ messages in thread
From: Patchwork @ 2018-10-30 12:26 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/icl: dsi enabling (rev3)
URL : https://patchwork.freedesktop.org/series/51011/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/icl: Move dsi host init code to common file
Okay!
Commit: drm/i915/dsi: move connector mode functions to common file
Okay!
Commit: drm/i915/icl: Set max return packet size for DSI panel
Okay!
Commit: drm/i915/icl: Power on DSI panel
Okay!
Commit: drm/i915/icl: Wait for header/payload credits release
Okay!
Commit: drm/i915/icl: Turn ON panel backlight
Okay!
Commit: drm/i915/icl: Turn OFF panel backlight
Okay!
Commit: drm/i915/icl: Disable DSI transcoders
Okay!
Commit: drm/i915/icl: Power down DSI panel
Okay!
Commit: drm/i915/icl: Put DSI link in ULPS
Okay!
Commit: drm/i915/icl: Disable DDI function
Okay!
Commit: drm/i915/icl: Disable portsync mode
Okay!
Commit: drm/i915/icl: Disable DSI ports
Okay!
Commit: drm/i915/icl: Disable DSI IO power
Okay!
Commit: drm/i915/icl: Define DSI timeout registers
Okay!
Commit: drm/i915/icl: Program HS_TX_TIMEOUT/LP_RX_TIMEOUT/TA_TIMEOUT registers
Okay!
Commit: drm/i915/icl: Find DSI presence for ICL
Okay!
Commit: drm/i915/icl: Allocate DSI encoder/connector
Okay!
Commit: drm/i915/icl: Allocate hosts for DSI ports
Okay!
Commit: drm/i915/icl: Add DSI packet payload/header registers
Okay!
Commit: drm/i915/icl: Fetch DSI pkt to be transferred
Okay!
Commit: drm/i915/icl: Load DSI packet payload to queue
+drivers/gpu/drm/i915/icl_dsi.c:128:33: warning: expression using sizeof(void)
Commit: drm/i915/icl: Add get config functionality for DSI
Okay!
Commit: drm/i915/icl: Get HW state for DSI encoder
Okay!
Commit: drm/i915/icl: Add DSI connector functions
Okay!
Commit: drm/i915/icl: Add DSI connector helper functions
Okay!
Commit: drm/i915/icl: Add DSI encoder remaining functions
Okay!
Commit: drm/i915/icl: Fill DSI ports info
Okay!
Commit: drm/i915/icl: Add DSS_CTL Registers
Okay!
Commit: drm/i915/icl: Configure DSI Dual link mode
Okay!
Commit: drm/i915/icl: Define Panel power ctrl register
Okay!
Commit: drm/i915/icl: Define missing bitfield for shortplug reg
Okay!
Commit: drm/i915/icl: Define display GPIO pins for DSI
Okay!
Commit: drm/i915/icl: Add changes to program DSI panel GPIOs
Okay!
Commit: HACK: drm/i915/icl: Configure backlight functions for DSI
Okay!
Commit: drm/i915/icl: Don't wait for empty FIFO
Okay!
Commit: drm/i915/icl: Consider DSI for getting transcoder state
Okay!
Commit: drm/i915/icl: Get pipe timings for DSI
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 75+ messages in thread* ✗ Fi.CI.BAT: failure for drm/i915/icl: dsi enabling (rev3)
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (39 preceding siblings ...)
2018-10-30 12:26 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2018-10-30 12:51 ` Patchwork
2018-10-30 13:07 ` [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
2018-10-30 16:07 ` ✗ Fi.CI.BAT: failure for drm/i915/icl: dsi enabling (rev3) Patchwork
42 siblings, 0 replies; 75+ messages in thread
From: Patchwork @ 2018-10-30 12:51 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/icl: dsi enabling (rev3)
URL : https://patchwork.freedesktop.org/series/51011/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5054 -> Patchwork_10650 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10650 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10650, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/51011/revisions/3/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10650:
=== IGT changes ===
==== Possible regressions ====
igt@kms_flip@basic-flip-vs-wf_vblank:
fi-icl-u: PASS -> DMESG-WARN +17
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-icl-u2: PASS -> DMESG-WARN +17
== Known issues ==
Here are the changes found in Patchwork_10650 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@debugfs_test@read_all_entries:
fi-icl-u2: PASS -> DMESG-WARN (fdo#108070)
igt@gem_exec_suspend@basic-s3:
fi-icl-u2: PASS -> DMESG-WARN (fdo#106612)
igt@gem_mmap_gtt@basic-small-copy:
fi-glk-dsi: PASS -> INCOMPLETE (fdo#103359, k.org#198133)
igt@kms_flip@basic-flip-vs-dpms:
fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998)
igt@kms_frontbuffer_tracking@basic:
fi-hsw-peppy: PASS -> DMESG-WARN (fdo#102614)
==== Possible fixes ====
igt@gem_ctx_create@basic-files:
fi-icl-u2: DMESG-WARN (fdo#107724) -> PASS
igt@kms_frontbuffer_tracking@basic:
fi-byt-clapper: FAIL (fdo#103167) -> PASS
==== Warnings ====
igt@drv_selftest@live_contexts:
fi-icl-u: DMESG-FAIL (fdo#108569) -> INCOMPLETE (fdo#108535)
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
fdo#106612 https://bugs.freedesktop.org/show_bug.cgi?id=106612
fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724
fdo#108070 https://bugs.freedesktop.org/show_bug.cgi?id=108070
fdo#108535 https://bugs.freedesktop.org/show_bug.cgi?id=108535
fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (46 -> 44) ==
Additional (2): fi-skl-iommu fi-pnv-d510
Missing (4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_5054 -> Patchwork_10650
CI_DRM_5054: dfa9e5c2b4b958e77c1109477b94c5c8615e25cc @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4699: 1270ec553741ac20c45178d2b26f9a9562ea565f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10650: 5c1e98162a65f719a83eb7c087727a94b3b5ab6e @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5c1e98162a65 drm/i915/icl: Get pipe timings for DSI
3e15da186132 drm/i915/icl: Consider DSI for getting transcoder state
ac08a6bf18b1 drm/i915/icl: Don't wait for empty FIFO
bbfcade0770f HACK: drm/i915/icl: Configure backlight functions for DSI
6670c2df2ab4 drm/i915/icl: Add changes to program DSI panel GPIOs
67a18f5eec36 drm/i915/icl: Define display GPIO pins for DSI
5a3ef42cc519 drm/i915/icl: Define missing bitfield for shortplug reg
1c9fdd4762a5 drm/i915/icl: Define Panel power ctrl register
89a7e3eca6a0 drm/i915/icl: Configure DSI Dual link mode
ac7d3b7155c4 drm/i915/icl: Add DSS_CTL Registers
d4823e7ae09f drm/i915/icl: Fill DSI ports info
2b52d7d72d09 drm/i915/icl: Add DSI encoder remaining functions
35cf407b3008 drm/i915/icl: Add DSI connector helper functions
b70c25327649 drm/i915/icl: Add DSI connector functions
c90986451421 drm/i915/icl: Get HW state for DSI encoder
93032ef7347e drm/i915/icl: Add get config functionality for DSI
e109cc511eb7 drm/i915/icl: Load DSI packet payload to queue
b28670b244e0 drm/i915/icl: Fetch DSI pkt to be transferred
6f27802c08aa drm/i915/icl: Add DSI packet payload/header registers
95614818e50b drm/i915/icl: Allocate hosts for DSI ports
9447a71cdb6b drm/i915/icl: Allocate DSI encoder/connector
f6c4ae07a154 drm/i915/icl: Find DSI presence for ICL
71f90c5344a2 drm/i915/icl: Program HS_TX_TIMEOUT/LP_RX_TIMEOUT/TA_TIMEOUT registers
8f96cf43f453 drm/i915/icl: Define DSI timeout registers
ffd539172104 drm/i915/icl: Disable DSI IO power
3dd8ac3bdc51 drm/i915/icl: Disable DSI ports
389528d1498d drm/i915/icl: Disable portsync mode
32ebc3e760a5 drm/i915/icl: Disable DDI function
f92b349c0578 drm/i915/icl: Put DSI link in ULPS
496f9c431181 drm/i915/icl: Power down DSI panel
e3b83d15858b drm/i915/icl: Disable DSI transcoders
22cfa12e43d3 drm/i915/icl: Turn OFF panel backlight
8dd7cb7cd9f4 drm/i915/icl: Turn ON panel backlight
23539e8ed054 drm/i915/icl: Wait for header/payload credits release
3c73fd0e759d drm/i915/icl: Power on DSI panel
d122a34905d5 drm/i915/icl: Set max return packet size for DSI panel
a43a103a8a44 drm/i915/dsi: move connector mode functions to common file
b251037fd588 drm/i915/icl: Move dsi host init code to common file
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10650/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [PATCH v8 00/38] drm/i915/icl: dsi enabling
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (40 preceding siblings ...)
2018-10-30 12:51 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2018-10-30 13:07 ` Jani Nikula
2018-10-30 16:07 ` ✗ Fi.CI.BAT: failure for drm/i915/icl: dsi enabling (rev3) Patchwork
42 siblings, 0 replies; 75+ messages in thread
From: Jani Nikula @ 2018-10-30 13:07 UTC (permalink / raw)
To: intel-gfx
On Tue, 30 Oct 2018, Jani Nikula <jani.nikula@intel.com> wrote:
> Jani Nikula (3):
> drm/i915/icl: Allocate DSI encoder/connector
> drm/i915/icl: Allocate hosts for DSI ports
> drm/i915/icl: Load DSI packet payload to queue
These are by Madhav, I accidentally took authorship while
rebasing. Fixed locally.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 75+ messages in thread* ✗ Fi.CI.BAT: failure for drm/i915/icl: dsi enabling (rev3)
2018-10-30 11:56 [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
` (41 preceding siblings ...)
2018-10-30 13:07 ` [PATCH v8 00/38] drm/i915/icl: dsi enabling Jani Nikula
@ 2018-10-30 16:07 ` Patchwork
42 siblings, 0 replies; 75+ messages in thread
From: Patchwork @ 2018-10-30 16:07 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/icl: dsi enabling (rev3)
URL : https://patchwork.freedesktop.org/series/51011/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5055 -> Patchwork_10651 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10651 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10651, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/51011/revisions/3/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10651:
=== IGT changes ===
==== Possible regressions ====
igt@kms_flip@basic-flip-vs-wf_vblank:
fi-icl-u: NOTRUN -> DMESG-WARN +17
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-icl-u2: PASS -> DMESG-WARN +17
== Known issues ==
Here are the changes found in Patchwork_10651 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_selftest@live_contexts:
fi-icl-u: NOTRUN -> DMESG-FAIL (fdo#108569)
igt@gem_ctx_create@basic-files:
fi-icl-u2: PASS -> DMESG-WARN (fdo#107724)
igt@kms_frontbuffer_tracking@basic:
fi-hsw-peppy: PASS -> DMESG-WARN (fdo#102614)
fi-byt-clapper: PASS -> FAIL (fdo#103167)
==== Possible fixes ====
igt@debugfs_test@read_all_entries:
fi-icl-u2: DMESG-WARN (fdo#108070) -> PASS
igt@gem_ctx_switch@basic-default:
fi-icl-u: INCOMPLETE (fdo#108315) -> PASS
igt@gem_exec_suspend@basic-s3:
fi-icl-u2: DMESG-WARN (fdo#106612) -> PASS
fi-skl-6700k2: INCOMPLETE (k.org#199541, fdo#104108, fdo#107773, fdo#105524) -> PASS
fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#105524 https://bugs.freedesktop.org/show_bug.cgi?id=105524
fdo#106612 https://bugs.freedesktop.org/show_bug.cgi?id=106612
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724
fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
fdo#108070 https://bugs.freedesktop.org/show_bug.cgi?id=108070
fdo#108315 https://bugs.freedesktop.org/show_bug.cgi?id=108315
fdo#108569 https://bugs.freedesktop.org/show_bug.cgi?id=108569
k.org#199541 https://bugzilla.kernel.org/show_bug.cgi?id=199541
== Participating hosts (48 -> 43) ==
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u
== Build changes ==
* Linux: CI_DRM_5055 -> Patchwork_10651
CI_DRM_5055: 9471771fb0a56bb6559279fcdbb445d270036af3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4700: b517f6533671552166c11748ee48019093ebd069 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10651: 87c8755de8fc26e7997599089806eed5a1b8d86d @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
87c8755de8fc drm/i915/icl: Get pipe timings for DSI
4e19ec989821 drm/i915/icl: Consider DSI for getting transcoder state
b4c783231fd1 drm/i915/icl: Don't wait for empty FIFO
b3834b323e7d HACK: drm/i915/icl: Configure backlight functions for DSI
cbd69ec4862c drm/i915/icl: Add changes to program DSI panel GPIOs
8092c3e0dd04 drm/i915/icl: Define display GPIO pins for DSI
01e453ac8a6a drm/i915/icl: Define missing bitfield for shortplug reg
aaf6977b06cb drm/i915/icl: Define Panel power ctrl register
72501c3a8bba drm/i915/icl: Configure DSI Dual link mode
2f152a982bd2 drm/i915/icl: Add DSS_CTL Registers
e26fb20cea2f drm/i915/icl: Fill DSI ports info
e894b96c824e drm/i915/icl: Add DSI encoder remaining functions
72c28090b6a5 drm/i915/icl: Add DSI connector helper functions
4748427f0452 drm/i915/icl: Add DSI connector functions
cd3d49a7257a drm/i915/icl: Get HW state for DSI encoder
7bc214009751 drm/i915/icl: Add get config functionality for DSI
df317648ec35 drm/i915/icl: Load DSI packet payload to queue
85ce70db0e45 drm/i915/icl: Fetch DSI pkt to be transferred
992b03129f02 drm/i915/icl: Add DSI packet payload/header registers
c69cff40f89b drm/i915/icl: Allocate hosts for DSI ports
83b3f57d6785 drm/i915/icl: Allocate DSI encoder/connector
0f3cc0b226a3 drm/i915/icl: Find DSI presence for ICL
ad6fc7baabda drm/i915/icl: Program HS_TX_TIMEOUT/LP_RX_TIMEOUT/TA_TIMEOUT registers
dfb7554669d3 drm/i915/icl: Define DSI timeout registers
cbfe2668e9d7 drm/i915/icl: Disable DSI IO power
32d59c491aa9 drm/i915/icl: Disable DSI ports
6b60f18669ea drm/i915/icl: Disable portsync mode
8c3c2895d1d6 drm/i915/icl: Disable DDI function
b6edabbc57fe drm/i915/icl: Put DSI link in ULPS
2067dfe457b7 drm/i915/icl: Power down DSI panel
b92c76578e74 drm/i915/icl: Disable DSI transcoders
950c3a1aa9a5 drm/i915/icl: Turn OFF panel backlight
60094b0b1a0f drm/i915/icl: Turn ON panel backlight
e9292f4d89a1 drm/i915/icl: Wait for header/payload credits release
305852897045 drm/i915/icl: Power on DSI panel
135a2b67e55c drm/i915/icl: Set max return packet size for DSI panel
f7f96e0f27e0 drm/i915/dsi: move connector mode functions to common file
3ebb13982976 drm/i915/icl: Move dsi host init code to common file
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10651/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 75+ messages in thread