[Intel-gfx] [PATCH 00/26] drm/i915: Make fastset not suck and allow seamless M/N changes

[Intel-gfx] [PATCH 00/26] drm/i915: Make fastset not suck and allow seamless M/N changes

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Here's a (still somewhat rough) series to get rid of al those horrible
fuzzy clock checks in the fastset code. We achieve that by feeding back
the actual DPLL frequency and actual dotclock into the crtc state.

And with fastset made to not suck we can consider allowing
seameless M/N changes on eDP panels that support such things.
I've given that a quick test here on a TGL and it seemed to work
OK.

The rough parts:
- The DPLL stuff is kinda messy still, a lot of which is due to
  the dpll_mgr vs. not depending on platform/output type. Maybe
  it's finally time to start cleaning that mess up...
- fastboot is a bit challenging due to rounding behaviour
  differences between i915 vs. VBIOS/GOP
- DSI clock handling is snafu
- Didn't polish some of the things fully yet
- Might be some stuff I've still overlooked

Figured I'd see if there's any feedback, and get CI results for
it anyway.

Pushed the lot here:
https://github.com/vsyrjala/linux.git crtc_clock_compute_8

Ville Syrjälä (26):
  drm/i915: Split shared dpll .get_dplls() into compute and get phases
  drm/i915: Do .crtc_compute_clock() earlier
  drm/i915: Clean up DPLL related debugs
  drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
  drm/i915: Extract PIPE_CONF_CHECK_TIMINGS()
  drm/i915: Extract PIPE_CONF_CHECK_RECT()
  drm/i915: Adjust intel_modeset_pipe_config() & co. calling convention
  drm/i915: s/pipe_config/crtc_state/
  drm/i915: Improve modeset debugs
  drm/i915: Extract intel_crtc_dotclock()
  drm/i915: Introduce struct iclkip_params
  drm/i915: Feed the DPLL output freq back into crtc_state
  drm/i915: Compute clocks earlier
  drm/i915: Skip FDI vs. dotclock sanity check during readout
  drm/i915: Make M/N checks non-fuzzy
  drm/i915: Make all clock checks non-fuzzy
  drm/i915: Set active dpll early for icl+
  drm/i915: Nuke fastet state copy hacks
  drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not
    enabled
  drm/i915: Check hw.enable and hw.active in intel_pipe_config_compare()
  drm/i915: Add intel_panel_highest_mode()
  drm/i915: Allow M/N change during fastset on bdw+
  drm/i915: Require an exact DP link freq match for the DG2 PLL
  drm/i915: Use a fixed N value always
  drm/i915: Round to closest in M/N calculations
  drm/i915: Round TMDS clock to nearest

 drivers/gpu/drm/i915/display/intel_crt.c      |   3 +
 drivers/gpu/drm/i915/display/intel_ddi.c      |  21 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 376 +++++++-----------
 drivers/gpu/drm/i915/display/intel_display.h  |   2 +-
 .../drm/i915/display/intel_display_types.h    |   1 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  36 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   3 +-
 drivers/gpu/drm/i915/display/intel_dpll.c     | 156 +++++---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 373 ++++++++++++-----
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   3 +
 drivers/gpu/drm/i915/display/intel_fdi.c      |   2 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c     |   2 +-
 drivers/gpu/drm/i915/display/intel_panel.c    |  15 +
 drivers/gpu/drm/i915/display/intel_panel.h    |   3 +
 .../gpu/drm/i915/display/intel_pch_refclk.c   | 100 +++--
 .../gpu/drm/i915/display/intel_pch_refclk.h   |   1 +
 drivers/gpu/drm/i915/display/intel_snps_phy.c |   2 +-
 17 files changed, 650 insertions(+), 449 deletions(-)

-- 
2.35.1

[Intel-gfx] [PATCH 01/26] drm/i915: Split shared dpll .get_dplls() into compute and get phases

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Split the DPLL state computation into a separate function
from the current .get_dplls() which currently serves a dual duty
by also reserving the shared DPLLs.

v2: s/false/-EINVAL/ (Jani)

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll.c     |  14 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 291 +++++++++++++-----
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   3 +
 3 files changed, 235 insertions(+), 73 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 6eef0b8a91eb..c19fb075ee6e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -933,7 +933,17 @@ static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
 static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
 				  struct intel_crtc *crtc)
 {
-	return 0;
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	struct intel_encoder *encoder =
+		intel_get_crtc_new_encoder(state, crtc_state);
+
+	if (DISPLAY_VER(dev_priv) < 11 &&
+	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
+		return 0;
+
+	return intel_compute_shared_dplls(state, crtc, encoder);
 }
 
 static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
@@ -1134,7 +1144,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
 	ilk_compute_dpll(crtc_state, &crtc_state->dpll,
 			 &crtc_state->dpll);
 
-	return 0;
+	return intel_compute_shared_dplls(state, crtc, NULL);
 }
 
 static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 22f55574a35c..4c5c3439b745 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -90,6 +90,9 @@ struct intel_shared_dpll_funcs {
 struct intel_dpll_mgr {
 	const struct dpll_info *dpll_info;
 
+	int (*compute_dplls)(struct intel_atomic_state *state,
+			     struct intel_crtc *crtc,
+			     struct intel_encoder *encoder);
 	int (*get_dplls)(struct intel_atomic_state *state,
 			 struct intel_crtc *crtc,
 			 struct intel_encoder *encoder);
@@ -514,6 +517,13 @@ static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
 	udelay(200);
 }
 
+static int ibx_compute_dpll(struct intel_atomic_state *state,
+			    struct intel_crtc *crtc,
+			    struct intel_encoder *encoder)
+{
+	return 0;
+}
+
 static int ibx_get_dpll(struct intel_atomic_state *state,
 			struct intel_crtc *crtc,
 			struct intel_encoder *encoder)
@@ -578,6 +588,7 @@ static const struct dpll_info pch_plls[] = {
 
 static const struct intel_dpll_mgr pch_pll_mgr = {
 	.dpll_info = pch_plls,
+	.compute_dplls = ibx_compute_dpll,
 	.get_dplls = ibx_get_dpll,
 	.put_dplls = intel_put_dpll,
 	.dump_hw_state = ibx_dump_hw_state,
@@ -894,33 +905,35 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
 	*r2_out = best.r2;
 }
 
-static struct intel_shared_dpll *
-hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
-		       struct intel_crtc *crtc)
+static int
+hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
+			   struct intel_crtc *crtc)
 {
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
-	struct intel_shared_dpll *pll;
-	u32 val;
 	unsigned int p, n2, r2;
 
 	hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p);
 
-	val = WRPLL_PLL_ENABLE | WRPLL_REF_LCPLL |
-	      WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
-	      WRPLL_DIVIDER_POST(p);
+	crtc_state->dpll_hw_state.wrpll =
+		WRPLL_PLL_ENABLE | WRPLL_REF_LCPLL |
+		WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
+		WRPLL_DIVIDER_POST(p);
 
-	crtc_state->dpll_hw_state.wrpll = val;
+	return 0;
+}
 
-	pll = intel_find_shared_dpll(state, crtc,
-				     &crtc_state->dpll_hw_state,
-				     BIT(DPLL_ID_WRPLL2) |
-				     BIT(DPLL_ID_WRPLL1));
+static struct intel_shared_dpll *
+hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
+		       struct intel_crtc *crtc)
+{
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
 
-	if (!pll)
-		return NULL;
-
-	return pll;
+	return intel_find_shared_dpll(state, crtc,
+				      &crtc_state->dpll_hw_state,
+				      BIT(DPLL_ID_WRPLL2) |
+				      BIT(DPLL_ID_WRPLL1));
 }
 
 static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
@@ -963,6 +976,24 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
 	return (refclk * n / 10) / (p * r) * 2;
 }
 
+static int
+hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+	int clock = crtc_state->port_clock;
+
+	switch (clock / 2) {
+	case 81000:
+	case 135000:
+	case 270000:
+		return 0;
+	default:
+		drm_dbg_kms(&dev_priv->drm, "Invalid clock for DP: %d\n",
+			    clock);
+		return -EINVAL;
+	}
+}
+
 static struct intel_shared_dpll *
 hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
 {
@@ -982,8 +1013,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
 		pll_id = DPLL_ID_LCPLL_2700;
 		break;
 	default:
-		drm_dbg_kms(&dev_priv->drm, "Invalid clock for DP: %d\n",
-			    clock);
+		MISSING_CASE(clock / 2);
 		return NULL;
 	}
 
@@ -1019,6 +1049,22 @@ static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915,
 	return link_clock * 2;
 }
 
+static int
+hsw_ddi_spll_compute_dpll(struct intel_atomic_state *state,
+			  struct intel_crtc *crtc)
+{
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+
+	if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000))
+		return -EINVAL;
+
+	crtc_state->dpll_hw_state.spll =
+		SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;
+
+	return 0;
+}
+
 static struct intel_shared_dpll *
 hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
 		      struct intel_crtc *crtc)
@@ -1026,12 +1072,6 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 
-	if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000))
-		return NULL;
-
-	crtc_state->dpll_hw_state.spll = SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz |
-					 SPLL_REF_MUXED_SSC;
-
 	return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state,
 				      BIT(DPLL_ID_SPLL));
 }
@@ -1060,6 +1100,23 @@ static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
 	return link_clock * 2;
 }
 
+static int hsw_compute_dpll(struct intel_atomic_state *state,
+			    struct intel_crtc *crtc,
+			    struct intel_encoder *encoder)
+{
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+		return hsw_ddi_wrpll_compute_dpll(state, crtc);
+	else if (intel_crtc_has_dp_encoder(crtc_state))
+		return hsw_ddi_lcpll_compute_dpll(crtc_state);
+	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
+		return hsw_ddi_spll_compute_dpll(state, crtc);
+	else
+		return -EINVAL;
+}
+
 static int hsw_get_dpll(struct intel_atomic_state *state,
 			struct intel_crtc *crtc,
 			struct intel_encoder *encoder)
@@ -1153,6 +1210,7 @@ static const struct dpll_info hsw_plls[] = {
 
 static const struct intel_dpll_mgr hsw_pll_mgr = {
 	.dpll_info = hsw_plls,
+	.compute_dplls = hsw_compute_dpll,
 	.get_dplls = hsw_get_dpll,
 	.put_dplls = intel_put_dpll,
 	.update_ref_clks = hsw_update_dpll_ref_clks,
@@ -1741,6 +1799,21 @@ static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
 	return link_clock * 2;
 }
 
+static int skl_compute_dpll(struct intel_atomic_state *state,
+			    struct intel_crtc *crtc,
+			    struct intel_encoder *encoder)
+{
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+		return skl_ddi_hdmi_pll_dividers(crtc_state);
+	else if (intel_crtc_has_dp_encoder(crtc_state))
+		return skl_ddi_dp_set_dpll_hw_state(crtc_state);
+	else
+		return -EINVAL;
+}
+
 static int skl_get_dpll(struct intel_atomic_state *state,
 			struct intel_crtc *crtc,
 			struct intel_encoder *encoder)
@@ -1748,16 +1821,6 @@ static int skl_get_dpll(struct intel_atomic_state *state,
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct intel_shared_dpll *pll;
-	int ret;
-
-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
-		ret = skl_ddi_hdmi_pll_dividers(crtc_state);
-	else if (intel_crtc_has_dp_encoder(crtc_state))
-		ret = skl_ddi_dp_set_dpll_hw_state(crtc_state);
-	else
-		ret = -EINVAL;
-	if (ret)
-		return ret;
 
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 		pll = intel_find_shared_dpll(state, crtc,
@@ -1834,6 +1897,7 @@ static const struct dpll_info skl_plls[] = {
 
 static const struct intel_dpll_mgr skl_pll_mgr = {
 	.dpll_info = skl_plls,
+	.compute_dplls = skl_compute_dpll,
 	.get_dplls = skl_get_dpll,
 	.put_dplls = intel_put_dpll,
 	.update_ref_clks = skl_update_dpll_ref_clks,
@@ -2225,6 +2289,21 @@ static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
 	return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock);
 }
 
+static int bxt_compute_dpll(struct intel_atomic_state *state,
+			    struct intel_crtc *crtc,
+			    struct intel_encoder *encoder)
+{
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+		return bxt_ddi_hdmi_set_dpll_hw_state(crtc_state);
+	else if (intel_crtc_has_dp_encoder(crtc_state))
+		return bxt_ddi_dp_set_dpll_hw_state(crtc_state);
+	else
+		return -EINVAL;
+}
+
 static int bxt_get_dpll(struct intel_atomic_state *state,
 			struct intel_crtc *crtc,
 			struct intel_encoder *encoder)
@@ -2234,16 +2313,6 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_shared_dpll *pll;
 	enum intel_dpll_id id;
-	int ret;
-
-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
-		ret = bxt_ddi_hdmi_set_dpll_hw_state(crtc_state);
-	else if (intel_crtc_has_dp_encoder(crtc_state))
-		ret = bxt_ddi_dp_set_dpll_hw_state(crtc_state);
-	else
-		ret = -EINVAL;
-	if (ret)
-		return ret;
 
 	/* 1:1 mapping between ports and PLLs */
 	id = (enum intel_dpll_id) encoder->port;
@@ -2302,6 +2371,7 @@ static const struct dpll_info bxt_plls[] = {
 
 static const struct intel_dpll_mgr bxt_pll_mgr = {
 	.dpll_info = bxt_plls,
+	.compute_dplls = bxt_compute_dpll,
 	.get_dplls = bxt_get_dpll,
 	.put_dplls = intel_put_dpll,
 	.update_ref_clks = bxt_update_dpll_ref_clks,
@@ -3119,19 +3189,16 @@ static u32 intel_get_hti_plls(struct drm_i915_private *i915)
 	return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->hti_state);
 }
 
-static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
-				  struct intel_crtc *crtc,
-				  struct intel_encoder *encoder)
+static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
+				      struct intel_crtc *crtc)
 {
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
-	struct skl_wrpll_params pll_params = { };
 	struct icl_port_dpll *port_dpll =
 		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	enum port port = encoder->port;
-	unsigned long dpll_mask;
-	int ret;
+	struct skl_wrpll_params pll_params = {};
+	bool ret;
 
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
@@ -3147,6 +3214,21 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
 
 	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
 
+	return 0;
+}
+
+static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
+				  struct intel_crtc *crtc,
+				  struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	struct icl_port_dpll *port_dpll =
+		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
+	enum port port = encoder->port;
+	unsigned long dpll_mask;
+
 	if (IS_ALDERLAKE_S(dev_priv)) {
 		dpll_mask =
 			BIT(DPLL_ID_DG1_DPLL3) |
@@ -3198,6 +3280,38 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
 	return 0;
 }
 
+static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
+				    struct intel_crtc *crtc)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	struct icl_port_dpll *port_dpll =
+		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
+	struct skl_wrpll_params pll_params = {};
+	int ret;
+
+	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
+	ret = icl_calc_tbt_pll(crtc_state, &pll_params);
+	if (ret) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "Could not calculate TBT PLL state.\n");
+		return ret;
+	}
+
+	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
+
+	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
+	ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
+	if (ret) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "Could not calculate MG PHY PLL state.\n");
+		return ret;
+	}
+
+	return 0;
+}
+
 static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
 				struct intel_crtc *crtc,
 				struct intel_encoder *encoder)
@@ -3205,21 +3319,12 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
-	struct skl_wrpll_params pll_params = { };
-	struct icl_port_dpll *port_dpll;
+	struct icl_port_dpll *port_dpll =
+		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
 	enum intel_dpll_id dpll_id;
 	int ret;
 
 	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
-	ret = icl_calc_tbt_pll(crtc_state, &pll_params);
-	if (ret) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "Could not calculate TBT PLL state.\n");
-		return ret;
-	}
-
-	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
-
 	port_dpll->pll = intel_find_shared_dpll(state, crtc,
 						&port_dpll->hw_state,
 						BIT(DPLL_ID_ICL_TBTPLL));
@@ -3232,13 +3337,6 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
 
 
 	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
-	ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
-	if (ret) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "Could not calculate MG PHY PLL state.\n");
-		goto err_unreference_tbt_pll;
-	}
-
 	dpll_id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
 							 encoder->port));
 	port_dpll->pll = intel_find_shared_dpll(state, crtc,
@@ -3263,6 +3361,23 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
 	return ret;
 }
 
+static int icl_compute_dplls(struct intel_atomic_state *state,
+			     struct intel_crtc *crtc,
+			     struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
+	if (intel_phy_is_combo(dev_priv, phy))
+		return icl_compute_combo_phy_dpll(state, crtc);
+	else if (intel_phy_is_tc(dev_priv, phy))
+		return icl_compute_tc_phy_dplls(state, crtc);
+
+	MISSING_CASE(phy);
+
+	return 0;
+}
+
 static int icl_get_dplls(struct intel_atomic_state *state,
 			 struct intel_crtc *crtc,
 			 struct intel_encoder *encoder)
@@ -3943,6 +4058,7 @@ static const struct dpll_info icl_plls[] = {
 
 static const struct intel_dpll_mgr icl_pll_mgr = {
 	.dpll_info = icl_plls,
+	.compute_dplls = icl_compute_dplls,
 	.get_dplls = icl_get_dplls,
 	.put_dplls = icl_put_dplls,
 	.update_active_dpll = icl_update_active_dpll,
@@ -3959,6 +4075,7 @@ static const struct dpll_info ehl_plls[] = {
 
 static const struct intel_dpll_mgr ehl_pll_mgr = {
 	.dpll_info = ehl_plls,
+	.compute_dplls = icl_compute_dplls,
 	.get_dplls = icl_get_dplls,
 	.put_dplls = icl_put_dplls,
 	.update_ref_clks = icl_update_dpll_ref_clks,
@@ -3987,6 +4104,7 @@ static const struct dpll_info tgl_plls[] = {
 
 static const struct intel_dpll_mgr tgl_pll_mgr = {
 	.dpll_info = tgl_plls,
+	.compute_dplls = icl_compute_dplls,
 	.get_dplls = icl_get_dplls,
 	.put_dplls = icl_put_dplls,
 	.update_active_dpll = icl_update_active_dpll,
@@ -4003,6 +4121,7 @@ static const struct dpll_info rkl_plls[] = {
 
 static const struct intel_dpll_mgr rkl_pll_mgr = {
 	.dpll_info = rkl_plls,
+	.compute_dplls = icl_compute_dplls,
 	.get_dplls = icl_get_dplls,
 	.put_dplls = icl_put_dplls,
 	.update_ref_clks = icl_update_dpll_ref_clks,
@@ -4019,6 +4138,7 @@ static const struct dpll_info dg1_plls[] = {
 
 static const struct intel_dpll_mgr dg1_pll_mgr = {
 	.dpll_info = dg1_plls,
+	.compute_dplls = icl_compute_dplls,
 	.get_dplls = icl_get_dplls,
 	.put_dplls = icl_put_dplls,
 	.update_ref_clks = icl_update_dpll_ref_clks,
@@ -4035,6 +4155,7 @@ static const struct dpll_info adls_plls[] = {
 
 static const struct intel_dpll_mgr adls_pll_mgr = {
 	.dpll_info = adls_plls,
+	.compute_dplls = icl_compute_dplls,
 	.get_dplls = icl_get_dplls,
 	.put_dplls = icl_put_dplls,
 	.update_ref_clks = icl_update_dpll_ref_clks,
@@ -4054,6 +4175,7 @@ static const struct dpll_info adlp_plls[] = {
 
 static const struct intel_dpll_mgr adlp_pll_mgr = {
 	.dpll_info = adlp_plls,
+	.compute_dplls = icl_compute_dplls,
 	.get_dplls = icl_get_dplls,
 	.put_dplls = icl_put_dplls,
 	.update_active_dpll = icl_update_active_dpll,
@@ -4118,6 +4240,33 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
 	BUG_ON(dev_priv->dpll.num_shared_dpll > I915_NUM_PLLS);
 }
 
+/**
+ * intel_compute_shared_dplls - compute DPLL state CRTC and encoder combination
+ * @state: atomic state
+ * @crtc: CRTC to compute DPLLs for
+ * @encoder: encoder
+ *
+ * This function computes the DPLL state for the given CRTC and encoder.
+ *
+ * The new configuration in the atomic commit @state is made effective by
+ * calling intel_shared_dpll_swap_state().
+ *
+ * Returns:
+ * 0 on success, negative error code on falure.
+ */
+int intel_compute_shared_dplls(struct intel_atomic_state *state,
+			       struct intel_crtc *crtc,
+			       struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;
+
+	if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr))
+		return -EINVAL;
+
+	return dpll_mgr->compute_dplls(state, crtc, encoder);
+}
+
 /**
  * intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination
  * @state: atomic state
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index f7c96a1f13c8..02412bf7625c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -336,6 +336,9 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
 			bool state);
 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
+int intel_compute_shared_dplls(struct intel_atomic_state *state,
+			       struct intel_crtc *crtc,
+			       struct intel_encoder *encoder);
 int intel_reserve_shared_dplls(struct intel_atomic_state *state,
 			       struct intel_crtc *crtc,
 			       struct intel_encoder *encoder);
-- 
2.35.1

Re: [Intel-gfx] [PATCH 01/26] drm/i915: Split shared dpll .get_dplls() into compute and get phases

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Split the DPLL state computation into a separate function
> from the current .get_dplls() which currently serves a dual duty
> by also reserving the shared DPLLs.
>
> v2: s/false/-EINVAL/ (Jani)
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Sorry for the procrastination, for some reason this was a bit difficult
to follow.

> ---
>  drivers/gpu/drm/i915/display/intel_dpll.c     |  14 +-
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 291 +++++++++++++-----
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   3 +
>  3 files changed, 235 insertions(+), 73 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 6eef0b8a91eb..c19fb075ee6e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -933,7 +933,17 @@ static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
>  static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
>  				  struct intel_crtc *crtc)
>  {
> -	return 0;
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	struct intel_encoder *encoder =
> +		intel_get_crtc_new_encoder(state, crtc_state);
> +
> +	if (DISPLAY_VER(dev_priv) < 11 &&
> +	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> +		return 0;
> +
> +	return intel_compute_shared_dplls(state, crtc, encoder);
>  }
>  
>  static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
> @@ -1134,7 +1144,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
>  	ilk_compute_dpll(crtc_state, &crtc_state->dpll,
>  			 &crtc_state->dpll);
>  
> -	return 0;
> +	return intel_compute_shared_dplls(state, crtc, NULL);
>  }
>  
>  static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 22f55574a35c..4c5c3439b745 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -90,6 +90,9 @@ struct intel_shared_dpll_funcs {
>  struct intel_dpll_mgr {
>  	const struct dpll_info *dpll_info;
>  
> +	int (*compute_dplls)(struct intel_atomic_state *state,
> +			     struct intel_crtc *crtc,
> +			     struct intel_encoder *encoder);
>  	int (*get_dplls)(struct intel_atomic_state *state,
>  			 struct intel_crtc *crtc,
>  			 struct intel_encoder *encoder);
> @@ -514,6 +517,13 @@ static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
>  	udelay(200);
>  }
>  
> +static int ibx_compute_dpll(struct intel_atomic_state *state,
> +			    struct intel_crtc *crtc,
> +			    struct intel_encoder *encoder)
> +{
> +	return 0;
> +}
> +
>  static int ibx_get_dpll(struct intel_atomic_state *state,
>  			struct intel_crtc *crtc,
>  			struct intel_encoder *encoder)
> @@ -578,6 +588,7 @@ static const struct dpll_info pch_plls[] = {
>  
>  static const struct intel_dpll_mgr pch_pll_mgr = {
>  	.dpll_info = pch_plls,
> +	.compute_dplls = ibx_compute_dpll,
>  	.get_dplls = ibx_get_dpll,
>  	.put_dplls = intel_put_dpll,
>  	.dump_hw_state = ibx_dump_hw_state,
> @@ -894,33 +905,35 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
>  	*r2_out = best.r2;
>  }
>  
> -static struct intel_shared_dpll *
> -hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
> -		       struct intel_crtc *crtc)
> +static int
> +hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
> +			   struct intel_crtc *crtc)
>  {
>  	struct intel_crtc_state *crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
> -	struct intel_shared_dpll *pll;
> -	u32 val;
>  	unsigned int p, n2, r2;
>  
>  	hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p);
>  
> -	val = WRPLL_PLL_ENABLE | WRPLL_REF_LCPLL |
> -	      WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
> -	      WRPLL_DIVIDER_POST(p);
> +	crtc_state->dpll_hw_state.wrpll =
> +		WRPLL_PLL_ENABLE | WRPLL_REF_LCPLL |
> +		WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
> +		WRPLL_DIVIDER_POST(p);
>  
> -	crtc_state->dpll_hw_state.wrpll = val;
> +	return 0;
> +}
>  
> -	pll = intel_find_shared_dpll(state, crtc,
> -				     &crtc_state->dpll_hw_state,
> -				     BIT(DPLL_ID_WRPLL2) |
> -				     BIT(DPLL_ID_WRPLL1));
> +static struct intel_shared_dpll *
> +hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
> +		       struct intel_crtc *crtc)
> +{
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
>  
> -	if (!pll)
> -		return NULL;
> -
> -	return pll;
> +	return intel_find_shared_dpll(state, crtc,
> +				      &crtc_state->dpll_hw_state,
> +				      BIT(DPLL_ID_WRPLL2) |
> +				      BIT(DPLL_ID_WRPLL1));
>  }
>  
>  static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> @@ -963,6 +976,24 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
>  	return (refclk * n / 10) / (p * r) * 2;
>  }
>  
> +static int
> +hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> +	int clock = crtc_state->port_clock;
> +
> +	switch (clock / 2) {
> +	case 81000:
> +	case 135000:
> +	case 270000:
> +		return 0;
> +	default:
> +		drm_dbg_kms(&dev_priv->drm, "Invalid clock for DP: %d\n",
> +			    clock);
> +		return -EINVAL;
> +	}
> +}
> +
>  static struct intel_shared_dpll *
>  hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
>  {
> @@ -982,8 +1013,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
>  		pll_id = DPLL_ID_LCPLL_2700;
>  		break;
>  	default:
> -		drm_dbg_kms(&dev_priv->drm, "Invalid clock for DP: %d\n",
> -			    clock);
> +		MISSING_CASE(clock / 2);
>  		return NULL;
>  	}
>  
> @@ -1019,6 +1049,22 @@ static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915,
>  	return link_clock * 2;
>  }
>  
> +static int
> +hsw_ddi_spll_compute_dpll(struct intel_atomic_state *state,
> +			  struct intel_crtc *crtc)
> +{
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +
> +	if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000))
> +		return -EINVAL;
> +
> +	crtc_state->dpll_hw_state.spll =
> +		SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;
> +
> +	return 0;
> +}
> +
>  static struct intel_shared_dpll *
>  hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
>  		      struct intel_crtc *crtc)
> @@ -1026,12 +1072,6 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
>  	struct intel_crtc_state *crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  
> -	if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000))
> -		return NULL;
> -
> -	crtc_state->dpll_hw_state.spll = SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz |
> -					 SPLL_REF_MUXED_SSC;
> -
>  	return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state,
>  				      BIT(DPLL_ID_SPLL));
>  }
> @@ -1060,6 +1100,23 @@ static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
>  	return link_clock * 2;
>  }
>  
> +static int hsw_compute_dpll(struct intel_atomic_state *state,
> +			    struct intel_crtc *crtc,
> +			    struct intel_encoder *encoder)
> +{
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> +		return hsw_ddi_wrpll_compute_dpll(state, crtc);
> +	else if (intel_crtc_has_dp_encoder(crtc_state))
> +		return hsw_ddi_lcpll_compute_dpll(crtc_state);
> +	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
> +		return hsw_ddi_spll_compute_dpll(state, crtc);
> +	else
> +		return -EINVAL;
> +}
> +
>  static int hsw_get_dpll(struct intel_atomic_state *state,
>  			struct intel_crtc *crtc,
>  			struct intel_encoder *encoder)
> @@ -1153,6 +1210,7 @@ static const struct dpll_info hsw_plls[] = {
>  
>  static const struct intel_dpll_mgr hsw_pll_mgr = {
>  	.dpll_info = hsw_plls,
> +	.compute_dplls = hsw_compute_dpll,
>  	.get_dplls = hsw_get_dpll,
>  	.put_dplls = intel_put_dpll,
>  	.update_ref_clks = hsw_update_dpll_ref_clks,
> @@ -1741,6 +1799,21 @@ static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
>  	return link_clock * 2;
>  }
>  
> +static int skl_compute_dpll(struct intel_atomic_state *state,
> +			    struct intel_crtc *crtc,
> +			    struct intel_encoder *encoder)
> +{
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> +		return skl_ddi_hdmi_pll_dividers(crtc_state);
> +	else if (intel_crtc_has_dp_encoder(crtc_state))
> +		return skl_ddi_dp_set_dpll_hw_state(crtc_state);
> +	else
> +		return -EINVAL;
> +}
> +
>  static int skl_get_dpll(struct intel_atomic_state *state,
>  			struct intel_crtc *crtc,
>  			struct intel_encoder *encoder)
> @@ -1748,16 +1821,6 @@ static int skl_get_dpll(struct intel_atomic_state *state,
>  	struct intel_crtc_state *crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	struct intel_shared_dpll *pll;
> -	int ret;
> -
> -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> -		ret = skl_ddi_hdmi_pll_dividers(crtc_state);
> -	else if (intel_crtc_has_dp_encoder(crtc_state))
> -		ret = skl_ddi_dp_set_dpll_hw_state(crtc_state);
> -	else
> -		ret = -EINVAL;
> -	if (ret)
> -		return ret;
>  
>  	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
>  		pll = intel_find_shared_dpll(state, crtc,
> @@ -1834,6 +1897,7 @@ static const struct dpll_info skl_plls[] = {
>  
>  static const struct intel_dpll_mgr skl_pll_mgr = {
>  	.dpll_info = skl_plls,
> +	.compute_dplls = skl_compute_dpll,
>  	.get_dplls = skl_get_dpll,
>  	.put_dplls = intel_put_dpll,
>  	.update_ref_clks = skl_update_dpll_ref_clks,
> @@ -2225,6 +2289,21 @@ static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
>  	return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock);
>  }
>  
> +static int bxt_compute_dpll(struct intel_atomic_state *state,
> +			    struct intel_crtc *crtc,
> +			    struct intel_encoder *encoder)
> +{
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> +		return bxt_ddi_hdmi_set_dpll_hw_state(crtc_state);
> +	else if (intel_crtc_has_dp_encoder(crtc_state))
> +		return bxt_ddi_dp_set_dpll_hw_state(crtc_state);
> +	else
> +		return -EINVAL;
> +}
> +
>  static int bxt_get_dpll(struct intel_atomic_state *state,
>  			struct intel_crtc *crtc,
>  			struct intel_encoder *encoder)
> @@ -2234,16 +2313,6 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_shared_dpll *pll;
>  	enum intel_dpll_id id;
> -	int ret;
> -
> -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> -		ret = bxt_ddi_hdmi_set_dpll_hw_state(crtc_state);
> -	else if (intel_crtc_has_dp_encoder(crtc_state))
> -		ret = bxt_ddi_dp_set_dpll_hw_state(crtc_state);
> -	else
> -		ret = -EINVAL;
> -	if (ret)
> -		return ret;
>  
>  	/* 1:1 mapping between ports and PLLs */
>  	id = (enum intel_dpll_id) encoder->port;
> @@ -2302,6 +2371,7 @@ static const struct dpll_info bxt_plls[] = {
>  
>  static const struct intel_dpll_mgr bxt_pll_mgr = {
>  	.dpll_info = bxt_plls,
> +	.compute_dplls = bxt_compute_dpll,
>  	.get_dplls = bxt_get_dpll,
>  	.put_dplls = intel_put_dpll,
>  	.update_ref_clks = bxt_update_dpll_ref_clks,
> @@ -3119,19 +3189,16 @@ static u32 intel_get_hti_plls(struct drm_i915_private *i915)
>  	return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->hti_state);
>  }
>  
> -static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
> -				  struct intel_crtc *crtc,
> -				  struct intel_encoder *encoder)
> +static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
> +				      struct intel_crtc *crtc)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct intel_crtc_state *crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
> -	struct skl_wrpll_params pll_params = { };
>  	struct icl_port_dpll *port_dpll =
>  		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	enum port port = encoder->port;
> -	unsigned long dpll_mask;
> -	int ret;
> +	struct skl_wrpll_params pll_params = {};
> +	bool ret;
>  
>  	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
>  	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> @@ -3147,6 +3214,21 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
>  
>  	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
>  
> +	return 0;
> +}
> +
> +static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
> +				  struct intel_crtc *crtc,
> +				  struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	struct icl_port_dpll *port_dpll =
> +		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> +	enum port port = encoder->port;
> +	unsigned long dpll_mask;
> +
>  	if (IS_ALDERLAKE_S(dev_priv)) {
>  		dpll_mask =
>  			BIT(DPLL_ID_DG1_DPLL3) |
> @@ -3198,6 +3280,38 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
>  	return 0;
>  }
>  
> +static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
> +				    struct intel_crtc *crtc)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	struct icl_port_dpll *port_dpll =
> +		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> +	struct skl_wrpll_params pll_params = {};
> +	int ret;
> +
> +	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> +	ret = icl_calc_tbt_pll(crtc_state, &pll_params);
> +	if (ret) {
> +		drm_dbg_kms(&dev_priv->drm,
> +			    "Could not calculate TBT PLL state.\n");
> +		return ret;
> +	}
> +
> +	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
> +
> +	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
> +	ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
> +	if (ret) {
> +		drm_dbg_kms(&dev_priv->drm,
> +			    "Could not calculate MG PHY PLL state.\n");
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
>  static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
>  				struct intel_crtc *crtc,
>  				struct intel_encoder *encoder)
> @@ -3205,21 +3319,12 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
>  	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>  	struct intel_crtc_state *crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
> -	struct skl_wrpll_params pll_params = { };
> -	struct icl_port_dpll *port_dpll;
> +	struct icl_port_dpll *port_dpll =
> +		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
>  	enum intel_dpll_id dpll_id;
>  	int ret;
>  
>  	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> -	ret = icl_calc_tbt_pll(crtc_state, &pll_params);
> -	if (ret) {
> -		drm_dbg_kms(&dev_priv->drm,
> -			    "Could not calculate TBT PLL state.\n");
> -		return ret;
> -	}
> -
> -	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
> -
>  	port_dpll->pll = intel_find_shared_dpll(state, crtc,
>  						&port_dpll->hw_state,
>  						BIT(DPLL_ID_ICL_TBTPLL));
> @@ -3232,13 +3337,6 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
>  
>  
>  	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
> -	ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
> -	if (ret) {
> -		drm_dbg_kms(&dev_priv->drm,
> -			    "Could not calculate MG PHY PLL state.\n");
> -		goto err_unreference_tbt_pll;
> -	}
> -
>  	dpll_id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
>  							 encoder->port));
>  	port_dpll->pll = intel_find_shared_dpll(state, crtc,
> @@ -3263,6 +3361,23 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
>  	return ret;
>  }
>  
> +static int icl_compute_dplls(struct intel_atomic_state *state,
> +			     struct intel_crtc *crtc,
> +			     struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> +
> +	if (intel_phy_is_combo(dev_priv, phy))
> +		return icl_compute_combo_phy_dpll(state, crtc);
> +	else if (intel_phy_is_tc(dev_priv, phy))
> +		return icl_compute_tc_phy_dplls(state, crtc);
> +
> +	MISSING_CASE(phy);
> +
> +	return 0;
> +}
> +
>  static int icl_get_dplls(struct intel_atomic_state *state,
>  			 struct intel_crtc *crtc,
>  			 struct intel_encoder *encoder)
> @@ -3943,6 +4058,7 @@ static const struct dpll_info icl_plls[] = {
>  
>  static const struct intel_dpll_mgr icl_pll_mgr = {
>  	.dpll_info = icl_plls,
> +	.compute_dplls = icl_compute_dplls,
>  	.get_dplls = icl_get_dplls,
>  	.put_dplls = icl_put_dplls,
>  	.update_active_dpll = icl_update_active_dpll,
> @@ -3959,6 +4075,7 @@ static const struct dpll_info ehl_plls[] = {
>  
>  static const struct intel_dpll_mgr ehl_pll_mgr = {
>  	.dpll_info = ehl_plls,
> +	.compute_dplls = icl_compute_dplls,
>  	.get_dplls = icl_get_dplls,
>  	.put_dplls = icl_put_dplls,
>  	.update_ref_clks = icl_update_dpll_ref_clks,
> @@ -3987,6 +4104,7 @@ static const struct dpll_info tgl_plls[] = {
>  
>  static const struct intel_dpll_mgr tgl_pll_mgr = {
>  	.dpll_info = tgl_plls,
> +	.compute_dplls = icl_compute_dplls,
>  	.get_dplls = icl_get_dplls,
>  	.put_dplls = icl_put_dplls,
>  	.update_active_dpll = icl_update_active_dpll,
> @@ -4003,6 +4121,7 @@ static const struct dpll_info rkl_plls[] = {
>  
>  static const struct intel_dpll_mgr rkl_pll_mgr = {
>  	.dpll_info = rkl_plls,
> +	.compute_dplls = icl_compute_dplls,
>  	.get_dplls = icl_get_dplls,
>  	.put_dplls = icl_put_dplls,
>  	.update_ref_clks = icl_update_dpll_ref_clks,
> @@ -4019,6 +4138,7 @@ static const struct dpll_info dg1_plls[] = {
>  
>  static const struct intel_dpll_mgr dg1_pll_mgr = {
>  	.dpll_info = dg1_plls,
> +	.compute_dplls = icl_compute_dplls,
>  	.get_dplls = icl_get_dplls,
>  	.put_dplls = icl_put_dplls,
>  	.update_ref_clks = icl_update_dpll_ref_clks,
> @@ -4035,6 +4155,7 @@ static const struct dpll_info adls_plls[] = {
>  
>  static const struct intel_dpll_mgr adls_pll_mgr = {
>  	.dpll_info = adls_plls,
> +	.compute_dplls = icl_compute_dplls,
>  	.get_dplls = icl_get_dplls,
>  	.put_dplls = icl_put_dplls,
>  	.update_ref_clks = icl_update_dpll_ref_clks,
> @@ -4054,6 +4175,7 @@ static const struct dpll_info adlp_plls[] = {
>  
>  static const struct intel_dpll_mgr adlp_pll_mgr = {
>  	.dpll_info = adlp_plls,
> +	.compute_dplls = icl_compute_dplls,
>  	.get_dplls = icl_get_dplls,
>  	.put_dplls = icl_put_dplls,
>  	.update_active_dpll = icl_update_active_dpll,
> @@ -4118,6 +4240,33 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
>  	BUG_ON(dev_priv->dpll.num_shared_dpll > I915_NUM_PLLS);
>  }
>  
> +/**
> + * intel_compute_shared_dplls - compute DPLL state CRTC and encoder combination
> + * @state: atomic state
> + * @crtc: CRTC to compute DPLLs for
> + * @encoder: encoder
> + *
> + * This function computes the DPLL state for the given CRTC and encoder.
> + *
> + * The new configuration in the atomic commit @state is made effective by
> + * calling intel_shared_dpll_swap_state().
> + *
> + * Returns:
> + * 0 on success, negative error code on falure.
> + */
> +int intel_compute_shared_dplls(struct intel_atomic_state *state,
> +			       struct intel_crtc *crtc,
> +			       struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +	const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;
> +
> +	if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr))
> +		return -EINVAL;
> +
> +	return dpll_mgr->compute_dplls(state, crtc, encoder);
> +}
> +
>  /**
>   * intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination
>   * @state: atomic state
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index f7c96a1f13c8..02412bf7625c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -336,6 +336,9 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
>  			bool state);
>  #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
>  #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
> +int intel_compute_shared_dplls(struct intel_atomic_state *state,
> +			       struct intel_crtc *crtc,
> +			       struct intel_encoder *encoder);
>  int intel_reserve_shared_dplls(struct intel_atomic_state *state,
>  			       struct intel_crtc *crtc,
>  			       struct intel_encoder *encoder);

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 02/26] drm/i915: Do .crtc_compute_clock() earlier

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we calculate a lot of things (pixel rate, watermarks,
cdclk) trusting that the DPLL can generate the exact frequency
we ask it. In practice that is not true and there can be
certain amount of rounding involved.

To allow us to eventually get accurate numbers for all our
DPLL clock derived state we need to move the DPLL calculation
to hapen much earlier. To that end we hoist it up to the just
after the fastset checks. For now we just do the easy code
motion, and the actual back feeding of the final DPLL clock
into the state will come later.

A slight change here is that now .crtc_compute_clock()
can get called while the shared_dpll is still assigned.
But since .crtc_compute_clock() no longer assignes new
shared_dplls this is perfectly fine.

TODO: I'd actually like to do this before the fastset check
so that if the DPLL state should change we actually do the
modeset. Which I think is what the video aficionados want,
but it might not be what the fans of fastboot want. Not yet
sure how to reconcile those conflicting requirements...

v2: s/return/goto/ in error handling

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 9 +++++----
 drivers/gpu/drm/i915/display/intel_dpll.c    | 3 ---
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0decf3d24237..5e50e0d56088 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4905,10 +4905,6 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
 		crtc_state->update_wm_post = true;
 
 	if (mode_changed) {
-		ret = intel_dpll_crtc_compute_clock(state, crtc);
-		if (ret)
-			return ret;
-
 		ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
 		if (ret)
 			return ret;
@@ -7801,6 +7797,11 @@ static int intel_atomic_check(struct drm_device *dev,
 					    new_crtc_state, i) {
 		if (intel_crtc_needs_modeset(new_crtc_state)) {
 			any_ms = true;
+
+			ret = intel_dpll_crtc_compute_clock(state, crtc);
+			if (ret)
+				goto fail;
+
 			continue;
 		}
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index c19fb075ee6e..7f0538ee2b51 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1449,9 +1449,6 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
 
 	drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
 
-	if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll))
-		return 0;
-
 	memset(&crtc_state->dpll_hw_state, 0,
 	       sizeof(crtc_state->dpll_hw_state));
 
-- 
2.35.1

Re: [Intel-gfx] [PATCH 02/26] drm/i915: Do .crtc_compute_clock() earlier

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Currently we calculate a lot of things (pixel rate, watermarks,
> cdclk) trusting that the DPLL can generate the exact frequency
> we ask it. In practice that is not true and there can be
> certain amount of rounding involved.
>
> To allow us to eventually get accurate numbers for all our
> DPLL clock derived state we need to move the DPLL calculation
> to hapen much earlier. To that end we hoist it up to the just
> after the fastset checks. For now we just do the easy code
> motion, and the actual back feeding of the final DPLL clock
> into the state will come later.
>
> A slight change here is that now .crtc_compute_clock()
> can get called while the shared_dpll is still assigned.
> But since .crtc_compute_clock() no longer assignes new
> shared_dplls this is perfectly fine.
>
> TODO: I'd actually like to do this before the fastset check
> so that if the DPLL state should change we actually do the
> modeset. Which I think is what the video aficionados want,
> but it might not be what the fans of fastboot want. Not yet
> sure how to reconcile those conflicting requirements...
>
> v2: s/return/goto/ in error handling
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 9 +++++----
>  drivers/gpu/drm/i915/display/intel_dpll.c    | 3 ---
>  2 files changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 0decf3d24237..5e50e0d56088 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4905,10 +4905,6 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
>  		crtc_state->update_wm_post = true;
>  
>  	if (mode_changed) {
> -		ret = intel_dpll_crtc_compute_clock(state, crtc);
> -		if (ret)
> -			return ret;
> -
>  		ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
>  		if (ret)
>  			return ret;
> @@ -7801,6 +7797,11 @@ static int intel_atomic_check(struct drm_device *dev,
>  					    new_crtc_state, i) {
>  		if (intel_crtc_needs_modeset(new_crtc_state)) {
>  			any_ms = true;
> +
> +			ret = intel_dpll_crtc_compute_clock(state, crtc);
> +			if (ret)
> +				goto fail;
> +
>  			continue;
>  		}
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index c19fb075ee6e..7f0538ee2b51 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1449,9 +1449,6 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
>  
>  	drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
>  
> -	if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll))
> -		return 0;
> -
>  	memset(&crtc_state->dpll_hw_state, 0,
>  	       sizeof(crtc_state->dpll_hw_state));

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 03/26] drm/i915: Clean up DPLL related debugs

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The debugs in lower level DPLL code don't really provide any
useful extra information AFAICS. Better just streamline the
code and just put the necessary debugs (to identify at which
step the modeset failed) into the higher level code. In
addition we'll get the full state dump as well, which should
hopefully have enough information to figure out what went wrong.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll.c     | 75 +++++++------------
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 48 +++---------
 2 files changed, 35 insertions(+), 88 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 7f0538ee2b51..2b3f72550e5a 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -954,21 +954,12 @@ static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct intel_encoder *encoder =
 		intel_get_crtc_new_encoder(state, crtc_state);
-	int ret;
 
 	if (DISPLAY_VER(dev_priv) < 11 &&
 	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
 		return 0;
 
-	ret = intel_reserve_shared_dplls(state, crtc, encoder);
-	if (ret) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "failed to find PLL for pipe %c\n",
-			    pipe_name(crtc->pipe));
-		return ret;
-	}
-
-	return 0;
+	return intel_reserve_shared_dplls(state, crtc, encoder);
 }
 
 static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
@@ -1135,11 +1126,8 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
 
 	if (!crtc_state->clock_set &&
 	    !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
-				refclk, NULL, &crtc_state->dpll)) {
-		drm_err(&dev_priv->drm,
-			"Couldn't find PLL settings for mode!\n");
+				refclk, NULL, &crtc_state->dpll))
 		return -EINVAL;
-	}
 
 	ilk_compute_dpll(crtc_state, &crtc_state->dpll,
 			 &crtc_state->dpll);
@@ -1150,24 +1138,14 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
 static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
 				    struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
-	int ret;
 
 	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
 	if (!crtc_state->has_pch_encoder)
 		return 0;
 
-	ret = intel_reserve_shared_dplls(state, crtc, NULL);
-	if (ret) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "failed to find PLL for pipe %c\n",
-			    pipe_name(crtc->pipe));
-		return ret;
-	}
-
-	return 0;
+	return intel_reserve_shared_dplls(state, crtc, NULL);
 }
 
 void vlv_compute_dpll(struct intel_crtc_state *crtc_state)
@@ -1208,7 +1186,6 @@ void chv_compute_dpll(struct intel_crtc_state *crtc_state)
 static int chv_crtc_compute_clock(struct intel_atomic_state *state,
 				  struct intel_crtc *crtc)
 {
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	const struct intel_limit *limit = &intel_limits_chv;
@@ -1216,10 +1193,8 @@ static int chv_crtc_compute_clock(struct intel_atomic_state *state,
 
 	if (!crtc_state->clock_set &&
 	    !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
-				refclk, NULL, &crtc_state->dpll)) {
-		drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
+				refclk, NULL, &crtc_state->dpll))
 		return -EINVAL;
-	}
 
 	chv_compute_dpll(crtc_state);
 
@@ -1229,7 +1204,6 @@ static int chv_crtc_compute_clock(struct intel_atomic_state *state,
 static int vlv_crtc_compute_clock(struct intel_atomic_state *state,
 				  struct intel_crtc *crtc)
 {
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	const struct intel_limit *limit = &intel_limits_vlv;
@@ -1238,7 +1212,6 @@ static int vlv_crtc_compute_clock(struct intel_atomic_state *state,
 	if (!crtc_state->clock_set &&
 	    !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
 				refclk, NULL, &crtc_state->dpll)) {
-		drm_err(&i915->drm,  "Couldn't find PLL settings for mode!\n");
 		return -EINVAL;
 	}
 
@@ -1280,11 +1253,8 @@ static int g4x_crtc_compute_clock(struct intel_atomic_state *state,
 
 	if (!crtc_state->clock_set &&
 	    !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
-				refclk, NULL, &crtc_state->dpll)) {
-		drm_err(&dev_priv->drm,
-			"Couldn't find PLL settings for mode!\n");
+				refclk, NULL, &crtc_state->dpll))
 		return -EINVAL;
-	}
 
 	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
 			  &crtc_state->dpll);
@@ -1316,11 +1286,8 @@ static int pnv_crtc_compute_clock(struct intel_atomic_state *state,
 
 	if (!crtc_state->clock_set &&
 	    !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
-				refclk, NULL, &crtc_state->dpll)) {
-		drm_err(&dev_priv->drm,
-			"Couldn't find PLL settings for mode!\n");
+				refclk, NULL, &crtc_state->dpll))
 		return -EINVAL;
-	}
 
 	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
 			  &crtc_state->dpll);
@@ -1352,11 +1319,8 @@ static int i9xx_crtc_compute_clock(struct intel_atomic_state *state,
 
 	if (!crtc_state->clock_set &&
 	    !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
-				 refclk, NULL, &crtc_state->dpll)) {
-		drm_err(&dev_priv->drm,
-			"Couldn't find PLL settings for mode!\n");
+				 refclk, NULL, &crtc_state->dpll))
 		return -EINVAL;
-	}
 
 	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
 			  &crtc_state->dpll);
@@ -1390,11 +1354,8 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
 
 	if (!crtc_state->clock_set &&
 	    !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
-				 refclk, NULL, &crtc_state->dpll)) {
-		drm_err(&dev_priv->drm,
-			"Couldn't find PLL settings for mode!\n");
+				 refclk, NULL, &crtc_state->dpll))
 		return -EINVAL;
-	}
 
 	i8xx_compute_dpll(crtc_state, &crtc_state->dpll,
 			  &crtc_state->dpll);
@@ -1446,6 +1407,7 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
 	struct drm_i915_private *i915 = to_i915(state->base.dev);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
+	int ret;
 
 	drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
 
@@ -1455,7 +1417,14 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
 	if (!crtc_state->hw.enable)
 		return 0;
 
-	return i915->dpll_funcs->crtc_compute_clock(state, crtc);
+	ret = i915->dpll_funcs->crtc_compute_clock(state, crtc);
+	if (ret) {
+		drm_dbg_kms(&i915->drm,  "[CRTC:%d:%s] Couldn't calculate DPLL settings\n",
+			    crtc->base.base.id, crtc->base.name);
+		return ret;
+	}
+
+	return 0;
 }
 
 int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
@@ -1464,6 +1433,7 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
 	struct drm_i915_private *i915 = to_i915(state->base.dev);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
+	int ret;
 
 	drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
 
@@ -1476,7 +1446,14 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
 	if (!i915->dpll_funcs->crtc_get_shared_dpll)
 		return 0;
 
-	return i915->dpll_funcs->crtc_get_shared_dpll(state, crtc);
+	ret = i915->dpll_funcs->crtc_get_shared_dpll(state, crtc);
+	if (ret) {
+		drm_dbg_kms(&i915->drm,  "[CRTC:%d:%s] Couldn't get a shared DPLL\n",
+			    crtc->base.base.id, crtc->base.name);
+		return ret;
+	}
+
+	return 0;
 }
 
 void
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 4c5c3439b745..64708e874b13 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1603,10 +1603,8 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
 			break;
 	}
 
-	if (!ctx.p) {
-		DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
+	if (!ctx.p)
 		return -EINVAL;
-	}
 
 	/*
 	 * gcc incorrectly analyses that these can be used without being
@@ -2145,19 +2143,14 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
 			  struct dpll *clk_div)
 {
 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	/* Calculate HDMI div */
 	/*
 	 * FIXME: tie the following calculation into
 	 * i9xx_crtc_compute_clock
 	 */
-	if (!bxt_find_best_dpll(crtc_state, clk_div)) {
-		drm_dbg(&i915->drm, "no PLL dividers found for clock %d pipe %c\n",
-			crtc_state->port_clock,
-			pipe_name(crtc->pipe));
+	if (!bxt_find_best_dpll(crtc_state, clk_div))
 		return -EINVAL;
-	}
 
 	drm_WARN_ON(&i915->drm, clk_div->m1 != 2);
 
@@ -2879,11 +2872,8 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
 
 	ret = icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
 				       pll_state, is_dkl);
-	if (ret) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "Failed to find divisors for clock %d\n", clock);
+	if (ret)
 		return ret;
-	}
 
 	m1div = 2;
 	m2div_int = dco_khz / (refclk_khz * m1div);
@@ -2893,12 +2883,8 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
 			m2div_int = dco_khz / (refclk_khz * m1div);
 		}
 
-		if (m2div_int > 255) {
-			drm_dbg_kms(&dev_priv->drm,
-				    "Failed to find mdiv for clock %d\n",
-				    clock);
+		if (m2div_int > 255)
 			return -EINVAL;
-		}
 	}
 	m2div_rem = dco_khz % (refclk_khz * m1div);
 
@@ -3206,11 +3192,8 @@ static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
 	else
 		ret = icl_calc_dp_combo_pll(crtc_state, &pll_params);
 
-	if (ret) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "Could not calculate combo PHY PLL state.\n");
+	if (ret)
 		return ret;
-	}
 
 	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
 
@@ -3265,12 +3248,8 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
 	port_dpll->pll = intel_find_shared_dpll(state, crtc,
 						&port_dpll->hw_state,
 						dpll_mask);
-	if (!port_dpll->pll) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "No combo PHY PLL found for [ENCODER:%d:%s]\n",
-			    encoder->base.base.id, encoder->base.name);
+	if (!port_dpll->pll)
 		return -EINVAL;
-	}
 
 	intel_reference_shared_dpll(state, crtc,
 				    port_dpll->pll, &port_dpll->hw_state);
@@ -3293,21 +3272,15 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
 
 	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
 	ret = icl_calc_tbt_pll(crtc_state, &pll_params);
-	if (ret) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "Could not calculate TBT PLL state.\n");
+	if (ret)
 		return ret;
-	}
 
 	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
 
 	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
 	ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
-	if (ret) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "Could not calculate MG PHY PLL state.\n");
+	if (ret)
 		return ret;
-	}
 
 	return 0;
 }
@@ -3328,10 +3301,8 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
 	port_dpll->pll = intel_find_shared_dpll(state, crtc,
 						&port_dpll->hw_state,
 						BIT(DPLL_ID_ICL_TBTPLL));
-	if (!port_dpll->pll) {
-		drm_dbg_kms(&dev_priv->drm, "No TBT-ALT PLL found\n");
+	if (!port_dpll->pll)
 		return -EINVAL;
-	}
 	intel_reference_shared_dpll(state, crtc,
 				    port_dpll->pll, &port_dpll->hw_state);
 
@@ -3344,7 +3315,6 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
 						BIT(dpll_id));
 	if (!port_dpll->pll) {
 		ret = -EINVAL;
-		drm_dbg_kms(&dev_priv->drm, "No MG PHY PLL found\n");
 		goto err_unreference_tbt_pll;
 	}
 	intel_reference_shared_dpll(state, crtc,
-- 
2.35.1

Re: [Intel-gfx] [PATCH 03/26] drm/i915: Clean up DPLL related debugs

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The debugs in lower level DPLL code don't really provide any
> useful extra information AFAICS. Better just streamline the
> code and just put the necessary debugs (to identify at which
> step the modeset failed) into the higher level code. In
> addition we'll get the full state dump as well, which should
> hopefully have enough information to figure out what went wrong.
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Yup.

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll.c     | 75 +++++++------------
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 48 +++---------
>  2 files changed, 35 insertions(+), 88 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 7f0538ee2b51..2b3f72550e5a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -954,21 +954,12 @@ static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	struct intel_encoder *encoder =
>  		intel_get_crtc_new_encoder(state, crtc_state);
> -	int ret;
>  
>  	if (DISPLAY_VER(dev_priv) < 11 &&
>  	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
>  		return 0;
>  
> -	ret = intel_reserve_shared_dplls(state, crtc, encoder);
> -	if (ret) {
> -		drm_dbg_kms(&dev_priv->drm,
> -			    "failed to find PLL for pipe %c\n",
> -			    pipe_name(crtc->pipe));
> -		return ret;
> -	}
> -
> -	return 0;
> +	return intel_reserve_shared_dplls(state, crtc, encoder);
>  }
>  
>  static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
> @@ -1135,11 +1126,8 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
>  
>  	if (!crtc_state->clock_set &&
>  	    !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
> -				refclk, NULL, &crtc_state->dpll)) {
> -		drm_err(&dev_priv->drm,
> -			"Couldn't find PLL settings for mode!\n");
> +				refclk, NULL, &crtc_state->dpll))
>  		return -EINVAL;
> -	}
>  
>  	ilk_compute_dpll(crtc_state, &crtc_state->dpll,
>  			 &crtc_state->dpll);
> @@ -1150,24 +1138,14 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
>  static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
>  				    struct intel_crtc *crtc)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>  	struct intel_crtc_state *crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
> -	int ret;
>  
>  	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
>  	if (!crtc_state->has_pch_encoder)
>  		return 0;
>  
> -	ret = intel_reserve_shared_dplls(state, crtc, NULL);
> -	if (ret) {
> -		drm_dbg_kms(&dev_priv->drm,
> -			    "failed to find PLL for pipe %c\n",
> -			    pipe_name(crtc->pipe));
> -		return ret;
> -	}
> -
> -	return 0;
> +	return intel_reserve_shared_dplls(state, crtc, NULL);
>  }
>  
>  void vlv_compute_dpll(struct intel_crtc_state *crtc_state)
> @@ -1208,7 +1186,6 @@ void chv_compute_dpll(struct intel_crtc_state *crtc_state)
>  static int chv_crtc_compute_clock(struct intel_atomic_state *state,
>  				  struct intel_crtc *crtc)
>  {
> -	struct drm_i915_private *i915 = to_i915(state->base.dev);
>  	struct intel_crtc_state *crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	const struct intel_limit *limit = &intel_limits_chv;
> @@ -1216,10 +1193,8 @@ static int chv_crtc_compute_clock(struct intel_atomic_state *state,
>  
>  	if (!crtc_state->clock_set &&
>  	    !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
> -				refclk, NULL, &crtc_state->dpll)) {
> -		drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
> +				refclk, NULL, &crtc_state->dpll))
>  		return -EINVAL;
> -	}
>  
>  	chv_compute_dpll(crtc_state);
>  
> @@ -1229,7 +1204,6 @@ static int chv_crtc_compute_clock(struct intel_atomic_state *state,
>  static int vlv_crtc_compute_clock(struct intel_atomic_state *state,
>  				  struct intel_crtc *crtc)
>  {
> -	struct drm_i915_private *i915 = to_i915(state->base.dev);
>  	struct intel_crtc_state *crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	const struct intel_limit *limit = &intel_limits_vlv;
> @@ -1238,7 +1212,6 @@ static int vlv_crtc_compute_clock(struct intel_atomic_state *state,
>  	if (!crtc_state->clock_set &&
>  	    !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
>  				refclk, NULL, &crtc_state->dpll)) {
> -		drm_err(&i915->drm,  "Couldn't find PLL settings for mode!\n");
>  		return -EINVAL;
>  	}
>  
> @@ -1280,11 +1253,8 @@ static int g4x_crtc_compute_clock(struct intel_atomic_state *state,
>  
>  	if (!crtc_state->clock_set &&
>  	    !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
> -				refclk, NULL, &crtc_state->dpll)) {
> -		drm_err(&dev_priv->drm,
> -			"Couldn't find PLL settings for mode!\n");
> +				refclk, NULL, &crtc_state->dpll))
>  		return -EINVAL;
> -	}
>  
>  	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
>  			  &crtc_state->dpll);
> @@ -1316,11 +1286,8 @@ static int pnv_crtc_compute_clock(struct intel_atomic_state *state,
>  
>  	if (!crtc_state->clock_set &&
>  	    !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
> -				refclk, NULL, &crtc_state->dpll)) {
> -		drm_err(&dev_priv->drm,
> -			"Couldn't find PLL settings for mode!\n");
> +				refclk, NULL, &crtc_state->dpll))
>  		return -EINVAL;
> -	}
>  
>  	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
>  			  &crtc_state->dpll);
> @@ -1352,11 +1319,8 @@ static int i9xx_crtc_compute_clock(struct intel_atomic_state *state,
>  
>  	if (!crtc_state->clock_set &&
>  	    !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
> -				 refclk, NULL, &crtc_state->dpll)) {
> -		drm_err(&dev_priv->drm,
> -			"Couldn't find PLL settings for mode!\n");
> +				 refclk, NULL, &crtc_state->dpll))
>  		return -EINVAL;
> -	}
>  
>  	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
>  			  &crtc_state->dpll);
> @@ -1390,11 +1354,8 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
>  
>  	if (!crtc_state->clock_set &&
>  	    !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
> -				 refclk, NULL, &crtc_state->dpll)) {
> -		drm_err(&dev_priv->drm,
> -			"Couldn't find PLL settings for mode!\n");
> +				 refclk, NULL, &crtc_state->dpll))
>  		return -EINVAL;
> -	}
>  
>  	i8xx_compute_dpll(crtc_state, &crtc_state->dpll,
>  			  &crtc_state->dpll);
> @@ -1446,6 +1407,7 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
>  	struct drm_i915_private *i915 = to_i915(state->base.dev);
>  	struct intel_crtc_state *crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
> +	int ret;
>  
>  	drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
>  
> @@ -1455,7 +1417,14 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
>  	if (!crtc_state->hw.enable)
>  		return 0;
>  
> -	return i915->dpll_funcs->crtc_compute_clock(state, crtc);
> +	ret = i915->dpll_funcs->crtc_compute_clock(state, crtc);
> +	if (ret) {
> +		drm_dbg_kms(&i915->drm,  "[CRTC:%d:%s] Couldn't calculate DPLL settings\n",
> +			    crtc->base.base.id, crtc->base.name);
> +		return ret;
> +	}
> +
> +	return 0;
>  }
>  
>  int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
> @@ -1464,6 +1433,7 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
>  	struct drm_i915_private *i915 = to_i915(state->base.dev);
>  	struct intel_crtc_state *crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
> +	int ret;
>  
>  	drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
>  
> @@ -1476,7 +1446,14 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
>  	if (!i915->dpll_funcs->crtc_get_shared_dpll)
>  		return 0;
>  
> -	return i915->dpll_funcs->crtc_get_shared_dpll(state, crtc);
> +	ret = i915->dpll_funcs->crtc_get_shared_dpll(state, crtc);
> +	if (ret) {
> +		drm_dbg_kms(&i915->drm,  "[CRTC:%d:%s] Couldn't get a shared DPLL\n",
> +			    crtc->base.base.id, crtc->base.name);
> +		return ret;
> +	}
> +
> +	return 0;
>  }
>  
>  void
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 4c5c3439b745..64708e874b13 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -1603,10 +1603,8 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
>  			break;
>  	}
>  
> -	if (!ctx.p) {
> -		DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
> +	if (!ctx.p)
>  		return -EINVAL;
> -	}
>  
>  	/*
>  	 * gcc incorrectly analyses that these can be used without being
> @@ -2145,19 +2143,14 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
>  			  struct dpll *clk_div)
>  {
>  	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  
>  	/* Calculate HDMI div */
>  	/*
>  	 * FIXME: tie the following calculation into
>  	 * i9xx_crtc_compute_clock
>  	 */
> -	if (!bxt_find_best_dpll(crtc_state, clk_div)) {
> -		drm_dbg(&i915->drm, "no PLL dividers found for clock %d pipe %c\n",
> -			crtc_state->port_clock,
> -			pipe_name(crtc->pipe));
> +	if (!bxt_find_best_dpll(crtc_state, clk_div))
>  		return -EINVAL;
> -	}
>  
>  	drm_WARN_ON(&i915->drm, clk_div->m1 != 2);
>  
> @@ -2879,11 +2872,8 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
>  
>  	ret = icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
>  				       pll_state, is_dkl);
> -	if (ret) {
> -		drm_dbg_kms(&dev_priv->drm,
> -			    "Failed to find divisors for clock %d\n", clock);
> +	if (ret)
>  		return ret;
> -	}
>  
>  	m1div = 2;
>  	m2div_int = dco_khz / (refclk_khz * m1div);
> @@ -2893,12 +2883,8 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
>  			m2div_int = dco_khz / (refclk_khz * m1div);
>  		}
>  
> -		if (m2div_int > 255) {
> -			drm_dbg_kms(&dev_priv->drm,
> -				    "Failed to find mdiv for clock %d\n",
> -				    clock);
> +		if (m2div_int > 255)
>  			return -EINVAL;
> -		}
>  	}
>  	m2div_rem = dco_khz % (refclk_khz * m1div);
>  
> @@ -3206,11 +3192,8 @@ static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
>  	else
>  		ret = icl_calc_dp_combo_pll(crtc_state, &pll_params);
>  
> -	if (ret) {
> -		drm_dbg_kms(&dev_priv->drm,
> -			    "Could not calculate combo PHY PLL state.\n");
> +	if (ret)
>  		return ret;
> -	}
>  
>  	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
>  
> @@ -3265,12 +3248,8 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
>  	port_dpll->pll = intel_find_shared_dpll(state, crtc,
>  						&port_dpll->hw_state,
>  						dpll_mask);
> -	if (!port_dpll->pll) {
> -		drm_dbg_kms(&dev_priv->drm,
> -			    "No combo PHY PLL found for [ENCODER:%d:%s]\n",
> -			    encoder->base.base.id, encoder->base.name);
> +	if (!port_dpll->pll)
>  		return -EINVAL;
> -	}
>  
>  	intel_reference_shared_dpll(state, crtc,
>  				    port_dpll->pll, &port_dpll->hw_state);
> @@ -3293,21 +3272,15 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
>  
>  	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
>  	ret = icl_calc_tbt_pll(crtc_state, &pll_params);
> -	if (ret) {
> -		drm_dbg_kms(&dev_priv->drm,
> -			    "Could not calculate TBT PLL state.\n");
> +	if (ret)
>  		return ret;
> -	}
>  
>  	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
>  
>  	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
>  	ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
> -	if (ret) {
> -		drm_dbg_kms(&dev_priv->drm,
> -			    "Could not calculate MG PHY PLL state.\n");
> +	if (ret)
>  		return ret;
> -	}
>  
>  	return 0;
>  }
> @@ -3328,10 +3301,8 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
>  	port_dpll->pll = intel_find_shared_dpll(state, crtc,
>  						&port_dpll->hw_state,
>  						BIT(DPLL_ID_ICL_TBTPLL));
> -	if (!port_dpll->pll) {
> -		drm_dbg_kms(&dev_priv->drm, "No TBT-ALT PLL found\n");
> +	if (!port_dpll->pll)
>  		return -EINVAL;
> -	}
>  	intel_reference_shared_dpll(state, crtc,
>  				    port_dpll->pll, &port_dpll->hw_state);
>  
> @@ -3344,7 +3315,6 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
>  						BIT(dpll_id));
>  	if (!port_dpll->pll) {
>  		ret = -EINVAL;
> -		drm_dbg_kms(&dev_priv->drm, "No MG PHY PLL found\n");
>  		goto err_unreference_tbt_pll;
>  	}
>  	intel_reference_shared_dpll(state, crtc,

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 04/26] drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Only reassign the pipe's DPLL if it's going through a full
.compute_config() cycle. If OTOH it's just getting modeset
eg. in order to change cdclk there doesn't seem much point in
picking a new DPLL for it.

This should also prevent .get_dplls() from seeing a funky port_clock
for DP even in cases where the readout produces a non-standard
clock and we (for some reason) have decided to not fully recompute
the state to remedy the situation.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 17 +----------------
 drivers/gpu/drm/i915/display/intel_dpll.c    |  6 ++----
 2 files changed, 3 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5e50e0d56088..7d488d320762 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6955,20 +6955,6 @@ intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
 	}
 }
 
-static void intel_modeset_clear_plls(struct intel_atomic_state *state)
-{
-	struct intel_crtc_state *new_crtc_state;
-	struct intel_crtc *crtc;
-	int i;
-
-	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
-		if (!intel_crtc_needs_modeset(new_crtc_state))
-			continue;
-
-		intel_release_shared_dplls(state, crtc);
-	}
-}
-
 /*
  * This implements the workaround described in the "notes" section of the mode
  * set sequence documentation. When going from no pipes or single pipe to
@@ -7802,6 +7788,7 @@ static int intel_atomic_check(struct drm_device *dev,
 			if (ret)
 				goto fail;
 
+			intel_release_shared_dplls(state, crtc);
 			continue;
 		}
 
@@ -7849,8 +7836,6 @@ static int intel_atomic_check(struct drm_device *dev,
 		ret = intel_modeset_calc_cdclk(state);
 		if (ret)
 			return ret;
-
-		intel_modeset_clear_plls(state);
 	}
 
 	ret = intel_atomic_check_crtcs(state);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 2b3f72550e5a..afd30c6cc34c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1436,11 +1436,9 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
 	int ret;
 
 	drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
+	drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->shared_dpll);
 
-	if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll))
-		return 0;
-
-	if (!crtc_state->hw.enable)
+	if (!crtc_state->hw.enable || crtc_state->shared_dpll)
 		return 0;
 
 	if (!i915->dpll_funcs->crtc_get_shared_dpll)
-- 
2.35.1

Re: [Intel-gfx] [PATCH 04/26] drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Only reassign the pipe's DPLL if it's going through a full
> .compute_config() cycle. If OTOH it's just getting modeset
> eg. in order to change cdclk there doesn't seem much point in
> picking a new DPLL for it.
>
> This should also prevent .get_dplls() from seeing a funky port_clock
> for DP even in cases where the readout produces a non-standard
> clock and we (for some reason) have decided to not fully recompute
> the state to remedy the situation.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

A bit unsure if I can appreciate all the subtleties here, but

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 17 +----------------
>  drivers/gpu/drm/i915/display/intel_dpll.c    |  6 ++----
>  2 files changed, 3 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 5e50e0d56088..7d488d320762 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6955,20 +6955,6 @@ intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
>  	}
>  }
>  
> -static void intel_modeset_clear_plls(struct intel_atomic_state *state)
> -{
> -	struct intel_crtc_state *new_crtc_state;
> -	struct intel_crtc *crtc;
> -	int i;
> -
> -	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> -		if (!intel_crtc_needs_modeset(new_crtc_state))
> -			continue;
> -
> -		intel_release_shared_dplls(state, crtc);
> -	}
> -}
> -
>  /*
>   * This implements the workaround described in the "notes" section of the mode
>   * set sequence documentation. When going from no pipes or single pipe to
> @@ -7802,6 +7788,7 @@ static int intel_atomic_check(struct drm_device *dev,
>  			if (ret)
>  				goto fail;
>  
> +			intel_release_shared_dplls(state, crtc);
>  			continue;
>  		}
>  
> @@ -7849,8 +7836,6 @@ static int intel_atomic_check(struct drm_device *dev,
>  		ret = intel_modeset_calc_cdclk(state);
>  		if (ret)
>  			return ret;
> -
> -		intel_modeset_clear_plls(state);
>  	}
>  
>  	ret = intel_atomic_check_crtcs(state);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 2b3f72550e5a..afd30c6cc34c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1436,11 +1436,9 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
>  	int ret;
>  
>  	drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
> +	drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->shared_dpll);
>  
> -	if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll))
> -		return 0;
> -
> -	if (!crtc_state->hw.enable)
> +	if (!crtc_state->hw.enable || crtc_state->shared_dpll)
>  		return 0;
>  
>  	if (!i915->dpll_funcs->crtc_get_shared_dpll)

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 05/26] drm/i915: Extract PIPE_CONF_CHECK_TIMINGS()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Deduplicate the crtc_ timigns comparisons.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 45 ++++++++------------
 1 file changed, 18 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7d488d320762..e38d93beafdd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6073,6 +6073,21 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	} \
 } while (0)
 
+#define PIPE_CONF_CHECK_TIMINGS(name) do { \
+	PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
+	PIPE_CONF_CHECK_I(name.crtc_htotal); \
+	PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
+	PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
+	PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
+	PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
+	PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
+	PIPE_CONF_CHECK_I(name.crtc_vtotal); \
+	PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
+	PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
+	PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
+	PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
+} while (0)
+
 /* This is required for BDW+ where there is only one set of registers for
  * switching between high and low RR.
  * This macro can be used whenever a comparison has to be made between one
@@ -6190,33 +6205,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_I(framestart_delay);
 	PIPE_CONF_CHECK_I(msa_timing_delay);
 
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_start);
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_end);
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_start);
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_end);
-
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay);
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal);
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_start);
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_end);
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_start);
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_end);
-
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
-
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
+	PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
+	PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
 
 	PIPE_CONF_CHECK_I(pixel_multiplier);
 
@@ -6392,6 +6382,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 #undef PIPE_CONF_CHECK_FLAGS
 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
 #undef PIPE_CONF_CHECK_COLOR_LUT
+#undef PIPE_CONF_CHECK_TIMINGS
 #undef PIPE_CONF_QUIRK
 
 	return ret;
-- 
2.35.1

Re: [Intel-gfx] [PATCH 05/26] drm/i915: Extract PIPE_CONF_CHECK_TIMINGS()

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Deduplicate the crtc_ timigns comparisons.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 45 ++++++++------------
>  1 file changed, 18 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 7d488d320762..e38d93beafdd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6073,6 +6073,21 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	} \
>  } while (0)
>  
> +#define PIPE_CONF_CHECK_TIMINGS(name) do { \
> +	PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
> +	PIPE_CONF_CHECK_I(name.crtc_htotal); \
> +	PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
> +	PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
> +	PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
> +	PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
> +	PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
> +	PIPE_CONF_CHECK_I(name.crtc_vtotal); \
> +	PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
> +	PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
> +	PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
> +	PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
> +} while (0)
> +
>  /* This is required for BDW+ where there is only one set of registers for
>   * switching between high and low RR.
>   * This macro can be used whenever a comparison has to be made between one
> @@ -6190,33 +6205,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	PIPE_CONF_CHECK_I(framestart_delay);
>  	PIPE_CONF_CHECK_I(msa_timing_delay);
>  
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_start);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_end);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_start);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_end);
> -
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_start);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_end);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_start);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_end);
> -
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
> -
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
> +	PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
> +	PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
>  
>  	PIPE_CONF_CHECK_I(pixel_multiplier);
>  
> @@ -6392,6 +6382,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  #undef PIPE_CONF_CHECK_FLAGS
>  #undef PIPE_CONF_CHECK_CLOCK_FUZZY
>  #undef PIPE_CONF_CHECK_COLOR_LUT
> +#undef PIPE_CONF_CHECK_TIMINGS
>  #undef PIPE_CONF_QUIRK
>  
>  	return ret;

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 05/26] drm/i915: Extract PIPE_CONF_CHECK_TIMINGS()

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Deduplicate the crtc_ timigns comparisons.

*timings

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 45 ++++++++------------
>  1 file changed, 18 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 7d488d320762..e38d93beafdd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6073,6 +6073,21 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	} \
>  } while (0)
>  
> +#define PIPE_CONF_CHECK_TIMINGS(name) do { \
> +	PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
> +	PIPE_CONF_CHECK_I(name.crtc_htotal); \
> +	PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
> +	PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
> +	PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
> +	PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
> +	PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
> +	PIPE_CONF_CHECK_I(name.crtc_vtotal); \
> +	PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
> +	PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
> +	PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
> +	PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
> +} while (0)
> +
>  /* This is required for BDW+ where there is only one set of registers for
>   * switching between high and low RR.
>   * This macro can be used whenever a comparison has to be made between one
> @@ -6190,33 +6205,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	PIPE_CONF_CHECK_I(framestart_delay);
>  	PIPE_CONF_CHECK_I(msa_timing_delay);
>  
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_start);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_end);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_start);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_end);
> -
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_start);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_end);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_start);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_end);
> -
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
> -
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
> +	PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
> +	PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
>  
>  	PIPE_CONF_CHECK_I(pixel_multiplier);
>  
> @@ -6392,6 +6382,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  #undef PIPE_CONF_CHECK_FLAGS
>  #undef PIPE_CONF_CHECK_CLOCK_FUZZY
>  #undef PIPE_CONF_CHECK_COLOR_LUT
> +#undef PIPE_CONF_CHECK_TIMINGS
>  #undef PIPE_CONF_QUIRK
>  
>  	return ret;

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 06/26] drm/i915: Extract PIPE_CONF_CHECK_RECT()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Deduplicate the drm_rect comparisons.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e38d93beafdd..1093665122a4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6088,6 +6088,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
 } while (0)
 
+#define PIPE_CONF_CHECK_RECT(name) do { \
+	PIPE_CONF_CHECK_I(name.x1); \
+	PIPE_CONF_CHECK_I(name.x2); \
+	PIPE_CONF_CHECK_I(name.y1); \
+	PIPE_CONF_CHECK_I(name.y2); \
+} while (0)
+
 /* This is required for BDW+ where there is only one set of registers for
  * switching between high and low RR.
  * This macro can be used whenever a comparison has to be made between one
@@ -6250,18 +6257,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
 
 	if (!fastset) {
-		PIPE_CONF_CHECK_I(pipe_src.x1);
-		PIPE_CONF_CHECK_I(pipe_src.y1);
-		PIPE_CONF_CHECK_I(pipe_src.x2);
-		PIPE_CONF_CHECK_I(pipe_src.y2);
+		PIPE_CONF_CHECK_RECT(pipe_src);
 
 		PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
-		if (current_config->pch_pfit.enabled) {
-			PIPE_CONF_CHECK_I(pch_pfit.dst.x1);
-			PIPE_CONF_CHECK_I(pch_pfit.dst.y1);
-			PIPE_CONF_CHECK_I(pch_pfit.dst.x2);
-			PIPE_CONF_CHECK_I(pch_pfit.dst.y2);
-		}
+		PIPE_CONF_CHECK_RECT(pch_pfit.dst);
 
 		PIPE_CONF_CHECK_I(scaler_state.scaler_id);
 		PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
@@ -6383,6 +6382,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
 #undef PIPE_CONF_CHECK_COLOR_LUT
 #undef PIPE_CONF_CHECK_TIMINGS
+#undef PIPE_CONF_CHECK_RECT
 #undef PIPE_CONF_QUIRK
 
 	return ret;
-- 
2.35.1

Re: [Intel-gfx] [PATCH 06/26] drm/i915: Extract PIPE_CONF_CHECK_RECT()

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Deduplicate the drm_rect comparisons.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 20 ++++++++++----------
>  1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index e38d93beafdd..1093665122a4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6088,6 +6088,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
>  } while (0)
>  
> +#define PIPE_CONF_CHECK_RECT(name) do { \
> +	PIPE_CONF_CHECK_I(name.x1); \
> +	PIPE_CONF_CHECK_I(name.x2); \
> +	PIPE_CONF_CHECK_I(name.y1); \
> +	PIPE_CONF_CHECK_I(name.y2); \
> +} while (0)
> +
>  /* This is required for BDW+ where there is only one set of registers for
>   * switching between high and low RR.
>   * This macro can be used whenever a comparison has to be made between one
> @@ -6250,18 +6257,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
>  
>  	if (!fastset) {
> -		PIPE_CONF_CHECK_I(pipe_src.x1);
> -		PIPE_CONF_CHECK_I(pipe_src.y1);
> -		PIPE_CONF_CHECK_I(pipe_src.x2);
> -		PIPE_CONF_CHECK_I(pipe_src.y2);
> +		PIPE_CONF_CHECK_RECT(pipe_src);
>  
>  		PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
> -		if (current_config->pch_pfit.enabled) {

Dropping the if is not what it says on the box. I guess it should be
fine though since we only populate the values if pfit is enabled
AFAICT. (Maybe this is what we should do in general to ensure we're not
reading stuff to state when some feature isn't enabled?)

With the commit message amended,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> -			PIPE_CONF_CHECK_I(pch_pfit.dst.x1);
> -			PIPE_CONF_CHECK_I(pch_pfit.dst.y1);
> -			PIPE_CONF_CHECK_I(pch_pfit.dst.x2);
> -			PIPE_CONF_CHECK_I(pch_pfit.dst.y2);
> -		}
> +		PIPE_CONF_CHECK_RECT(pch_pfit.dst);
>  
>  		PIPE_CONF_CHECK_I(scaler_state.scaler_id);
>  		PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
> @@ -6383,6 +6382,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  #undef PIPE_CONF_CHECK_CLOCK_FUZZY
>  #undef PIPE_CONF_CHECK_COLOR_LUT
>  #undef PIPE_CONF_CHECK_TIMINGS
> +#undef PIPE_CONF_CHECK_RECT
>  #undef PIPE_CONF_QUIRK
>  
>  	return ret;

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 07/26] drm/i915: Adjust intel_modeset_pipe_config() & co. calling convention

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use the state+crtc calling convention for intel_modeset_pipe_config()
and othere related functions. Many of these need the full atomic state
anyway so passing it all the way through is just nicer than having to
worry about whether it can actually be extracted from eg. the crtc
state passed in.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 48 ++++++++++----------
 1 file changed, 25 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1093665122a4..4615cf3564eb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2811,9 +2811,11 @@ static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
 	return 0;
 }
 
-static int intel_crtc_compute_config(struct intel_crtc *crtc,
-				     struct intel_crtc_state *crtc_state)
+static int intel_crtc_compute_config(struct intel_atomic_state *state,
+				     struct intel_crtc *crtc)
 {
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
 	int ret;
 
 	ret = intel_crtc_compute_pipe_src(crtc_state);
@@ -5052,11 +5054,12 @@ compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
 }
 
 static int
-compute_baseline_pipe_bpp(struct intel_crtc *crtc,
-			  struct intel_crtc_state *pipe_config)
+compute_baseline_pipe_bpp(struct intel_atomic_state *state,
+			  struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	struct drm_atomic_state *state = pipe_config->uapi.state;
+	struct intel_crtc_state *pipe_config =
+		intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_connector *connector;
 	struct drm_connector_state *connector_state;
 	int bpp, i;
@@ -5072,7 +5075,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
 	pipe_config->pipe_bpp = bpp;
 
 	/* Clamp display bpp to connector max bpp */
-	for_each_new_connector_in_state(state, connector, connector_state, i) {
+	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
 		int ret;
 
 		if (connector_state->crtc != &crtc->base)
@@ -5632,18 +5635,18 @@ intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
 
 static int
 intel_modeset_pipe_config(struct intel_atomic_state *state,
-			  struct intel_crtc_state *pipe_config)
+			  struct intel_crtc *crtc)
 {
-	struct drm_crtc *crtc = pipe_config->uapi.crtc;
-	struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	struct intel_crtc_state *pipe_config =
+		intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_connector *connector;
 	struct drm_connector_state *connector_state;
 	int pipe_src_w, pipe_src_h;
 	int base_bpp, ret, i;
 	bool retry = true;
 
-	pipe_config->cpu_transcoder =
-		(enum transcoder) to_intel_crtc(crtc)->pipe;
+	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
 
 	pipe_config->framestart_delay = 1;
 
@@ -5660,8 +5663,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 	      (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
 		pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
 
-	ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
-					pipe_config);
+	ret = compute_baseline_pipe_bpp(state, crtc);
 	if (ret)
 		return ret;
 
@@ -5684,10 +5686,10 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 		struct intel_encoder *encoder =
 			to_intel_encoder(connector_state->best_encoder);
 
-		if (connector_state->crtc != crtc)
+		if (connector_state->crtc != &crtc->base)
 			continue;
 
-		if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
+		if (!check_single_encoder_cloning(state, crtc, encoder)) {
 			drm_dbg_kms(&i915->drm,
 				    "rejecting invalid cloning configuration\n");
 			return -EINVAL;
@@ -5722,7 +5724,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 		struct intel_encoder *encoder =
 			to_intel_encoder(connector_state->best_encoder);
 
-		if (connector_state->crtc != crtc)
+		if (connector_state->crtc != &crtc->base)
 			continue;
 
 		ret = encoder->compute_config(encoder, pipe_config,
@@ -5741,7 +5743,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 		pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
 			* pipe_config->pixel_multiplier;
 
-	ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
+	ret = intel_crtc_compute_config(state, crtc);
 	if (ret == -EDEADLK)
 		return ret;
 	if (ret == -EAGAIN) {
@@ -5772,11 +5774,11 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 }
 
 static int
-intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state)
+intel_modeset_pipe_config_late(struct intel_atomic_state *state,
+			       struct intel_crtc *crtc)
 {
-	struct intel_atomic_state *state =
-		to_intel_atomic_state(crtc_state->uapi.state);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_connector_state *conn_state;
 	struct drm_connector *connector;
 	int i;
@@ -7705,7 +7707,7 @@ static int intel_atomic_check(struct drm_device *dev,
 		if (!new_crtc_state->hw.enable)
 			continue;
 
-		ret = intel_modeset_pipe_config(state, new_crtc_state);
+		ret = intel_modeset_pipe_config(state, crtc);
 		if (ret)
 			goto fail;
 
@@ -7719,7 +7721,7 @@ static int intel_atomic_check(struct drm_device *dev,
 		if (!intel_crtc_needs_modeset(new_crtc_state))
 			continue;
 
-		ret = intel_modeset_pipe_config_late(new_crtc_state);
+		ret = intel_modeset_pipe_config_late(state, crtc);
 		if (ret)
 			goto fail;
 
-- 
2.35.1

Re: [Intel-gfx] [PATCH 07/26] drm/i915: Adjust intel_modeset_pipe_config() & co. calling convention

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use the state+crtc calling convention for intel_modeset_pipe_config()
> and othere related functions. Many of these need the full atomic state
> anyway so passing it all the way through is just nicer than having to
> worry about whether it can actually be extracted from eg. the crtc
> state passed in.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 48 ++++++++++----------
>  1 file changed, 25 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 1093665122a4..4615cf3564eb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2811,9 +2811,11 @@ static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
>  	return 0;
>  }
>  
> -static int intel_crtc_compute_config(struct intel_crtc *crtc,
> -				     struct intel_crtc_state *crtc_state)
> +static int intel_crtc_compute_config(struct intel_atomic_state *state,
> +				     struct intel_crtc *crtc)
>  {
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
>  	int ret;
>  
>  	ret = intel_crtc_compute_pipe_src(crtc_state);
> @@ -5052,11 +5054,12 @@ compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
>  }
>  
>  static int
> -compute_baseline_pipe_bpp(struct intel_crtc *crtc,
> -			  struct intel_crtc_state *pipe_config)
> +compute_baseline_pipe_bpp(struct intel_atomic_state *state,
> +			  struct intel_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	struct drm_atomic_state *state = pipe_config->uapi.state;
> +	struct intel_crtc_state *pipe_config =
> +		intel_atomic_get_new_crtc_state(state, crtc);
>  	struct drm_connector *connector;
>  	struct drm_connector_state *connector_state;
>  	int bpp, i;
> @@ -5072,7 +5075,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
>  	pipe_config->pipe_bpp = bpp;
>  
>  	/* Clamp display bpp to connector max bpp */
> -	for_each_new_connector_in_state(state, connector, connector_state, i) {
> +	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
>  		int ret;
>  
>  		if (connector_state->crtc != &crtc->base)
> @@ -5632,18 +5635,18 @@ intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
>  
>  static int
>  intel_modeset_pipe_config(struct intel_atomic_state *state,
> -			  struct intel_crtc_state *pipe_config)
> +			  struct intel_crtc *crtc)
>  {
> -	struct drm_crtc *crtc = pipe_config->uapi.crtc;
> -	struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +	struct intel_crtc_state *pipe_config =
> +		intel_atomic_get_new_crtc_state(state, crtc);
>  	struct drm_connector *connector;
>  	struct drm_connector_state *connector_state;
>  	int pipe_src_w, pipe_src_h;
>  	int base_bpp, ret, i;
>  	bool retry = true;
>  
> -	pipe_config->cpu_transcoder =
> -		(enum transcoder) to_intel_crtc(crtc)->pipe;
> +	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
>  
>  	pipe_config->framestart_delay = 1;
>  
> @@ -5660,8 +5663,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
>  	      (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
>  		pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
>  
> -	ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
> -					pipe_config);
> +	ret = compute_baseline_pipe_bpp(state, crtc);
>  	if (ret)
>  		return ret;
>  
> @@ -5684,10 +5686,10 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
>  		struct intel_encoder *encoder =
>  			to_intel_encoder(connector_state->best_encoder);
>  
> -		if (connector_state->crtc != crtc)
> +		if (connector_state->crtc != &crtc->base)
>  			continue;
>  
> -		if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
> +		if (!check_single_encoder_cloning(state, crtc, encoder)) {
>  			drm_dbg_kms(&i915->drm,
>  				    "rejecting invalid cloning configuration\n");
>  			return -EINVAL;
> @@ -5722,7 +5724,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
>  		struct intel_encoder *encoder =
>  			to_intel_encoder(connector_state->best_encoder);
>  
> -		if (connector_state->crtc != crtc)
> +		if (connector_state->crtc != &crtc->base)
>  			continue;
>  
>  		ret = encoder->compute_config(encoder, pipe_config,
> @@ -5741,7 +5743,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
>  		pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
>  			* pipe_config->pixel_multiplier;
>  
> -	ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
> +	ret = intel_crtc_compute_config(state, crtc);
>  	if (ret == -EDEADLK)
>  		return ret;
>  	if (ret == -EAGAIN) {
> @@ -5772,11 +5774,11 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
>  }
>  
>  static int
> -intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state)
> +intel_modeset_pipe_config_late(struct intel_atomic_state *state,
> +			       struct intel_crtc *crtc)
>  {
> -	struct intel_atomic_state *state =
> -		to_intel_atomic_state(crtc_state->uapi.state);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
>  	struct drm_connector_state *conn_state;
>  	struct drm_connector *connector;
>  	int i;
> @@ -7705,7 +7707,7 @@ static int intel_atomic_check(struct drm_device *dev,
>  		if (!new_crtc_state->hw.enable)
>  			continue;
>  
> -		ret = intel_modeset_pipe_config(state, new_crtc_state);
> +		ret = intel_modeset_pipe_config(state, crtc);
>  		if (ret)
>  			goto fail;
>  
> @@ -7719,7 +7721,7 @@ static int intel_atomic_check(struct drm_device *dev,
>  		if (!intel_crtc_needs_modeset(new_crtc_state))
>  			continue;
>  
> -		ret = intel_modeset_pipe_config_late(new_crtc_state);
> +		ret = intel_modeset_pipe_config_late(state, crtc);
>  		if (ret)
>  			goto fail;

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 08/26] drm/i915: s/pipe_config/crtc_state/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Rename some of the 'pipe_config's to the more modern
'crtc_state'.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 62 ++++++++++----------
 1 file changed, 31 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4615cf3564eb..ac476976dc0b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5013,10 +5013,10 @@ static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
 
 static int
 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
-		      struct intel_crtc_state *pipe_config)
+		      struct intel_crtc_state *crtc_state)
 {
 	struct drm_connector *connector = conn_state->connector;
-	struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
+	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 	const struct drm_display_info *info = &connector->display_info;
 	int bpp;
 
@@ -5038,16 +5038,16 @@ compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
 		return -EINVAL;
 	}
 
-	if (bpp < pipe_config->pipe_bpp) {
+	if (bpp < crtc_state->pipe_bpp) {
 		drm_dbg_kms(&i915->drm,
 			    "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
 			    "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
 			    connector->base.id, connector->name,
 			    bpp, 3 * info->bpc,
 			    3 * conn_state->max_requested_bpc,
-			    pipe_config->pipe_bpp);
+			    crtc_state->pipe_bpp);
 
-		pipe_config->pipe_bpp = bpp;
+		crtc_state->pipe_bpp = bpp;
 	}
 
 	return 0;
@@ -5058,7 +5058,7 @@ compute_baseline_pipe_bpp(struct intel_atomic_state *state,
 			  struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	struct intel_crtc_state *pipe_config =
+	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_connector *connector;
 	struct drm_connector_state *connector_state;
@@ -5072,7 +5072,7 @@ compute_baseline_pipe_bpp(struct intel_atomic_state *state,
 	else
 		bpp = 8*3;
 
-	pipe_config->pipe_bpp = bpp;
+	crtc_state->pipe_bpp = bpp;
 
 	/* Clamp display bpp to connector max bpp */
 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
@@ -5081,7 +5081,7 @@ compute_baseline_pipe_bpp(struct intel_atomic_state *state,
 		if (connector_state->crtc != &crtc->base)
 			continue;
 
-		ret = compute_sink_pipe_bpp(connector_state, pipe_config);
+		ret = compute_sink_pipe_bpp(connector_state, crtc_state);
 		if (ret)
 			return ret;
 	}
@@ -5638,7 +5638,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 			  struct intel_crtc *crtc)
 {
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
-	struct intel_crtc_state *pipe_config =
+	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_connector *connector;
 	struct drm_connector_state *connector_state;
@@ -5646,28 +5646,28 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 	int base_bpp, ret, i;
 	bool retry = true;
 
-	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
+	crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
 
-	pipe_config->framestart_delay = 1;
+	crtc_state->framestart_delay = 1;
 
 	/*
 	 * Sanitize sync polarity flags based on requested ones. If neither
 	 * positive or negative polarity is requested, treat this as meaning
 	 * negative polarity.
 	 */
-	if (!(pipe_config->hw.adjusted_mode.flags &
+	if (!(crtc_state->hw.adjusted_mode.flags &
 	      (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
-		pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
+		crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
 
-	if (!(pipe_config->hw.adjusted_mode.flags &
+	if (!(crtc_state->hw.adjusted_mode.flags &
 	      (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
-		pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
+		crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
 
 	ret = compute_baseline_pipe_bpp(state, crtc);
 	if (ret)
 		return ret;
 
-	base_bpp = pipe_config->pipe_bpp;
+	base_bpp = crtc_state->pipe_bpp;
 
 	/*
 	 * Determine the real pipe dimensions. Note that stereo modes can
@@ -5677,9 +5677,9 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 	 * computation to clearly distinguish it from the adjusted mode, which
 	 * can be changed by the connectors in the below retry loop.
 	 */
-	drm_mode_get_hv_timing(&pipe_config->hw.mode,
+	drm_mode_get_hv_timing(&crtc_state->hw.mode,
 			       &pipe_src_w, &pipe_src_h);
-	drm_rect_init(&pipe_config->pipe_src, 0, 0,
+	drm_rect_init(&crtc_state->pipe_src, 0, 0,
 		      pipe_src_w, pipe_src_h);
 
 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
@@ -5700,20 +5700,20 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 		 * hooks so that the hooks can use this information safely.
 		 */
 		if (encoder->compute_output_type)
-			pipe_config->output_types |=
-				BIT(encoder->compute_output_type(encoder, pipe_config,
+			crtc_state->output_types |=
+				BIT(encoder->compute_output_type(encoder, crtc_state,
 								 connector_state));
 		else
-			pipe_config->output_types |= BIT(encoder->type);
+			crtc_state->output_types |= BIT(encoder->type);
 	}
 
 encoder_retry:
 	/* Ensure the port clock defaults are reset when retrying. */
-	pipe_config->port_clock = 0;
-	pipe_config->pixel_multiplier = 1;
+	crtc_state->port_clock = 0;
+	crtc_state->pixel_multiplier = 1;
 
 	/* Fill in default crtc timings, allow encoders to overwrite them. */
-	drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
+	drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,
 			      CRTC_STEREO_DOUBLE);
 
 	/* Pass our mode to the connectors and the CRTC to give them a chance to
@@ -5727,7 +5727,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 		if (connector_state->crtc != &crtc->base)
 			continue;
 
-		ret = encoder->compute_config(encoder, pipe_config,
+		ret = encoder->compute_config(encoder, crtc_state,
 					      connector_state);
 		if (ret == -EDEADLK)
 			return ret;
@@ -5739,9 +5739,9 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 
 	/* Set default port clock if not overwritten by the encoder. Needs to be
 	 * done afterwards in case the encoder adjusts the mode. */
-	if (!pipe_config->port_clock)
-		pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
-			* pipe_config->pixel_multiplier;
+	if (!crtc_state->port_clock)
+		crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock
+			* crtc_state->pixel_multiplier;
 
 	ret = intel_crtc_compute_config(state, crtc);
 	if (ret == -EDEADLK)
@@ -5764,11 +5764,11 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 	 * only enable it on 6bpc panels and when its not a compliance
 	 * test requesting 6bpc video pattern.
 	 */
-	pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
-		!pipe_config->dither_force_disable;
+	crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
+		!crtc_state->dither_force_disable;
 	drm_dbg_kms(&i915->drm,
 		    "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
-		    base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
+		    base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
 
 	return 0;
 }
-- 
2.35.1

Re: [Intel-gfx] [PATCH 08/26] drm/i915: s/pipe_config/crtc_state/

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rename some of the 'pipe_config's to the more modern
> 'crtc_state'.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 62 ++++++++++----------
>  1 file changed, 31 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 4615cf3564eb..ac476976dc0b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5013,10 +5013,10 @@ static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
>  
>  static int
>  compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
> -		      struct intel_crtc_state *pipe_config)
> +		      struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_connector *connector = conn_state->connector;
> -	struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
> +	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>  	const struct drm_display_info *info = &connector->display_info;
>  	int bpp;
>  
> @@ -5038,16 +5038,16 @@ compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
>  		return -EINVAL;
>  	}
>  
> -	if (bpp < pipe_config->pipe_bpp) {
> +	if (bpp < crtc_state->pipe_bpp) {
>  		drm_dbg_kms(&i915->drm,
>  			    "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
>  			    "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
>  			    connector->base.id, connector->name,
>  			    bpp, 3 * info->bpc,
>  			    3 * conn_state->max_requested_bpc,
> -			    pipe_config->pipe_bpp);
> +			    crtc_state->pipe_bpp);
>  
> -		pipe_config->pipe_bpp = bpp;
> +		crtc_state->pipe_bpp = bpp;
>  	}
>  
>  	return 0;
> @@ -5058,7 +5058,7 @@ compute_baseline_pipe_bpp(struct intel_atomic_state *state,
>  			  struct intel_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	struct intel_crtc_state *pipe_config =
> +	struct intel_crtc_state *crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	struct drm_connector *connector;
>  	struct drm_connector_state *connector_state;
> @@ -5072,7 +5072,7 @@ compute_baseline_pipe_bpp(struct intel_atomic_state *state,
>  	else
>  		bpp = 8*3;
>  
> -	pipe_config->pipe_bpp = bpp;
> +	crtc_state->pipe_bpp = bpp;
>  
>  	/* Clamp display bpp to connector max bpp */
>  	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
> @@ -5081,7 +5081,7 @@ compute_baseline_pipe_bpp(struct intel_atomic_state *state,
>  		if (connector_state->crtc != &crtc->base)
>  			continue;
>  
> -		ret = compute_sink_pipe_bpp(connector_state, pipe_config);
> +		ret = compute_sink_pipe_bpp(connector_state, crtc_state);
>  		if (ret)
>  			return ret;
>  	}
> @@ -5638,7 +5638,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
>  			  struct intel_crtc *crtc)
>  {
>  	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> -	struct intel_crtc_state *pipe_config =
> +	struct intel_crtc_state *crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	struct drm_connector *connector;
>  	struct drm_connector_state *connector_state;
> @@ -5646,28 +5646,28 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
>  	int base_bpp, ret, i;
>  	bool retry = true;
>  
> -	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
> +	crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
>  
> -	pipe_config->framestart_delay = 1;
> +	crtc_state->framestart_delay = 1;
>  
>  	/*
>  	 * Sanitize sync polarity flags based on requested ones. If neither
>  	 * positive or negative polarity is requested, treat this as meaning
>  	 * negative polarity.
>  	 */
> -	if (!(pipe_config->hw.adjusted_mode.flags &
> +	if (!(crtc_state->hw.adjusted_mode.flags &
>  	      (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
> -		pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
> +		crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
>  
> -	if (!(pipe_config->hw.adjusted_mode.flags &
> +	if (!(crtc_state->hw.adjusted_mode.flags &
>  	      (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
> -		pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
> +		crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
>  
>  	ret = compute_baseline_pipe_bpp(state, crtc);
>  	if (ret)
>  		return ret;
>  
> -	base_bpp = pipe_config->pipe_bpp;
> +	base_bpp = crtc_state->pipe_bpp;
>  
>  	/*
>  	 * Determine the real pipe dimensions. Note that stereo modes can
> @@ -5677,9 +5677,9 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
>  	 * computation to clearly distinguish it from the adjusted mode, which
>  	 * can be changed by the connectors in the below retry loop.
>  	 */
> -	drm_mode_get_hv_timing(&pipe_config->hw.mode,
> +	drm_mode_get_hv_timing(&crtc_state->hw.mode,
>  			       &pipe_src_w, &pipe_src_h);
> -	drm_rect_init(&pipe_config->pipe_src, 0, 0,
> +	drm_rect_init(&crtc_state->pipe_src, 0, 0,
>  		      pipe_src_w, pipe_src_h);
>  
>  	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
> @@ -5700,20 +5700,20 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
>  		 * hooks so that the hooks can use this information safely.
>  		 */
>  		if (encoder->compute_output_type)
> -			pipe_config->output_types |=
> -				BIT(encoder->compute_output_type(encoder, pipe_config,
> +			crtc_state->output_types |=
> +				BIT(encoder->compute_output_type(encoder, crtc_state,
>  								 connector_state));
>  		else
> -			pipe_config->output_types |= BIT(encoder->type);
> +			crtc_state->output_types |= BIT(encoder->type);
>  	}
>  
>  encoder_retry:
>  	/* Ensure the port clock defaults are reset when retrying. */
> -	pipe_config->port_clock = 0;
> -	pipe_config->pixel_multiplier = 1;
> +	crtc_state->port_clock = 0;
> +	crtc_state->pixel_multiplier = 1;
>  
>  	/* Fill in default crtc timings, allow encoders to overwrite them. */
> -	drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
> +	drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,
>  			      CRTC_STEREO_DOUBLE);
>  
>  	/* Pass our mode to the connectors and the CRTC to give them a chance to
> @@ -5727,7 +5727,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
>  		if (connector_state->crtc != &crtc->base)
>  			continue;
>  
> -		ret = encoder->compute_config(encoder, pipe_config,
> +		ret = encoder->compute_config(encoder, crtc_state,
>  					      connector_state);
>  		if (ret == -EDEADLK)
>  			return ret;
> @@ -5739,9 +5739,9 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
>  
>  	/* Set default port clock if not overwritten by the encoder. Needs to be
>  	 * done afterwards in case the encoder adjusts the mode. */
> -	if (!pipe_config->port_clock)
> -		pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
> -			* pipe_config->pixel_multiplier;
> +	if (!crtc_state->port_clock)
> +		crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock
> +			* crtc_state->pixel_multiplier;
>  
>  	ret = intel_crtc_compute_config(state, crtc);
>  	if (ret == -EDEADLK)
> @@ -5764,11 +5764,11 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
>  	 * only enable it on 6bpc panels and when its not a compliance
>  	 * test requesting 6bpc video pattern.
>  	 */
> -	pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
> -		!pipe_config->dither_force_disable;
> +	crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
> +		!crtc_state->dither_force_disable;
>  	drm_dbg_kms(&i915->drm,
>  		    "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
> -		    base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
> +		    base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
>  
>  	return 0;
>  }

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 09/26] drm/i915: Improve modeset debugs

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use the "[CRTC:%d:%s]'/etc. format for some of the modeset debugs
so we know more about what has happened during the modeset state
computation.

Also tweak the connector bpp debug message a bit to make it less
confusing.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 22 +++++++++++++-------
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ac476976dc0b..8d6cbfbaf20d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5040,8 +5040,8 @@ compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
 
 	if (bpp < crtc_state->pipe_bpp) {
 		drm_dbg_kms(&i915->drm,
-			    "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
-			    "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
+			    "[CONNECTOR:%d:%s] Limiting display bpp to %d "
+			    "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n",
 			    connector->base.id, connector->name,
 			    bpp, 3 * info->bpc,
 			    3 * conn_state->max_requested_bpc,
@@ -5691,7 +5691,8 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 
 		if (!check_single_encoder_cloning(state, crtc, encoder)) {
 			drm_dbg_kms(&i915->drm,
-				    "rejecting invalid cloning configuration\n");
+				    "[ENCODER:%d:%s] rejecting invalid cloning configuration\n",
+				    encoder->base.base.id, encoder->base.name);
 			return -EINVAL;
 		}
 
@@ -5732,7 +5733,8 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 		if (ret == -EDEADLK)
 			return ret;
 		if (ret < 0) {
-			drm_dbg_kms(&i915->drm, "Encoder config failure: %d\n", ret);
+			drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n",
+				    encoder->base.base.id, encoder->base.name, ret);
 			return ret;
 		}
 	}
@@ -5748,15 +5750,18 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 		return ret;
 	if (ret == -EAGAIN) {
 		if (drm_WARN(&i915->drm, !retry,
-			     "loop in pipe configuration computation\n"))
+			     "[CRTC:%d:%s] loop in pipe configuration computation\n",
+			     crtc->base.base.id, crtc->base.name))
 			return -EINVAL;
 
-		drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n");
+		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n",
+			    crtc->base.base.id, crtc->base.name);
 		retry = false;
 		goto encoder_retry;
 	}
 	if (ret < 0) {
-		drm_dbg_kms(&i915->drm, "CRTC config failure: %d\n", ret);
+		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",
+			    crtc->base.base.id, crtc->base.name, ret);
 		return ret;
 	}
 
@@ -5767,7 +5772,8 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 	crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
 		!crtc_state->dither_force_disable;
 	drm_dbg_kms(&i915->drm,
-		    "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
+		    "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
+		    crtc->base.base.id, crtc->base.name,
 		    base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
 
 	return 0;
-- 
2.35.1

Re: [Intel-gfx] [PATCH 09/26] drm/i915: Improve modeset debugs

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use the "[CRTC:%d:%s]'/etc. format for some of the modeset debugs
> so we know more about what has happened during the modeset state
> computation.
>
> Also tweak the connector bpp debug message a bit to make it less
> confusing.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 22 +++++++++++++-------
>  1 file changed, 14 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ac476976dc0b..8d6cbfbaf20d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5040,8 +5040,8 @@ compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
>  
>  	if (bpp < crtc_state->pipe_bpp) {
>  		drm_dbg_kms(&i915->drm,
> -			    "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
> -			    "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
> +			    "[CONNECTOR:%d:%s] Limiting display bpp to %d "
> +			    "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n",
>  			    connector->base.id, connector->name,
>  			    bpp, 3 * info->bpc,
>  			    3 * conn_state->max_requested_bpc,
> @@ -5691,7 +5691,8 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
>  
>  		if (!check_single_encoder_cloning(state, crtc, encoder)) {
>  			drm_dbg_kms(&i915->drm,
> -				    "rejecting invalid cloning configuration\n");
> +				    "[ENCODER:%d:%s] rejecting invalid cloning configuration\n",
> +				    encoder->base.base.id, encoder->base.name);
>  			return -EINVAL;
>  		}
>  
> @@ -5732,7 +5733,8 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
>  		if (ret == -EDEADLK)
>  			return ret;
>  		if (ret < 0) {
> -			drm_dbg_kms(&i915->drm, "Encoder config failure: %d\n", ret);
> +			drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n",
> +				    encoder->base.base.id, encoder->base.name, ret);
>  			return ret;
>  		}
>  	}
> @@ -5748,15 +5750,18 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
>  		return ret;
>  	if (ret == -EAGAIN) {
>  		if (drm_WARN(&i915->drm, !retry,
> -			     "loop in pipe configuration computation\n"))
> +			     "[CRTC:%d:%s] loop in pipe configuration computation\n",
> +			     crtc->base.base.id, crtc->base.name))
>  			return -EINVAL;
>  
> -		drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n");
> +		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n",
> +			    crtc->base.base.id, crtc->base.name);
>  		retry = false;
>  		goto encoder_retry;
>  	}
>  	if (ret < 0) {
> -		drm_dbg_kms(&i915->drm, "CRTC config failure: %d\n", ret);
> +		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",
> +			    crtc->base.base.id, crtc->base.name, ret);
>  		return ret;
>  	}
>  
> @@ -5767,7 +5772,8 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
>  	crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
>  		!crtc_state->dither_force_disable;
>  	drm_dbg_kms(&i915->drm,
> -		    "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
> +		    "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
> +		    crtc->base.base.id, crtc->base.name,
>  		    base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
>  
>  	return 0;

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 10/26] drm/i915: Extract intel_crtc_dotclock()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract intel_crtc_dotclock() from ddi_dotclock_get(). We'll reuse
this during state computation in order to determine the actual final
dotclcok after the DPLL computation has been done (which may not give
us the exact same port_clock that we fed in).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9e6fa59eabba..0cf2d4fba6a8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -322,14 +322,10 @@ static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
 	}
 }
 
-static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
+int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
 {
 	int dotclock;
 
-	/* CRT dotclock is determined via other means */
-	if (pipe_config->has_pch_encoder)
-		return;
-
 	if (intel_crtc_has_dp_encoder(pipe_config))
 		dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 						    &pipe_config->dp_m_n);
@@ -345,7 +341,17 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
 	if (pipe_config->pixel_multiplier)
 		dotclock /= pipe_config->pixel_multiplier;
 
-	pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
+	return dotclock;
+}
+
+static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
+{
+	/* CRT dotclock is determined via other means */
+	if (pipe_config->has_pch_encoder)
+		return;
+
+	pipe_config->hw.adjusted_mode.crtc_clock =
+		intel_crtc_dotclock(pipe_config);
 }
 
 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
-- 
2.35.1

Re: [Intel-gfx] [PATCH 10/26] drm/i915: Extract intel_crtc_dotclock()

[kernel test robot]

Hi Ville,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20220503]
[cannot apply to v5.18-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/intel-lab-lkp/linux/commits/Ville-Syrjala/drm-i915-Make-fastset-not-suck-and-allow-seamless-M-N-changes/20220504-022619
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-a004 (https://download.01.org/0day-ci/archive/20220504/202205041054.2CCCG4hP-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 363b3a645a1e30011cc8da624f13dac5fd915628)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/a7c24aec0d5727b1e827ab8c847aa42188d199f2
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Ville-Syrjala/drm-i915-Make-fastset-not-suck-and-allow-seamless-M-N-changes/20220504-022619
        git checkout a7c24aec0d5727b1e827ab8c847aa42188d199f2
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/display/intel_ddi.c:325:5: warning: no previous prototype for function 'intel_crtc_dotclock' [-Wmissing-prototypes]
   int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
       ^
   drivers/gpu/drm/i915/display/intel_ddi.c:325:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
   int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
   ^
   static 
   1 warning generated.


vim +/intel_crtc_dotclock +325 drivers/gpu/drm/i915/display/intel_ddi.c

   324	
 > 325	int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
   326	{
   327		int dotclock;
   328	
   329		if (intel_crtc_has_dp_encoder(pipe_config))
   330			dotclock = intel_dotclock_calculate(pipe_config->port_clock,
   331							    &pipe_config->dp_m_n);
   332		else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
   333			dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
   334		else
   335			dotclock = pipe_config->port_clock;
   336	
   337		if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
   338		    !intel_crtc_has_dp_encoder(pipe_config))
   339			dotclock *= 2;
   340	
   341		if (pipe_config->pixel_multiplier)
   342			dotclock /= pipe_config->pixel_multiplier;
   343	
   344		return dotclock;
   345	}
   346	

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp

[Intel-gfx] [PATCH v2 10/26] drm/i915: Extract intel_crtc_dotclock()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract intel_crtc_dotclock() from ddi_dotclock_get(). We'll reuse
this during state computation in order to determine the actual final
dotclcok after the DPLL computation has been done (which may not give
us the exact same port_clock that we fed in).

v2: Add the prototype

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c     | 18 ++++++++++++------
 drivers/gpu/drm/i915/display/intel_display.h |  1 +
 2 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9e6fa59eabba..0cf2d4fba6a8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -322,14 +322,10 @@ static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
 	}
 }
 
-static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
+int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
 {
 	int dotclock;
 
-	/* CRT dotclock is determined via other means */
-	if (pipe_config->has_pch_encoder)
-		return;
-
 	if (intel_crtc_has_dp_encoder(pipe_config))
 		dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 						    &pipe_config->dp_m_n);
@@ -345,7 +341,17 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
 	if (pipe_config->pixel_multiplier)
 		dotclock /= pipe_config->pixel_multiplier;
 
-	pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
+	return dotclock;
+}
+
+static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
+{
+	/* CRT dotclock is determined via other means */
+	if (pipe_config->has_pch_encoder)
+		return;
+
+	pipe_config->hw.adjusted_mode.crtc_clock =
+		intel_crtc_dotclock(pipe_config);
 }
 
 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 187910d94ec6..7af6b5a413dc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -635,6 +635,7 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
 void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 			 struct intel_crtc_state *pipe_config);
 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
+int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config);
 enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);
 enum intel_display_power_domain
 intel_aux_power_domain(struct intel_digital_port *dig_port);
-- 
2.35.1

Re: [Intel-gfx] [PATCH v2 10/26] drm/i915: Extract intel_crtc_dotclock()

[Jani Nikula]

On Wed, 04 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Extract intel_crtc_dotclock() from ddi_dotclock_get(). We'll reuse
> this during state computation in order to determine the actual final
> dotclcok after the DPLL computation has been done (which may not give
> us the exact same port_clock that we fed in).
>
> v2: Add the prototype
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Okay, seems like intel_crtc_dotclock() might be in the wrong place now,
but okay for now.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c     | 18 ++++++++++++------
>  drivers/gpu/drm/i915/display/intel_display.h |  1 +
>  2 files changed, 13 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 9e6fa59eabba..0cf2d4fba6a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -322,14 +322,10 @@ static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
>  	}
>  }
>  
> -static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
> +int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
>  {
>  	int dotclock;
>  
> -	/* CRT dotclock is determined via other means */
> -	if (pipe_config->has_pch_encoder)
> -		return;
> -
>  	if (intel_crtc_has_dp_encoder(pipe_config))
>  		dotclock = intel_dotclock_calculate(pipe_config->port_clock,
>  						    &pipe_config->dp_m_n);
> @@ -345,7 +341,17 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
>  	if (pipe_config->pixel_multiplier)
>  		dotclock /= pipe_config->pixel_multiplier;
>  
> -	pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
> +	return dotclock;
> +}
> +
> +static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
> +{
> +	/* CRT dotclock is determined via other means */
> +	if (pipe_config->has_pch_encoder)
> +		return;
> +
> +	pipe_config->hw.adjusted_mode.crtc_clock =
> +		intel_crtc_dotclock(pipe_config);
>  }
>  
>  void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 187910d94ec6..7af6b5a413dc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -635,6 +635,7 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
>  void i9xx_crtc_clock_get(struct intel_crtc *crtc,
>  			 struct intel_crtc_state *pipe_config);
>  int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
> +int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config);
>  enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);
>  enum intel_display_power_domain
>  intel_aux_power_domain(struct intel_digital_port *dig_port);

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 11/26] drm/i915: Introduce struct iclkip_params

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pull the various iCLKIP parameters into a struct. Later on
we'll reuse this during the state computation to determine
the exact dotclock the hardware will be generating for us.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_crt.c      |  1 +
 .../gpu/drm/i915/display/intel_pch_refclk.c   | 91 ++++++++++++-------
 2 files changed, 57 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 6a3893c8ff22..d746c85e7e8c 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -46,6 +46,7 @@
 #include "intel_gmbus.h"
 #include "intel_hotplug.h"
 #include "intel_pch_display.h"
+#include "intel_pch_refclk.h"
 
 /* Here's the desired hotplug mode */
 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |		\
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index b688fd87e3da..6610160cf825 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -122,16 +122,29 @@ void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
 	mutex_unlock(&dev_priv->sb_lock);
 }
 
-/* Program iCLKIP clock to the desired frequency */
-void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
+struct iclkip_params {
+	u32 iclk_virtual_root_freq;
+	u32 iclk_pi_range;
+	u32 divsel, phaseinc, auxdiv, phasedir, desired_divisor;
+};
+
+static void iclkip_params_init(struct iclkip_params *p)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
-	u32 divsel, phaseinc, auxdiv, phasedir = 0;
-	u32 temp;
+	memset(p, 0, sizeof(*p));
+
+	p->iclk_virtual_root_freq = 172800 * 1000;
+	p->iclk_pi_range = 64;
+}
 
-	lpt_disable_iclkip(dev_priv);
+static int lpt_iclkip_freq(struct iclkip_params *p)
+{
+	return DIV_ROUND_CLOSEST(p->iclk_virtual_root_freq,
+				 p->desired_divisor << p->auxdiv);
+}
+
+static void lpt_compute_iclkip(struct iclkip_params *p, int clock)
+{
+	iclkip_params_init(p);
 
 	/* The iCLK virtual clock root frequency is in MHz,
 	 * but the adjusted_mode->crtc_clock in KHz. To get the
@@ -139,50 +152,60 @@ void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
 	 * convert the virtual clock precision to KHz here for higher
 	 * precision.
 	 */
-	for (auxdiv = 0; auxdiv < 2; auxdiv++) {
-		u32 iclk_virtual_root_freq = 172800 * 1000;
-		u32 iclk_pi_range = 64;
-		u32 desired_divisor;
-
-		desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
-						    clock << auxdiv);
-		divsel = (desired_divisor / iclk_pi_range) - 2;
-		phaseinc = desired_divisor % iclk_pi_range;
+	for (p->auxdiv = 0; p->auxdiv < 2; p->auxdiv++) {
+		p->desired_divisor = DIV_ROUND_CLOSEST(p->iclk_virtual_root_freq,
+						       clock << p->auxdiv);
+		p->divsel = (p->desired_divisor / p->iclk_pi_range) - 2;
 
 		/*
 		 * Near 20MHz is a corner case which is
 		 * out of range for the 7-bit divisor
 		 */
-		if (divsel <= 0x7f)
+		if (p->divsel <= 0x7f)
 			break;
 	}
+}
+
+/* Program iCLKIP clock to the desired frequency */
+void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
+	struct iclkip_params p;
+	u32 temp;
+
+	lpt_disable_iclkip(dev_priv);
+
+	lpt_compute_iclkip(&p, clock);
+	drm_WARN_ON(&dev_priv->drm, lpt_iclkip_freq(&p) != clock);
 
 	/* This should not happen with any sane values */
-	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
+	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(p.divsel) &
 		    ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
-	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
+	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(p.phasedir) &
 		    ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
 
 	drm_dbg_kms(&dev_priv->drm,
 		    "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
-		    clock, auxdiv, divsel, phasedir, phaseinc);
+		    clock, p.auxdiv, p.divsel, p.phasedir, p.phaseinc);
 
 	mutex_lock(&dev_priv->sb_lock);
 
 	/* Program SSCDIVINTPHASE6 */
 	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
 	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
-	temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
+	temp |= SBI_SSCDIVINTPHASE_DIVSEL(p.divsel);
 	temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
-	temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
-	temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
+	temp |= SBI_SSCDIVINTPHASE_INCVAL(p.phaseinc);
+	temp |= SBI_SSCDIVINTPHASE_DIR(p.phasedir);
 	temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
 	intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
 
 	/* Program SSCAUXDIV */
 	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
 	temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
-	temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
+	temp |= SBI_SSCAUXDIV_FINALDIV2SEL(p.auxdiv);
 	intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
 
 	/* Enable modulator and associated divider */
@@ -200,15 +223,14 @@ void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
 
 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
 {
-	u32 divsel, phaseinc, auxdiv;
-	u32 iclk_virtual_root_freq = 172800 * 1000;
-	u32 iclk_pi_range = 64;
-	u32 desired_divisor;
+	struct iclkip_params p;
 	u32 temp;
 
 	if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
 		return 0;
 
+	iclkip_params_init(&p);
+
 	mutex_lock(&dev_priv->sb_lock);
 
 	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
@@ -218,21 +240,20 @@ int lpt_get_iclkip(struct drm_i915_private *dev_priv)
 	}
 
 	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
-	divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
+	p.divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
 		SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
-	phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
+	p.phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
 		SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
 
 	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
-	auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
+	p.auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
 		SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
 
 	mutex_unlock(&dev_priv->sb_lock);
 
-	desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
+	p.desired_divisor = (p.divsel + 2) * p.iclk_pi_range + p.phaseinc;
 
-	return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
-				 desired_divisor << auxdiv);
+	return lpt_iclkip_freq(&p);
 }
 
 /* Implements 3 different sequences from BSpec chapter "Display iCLK
-- 
2.35.1

[Intel-gfx] [PATCH v2 11/26] drm/i915: Introduce struct iclkip_params

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pull the various iCLKIP parameters into a struct. Later on
we'll reuse this during the state computation to determine
the exact dotclock the hardware will be generating for us.

v2: Don't lost the phaseinc calculation

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_crt.c      |  1 +
 .../gpu/drm/i915/display/intel_pch_refclk.c   | 92 ++++++++++++-------
 2 files changed, 58 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 6a3893c8ff22..d746c85e7e8c 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -46,6 +46,7 @@
 #include "intel_gmbus.h"
 #include "intel_hotplug.h"
 #include "intel_pch_display.h"
+#include "intel_pch_refclk.h"
 
 /* Here's the desired hotplug mode */
 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |		\
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index b688fd87e3da..752dab11667f 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -122,16 +122,29 @@ void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
 	mutex_unlock(&dev_priv->sb_lock);
 }
 
-/* Program iCLKIP clock to the desired frequency */
-void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
+struct iclkip_params {
+	u32 iclk_virtual_root_freq;
+	u32 iclk_pi_range;
+	u32 divsel, phaseinc, auxdiv, phasedir, desired_divisor;
+};
+
+static void iclkip_params_init(struct iclkip_params *p)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
-	u32 divsel, phaseinc, auxdiv, phasedir = 0;
-	u32 temp;
+	memset(p, 0, sizeof(*p));
+
+	p->iclk_virtual_root_freq = 172800 * 1000;
+	p->iclk_pi_range = 64;
+}
 
-	lpt_disable_iclkip(dev_priv);
+static int lpt_iclkip_freq(struct iclkip_params *p)
+{
+	return DIV_ROUND_CLOSEST(p->iclk_virtual_root_freq,
+				 p->desired_divisor << p->auxdiv);
+}
+
+static void lpt_compute_iclkip(struct iclkip_params *p, int clock)
+{
+	iclkip_params_init(p);
 
 	/* The iCLK virtual clock root frequency is in MHz,
 	 * but the adjusted_mode->crtc_clock in KHz. To get the
@@ -139,50 +152,61 @@ void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
 	 * convert the virtual clock precision to KHz here for higher
 	 * precision.
 	 */
-	for (auxdiv = 0; auxdiv < 2; auxdiv++) {
-		u32 iclk_virtual_root_freq = 172800 * 1000;
-		u32 iclk_pi_range = 64;
-		u32 desired_divisor;
-
-		desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
-						    clock << auxdiv);
-		divsel = (desired_divisor / iclk_pi_range) - 2;
-		phaseinc = desired_divisor % iclk_pi_range;
+	for (p->auxdiv = 0; p->auxdiv < 2; p->auxdiv++) {
+		p->desired_divisor = DIV_ROUND_CLOSEST(p->iclk_virtual_root_freq,
+						       clock << p->auxdiv);
+		p->divsel = (p->desired_divisor / p->iclk_pi_range) - 2;
+		p->phaseinc = p->desired_divisor % p->iclk_pi_range;
 
 		/*
 		 * Near 20MHz is a corner case which is
 		 * out of range for the 7-bit divisor
 		 */
-		if (divsel <= 0x7f)
+		if (p->divsel <= 0x7f)
 			break;
 	}
+}
+
+/* Program iCLKIP clock to the desired frequency */
+void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
+	struct iclkip_params p;
+	u32 temp;
+
+	lpt_disable_iclkip(dev_priv);
+
+	lpt_compute_iclkip(&p, clock);
+	drm_WARN_ON(&dev_priv->drm, lpt_iclkip_freq(&p) != clock);
 
 	/* This should not happen with any sane values */
-	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
+	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(p.divsel) &
 		    ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
-	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
+	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(p.phasedir) &
 		    ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
 
 	drm_dbg_kms(&dev_priv->drm,
 		    "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
-		    clock, auxdiv, divsel, phasedir, phaseinc);
+		    clock, p.auxdiv, p.divsel, p.phasedir, p.phaseinc);
 
 	mutex_lock(&dev_priv->sb_lock);
 
 	/* Program SSCDIVINTPHASE6 */
 	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
 	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
-	temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
+	temp |= SBI_SSCDIVINTPHASE_DIVSEL(p.divsel);
 	temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
-	temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
-	temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
+	temp |= SBI_SSCDIVINTPHASE_INCVAL(p.phaseinc);
+	temp |= SBI_SSCDIVINTPHASE_DIR(p.phasedir);
 	temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
 	intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
 
 	/* Program SSCAUXDIV */
 	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
 	temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
-	temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
+	temp |= SBI_SSCAUXDIV_FINALDIV2SEL(p.auxdiv);
 	intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
 
 	/* Enable modulator and associated divider */
@@ -200,15 +224,14 @@ void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
 
 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
 {
-	u32 divsel, phaseinc, auxdiv;
-	u32 iclk_virtual_root_freq = 172800 * 1000;
-	u32 iclk_pi_range = 64;
-	u32 desired_divisor;
+	struct iclkip_params p;
 	u32 temp;
 
 	if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
 		return 0;
 
+	iclkip_params_init(&p);
+
 	mutex_lock(&dev_priv->sb_lock);
 
 	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
@@ -218,21 +241,20 @@ int lpt_get_iclkip(struct drm_i915_private *dev_priv)
 	}
 
 	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
-	divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
+	p.divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
 		SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
-	phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
+	p.phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
 		SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
 
 	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
-	auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
+	p.auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
 		SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
 
 	mutex_unlock(&dev_priv->sb_lock);
 
-	desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
+	p.desired_divisor = (p.divsel + 2) * p.iclk_pi_range + p.phaseinc;
 
-	return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
-				 desired_divisor << auxdiv);
+	return lpt_iclkip_freq(&p);
 }
 
 /* Implements 3 different sequences from BSpec chapter "Display iCLK
-- 
2.35.1

Re: [Intel-gfx] [PATCH v2 11/26] drm/i915: Introduce struct iclkip_params

[Jani Nikula]

On Thu, 05 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Pull the various iCLKIP parameters into a struct. Later on
> we'll reuse this during the state computation to determine
> the exact dotclock the hardware will be generating for us.
>
> v2: Don't lost the phaseinc calculation

Oh noes, I didn't spot that in my review of v1. /o\

What do I reply here now? R-b again?!

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_crt.c      |  1 +
>  .../gpu/drm/i915/display/intel_pch_refclk.c   | 92 ++++++++++++-------
>  2 files changed, 58 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index 6a3893c8ff22..d746c85e7e8c 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -46,6 +46,7 @@
>  #include "intel_gmbus.h"
>  #include "intel_hotplug.h"
>  #include "intel_pch_display.h"
> +#include "intel_pch_refclk.h"
>  
>  /* Here's the desired hotplug mode */
>  #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |		\
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> index b688fd87e3da..752dab11667f 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> @@ -122,16 +122,29 @@ void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
>  	mutex_unlock(&dev_priv->sb_lock);
>  }
>  
> -/* Program iCLKIP clock to the desired frequency */
> -void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
> +struct iclkip_params {
> +	u32 iclk_virtual_root_freq;
> +	u32 iclk_pi_range;
> +	u32 divsel, phaseinc, auxdiv, phasedir, desired_divisor;
> +};
> +
> +static void iclkip_params_init(struct iclkip_params *p)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
> -	u32 divsel, phaseinc, auxdiv, phasedir = 0;
> -	u32 temp;
> +	memset(p, 0, sizeof(*p));
> +
> +	p->iclk_virtual_root_freq = 172800 * 1000;
> +	p->iclk_pi_range = 64;
> +}
>  
> -	lpt_disable_iclkip(dev_priv);
> +static int lpt_iclkip_freq(struct iclkip_params *p)
> +{
> +	return DIV_ROUND_CLOSEST(p->iclk_virtual_root_freq,
> +				 p->desired_divisor << p->auxdiv);
> +}
> +
> +static void lpt_compute_iclkip(struct iclkip_params *p, int clock)
> +{
> +	iclkip_params_init(p);
>  
>  	/* The iCLK virtual clock root frequency is in MHz,
>  	 * but the adjusted_mode->crtc_clock in KHz. To get the
> @@ -139,50 +152,61 @@ void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
>  	 * convert the virtual clock precision to KHz here for higher
>  	 * precision.
>  	 */
> -	for (auxdiv = 0; auxdiv < 2; auxdiv++) {
> -		u32 iclk_virtual_root_freq = 172800 * 1000;
> -		u32 iclk_pi_range = 64;
> -		u32 desired_divisor;
> -
> -		desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
> -						    clock << auxdiv);
> -		divsel = (desired_divisor / iclk_pi_range) - 2;
> -		phaseinc = desired_divisor % iclk_pi_range;
> +	for (p->auxdiv = 0; p->auxdiv < 2; p->auxdiv++) {
> +		p->desired_divisor = DIV_ROUND_CLOSEST(p->iclk_virtual_root_freq,
> +						       clock << p->auxdiv);
> +		p->divsel = (p->desired_divisor / p->iclk_pi_range) - 2;
> +		p->phaseinc = p->desired_divisor % p->iclk_pi_range;
>  
>  		/*
>  		 * Near 20MHz is a corner case which is
>  		 * out of range for the 7-bit divisor
>  		 */
> -		if (divsel <= 0x7f)
> +		if (p->divsel <= 0x7f)
>  			break;
>  	}
> +}
> +
> +/* Program iCLKIP clock to the desired frequency */
> +void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
> +	struct iclkip_params p;
> +	u32 temp;
> +
> +	lpt_disable_iclkip(dev_priv);
> +
> +	lpt_compute_iclkip(&p, clock);
> +	drm_WARN_ON(&dev_priv->drm, lpt_iclkip_freq(&p) != clock);
>  
>  	/* This should not happen with any sane values */
> -	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
> +	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(p.divsel) &
>  		    ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
> -	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
> +	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(p.phasedir) &
>  		    ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
>  
>  	drm_dbg_kms(&dev_priv->drm,
>  		    "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
> -		    clock, auxdiv, divsel, phasedir, phaseinc);
> +		    clock, p.auxdiv, p.divsel, p.phasedir, p.phaseinc);
>  
>  	mutex_lock(&dev_priv->sb_lock);
>  
>  	/* Program SSCDIVINTPHASE6 */
>  	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
>  	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
> -	temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
> +	temp |= SBI_SSCDIVINTPHASE_DIVSEL(p.divsel);
>  	temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
> -	temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
> -	temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
> +	temp |= SBI_SSCDIVINTPHASE_INCVAL(p.phaseinc);
> +	temp |= SBI_SSCDIVINTPHASE_DIR(p.phasedir);
>  	temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
>  	intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
>  
>  	/* Program SSCAUXDIV */
>  	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
>  	temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
> -	temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
> +	temp |= SBI_SSCAUXDIV_FINALDIV2SEL(p.auxdiv);
>  	intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
>  
>  	/* Enable modulator and associated divider */
> @@ -200,15 +224,14 @@ void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
>  
>  int lpt_get_iclkip(struct drm_i915_private *dev_priv)
>  {
> -	u32 divsel, phaseinc, auxdiv;
> -	u32 iclk_virtual_root_freq = 172800 * 1000;
> -	u32 iclk_pi_range = 64;
> -	u32 desired_divisor;
> +	struct iclkip_params p;
>  	u32 temp;
>  
>  	if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
>  		return 0;
>  
> +	iclkip_params_init(&p);
> +
>  	mutex_lock(&dev_priv->sb_lock);
>  
>  	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
> @@ -218,21 +241,20 @@ int lpt_get_iclkip(struct drm_i915_private *dev_priv)
>  	}
>  
>  	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
> -	divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
> +	p.divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
>  		SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
> -	phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
> +	p.phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
>  		SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
>  
>  	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
> -	auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
> +	p.auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
>  		SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
>  
>  	mutex_unlock(&dev_priv->sb_lock);
>  
> -	desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
> +	p.desired_divisor = (p.divsel + 2) * p.iclk_pi_range + p.phaseinc;
>  
> -	return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
> -				 desired_divisor << auxdiv);
> +	return lpt_iclkip_freq(&p);
>  }
>  
>  /* Implements 3 different sequences from BSpec chapter "Display iCLK

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 11/26] drm/i915: Introduce struct iclkip_params

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Pull the various iCLKIP parameters into a struct. Later on
> we'll reuse this during the state computation to determine
> the exact dotclock the hardware will be generating for us.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_crt.c      |  1 +
>  .../gpu/drm/i915/display/intel_pch_refclk.c   | 91 ++++++++++++-------
>  2 files changed, 57 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index 6a3893c8ff22..d746c85e7e8c 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -46,6 +46,7 @@
>  #include "intel_gmbus.h"
>  #include "intel_hotplug.h"
>  #include "intel_pch_display.h"
> +#include "intel_pch_refclk.h"

Seems out of place.

Otherwise,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>  
>  /* Here's the desired hotplug mode */
>  #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |		\
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> index b688fd87e3da..6610160cf825 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> @@ -122,16 +122,29 @@ void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
>  	mutex_unlock(&dev_priv->sb_lock);
>  }
>  
> -/* Program iCLKIP clock to the desired frequency */
> -void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
> +struct iclkip_params {
> +	u32 iclk_virtual_root_freq;
> +	u32 iclk_pi_range;
> +	u32 divsel, phaseinc, auxdiv, phasedir, desired_divisor;
> +};
> +
> +static void iclkip_params_init(struct iclkip_params *p)
>  {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
> -	u32 divsel, phaseinc, auxdiv, phasedir = 0;
> -	u32 temp;
> +	memset(p, 0, sizeof(*p));
> +
> +	p->iclk_virtual_root_freq = 172800 * 1000;
> +	p->iclk_pi_range = 64;
> +}
>  
> -	lpt_disable_iclkip(dev_priv);
> +static int lpt_iclkip_freq(struct iclkip_params *p)
> +{
> +	return DIV_ROUND_CLOSEST(p->iclk_virtual_root_freq,
> +				 p->desired_divisor << p->auxdiv);
> +}
> +
> +static void lpt_compute_iclkip(struct iclkip_params *p, int clock)
> +{
> +	iclkip_params_init(p);
>  
>  	/* The iCLK virtual clock root frequency is in MHz,
>  	 * but the adjusted_mode->crtc_clock in KHz. To get the
> @@ -139,50 +152,60 @@ void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
>  	 * convert the virtual clock precision to KHz here for higher
>  	 * precision.
>  	 */
> -	for (auxdiv = 0; auxdiv < 2; auxdiv++) {
> -		u32 iclk_virtual_root_freq = 172800 * 1000;
> -		u32 iclk_pi_range = 64;
> -		u32 desired_divisor;
> -
> -		desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
> -						    clock << auxdiv);
> -		divsel = (desired_divisor / iclk_pi_range) - 2;
> -		phaseinc = desired_divisor % iclk_pi_range;
> +	for (p->auxdiv = 0; p->auxdiv < 2; p->auxdiv++) {
> +		p->desired_divisor = DIV_ROUND_CLOSEST(p->iclk_virtual_root_freq,
> +						       clock << p->auxdiv);
> +		p->divsel = (p->desired_divisor / p->iclk_pi_range) - 2;
>  
>  		/*
>  		 * Near 20MHz is a corner case which is
>  		 * out of range for the 7-bit divisor
>  		 */
> -		if (divsel <= 0x7f)
> +		if (p->divsel <= 0x7f)
>  			break;
>  	}
> +}
> +
> +/* Program iCLKIP clock to the desired frequency */
> +void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
> +	struct iclkip_params p;
> +	u32 temp;
> +
> +	lpt_disable_iclkip(dev_priv);
> +
> +	lpt_compute_iclkip(&p, clock);
> +	drm_WARN_ON(&dev_priv->drm, lpt_iclkip_freq(&p) != clock);
>  
>  	/* This should not happen with any sane values */
> -	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
> +	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(p.divsel) &
>  		    ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
> -	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &
> +	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(p.phasedir) &
>  		    ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
>  
>  	drm_dbg_kms(&dev_priv->drm,
>  		    "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
> -		    clock, auxdiv, divsel, phasedir, phaseinc);
> +		    clock, p.auxdiv, p.divsel, p.phasedir, p.phaseinc);
>  
>  	mutex_lock(&dev_priv->sb_lock);
>  
>  	/* Program SSCDIVINTPHASE6 */
>  	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
>  	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
> -	temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
> +	temp |= SBI_SSCDIVINTPHASE_DIVSEL(p.divsel);
>  	temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
> -	temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
> -	temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
> +	temp |= SBI_SSCDIVINTPHASE_INCVAL(p.phaseinc);
> +	temp |= SBI_SSCDIVINTPHASE_DIR(p.phasedir);
>  	temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
>  	intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
>  
>  	/* Program SSCAUXDIV */
>  	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
>  	temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
> -	temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
> +	temp |= SBI_SSCAUXDIV_FINALDIV2SEL(p.auxdiv);
>  	intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
>  
>  	/* Enable modulator and associated divider */
> @@ -200,15 +223,14 @@ void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
>  
>  int lpt_get_iclkip(struct drm_i915_private *dev_priv)
>  {
> -	u32 divsel, phaseinc, auxdiv;
> -	u32 iclk_virtual_root_freq = 172800 * 1000;
> -	u32 iclk_pi_range = 64;
> -	u32 desired_divisor;
> +	struct iclkip_params p;
>  	u32 temp;
>  
>  	if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
>  		return 0;
>  
> +	iclkip_params_init(&p);
> +
>  	mutex_lock(&dev_priv->sb_lock);
>  
>  	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
> @@ -218,21 +240,20 @@ int lpt_get_iclkip(struct drm_i915_private *dev_priv)
>  	}
>  
>  	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
> -	divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
> +	p.divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
>  		SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
> -	phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
> +	p.phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
>  		SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
>  
>  	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
> -	auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
> +	p.auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
>  		SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
>  
>  	mutex_unlock(&dev_priv->sb_lock);
>  
> -	desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
> +	p.desired_divisor = (p.divsel + 2) * p.iclk_pi_range + p.phaseinc;
>  
> -	return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
> -				 desired_divisor << auxdiv);
> +	return lpt_iclkip_freq(&p);
>  }
>  
>  /* Implements 3 different sequences from BSpec chapter "Display iCLK

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 12/26] drm/i915: Feed the DPLL output freq back into crtc_state

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Fill port_clock and hw.adjusted_mode.crtc_clock with the actual
frequency we're going to be getting from the hardware. This will
let us accurately compute all derived state that depends on those.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_crt.c      |  2 +
 drivers/gpu/drm/i915/display/intel_dpll.c     | 64 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 36 ++++++++++-
 .../gpu/drm/i915/display/intel_pch_refclk.c   |  9 +++
 .../gpu/drm/i915/display/intel_pch_refclk.h   |  1 +
 5 files changed, 108 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index d746c85e7e8c..a225af030ad7 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -445,6 +445,8 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
 	/* FDI must always be 2.7 GHz */
 	pipe_config->port_clock = 135000 * 2;
 
+	adjusted_mode->crtc_clock = lpt_iclkip(pipe_config);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index afd30c6cc34c..4a9d7b6d16cc 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -930,6 +930,8 @@ static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
 	crtc_state->dpll_hw_state.dpll = dpll;
 }
 
+int intel_crtc_dotclock(const struct intel_crtc_state *crtc_state);
+
 static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
 				  struct intel_crtc *crtc)
 {
@@ -938,12 +940,25 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct intel_encoder *encoder =
 		intel_get_crtc_new_encoder(state, crtc_state);
+	int ret;
 
 	if (DISPLAY_VER(dev_priv) < 11 &&
 	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
 		return 0;
 
-	return intel_compute_shared_dplls(state, crtc, encoder);
+	ret = intel_compute_shared_dplls(state, crtc, encoder);
+	if (ret)
+		return ret;
+
+	/* FIXME this is a mess */
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
+		return 0;
+
+	/* CRT dotclock is determined via other means */
+	if (!crtc_state->has_pch_encoder)
+		crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
+
+	return 0;
 }
 
 static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
@@ -969,8 +984,15 @@ static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct intel_encoder *encoder =
 		intel_get_crtc_new_encoder(state, crtc_state);
+	int ret;
 
-	return intel_mpllb_calc_state(crtc_state, encoder);
+	ret = intel_mpllb_calc_state(crtc_state, encoder);
+	if (ret)
+		return ret;
+
+	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
+
+	return 0;
 }
 
 static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
@@ -1096,6 +1118,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
 		intel_atomic_get_new_crtc_state(state, crtc);
 	const struct intel_limit *limit;
 	int refclk = 120000;
+	int ret;
 
 	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
 	if (!crtc_state->has_pch_encoder)
@@ -1132,7 +1155,14 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
 	ilk_compute_dpll(crtc_state, &crtc_state->dpll,
 			 &crtc_state->dpll);
 
-	return intel_compute_shared_dplls(state, crtc, NULL);
+	ret = intel_compute_shared_dplls(state, crtc, NULL);
+	if (ret)
+		return ret;
+
+	crtc_state->port_clock = crtc_state->dpll.dot;
+	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
+
+	return ret;
 }
 
 static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
@@ -1198,6 +1228,13 @@ static int chv_crtc_compute_clock(struct intel_atomic_state *state,
 
 	chv_compute_dpll(crtc_state);
 
+	/* FIXME this is a mess */
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
+		return 0;
+
+	crtc_state->port_clock = crtc_state->dpll.dot;
+	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
+
 	return 0;
 }
 
@@ -1217,6 +1254,13 @@ static int vlv_crtc_compute_clock(struct intel_atomic_state *state,
 
 	vlv_compute_dpll(crtc_state);
 
+	/* FIXME this is a mess */
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
+		return 0;
+
+	crtc_state->port_clock = crtc_state->dpll.dot;
+	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
+
 	return 0;
 }
 
@@ -1259,6 +1303,9 @@ static int g4x_crtc_compute_clock(struct intel_atomic_state *state,
 	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
 			  &crtc_state->dpll);
 
+	crtc_state->port_clock = crtc_state->dpll.dot;
+	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
+
 	return 0;
 }
 
@@ -1292,6 +1339,9 @@ static int pnv_crtc_compute_clock(struct intel_atomic_state *state,
 	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
 			  &crtc_state->dpll);
 
+	crtc_state->port_clock = crtc_state->dpll.dot;
+	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
+
 	return 0;
 }
 
@@ -1325,6 +1375,9 @@ static int i9xx_crtc_compute_clock(struct intel_atomic_state *state,
 	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
 			  &crtc_state->dpll);
 
+	crtc_state->port_clock = crtc_state->dpll.dot;
+	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
+
 	return 0;
 }
 
@@ -1360,6 +1413,9 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
 	i8xx_compute_dpll(crtc_state, &crtc_state->dpll,
 			  &crtc_state->dpll);
 
+	crtc_state->port_clock = crtc_state->dpll.dot;
+	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
+
 	return 0;
 }
 
@@ -1401,6 +1457,8 @@ static const struct intel_dpll_funcs i8xx_dpll_funcs = {
 	.crtc_compute_clock = i8xx_crtc_compute_clock,
 };
 
+int intel_calculate_dotclock(const struct intel_crtc_state *crtc_state);
+
 int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
 				  struct intel_crtc *crtc)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 64708e874b13..416d78f9e140 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -905,10 +905,15 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
 	*r2_out = best.r2;
 }
 
+static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
+				  const struct intel_shared_dpll *pll,
+				  const struct intel_dpll_hw_state *pll_state);
+
 static int
 hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
 			   struct intel_crtc *crtc)
 {
+	struct drm_i915_private *i915 = to_i915(state->base.dev);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	unsigned int p, n2, r2;
@@ -920,6 +925,9 @@ hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
 		WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
 		WRPLL_DIVIDER_POST(p);
 
+	crtc_state->port_clock = hsw_ddi_wrpll_get_freq(i915, NULL,
+							&crtc_state->dpll_hw_state);
+
 	return 0;
 }
 
@@ -1618,6 +1626,10 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
 	return 0;
 }
 
+static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
+				  const struct intel_shared_dpll *pll,
+				  const struct intel_dpll_hw_state *pll_state);
+
 static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
@@ -1652,6 +1664,9 @@ static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
 	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
 	crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
 
+	crtc_state->port_clock = skl_ddi_wrpll_get_freq(i915, NULL,
+							&crtc_state->dpll_hw_state);
+
 	return 0;
 }
 
@@ -2255,14 +2270,27 @@ bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
 	return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
 }
 
+static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
+				const struct intel_shared_dpll *pll,
+				const struct intel_dpll_hw_state *pll_state);
+
 static int
 bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
 {
+	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 	struct dpll clk_div = {};
+	int ret;
 
 	bxt_ddi_hdmi_pll_dividers(crtc_state, &clk_div);
 
-	return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
+	ret = bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
+	if (ret)
+		return ret;
+
+	crtc_state->port_clock = bxt_ddi_pll_get_freq(i915, NULL,
+						      &crtc_state->dpll_hw_state);
+
+	return 0;
 }
 
 static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
@@ -3197,6 +3225,9 @@ static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
 
 	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
 
+	crtc_state->port_clock = icl_ddi_combo_pll_get_freq(dev_priv, NULL,
+							    &port_dpll->hw_state);
+
 	return 0;
 }
 
@@ -3282,6 +3313,9 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
 	if (ret)
 		return ret;
 
+	crtc_state->port_clock = icl_ddi_mg_pll_get_freq(dev_priv, NULL,
+							 &port_dpll->hw_state);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index 6610160cf825..5fb7ead97c90 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -166,6 +166,15 @@ static void lpt_compute_iclkip(struct iclkip_params *p, int clock)
 	}
 }
 
+int lpt_iclkip(const struct intel_crtc_state *crtc_state)
+{
+	struct iclkip_params p;
+
+	lpt_compute_iclkip(&p, crtc_state->hw.adjusted_mode.crtc_clock);
+
+	return lpt_iclkip_freq(&p);
+}
+
 /* Program iCLKIP clock to the desired frequency */
 void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.h b/drivers/gpu/drm/i915/display/intel_pch_refclk.h
index 12ab2c75a800..9bcf56629f24 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.h
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.h
@@ -14,6 +14,7 @@ struct intel_crtc_state;
 void lpt_program_iclkip(const struct intel_crtc_state *crtc_state);
 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
+int lpt_iclkip(const struct intel_crtc_state *crtc_state);
 
 void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
-- 
2.35.1

Re: [Intel-gfx] [PATCH 12/26] drm/i915: Feed the DPLL output freq back into crtc_state

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Fill port_clock and hw.adjusted_mode.crtc_clock with the actual
> frequency we're going to be getting from the hardware. This will
> let us accurately compute all derived state that depends on those.

This patch (and to be honest, quite a few of the subsequent ones too)
make my brain hurt. So I can't spot anything obviously wrong here, it's
just that my confidence is low. And that makes me feel dumb. It's either
that, or the existing code base is overly complex. I'm 50-50, could lean
either way.

Anyway.

Why haven't we set .crtc_clock before?

Should we remove the "Set default port clock if not overwritten by the
encoder. Needs to be done afterwards in case the encoder adjusts the
mode." bit in intel_modeset_pipe_config(), and require encoder needs to
do it?

A self-doubting

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_crt.c      |  2 +
>  drivers/gpu/drm/i915/display/intel_dpll.c     | 64 ++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 36 ++++++++++-
>  .../gpu/drm/i915/display/intel_pch_refclk.c   |  9 +++
>  .../gpu/drm/i915/display/intel_pch_refclk.h   |  1 +
>  5 files changed, 108 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index d746c85e7e8c..a225af030ad7 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -445,6 +445,8 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
>  	/* FDI must always be 2.7 GHz */
>  	pipe_config->port_clock = 135000 * 2;
>  
> +	adjusted_mode->crtc_clock = lpt_iclkip(pipe_config);
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index afd30c6cc34c..4a9d7b6d16cc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -930,6 +930,8 @@ static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
>  	crtc_state->dpll_hw_state.dpll = dpll;
>  }
>  
> +int intel_crtc_dotclock(const struct intel_crtc_state *crtc_state);
> +
>  static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
>  				  struct intel_crtc *crtc)
>  {
> @@ -938,12 +940,25 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	struct intel_encoder *encoder =
>  		intel_get_crtc_new_encoder(state, crtc_state);
> +	int ret;
>  
>  	if (DISPLAY_VER(dev_priv) < 11 &&
>  	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
>  		return 0;
>  
> -	return intel_compute_shared_dplls(state, crtc, encoder);
> +	ret = intel_compute_shared_dplls(state, crtc, encoder);
> +	if (ret)
> +		return ret;
> +
> +	/* FIXME this is a mess */
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> +		return 0;
> +
> +	/* CRT dotclock is determined via other means */
> +	if (!crtc_state->has_pch_encoder)
> +		crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
> +
> +	return 0;
>  }
>  
>  static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
> @@ -969,8 +984,15 @@ static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	struct intel_encoder *encoder =
>  		intel_get_crtc_new_encoder(state, crtc_state);
> +	int ret;
>  
> -	return intel_mpllb_calc_state(crtc_state, encoder);
> +	ret = intel_mpllb_calc_state(crtc_state, encoder);
> +	if (ret)
> +		return ret;
> +
> +	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
> +
> +	return 0;
>  }
>  
>  static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
> @@ -1096,6 +1118,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	const struct intel_limit *limit;
>  	int refclk = 120000;
> +	int ret;
>  
>  	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
>  	if (!crtc_state->has_pch_encoder)
> @@ -1132,7 +1155,14 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
>  	ilk_compute_dpll(crtc_state, &crtc_state->dpll,
>  			 &crtc_state->dpll);
>  
> -	return intel_compute_shared_dplls(state, crtc, NULL);
> +	ret = intel_compute_shared_dplls(state, crtc, NULL);
> +	if (ret)
> +		return ret;
> +
> +	crtc_state->port_clock = crtc_state->dpll.dot;
> +	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
> +
> +	return ret;
>  }
>  
>  static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
> @@ -1198,6 +1228,13 @@ static int chv_crtc_compute_clock(struct intel_atomic_state *state,
>  
>  	chv_compute_dpll(crtc_state);
>  
> +	/* FIXME this is a mess */
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> +		return 0;
> +
> +	crtc_state->port_clock = crtc_state->dpll.dot;
> +	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
> +
>  	return 0;
>  }
>  
> @@ -1217,6 +1254,13 @@ static int vlv_crtc_compute_clock(struct intel_atomic_state *state,
>  
>  	vlv_compute_dpll(crtc_state);
>  
> +	/* FIXME this is a mess */
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> +		return 0;
> +
> +	crtc_state->port_clock = crtc_state->dpll.dot;
> +	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
> +
>  	return 0;
>  }
>  
> @@ -1259,6 +1303,9 @@ static int g4x_crtc_compute_clock(struct intel_atomic_state *state,
>  	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
>  			  &crtc_state->dpll);
>  
> +	crtc_state->port_clock = crtc_state->dpll.dot;
> +	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
> +
>  	return 0;
>  }
>  
> @@ -1292,6 +1339,9 @@ static int pnv_crtc_compute_clock(struct intel_atomic_state *state,
>  	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
>  			  &crtc_state->dpll);
>  
> +	crtc_state->port_clock = crtc_state->dpll.dot;
> +	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
> +
>  	return 0;
>  }
>  
> @@ -1325,6 +1375,9 @@ static int i9xx_crtc_compute_clock(struct intel_atomic_state *state,
>  	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
>  			  &crtc_state->dpll);
>  
> +	crtc_state->port_clock = crtc_state->dpll.dot;
> +	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
> +
>  	return 0;
>  }
>  
> @@ -1360,6 +1413,9 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
>  	i8xx_compute_dpll(crtc_state, &crtc_state->dpll,
>  			  &crtc_state->dpll);
>  
> +	crtc_state->port_clock = crtc_state->dpll.dot;
> +	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
> +
>  	return 0;
>  }
>  
> @@ -1401,6 +1457,8 @@ static const struct intel_dpll_funcs i8xx_dpll_funcs = {
>  	.crtc_compute_clock = i8xx_crtc_compute_clock,
>  };
>  
> +int intel_calculate_dotclock(const struct intel_crtc_state *crtc_state);
> +
>  int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
>  				  struct intel_crtc *crtc)
>  {
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 64708e874b13..416d78f9e140 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -905,10 +905,15 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
>  	*r2_out = best.r2;
>  }
>  
> +static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> +				  const struct intel_shared_dpll *pll,
> +				  const struct intel_dpll_hw_state *pll_state);
> +
>  static int
>  hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
>  			   struct intel_crtc *crtc)
>  {
> +	struct drm_i915_private *i915 = to_i915(state->base.dev);
>  	struct intel_crtc_state *crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	unsigned int p, n2, r2;
> @@ -920,6 +925,9 @@ hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
>  		WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
>  		WRPLL_DIVIDER_POST(p);
>  
> +	crtc_state->port_clock = hsw_ddi_wrpll_get_freq(i915, NULL,
> +							&crtc_state->dpll_hw_state);
> +
>  	return 0;
>  }
>  
> @@ -1618,6 +1626,10 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
>  	return 0;
>  }
>  
> +static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
> +				  const struct intel_shared_dpll *pll,
> +				  const struct intel_dpll_hw_state *pll_state);
> +
>  static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> @@ -1652,6 +1664,9 @@ static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
>  	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
>  	crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
>  
> +	crtc_state->port_clock = skl_ddi_wrpll_get_freq(i915, NULL,
> +							&crtc_state->dpll_hw_state);
> +
>  	return 0;
>  }
>  
> @@ -2255,14 +2270,27 @@ bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
>  	return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
>  }
>  
> +static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
> +				const struct intel_shared_dpll *pll,
> +				const struct intel_dpll_hw_state *pll_state);
> +
>  static int
>  bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
>  {
> +	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>  	struct dpll clk_div = {};
> +	int ret;
>  
>  	bxt_ddi_hdmi_pll_dividers(crtc_state, &clk_div);
>  
> -	return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
> +	ret = bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
> +	if (ret)
> +		return ret;
> +
> +	crtc_state->port_clock = bxt_ddi_pll_get_freq(i915, NULL,
> +						      &crtc_state->dpll_hw_state);
> +
> +	return 0;
>  }
>  
>  static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
> @@ -3197,6 +3225,9 @@ static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
>  
>  	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
>  
> +	crtc_state->port_clock = icl_ddi_combo_pll_get_freq(dev_priv, NULL,
> +							    &port_dpll->hw_state);
> +
>  	return 0;
>  }
>  
> @@ -3282,6 +3313,9 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
>  	if (ret)
>  		return ret;
>  
> +	crtc_state->port_clock = icl_ddi_mg_pll_get_freq(dev_priv, NULL,
> +							 &port_dpll->hw_state);
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> index 6610160cf825..5fb7ead97c90 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> @@ -166,6 +166,15 @@ static void lpt_compute_iclkip(struct iclkip_params *p, int clock)
>  	}
>  }
>  
> +int lpt_iclkip(const struct intel_crtc_state *crtc_state)
> +{
> +	struct iclkip_params p;
> +
> +	lpt_compute_iclkip(&p, crtc_state->hw.adjusted_mode.crtc_clock);
> +
> +	return lpt_iclkip_freq(&p);
> +}
> +
>  /* Program iCLKIP clock to the desired frequency */
>  void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
>  {
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.h b/drivers/gpu/drm/i915/display/intel_pch_refclk.h
> index 12ab2c75a800..9bcf56629f24 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.h
> @@ -14,6 +14,7 @@ struct intel_crtc_state;
>  void lpt_program_iclkip(const struct intel_crtc_state *crtc_state);
>  void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
>  int lpt_get_iclkip(struct drm_i915_private *dev_priv);
> +int lpt_iclkip(const struct intel_crtc_state *crtc_state);
>  
>  void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
>  void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 12/26] drm/i915: Feed the DPLL output freq back into crtc_state

[Ville Syrjälä]

On Wed, May 25, 2022 at 01:53:38PM +0300, Jani Nikula wrote:
> On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Fill port_clock and hw.adjusted_mode.crtc_clock with the actual
> > frequency we're going to be getting from the hardware. This will
> > let us accurately compute all derived state that depends on those.
> 
> This patch (and to be honest, quite a few of the subsequent ones too)
> make my brain hurt. So I can't spot anything obviously wrong here, it's
> just that my confidence is low. And that makes me feel dumb. It's either
> that, or the existing code base is overly complex. I'm 50-50, could lean
> either way.
> 
> Anyway.
> 
> Why haven't we set .crtc_clock before?

Who knows. Just always been like that.

> 
> Should we remove the "Set default port clock if not overwritten by the
> encoder. Needs to be done afterwards in case the encoder adjusts the
> mode." bit in intel_modeset_pipe_config(), and require encoder needs to
> do it?

Yeah, moving all this clock stuff into encoder->compute_config() is
perhaps what we want to do eventually. What makes it a bit awkward
is cloning since each cloned encoder would then recompute the
DPLL/clock state for the same crtc. I guess that shouldn't really
matter as long as we'd still end up with the same computed state
at the end. 

But I might be missing something so probably need to let that idea
simmer a bit further.

> 
> A self-doubting
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_crt.c      |  2 +
> >  drivers/gpu/drm/i915/display/intel_dpll.c     | 64 ++++++++++++++++++-
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 36 ++++++++++-
> >  .../gpu/drm/i915/display/intel_pch_refclk.c   |  9 +++
> >  .../gpu/drm/i915/display/intel_pch_refclk.h   |  1 +
> >  5 files changed, 108 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> > index d746c85e7e8c..a225af030ad7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crt.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> > @@ -445,6 +445,8 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
> >  	/* FDI must always be 2.7 GHz */
> >  	pipe_config->port_clock = 135000 * 2;
> >  
> > +	adjusted_mode->crtc_clock = lpt_iclkip(pipe_config);
> > +
> >  	return 0;
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> > index afd30c6cc34c..4a9d7b6d16cc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> > @@ -930,6 +930,8 @@ static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
> >  	crtc_state->dpll_hw_state.dpll = dpll;
> >  }
> >  
> > +int intel_crtc_dotclock(const struct intel_crtc_state *crtc_state);
> > +
> >  static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
> >  				  struct intel_crtc *crtc)
> >  {
> > @@ -938,12 +940,25 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
> >  		intel_atomic_get_new_crtc_state(state, crtc);
> >  	struct intel_encoder *encoder =
> >  		intel_get_crtc_new_encoder(state, crtc_state);
> > +	int ret;
> >  
> >  	if (DISPLAY_VER(dev_priv) < 11 &&
> >  	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> >  		return 0;
> >  
> > -	return intel_compute_shared_dplls(state, crtc, encoder);
> > +	ret = intel_compute_shared_dplls(state, crtc, encoder);
> > +	if (ret)
> > +		return ret;
> > +
> > +	/* FIXME this is a mess */
> > +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> > +		return 0;
> > +
> > +	/* CRT dotclock is determined via other means */
> > +	if (!crtc_state->has_pch_encoder)
> > +		crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
> > +
> > +	return 0;
> >  }
> >  
> >  static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
> > @@ -969,8 +984,15 @@ static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
> >  		intel_atomic_get_new_crtc_state(state, crtc);
> >  	struct intel_encoder *encoder =
> >  		intel_get_crtc_new_encoder(state, crtc_state);
> > +	int ret;
> >  
> > -	return intel_mpllb_calc_state(crtc_state, encoder);
> > +	ret = intel_mpllb_calc_state(crtc_state, encoder);
> > +	if (ret)
> > +		return ret;
> > +
> > +	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
> > +
> > +	return 0;
> >  }
> >  
> >  static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
> > @@ -1096,6 +1118,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
> >  		intel_atomic_get_new_crtc_state(state, crtc);
> >  	const struct intel_limit *limit;
> >  	int refclk = 120000;
> > +	int ret;
> >  
> >  	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
> >  	if (!crtc_state->has_pch_encoder)
> > @@ -1132,7 +1155,14 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
> >  	ilk_compute_dpll(crtc_state, &crtc_state->dpll,
> >  			 &crtc_state->dpll);
> >  
> > -	return intel_compute_shared_dplls(state, crtc, NULL);
> > +	ret = intel_compute_shared_dplls(state, crtc, NULL);
> > +	if (ret)
> > +		return ret;
> > +
> > +	crtc_state->port_clock = crtc_state->dpll.dot;
> > +	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
> > +
> > +	return ret;
> >  }
> >  
> >  static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
> > @@ -1198,6 +1228,13 @@ static int chv_crtc_compute_clock(struct intel_atomic_state *state,
> >  
> >  	chv_compute_dpll(crtc_state);
> >  
> > +	/* FIXME this is a mess */
> > +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> > +		return 0;
> > +
> > +	crtc_state->port_clock = crtc_state->dpll.dot;
> > +	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
> > +
> >  	return 0;
> >  }
> >  
> > @@ -1217,6 +1254,13 @@ static int vlv_crtc_compute_clock(struct intel_atomic_state *state,
> >  
> >  	vlv_compute_dpll(crtc_state);
> >  
> > +	/* FIXME this is a mess */
> > +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> > +		return 0;
> > +
> > +	crtc_state->port_clock = crtc_state->dpll.dot;
> > +	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
> > +
> >  	return 0;
> >  }
> >  
> > @@ -1259,6 +1303,9 @@ static int g4x_crtc_compute_clock(struct intel_atomic_state *state,
> >  	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
> >  			  &crtc_state->dpll);
> >  
> > +	crtc_state->port_clock = crtc_state->dpll.dot;
> > +	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
> > +
> >  	return 0;
> >  }
> >  
> > @@ -1292,6 +1339,9 @@ static int pnv_crtc_compute_clock(struct intel_atomic_state *state,
> >  	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
> >  			  &crtc_state->dpll);
> >  
> > +	crtc_state->port_clock = crtc_state->dpll.dot;
> > +	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
> > +
> >  	return 0;
> >  }
> >  
> > @@ -1325,6 +1375,9 @@ static int i9xx_crtc_compute_clock(struct intel_atomic_state *state,
> >  	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
> >  			  &crtc_state->dpll);
> >  
> > +	crtc_state->port_clock = crtc_state->dpll.dot;
> > +	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
> > +
> >  	return 0;
> >  }
> >  
> > @@ -1360,6 +1413,9 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
> >  	i8xx_compute_dpll(crtc_state, &crtc_state->dpll,
> >  			  &crtc_state->dpll);
> >  
> > +	crtc_state->port_clock = crtc_state->dpll.dot;
> > +	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
> > +
> >  	return 0;
> >  }
> >  
> > @@ -1401,6 +1457,8 @@ static const struct intel_dpll_funcs i8xx_dpll_funcs = {
> >  	.crtc_compute_clock = i8xx_crtc_compute_clock,
> >  };
> >  
> > +int intel_calculate_dotclock(const struct intel_crtc_state *crtc_state);
> > +
> >  int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
> >  				  struct intel_crtc *crtc)
> >  {
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index 64708e874b13..416d78f9e140 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -905,10 +905,15 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
> >  	*r2_out = best.r2;
> >  }
> >  
> > +static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
> > +				  const struct intel_shared_dpll *pll,
> > +				  const struct intel_dpll_hw_state *pll_state);
> > +
> >  static int
> >  hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
> >  			   struct intel_crtc *crtc)
> >  {
> > +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> >  	struct intel_crtc_state *crtc_state =
> >  		intel_atomic_get_new_crtc_state(state, crtc);
> >  	unsigned int p, n2, r2;
> > @@ -920,6 +925,9 @@ hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
> >  		WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
> >  		WRPLL_DIVIDER_POST(p);
> >  
> > +	crtc_state->port_clock = hsw_ddi_wrpll_get_freq(i915, NULL,
> > +							&crtc_state->dpll_hw_state);
> > +
> >  	return 0;
> >  }
> >  
> > @@ -1618,6 +1626,10 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
> >  	return 0;
> >  }
> >  
> > +static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
> > +				  const struct intel_shared_dpll *pll,
> > +				  const struct intel_dpll_hw_state *pll_state);
> > +
> >  static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
> >  {
> >  	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> > @@ -1652,6 +1664,9 @@ static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
> >  	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
> >  	crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
> >  
> > +	crtc_state->port_clock = skl_ddi_wrpll_get_freq(i915, NULL,
> > +							&crtc_state->dpll_hw_state);
> > +
> >  	return 0;
> >  }
> >  
> > @@ -2255,14 +2270,27 @@ bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> >  	return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
> >  }
> >  
> > +static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
> > +				const struct intel_shared_dpll *pll,
> > +				const struct intel_dpll_hw_state *pll_state);
> > +
> >  static int
> >  bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> >  {
> > +	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> >  	struct dpll clk_div = {};
> > +	int ret;
> >  
> >  	bxt_ddi_hdmi_pll_dividers(crtc_state, &clk_div);
> >  
> > -	return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
> > +	ret = bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
> > +	if (ret)
> > +		return ret;
> > +
> > +	crtc_state->port_clock = bxt_ddi_pll_get_freq(i915, NULL,
> > +						      &crtc_state->dpll_hw_state);
> > +
> > +	return 0;
> >  }
> >  
> >  static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
> > @@ -3197,6 +3225,9 @@ static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
> >  
> >  	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
> >  
> > +	crtc_state->port_clock = icl_ddi_combo_pll_get_freq(dev_priv, NULL,
> > +							    &port_dpll->hw_state);
> > +
> >  	return 0;
> >  }
> >  
> > @@ -3282,6 +3313,9 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
> >  	if (ret)
> >  		return ret;
> >  
> > +	crtc_state->port_clock = icl_ddi_mg_pll_get_freq(dev_priv, NULL,
> > +							 &port_dpll->hw_state);
> > +
> >  	return 0;
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> > index 6610160cf825..5fb7ead97c90 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> > @@ -166,6 +166,15 @@ static void lpt_compute_iclkip(struct iclkip_params *p, int clock)
> >  	}
> >  }
> >  
> > +int lpt_iclkip(const struct intel_crtc_state *crtc_state)
> > +{
> > +	struct iclkip_params p;
> > +
> > +	lpt_compute_iclkip(&p, crtc_state->hw.adjusted_mode.crtc_clock);
> > +
> > +	return lpt_iclkip_freq(&p);
> > +}
> > +
> >  /* Program iCLKIP clock to the desired frequency */
> >  void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
> >  {
> > diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.h b/drivers/gpu/drm/i915/display/intel_pch_refclk.h
> > index 12ab2c75a800..9bcf56629f24 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.h
> > +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.h
> > @@ -14,6 +14,7 @@ struct intel_crtc_state;
> >  void lpt_program_iclkip(const struct intel_crtc_state *crtc_state);
> >  void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
> >  int lpt_get_iclkip(struct drm_i915_private *dev_priv);
> > +int lpt_iclkip(const struct intel_crtc_state *crtc_state);
> >  
> >  void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
> >  void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Ville Syrjälä
Intel

[Intel-gfx] [PATCH 13/26] drm/i915: Compute clocks earlier

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Do the DPLL computation before fastset checks. This should
allow us to get rid of all that horrible fuzzy clock handling
for fastsets. Who knows how many bugs there are caused by our
state not actually matching what the hardware will generate.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8d6cbfbaf20d..1a25addadc21 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2818,6 +2818,10 @@ static int intel_crtc_compute_config(struct intel_atomic_state *state,
 		intel_atomic_get_new_crtc_state(state, crtc);
 	int ret;
 
+	ret = intel_dpll_crtc_compute_clock(state, crtc);
+	if (ret)
+		return ret;
+
 	ret = intel_crtc_compute_pipe_src(crtc_state);
 	if (ret)
 		return ret;
@@ -7783,10 +7787,6 @@ static int intel_atomic_check(struct drm_device *dev,
 		if (intel_crtc_needs_modeset(new_crtc_state)) {
 			any_ms = true;
 
-			ret = intel_dpll_crtc_compute_clock(state, crtc);
-			if (ret)
-				goto fail;
-
 			intel_release_shared_dplls(state, crtc);
 			continue;
 		}
-- 
2.35.1

Re: [Intel-gfx] [PATCH 13/26] drm/i915: Compute clocks earlier

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Do the DPLL computation before fastset checks. This should
> allow us to get rid of all that horrible fuzzy clock handling
> for fastsets. Who knows how many bugs there are caused by our
> state not actually matching what the hardware will generate.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 8d6cbfbaf20d..1a25addadc21 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2818,6 +2818,10 @@ static int intel_crtc_compute_config(struct intel_atomic_state *state,
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	int ret;
>  
> +	ret = intel_dpll_crtc_compute_clock(state, crtc);
> +	if (ret)
> +		return ret;
> +
>  	ret = intel_crtc_compute_pipe_src(crtc_state);
>  	if (ret)
>  		return ret;
> @@ -7783,10 +7787,6 @@ static int intel_atomic_check(struct drm_device *dev,
>  		if (intel_crtc_needs_modeset(new_crtc_state)) {
>  			any_ms = true;
>  
> -			ret = intel_dpll_crtc_compute_clock(state, crtc);
> -			if (ret)
> -				goto fail;
> -
>  			intel_release_shared_dplls(state, crtc);
>  			continue;
>  		}

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 14/26] drm/i915: Skip FDI vs. dotclock sanity check during readout

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The VBIOS/GOP may not program the FDI M/n vs. dotclock entirely
consistently. Eg. on a SNB Thinkpad X220 LVDS I see dotclock of
69.286 MHz (the best the DPLL can do) vs. FDI M/N 69.3 MHz
(matches what the EDID actually declares).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1a25addadc21..86971be92e57 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10248,8 +10248,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 			crtc_state->min_voltage_level;
 
 		intel_bw_crtc_update(bw_state, crtc_state);
-
-		intel_pipe_config_sanity_check(dev_priv, crtc_state);
 	}
 }
 
-- 
2.35.1

Re: [Intel-gfx] [PATCH 14/26] drm/i915: Skip FDI vs. dotclock sanity check during readout

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The VBIOS/GOP may not program the FDI M/n vs. dotclock entirely
> consistently. Eg. on a SNB Thinkpad X220 LVDS I see dotclock of
> 69.286 MHz (the best the DPLL can do) vs. FDI M/N 69.3 MHz
> (matches what the EDID actually declares).
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 2 --
>  1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 1a25addadc21..86971be92e57 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -10248,8 +10248,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
>  			crtc_state->min_voltage_level;
>  
>  		intel_bw_crtc_update(bw_state, crtc_state);
> -
> -		intel_pipe_config_sanity_check(dev_priv, crtc_state);
>  	}
>  }

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 15/26] drm/i915: Make M/N checks non-fuzzy

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Now that we no longer fuzz M/N during fastset these should
match exctly.

TODO: we may need to do something for fastboot here as the
VBIOS/GOP may not compute M/N exactly the same way we do.
Though I guess we could try to match the VBIOS/GOP exactly.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 49 ++++----------------
 1 file changed, 8 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 86971be92e57..198c6340a463 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5832,47 +5832,15 @@ bool intel_fuzzy_clock_check(int clock1, int clock2)
 	return false;
 }
 
-static bool
-intel_compare_m_n(unsigned int m, unsigned int n,
-		  unsigned int m2, unsigned int n2,
-		  bool exact)
-{
-	if (m == m2 && n == n2)
-		return true;
-
-	if (exact || !m || !n || !m2 || !n2)
-		return false;
-
-	BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
-
-	if (n > n2) {
-		while (n > n2) {
-			m2 <<= 1;
-			n2 <<= 1;
-		}
-	} else if (n < n2) {
-		while (n < n2) {
-			m <<= 1;
-			n <<= 1;
-		}
-	}
-
-	if (n != n2)
-		return false;
-
-	return intel_fuzzy_clock_check(m, m2);
-}
-
 static bool
 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
-		       const struct intel_link_m_n *m2_n2,
-		       bool exact)
+		       const struct intel_link_m_n *m2_n2)
 {
 	return m_n->tu == m2_n2->tu &&
-		intel_compare_m_n(m_n->data_m, m_n->data_n,
-				  m2_n2->data_m, m2_n2->data_n, exact) &&
-		intel_compare_m_n(m_n->link_m, m_n->link_n,
-				  m2_n2->link_m, m2_n2->link_n, exact);
+		m_n->data_m == m2_n2->data_m &&
+		m_n->data_n == m2_n2->data_n &&
+		m_n->link_m == m2_n2->link_m &&
+		m_n->link_n == m2_n2->link_n;
 }
 
 static bool
@@ -6066,8 +6034,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 
 #define PIPE_CONF_CHECK_M_N(name) do { \
 	if (!intel_compare_link_m_n(&current_config->name, \
-				    &pipe_config->name,\
-				    !fastset)) { \
+				    &pipe_config->name)) { \
 		pipe_config_mismatch(fastset, crtc, __stringify(name), \
 				     "(expected tu %i data %i/%i link %i/%i, " \
 				     "found tu %i, data %i/%i link %i/%i)", \
@@ -6114,9 +6081,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
  */
 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
 	if (!intel_compare_link_m_n(&current_config->name, \
-				    &pipe_config->name, !fastset) && \
+				    &pipe_config->name) && \
 	    !intel_compare_link_m_n(&current_config->alt_name, \
-				    &pipe_config->name, !fastset)) { \
+				    &pipe_config->name)) { \
 		pipe_config_mismatch(fastset, crtc, __stringify(name), \
 				     "(expected tu %i data %i/%i link %i/%i, " \
 				     "or tu %i data %i/%i link %i/%i, " \
-- 
2.35.1

Re: [Intel-gfx] [PATCH 15/26] drm/i915: Make M/N checks non-fuzzy

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Now that we no longer fuzz M/N during fastset these should
> match exctly.
>
> TODO: we may need to do something for fastboot here as the
> VBIOS/GOP may not compute M/N exactly the same way we do.
> Though I guess we could try to match the VBIOS/GOP exactly.

I see that later patches change the M/N calculation, and that may be
enough.

But if GOP isn't consistent about this (I don't know), it's going to be
whack-a-mole if we get regression reports on not having fastboot.

Mmh. If we support seamless M/N change, could we do that on fastboot?

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 49 ++++----------------
>  1 file changed, 8 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 86971be92e57..198c6340a463 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5832,47 +5832,15 @@ bool intel_fuzzy_clock_check(int clock1, int clock2)
>  	return false;
>  }
>  
> -static bool
> -intel_compare_m_n(unsigned int m, unsigned int n,
> -		  unsigned int m2, unsigned int n2,
> -		  bool exact)
> -{
> -	if (m == m2 && n == n2)
> -		return true;
> -
> -	if (exact || !m || !n || !m2 || !n2)
> -		return false;
> -
> -	BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
> -
> -	if (n > n2) {
> -		while (n > n2) {
> -			m2 <<= 1;
> -			n2 <<= 1;
> -		}
> -	} else if (n < n2) {
> -		while (n < n2) {
> -			m <<= 1;
> -			n <<= 1;
> -		}
> -	}
> -
> -	if (n != n2)
> -		return false;
> -
> -	return intel_fuzzy_clock_check(m, m2);
> -}
> -
>  static bool
>  intel_compare_link_m_n(const struct intel_link_m_n *m_n,
> -		       const struct intel_link_m_n *m2_n2,
> -		       bool exact)
> +		       const struct intel_link_m_n *m2_n2)
>  {
>  	return m_n->tu == m2_n2->tu &&
> -		intel_compare_m_n(m_n->data_m, m_n->data_n,
> -				  m2_n2->data_m, m2_n2->data_n, exact) &&
> -		intel_compare_m_n(m_n->link_m, m_n->link_n,
> -				  m2_n2->link_m, m2_n2->link_n, exact);
> +		m_n->data_m == m2_n2->data_m &&
> +		m_n->data_n == m2_n2->data_n &&
> +		m_n->link_m == m2_n2->link_m &&
> +		m_n->link_n == m2_n2->link_n;
>  }
>  
>  static bool
> @@ -6066,8 +6034,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  
>  #define PIPE_CONF_CHECK_M_N(name) do { \
>  	if (!intel_compare_link_m_n(&current_config->name, \
> -				    &pipe_config->name,\
> -				    !fastset)) { \
> +				    &pipe_config->name)) { \
>  		pipe_config_mismatch(fastset, crtc, __stringify(name), \
>  				     "(expected tu %i data %i/%i link %i/%i, " \
>  				     "found tu %i, data %i/%i link %i/%i)", \
> @@ -6114,9 +6081,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>   */
>  #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
>  	if (!intel_compare_link_m_n(&current_config->name, \
> -				    &pipe_config->name, !fastset) && \
> +				    &pipe_config->name) && \
>  	    !intel_compare_link_m_n(&current_config->alt_name, \
> -				    &pipe_config->name, !fastset)) { \
> +				    &pipe_config->name)) { \
>  		pipe_config_mismatch(fastset, crtc, __stringify(name), \
>  				     "(expected tu %i data %i/%i link %i/%i, " \
>  				     "or tu %i data %i/%i link %i/%i, " \

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 16/26] drm/i915: Make all clock checks non-fuzzy

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Now that we backfeed the actual DPLL frequency into the
compute crtc state all our clocks should come out exact.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 22 +++++---------------
 1 file changed, 5 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 198c6340a463..066b9e7a5696 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6118,16 +6118,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	} \
 } while (0)
 
-#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
-	if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
-		pipe_config_mismatch(fastset, crtc, __stringify(name), \
-				     "(expected %i, found %i)", \
-				     current_config->name, \
-				     pipe_config->name); \
-		ret = false; \
-	} \
-} while (0)
-
 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
 	if (!intel_compare_infoframe(&current_config->infoframes.name, \
 				     &pipe_config->infoframes.name)) { \
@@ -6242,7 +6232,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_RECT(pch_pfit.dst);
 
 		PIPE_CONF_CHECK_I(scaler_state.scaler_id);
-		PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
+		PIPE_CONF_CHECK_I(pixel_rate);
 
 		PIPE_CONF_CHECK_X(gamma_mode);
 		if (IS_CHERRYVIEW(dev_priv))
@@ -6312,9 +6302,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
 		PIPE_CONF_CHECK_I(pipe_bpp);
 
-	PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
-	PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
-	PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
+	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
+	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
+	PIPE_CONF_CHECK_I(port_clock);
 
 	PIPE_CONF_CHECK_I(min_voltage_level);
 
@@ -6358,7 +6348,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
 #undef PIPE_CONF_CHECK_P
 #undef PIPE_CONF_CHECK_FLAGS
-#undef PIPE_CONF_CHECK_CLOCK_FUZZY
 #undef PIPE_CONF_CHECK_COLOR_LUT
 #undef PIPE_CONF_CHECK_TIMINGS
 #undef PIPE_CONF_CHECK_RECT
@@ -6379,8 +6368,7 @@ static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
 		 * FDI already provided one idea for the dotclock.
 		 * Yell if the encoder disagrees.
 		 */
-		drm_WARN(&dev_priv->drm,
-			 !intel_fuzzy_clock_check(fdi_dotclock, dotclock),
+		drm_WARN(&dev_priv->drm, fdi_dotclock != dotclock,
 			 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
 			 fdi_dotclock, dotclock);
 	}
-- 
2.35.1

Re: [Intel-gfx] [PATCH 16/26] drm/i915: Make all clock checks non-fuzzy

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Now that we backfeed the actual DPLL frequency into the
> compute crtc state all our clocks should come out exact.

/me looks at where intel_fuzzy_clock_check() is still used, and it's of
course DSI. Maybe we could move the function there until we figure it
out.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 22 +++++---------------
>  1 file changed, 5 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 198c6340a463..066b9e7a5696 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6118,16 +6118,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	} \
>  } while (0)
>  
> -#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
> -	if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
> -		pipe_config_mismatch(fastset, crtc, __stringify(name), \
> -				     "(expected %i, found %i)", \
> -				     current_config->name, \
> -				     pipe_config->name); \
> -		ret = false; \
> -	} \
> -} while (0)
> -
>  #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
>  	if (!intel_compare_infoframe(&current_config->infoframes.name, \
>  				     &pipe_config->infoframes.name)) { \
> @@ -6242,7 +6232,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  		PIPE_CONF_CHECK_RECT(pch_pfit.dst);
>  
>  		PIPE_CONF_CHECK_I(scaler_state.scaler_id);
> -		PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
> +		PIPE_CONF_CHECK_I(pixel_rate);
>  
>  		PIPE_CONF_CHECK_X(gamma_mode);
>  		if (IS_CHERRYVIEW(dev_priv))
> @@ -6312,9 +6302,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
>  		PIPE_CONF_CHECK_I(pipe_bpp);
>  
> -	PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
> -	PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
> -	PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
> +	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
> +	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
> +	PIPE_CONF_CHECK_I(port_clock);
>  
>  	PIPE_CONF_CHECK_I(min_voltage_level);
>  
> @@ -6358,7 +6348,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
>  #undef PIPE_CONF_CHECK_P
>  #undef PIPE_CONF_CHECK_FLAGS
> -#undef PIPE_CONF_CHECK_CLOCK_FUZZY
>  #undef PIPE_CONF_CHECK_COLOR_LUT
>  #undef PIPE_CONF_CHECK_TIMINGS
>  #undef PIPE_CONF_CHECK_RECT
> @@ -6379,8 +6368,7 @@ static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
>  		 * FDI already provided one idea for the dotclock.
>  		 * Yell if the encoder disagrees.
>  		 */
> -		drm_WARN(&dev_priv->drm,
> -			 !intel_fuzzy_clock_check(fdi_dotclock, dotclock),
> +		drm_WARN(&dev_priv->drm, fdi_dotclock != dotclock,
>  			 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
>  			 fdi_dotclock, dotclock);
>  	}

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 17/26] drm/i915: Set active dpll early for icl+

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

To make the fastboot checks at least somewhat sensible let's mark
the expected DPLL as the active one right after we finished the
state computation. Otherwise intel_pipe_config_compare() will
always be comparing things against NULL/0.

TODO: This is still not really right. If the previous commit
had to fall back to the other PLL then the comparisong will
now fail. I guess intel_pipe_config_compare() should rather
be comparing port_dplls[] instead. But to do that we really
should just unify every platform to use the port_dplls[]
approach whether they have any need for PLL fallbacks or not.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 416d78f9e140..6564d7baf978 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3225,6 +3225,9 @@ static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
 
 	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
 
+	/* this is mainly for the fastset check */
+	icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
+
 	crtc_state->port_clock = icl_ddi_combo_pll_get_freq(dev_priv, NULL,
 							    &port_dpll->hw_state);
 
@@ -3313,6 +3316,9 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
 	if (ret)
 		return ret;
 
+	/* this is mainly for the fastset check */
+	icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
+
 	crtc_state->port_clock = icl_ddi_mg_pll_get_freq(dev_priv, NULL,
 							 &port_dpll->hw_state);
 
-- 
2.35.1

Re: [Intel-gfx] [PATCH 17/26] drm/i915: Set active dpll early for icl+

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> To make the fastboot checks at least somewhat sensible let's mark
> the expected DPLL as the active one right after we finished the
> state computation. Otherwise intel_pipe_config_compare() will
> always be comparing things against NULL/0.
>
> TODO: This is still not really right. If the previous commit
> had to fall back to the other PLL then the comparisong will
> now fail. I guess intel_pipe_config_compare() should rather
> be comparing port_dplls[] instead. But to do that we really
> should just unify every platform to use the port_dplls[]
> approach whether they have any need for PLL fallbacks or not.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Acked-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 416d78f9e140..6564d7baf978 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -3225,6 +3225,9 @@ static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
>  
>  	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
>  
> +	/* this is mainly for the fastset check */
> +	icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
> +
>  	crtc_state->port_clock = icl_ddi_combo_pll_get_freq(dev_priv, NULL,
>  							    &port_dpll->hw_state);
>  
> @@ -3313,6 +3316,9 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
>  	if (ret)
>  		return ret;
>  
> +	/* this is mainly for the fastset check */
> +	icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
> +
>  	crtc_state->port_clock = icl_ddi_mg_pll_get_freq(dev_priv, NULL,
>  							 &port_dpll->hw_state);

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 18/26] drm/i915: Nuke fastet state copy hacks

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Now that we no longer do the fuzzy clock and M/N checks we can
get rid of the fastset state copy hacks.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 28 +++-----------------
 1 file changed, 3 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 066b9e7a5696..11e974d66c29 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7013,23 +7013,6 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
 	new_crtc_state->update_pipe = true;
 }
 
-static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state,
-				    struct intel_crtc_state *new_crtc_state)
-{
-	/*
-	 * If we're not doing the full modeset we want to
-	 * keep the current M/N values as they may be
-	 * sufficiently different to the computed values
-	 * to cause problems.
-	 *
-	 * FIXME: should really copy more fuzzy state here
-	 */
-	new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
-	new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
-	new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
-	new_crtc_state->has_drrs = old_crtc_state->has_drrs;
-}
-
 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
 					  struct intel_crtc *crtc,
 					  u8 plane_ids_mask)
@@ -7739,17 +7722,12 @@ static int intel_atomic_check(struct drm_device *dev,
 
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
 					    new_crtc_state, i) {
-		if (intel_crtc_needs_modeset(new_crtc_state)) {
-			any_ms = true;
-
-			intel_release_shared_dplls(state, crtc);
+		if (!intel_crtc_needs_modeset(new_crtc_state))
 			continue;
-		}
 
-		if (!new_crtc_state->update_pipe)
-			continue;
+		any_ms = true;
 
-		intel_crtc_copy_fastset(old_crtc_state, new_crtc_state);
+		intel_release_shared_dplls(state, crtc);
 	}
 
 	if (any_ms && !check_digital_port_conflicts(state)) {
-- 
2.35.1

Re: [Intel-gfx] [PATCH 18/26] drm/i915: Nuke fastet state copy hacks

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Now that we no longer do the fuzzy clock and M/N checks we can
> get rid of the fastset state copy hacks.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 28 +++-----------------
>  1 file changed, 3 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 066b9e7a5696..11e974d66c29 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7013,23 +7013,6 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
>  	new_crtc_state->update_pipe = true;
>  }
>  
> -static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state,
> -				    struct intel_crtc_state *new_crtc_state)
> -{
> -	/*
> -	 * If we're not doing the full modeset we want to
> -	 * keep the current M/N values as they may be
> -	 * sufficiently different to the computed values
> -	 * to cause problems.
> -	 *
> -	 * FIXME: should really copy more fuzzy state here
> -	 */
> -	new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n;
> -	new_crtc_state->dp_m_n = old_crtc_state->dp_m_n;
> -	new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2;
> -	new_crtc_state->has_drrs = old_crtc_state->has_drrs;
> -}
> -
>  static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
>  					  struct intel_crtc *crtc,
>  					  u8 plane_ids_mask)
> @@ -7739,17 +7722,12 @@ static int intel_atomic_check(struct drm_device *dev,
>  
>  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>  					    new_crtc_state, i) {
> -		if (intel_crtc_needs_modeset(new_crtc_state)) {
> -			any_ms = true;
> -
> -			intel_release_shared_dplls(state, crtc);
> +		if (!intel_crtc_needs_modeset(new_crtc_state))
>  			continue;
> -		}
>  
> -		if (!new_crtc_state->update_pipe)
> -			continue;
> +		any_ms = true;
>  
> -		intel_crtc_copy_fastset(old_crtc_state, new_crtc_state);
> +		intel_release_shared_dplls(state, crtc);
>  	}
>  
>  	if (any_ms && !check_digital_port_conflicts(state)) {

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 19/26] drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not enabled

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

No sense in calling intel_modeset_pipe_config_late() for a disabled
pipe.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 11e974d66c29..a81d866bdb19 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7669,9 +7669,11 @@ static int intel_atomic_check(struct drm_device *dev,
 		if (!intel_crtc_needs_modeset(new_crtc_state))
 			continue;
 
-		ret = intel_modeset_pipe_config_late(state, crtc);
-		if (ret)
-			goto fail;
+		if (new_crtc_state->hw.enable) {
+			ret = intel_modeset_pipe_config_late(state, crtc);
+			if (ret)
+				goto fail;
+		}
 
 		intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
 	}
-- 
2.35.1

Re: [Intel-gfx] [PATCH 19/26] drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not enabled

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> No sense in calling intel_modeset_pipe_config_late() for a disabled
> pipe.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 11e974d66c29..a81d866bdb19 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7669,9 +7669,11 @@ static int intel_atomic_check(struct drm_device *dev,
>  		if (!intel_crtc_needs_modeset(new_crtc_state))
>  			continue;
>  
> -		ret = intel_modeset_pipe_config_late(state, crtc);
> -		if (ret)
> -			goto fail;
> +		if (new_crtc_state->hw.enable) {
> +			ret = intel_modeset_pipe_config_late(state, crtc);
> +			if (ret)
> +				goto fail;
> +		}
>  
>  		intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
>  	}

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 20/26] drm/i915: Check hw.enable and hw.active in intel_pipe_config_compare()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Don't see a real reson not to check hw.active and hw.enable in
intel_pipe_config_compare(). We do have some checks for them
at a higher level, but I think better check them also in
intel_pipe_config_compare() in case something else doesn't
do a thorough enough job.

Also shuffle the mst_master_transcoder check next to the
cpu_transcoder check for a bit of consistency.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a81d866bdb19..2acc5f3a2c0e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6160,7 +6160,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 #define PIPE_CONF_QUIRK(quirk) \
 	((current_config->quirks | pipe_config->quirks) & (quirk))
 
+	PIPE_CONF_CHECK_I(hw.enable);
+	PIPE_CONF_CHECK_I(hw.active);
+
 	PIPE_CONF_CHECK_I(cpu_transcoder);
+	PIPE_CONF_CHECK_I(mst_master_transcoder);
 
 	PIPE_CONF_CHECK_BOOL(has_pch_encoder);
 	PIPE_CONF_CHECK_I(fdi_lanes);
@@ -6333,8 +6337,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_I(splitter.link_count);
 	PIPE_CONF_CHECK_I(splitter.pixel_overlap);
 
-	PIPE_CONF_CHECK_I(mst_master_transcoder);
-
 	PIPE_CONF_CHECK_BOOL(vrr.enable);
 	PIPE_CONF_CHECK_I(vrr.vmin);
 	PIPE_CONF_CHECK_I(vrr.vmax);
-- 
2.35.1

Re: [Intel-gfx] [PATCH 20/26] drm/i915: Check hw.enable and hw.active in intel_pipe_config_compare()

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Don't see a real reson not to check hw.active and hw.enable in
> intel_pipe_config_compare(). We do have some checks for them
> at a higher level, but I think better check them also in
> intel_pipe_config_compare() in case something else doesn't
> do a thorough enough job.
>
> Also shuffle the mst_master_transcoder check next to the
> cpu_transcoder check for a bit of consistency.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a81d866bdb19..2acc5f3a2c0e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6160,7 +6160,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  #define PIPE_CONF_QUIRK(quirk) \
>  	((current_config->quirks | pipe_config->quirks) & (quirk))
>  
> +	PIPE_CONF_CHECK_I(hw.enable);
> +	PIPE_CONF_CHECK_I(hw.active);
> +
>  	PIPE_CONF_CHECK_I(cpu_transcoder);
> +	PIPE_CONF_CHECK_I(mst_master_transcoder);
>  
>  	PIPE_CONF_CHECK_BOOL(has_pch_encoder);
>  	PIPE_CONF_CHECK_I(fdi_lanes);
> @@ -6333,8 +6337,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	PIPE_CONF_CHECK_I(splitter.link_count);
>  	PIPE_CONF_CHECK_I(splitter.pixel_overlap);
>  
> -	PIPE_CONF_CHECK_I(mst_master_transcoder);
> -
>  	PIPE_CONF_CHECK_BOOL(vrr.enable);
>  	PIPE_CONF_CHECK_I(vrr.vmin);
>  	PIPE_CONF_CHECK_I(vrr.vmax);

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 21/26] drm/i915: Add intel_panel_highest_mode()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add a function to get the fixed_mode with the highest clock.
The plan is to use this for the link bw calculation on seamless
DRRS panels so that we alwasy end up with the same link params
regardless of the requested refresh rate. This will allow fastset
to do seamless refresh rate changes based on userspace request
instead of having to go for a full modeset.

TODO: the function name isn't great

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_panel.c | 15 +++++++++++++++
 drivers/gpu/drm/i915/display/intel_panel.h |  3 +++
 2 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 03398feb6676..0121d38fc36c 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -89,6 +89,21 @@ intel_panel_downclock_mode(struct intel_connector *connector,
 	return best_mode;
 }
 
+const struct drm_display_mode *
+intel_panel_highest_mode(struct intel_connector *connector,
+			 const struct drm_display_mode *adjusted_mode)
+{
+	const struct drm_display_mode *fixed_mode, *best_mode = adjusted_mode;
+
+	/* pick the fixed_mode that has the highest clock */
+	list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head) {
+		if (fixed_mode->clock > best_mode->clock)
+			best_mode = fixed_mode;
+	}
+
+	return best_mode;
+}
+
 int intel_panel_get_modes(struct intel_connector *connector)
 {
 	const struct drm_display_mode *fixed_mode;
diff --git a/drivers/gpu/drm/i915/display/intel_panel.h b/drivers/gpu/drm/i915/display/intel_panel.h
index 2e32bb728beb..8a3b84a53c44 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.h
+++ b/drivers/gpu/drm/i915/display/intel_panel.h
@@ -31,6 +31,9 @@ intel_panel_fixed_mode(struct intel_connector *connector,
 const struct drm_display_mode *
 intel_panel_downclock_mode(struct intel_connector *connector,
 			   const struct drm_display_mode *adjusted_mode);
+const struct drm_display_mode *
+intel_panel_highest_mode(struct intel_connector *connector,
+			 const struct drm_display_mode *adjusted_mode);
 int intel_panel_get_modes(struct intel_connector *connector);
 enum drrs_type intel_panel_drrs_type(struct intel_connector *connector);
 enum drm_mode_status
-- 
2.35.1

Re: [Intel-gfx] [PATCH 21/26] drm/i915: Add intel_panel_highest_mode()

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add a function to get the fixed_mode with the highest clock.
> The plan is to use this for the link bw calculation on seamless
> DRRS panels so that we alwasy end up with the same link params
> regardless of the requested refresh rate. This will allow fastset
> to do seamless refresh rate changes based on userspace request
> instead of having to go for a full modeset.
>
> TODO: the function name isn't great

Agreed.

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_panel.c | 15 +++++++++++++++
>  drivers/gpu/drm/i915/display/intel_panel.h |  3 +++
>  2 files changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
> index 03398feb6676..0121d38fc36c 100644
> --- a/drivers/gpu/drm/i915/display/intel_panel.c
> +++ b/drivers/gpu/drm/i915/display/intel_panel.c
> @@ -89,6 +89,21 @@ intel_panel_downclock_mode(struct intel_connector *connector,
>  	return best_mode;
>  }
>  
> +const struct drm_display_mode *
> +intel_panel_highest_mode(struct intel_connector *connector,
> +			 const struct drm_display_mode *adjusted_mode)
> +{
> +	const struct drm_display_mode *fixed_mode, *best_mode = adjusted_mode;
> +
> +	/* pick the fixed_mode that has the highest clock */
> +	list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head) {
> +		if (fixed_mode->clock > best_mode->clock)
> +			best_mode = fixed_mode;
> +	}
> +
> +	return best_mode;
> +}
> +
>  int intel_panel_get_modes(struct intel_connector *connector)
>  {
>  	const struct drm_display_mode *fixed_mode;
> diff --git a/drivers/gpu/drm/i915/display/intel_panel.h b/drivers/gpu/drm/i915/display/intel_panel.h
> index 2e32bb728beb..8a3b84a53c44 100644
> --- a/drivers/gpu/drm/i915/display/intel_panel.h
> +++ b/drivers/gpu/drm/i915/display/intel_panel.h
> @@ -31,6 +31,9 @@ intel_panel_fixed_mode(struct intel_connector *connector,
>  const struct drm_display_mode *
>  intel_panel_downclock_mode(struct intel_connector *connector,
>  			   const struct drm_display_mode *adjusted_mode);
> +const struct drm_display_mode *
> +intel_panel_highest_mode(struct intel_connector *connector,
> +			 const struct drm_display_mode *adjusted_mode);
>  int intel_panel_get_modes(struct intel_connector *connector);
>  enum drrs_type intel_panel_drrs_type(struct intel_connector *connector);
>  enum drm_mode_status

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 22/26] drm/i915: Allow M/N change during fastset on bdw+

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On BDW+ M/N are double buffered and so we can easily reprogram them
during a fastset. So for eDP panels that support seamless DRRS we
can just change these without a full modeset.

For earlier platforms we'd need to play tricks with M1/N1 vs.
M2/N2 during the fastset to make sure we do the switch atomically.
Not sure the added complexity is worth the hassle, so leave it
alone for now.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 13 +++++++---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 26 +++++++++++++++----
 3 files changed, 32 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2acc5f3a2c0e..f30bdcdd4c84 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6174,7 +6174,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_X(lane_lat_optim_mask);
 
 	if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) {
-		PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
+		if (!fastset || !pipe_config->seamless_m_n)
+			PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
 	} else {
 		PIPE_CONF_CHECK_M_N(dp_m_n);
 		PIPE_CONF_CHECK_M_N(dp_m2_n2);
@@ -6306,8 +6307,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
 		PIPE_CONF_CHECK_I(pipe_bpp);
 
-	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
-	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
+	if (!fastset || !pipe_config->seamless_m_n) {
+		PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
+		PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
+	}
 	PIPE_CONF_CHECK_I(port_clock);
 
 	PIPE_CONF_CHECK_I(min_voltage_level);
@@ -7890,6 +7893,10 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
 	if (DISPLAY_VER(dev_priv) >= 9 ||
 	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
 		hsw_set_linetime_wm(new_crtc_state);
+
+	if (new_crtc_state->seamless_m_n)
+		intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
+					       &new_crtc_state->dp_m_n);
 }
 
 static void commit_pipe_pre_planes(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 408152f9f46a..fb58893510a1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1057,6 +1057,7 @@ struct intel_crtc_state {
 	/* m2_n2 for eDP downclock */
 	struct intel_link_m_n dp_m2_n2;
 	bool has_drrs;
+	bool seamless_m_n;
 
 	/* PSR is supported but might not be enabled due the lack of enabled planes */
 	bool has_psr;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e4a79c11fd25..9385178c7fd6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1270,21 +1270,33 @@ intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
 	}
 }
 
+static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
+			       const struct drm_connector_state *conn_state)
+{
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+
+	/* FIXME a bit of a mess wrt clock vs. crtc_clock */
+	if (intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS)
+		return intel_panel_highest_mode(connector, adjusted_mode)->clock;
+	else
+		return adjusted_mode->crtc_clock;
+}
+
 /* Optimize link config in order: max bpp, min clock, min lanes */
 static int
 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
 				  struct intel_crtc_state *pipe_config,
+				  const struct drm_connector_state *conn_state,
 				  const struct link_config_limits *limits)
 {
-	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
-	int bpp, i, lane_count;
+	int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
 	int mode_rate, link_rate, link_avail;
 
 	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
 		int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
 
-		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
-						   output_bpp);
+		mode_rate = intel_dp_link_required(clock, output_bpp);
 
 		for (i = 0; i < intel_dp->num_common_rates; i++) {
 			link_rate = intel_dp_common_rate(intel_dp, i);
@@ -1584,7 +1596,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 	 * Optimize for slow and wide for everything, because there are some
 	 * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
 	 */
-	ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
+	ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, conn_state, &limits);
 
 	if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) {
 		drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
@@ -1873,6 +1885,10 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
 		intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
 	int pixel_clock;
 
+	if ((DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915)) &&
+	    intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS)
+		pipe_config->seamless_m_n = true;
+
 	if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
 		if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
 			intel_zero_m_n(&pipe_config->dp_m2_n2);
-- 
2.35.1

Re: [Intel-gfx] [PATCH 22/26] drm/i915: Allow M/N change during fastset on bdw+

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> On BDW+ M/N are double buffered and so we can easily reprogram them
> during a fastset. So for eDP panels that support seamless DRRS we
> can just change these without a full modeset.
>
> For earlier platforms we'd need to play tricks with M1/N1 vs.
> M2/N2 during the fastset to make sure we do the switch atomically.
> Not sure the added complexity is worth the hassle, so leave it
> alone for now.

I guess the commit message should mention this bumps the bandwidth
requirement for eDP to the native mode with the max refresh rate.

It's also not obvious to me this takes link training fallback into
account. AFAICT the modes get pruned, but the userspace switching to a
different mode does not help?

One nitpick inline below.

BR,
Jani.

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  | 13 +++++++---
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c       | 26 +++++++++++++++----
>  3 files changed, 32 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 2acc5f3a2c0e..f30bdcdd4c84 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6174,7 +6174,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	PIPE_CONF_CHECK_X(lane_lat_optim_mask);
>  
>  	if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) {
> -		PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
> +		if (!fastset || !pipe_config->seamless_m_n)
> +			PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
>  	} else {
>  		PIPE_CONF_CHECK_M_N(dp_m_n);
>  		PIPE_CONF_CHECK_M_N(dp_m2_n2);
> @@ -6306,8 +6307,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
>  		PIPE_CONF_CHECK_I(pipe_bpp);
>  
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
> +	if (!fastset || !pipe_config->seamless_m_n) {
> +		PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
> +		PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
> +	}
>  	PIPE_CONF_CHECK_I(port_clock);
>  
>  	PIPE_CONF_CHECK_I(min_voltage_level);
> @@ -7890,6 +7893,10 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
>  	if (DISPLAY_VER(dev_priv) >= 9 ||
>  	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
>  		hsw_set_linetime_wm(new_crtc_state);
> +
> +	if (new_crtc_state->seamless_m_n)
> +		intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
> +					       &new_crtc_state->dp_m_n);
>  }
>  
>  static void commit_pipe_pre_planes(struct intel_atomic_state *state,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 408152f9f46a..fb58893510a1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1057,6 +1057,7 @@ struct intel_crtc_state {
>  	/* m2_n2 for eDP downclock */
>  	struct intel_link_m_n dp_m2_n2;
>  	bool has_drrs;
> +	bool seamless_m_n;
>  
>  	/* PSR is supported but might not be enabled due the lack of enabled planes */
>  	bool has_psr;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index e4a79c11fd25..9385178c7fd6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1270,21 +1270,33 @@ intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
>  	}
>  }
>  
> +static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
> +			       const struct drm_connector_state *conn_state)
> +{
> +	struct intel_connector *connector = to_intel_connector(conn_state->connector);
> +	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> +
> +	/* FIXME a bit of a mess wrt clock vs. crtc_clock */
> +	if (intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS)
> +		return intel_panel_highest_mode(connector, adjusted_mode)->clock;
> +	else
> +		return adjusted_mode->crtc_clock;
> +}
> +
>  /* Optimize link config in order: max bpp, min clock, min lanes */
>  static int
>  intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
>  				  struct intel_crtc_state *pipe_config,
> +				  const struct drm_connector_state *conn_state,
>  				  const struct link_config_limits *limits)
>  {
> -	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> -	int bpp, i, lane_count;
> +	int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
>  	int mode_rate, link_rate, link_avail;
>  
>  	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
>  		int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
>  
> -		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
> -						   output_bpp);
> +		mode_rate = intel_dp_link_required(clock, output_bpp);
>  
>  		for (i = 0; i < intel_dp->num_common_rates; i++) {
>  			link_rate = intel_dp_common_rate(intel_dp, i);
> @@ -1584,7 +1596,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>  	 * Optimize for slow and wide for everything, because there are some
>  	 * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
>  	 */
> -	ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
> +	ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, conn_state, &limits);
>  
>  	if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) {
>  		drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
> @@ -1873,6 +1885,10 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
>  		intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
>  	int pixel_clock;
>  
> +	if ((DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915)) &&

Seems like this condition is duplicated in a few places.

> +	    intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS)
> +		pipe_config->seamless_m_n = true;
> +
>  	if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
>  		if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
>  			intel_zero_m_n(&pipe_config->dp_m2_n2);

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 23/26] drm/i915: Require an exact DP link freq match for the DG2 PLL

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

No idea why the DG2 PLL DP link frequency calculation is allowing
a non-exact match. That makes no sense so get rid of it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 0dd4775e8195..877f9a4bd7a5 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -597,7 +597,7 @@ int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
 		return -EINVAL;
 
 	for (i = 0; tables[i]; i++) {
-		if (crtc_state->port_clock <= tables[i]->clock) {
+		if (crtc_state->port_clock == tables[i]->clock) {
 			crtc_state->mpllb_state = *tables[i];
 			return 0;
 		}
-- 
2.35.1

Re: [Intel-gfx] [PATCH 23/26] drm/i915: Require an exact DP link freq match for the DG2 PLL

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> No idea why the DG2 PLL DP link frequency calculation is allowing
> a non-exact match. That makes no sense so get rid of it.

Cc: Matt.

This also makes the hdmi link rate check in the same function redundant.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> index 0dd4775e8195..877f9a4bd7a5 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> @@ -597,7 +597,7 @@ int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
>  		return -EINVAL;
>  
>  	for (i = 0; tables[i]; i++) {
> -		if (crtc_state->port_clock <= tables[i]->clock) {
> +		if (crtc_state->port_clock == tables[i]->clock) {
>  			crtc_state->mpllb_state = *tables[i];
>  			return 0;
>  		}

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 23/26] drm/i915: Require an exact DP link freq match for the DG2 PLL

[Matt Roper]

On Wed, May 25, 2022 at 02:30:55PM +0300, Jani Nikula wrote:
> On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > No idea why the DG2 PLL DP link frequency calculation is allowing
> > a non-exact match. That makes no sense so get rid of it.
> 
> Cc: Matt.
> 
> This also makes the hdmi link rate check in the same function redundant.
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 

I don't remember any specific reason the code was written this way, so
the change looks okay to me.

Acked-by: Matt Roper <matthew.d.roper@intel.com>

> 
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> > index 0dd4775e8195..877f9a4bd7a5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> > @@ -597,7 +597,7 @@ int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
> >  		return -EINVAL;
> >  
> >  	for (i = 0; tables[i]; i++) {
> > -		if (crtc_state->port_clock <= tables[i]->clock) {
> > +		if (crtc_state->port_clock == tables[i]->clock) {
> >  			crtc_state->mpllb_state = *tables[i];
> >  			return 0;
> >  		}
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

[Intel-gfx] [PATCH 24/26] drm/i915: Use a fixed N value always

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Windows/BIOS always uses fixed N values. Let's match that
behaviour.

Allows us to also get rid of that constant_n quirk stuff.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 36 +++++++++-----------
 drivers/gpu/drm/i915/display/intel_display.h |  2 +-
 drivers/gpu/drm/i915/display/intel_dp.c      | 10 +++---
 drivers/gpu/drm/i915/display/intel_dp_mst.c  |  3 +-
 drivers/gpu/drm/i915/display/intel_fdi.c     |  2 +-
 5 files changed, 24 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f30bdcdd4c84..89a7c8c1be28 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2848,19 +2848,11 @@ intel_reduce_m_n_ratio(u32 *num, u32 *den)
 	}
 }
 
-static void compute_m_n(unsigned int m, unsigned int n,
-			u32 *ret_m, u32 *ret_n,
-			bool constant_n)
+static void compute_m_n(u32 *ret_m, u32 *ret_n,
+			u32 m, u32 n, u32 constant_n)
 {
-	/*
-	 * Several DP dongles in particular seem to be fussy about
-	 * too large link M/N values. Give N value as 0x8000 that
-	 * should be acceptable by specific devices. 0x8000 is the
-	 * specified fixed N value for asynchronous clock mode,
-	 * which the devices expect also in synchronous clock mode.
-	 */
 	if (constant_n)
-		*ret_n = DP_LINK_CONSTANT_N_VALUE;
+		*ret_n = constant_n;
 	else
 		*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
 
@@ -2872,22 +2864,28 @@ void
 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
 		       int pixel_clock, int link_clock,
 		       struct intel_link_m_n *m_n,
-		       bool constant_n, bool fec_enable)
+		       bool fec_enable)
 {
 	u32 data_clock = bits_per_pixel * pixel_clock;
 
 	if (fec_enable)
 		data_clock = intel_dp_mode_to_fec_clock(data_clock);
 
+	/*
+	 * Windows/BIOS uses fixed M/N values always. Follow suit.
+	 *
+	 * Also several DP dongles in particular seem to be fussy
+	 * about too large link M/N values. Presumably the 20bit
+	 * value used by Windows/BIOS is acceptable to everyone.
+	 */
 	m_n->tu = 64;
-	compute_m_n(data_clock,
-		    link_clock * nlanes * 8,
-		    &m_n->data_m, &m_n->data_n,
-		    constant_n);
+	compute_m_n(&m_n->data_m, &m_n->data_n,
+		    data_clock, link_clock * nlanes * 8,
+		    0x8000000);
 
-	compute_m_n(pixel_clock, link_clock,
-		    &m_n->link_m, &m_n->link_n,
-		    constant_n);
+	compute_m_n(&m_n->link_m, &m_n->link_n,
+		    pixel_clock, link_clock,
+		    0x80000);
 }
 
 static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 187910d94ec6..862338b6c4fa 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -546,7 +546,7 @@ u8 intel_calc_active_pipes(struct intel_atomic_state *state,
 void intel_link_compute_m_n(u16 bpp, int nlanes,
 			    int pixel_clock, int link_clock,
 			    struct intel_link_m_n *m_n,
-			    bool constant_n, bool fec_enable);
+			    bool fec_enable);
 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 			      u32 pixel_format, u64 modifier);
 enum drm_mode_status
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9385178c7fd6..d10f05d40360 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1878,7 +1878,7 @@ static bool can_enable_drrs(struct intel_connector *connector,
 static void
 intel_dp_drrs_compute_config(struct intel_connector *connector,
 			     struct intel_crtc_state *pipe_config,
-			     int output_bpp, bool constant_n)
+			     int output_bpp)
 {
 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
 	const struct drm_display_mode *downclock_mode =
@@ -1906,7 +1906,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
 
 	intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
 			       pipe_config->port_clock, &pipe_config->dp_m2_n2,
-			       constant_n, pipe_config->fec_enable);
+			       pipe_config->fec_enable);
 
 	/* FIXME: abstract this better */
 	if (pipe_config->splitter.enable)
@@ -1981,7 +1981,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	const struct drm_display_mode *fixed_mode;
 	struct intel_connector *connector = intel_dp->attached_connector;
-	bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);
 	int ret = 0, output_bpp;
 
 	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
@@ -2060,7 +2059,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 			       adjusted_mode->crtc_clock,
 			       pipe_config->port_clock,
 			       &pipe_config->dp_m_n,
-			       constant_n, pipe_config->fec_enable);
+			       pipe_config->fec_enable);
 
 	/* FIXME: abstract this better */
 	if (pipe_config->splitter.enable)
@@ -2071,8 +2070,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 
 	intel_vrr_compute_config(pipe_config, conn_state);
 	intel_psr_compute_config(intel_dp, pipe_config, conn_state);
-	intel_dp_drrs_compute_config(connector, pipe_config,
-				     output_bpp, constant_n);
+	intel_dp_drrs_compute_config(connector, pipe_config, output_bpp);
 	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
 	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 061b277e5ce7..00e55555091a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -57,7 +57,6 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
-	bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);
 	int bpp, slots = -EINVAL;
 
 	crtc_state->lane_count = limits->max_lane_count;
@@ -93,7 +92,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
 			       adjusted_mode->crtc_clock,
 			       crtc_state->port_clock,
 			       &crtc_state->dp_m_n,
-			       constant_n, crtc_state->fec_enable);
+			       crtc_state->fec_enable);
 	crtc_state->dp_m_n.tu = slots;
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 67d2484afbaa..0dc6414a56c4 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -256,7 +256,7 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
 	pipe_config->fdi_lanes = lane;
 
 	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
-			       link_bw, &pipe_config->fdi_m_n, false, false);
+			       link_bw, &pipe_config->fdi_m_n, false);
 
 	ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config);
 	if (ret == -EDEADLK)
-- 
2.35.1

Re: [Intel-gfx] [PATCH 24/26] drm/i915: Use a fixed N value always

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Windows/BIOS always uses fixed N values. Let's match that
> behaviour.
>
> Allows us to also get rid of that constant_n quirk stuff.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 36 +++++++++-----------
>  drivers/gpu/drm/i915/display/intel_display.h |  2 +-
>  drivers/gpu/drm/i915/display/intel_dp.c      | 10 +++---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c  |  3 +-
>  drivers/gpu/drm/i915/display/intel_fdi.c     |  2 +-
>  5 files changed, 24 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f30bdcdd4c84..89a7c8c1be28 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2848,19 +2848,11 @@ intel_reduce_m_n_ratio(u32 *num, u32 *den)
>  	}
>  }
>  
> -static void compute_m_n(unsigned int m, unsigned int n,
> -			u32 *ret_m, u32 *ret_n,
> -			bool constant_n)
> +static void compute_m_n(u32 *ret_m, u32 *ret_n,
> +			u32 m, u32 n, u32 constant_n)
>  {
> -	/*
> -	 * Several DP dongles in particular seem to be fussy about
> -	 * too large link M/N values. Give N value as 0x8000 that
> -	 * should be acceptable by specific devices. 0x8000 is the
> -	 * specified fixed N value for asynchronous clock mode,
> -	 * which the devices expect also in synchronous clock mode.
> -	 */
>  	if (constant_n)
> -		*ret_n = DP_LINK_CONSTANT_N_VALUE;
> +		*ret_n = constant_n;
>  	else
>  		*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
>  
> @@ -2872,22 +2864,28 @@ void
>  intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
>  		       int pixel_clock, int link_clock,
>  		       struct intel_link_m_n *m_n,
> -		       bool constant_n, bool fec_enable)
> +		       bool fec_enable)
>  {
>  	u32 data_clock = bits_per_pixel * pixel_clock;
>  
>  	if (fec_enable)
>  		data_clock = intel_dp_mode_to_fec_clock(data_clock);
>  
> +	/*
> +	 * Windows/BIOS uses fixed M/N values always. Follow suit.
> +	 *
> +	 * Also several DP dongles in particular seem to be fussy
> +	 * about too large link M/N values. Presumably the 20bit
> +	 * value used by Windows/BIOS is acceptable to everyone.
> +	 */
>  	m_n->tu = 64;
> -	compute_m_n(data_clock,
> -		    link_clock * nlanes * 8,
> -		    &m_n->data_m, &m_n->data_n,
> -		    constant_n);
> +	compute_m_n(&m_n->data_m, &m_n->data_n,
> +		    data_clock, link_clock * nlanes * 8,
> +		    0x8000000);
>  
> -	compute_m_n(pixel_clock, link_clock,
> -		    &m_n->link_m, &m_n->link_n,
> -		    constant_n);
> +	compute_m_n(&m_n->link_m, &m_n->link_n,
> +		    pixel_clock, link_clock,
> +		    0x80000);
>  }
>  
>  static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 187910d94ec6..862338b6c4fa 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -546,7 +546,7 @@ u8 intel_calc_active_pipes(struct intel_atomic_state *state,
>  void intel_link_compute_m_n(u16 bpp, int nlanes,
>  			    int pixel_clock, int link_clock,
>  			    struct intel_link_m_n *m_n,
> -			    bool constant_n, bool fec_enable);
> +			    bool fec_enable);
>  u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
>  			      u32 pixel_format, u64 modifier);
>  enum drm_mode_status
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 9385178c7fd6..d10f05d40360 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1878,7 +1878,7 @@ static bool can_enable_drrs(struct intel_connector *connector,
>  static void
>  intel_dp_drrs_compute_config(struct intel_connector *connector,
>  			     struct intel_crtc_state *pipe_config,
> -			     int output_bpp, bool constant_n)
> +			     int output_bpp)
>  {
>  	struct drm_i915_private *i915 = to_i915(connector->base.dev);
>  	const struct drm_display_mode *downclock_mode =
> @@ -1906,7 +1906,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
>  
>  	intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock,
>  			       pipe_config->port_clock, &pipe_config->dp_m2_n2,
> -			       constant_n, pipe_config->fec_enable);
> +			       pipe_config->fec_enable);
>  
>  	/* FIXME: abstract this better */
>  	if (pipe_config->splitter.enable)
> @@ -1981,7 +1981,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	const struct drm_display_mode *fixed_mode;
>  	struct intel_connector *connector = intel_dp->attached_connector;
> -	bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);
>  	int ret = 0, output_bpp;
>  
>  	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
> @@ -2060,7 +2059,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  			       adjusted_mode->crtc_clock,
>  			       pipe_config->port_clock,
>  			       &pipe_config->dp_m_n,
> -			       constant_n, pipe_config->fec_enable);
> +			       pipe_config->fec_enable);
>  
>  	/* FIXME: abstract this better */
>  	if (pipe_config->splitter.enable)
> @@ -2071,8 +2070,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  
>  	intel_vrr_compute_config(pipe_config, conn_state);
>  	intel_psr_compute_config(intel_dp, pipe_config, conn_state);
> -	intel_dp_drrs_compute_config(connector, pipe_config,
> -				     output_bpp, constant_n);
> +	intel_dp_drrs_compute_config(connector, pipe_config, output_bpp);
>  	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
>  	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 061b277e5ce7..00e55555091a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -57,7 +57,6 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
>  	struct drm_i915_private *i915 = to_i915(connector->base.dev);
>  	const struct drm_display_mode *adjusted_mode =
>  		&crtc_state->hw.adjusted_mode;
> -	bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N);
>  	int bpp, slots = -EINVAL;
>  
>  	crtc_state->lane_count = limits->max_lane_count;
> @@ -93,7 +92,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
>  			       adjusted_mode->crtc_clock,
>  			       crtc_state->port_clock,
>  			       &crtc_state->dp_m_n,
> -			       constant_n, crtc_state->fec_enable);
> +			       crtc_state->fec_enable);
>  	crtc_state->dp_m_n.tu = slots;
>  
>  	return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> index 67d2484afbaa..0dc6414a56c4 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -256,7 +256,7 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
>  	pipe_config->fdi_lanes = lane;
>  
>  	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> -			       link_bw, &pipe_config->fdi_m_n, false, false);
> +			       link_bw, &pipe_config->fdi_m_n, false);
>  
>  	ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config);
>  	if (ret == -EDEADLK)

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 25/26] drm/i915: Round to closest in M/N calculations

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Rounding to nearest is what we do for most other clock calculations
so should probably do that for M/N too.

TODO: GOP seems to truncate instead so fastboot is going to be
a PITA to get right. Not sure what to do about it yet.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 89a7c8c1be28..c4257630a3fe 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2856,7 +2856,7 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n,
 	else
 		*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
 
-	*ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
+	*ret_m = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(m, *ret_n), n);
 	intel_reduce_m_n_ratio(ret_m, ret_n);
 }
 
@@ -4602,7 +4602,8 @@ int intel_dotclock_calculate(int link_freq,
 	if (!m_n->link_n)
 		return 0;
 
-	return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
+	return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(m_n->link_m, link_freq),
+				     m_n->link_n);
 }
 
 /* Returns the currently programmed mode of the given encoder. */
-- 
2.35.1

Re: [Intel-gfx] [PATCH 25/26] drm/i915: Round to closest in M/N calculations

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rounding to nearest is what we do for most other clock calculations
> so should probably do that for M/N too.
>
> TODO: GOP seems to truncate instead so fastboot is going to be
> a PITA to get right. Not sure what to do about it yet.

Meh. Damned if you do, damned if you don't.

Acked-by: Jani Nikula <jani.nikula@intel.com>

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 89a7c8c1be28..c4257630a3fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2856,7 +2856,7 @@ static void compute_m_n(u32 *ret_m, u32 *ret_n,
>  	else
>  		*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
>  
> -	*ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
> +	*ret_m = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(m, *ret_n), n);
>  	intel_reduce_m_n_ratio(ret_m, ret_n);
>  }
>  
> @@ -4602,7 +4602,8 @@ int intel_dotclock_calculate(int link_freq,
>  	if (!m_n->link_n)
>  		return 0;
>  
> -	return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n);
> +	return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(m_n->link_m, link_freq),
> +				     m_n->link_n);
>  }
>  
>  /* Returns the currently programmed mode of the given encoder. */

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH 26/26] drm/i915: Round TMDS clock to nearest

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use round-to-nearest behavour when calculating the TMDS clock.
Matches what we co for most other clock related things.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c  | 3 ++-
 drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 0cf2d4fba6a8..8b3e6ae85a08 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -330,7 +330,8 @@ int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
 		dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 						    &pipe_config->dp_m_n);
 	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
-		dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
+		dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24,
+					     pipe_config->pipe_bpp);
 	else
 		dotclock = pipe_config->port_clock;
 
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 1ae09431f53a..0b04b3800cd4 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1891,7 +1891,7 @@ int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output)
 	 *  1.5x for 12bpc
 	 *  1.25x for 10bpc
 	 */
-	return clock * bpc / 8;
+	return DIV_ROUND_CLOSEST(clock * bpc, 8);
 }
 
 static bool intel_hdmi_source_bpc_possible(struct drm_i915_private *i915, int bpc)
-- 
2.35.1

Re: [Intel-gfx] [PATCH 26/26] drm/i915: Round TMDS clock to nearest

[Jani Nikula]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use round-to-nearest behavour when calculating the TMDS clock.
> Matches what we co for most other clock related things.

*do

Acked-by: Jani Nikula <jani.nikula@intel.com>


>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c  | 3 ++-
>  drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
>  2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 0cf2d4fba6a8..8b3e6ae85a08 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -330,7 +330,8 @@ int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
>  		dotclock = intel_dotclock_calculate(pipe_config->port_clock,
>  						    &pipe_config->dp_m_n);
>  	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
> -		dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
> +		dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24,
> +					     pipe_config->pipe_bpp);
>  	else
>  		dotclock = pipe_config->port_clock;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 1ae09431f53a..0b04b3800cd4 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -1891,7 +1891,7 @@ int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output)
>  	 *  1.5x for 12bpc
>  	 *  1.25x for 10bpc
>  	 */
> -	return clock * bpc / 8;
> +	return DIV_ROUND_CLOSEST(clock * bpc, 8);
>  }
>  
>  static bool intel_hdmi_source_bpc_possible(struct drm_i915_private *i915, int bpc)

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Make fastset not suck and allow seamless M/N changes

[Patchwork]

== Series Details ==

Series: drm/i915: Make fastset not suck and allow seamless M/N changes
URL   : https://patchwork.freedesktop.org/series/103491/
State : failure

== Summary ==

Error: make failed
  CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  DESCEND objtool
  CHK     include/generated/compile.h
  CC [M]  drivers/gpu/drm/i915/display/intel_ddi.o
drivers/gpu/drm/i915/display/intel_ddi.c:325:5: error: no previous prototype for ‘intel_crtc_dotclock’ [-Werror=missing-prototypes]
 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
     ^~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
scripts/Makefile.build:288: recipe for target 'drivers/gpu/drm/i915/display/intel_ddi.o' failed
make[4]: *** [drivers/gpu/drm/i915/display/intel_ddi.o] Error 1
scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:550: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1834: recipe for target 'drivers' failed
make: *** [drivers] Error 2

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Make fastset not suck and allow seamless M/N changes (rev2)
URL   : https://patchwork.freedesktop.org/series/103491/
State : warning

== Summary ==

Error: dim checkpatch failed
e071bdd7839d drm/i915: Split shared dpll .get_dplls() into compute and get phases
-:194: CHECK:CAMELCASE: Avoid CamelCase: <SPLL_FREQ_1350MHz>
#194: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1063:
+		SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;

total: 0 errors, 0 warnings, 1 checks, 516 lines checked
c986a8eec081 drm/i915: Do .crtc_compute_clock() earlier
af15247e6cc6 drm/i915: Clean up DPLL related debugs
5524d78e52c7 drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
19a1131cf0b7 drm/i915: Extract PIPE_CONF_CHECK_TIMINGS()
-:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#21: FILE: drivers/gpu/drm/i915/display/intel_display.c:6076:
+#define PIPE_CONF_CHECK_TIMINGS(name) do { \
+	PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
+	PIPE_CONF_CHECK_I(name.crtc_htotal); \
+	PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
+	PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
+	PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
+	PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
+	PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
+	PIPE_CONF_CHECK_I(name.crtc_vtotal); \
+	PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
+	PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
+	PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
+	PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
+} while (0)

total: 0 errors, 0 warnings, 1 checks, 63 lines checked
f124e0c495ef drm/i915: Extract PIPE_CONF_CHECK_RECT()
-:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#21: FILE: drivers/gpu/drm/i915/display/intel_display.c:6091:
+#define PIPE_CONF_CHECK_RECT(name) do { \
+	PIPE_CONF_CHECK_I(name.x1); \
+	PIPE_CONF_CHECK_I(name.x2); \
+	PIPE_CONF_CHECK_I(name.y1); \
+	PIPE_CONF_CHECK_I(name.y2); \
+} while (0)

total: 0 errors, 0 warnings, 1 checks, 40 lines checked
bf14ee24645d drm/i915: Adjust intel_modeset_pipe_config() & co. calling convention
-:81: CHECK:SPACING: No space is necessary after a cast
#81: FILE: drivers/gpu/drm/i915/display/intel_display.c:5649:
+	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;

total: 0 errors, 0 warnings, 1 checks, 127 lines checked
9c1f612c7a53 drm/i915: s/pipe_config/crtc_state/
-:92: CHECK:SPACING: No space is necessary after a cast
#92: FILE: drivers/gpu/drm/i915/display/intel_display.c:5649:
+	crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;

-:190: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#190: FILE: drivers/gpu/drm/i915/display/intel_display.c:5767:
+	crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
 	                                               ^

total: 0 errors, 0 warnings, 2 checks, 169 lines checked
0b3d6909d086 drm/i915: Improve modeset debugs
a34799f2c9d5 drm/i915: Extract intel_crtc_dotclock()
ca638562f4a7 drm/i915: Introduce struct iclkip_params
3d3e8c895f11 drm/i915: Feed the DPLL output freq back into crtc_state
-:36: WARNING:AVOID_EXTERNS: externs should be avoided in .c files
#36: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:933:
+int intel_crtc_dotclock(const struct intel_crtc_state *crtc_state);

-:181: WARNING:AVOID_EXTERNS: externs should be avoided in .c files
#181: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1460:
+int intel_calculate_dotclock(const struct intel_crtc_state *crtc_state);

total: 0 errors, 2 warnings, 0 checks, 261 lines checked
daeb16028fe9 drm/i915: Compute clocks earlier
da303a89e10e drm/i915: Skip FDI vs. dotclock sanity check during readout
2d347b951e01 drm/i915: Make M/N checks non-fuzzy
a758ec2669c5 drm/i915: Make all clock checks non-fuzzy
9796263531df drm/i915: Set active dpll early for icl+
5eeb6716be8f drm/i915: Nuke fastet state copy hacks
4afe7158b868 drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not enabled
5e4f5952612c drm/i915: Check hw.enable and hw.active in intel_pipe_config_compare()
5f9c7c33e952 drm/i915: Add intel_panel_highest_mode()
a83f45006a03 drm/i915: Allow M/N change during fastset on bdw+
ce552dfa0ce1 drm/i915: Require an exact DP link freq match for the DG2 PLL
36dcfffc51fd drm/i915: Use a fixed N value always
fe0376ddca68 drm/i915: Round to closest in M/N calculations
f82c7d74a445 drm/i915: Round TMDS clock to nearest

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Make fastset not suck and allow seamless M/N changes (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 9686 bytes --]

== Series Details ==

Series: drm/i915: Make fastset not suck and allow seamless M/N changes (rev2)
URL   : https://patchwork.freedesktop.org/series/103491/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11602 -> Patchwork_103491v2
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_103491v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_103491v2, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/index.html

Participating hosts (33 -> 40)
------------------------------

  Additional (7): fi-rkl-11600 bat-adlm-1 bat-adlp-6 bat-adln-1 bat-rpls-1 bat-rpls-2 bat-jsl-1 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_103491v2:

### IGT changes ###

#### Possible regressions ####

  * igt@runner@aborted:
    - fi-hsw-g3258:       NOTRUN -> [FAIL][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-hsw-g3258/igt@runner@aborted.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@gt_heartbeat:
    - {bat-adlm-1}:       NOTRUN -> [INCOMPLETE][2]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/bat-adlm-1/igt@i915_selftest@live@gt_heartbeat.html

  
Known issues
------------

  Here are the changes found in Patchwork_103491v2 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_huc_copy@huc-copy:
    - fi-rkl-11600:       NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-rkl-11600/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-rkl-11600:       NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-rkl-11600/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_tiled_pread_basic:
    - fi-rkl-11600:       NOTRUN -> [SKIP][5] ([i915#3282])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-rkl-11600/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
    - fi-rkl-11600:       NOTRUN -> [SKIP][6] ([i915#3012])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-rkl-11600/igt@i915_pm_backlight@basic-brightness.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-rkl-11600:       NOTRUN -> [SKIP][7] ([fdo#111827]) +8 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-rkl-11600/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-rkl-11600:       NOTRUN -> [SKIP][8] ([i915#4070] / [i915#4103]) +1 similar issue
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-rkl-11600/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-rkl-11600:       NOTRUN -> [SKIP][9] ([fdo#109285] / [i915#4098])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-rkl-11600/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-rkl-11600:       NOTRUN -> [SKIP][10] ([i915#4070] / [i915#533])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-rkl-11600/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@primary_mmap_gtt:
    - fi-rkl-11600:       NOTRUN -> [SKIP][11] ([i915#1072]) +3 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-rkl-11600/igt@kms_psr@primary_mmap_gtt.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - fi-rkl-11600:       NOTRUN -> [SKIP][12] ([i915#3555] / [i915#4098])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-rkl-11600/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
    - fi-rkl-11600:       NOTRUN -> [SKIP][13] ([i915#3301] / [i915#3708])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-rkl-11600/igt@prime_vgem@basic-userptr.html

  * igt@prime_vgem@basic-write:
    - fi-rkl-11600:       NOTRUN -> [SKIP][14] ([i915#3291] / [i915#3708]) +2 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-rkl-11600/igt@prime_vgem@basic-write.html

  * igt@runner@aborted:
    - fi-hsw-4770:        NOTRUN -> [FAIL][15] ([i915#5594])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-hsw-4770/igt@runner@aborted.html
    - fi-bxt-dsi:         NOTRUN -> [FAIL][16] ([i915#5257])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-bxt-dsi/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s0@smem:
    - {fi-ehl-2}:         [DMESG-WARN][17] ([i915#5122]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/fi-ehl-2/igt@gem_exec_suspend@basic-s0@smem.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/fi-ehl-2/igt@gem_exec_suspend@basic-s0@smem.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#3003]: https://gitlab.freedesktop.org/drm/intel/issues/3003
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5087]: https://gitlab.freedesktop.org/drm/intel/issues/5087
  [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
  [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
  [i915#5329]: https://gitlab.freedesktop.org/drm/intel/issues/5329
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594
  [i915#5869]: https://gitlab.freedesktop.org/drm/intel/issues/5869
  [i915#5874]: https://gitlab.freedesktop.org/drm/intel/issues/5874


Build changes
-------------

  * Linux: CI_DRM_11602 -> Patchwork_103491v2

  CI-20190529: 20190529
  CI_DRM_11602: 4c7e3b6eee2669c87798d1303bca653b1b26d790 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6465: f6bb4399881a806fbff75ce3df89b60286d55917 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_103491v2: 4c7e3b6eee2669c87798d1303bca653b1b26d790 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

29ac5a84a4cf drm/i915: Round TMDS clock to nearest
688a86a341d1 drm/i915: Round to closest in M/N calculations
2ad767de5dc7 drm/i915: Use a fixed N value always
5d3b79386c19 drm/i915: Require an exact DP link freq match for the DG2 PLL
5b37da7cade8 drm/i915: Allow M/N change during fastset on bdw+
242091ed8031 drm/i915: Add intel_panel_highest_mode()
52c685e3ec81 drm/i915: Check hw.enable and hw.active in intel_pipe_config_compare()
fd57fe74a557 drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not enabled
e08ca82322ac drm/i915: Nuke fastet state copy hacks
9d2be6ee5075 drm/i915: Set active dpll early for icl+
46533d322cef drm/i915: Make all clock checks non-fuzzy
ad0f49a02539 drm/i915: Make M/N checks non-fuzzy
d966ca658a54 drm/i915: Skip FDI vs. dotclock sanity check during readout
9e52281e51b6 drm/i915: Compute clocks earlier
17637617d43d drm/i915: Feed the DPLL output freq back into crtc_state
236bf6e798b1 drm/i915: Introduce struct iclkip_params
4fecd92e096a drm/i915: Extract intel_crtc_dotclock()
5e378e198cdf drm/i915: Improve modeset debugs
72e63ec6cd3d drm/i915: s/pipe_config/crtc_state/
9961779ebd5c drm/i915: Adjust intel_modeset_pipe_config() & co. calling convention
bf55f4919fa9 drm/i915: Extract PIPE_CONF_CHECK_RECT()
424d8b1e173f drm/i915: Extract PIPE_CONF_CHECK_TIMINGS()
257c96d93846 drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
460e137d3d94 drm/i915: Clean up DPLL related debugs
8f142dbfa1d7 drm/i915: Do .crtc_compute_clock() earlier
0bd0056d9ff0 drm/i915: Split shared dpll .get_dplls() into compute and get phases

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v2/index.html

[-- Attachment #2: Type: text/html, Size: 10334 bytes --]

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Make fastset not suck and allow seamless M/N changes (rev3)
URL   : https://patchwork.freedesktop.org/series/103491/
State : warning

== Summary ==

Error: dim checkpatch failed
231785cfe6ad drm/i915: Split shared dpll .get_dplls() into compute and get phases
-:194: CHECK:CAMELCASE: Avoid CamelCase: <SPLL_FREQ_1350MHz>
#194: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1063:
+		SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;

total: 0 errors, 0 warnings, 1 checks, 516 lines checked
149c650e3c92 drm/i915: Do .crtc_compute_clock() earlier
fa07341e9078 drm/i915: Clean up DPLL related debugs
cd38c6f33ca7 drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
2bfa7d6f7335 drm/i915: Extract PIPE_CONF_CHECK_TIMINGS()
-:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#21: FILE: drivers/gpu/drm/i915/display/intel_display.c:6076:
+#define PIPE_CONF_CHECK_TIMINGS(name) do { \
+	PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
+	PIPE_CONF_CHECK_I(name.crtc_htotal); \
+	PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
+	PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
+	PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
+	PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
+	PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
+	PIPE_CONF_CHECK_I(name.crtc_vtotal); \
+	PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
+	PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
+	PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
+	PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
+} while (0)

total: 0 errors, 0 warnings, 1 checks, 63 lines checked
ff6cab1d620b drm/i915: Extract PIPE_CONF_CHECK_RECT()
-:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#21: FILE: drivers/gpu/drm/i915/display/intel_display.c:6091:
+#define PIPE_CONF_CHECK_RECT(name) do { \
+	PIPE_CONF_CHECK_I(name.x1); \
+	PIPE_CONF_CHECK_I(name.x2); \
+	PIPE_CONF_CHECK_I(name.y1); \
+	PIPE_CONF_CHECK_I(name.y2); \
+} while (0)

total: 0 errors, 0 warnings, 1 checks, 40 lines checked
fb7078b9e786 drm/i915: Adjust intel_modeset_pipe_config() & co. calling convention
-:81: CHECK:SPACING: No space is necessary after a cast
#81: FILE: drivers/gpu/drm/i915/display/intel_display.c:5649:
+	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;

total: 0 errors, 0 warnings, 1 checks, 127 lines checked
fc7e80cb709d drm/i915: s/pipe_config/crtc_state/
-:92: CHECK:SPACING: No space is necessary after a cast
#92: FILE: drivers/gpu/drm/i915/display/intel_display.c:5649:
+	crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;

-:190: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#190: FILE: drivers/gpu/drm/i915/display/intel_display.c:5767:
+	crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
 	                                               ^

total: 0 errors, 0 warnings, 2 checks, 169 lines checked
27b6922af13b drm/i915: Improve modeset debugs
38e979baf682 drm/i915: Extract intel_crtc_dotclock()
8b15f2405ad0 drm/i915: Introduce struct iclkip_params
f61c5b50fa28 drm/i915: Feed the DPLL output freq back into crtc_state
-:36: WARNING:AVOID_EXTERNS: externs should be avoided in .c files
#36: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:933:
+int intel_crtc_dotclock(const struct intel_crtc_state *crtc_state);

-:181: WARNING:AVOID_EXTERNS: externs should be avoided in .c files
#181: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1460:
+int intel_calculate_dotclock(const struct intel_crtc_state *crtc_state);

total: 0 errors, 2 warnings, 0 checks, 261 lines checked
07c0d384f102 drm/i915: Compute clocks earlier
ccbe5abf3ae6 drm/i915: Skip FDI vs. dotclock sanity check during readout
83ec228a297a drm/i915: Make M/N checks non-fuzzy
91e845fa1ecd drm/i915: Make all clock checks non-fuzzy
c27f33a67564 drm/i915: Set active dpll early for icl+
d9544b07e2ba drm/i915: Nuke fastet state copy hacks
477d1ccd6fac drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not enabled
5827bb6bd270 drm/i915: Check hw.enable and hw.active in intel_pipe_config_compare()
5c18a117f889 drm/i915: Add intel_panel_highest_mode()
7e294526263c drm/i915: Allow M/N change during fastset on bdw+
0d94627a7bee drm/i915: Require an exact DP link freq match for the DG2 PLL
13b567379cec drm/i915: Use a fixed N value always
47089a91ef2e drm/i915: Round to closest in M/N calculations
4776e9b1dc55 drm/i915: Round TMDS clock to nearest

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Make fastset not suck and allow seamless M/N changes (rev3)
URL   : https://patchwork.freedesktop.org/series/103491/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Make fastset not suck and allow seamless M/N changes (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 16371 bytes --]

== Series Details ==

Series: drm/i915: Make fastset not suck and allow seamless M/N changes (rev3)
URL   : https://patchwork.freedesktop.org/series/103491/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11607 -> Patchwork_103491v3
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_103491v3 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_103491v3, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/index.html

Participating hosts (41 -> 43)
------------------------------

  Additional (4): bat-adlm-1 bat-dg2-9 bat-dg1-6 bat-dg1-5 
  Missing    (2): bat-rpls-1 fi-bsw-cyan 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_103491v3:

### CI changes ###

#### Possible regressions ####

  * boot:
    - fi-kbl-7500u:       [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-kbl-7500u/boot.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/fi-kbl-7500u/boot.html

  
Known issues
------------

  Here are the changes found in Patchwork_103491v3 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@fbdev@write:
    - bat-dg1-5:          NOTRUN -> [SKIP][3] ([i915#2582]) +4 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@fbdev@write.html

  * igt@gem_mmap@basic:
    - bat-dg1-6:          NOTRUN -> [SKIP][4] ([i915#4083])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-6/igt@gem_mmap@basic.html
    - bat-dg1-5:          NOTRUN -> [SKIP][5] ([i915#4083])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@gem_mmap@basic.html

  * igt@gem_tiled_blits@basic:
    - bat-dg1-6:          NOTRUN -> [SKIP][6] ([i915#4077]) +2 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-6/igt@gem_tiled_blits@basic.html

  * igt@gem_tiled_fence_blits@basic:
    - bat-dg1-5:          NOTRUN -> [SKIP][7] ([i915#4077]) +2 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@gem_tiled_fence_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-dg1-5:          NOTRUN -> [SKIP][8] ([i915#4079]) +1 similar issue
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@gem_tiled_pread_basic.html
    - bat-dg1-6:          NOTRUN -> [SKIP][9] ([i915#4079]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-6/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
    - bat-dg1-5:          NOTRUN -> [SKIP][10] ([i915#1155])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@i915_pm_backlight@basic-brightness.html
    - bat-dg1-6:          NOTRUN -> [SKIP][11] ([i915#1155])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-6/igt@i915_pm_backlight@basic-brightness.html

  * igt@i915_selftest@live@gt_engines:
    - bat-dg1-6:          NOTRUN -> [INCOMPLETE][12] ([i915#4418])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
    - fi-rkl-guc:         [PASS][13] -> [INCOMPLETE][14] ([i915#4418])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@hangcheck:
    - bat-dg1-5:          NOTRUN -> [DMESG-FAIL][15] ([i915#4494] / [i915#4957])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@i915_selftest@live@hangcheck.html

  * igt@i915_suspend@system-suspend-without-i915:
    - bat-dg1-5:          NOTRUN -> [INCOMPLETE][16] ([i915#5849])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@i915_suspend@system-suspend-without-i915.html

  * igt@kms_addfb_basic@addfb25-x-tiled-legacy:
    - bat-dg1-6:          NOTRUN -> [SKIP][17] ([i915#4212]) +7 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-6/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - bat-dg1-5:          NOTRUN -> [SKIP][18] ([i915#4215])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@kms_addfb_basic@basic-y-tiled-legacy.html
    - bat-dg1-6:          NOTRUN -> [SKIP][19] ([i915#4215])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-6/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
    - bat-dg1-5:          NOTRUN -> [SKIP][20] ([i915#4212]) +7 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@kms_addfb_basic@tile-pitch-mismatch.html

  * igt@kms_busy@basic:
    - bat-dg1-5:          NOTRUN -> [SKIP][21] ([i915#4303])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@kms_busy@basic.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-hsw-g3258:       NOTRUN -> [SKIP][22] ([fdo#109271] / [fdo#111827])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/fi-hsw-g3258/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-edid-read:
    - bat-dg1-6:          NOTRUN -> [SKIP][23] ([fdo#111827]) +7 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-6/igt@kms_chamelium@hdmi-edid-read.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - bat-dg1-5:          NOTRUN -> [SKIP][24] ([fdo#111827]) +7 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - bat-dg1-6:          NOTRUN -> [SKIP][25] ([i915#4103] / [i915#4213]) +1 similar issue
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-dg1-5:          NOTRUN -> [SKIP][26] ([i915#4103] / [i915#4213]) +1 similar issue
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_flip@basic-flip-vs-dpms:
    - bat-dg1-5:          NOTRUN -> [SKIP][27] ([i915#4078]) +23 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@kms_flip@basic-flip-vs-dpms.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-dg1-6:          NOTRUN -> [SKIP][28] ([fdo#109285])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-6/igt@kms_force_connector_basic@force-load-detect.html
    - bat-dg1-5:          NOTRUN -> [SKIP][29] ([fdo#109285])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_psr@primary_page_flip:
    - bat-dg1-5:          NOTRUN -> [SKIP][30] ([i915#1072] / [i915#4078]) +3 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@kms_psr@primary_page_flip.html

  * igt@kms_psr@sprite_plane_onoff:
    - bat-dg1-6:          NOTRUN -> [SKIP][31] ([i915#1072] / [i915#4078]) +3 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-6/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-dg1-6:          NOTRUN -> [SKIP][32] ([i915#3555])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-6/igt@kms_setmode@basic-clone-single-crtc.html
    - bat-dg1-5:          NOTRUN -> [SKIP][33] ([i915#3555])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-mmap:
    - bat-dg1-5:          NOTRUN -> [SKIP][34] ([i915#3708] / [i915#4077]) +1 similar issue
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-gtt:
    - bat-dg1-6:          NOTRUN -> [SKIP][35] ([i915#3708] / [i915#4077]) +1 similar issue
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-6/igt@prime_vgem@basic-gtt.html

  * igt@prime_vgem@basic-userptr:
    - bat-dg1-6:          NOTRUN -> [SKIP][36] ([i915#3708] / [i915#4873])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-6/igt@prime_vgem@basic-userptr.html
    - bat-dg1-5:          NOTRUN -> [SKIP][37] ([i915#3708] / [i915#4873])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@prime_vgem@basic-userptr.html

  * igt@prime_vgem@basic-write:
    - bat-dg1-5:          NOTRUN -> [SKIP][38] ([i915#3708]) +3 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-5/igt@prime_vgem@basic-write.html
    - bat-dg1-6:          NOTRUN -> [SKIP][39] ([i915#3708]) +3 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-6/igt@prime_vgem@basic-write.html

  * igt@runner@aborted:
    - fi-rkl-guc:         NOTRUN -> [FAIL][40] ([i915#4312])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/fi-rkl-guc/igt@runner@aborted.html
    - fi-bxt-dsi:         NOTRUN -> [FAIL][41] ([i915#5257])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/fi-bxt-dsi/igt@runner@aborted.html
    - bat-dg1-6:          NOTRUN -> [FAIL][42] ([i915#4312] / [i915#5257])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-dg1-6/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@hangcheck:
    - fi-hsw-g3258:       [INCOMPLETE][43] ([i915#3303] / [i915#4785]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
    - {fi-ehl-2}:         [INCOMPLETE][45] ([i915#5134]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-ehl-2/igt@i915_selftest@live@hangcheck.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/fi-ehl-2/igt@i915_selftest@live@hangcheck.html

  * igt@kms_flip@basic-flip-vs-modeset@b-edp1:
    - {bat-adlp-6}:       [DMESG-WARN][47] ([i915#3576]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#4303]: https://gitlab.freedesktop.org/drm/intel/issues/4303
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
  [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
  [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
  [i915#5134]: https://gitlab.freedesktop.org/drm/intel/issues/5134
  [i915#5171]: https://gitlab.freedesktop.org/drm/intel/issues/5171
  [i915#5174]: https://gitlab.freedesktop.org/drm/intel/issues/5174
  [i915#5181]: https://gitlab.freedesktop.org/drm/intel/issues/5181
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
  [i915#5606]: https://gitlab.freedesktop.org/drm/intel/issues/5606
  [i915#5703]: https://gitlab.freedesktop.org/drm/intel/issues/5703
  [i915#5709]: https://gitlab.freedesktop.org/drm/intel/issues/5709
  [i915#5775]: https://gitlab.freedesktop.org/drm/intel/issues/5775
  [i915#5801]: https://gitlab.freedesktop.org/drm/intel/issues/5801
  [i915#5849]: https://gitlab.freedesktop.org/drm/intel/issues/5849
  [i915#5885]: https://gitlab.freedesktop.org/drm/intel/issues/5885


Build changes
-------------

  * Linux: CI_DRM_11607 -> Patchwork_103491v3

  CI-20190529: 20190529
  CI_DRM_11607: b0f0de5bb000952abb29696adb93f289e49b129c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6465: f6bb4399881a806fbff75ce3df89b60286d55917 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_103491v3: b0f0de5bb000952abb29696adb93f289e49b129c @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

e47ee538fdac drm/i915: Round TMDS clock to nearest
2c15dc8d0431 drm/i915: Round to closest in M/N calculations
ed84fb347dbe drm/i915: Use a fixed N value always
2f23a795f9b3 drm/i915: Require an exact DP link freq match for the DG2 PLL
f21ef6758edc drm/i915: Allow M/N change during fastset on bdw+
4cee8cdbf92a drm/i915: Add intel_panel_highest_mode()
d8c4c0523cf5 drm/i915: Check hw.enable and hw.active in intel_pipe_config_compare()
ea029822b164 drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not enabled
deb76f94c1c8 drm/i915: Nuke fastet state copy hacks
50134a3f553e drm/i915: Set active dpll early for icl+
2fecea3f92c8 drm/i915: Make all clock checks non-fuzzy
7a3196e310fe drm/i915: Make M/N checks non-fuzzy
88adc6978813 drm/i915: Skip FDI vs. dotclock sanity check during readout
47a7e822fa39 drm/i915: Compute clocks earlier
f0669cd95559 drm/i915: Feed the DPLL output freq back into crtc_state
86073c76b21a drm/i915: Introduce struct iclkip_params
62eb500d0db0 drm/i915: Extract intel_crtc_dotclock()
8794835b216b drm/i915: Improve modeset debugs
e8d85ab5494d drm/i915: s/pipe_config/crtc_state/
ae9354c7d071 drm/i915: Adjust intel_modeset_pipe_config() & co. calling convention
92259ea0a65e drm/i915: Extract PIPE_CONF_CHECK_RECT()
40c6ace45fcd drm/i915: Extract PIPE_CONF_CHECK_TIMINGS()
3443b586e221 drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
42d3ab605cbd drm/i915: Clean up DPLL related debugs
fb6021bb240a drm/i915: Do .crtc_compute_clock() earlier
b8d3f58a88d6 drm/i915: Split shared dpll .get_dplls() into compute and get phases

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v3/index.html

[-- Attachment #2: Type: text/html, Size: 18958 bytes --]

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Make fastset not suck and allow seamless M/N changes (rev4)
URL   : https://patchwork.freedesktop.org/series/103491/
State : warning

== Summary ==

Error: dim checkpatch failed
c22b28cfffd3 drm/i915: Split shared dpll .get_dplls() into compute and get phases
-:194: CHECK:CAMELCASE: Avoid CamelCase: <SPLL_FREQ_1350MHz>
#194: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1063:
+		SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;

total: 0 errors, 0 warnings, 1 checks, 516 lines checked
879cc74477fa drm/i915: Do .crtc_compute_clock() earlier
35d18170c1ab drm/i915: Clean up DPLL related debugs
bd06d6413c61 drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
60c9a564c630 drm/i915: Extract PIPE_CONF_CHECK_TIMINGS()
-:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#21: FILE: drivers/gpu/drm/i915/display/intel_display.c:6076:
+#define PIPE_CONF_CHECK_TIMINGS(name) do { \
+	PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
+	PIPE_CONF_CHECK_I(name.crtc_htotal); \
+	PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
+	PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
+	PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
+	PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
+	PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
+	PIPE_CONF_CHECK_I(name.crtc_vtotal); \
+	PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
+	PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
+	PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
+	PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
+} while (0)

total: 0 errors, 0 warnings, 1 checks, 63 lines checked
6de8ad90b89b drm/i915: Extract PIPE_CONF_CHECK_RECT()
-:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#21: FILE: drivers/gpu/drm/i915/display/intel_display.c:6091:
+#define PIPE_CONF_CHECK_RECT(name) do { \
+	PIPE_CONF_CHECK_I(name.x1); \
+	PIPE_CONF_CHECK_I(name.x2); \
+	PIPE_CONF_CHECK_I(name.y1); \
+	PIPE_CONF_CHECK_I(name.y2); \
+} while (0)

total: 0 errors, 0 warnings, 1 checks, 40 lines checked
514a77ad0c48 drm/i915: Adjust intel_modeset_pipe_config() & co. calling convention
-:81: CHECK:SPACING: No space is necessary after a cast
#81: FILE: drivers/gpu/drm/i915/display/intel_display.c:5649:
+	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;

total: 0 errors, 0 warnings, 1 checks, 127 lines checked
99f57f1bbfb6 drm/i915: s/pipe_config/crtc_state/
-:92: CHECK:SPACING: No space is necessary after a cast
#92: FILE: drivers/gpu/drm/i915/display/intel_display.c:5649:
+	crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;

-:190: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#190: FILE: drivers/gpu/drm/i915/display/intel_display.c:5767:
+	crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
 	                                               ^

total: 0 errors, 0 warnings, 2 checks, 169 lines checked
24b44ff8d3cc drm/i915: Improve modeset debugs
6736bc609e67 drm/i915: Extract intel_crtc_dotclock()
cf4444c0b6db drm/i915: Introduce struct iclkip_params
5f9ecd0a3455 drm/i915: Feed the DPLL output freq back into crtc_state
-:36: WARNING:AVOID_EXTERNS: externs should be avoided in .c files
#36: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:933:
+int intel_crtc_dotclock(const struct intel_crtc_state *crtc_state);

-:181: WARNING:AVOID_EXTERNS: externs should be avoided in .c files
#181: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1460:
+int intel_calculate_dotclock(const struct intel_crtc_state *crtc_state);

total: 0 errors, 2 warnings, 0 checks, 261 lines checked
b99e6189702a drm/i915: Compute clocks earlier
90e0b8e479b7 drm/i915: Skip FDI vs. dotclock sanity check during readout
b1ba2dd163dc drm/i915: Make M/N checks non-fuzzy
a21379dc8365 drm/i915: Make all clock checks non-fuzzy
c310a1210f63 drm/i915: Set active dpll early for icl+
86fafa6d29d8 drm/i915: Nuke fastet state copy hacks
9811567591ac drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not enabled
2c1626fe0bbb drm/i915: Check hw.enable and hw.active in intel_pipe_config_compare()
d699f5d194c8 drm/i915: Add intel_panel_highest_mode()
190d3ba0aa1f drm/i915: Allow M/N change during fastset on bdw+
d686b8dfd9db drm/i915: Require an exact DP link freq match for the DG2 PLL
b470ae0f272b drm/i915: Use a fixed N value always
fd6a9551796d drm/i915: Round to closest in M/N calculations
7b1987f4581b drm/i915: Round TMDS clock to nearest

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Make fastset not suck and allow seamless M/N changes (rev4)
URL   : https://patchwork.freedesktop.org/series/103491/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Make fastset not suck and allow seamless M/N changes (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 8882 bytes --]

== Series Details ==

Series: drm/i915: Make fastset not suck and allow seamless M/N changes (rev4)
URL   : https://patchwork.freedesktop.org/series/103491/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11607 -> Patchwork_103491v4
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/index.html

Participating hosts (41 -> 40)
------------------------------

  Additional (2): bat-adlm-1 bat-dg2-9 
  Missing    (3): bat-dg2-8 fi-rkl-11600 fi-bsw-cyan 

Known issues
------------

  Here are the changes found in Patchwork_103491v4 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@execlists:
    - fi-bsw-kefka:       [PASS][1] -> [INCOMPLETE][2] ([i915#5801] / [i915#5847])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/fi-bsw-kefka/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-kbl-8809g:       [PASS][3] -> [DMESG-FAIL][4] ([i915#5334])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-kbl-8809g/igt@i915_selftest@live@gt_heartbeat.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/fi-kbl-8809g/igt@i915_selftest@live@gt_heartbeat.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-hsw-g3258:       NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/fi-hsw-g3258/igt@kms_chamelium@common-hpd-after-suspend.html
    - fi-snb-2600:        NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/fi-snb-2600/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@runner@aborted:
    - fi-bsw-kefka:       NOTRUN -> [FAIL][7] ([fdo#109271] / [i915#3428] / [i915#4312])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/fi-bsw-kefka/igt@runner@aborted.html
    - fi-bxt-dsi:         NOTRUN -> [FAIL][8] ([i915#5257])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/fi-bxt-dsi/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@hangcheck:
    - fi-hsw-g3258:       [INCOMPLETE][9] ([i915#3303] / [i915#4785]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
    - {fi-ehl-2}:         [INCOMPLETE][11] ([i915#5134]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-ehl-2/igt@i915_selftest@live@hangcheck.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/fi-ehl-2/igt@i915_selftest@live@hangcheck.html
    - fi-snb-2600:        [INCOMPLETE][13] ([i915#3921]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/fi-snb-2600/igt@i915_selftest@live@hangcheck.html

  * igt@i915_selftest@live@requests:
    - {bat-rpls-1}:       [INCOMPLETE][15] ([i915#4983] / [i915#5338]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/bat-rpls-1/igt@i915_selftest@live@requests.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/bat-rpls-1/igt@i915_selftest@live@requests.html

  * igt@kms_flip@basic-flip-vs-modeset@b-edp1:
    - {bat-adlp-6}:       [DMESG-WARN][17] ([i915#3576]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5087]: https://gitlab.freedesktop.org/drm/intel/issues/5087
  [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
  [i915#5134]: https://gitlab.freedesktop.org/drm/intel/issues/5134
  [i915#5171]: https://gitlab.freedesktop.org/drm/intel/issues/5171
  [i915#5174]: https://gitlab.freedesktop.org/drm/intel/issues/5174
  [i915#5181]: https://gitlab.freedesktop.org/drm/intel/issues/5181
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
  [i915#5278]: https://gitlab.freedesktop.org/drm/intel/issues/5278
  [i915#5329]: https://gitlab.freedesktop.org/drm/intel/issues/5329
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#5338]: https://gitlab.freedesktop.org/drm/intel/issues/5338
  [i915#5537]: https://gitlab.freedesktop.org/drm/intel/issues/5537
  [i915#5606]: https://gitlab.freedesktop.org/drm/intel/issues/5606
  [i915#5703]: https://gitlab.freedesktop.org/drm/intel/issues/5703
  [i915#5775]: https://gitlab.freedesktop.org/drm/intel/issues/5775
  [i915#5801]: https://gitlab.freedesktop.org/drm/intel/issues/5801
  [i915#5847]: https://gitlab.freedesktop.org/drm/intel/issues/5847


Build changes
-------------

  * Linux: CI_DRM_11607 -> Patchwork_103491v4

  CI-20190529: 20190529
  CI_DRM_11607: b0f0de5bb000952abb29696adb93f289e49b129c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6465: f6bb4399881a806fbff75ce3df89b60286d55917 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_103491v4: b0f0de5bb000952abb29696adb93f289e49b129c @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

940d8c3ae7e3 drm/i915: Round TMDS clock to nearest
974d1f0f2f47 drm/i915: Round to closest in M/N calculations
1ee98a0e8064 drm/i915: Use a fixed N value always
4f6da868519b drm/i915: Require an exact DP link freq match for the DG2 PLL
e6528bc1b478 drm/i915: Allow M/N change during fastset on bdw+
c61b8c7394c9 drm/i915: Add intel_panel_highest_mode()
28216b3c7e50 drm/i915: Check hw.enable and hw.active in intel_pipe_config_compare()
ec03a48feaa4 drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not enabled
feab306ca85b drm/i915: Nuke fastet state copy hacks
77cfcaa85641 drm/i915: Set active dpll early for icl+
a95aebd02268 drm/i915: Make all clock checks non-fuzzy
73adc42965f8 drm/i915: Make M/N checks non-fuzzy
9dad727d1830 drm/i915: Skip FDI vs. dotclock sanity check during readout
89b67046c1ce drm/i915: Compute clocks earlier
b3171a362400 drm/i915: Feed the DPLL output freq back into crtc_state
8bd35246ef57 drm/i915: Introduce struct iclkip_params
80358929fadb drm/i915: Extract intel_crtc_dotclock()
a16a168a5a0c drm/i915: Improve modeset debugs
7030a2cd7cb7 drm/i915: s/pipe_config/crtc_state/
e68b09f90e06 drm/i915: Adjust intel_modeset_pipe_config() & co. calling convention
d8d0963f2a10 drm/i915: Extract PIPE_CONF_CHECK_RECT()
fee56952e76c drm/i915: Extract PIPE_CONF_CHECK_TIMINGS()
c449b9a0548d drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
bcfb20e75d14 drm/i915: Clean up DPLL related debugs
eb226d9ddd6a drm/i915: Do .crtc_compute_clock() earlier
dff87200df64 drm/i915: Split shared dpll .get_dplls() into compute and get phases

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/index.html

[-- Attachment #2: Type: text/html, Size: 8511 bytes --]

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Make fastset not suck and allow seamless M/N changes (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 65494 bytes --]

== Series Details ==

Series: drm/i915: Make fastset not suck and allow seamless M/N changes (rev4)
URL   : https://patchwork.freedesktop.org/series/103491/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11607_full -> Patchwork_103491v4_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_103491v4_full:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_softpin@noreloc-interruptible:
    - {shard-rkl}:        [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-rkl-6/igt@gem_softpin@noreloc-interruptible.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-rkl-5/igt@gem_softpin@noreloc-interruptible.html

  
Known issues
------------

  Here are the changes found in Patchwork_103491v4_full that come from known issues:

### CI changes ###

#### Possible fixes ####

  * boot:
    - shard-snb:          ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [FAIL][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27]) ([i915#4338]) -> ([PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb7/boot.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb7/boot.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb7/boot.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb7/boot.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb7/boot.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb6/boot.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb6/boot.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb6/boot.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb6/boot.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb5/boot.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb5/boot.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb5/boot.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb5/boot.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb5/boot.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb4/boot.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb4/boot.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb4/boot.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb4/boot.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb4/boot.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb2/boot.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb2/boot.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb2/boot.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb2/boot.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb2/boot.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb2/boot.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb7/boot.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb7/boot.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb7/boot.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb7/boot.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb6/boot.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb6/boot.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb6/boot.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb6/boot.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb6/boot.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb5/boot.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb5/boot.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb5/boot.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb5/boot.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb5/boot.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb5/boot.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb4/boot.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb4/boot.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb4/boot.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb4/boot.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb4/boot.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb2/boot.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb2/boot.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb2/boot.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb2/boot.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb2/boot.html

  

### IGT changes ###

#### Issues hit ####

  * igt@gem_ccs@suspend-resume:
    - shard-iclb:         NOTRUN -> [SKIP][53] ([i915#5327]) +1 similar issue
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb1/igt@gem_ccs@suspend-resume.html

  * igt@gem_ctx_param@set-priority-not-supported:
    - shard-iclb:         NOTRUN -> [SKIP][54] ([fdo#109314])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb6/igt@gem_ctx_param@set-priority-not-supported.html

  * igt@gem_ctx_persistence@legacy-engines-hostile:
    - shard-snb:          NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#1099])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb7/igt@gem_ctx_persistence@legacy-engines-hostile.html

  * igt@gem_eio@in-flight-contexts-1us:
    - shard-tglb:         [PASS][56] -> [TIMEOUT][57] ([i915#3063])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-tglb6/igt@gem_eio@in-flight-contexts-1us.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb7/igt@gem_eio@in-flight-contexts-1us.html

  * igt@gem_eio@unwedge-stress:
    - shard-tglb:         NOTRUN -> [TIMEOUT][58] ([i915#3063])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb6/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_balancer@parallel-bb-first:
    - shard-tglb:         NOTRUN -> [DMESG-WARN][59] ([i915#5076] / [i915#5614])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb6/igt@gem_exec_balancer@parallel-bb-first.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-skl:          NOTRUN -> [FAIL][60] ([i915#2846])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-skl9/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
    - shard-tglb:         NOTRUN -> [FAIL][61] ([i915#2842])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb6/igt@gem_exec_fair@basic-none-vip@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         [PASS][62] -> [FAIL][63] ([i915#2842])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-apl:          [PASS][64] -> [FAIL][65] ([i915#2842])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-apl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-apl3/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
    - shard-iclb:         NOTRUN -> [FAIL][66] ([i915#2842]) +3 similar issues
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb6/igt@gem_exec_fair@basic-pace@vcs0.html

  * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
    - shard-iclb:         NOTRUN -> [SKIP][67] ([fdo#109313])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb3/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html

  * igt@gem_lmem_swapping@heavy-random:
    - shard-skl:          NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#4613]) +1 similar issue
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-skl9/igt@gem_lmem_swapping@heavy-random.html

  * igt@gem_lmem_swapping@random:
    - shard-iclb:         NOTRUN -> [SKIP][69] ([i915#4613])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb1/igt@gem_lmem_swapping@random.html

  * igt@gem_lmem_swapping@verify-random:
    - shard-apl:          NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#4613]) +2 similar issues
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-apl7/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_media_vme:
    - shard-tglb:         NOTRUN -> [SKIP][71] ([i915#284])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb6/igt@gem_media_vme.html

  * igt@gem_pread@exhaustion:
    - shard-iclb:         NOTRUN -> [WARN][72] ([i915#2658])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb3/igt@gem_pread@exhaustion.html

  * igt@gem_pxp@regular-baseline-src-copy-readible:
    - shard-tglb:         NOTRUN -> [SKIP][73] ([i915#4270])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb6/igt@gem_pxp@regular-baseline-src-copy-readible.html

  * igt@gem_render_copy@linear-to-vebox-y-tiled:
    - shard-iclb:         NOTRUN -> [SKIP][74] ([i915#768]) +1 similar issue
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb1/igt@gem_render_copy@linear-to-vebox-y-tiled.html

  * igt@gem_userptr_blits@coherency-unsync:
    - shard-iclb:         NOTRUN -> [SKIP][75] ([i915#3297])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb1/igt@gem_userptr_blits@coherency-unsync.html

  * igt@gen7_exec_parse@basic-offset:
    - shard-iclb:         NOTRUN -> [SKIP][76] ([fdo#109289])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb1/igt@gen7_exec_parse@basic-offset.html

  * igt@gen9_exec_parse@shadow-peek:
    - shard-tglb:         NOTRUN -> [SKIP][77] ([i915#2527] / [i915#2856])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb6/igt@gen9_exec_parse@shadow-peek.html

  * igt@gen9_exec_parse@valid-registers:
    - shard-iclb:         NOTRUN -> [SKIP][78] ([i915#2856]) +2 similar issues
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb1/igt@gen9_exec_parse@valid-registers.html

  * igt@i915_hangman@engine-engine-hang:
    - shard-snb:          NOTRUN -> [SKIP][79] ([fdo#109271]) +79 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb7/igt@i915_hangman@engine-engine-hang.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-skl:          NOTRUN -> [FAIL][80] ([i915#454])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-skl9/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_pm_lpsp@screens-disabled:
    - shard-iclb:         NOTRUN -> [SKIP][81] ([i915#1902])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb3/igt@i915_pm_lpsp@screens-disabled.html

  * igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-tglb:         NOTRUN -> [SKIP][82] ([fdo#111644] / [i915#1397] / [i915#2411])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb8/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@i915_pm_rpm@modeset-pc8-residency-stress:
    - shard-iclb:         NOTRUN -> [SKIP][83] ([fdo#109293] / [fdo#109506])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb6/igt@i915_pm_rpm@modeset-pc8-residency-stress.html

  * igt@i915_suspend@fence-restore-untiled:
    - shard-skl:          NOTRUN -> [INCOMPLETE][84] ([i915#4939])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-skl2/igt@i915_suspend@fence-restore-untiled.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-0:
    - shard-tglb:         NOTRUN -> [SKIP][85] ([i915#5286]) +2 similar issues
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb6/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-iclb:         NOTRUN -> [SKIP][86] ([i915#5286]) +2 similar issues
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@linear-16bpp-rotate-270:
    - shard-tglb:         NOTRUN -> [SKIP][87] ([fdo#111614])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb8/igt@kms_big_fb@linear-16bpp-rotate-270.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-apl:          NOTRUN -> [SKIP][88] ([fdo#109271]) +181 similar issues
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-apl7/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@linear-32bpp-rotate-90:
    - shard-iclb:         NOTRUN -> [SKIP][89] ([fdo#110725] / [fdo#111614]) +4 similar issues
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb1/igt@kms_big_fb@linear-32bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
    - shard-iclb:         NOTRUN -> [SKIP][90] ([fdo#110723]) +1 similar issue
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb1/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html

  * igt@kms_ccs@pipe-a-ccs-on-another-bo-yf_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][91] ([fdo#111615] / [i915#3689])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb6/igt@kms_ccs@pipe-a-ccs-on-another-bo-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs:
    - shard-iclb:         NOTRUN -> [SKIP][92] ([fdo#109278] / [i915#3886]) +4 similar issues
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb1/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][93] ([i915#3689])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb6/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_ccs.html

  * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][94] ([fdo#109271] / [i915#3886]) +9 similar issues
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-apl7/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
    - shard-skl:          NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#3886]) +4 similar issues
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-skl1/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][96] ([i915#3689] / [i915#3886]) +2 similar issues
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb6/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs.html

  * igt@kms_cdclk@mode-transition:
    - shard-tglb:         NOTRUN -> [SKIP][97] ([i915#3742])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb6/igt@kms_cdclk@mode-transition.html

  * igt@kms_chamelium@dp-audio:
    - shard-snb:          NOTRUN -> [SKIP][98] ([fdo#109271] / [fdo#111827]) +3 similar issues
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb7/igt@kms_chamelium@dp-audio.html

  * igt@kms_chamelium@dp-hpd-storm-disable:
    - shard-tglb:         NOTRUN -> [SKIP][99] ([fdo#109284] / [fdo#111827]) +3 similar issues
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb6/igt@kms_chamelium@dp-hpd-storm-disable.html

  * igt@kms_chamelium@dp-mode-timings:
    - shard-apl:          NOTRUN -> [SKIP][100] ([fdo#109271] / [fdo#111827]) +14 similar issues
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-apl7/igt@kms_chamelium@dp-mode-timings.html

  * igt@kms_chamelium@hdmi-audio-edid:
    - shard-kbl:          NOTRUN -> [SKIP][101] ([fdo#109271] / [fdo#111827])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-kbl7/igt@kms_chamelium@hdmi-audio-edid.html

  * igt@kms_chamelium@hdmi-hpd-after-suspend:
    - shard-iclb:         NOTRUN -> [SKIP][102] ([fdo#109284] / [fdo#111827]) +7 similar issues
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb3/igt@kms_chamelium@hdmi-hpd-after-suspend.html

  * igt@kms_chamelium@vga-hpd-for-each-pipe:
    - shard-skl:          NOTRUN -> [SKIP][103] ([fdo#109271] / [fdo#111827]) +6 similar issues
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-skl1/igt@kms_chamelium@vga-hpd-for-each-pipe.html

  * igt@kms_color@pipe-a-deep-color:
    - shard-tglb:         NOTRUN -> [SKIP][104] ([i915#3555])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb6/igt@kms_color@pipe-a-deep-color.html

  * igt@kms_color@pipe-d-gamma:
    - shard-iclb:         NOTRUN -> [SKIP][105] ([fdo#109278] / [i915#1149])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb3/igt@kms_color@pipe-d-gamma.html

  * igt@kms_color_chamelium@pipe-d-ctm-green-to-red:
    - shard-iclb:         NOTRUN -> [SKIP][106] ([fdo#109278] / [fdo#109284] / [fdo#111827])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb6/igt@kms_color_chamelium@pipe-d-ctm-green-to-red.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-iclb:         NOTRUN -> [SKIP][107] ([i915#3116])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb6/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-tglb:         NOTRUN -> [SKIP][108] ([i915#3116] / [i915#3299])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb6/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@lic:
    - shard-apl:          NOTRUN -> [TIMEOUT][109] ([i915#1319])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-apl7/igt@kms_content_protection@lic.html

  * igt@kms_cursor_crc@pipe-b-cursor-512x512-rapid-movement:
    - shard-iclb:         NOTRUN -> [SKIP][110] ([fdo#109278] / [fdo#109279])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb6/igt@kms_cursor_crc@pipe-b-cursor-512x512-rapid-movement.html

  * igt@kms_cursor_crc@pipe-c-cursor-32x10-sliding:
    - shard-tglb:         NOTRUN -> [SKIP][111] ([i915#3359])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb6/igt@kms_cursor_crc@pipe-c-cursor-32x10-sliding.html

  * igt@kms_cursor_crc@pipe-d-cursor-32x32-rapid-movement:
    - shard-iclb:         NOTRUN -> [SKIP][112] ([fdo#109278]) +25 similar issues
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb6/igt@kms_cursor_crc@pipe-d-cursor-32x32-rapid-movement.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-iclb:         NOTRUN -> [SKIP][113] ([fdo#109274] / [fdo#109278]) +6 similar issues
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb6/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-glk:          [PASS][114] -> [FAIL][115] ([i915#2346] / [i915#533])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
    - shard-iclb:         [PASS][116] -> [FAIL][117] ([i915#2346])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-iclb2/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html

  * igt@kms_cursor_legacy@pipe-d-torture-bo:
    - shard-skl:          NOTRUN -> [SKIP][118] ([fdo#109271] / [i915#533])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-skl9/igt@kms_cursor_legacy@pipe-d-torture-bo.html

  * igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-4tiled:
    - shard-iclb:         NOTRUN -> [SKIP][119] ([i915#5287]) +1 similar issue
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb3/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-4tiled.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-skl:          NOTRUN -> [FAIL][120] ([i915#4767])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-skl9/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_flip@2x-dpms-vs-vblank-race:
    - shard-tglb:         NOTRUN -> [SKIP][121] ([fdo#109274] / [fdo#111825]) +1 similar issue
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb6/igt@kms_flip@2x-dpms-vs-vblank-race.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-iclb:         NOTRUN -> [SKIP][122] ([fdo#109274]) +2 similar issues
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb1/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-edp1:
    - shard-skl:          [PASS][123] -> [INCOMPLETE][124] ([i915#5864])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl6/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-skl1/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
    - shard-iclb:         [PASS][125] -> [SKIP][126] ([i915#3701])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-iclb7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render:
    - shard-tglb:         NOTRUN -> [SKIP][127] ([fdo#109280] / [fdo#111825]) +7 similar issues
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-kbl:          [PASS][128] -> [DMESG-WARN][129] ([i915#180]) +6 similar issues
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-iclb:         NOTRUN -> [SKIP][130] ([fdo#109280]) +25 similar issues
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_hdr@bpc-switch-dpms@bpc-switch-dpms-edp-1-pipe-a:
    - shard-skl:          [PASS][131] -> [FAIL][132] ([i915#1188])
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl5/igt@kms_hdr@bpc-switch-dpms@bpc-switch-dpms-edp-1-pipe-a.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-skl2/igt@kms_hdr@bpc-switch-dpms@bpc-switch-dpms-edp-1-pipe-a.html

  * igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c:
    - shard-tglb:         NOTRUN -> [SKIP][133] ([fdo#109289]) +1 similar issue
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb6/igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-skl:          [PASS][134] -> [INCOMPLETE][135] ([i915#4444])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
    - shard-apl:          [PASS][136] -> [DMESG-WARN][137] ([i915#180]) +3 similar issues
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          NOTRUN -> [FAIL][138] ([fdo#108145] / [i915#265]) +1 similar issue
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_plane_lowres@pipe-b-tiling-none:
    - shard-iclb:         NOTRUN -> [SKIP][139] ([i915#3536]) +2 similar issues
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb3/igt@kms_plane_lowres@pipe-b-tiling-none.html

  * igt@kms_plane_lowres@pipe-d-tiling-yf:
    - shard-tglb:         NOTRUN -> [SKIP][140] ([fdo#111615] / [fdo#112054]) +1 similar issue
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb6/igt@kms_plane_lowres@pipe-d-tiling-yf.html

  * igt@kms_plane_scaling@downscale-with-rotation-factor-0-25@pipe-a-edp-1-downscale-with-rotation:
    - shard-iclb:         NOTRUN -> [SKIP][141] ([i915#5176]) +2 similar issues
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb6/igt@kms_plane_scaling@downscale-with-rotation-factor-0-25@pipe-a-edp-1-downscale-with-rotation.html

  * igt@kms_plane_scaling@invalid-num-scalers@pipe-a-edp-1-invalid-num-scalers:
    - shard-skl:          NOTRUN -> [SKIP][142] ([fdo#109271] / [i915#5776]) +2 similar issues
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-skl9/igt@kms_plane_scaling@invalid-num-scalers@pipe-a-edp-1-invalid-num-scalers.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-edp-1-planes-downscale:
    - shard-iclb:         NOTRUN -> [SKIP][143] ([i915#5235]) +2 similar issues
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb3/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-edp-1-planes-downscale.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale:
    - shard-iclb:         [PASS][144] -> [SKIP][145] ([i915#5235]) +2 similar issues
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-iclb1/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale.html

  * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping:
    - shard-iclb:         [PASS][146] -> [INCOMPLETE][147] ([i915#5243])
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-iclb1/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping.html
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb2/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping.html

  * igt@kms_prime@basic-crc@first-to-second:
    - shard-iclb:         NOTRUN -> [SKIP][148] ([i915#1836])
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb1/igt@kms_prime@basic-crc@first-to-second.html

  * igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
    - shard-apl:          NOTRUN -> [SKIP][149] ([fdo#109271] / [i915#658]) +1 similar issue
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-apl7/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
    - shard-iclb:         NOTRUN -> [SKIP][150] ([fdo#111068] / [i915#658]) +2 similar issues
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb6/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-iclb:         [PASS][151] -> [SKIP][152] ([fdo#109642] / [fdo#111068] / [i915#658])
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-iclb2/igt@kms_psr2_su@frontbuffer-xrgb8888.html
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb8/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-skl:          NOTRUN -> [SKIP][153] ([fdo#109271] / [i915#658])
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-skl1/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-tglb:         NOTRUN -> [FAIL][154] ([i915#132] / [i915#3467])
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb6/igt@kms_psr@psr2_no_drrs.html

  * igt@kms_psr@psr2_primary_mmap_cpu:
    - shard-iclb:         [PASS][155] -> [SKIP][156] ([fdo#109441]) +3 similar issues
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb7/igt@kms_psr@psr2_primary_mmap_cpu.html

  * igt@kms_psr@psr2_sprite_mmap_cpu:
    - shard-iclb:         NOTRUN -> [SKIP][157] ([fdo#109441])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb1/igt@kms_psr@psr2_sprite_mmap_cpu.html

  * igt@kms_scaling_modes@scaling-mode-none@edp-1-pipe-a:
    - shard-skl:          NOTRUN -> [SKIP][158] ([fdo#109271]) +114 similar issues
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-skl9/igt@kms_scaling_modes@scaling-mode-none@edp-1-pipe-a.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - shard-iclb:         NOTRUN -> [SKIP][159] ([i915#3555]) +1 similar issue
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb6/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@kms_vblank@pipe-a-ts-continuation-modeset:
    - shard-snb:          [PASS][160] -> [SKIP][161] ([fdo#109271]) +4 similar issues
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb5/igt@kms_vblank@pipe-a-ts-continuation-modeset.html
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb2/igt@kms_vblank@pipe-a-ts-continuation-modeset.html

  * igt@kms_vblank@pipe-d-wait-idle:
    - shard-apl:          NOTRUN -> [SKIP][162] ([fdo#109271] / [i915#533])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-apl7/igt@kms_vblank@pipe-d-wait-idle.html

  * igt@nouveau_crc@ctx-flip-threshold-reset-after-capture:
    - shard-iclb:         NOTRUN -> [SKIP][163] ([i915#2530]) +1 similar issue
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb6/igt@nouveau_crc@ctx-flip-threshold-reset-after-capture.html

  * igt@nouveau_crc@pipe-b-source-outp-inactive:
    - shard-tglb:         NOTRUN -> [SKIP][164] ([i915#2530])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb6/igt@nouveau_crc@pipe-b-source-outp-inactive.html

  * igt@perf@polling-parameterized:
    - shard-skl:          [PASS][165] -> [FAIL][166] ([i915#5639])
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl4/igt@perf@polling-parameterized.html
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-skl7/igt@perf@polling-parameterized.html

  * igt@prime_nv_pcopy@test1_micro:
    - shard-tglb:         NOTRUN -> [SKIP][167] ([fdo#109291])
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb6/igt@prime_nv_pcopy@test1_micro.html

  * igt@prime_nv_pcopy@test2:
    - shard-kbl:          NOTRUN -> [SKIP][168] ([fdo#109271]) +22 similar issues
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-kbl7/igt@prime_nv_pcopy@test2.html

  * igt@prime_nv_pcopy@test3_4:
    - shard-iclb:         NOTRUN -> [SKIP][169] ([fdo#109291]) +2 similar issues
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb6/igt@prime_nv_pcopy@test3_4.html

  * igt@prime_vgem@basic-userptr:
    - shard-iclb:         NOTRUN -> [SKIP][170] ([i915#3301])
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb3/igt@prime_vgem@basic-userptr.html

  * igt@syncobj_timeline@transfer-timeline-point:
    - shard-tglb:         NOTRUN -> [DMESG-FAIL][171] ([i915#5098])
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb8/igt@syncobj_timeline@transfer-timeline-point.html

  * igt@sysfs_clients@recycle-many:
    - shard-apl:          NOTRUN -> [SKIP][172] ([fdo#109271] / [i915#2994]) +2 similar issues
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-apl4/igt@sysfs_clients@recycle-many.html

  * igt@sysfs_clients@sema-50:
    - shard-iclb:         NOTRUN -> [SKIP][173] ([i915#2994]) +1 similar issue
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb1/igt@sysfs_clients@sema-50.html

  * igt@sysfs_clients@split-10:
    - shard-skl:          NOTRUN -> [SKIP][174] ([fdo#109271] / [i915#2994]) +1 similar issue
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-skl9/igt@sysfs_clients@split-10.html

  
#### Possible fixes ####

  * igt@drm_import_export@import-close-race-prime:
    - {shard-rkl}:        [INCOMPLETE][175] -> [PASS][176]
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-rkl-5/igt@drm_import_export@import-close-race-prime.html
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-rkl-2/igt@drm_import_export@import-close-race-prime.html

  * igt@fbdev@nullptr:
    - {shard-rkl}:        [SKIP][177] ([i915#2582]) -> [PASS][178] +1 similar issue
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-rkl-4/igt@fbdev@nullptr.html
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-rkl-6/igt@fbdev@nullptr.html

  * igt@gem_eio@unwedge-stress:
    - {shard-tglu}:       [TIMEOUT][179] ([i915#3063]) -> [PASS][180]
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-tglu-8/igt@gem_eio@unwedge-stress.html
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglu-4/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_flush@basic-wb-prw-default:
    - shard-snb:          [SKIP][181] ([fdo#109271]) -> [PASS][182]
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-snb6/igt@gem_exec_flush@basic-wb-prw-default.html
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-snb4/igt@gem_exec_flush@basic-wb-prw-default.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          [DMESG-WARN][183] ([i915#180]) -> [PASS][184] +4 similar issues
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-apl2/igt@gem_workarounds@suspend-resume-context.html
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-apl4/igt@gem_workarounds@suspend-resume-context.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-apl:          [DMESG-WARN][185] ([i915#5566] / [i915#716]) -> [PASS][186]
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-apl3/igt@gen9_exec_parse@allowed-all.html
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-apl6/igt@gen9_exec_parse@allowed-all.html

  * igt@i915_pm_backlight@fade_with_suspend:
    - {shard-rkl}:        [SKIP][187] ([i915#3012]) -> [PASS][188]
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-rkl-4/igt@i915_pm_backlight@fade_with_suspend.html
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-rkl-6/igt@i915_pm_backlight@fade_with_suspend.html

  * igt@i915_pm_rpm@cursor-dpms:
    - {shard-rkl}:        [SKIP][189] ([i915#1849]) -> [PASS][190]
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-rkl-4/igt@i915_pm_rpm@cursor-dpms.html
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-rkl-6/igt@i915_pm_rpm@cursor-dpms.html

  * igt@i915_pm_rpm@dpms-lpsp:
    - {shard-rkl}:        [SKIP][191] ([i915#1397]) -> [PASS][192]
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-rkl-2/igt@i915_pm_rpm@dpms-lpsp.html
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-rkl-6/igt@i915_pm_rpm@dpms-lpsp.html

  * igt@i915_pm_rps@min-max-config-idle:
    - {shard-rkl}:        [FAIL][193] ([i915#4016]) -> [PASS][194]
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-rkl-1/igt@i915_pm_rps@min-max-config-idle.html
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-rkl-5/igt@i915_pm_rps@min-max-config-idle.html

  * igt@i915_suspend@debugfs-reader:
    - shard-kbl:          [DMESG-WARN][195] ([i915#180]) -> [PASS][196]
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-kbl7/igt@i915_suspend@debugfs-reader.html
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-kbl7/igt@i915_suspend@debugfs-reader.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-180:
    - {shard-rkl}:        [SKIP][197] ([i915#1845] / [i915#4098]) -> [PASS][198] +21 similar issues
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-rkl-4/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-rkl-6/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html

  * igt@kms_color@pipe-b-ctm-red-to-blue:
    - {shard-rkl}:        [SKIP][199] ([i915#1149] / [i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][200]
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-rkl-2/igt@kms_color@pipe-b-ctm-red-to-blue.html
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-rkl-6/igt@kms_color@pipe-b-ctm-red-to-blue.html

  * igt@kms_cursor_crc@pipe-b-cursor-128x128-sliding:
    - {shard-rkl}:        [SKIP][201] ([fdo#112022] / [i915#4070]) -> [PASS][202] +2 similar issues
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-rkl-2/igt@kms_cursor_crc@pipe-b-cursor-128x128-sliding.html
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-128x128-sliding.html

  * igt@kms_cursor_edge_walk@pipe-a-256x256-right-edge:
    - {shard-rkl}:        [SKIP][203] ([i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][204] +1 similar issue
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-rkl-2/igt@kms_cursor_edge_walk@pipe-a-256x256-right-edge.html
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-a-256x256-right-edge.html

  * igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge:
    - {shard-rkl}:        [SKIP][205] ([i915#4070] / [i915#4098]) -> [PASS][206] +2 similar issues
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-rkl-4/igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge.html
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge.html

  * igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions-varying-size:
    - {shard-rkl}:        [SKIP][207] ([fdo#111825] / [i915#4070]) -> [PASS][208]
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-rkl-4/igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions-varying-size.html
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-rkl-6/igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-skl:          [FAIL][209] -> [PASS][210]
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_draw_crc@draw-method-xrgb2101010-render-untiled:
    - {shard-rkl}:        [SKIP][211] ([fdo#111314] / [i915#4098] / [i915#4369]) -> [PASS][212] +2 similar issues
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-rkl-2/igt@kms_draw_crc@draw-method-xrgb2101010-render-untiled.html
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb2101010-render-untiled.html

  * igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-untiled:
    - {shard-rkl}:        [SKIP][213] ([i915#4098] / [i915#4369]) -> [PASS][214] +1 similar issue
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-rkl-4/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-untiled.html
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-untiled.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-skl:          [FAIL][215] ([i915#79]) -> [PASS][216] +1 similar issue
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-skl9/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip@wf_vblank-ts-check-interruptible@c-edp1:
    - shard-skl:          [FAIL][217] ([i915#2122]) -> [PASS][218] +2 similar issues
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl5/igt@kms_flip@wf_vblank-ts-check-interruptible@c-edp1.html
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-skl2/igt@kms_flip@wf_vblank-ts-check-interruptible@c-edp1.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render:
    - {shard-rkl}:        [SKIP][219] ([i915#1849] / [i915#4098]) -> [PASS][220] +16 similar issues
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render.html
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
    - shard-skl:          [FAIL][221] ([fdo#108145] / [i915#265]) -> [PASS][222]
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
    - {shard-rkl}:        [SKIP][223] ([i915#3558] / [i915#4070]) -> [PASS][224]
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-rkl-4/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-rkl-6/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-edp-1-planes-upscale-downscale:
    - shard-iclb:         [SKIP][225] ([i915#5235]) -> [PASS][226] +2 similar issues
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-edp-1-planes-upscale-downscale.html
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb8/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-edp-1-planes-upscale-downscale.html

  * igt@kms_psr@primary_render:
    - {shard-rkl}:        [SKIP][227] ([i915#1072]) -> [PASS][228]
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-rkl-2/igt@kms_psr@primary_render.html
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-rkl-6/igt@kms_psr@primary_render.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [SKIP][229] ([fdo#109441]) -> [PASS][230] +2 similar issues
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-iclb1/igt@kms_psr@psr2_cursor_render.html
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb2/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_universal_plane@disable-primary-vs-flip-pipe-a:
    - {shard-rkl}:        [SKIP][231] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][232] +2 similar issues
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-rkl-4/igt@kms_universal_plane@disable-primary-vs-flip-pipe-a.html
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-rkl-6/igt@kms_universal_plane@disable-primary-vs-flip-pipe-a.html

  * igt@kms_vblank@pipe-d-query-idle-hang:
    - shard-tglb:         [INCOMPLETE][233] -> [PASS][234]
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-tglb8/igt@kms_vblank@pipe-d-query-idle-hang.html
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-tglb6/igt@kms_vblank@pipe-d-query-idle-hang.html

  * igt@sysfs_heartbeat_interval@mixed@bcs0:
    - shard-skl:          [WARN][235] ([i915#4055]) -> [PASS][236]
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl2/igt@sysfs_heartbeat_interval@mixed@bcs0.html
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-skl9/igt@sysfs_heartbeat_interval@mixed@bcs0.html

  * igt@sysfs_heartbeat_interval@mixed@vcs0:
    - shard-skl:          [FAIL][237] ([i915#1731]) -> [PASS][238] +1 similar issue
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-skl2/igt@sysfs_heartbeat_interval@mixed@vcs0.html
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-skl9/igt@sysfs_heartbeat_interval@mixed@vcs0.html

  
#### Warnings ####

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
    - shard-iclb:         [DMESG-WARN][239] ([i915#5614]) -> [SKIP][240] ([i915#4525])
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-iclb1/igt@gem_exec_balancer@parallel-keep-submit-fence.html
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb3/igt@gem_exec_balancer@parallel-keep-submit-fence.html

  * igt@gem_exec_balancer@parallel-ordering:
    - shard-iclb:         [DMESG-FAIL][241] ([i915#5614]) -> [SKIP][242] ([i915#4525])
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb6/igt@gem_exec_balancer@parallel-ordering.html

  * igt@gem_exec_balancer@parallel-out-fence:
    - shard-iclb:         [SKIP][243] ([i915#4525]) -> [DMESG-WARN][244] ([i915#5614]) +2 similar issues
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-iclb8/igt@gem_exec_balancer@parallel-out-fence.html
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb1/igt@gem_exec_balancer@parallel-out-fence.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-iclb:         [FAIL][245] ([i915#2852]) -> [FAIL][246] ([i915#2842])
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-iclb7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb6/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-iclb:         [FAIL][247] ([i915#2842]) -> [FAIL][248] ([i915#2849])
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@i915_pm_dc@dc3co-vpb-simulation:
    - shard-iclb:         [SKIP][249] ([i915#588]) -> [SKIP][250] ([i915#658])
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-iclb7/igt@i915_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_draw_crc@draw-method-rgb565-render-xtiled:
    - shard-glk:          [DMESG-FAIL][251] ([i915#118]) -> [FAIL][252] ([i915#5160])
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-glk5/igt@kms_draw_crc@draw-method-rgb565-render-xtiled.html
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-glk8/igt@kms_draw_crc@draw-method-rgb565-render-xtiled.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][253], [FAIL][254], [FAIL][255], [FAIL][256], [FAIL][257], [FAIL][258], [FAIL][259], [FAIL][260], [FAIL][261], [FAIL][262], [FAIL][263], [FAIL][264]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][265], [FAIL][266], [FAIL][267], [FAIL][268], [FAIL][269], [FAIL][270], [FAIL][271], [FAIL][272], [FAIL][273], [FAIL][274], [FAIL][275], [FAIL][276], [FAIL][277], [FAIL][278], [FAIL][279], [FAIL][280]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-kbl7/igt@runner@aborted.html
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-kbl7/igt@runner@aborted.html
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-kbl7/igt@runner@aborted.html
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-kbl6/igt@runner@aborted.html
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-kbl3/igt@runner@aborted.html
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-kbl3/igt@runner@aborted.html
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-kbl4/igt@runner@aborted.html
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-kbl3/igt@runner@aborted.html
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-kbl3/igt@runner@aborted.html
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-kbl1/igt@runner@aborted.html
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-kbl3/igt@runner@aborted.html
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-kbl3/igt@runner@aborted.html
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-kbl3/igt@runner@aborted.html
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-kbl7/igt@runner@aborted.html
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-kbl4/igt@runner@aborted.html
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-kbl3/igt@runner@aborted.html
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-kbl4/igt@runner@aborted.html
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-kbl4/igt@runner@aborted.html
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-kbl6/igt@runner@aborted.html
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-kbl1/igt@runner@aborted.html
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-kbl3/igt@runner@aborted.html
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-kbl1/igt@runner@aborted.html
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-kbl1/igt@runner@aborted.html
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-kbl1/igt@runner@aborted.html
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-kbl7/igt@runner@aborted.html
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-kbl1/igt@runner@aborted.html
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-kbl7/igt@runner@aborted.html
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-kbl7/igt@runner@aborted.html
    - shard-apl:          ([FAIL][281], [FAIL][282], [FAIL][283], [FAIL][284], [FAIL][285], [FAIL][286], [FAIL][287], [FAIL][288], [FAIL][289], [FAIL][290]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][291], [FAIL][292], [FAIL][293], [FAIL][294], [FAIL][295], [FAIL][296], [FAIL][297], [FAIL][298]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-apl1/igt@runner@aborted.html
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-apl2/igt@runner@aborted.html
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-apl2/igt@runner@aborted.html
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-apl2/igt@runner@aborted.html
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-apl3/igt@runner@aborted.html
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-apl4/igt@runner@aborted.html
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-apl6/igt@runner@aborted.html
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-apl3/igt@runner@aborted.html
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-apl8/igt@runner@aborted.html
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11607/shard-apl4/igt@runner@aborted.html
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-apl7/igt@runner@aborted.html
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-apl6/igt@runner@aborted.html
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-apl1/igt@runner@aborted.html
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-apl7/igt@runner@aborted.html
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-apl7/igt@runner@aborted.html
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-apl6/igt@runner@aborted.html
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-apl4/igt@runner@aborted.html
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/shard-apl3/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293
  [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
  [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
  [fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022
  [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
  [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
  [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
  [i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
  [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
  [i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
  [i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
  [i915#2852]: https://gitlab.freedesktop.org/drm/intel/issues/2852
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
  [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
  [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3467]: https://gitlab.freedesktop.org/drm/intel/issues/3467
  [i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016
  [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
  [i915#4055]: https://gitlab.freedesktop.org/drm/intel/issues/4055
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4338]: https://gitlab.freedesktop.org/drm/intel/issues/4338
  [i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
  [i915#4444]: https://gitlab.freedesktop.org/drm/intel/issues/4444
  [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
  [i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
  [i915#5076]: https://gitlab.freedesktop.org/drm/intel/issues/5076
  [i915#5098]: https://gitlab.freedesktop.org/drm/intel/issues/5098
  [i915#5160]: https://gitlab.freedesktop.org/drm/intel/issues/5160
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5243]: https://gitlab.freedesktop.org/drm/intel/issues/5243
  [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5498]: https://gitlab.freedesktop.org/drm/intel/issues/5498
  [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
  [i915#5614]: https://gitlab.freedesktop.org/drm/intel/issues/5614
  [i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
  [i915#5691]: https://gitlab.freedesktop.org/drm/intel/issues/5691
  [i915#5776]: https://gitlab.freedesktop.org/drm/intel/issues/5776
  [i915#5864]: https://gitlab.freedesktop.org/drm/intel/issues/5864
  [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79


Build changes
-------------

  * Linux: CI_DRM_11607 -> Patchwork_103491v4

  CI-20190529: 20190529
  CI_DRM_11607: b0f0de5bb000952abb29696adb93f289e49b129c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6465: f6bb4399881a806fbff75ce3df89b60286d55917 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_103491v4: b0f0de5bb000952abb29696adb93f289e49b129c @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103491v4/index.html

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