From: Jani Nikula <jani.nikula@intel.com>
To: mika.kahola@intel.com
Cc: Deepak M <m.deepak@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/3 V2] drm/i915: Using the bpp value wrt the pixel format
Date: Fri, 19 Feb 2016 15:08:39 +0200 [thread overview]
Message-ID: <87vb5kx2y0.fsf@intel.com> (raw)
In-Reply-To: <1455886217.18069.1.camel@sorvi>
On Fri, 19 Feb 2016, Mika Kahola <mika.kahola@intel.com> wrote:
> On Fri, 2016-02-19 at 10:50 +0200, Jani Nikula wrote:
>> On Thu, 11 Feb 2016, Ramalingam C <ramalingam.c@intel.com> wrote:
>> > From: Deepak M <m.deepak@intel.com>
>> >
>> > The bpp value which is used while calulating the txbyteclkhs values
>> > should be wrt the pixel format value. Currently bpp is coming
>> > from pipe config to calculate txbyteclkhs. Fix it in this patch.
>> >
>> > V2: dsi_pixel_format_bpp is used to retrieve the bpp from pixel_format
>> > [Review: Jani]
>> >
>> > Signed-off-by: Deepak M <m.deepak@intel.com>
>> > Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
>> > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> Tested-by: Mika Kahola <mika.kahola@intel.com>
>
> Tested on BYT, Asus T100
Thanks, pushed to drm-intel-next-queued.
BR,
Jani.
>
>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>>
>> This needs a Tested-by on at least BYT to ensure everything still works.
>>
>> > ---
>> > drivers/gpu/drm/i915/intel_dsi.c | 5 ++---
>> > drivers/gpu/drm/i915/intel_dsi.h | 2 ++
>> > drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 5 +----
>> > drivers/gpu/drm/i915/intel_dsi_pll.c | 2 +-
>> > 4 files changed, 6 insertions(+), 8 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>> > index 91cef35..ce94342 100644
>> > --- a/drivers/gpu/drm/i915/intel_dsi.c
>> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> > @@ -775,10 +775,9 @@ static void set_dsi_timings(struct drm_encoder *encoder,
>> > {
>> > struct drm_device *dev = encoder->dev;
>> > struct drm_i915_private *dev_priv = dev->dev_private;
>> > - struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
>> > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
>> > enum port port;
>> > - unsigned int bpp = intel_crtc->config->pipe_bpp;
>> > + unsigned int bpp = dsi_pixel_format_bpp(intel_dsi->pixel_format);
>> > unsigned int lane_count = intel_dsi->lane_count;
>> >
>> > u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
>> > @@ -849,7 +848,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
>> > struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
>> > const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
>> > enum port port;
>> > - unsigned int bpp = intel_crtc->config->pipe_bpp;
>> > + unsigned int bpp = dsi_pixel_format_bpp(intel_dsi->pixel_format);
>> > u32 val, tmp;
>> > u16 mode_hdisplay;
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
>> > index de7be7f..92f3922 100644
>> > --- a/drivers/gpu/drm/i915/intel_dsi.h
>> > +++ b/drivers/gpu/drm/i915/intel_dsi.h
>> > @@ -34,6 +34,8 @@
>> > #define DSI_DUAL_LINK_FRONT_BACK 1
>> > #define DSI_DUAL_LINK_PIXEL_ALT 2
>> >
>> > +int dsi_pixel_format_bpp(int pixel_format);
>> > +
>> > struct intel_dsi_host;
>> >
>> > struct intel_dsi {
>> > diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> > index 1d43e6f..23c0f67 100644
>> > --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> > +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> > @@ -420,10 +420,7 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
>> > intel_dsi->dual_link = mipi_config->dual_link;
>> > intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
>> >
>> > - if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
>> > - bits_per_pixel = 18;
>> > - else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565)
>> > - bits_per_pixel = 16;
>> > + bits_per_pixel = dsi_pixel_format_bpp(intel_dsi->pixel_format);
>> >
>> > intel_dsi->operation_mode = mipi_config->is_cmd_mode;
>> > intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
>> > diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
>> > index bb5e95a..70883c5 100644
>> > --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
>> > +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
>> > @@ -30,7 +30,7 @@
>> > #include "i915_drv.h"
>> > #include "intel_dsi.h"
>> >
>> > -static int dsi_pixel_format_bpp(int pixel_format)
>> > +int dsi_pixel_format_bpp(int pixel_format)
>> > {
>> > int bpp;
>>
>
>
--
Jani Nikula, Intel Open Source Technology Center
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next prev parent reply other threads:[~2016-02-19 13:08 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-02 17:54 [PATCH 1/2] drm/i915/BXT: Fixed COS blanking issue Ramalingam C
2016-02-02 17:54 ` [PATCH 2/2] drm/i915/dsi: Add audio reference in dsi encoder Ramalingam C
2016-02-03 1:52 ` Thulasimani, Sivakumar
2016-02-03 8:57 ` Jani Nikula
2016-02-03 9:24 ` Ramalingam C
2016-02-03 10:01 ` Jani Nikula
2016-02-19 9:23 ` Jani Nikula
2016-02-19 9:31 ` Ramalingam C
2016-02-02 18:23 ` [PATCH 1/2] drm/i915/BXT: Fixed COS blanking issue kbuild test robot
2016-02-02 18:38 ` kbuild test robot
2016-02-03 1:49 ` Thulasimani, Sivakumar
2016-02-03 12:20 ` Ramalingam C
2016-02-03 8:02 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] " Patchwork
2016-02-03 9:44 ` [PATCH 1/2] " Jani Nikula
2016-02-03 12:18 ` Ramalingam C
2016-02-03 12:27 ` [PATCH 1/2] drm/i915: Using the bpp value wrt the pixel format Ramalingam C
2016-02-03 12:27 ` [PATCH 2/2] drm/i915/BXT: Fixed COS blanking issue Ramalingam C
2016-02-04 13:54 ` Jani Nikula
2016-02-11 14:49 ` Ramalingam C
2016-02-11 14:59 ` [PATCH 2/3 V3] " Ramalingam C
2016-02-19 9:16 ` Jani Nikula
2016-02-04 13:13 ` [PATCH 1/2] drm/i915: Using the bpp value wrt the pixel format Jani Nikula
2016-02-11 15:00 ` Ramalingam C
2016-02-11 15:03 ` [PATCH 1/3 V2] " Ramalingam C
2016-02-11 15:05 ` [PATCH 3/3] drm/i915: Updating the CPU_TRANSCODER for BXT DSI Ramalingam C
2016-02-19 9:07 ` Jani Nikula
2016-02-23 14:31 ` Ramalingam C
2016-02-19 8:50 ` [PATCH 1/3 V2] drm/i915: Using the bpp value wrt the pixel format Jani Nikula
2016-02-19 12:50 ` Mika Kahola
2016-02-19 13:08 ` Jani Nikula [this message]
2016-02-15 16:28 ` [PATCH 1/2] drm/i915/BXT: Fixed COS blanking issue Daniel Vetter
2016-02-03 13:12 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Using the bpp value wrt the pixel format (rev2) Patchwork
2016-02-15 16:24 ` [PATCH 1/2] drm/i915/BXT: Fixed COS blanking issue Daniel Vetter
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