* [PATCH 01/10] hw/intc: RX62N interrupt controller (ICUa)
2020-05-31 16:24 [PATCH 00/10] Add RX hardware emulation Yoshinori Sato
@ 2020-05-31 16:24 ` Yoshinori Sato
2020-06-05 15:45 ` Philippe Mathieu-Daudé
2020-05-31 16:24 ` [PATCH 02/10] hw/timer: Renesas 8bit timer module Yoshinori Sato
` (9 subsequent siblings)
10 siblings, 1 reply; 17+ messages in thread
From: Yoshinori Sato @ 2020-05-31 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: Yoshinori Sato
This implementation supported only ICUa.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
include/hw/intc/rx_icu.h | 56 ++++++
hw/intc/rx_icu.c | 379 +++++++++++++++++++++++++++++++++++++++
hw/intc/Makefile.objs | 1 +
3 files changed, 436 insertions(+)
create mode 100644 include/hw/intc/rx_icu.h
create mode 100644 hw/intc/rx_icu.c
diff --git a/include/hw/intc/rx_icu.h b/include/hw/intc/rx_icu.h
new file mode 100644
index 0000000000..acfcf06aef
--- /dev/null
+++ b/include/hw/intc/rx_icu.h
@@ -0,0 +1,56 @@
+#ifndef RX_ICU_H
+#define RX_ICU_H
+
+#include "qemu-common.h"
+#include "hw/irq.h"
+
+enum TRG_MODE {
+ TRG_LEVEL = 0,
+ TRG_NEDGE = 1, /* Falling */
+ TRG_PEDGE = 2, /* Raising */
+ TRG_BEDGE = 3, /* Both */
+};
+
+struct IRQSource {
+ enum TRG_MODE sense;
+ int level;
+};
+
+enum {
+ /* Software interrupt request */
+ SWI = 27,
+ NR_IRQS = 256,
+};
+
+struct RXICUState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion memory;
+ struct IRQSource src[NR_IRQS];
+ char *icutype;
+ uint32_t nr_irqs;
+ uint32_t *map;
+ uint32_t nr_sense;
+ uint32_t *init_sense;
+
+ uint8_t ir[NR_IRQS];
+ uint8_t dtcer[NR_IRQS];
+ uint8_t ier[NR_IRQS / 8];
+ uint8_t ipr[142];
+ uint8_t dmasr[4];
+ uint16_t fir;
+ uint8_t nmisr;
+ uint8_t nmier;
+ uint8_t nmiclr;
+ uint8_t nmicr;
+ int req_irq;
+ qemu_irq _irq;
+ qemu_irq _fir;
+ qemu_irq _swi;
+};
+typedef struct RXICUState RXICUState;
+
+#define TYPE_RXICU "rx-icu"
+#define RXICU(obj) OBJECT_CHECK(RXICUState, (obj), TYPE_RXICU)
+
+#endif /* RX_ICU_H */
diff --git a/hw/intc/rx_icu.c b/hw/intc/rx_icu.c
new file mode 100644
index 0000000000..ab9a300467
--- /dev/null
+++ b/hw/intc/rx_icu.c
@@ -0,0 +1,379 @@
+/*
+ * RX Interrupt Control Unit
+ *
+ * Warning: Only ICUa is supported.
+ *
+ * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware
+ * (Rev.1.40 R01UH0033EJ0140)
+ *
+ * Copyright (c) 2019 Yoshinori Sato
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "cpu.h"
+#include "hw/hw.h"
+#include "hw/irq.h"
+#include "hw/sysbus.h"
+#include "hw/registerfields.h"
+#include "hw/qdev-properties.h"
+#include "hw/intc/rx_icu.h"
+#include "migration/vmstate.h"
+#include "qemu/error-report.h"
+
+REG8(IR, 0)
+ FIELD(IR, IR, 0, 1)
+REG8(DTCER, 0x100)
+ FIELD(DTCER, DTCE, 0, 1)
+REG8(IER, 0x200)
+REG8(SWINTR, 0x2e0)
+ FIELD(SWINTR, SWINT, 0, 1)
+REG16(FIR, 0x2f0)
+ FIELD(FIR, FVCT, 0, 8)
+ FIELD(FIR, FIEN, 15, 1)
+REG8(IPR, 0x300)
+ FIELD(IPR, IPR, 0, 4)
+REG8(DMRSR, 0x400)
+REG8(IRQCR, 0x500)
+ FIELD(IRQCR, IRQMD, 2, 2)
+REG8(NMISR, 0x580)
+ FIELD(NMISR, NMIST, 0, 1)
+ FIELD(NMISR, LVDST, 1, 1)
+ FIELD(NMISR, OSTST, 2, 1)
+REG8(NMIER, 0x581)
+ FIELD(NMIER, NMIEN, 0, 1)
+ FIELD(NMIER, LVDEN, 1, 1)
+ FIELD(NMIER, OSTEN, 2, 1)
+REG8(NMICLR, 0x582)
+ FIELD(NMICLR, NMICLR, 0, 1)
+ FIELD(NMICLR, OSTCLR, 2, 1)
+REG8(NMICR, 0x583)
+ FIELD(NMICR, NMIMD, 3, 1)
+
+#define request(icu, n) (icu->ipr[icu->map[n]] << 8 | n)
+
+static void set_irq(RXICUState *icu, int n_IRQ, int req)
+{
+ if ((icu->fir & R_FIR_FIEN_MASK) &&
+ (icu->fir & R_FIR_FVCT_MASK) == n_IRQ) {
+ qemu_set_irq(icu->_fir, req);
+ } else {
+ qemu_set_irq(icu->_irq, req);
+ }
+}
+
+static void rxicu_request(RXICUState *icu, int n_IRQ)
+{
+ int enable;
+
+ enable = icu->ier[n_IRQ / 8] & (1 << (n_IRQ & 7));
+ if (n_IRQ > 0 && enable != 0 && atomic_read(&icu->req_irq) < 0) {
+ atomic_set(&icu->req_irq, n_IRQ);
+ set_irq(icu, n_IRQ, request(icu, n_IRQ));
+ }
+}
+
+static void rxicu_set_irq(void *opaque, int n_IRQ, int level)
+{
+ RXICUState *icu = opaque;
+ struct IRQSource *src;
+ int issue;
+
+ if (n_IRQ >= NR_IRQS) {
+ error_report("%s: IRQ %d out of range", __func__, n_IRQ);
+ return;
+ }
+
+ src = &icu->src[n_IRQ];
+
+ level = (level != 0);
+ switch (src->sense) {
+ case TRG_LEVEL:
+ /* level-sensitive irq */
+ issue = level;
+ src->level = level;
+ break;
+ case TRG_NEDGE:
+ issue = (level == 0 && src->level == 1);
+ src->level = level;
+ break;
+ case TRG_PEDGE:
+ issue = (level == 1 && src->level == 0);
+ src->level = level;
+ break;
+ case TRG_BEDGE:
+ issue = ((level ^ src->level) & 1);
+ src->level = level;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ if (issue == 0 && src->sense == TRG_LEVEL) {
+ icu->ir[n_IRQ] = 0;
+ if (atomic_read(&icu->req_irq) == n_IRQ) {
+ /* clear request */
+ set_irq(icu, n_IRQ, 0);
+ atomic_set(&icu->req_irq, -1);
+ }
+ return;
+ }
+ if (issue) {
+ icu->ir[n_IRQ] = 1;
+ rxicu_request(icu, n_IRQ);
+ }
+}
+
+static void rxicu_ack_irq(void *opaque, int no, int level)
+{
+ RXICUState *icu = opaque;
+ int i;
+ int n_IRQ;
+ int max_pri;
+
+ n_IRQ = atomic_read(&icu->req_irq);
+ if (n_IRQ < 0) {
+ return;
+ }
+ atomic_set(&icu->req_irq, -1);
+ if (icu->src[n_IRQ].sense != TRG_LEVEL) {
+ icu->ir[n_IRQ] = 0;
+ }
+
+ max_pri = 0;
+ n_IRQ = -1;
+ for (i = 0; i < NR_IRQS; i++) {
+ if (icu->ir[i]) {
+ if (max_pri < icu->ipr[icu->map[i]]) {
+ n_IRQ = i;
+ max_pri = icu->ipr[icu->map[i]];
+ }
+ }
+ }
+
+ if (n_IRQ >= 0) {
+ rxicu_request(icu, n_IRQ);
+ }
+}
+
+static uint64_t icu_read(void *opaque, hwaddr addr, unsigned size)
+{
+ RXICUState *icu = opaque;
+ int reg = addr & 0xff;
+
+ if ((addr != A_FIR && size != 1) ||
+ (addr == A_FIR && size != 2)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "rx_icu: Invalid read size 0x%"
+ HWADDR_PRIX "\n", addr);
+ return UINT64_MAX;
+ }
+ switch (addr) {
+ case A_IR ... A_IR + 0xff:
+ return icu->ir[reg] & R_IR_IR_MASK;
+ case A_DTCER ... A_DTCER + 0xff:
+ return icu->dtcer[reg] & R_DTCER_DTCE_MASK;
+ case A_IER ... A_IER + 0x1f:
+ return icu->ier[reg];
+ case A_SWINTR:
+ return 0;
+ case A_FIR:
+ return icu->fir & (R_FIR_FIEN_MASK | R_FIR_FVCT_MASK);
+ case A_IPR ... A_IPR + 0x8f:
+ return icu->ipr[reg] & R_IPR_IPR_MASK;
+ case A_DMRSR:
+ case A_DMRSR + 4:
+ case A_DMRSR + 8:
+ case A_DMRSR + 12:
+ return icu->dmasr[reg >> 2];
+ case A_IRQCR ... A_IRQCR + 0x1f:
+ return icu->src[64 + reg].sense << R_IRQCR_IRQMD_SHIFT;
+ case A_NMISR:
+ case A_NMICLR:
+ return 0;
+ case A_NMIER:
+ return icu->nmier;
+ case A_NMICR:
+ return icu->nmicr;
+ default:
+ qemu_log_mask(LOG_UNIMP, "rx_icu: Register 0x%" HWADDR_PRIX
+ " not implemented.\n", addr);
+ break;
+ }
+ return UINT64_MAX;
+}
+
+static void icu_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
+{
+ RXICUState *icu = opaque;
+ int reg = addr & 0xff;
+
+ if ((addr != A_FIR && size != 1) ||
+ (addr == A_FIR && size != 2)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "rx_icu: Invalid write size at 0x%"
+ HWADDR_PRIX "\n", addr);
+ return;
+ }
+ switch (addr) {
+ case A_IR ... A_IR + 0xff:
+ if (icu->src[reg].sense != TRG_LEVEL && val == 0) {
+ icu->ir[reg] = 0;
+ }
+ break;
+ case A_DTCER ... A_DTCER + 0xff:
+ icu->dtcer[reg] = val & R_DTCER_DTCE_MASK;
+ qemu_log_mask(LOG_UNIMP,
+ "rx_icu: DTC not implemented\n");
+ break;
+ case A_IER ... A_IER + 0x1f:
+ icu->ier[reg] = val;
+ break;
+ case A_SWINTR:
+ if (val & R_SWINTR_SWINT_MASK) {
+ qemu_irq_pulse(icu->_swi);
+ }
+ break;
+ case A_FIR:
+ icu->fir = val & (R_FIR_FIEN_MASK | R_FIR_FVCT_MASK);
+ break;
+ case A_IPR ... A_IPR + 0x8f:
+ icu->ipr[reg] = val & R_IPR_IPR_MASK;
+ break;
+ case A_DMRSR:
+ case A_DMRSR + 4:
+ case A_DMRSR + 8:
+ case A_DMRSR + 12:
+ icu->dmasr[reg >> 2] = val;
+ qemu_log_mask(LOG_UNIMP,
+ "rx_icu: DMAC not implemented\n");
+ break;
+ case A_IRQCR ... A_IRQCR + 0x1f:
+ icu->src[64 + reg].sense = val >> R_IRQCR_IRQMD_SHIFT;
+ break;
+ case A_NMICLR:
+ break;
+ case A_NMIER:
+ icu->nmier |= val & (R_NMIER_NMIEN_MASK |
+ R_NMIER_LVDEN_MASK |
+ R_NMIER_OSTEN_MASK);
+ break;
+ case A_NMICR:
+ if ((icu->nmier & R_NMIER_NMIEN_MASK) == 0) {
+ icu->nmicr = val & R_NMICR_NMIMD_MASK;
+ }
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "rx_icu: Register 0x%" HWADDR_PRIX
+ " not implemented\n", addr);
+ break;
+ }
+}
+
+static const MemoryRegionOps icu_ops = {
+ .write = icu_write,
+ .read = icu_read,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .impl = {
+ .max_access_size = 2,
+ },
+};
+
+static void rxicu_realize(DeviceState *dev, Error **errp)
+{
+ RXICUState *icu = RXICU(dev);
+ int i, j;
+
+ if (icu->init_sense == NULL) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "rx_icu: trigger-level property must be set.");
+ return;
+ }
+ for (i = j = 0; i < NR_IRQS; i++) {
+ if (icu->init_sense[j] == i) {
+ icu->src[i].sense = TRG_LEVEL;
+ if (j < icu->nr_sense) {
+ j++;
+ }
+ } else {
+ icu->src[i].sense = TRG_PEDGE;
+ }
+ }
+ icu->req_irq = -1;
+}
+
+static void rxicu_init(Object *obj)
+{
+ SysBusDevice *d = SYS_BUS_DEVICE(obj);
+ RXICUState *icu = RXICU(obj);
+
+ memory_region_init_io(&icu->memory, OBJECT(icu), &icu_ops,
+ icu, "rx-icu", 0x600);
+ sysbus_init_mmio(d, &icu->memory);
+
+ qdev_init_gpio_in(DEVICE(d), rxicu_set_irq, NR_IRQS);
+ qdev_init_gpio_in_named(DEVICE(d), rxicu_ack_irq, "ack", 1);
+ sysbus_init_irq(d, &icu->_irq);
+ sysbus_init_irq(d, &icu->_fir);
+ sysbus_init_irq(d, &icu->_swi);
+}
+
+static void rxicu_fini(Object *obj)
+{
+ RXICUState *icu = RXICU(obj);
+ g_free(icu->map);
+ g_free(icu->init_sense);
+}
+
+static const VMStateDescription vmstate_rxicu = {
+ .name = "rx-icu",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static Property rxicu_properties[] = {
+ DEFINE_PROP_ARRAY("ipr-map", RXICUState, nr_irqs, map,
+ qdev_prop_uint32, uint32_t),
+ DEFINE_PROP_ARRAY("trigger-level", RXICUState, nr_sense, init_sense,
+ qdev_prop_uint32, uint32_t),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void rxicu_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = rxicu_realize;
+ dc->vmsd = &vmstate_rxicu;
+ device_class_set_props(dc, rxicu_properties);
+}
+
+static const TypeInfo rxicu_info = {
+ .name = TYPE_RXICU,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(RXICUState),
+ .instance_init = rxicu_init,
+ .instance_finalize = rxicu_fini,
+ .class_init = rxicu_class_init,
+};
+
+static void rxicu_register_types(void)
+{
+ type_register_static(&rxicu_info);
+}
+
+type_init(rxicu_register_types)
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index f726d87532..f17cbd1a9f 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -49,3 +49,4 @@ obj-$(CONFIG_ARM_GIC) += arm_gicv3_cpuif.o
obj-$(CONFIG_MIPS_CPS) += mips_gic.o
obj-$(CONFIG_NIOS2) += nios2_iic.o
obj-$(CONFIG_OMPIC) += ompic.o
+obj-$(CONFIG_RX) += rx_icu.o
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 02/10] hw/timer: Renesas 8bit timer module.
2020-05-31 16:24 [PATCH 00/10] Add RX hardware emulation Yoshinori Sato
2020-05-31 16:24 ` [PATCH 01/10] hw/intc: RX62N interrupt controller (ICUa) Yoshinori Sato
@ 2020-05-31 16:24 ` Yoshinori Sato
2020-05-31 16:24 ` [PATCH 03/10] hw/timer: Renesas TMU/CMT module Yoshinori Sato
` (8 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Yoshinori Sato @ 2020-05-31 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: Yoshinori Sato
8bit or 16bit timer.
This implementation support only internal clock mode.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
include/hw/timer/renesas_8timer.h | 61 ++++
hw/timer/renesas_8timer.c | 466 ++++++++++++++++++++++++++++++
hw/timer/Kconfig | 3 +
hw/timer/Makefile.objs | 2 +
4 files changed, 532 insertions(+)
create mode 100644 include/hw/timer/renesas_8timer.h
create mode 100644 hw/timer/renesas_8timer.c
diff --git a/include/hw/timer/renesas_8timer.h b/include/hw/timer/renesas_8timer.h
new file mode 100644
index 0000000000..7e05c7be97
--- /dev/null
+++ b/include/hw/timer/renesas_8timer.h
@@ -0,0 +1,61 @@
+/*
+ * Renesas 8bit timer Object
+ *
+ * Copyright (c) 2018 Yoshinori Sato
+ *
+ * This code is licensed under the GPL version 2 or later.
+ *
+ */
+
+#ifndef HW_RENESAS_TMR_H
+#define HW_RENESAS_TMR_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_RENESAS_8TMR "renesas-8tmr"
+#define RTMR(obj) OBJECT_CHECK(RTMRState, (obj), TYPE_RENESAS_8TMR)
+
+enum timer_event {
+ cmia, cmib, ovi, wovi,
+ TMR_NR_EVENTS,
+};
+
+enum {
+ TMR_CH = 2,
+ TMR_NR_COR = 2,
+ TMR_NR_IRQ = 3,
+};
+
+enum {
+ IRQ_CMIA, IRQ_CMIB, IRQ_OVI,
+};
+
+struct RTMRState;
+
+struct channel_8tmr {
+ uint16_t cnt;
+ uint16_t cor[TMR_NR_COR];
+ uint8_t tcr;
+ uint8_t tccr;
+ uint8_t tcsr;
+ qemu_irq irq[TMR_NR_IRQ];
+ QEMUTimer *timer;
+ int64_t base;
+ int64_t next;
+ int64_t clk;
+ enum timer_event event;
+ int id;
+ struct RTMRState *tmrp;
+ bool word;
+};
+
+typedef struct RTMRState {
+ SysBusDevice parent_obj;
+
+ uint64_t input_freq;
+ MemoryRegion memory;
+
+ struct channel_8tmr ch[TMR_CH];
+} RTMRState;
+
+#endif
diff --git a/hw/timer/renesas_8timer.c b/hw/timer/renesas_8timer.c
new file mode 100644
index 0000000000..b545ba0e2b
--- /dev/null
+++ b/hw/timer/renesas_8timer.c
@@ -0,0 +1,466 @@
+/*
+ * Renesas 8bit timer
+ *
+ * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware
+ * (Rev.1.40 R01UH0033EJ0140)
+ *
+ * Copyright (c) 2019 Yoshinori Sato
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "qemu/timer.h"
+#include "qemu/bitops.h"
+#include "hw/hw.h"
+#include "hw/irq.h"
+#include "hw/sysbus.h"
+#include "hw/registerfields.h"
+#include "hw/qdev-properties.h"
+#include "hw/timer/renesas_8timer.h"
+#include "migration/vmstate.h"
+#include "qemu/error-report.h"
+
+REG8(TCR, 0)
+ FIELD(TCR, CCLR, 3, 2)
+ FIELD(TCR, OVIE, 5, 1)
+ FIELD(TCR, CMIEA, 6, 1)
+ FIELD(TCR, CMIEB, 7, 1)
+REG8(TCSR, 2)
+ FIELD(TCSR, OSA, 0, 2)
+ FIELD(TCSR, OSB, 2, 2)
+ FIELD(TCSR, ADTE, 4, 1)
+REG8(TCORA, 4)
+REG8(TCORB, 6)
+REG8(TCNT, 8)
+REG8(TCCR, 10)
+ FIELD(TCCR, CKS, 0, 3)
+ FIELD(TCCR, CSS, 3, 2)
+ FIELD(TCCR, TMRIS, 7, 1)
+
+#define CLK_EVT -1
+
+static void update_clk(RTMRState *tmr, int ch)
+{
+ int64_t t;
+ static const int divlist[] = {1, 2, 8, 32, 64, 1024, 8192, 0};
+ switch (FIELD_EX8(tmr->ch[ch].tccr, TCCR, CSS)) {
+ case 0:
+ qemu_log_mask(LOG_UNIMP,
+ "renesas_8timer: External clock not implemented.");
+ tmr->ch[ch].clk = 0;
+ break;
+ case 1:
+ /* Internal clock */
+ t = divlist[FIELD_EX8(tmr->ch[ch].tccr, TCCR, CKS)];
+ if (t > 0) {
+ tmr->ch[ch].clk = tmr->input_freq / t;
+ tmr->ch[ch].clk = NANOSECONDS_PER_SECOND / t;
+ } else {
+ tmr->ch[ch].clk = 0;
+ }
+ break;
+ case 2:
+ qemu_log_mask(LOG_UNIMP,
+ "renesas_8timer: CSS undefined.");
+ tmr->ch[ch].clk = 0;
+ break;
+ case 3:
+ /* Event count */
+ tmr->ch[ch].clk = CLK_EVT;
+ break;
+ }
+}
+
+static uint16_t catreg(uint8_t hi, uint8_t lo)
+{
+ uint16_t ret = 0;
+ ret = deposit32(ret, 8, 8, hi);
+ ret = deposit32(ret, 0, 8, lo);
+ return ret;
+}
+
+static int is_clr(uint8_t tcr, int event)
+{
+ return FIELD_EX8(tcr, TCR, CCLR) == (event + 1);
+}
+
+static int is_irq(uint8_t tcr, int event)
+{
+ switch (event) {
+ case cmia:
+ return FIELD_EX8(tcr, TCR, CMIEA);
+ case cmib:
+ return FIELD_EX8(tcr, TCR, CMIEB);
+ case ovi:
+ return FIELD_EX8(tcr, TCR, OVIE);
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void set_next_event(RTMRState *tmr, int ch)
+{
+ int64_t next = 0;
+ int evt;
+ int cor;
+ int min;
+ if (ch == 1 && tmr->ch[ch].word) {
+ /* 16bit count mode */
+ next = 0x10000 - catreg(tmr->ch[0].cnt, tmr->ch[1].cnt);
+ next *= tmr->ch[1].clk;
+ tmr->ch[0].event = tmr->ch[1].event = wovi;
+ } else if (tmr->ch[1].clk > 0) {
+ min = 0x101;
+ for (evt = cmia; evt < TMR_NR_EVENTS - 1; evt++) {
+ cor = (evt < TMR_NR_COR) ? (tmr->ch[ch].cor[evt]) : 0xff;
+ /* event happend compare match +1 */
+ cor++;
+ if (tmr->ch[ch].cnt < cor) {
+ if (evt < TMR_NR_COR &&
+ !is_clr(tmr->ch[ch].tcr, evt) &&
+ !is_irq(tmr->ch[ch].tcr, evt)) {
+ /* no event happend */
+ continue;
+ }
+ if (min > cor) {
+ min = cor;
+ next = cor - tmr->ch[ch].cnt;
+ next *= tmr->ch[ch].clk;
+ tmr->ch[ch].event = evt;
+ }
+ }
+ }
+ }
+ if (next > 0) {
+ tmr->ch[ch].base = tmr->ch[ch].next;
+ tmr->ch[ch].next += next;
+ timer_mod(tmr->ch[ch].timer, tmr->ch[ch].next);
+ } else {
+ timer_del(tmr->ch[ch].timer);
+ }
+}
+
+static void event_countup(struct channel_8tmr *ch)
+{
+ int evt;
+ int cor;
+
+ ch->cnt++;
+ for (evt = cmia; evt < TMR_NR_COR - 1; evt++) {
+ cor = ch->cor[evt];
+ if (ch->cnt == (cor + 1) && is_clr(ch->tcr, evt)) {
+ ch->cnt = 0;
+ }
+ if (ch->cnt == cor && is_irq(ch->tcr, evt)) {
+ qemu_irq_pulse(ch->irq[evt]);
+ }
+ }
+ if (ch->cnt == 0x100) {
+ ch->cnt = 0;
+ if (is_irq(ch->tcr, ovi)) {
+ qemu_irq_pulse(ch->irq[IRQ_OVI]);
+ }
+ }
+}
+
+static void timer_event(void *opaque)
+{
+ struct channel_8tmr *ch = opaque;
+ RTMRState *tmr = ch->tmrp;
+
+ switch (ch->event) {
+ case cmia:
+ if (ch->id == 0 && tmr->ch[1].clk == CLK_EVT) {
+ /* CH1 event count */
+ event_countup(&tmr->ch[1]);
+ }
+ /* Falls through. */
+ case cmib:
+ if (FIELD_EX8(ch->tcr, TCR, CCLR) == (ch->event + 1)) {
+ ch->cnt = 0;
+ } else {
+ ch->cnt = ch->cor[ch->event] + 1;
+ }
+ if (is_irq(ch->tcr, ch->event)) {
+ qemu_irq_pulse(ch->irq[ch->event]);
+ }
+ break;
+ case ovi:
+ ch->cnt = 0;
+ if (is_irq(ch->tcr, ovi)) {
+ qemu_irq_pulse(ch->irq[IRQ_OVI]);
+ }
+ if (ch->id == 1 && tmr->ch[0].clk == CLK_EVT) {
+ /* CH0 event count */
+ event_countup(&tmr->ch[0]);
+ }
+ break;
+ case wovi:
+ tmr->ch[0].cnt = tmr->ch[1].cnt = 0;
+ if (is_irq(tmr->ch[0].tcr, ovi)) {
+ qemu_irq_pulse(tmr->ch[0].irq[IRQ_OVI]);
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ set_next_event(tmr, ch->id);
+}
+
+static uint16_t read_tcnt(RTMRState *tmr, unsigned int size, int ch)
+{
+ int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ int64_t delta;
+ uint8_t ret[2];
+ int i;
+
+ switch (size) {
+ case 1:
+ if (tmr->ch[ch].clk > 0) {
+ delta = now - tmr->ch[ch].base;
+ delta /= tmr->ch[ch].clk;
+ } else {
+ delta = 0;
+ }
+ return tmr->ch[ch].cnt + delta;
+ case 2:
+ if (tmr->ch[1].word) {
+ /* 16bit count mode */
+ delta = now - tmr->ch[1].base;
+ delta /= tmr->ch[1].clk;
+ return catreg(tmr->ch[0].cnt, tmr->ch[1].cnt) + delta;
+ } else {
+ for (i = 0; i < TMR_CH; i++) {
+ if (tmr->ch[ch].clk > 0) {
+ delta = now - tmr->ch[ch].base;
+ delta /= tmr->ch[ch].clk;
+ } else {
+ delta = 0;
+ }
+ ret[i] = tmr->ch[i].cnt + delta;
+ }
+ return catreg(ret[0], ret[1]);
+ }
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static int validate_access(hwaddr addr, unsigned int size)
+{
+ /* Byte access always OK */
+ if (size == 1) {
+ return 1;
+ }
+ return (addr >= A_TCORA);
+}
+
+static uint64_t tmr_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ RTMRState *tmr = opaque;
+ int ch = addr & 1;
+ int cor;
+
+ if (!validate_access(addr, size)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "renesas_tmr: Invalid read size 0x%"
+ HWADDR_PRIX "\n", addr);
+ return UINT64_MAX;
+ }
+ switch (addr & ~1) {
+ case A_TCR:
+ return tmr->ch[ch].tcr;
+ case A_TCSR:
+ return tmr->ch[ch].tcsr;
+ case A_TCORA:
+ case A_TCORB:
+ cor = (addr & 2) >> 1;
+ if (size == 1) {
+ return tmr->ch[ch].cor[cor];
+ } else {
+ return catreg(tmr->ch[0].cor[cor], tmr->ch[1].cor[cor]);
+ }
+ case A_TCNT:
+ return read_tcnt(tmr, size, ch);
+ case A_TCCR:
+ if (size == 1) {
+ return tmr->ch[ch].tccr;
+ } else {
+ return catreg(tmr->ch[0].tccr, tmr->ch[1].tccr);
+ }
+ default:
+ qemu_log_mask(LOG_UNIMP, "renesas_tmr: Register 0x%" HWADDR_PRIX
+ " not implemented\n", addr);
+ break;
+ }
+ return UINT64_MAX;
+}
+
+static void tmr_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
+{
+ RTMRState *tmr = opaque;
+ int ch = addr & 1;
+ int cor;
+ int64_t now;
+
+ if (!validate_access(addr, size)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "renesas_tmr: Invalid write size 0x%" HWADDR_PRIX
+ "\n", addr);
+ return;
+ }
+ switch (addr & ~1) {
+ case A_TCR:
+ tmr->ch[ch].tcr = val;
+ break;
+ case A_TCSR:
+ if (ch == 1) {
+ val = FIELD_DP8(val, TCSR, ADTE, 1);
+ }
+ tmr->ch[ch].tcsr = val;
+ break;
+ case A_TCORA:
+ case A_TCORB:
+ cor = (addr & 2) >> 1;
+ if (size == 1) {
+ tmr->ch[ch].cor[cor] = val;
+ } else {
+ tmr->ch[0].cor[cor] = extract32(val, 0, 8);
+ tmr->ch[1].cor[cor] = extract32(val, 8, 8);
+ }
+ break;
+ case A_TCNT:
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ if (size == 1) {
+ tmr->ch[ch].base = now;
+ tmr->ch[ch].cnt = val;
+ } else {
+ tmr->ch[0].base = tmr->ch[1].base = now;
+ tmr->ch[0].cnt = extract32(val, 0, 8);
+ tmr->ch[1].cnt = extract32(val, 8, 8);
+ }
+ break;
+ case A_TCCR:
+ val &= ~0x6060;
+ if (size == 1) {
+ tmr->ch[ch].tccr = val;
+ update_clk(tmr, ch);
+ } else {
+ tmr->ch[0].tccr = extract32(val, 0, 8);
+ tmr->ch[1].tccr = extract32(val, 8, 8);
+ update_clk(tmr, 0);
+ update_clk(tmr, 1);
+ }
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "renesas_tmr: Register 0x%" HWADDR_PRIX
+ " not implemented\n", addr);
+ return;
+ }
+ /*
+ * If some conditions are met,
+ * the event does not occur until the 16-bit counter overflows.
+ */
+ tmr->ch[1].word = (tmr->ch[0].clk == -1 && tmr->ch[1].clk > 0 &&
+ (tmr->ch[0].tcr & 0xe8) == 0x00 &&
+ (tmr->ch[0].tcr & 0xf8) == 0x00);
+ if (size == 1) {
+ set_next_event(tmr, ch);
+ } else {
+ set_next_event(tmr, 0);
+ set_next_event(tmr, 1);
+ }
+}
+
+static const MemoryRegionOps tmr_ops = {
+ .write = tmr_write,
+ .read = tmr_read,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 2,
+ },
+};
+
+static void rtmr_realize(DeviceState *dev, Error **errp)
+{
+ SysBusDevice *d = SYS_BUS_DEVICE(dev);
+ RTMRState *tmr = RTMR(dev);
+ int i;
+
+ if (tmr->input_freq == 0) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "renesas_8tmr: input-freq property must be set.");
+ return;
+ }
+
+ memory_region_init_io(&tmr->memory, OBJECT(tmr), &tmr_ops,
+ tmr, "renesas-8tmr", 0x10);
+ sysbus_init_mmio(d, &tmr->memory);
+
+ for (i = 0; i < TMR_CH; i++) {
+ sysbus_init_irq(d, &tmr->ch[i].irq[IRQ_CMIA]);
+ sysbus_init_irq(d, &tmr->ch[i].irq[IRQ_CMIB]);
+ sysbus_init_irq(d, &tmr->ch[i].irq[IRQ_OVI]);
+ tmr->ch[i].id = i;
+ tmr->ch[i].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
+ timer_event, &tmr->ch[i]);
+ tmr->ch[i].tmrp = tmr;
+ tmr->ch[i].tcr = 0x00;
+ tmr->ch[i].tcsr = (i == 0) ? 0x00 : 0x10;
+ tmr->ch[i].cnt = 0x00;
+ tmr->ch[i].cor[0] = 0xff;
+ tmr->ch[i].cor[1] = 0xff;
+ tmr->ch[i].tccr = 0x00;
+ }
+}
+
+static const VMStateDescription vmstate_rtmr = {
+ .name = "renesas-8tmr",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static Property rtmr_properties[] = {
+ DEFINE_PROP_UINT64("input-freq", RTMRState, input_freq, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void rtmr_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->vmsd = &vmstate_rtmr;
+ dc->realize = rtmr_realize;
+ device_class_set_props(dc, rtmr_properties);
+}
+
+static const TypeInfo rtmr_info = {
+ .name = TYPE_RENESAS_8TMR,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(RTMRState),
+ .class_init = rtmr_class_init,
+};
+
+static void rtmr_register_types(void)
+{
+ type_register_static(&rtmr_info);
+}
+
+type_init(rtmr_register_types)
diff --git a/hw/timer/Kconfig b/hw/timer/Kconfig
index 59b3f44d69..93f62999eb 100644
--- a/hw/timer/Kconfig
+++ b/hw/timer/Kconfig
@@ -35,3 +35,6 @@ config CMSDK_APB_TIMER
config CMSDK_APB_DUALTIMER
bool
select PTIMER
+
+config RENESAS_8TMR
+ bool
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index dece235fd7..9ea88b964d 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -35,3 +35,5 @@ common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o
common-obj-$(CONFIG_CMSDK_APB_DUALTIMER) += cmsdk-apb-dualtimer.o
common-obj-$(CONFIG_MSF2) += mss-timer.o
common-obj-$(CONFIG_RASPI) += bcm2835_systmr.o
+
+common-obj-$(CONFIG_RENESAS_8TMR) += renesas_8timer.o
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 03/10] hw/timer: Renesas TMU/CMT module.
2020-05-31 16:24 [PATCH 00/10] Add RX hardware emulation Yoshinori Sato
2020-05-31 16:24 ` [PATCH 01/10] hw/intc: RX62N interrupt controller (ICUa) Yoshinori Sato
2020-05-31 16:24 ` [PATCH 02/10] hw/timer: Renesas 8bit timer module Yoshinori Sato
@ 2020-05-31 16:24 ` Yoshinori Sato
2020-05-31 16:24 ` [PATCH 04/10] hw/char: Renesas SCI module Yoshinori Sato
` (7 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Yoshinori Sato @ 2020-05-31 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: Yoshinori Sato
TMU - SH4 Timer module.
CMT - Compare and match timer used by some Renesas MCUs.
The two modules have similar interfaces and have been merged.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
include/hw/timer/renesas_timer.h | 59 +++++
hw/timer/renesas_timer.c | 421 +++++++++++++++++++++++++++++++
hw/timer/Kconfig | 3 +
hw/timer/Makefile.objs | 1 +
4 files changed, 484 insertions(+)
create mode 100644 include/hw/timer/renesas_timer.h
create mode 100644 hw/timer/renesas_timer.c
diff --git a/include/hw/timer/renesas_timer.h b/include/hw/timer/renesas_timer.h
new file mode 100644
index 0000000000..f9a2661203
--- /dev/null
+++ b/include/hw/timer/renesas_timer.h
@@ -0,0 +1,59 @@
+/*
+ * Renesas Timer unit Object
+ *
+ * Copyright (c) 2020 Yoshinori Sato
+ *
+ * This code is licensed under the GPL version 2 or later.
+ *
+ */
+
+#ifndef HW_RENESAS_TIMER_H
+#define HW_RENESAS_TIMER_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_RENESAS_TIMER "renesas-timer"
+#define RTIMER(obj) OBJECT_CHECK(RTIMERState, (obj), TYPE_RENESAS_TIMER)
+
+enum {
+ TIMER_CH_CMT = 2,
+ /* TMU have 5channels. It separated 0-2 and 3-4. */
+ TIMER_CH_TMU = 3,
+};
+
+enum {
+ RTIMER_FEAT_CMT,
+ RTIMER_FEAT_TMU_LOW,
+ RTIMER_FEAT_TMU_HIGH,
+};
+
+struct RTIMERState;
+
+struct channel_rtimer {
+ uint32_t cnt;
+ uint32_t cor;
+ uint16_t ctrl;
+ qemu_irq irq;
+ int64_t base;
+ int64_t next;
+ uint64_t clk;
+ bool start;
+ QEMUTimer *timer;
+ struct RTIMERState *tmrp;
+};
+
+typedef struct RTIMERState {
+ SysBusDevice parent_obj;
+
+ uint64_t input_freq;
+ MemoryRegion memory;
+ MemoryRegion memory_p4;
+ MemoryRegion memory_a7;
+
+ uint8_t tocr;
+ struct channel_rtimer ch[TIMER_CH_TMU];
+ uint32_t feature;
+ int num_ch;
+} RTIMERState;
+
+#endif
diff --git a/hw/timer/renesas_timer.c b/hw/timer/renesas_timer.c
new file mode 100644
index 0000000000..459c7a4708
--- /dev/null
+++ b/hw/timer/renesas_timer.c
@@ -0,0 +1,421 @@
+/*
+ * Renesas 16bit Compare-match timer
+ *
+ * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware
+ * (Rev.1.40 R01UH0033EJ0140)
+ *
+ * Copyright (c) 2019 Yoshinori Sato
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "qemu/timer.h"
+#include "hw/hw.h"
+#include "hw/irq.h"
+#include "hw/sysbus.h"
+#include "hw/registerfields.h"
+#include "hw/qdev-properties.h"
+#include "hw/timer/renesas_timer.h"
+#include "migration/vmstate.h"
+#include "qemu/error-report.h"
+
+REG32(TOCR, 0)
+ FIELD(TOCR, TCOE, 0, 1)
+REG32(TSTR, 4)
+REG32(TCOR, 8)
+REG32(TCNT, 12)
+REG32(TCR, 16)
+ FIELD(TCR, TPSC, 0, 3)
+ FIELD(TCR, CKEG, 3, 2)
+ FIELD(TCR, UNIE, 5, 1)
+ FIELD(TCR, ICPE, 6, 2)
+ FIELD(TCR, UNF, 8, 1)
+ FIELD(TCR, ICPF, 9, 1)
+REG32(CMCR, 16)
+ FIELD(CMCR, CKS, 0, 2)
+ FIELD(CMCR, CMIE, 6, 1)
+REG32(TCPR, 20)
+
+#define IS_CMT(t) (t->feature == RTIMER_FEAT_CMT)
+
+static int clkdiv(RTIMERState *tmr, int ch)
+{
+ if (IS_CMT(tmr)) {
+ return 8 << (2 * FIELD_EX16(tmr->ch[ch].ctrl, CMCR, CKS));
+ } else {
+ if (FIELD_EX16(tmr->ch[ch].ctrl, TCR, TPSC) <= 5) {
+ return 4 << (2 * FIELD_EX16(tmr->ch[ch].ctrl, TCR, TPSC));
+ } else {
+ return 0;
+ }
+ }
+}
+
+static void set_next_event(struct channel_rtimer *ch, int64_t now)
+{
+ int64_t next;
+ RTIMERState *tmr = ch->tmrp;
+ if (IS_CMT(tmr)) {
+ next = ch->cor - ch->cnt;
+ } else {
+ next = ch->cnt;
+ }
+ next *= ch->clk;
+ ch->base = now;
+ ch->next = now + next;
+ timer_mod(ch->timer, ch->next);
+}
+
+static void timer_event(void *opaque)
+{
+ struct channel_rtimer *ch = opaque;
+ RTIMERState *tmr = ch->tmrp;
+
+ if (IS_CMT(tmr)) {
+ ch->cnt = 0;
+ if (FIELD_EX16(ch->ctrl, CMCR, CMIE)) {
+ qemu_irq_pulse(ch->irq);
+ }
+ } else {
+ ch->cnt = ch->cor;
+ if (!FIELD_EX16(ch->ctrl, TCR, UNF)) {
+ ch->ctrl = FIELD_DP16(ch->ctrl, TCR, UNF, 1);
+ qemu_set_irq(ch->irq, FIELD_EX16(ch->ctrl, TCR, UNIE));
+ }
+ }
+ set_next_event(ch, ch->next);
+}
+
+static int64_t read_tcnt(RTIMERState *tmr, int ch)
+{
+ int64_t delta, now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+
+ if (tmr->ch[ch].clk > 0) {
+ delta = (now - tmr->ch[ch].base);
+ delta /= tmr->ch[ch].clk;
+ if (IS_CMT(tmr)) {
+ return delta;
+ } else {
+ return tmr->ch[ch].cnt - delta;
+ }
+ } else {
+ return tmr->ch[ch].cnt;
+ }
+}
+
+static void tmr_start_stop(RTIMERState *tmr, int ch, int start)
+{
+ int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ tmr->ch[ch].start = start;
+ if (start) {
+ if (!tmr->ch[ch].timer) {
+ tmr->ch[ch].timer =
+ timer_new_ns(QEMU_CLOCK_VIRTUAL, timer_event, &tmr->ch[ch]);
+ }
+ set_next_event(&tmr->ch[ch], now);
+ } else {
+ tmr->ch[ch].cnt = read_tcnt(tmr, ch);
+ tmr->ch[ch].next = 0;
+ if (tmr->ch[ch].timer) {
+ timer_del(tmr->ch[ch].timer);
+ }
+ }
+}
+
+static void timer_register(RTIMERState *tmr, hwaddr addr, int *ch, int *reg)
+{
+ if (IS_CMT(tmr)) {
+ /* +0 - CMSTR (TSTR) */
+ /* +2 - CMCR0 (TCR) */
+ /* +4 - CMCNT0 (TCNT) */
+ /* +6 - CMCOR0 (TCOR) */
+ /* +8 - CMCR1 (TCR) */
+ /* +10 - CMCNT1 (TCNT) */
+ /* +12 - CMCOR1 (TCOR) */
+ addr /= 2;
+ if (addr > 6) {
+ /* Out of register area */
+ *reg = -1;
+ return;
+ }
+ if (addr == 0) {
+ *ch = -1;
+ *reg = R_TSTR;
+ } else {
+ *ch = addr / 4;
+ if (addr < 4) {
+ /* skip CMSTR */
+ addr--;
+ }
+ *reg = 2 - (addr % 4);
+ }
+ } else {
+ /* +0 - TCOR */
+ /* +4 - TSTR */
+ /* +8 - TCOR0 */
+ /* +12 - TCNT0 */
+ /* +16 - TCR0 */
+ /* +20 - TCOR1 */
+ /* +24 - TCNT1 */
+ /* +28 - TCR1 */
+ /* +32 - TCOR2 */
+ /* +36 - TCNT2 */
+ /* +40 - TCR2 */
+ /* +44 - TCPR2 */
+ if (tmr->feature == RTIMER_FEAT_TMU_HIGH && addr >= 8) {
+ *reg = -1;
+ return;
+ }
+ addr /= 4;
+ if (addr < 2) {
+ *ch = -1;
+ *reg = addr;
+ } else if (addr < 11) {
+ *ch = (addr - 2) / 3;
+ *reg = (addr - 2) % 3 + 2;
+ } else {
+ *ch = 2;
+ *reg = R_TCPR;
+ }
+ }
+}
+
+static uint64_t read_tstr(RTIMERState *tmr)
+{
+ uint64_t ret = 0;
+ int ch;
+ for (ch = 0; ch < tmr->num_ch; ch++) {
+ ret = deposit64(ret, ch, 1, tmr->ch[ch].start);
+ }
+ return ret;
+}
+
+static void update_clk(RTIMERState *tmr, int ch)
+{
+ int tpsc;
+ int t;
+ if (!IS_CMT(tmr)) {
+ /* Clock setting validation */
+ tpsc = FIELD_EX16(tmr->ch[ch].ctrl, TCR, TPSC);
+ switch (tpsc) {
+ case 5:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "renesas_timer: Invalid TPSC valule %d.", tpsc);
+ break;
+ case 6:
+ case 7:
+ qemu_log_mask(LOG_UNIMP,
+ "renesas_timer: External clock not implemented.");
+ break;
+ }
+ /* Interrupt clear */
+ if (FIELD_EX16(tmr->ch[ch].ctrl, TCR, UNF) == 0) {
+ qemu_set_irq(tmr->ch[ch].irq, 0);
+ }
+ }
+ t = clkdiv(tmr, ch);
+ if (t > 0) {
+ t = tmr->input_freq / t;
+ tmr->ch[ch].clk = NANOSECONDS_PER_SECOND / t;
+ } else {
+ tmr->ch[ch].clk = 0;
+ }
+}
+
+static uint64_t tmr_read(void *opaque, hwaddr addr, unsigned size)
+{
+ RTIMERState *tmr = opaque;
+ int ch = -1, reg = -1;
+
+ timer_register(tmr, addr, &ch, ®);
+ switch (reg) {
+ case R_TOCR:
+ return tmr->tocr;
+ case R_TSTR:
+ return read_tstr(tmr);
+ case R_TCR:
+ return tmr->ch[ch].ctrl;
+ case R_TCNT:
+ if (tmr->ch[ch].start) {
+ return read_tcnt(tmr, ch);
+ } else {
+ return tmr->ch[ch].cnt;
+ }
+ case R_TCOR:
+ return tmr->ch[ch].cor;
+ case R_TCPR:
+ qemu_log_mask(LOG_UNIMP,
+ "renesas_timer: Input capture not implemented\n");
+ return 0;
+ default:
+ qemu_log_mask(LOG_UNIMP, "renesas_timer: Register 0x%"
+ HWADDR_PRIX " not implemented\n", addr);
+ }
+ return UINT64_MAX;
+}
+
+static void tmr_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
+{
+ RTIMERState *tmr = opaque;
+ int ch = -1, reg = -1;
+ uint16_t tcr_mask;
+
+ timer_register(tmr, addr, &ch, ®);
+ switch (reg) {
+ case R_TOCR:
+ tmr->tocr = FIELD_DP8(tmr->tocr, TOCR, TCOE,
+ FIELD_EX8(val, TOCR, TCOE));
+ break;
+ case R_TSTR:
+ for (ch = 0; ch < tmr->num_ch; ch++) {
+ tmr_start_stop(tmr, ch, extract32(val, ch, 1));
+ }
+ break;
+ case R_TCR:
+ switch (tmr->feature) {
+ case RTIMER_FEAT_CMT:
+ tcr_mask = 0x00a3;
+ /* bit7 always 1 */
+ val |= 0x0080;
+ break;
+ case RTIMER_FEAT_TMU_LOW:
+ tcr_mask = (ch < 2) ? 0x013f : 0x03ff;
+ break;
+ case RTIMER_FEAT_TMU_HIGH:
+ tcr_mask = 0x0127;
+ break;
+ default:
+ tcr_mask = 0x00ff;
+ break;
+ }
+ /* Upper byte write only 0 */
+ tmr->ch[ch].ctrl |= (tcr_mask & 0x00ff);
+ tmr->ch[ch].ctrl &= val & tcr_mask;
+ update_clk(tmr, ch);
+ break;
+ case R_TCNT:
+ tmr->ch[ch].cnt = val;
+ break;
+ case R_TCOR:
+ tmr->ch[ch].cor = val;
+ break;
+ case R_TCPR:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "renesas_timer: TCPR is read only.");
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "renesas_timer: Register 0x%"
+ HWADDR_PRIX " not implemented\n", addr);
+ }
+}
+
+static const MemoryRegionOps tmr_ops = {
+ .write = tmr_write,
+ .read = tmr_read,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ .min_access_size = 2,
+ .max_access_size = 4,
+ },
+};
+
+static void rtimer_realize(DeviceState *dev, Error **errp)
+{
+ SysBusDevice *d = SYS_BUS_DEVICE(dev);
+ RTIMERState *tmr = RTIMER(dev);
+ int i;
+ int ch;
+
+ if (tmr->input_freq == 0) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "renesas_timer: input-freq property must be set.");
+ return;
+ }
+ if (IS_CMT(tmr)) {
+ memory_region_init_io(&tmr->memory, OBJECT(tmr), &tmr_ops,
+ tmr, "renesas-cmt", 0x10);
+ sysbus_init_mmio(d, &tmr->memory);
+
+ for (i = 0; i < TIMER_CH_CMT; i++) {
+ sysbus_init_irq(d, &tmr->ch[i].irq);
+ }
+ tmr->num_ch = 2;
+ } else {
+ memory_region_init_io(&tmr->memory, OBJECT(tmr), &tmr_ops,
+ tmr, "renesas-tmu", 0x30);
+ sysbus_init_mmio(d, &tmr->memory);
+ memory_region_init_alias(&tmr->memory_p4, NULL, "renesas-tmu-p4",
+ &tmr->memory, 0, 0x30);
+ sysbus_init_mmio(d, &tmr->memory_p4);
+ memory_region_init_alias(&tmr->memory_a7, NULL, "renesas-tmu-a7",
+ &tmr->memory, 0, 0x30);
+ sysbus_init_mmio(d, &tmr->memory_a7);
+ ch = (tmr->feature == RTIMER_FEAT_TMU_LOW) ?
+ TIMER_CH_TMU : TIMER_CH_TMU - 1;
+ for (i = 0; i < ch; i++) {
+ sysbus_init_irq(d, &tmr->ch[i].irq);
+ }
+ tmr->num_ch = (tmr->feature == RTIMER_FEAT_TMU_LOW) ? 3 : 2;
+ }
+ for (ch = 0; ch < tmr->num_ch; ch++) {
+ tmr->ch[ch].tmrp = tmr;
+ update_clk(tmr, ch);
+ if (IS_CMT(tmr)) {
+ tmr->ch[ch].cor = 0xffff;
+ } else {
+ tmr->ch[ch].cor = tmr->ch[ch].cnt = 0xffffffff;
+ }
+ }
+}
+
+static const VMStateDescription vmstate_rtimer = {
+ .name = "rx-cmt",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static Property rtimer_properties[] = {
+ DEFINE_PROP_UINT32("feature", RTIMERState, feature, 0),
+ DEFINE_PROP_UINT64("input-freq", RTIMERState, input_freq, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void rtimer_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->vmsd = &vmstate_rtimer;
+ dc->realize = rtimer_realize;
+ device_class_set_props(dc, rtimer_properties);
+}
+
+static const TypeInfo rtimer_info = {
+ .name = TYPE_RENESAS_TIMER,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(RTIMERState),
+ .class_init = rtimer_class_init,
+};
+
+static void rtimer_register_types(void)
+{
+ type_register_static(&rtimer_info);
+}
+
+type_init(rtimer_register_types)
diff --git a/hw/timer/Kconfig b/hw/timer/Kconfig
index 93f62999eb..ff4b0cd0bc 100644
--- a/hw/timer/Kconfig
+++ b/hw/timer/Kconfig
@@ -38,3 +38,6 @@ config CMSDK_APB_DUALTIMER
config RENESAS_8TMR
bool
+
+config RENESAS_TIMER
+ bool
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index 9ea88b964d..289b6b03ab 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -37,3 +37,4 @@ common-obj-$(CONFIG_MSF2) += mss-timer.o
common-obj-$(CONFIG_RASPI) += bcm2835_systmr.o
common-obj-$(CONFIG_RENESAS_8TMR) += renesas_8timer.o
+common-obj-$(CONFIG_RENESAS_TIMER) += renesas_timer.o
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 04/10] hw/char: Renesas SCI module.
2020-05-31 16:24 [PATCH 00/10] Add RX hardware emulation Yoshinori Sato
` (2 preceding siblings ...)
2020-05-31 16:24 ` [PATCH 03/10] hw/timer: Renesas TMU/CMT module Yoshinori Sato
@ 2020-05-31 16:24 ` Yoshinori Sato
2020-06-05 16:05 ` Philippe Mathieu-Daudé
2020-05-31 16:24 ` [PATCH 05/10] hw/rx: RX MCU and target Yoshinori Sato
` (6 subsequent siblings)
10 siblings, 1 reply; 17+ messages in thread
From: Yoshinori Sato @ 2020-05-31 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: Yoshinori Sato
This module supported SCI / SCIa / SCIF.
Hardware manual.
SCI / SCIF
https://www.renesas.com/us/en/doc/products/mpumcu/001/r01uh0457ej0401_sh7751.pdf
SCIa
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
include/hw/char/renesas_sci.h | 77 ++++
hw/char/renesas_sci.c | 786 ++++++++++++++++++++++++++++++++++
hw/char/Kconfig | 3 +
hw/char/Makefile.objs | 3 +-
4 files changed, 868 insertions(+), 1 deletion(-)
create mode 100644 include/hw/char/renesas_sci.h
create mode 100644 hw/char/renesas_sci.c
diff --git a/include/hw/char/renesas_sci.h b/include/hw/char/renesas_sci.h
new file mode 100644
index 0000000000..9152faff6c
--- /dev/null
+++ b/include/hw/char/renesas_sci.h
@@ -0,0 +1,77 @@
+/*
+ * Renesas Serial Communication Interface
+ *
+ * Copyright (c) 2020 Yoshinori Sato
+ *
+ * This code is licensed under the GPL version 2 or later.
+ *
+ */
+
+#include "chardev/char-fe.h"
+#include "qemu/timer.h"
+#include "qemu/fifo8.h"
+#include "hw/sysbus.h"
+
+#define TYPE_RENESAS_SCI "renesas-sci"
+#define RSCI(obj) OBJECT_CHECK(RSCIState, (obj), TYPE_RENESAS_SCI)
+
+enum {
+ ERI = 0,
+ RXI = 1,
+ TXI = 2,
+ TEI = 3,
+ BRI = 3,
+ SCI_NR_IRQ = 4,
+};
+
+enum {
+ SCI_FEAT_SCI = 0x00,
+ SCI_FEAT_SCIA = 0x01,
+ SCI_FEAT_SCIF = 0x10,
+};
+
+enum {
+ RXTOUT,
+ RXNEXT,
+ TXEMPTY,
+ TXEND,
+ NR_SCI_EVENT,
+};
+
+typedef struct RSCIState {
+ SysBusDevice parent_obj;
+ MemoryRegion memory;
+ MemoryRegion memory_p4;
+ MemoryRegion memory_a7;
+
+ /* SCI register */
+ uint8_t smr;
+ uint8_t brr;
+ uint8_t scr;
+ uint8_t tdr;
+ uint16_t Xsr;
+ uint8_t scmr;
+ uint8_t semr;
+ uint16_t fcr;
+ uint16_t sptr;
+ uint16_t lsr;
+
+ /* internal use */
+ uint16_t read_Xsr;
+ uint16_t read_lsr;
+ int64_t etu;
+ int64_t trtime;
+ int64_t tx_start_time;
+ int tdcnt;
+ int regsize;
+ struct {
+ int64_t time;
+ int64_t (*handler)(struct RSCIState *sci);
+ } event[NR_SCI_EVENT];
+ QEMUTimer *event_timer;
+ CharBackend chr;
+ uint64_t input_freq;
+ int feature;
+ qemu_irq irq[SCI_NR_IRQ];
+ Fifo8 rxfifo;
+} RSCIState;
diff --git a/hw/char/renesas_sci.c b/hw/char/renesas_sci.c
new file mode 100644
index 0000000000..6b23055a40
--- /dev/null
+++ b/hw/char/renesas_sci.c
@@ -0,0 +1,786 @@
+/*
+ * Renesas Serial Communication Interface (SCI / SCIa / SCIF)
+ *
+ * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware
+ * (Rev.1.40 R01UH0033EJ0140)
+ * And SH7751 Group, SH7751R Group User's Manual: Hardware
+ * (Rev.4.01 R01UH0457EJ0401)
+ *
+ * Copyright (c) 2020 Yoshinori Sato
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "hw/hw.h"
+#include "hw/irq.h"
+#include "hw/sysbus.h"
+#include "hw/registerfields.h"
+#include "hw/qdev-properties.h"
+#include "hw/char/renesas_sci.h"
+#include "migration/vmstate.h"
+#include "qemu/error-report.h"
+
+/* SCI register map */
+REG8(SMR, 0)
+ FIELD(SMR, CKS, 0, 2)
+ FIELD(SMR, MP, 2, 1)
+ FIELD(SMR, STOP, 3, 1)
+ FIELD(SMR, PM, 4, 1)
+ FIELD(SMR, PE, 5, 1)
+ FIELD(SMR, CHR, 6, 1)
+ FIELD(SMR, CM, 7, 1)
+REG16(BRR, 2)
+REG16(SCR, 4)
+ FIELD(SCR, CKE, 0, 2)
+ FIELD(SCR, TEIE, 2, 1)
+ FIELD(SCR, MPIE, 3, 1)
+ FIELD(SCR, REIE, 3, 1)
+ FIELD(SCR, RE, 4, 1)
+ FIELD(SCR, TE, 5, 1)
+ FIELD(SCR, RIE, 6, 1)
+ FIELD(SCR, TIE, 7, 1)
+REG16(TDR, 6)
+REG16(SSR, 8)
+ FIELD(SSR, MPBT, 0, 1)
+ FIELD(SSR, MPB, 1, 1)
+ FIELD(SSR, TEND, 2, 1)
+ FIELD(SSR, ERR, 3, 3)
+ FIELD(SSR, PER, 3, 1)
+ FIELD(SSR, FER, 4, 1)
+ FIELD(SSR, ORER, 5, 1)
+ FIELD(SSR, RDRF, 6, 1)
+ FIELD(SSR, TDRE, 7, 1)
+REG16(FSR, 8)
+ FIELD(FSR, DR, 0, 1)
+ FIELD(FSR, RDF, 1, 1)
+ FIELD(FSR, RDF_DR, 0, 2)
+ FIELD(FSR, PER, 2, 1)
+ FIELD(FSR, FER, 3, 1)
+ FIELD(FSR, BRK, 4, 1)
+ FIELD(FSR, TDFE, 5, 1)
+ FIELD(FSR, TEND, 6, 1)
+ FIELD(FSR, ER, 7, 1)
+ FIELD(FSR, FERn, 8, 4)
+ FIELD(FSR, PERn, 12, 4)
+REG16(RDR, 10)
+REG16(SCMR, 12)
+ FIELD(SCMR, SMIF, 0, 1)
+ FIELD(SCMR, SINV, 2, 1)
+ FIELD(SCMR, SDIR, 3, 1)
+ FIELD(SCMR, BCP2, 7, 1)
+REG16(FCR, 12)
+ FIELD(FCR, LOOP, 0, 1)
+ FIELD(FCR, RFRST, 1, 1)
+ FIELD(FCR, TFRST, 2, 1)
+ FIELD(FCR, MCE, 3, 1)
+ FIELD(FCR, TTRG, 4, 2)
+ FIELD(FCR, RTRG, 6, 2)
+ FIELD(FCR, RSTRG, 8, 3)
+REG16(SEMR, 14)
+ FIELD(SEMR, ACS0, 0, 1)
+ FIELD(SEMR, ABCS, 4, 1)
+REG16(FDR, 14)
+ FIELD(FDR, Rn, 0, 4)
+ FIELD(FDR, Tn, 8, 4)
+REG16(SPTR, 16)
+ FIELD(SPTR, SPB2DT, 0, 1)
+ FIELD(SPTR, SPB2IO, 1, 1)
+ FIELD(SPTR, SCKDT, 2, 1)
+ FIELD(SPTR, SCKIO, 3, 1)
+ FIELD(SPTR, CTSDT, 4, 1)
+ FIELD(SPTR, CTSIO, 5, 1)
+ FIELD(SPTR, RTSDT, 6, 1)
+ FIELD(SPTR, RTSIO, 7, 1)
+ FIELD(SPTR, EIO, 7, 1)
+REG16(LSR, 18)
+ FIELD(LSR, ORER, 0, 1)
+
+#define SCIF_FIFO_DEPTH 16
+#define IS_SCI(sci) (sci->feature < SCI_FEAT_SCIF)
+#define IS_SCIA(sci) (IS_SCI(sci) && sci->feature >= SCI_FEAT_SCIA)
+#define IS_SCIF(sci) (!IS_SCI(sci))
+
+static const int sci_rtrg[] = {1, 4, 8, 14};
+
+static void update_event_time(RSCIState *sci, int evt, int64_t t)
+{
+ if (t > 0) {
+ t += qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ sci->event[evt].time = t;
+ if (timer_expire_time_ns(sci->event_timer) > t) {
+ timer_mod(sci->event_timer, t);
+ }
+ } else {
+ sci->event[evt].time = 0;
+ }
+}
+
+static int sci_is_rxi(RSCIState *sci)
+{
+ int eio;
+ int enable;
+ enable = FIELD_EX16(sci->scr, SCR, RIE);
+ if (IS_SCI(sci)) {
+ eio = (sci->feature != SCI_FEAT_SCI) ||
+ (FIELD_EX16(sci->sptr, SPTR, EIO) == 0);
+ return FIELD_EX16(sci->Xsr, SSR, RDRF) && enable && eio;
+ } else {
+ return (FIELD_EX16(sci->Xsr, FSR, RDF_DR) != 0) && enable;
+ }
+}
+
+static int sci_is_txi(RSCIState *sci)
+{
+ int enable = FIELD_EX16(sci->scr, SCR, TIE);
+ if (IS_SCI(sci)) {
+ return enable && FIELD_EX16(sci->Xsr, SSR, TDRE);
+ } else {
+ return enable && FIELD_EX16(sci->Xsr, FSR, TDFE);
+ }
+}
+
+static void sci_irq(RSCIState *sci, int req)
+{
+ int br;
+ int irq;
+ int rie;
+
+ switch (req) {
+ case ERI:
+ rie = FIELD_EX16(sci->scr, SCR, RIE);
+ if (IS_SCI(sci)) {
+ irq = rie && (FIELD_EX16(sci->Xsr, SSR, ERR) != 0);
+ } else {
+ irq = (rie || FIELD_EX16(sci->scr, SCR, REIE)) &&
+ FIELD_EX16(sci->Xsr, FSR, ER);
+ }
+ qemu_set_irq(sci->irq[ERI], irq);
+ break;
+ case RXI:
+ if (IS_SCIA(sci)) {
+ if (sci_is_rxi(sci)) {
+ qemu_irq_pulse(sci->irq[RXI]);
+ }
+ } else {
+ qemu_set_irq(sci->irq[RXI], sci_is_rxi(sci));
+ }
+ break;
+ case TXI:
+ if (IS_SCIA(sci)) {
+ if (sci_is_txi(sci)) {
+ qemu_irq_pulse(sci->irq[TXI]);
+ }
+ } else {
+ qemu_set_irq(sci->irq[TXI], sci_is_txi(sci));
+ }
+ break;
+ case BRI: /* TEI */
+ if (IS_SCI(sci)) {
+ qemu_set_irq(sci->irq[TEI],
+ FIELD_EX16(sci->Xsr, SSR, TEND) &&
+ FIELD_EX16(sci->scr, SCR, TEIE));
+ } else {
+ rie = FIELD_EX16(sci->scr, SCR, RIE);
+ br = (rie || FIELD_EX16(sci->scr, SCR, REIE)) &&
+ FIELD_EX16(sci->Xsr, FSR, BRK);
+ qemu_set_irq(sci->irq[BRI], br);
+ }
+ break;
+ }
+}
+
+static int can_receive(void *opaque)
+{
+ RSCIState *sci = RSCI(opaque);
+ int fifo_free = 0;
+ if (FIELD_EX16(sci->scr, SCR, RE)) {
+ /* Receiver enabled */
+ fifo_free = fifo8_num_free(&sci->rxfifo);
+ if (IS_SCIF(sci) && fifo_free == 0) {
+ /* FIFO overrun */
+ sci->lsr = FIELD_DP16(sci->lsr, LSR, ORER, 1);
+ sci_irq(sci, ERI);
+ }
+ }
+ return fifo_free;
+}
+
+static void sci_receive(void *opaque, const uint8_t *buf, int size)
+{
+ RSCIState *sci = RSCI(opaque);
+ int rtrg;
+
+ fifo8_push_all(&sci->rxfifo, buf, size);
+ if (sci->event[RXNEXT].time == 0) {
+ if (IS_SCI(sci)) {
+ sci->Xsr = FIELD_DP16(sci->Xsr, SSR, RDRF, 1);
+ update_event_time(sci, RXNEXT, sci->trtime);
+ } else {
+ rtrg = sci_rtrg[FIELD_EX16(sci->fcr, FCR, RTRG)];
+ if (fifo8_num_used(&sci->rxfifo) >= rtrg) {
+ sci->Xsr = FIELD_DP16(sci->Xsr, FSR, RDF, 1);
+ } else {
+ update_event_time(sci, RXTOUT, 15 * sci->etu);
+ }
+ }
+ sci_irq(sci, RXI);
+ }
+}
+
+static void sci_send_byte(RSCIState *sci)
+{
+ if (IS_SCI(sci)) {
+ if (qemu_chr_fe_backend_connected(&sci->chr)) {
+ qemu_chr_fe_write_all(&sci->chr, &sci->tdr, 1);
+ }
+ sci->Xsr = FIELD_DP16(sci->Xsr, SSR, TEND, 0);
+ sci->Xsr = FIELD_DP16(sci->Xsr, SSR, TDRE, 1);
+ }
+}
+
+static int transmit_byte(RSCIState *sci)
+{
+ int64_t elapsed;
+ int byte = 0;
+ if (sci->tx_start_time > 0) {
+ elapsed = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - sci->tx_start_time;
+ byte = elapsed / sci->trtime;
+ if (byte > sci->tdcnt) {
+ byte = sci->tdcnt;
+ }
+ }
+ return byte;
+}
+
+static int64_t sci_rx_timeout(RSCIState *sci)
+{
+ if (IS_SCIF(sci)) {
+ sci->Xsr = FIELD_DP16(sci->Xsr, FSR, DR, 1);
+ sci_irq(sci, RXI);
+ }
+ return 0;
+}
+
+static int64_t sci_rx_next(RSCIState *sci)
+{
+ int64_t next_event = 0;
+ if (IS_SCI(sci) && !fifo8_is_empty(&sci->rxfifo)) {
+ if (FIELD_EX16(sci->Xsr, SSR, RDRF)) {
+ /* Receiver overrun */
+ sci->Xsr = FIELD_DP16(sci->Xsr, SSR, ORER, 1);
+ sci_irq(sci, ERI);
+ } else {
+ /* Trigger next event */
+ sci->Xsr = FIELD_DP16(sci->Xsr, SSR, RDRF, 1);
+ sci_irq(sci, RXI);
+ next_event = sci->trtime;
+ }
+ }
+ return next_event;
+}
+
+static int64_t sci_tx_empty(RSCIState *sci)
+{
+ int64_t ret = 0;
+ if (IS_SCI(sci)) {
+ if (!FIELD_EX16(sci->Xsr, SSR, TDRE)) {
+ sci_send_byte(sci);
+ ret = sci->trtime;
+ sci_irq(sci, TXI);
+ } else {
+ sci->Xsr = FIELD_DP16(sci->Xsr, SSR, TEND, 1);
+ sci_irq(sci, TEI);
+ }
+ } else {
+ sci->tdcnt -= transmit_byte(sci);
+ sci->Xsr = FIELD_DP16(sci->Xsr, FSR, TDFE, 1);
+ sci_irq(sci, TXI);
+ }
+ return ret;
+}
+
+static int64_t sci_tx_end(RSCIState *sci)
+{
+ if (IS_SCIF(sci)) {
+ sci->tdcnt = 0;
+ sci->Xsr = FIELD_DP16(sci->Xsr, FSR, TEND, 1);
+ sci_irq(sci, TEI);
+ }
+ return 0;
+}
+
+static void sci_timer_event(void *opaque)
+{
+ RSCIState *sci = RSCI(opaque);
+ int64_t now, next, t;
+ int i;
+
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ next = INT64_MAX;
+ for (i = 0; i < NR_SCI_EVENT; i++) {
+ if (sci->event[i].time > 0 && sci->event[i].time <= now) {
+ t = sci->event[i].handler(sci);
+ sci->event[i].time = (t > 0) ? now + t : 0;
+ }
+ if (sci->event[i].time > 0) {
+ next = MIN(next, sci->event[i].time);
+ }
+ }
+ if (next < INT64_MAX) {
+ timer_mod(sci->event_timer, next);
+ } else {
+ timer_del(sci->event_timer);
+ }
+}
+
+static void update_trtime(RSCIState *sci)
+{
+ int divrate;
+ if (IS_SCIA(sci)) {
+ divrate = 16 * (2 - FIELD_EX8(sci->semr, SEMR, ABCS));
+ } else {
+ divrate = 32;
+ }
+
+ /* x bit transmit time (divrate * brr) / base freq */
+ sci->etu = divrate * 1 << (2 * FIELD_EX16(sci->smr, SMR, CKS));
+ sci->etu *= sci->brr + 1;
+ sci->etu *= NANOSECONDS_PER_SECOND;
+ sci->etu /= sci->input_freq;
+
+ /* char per bits */
+ sci->trtime = 8 - FIELD_EX16(sci->smr, SMR, CHR);
+ sci->trtime += FIELD_EX16(sci->smr, SMR, PE);
+ sci->trtime += FIELD_EX16(sci->smr, SMR, STOP) + 1 + 1;
+ sci->trtime *= sci->etu;
+}
+
+#define IS_TR_ENABLED(scr) \
+ (FIELD_EX16(scr, SCR, TE) || FIELD_EX16(scr, SCR, RE))
+
+#define SCI_IS_NOT_SUPPORTED(sci, name) \
+ if (sci->feature == SCI_FEAT_SCI) { \
+ qemu_log_mask(LOG_GUEST_ERROR, \
+ "reneas_sci: " #name " is not supported.\n"); \
+ }
+
+static void sci_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
+{
+ RSCIState *sci = RSCI(opaque);
+ int txtrg;
+ int rxtrg;
+ uint8_t txd;
+ uint16_t ssr_mask;
+ bool tx_start = false;
+
+ if (IS_SCI(sci)) {
+ txtrg = 1;
+ } else {
+ txtrg = 1 << (3 - FIELD_EX16(sci->fcr, FCR, TTRG));
+ }
+ switch (sci->regsize) {
+ case 8:
+ addr <<= 1; break;
+ case 32:
+ addr >>= 1; break;
+ }
+ switch (addr) {
+ case A_SMR:
+ if (IS_SCIA(sci) && IS_TR_ENABLED(sci->scr)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "reneas_sci: SMR write protected.\n");
+ break;
+ }
+ sci->smr = val;
+ update_trtime(sci);
+ break;
+ case A_BRR:
+ if (IS_SCIA(sci) && IS_TR_ENABLED(sci->scr)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "reneas_sci: BRR write protected.\n");
+ break;
+ }
+ sci->brr = val;
+ update_trtime(sci);
+ break;
+ case A_SCR:
+ sci->scr = val;
+ if (FIELD_EX16(sci->scr, SCR, TE)) {
+ /* Transmitter enable */
+ if (IS_SCI(sci)) {
+ sci->Xsr = FIELD_DP16(sci->Xsr, SSR, TDRE, 1);
+ sci->Xsr = FIELD_DP16(sci->Xsr, SSR, TEND, 1);
+ } else {
+ sci->Xsr = FIELD_DP16(sci->Xsr, FSR, TEND, 1);
+ sci->Xsr = FIELD_DP16(sci->Xsr, FSR, TDFE, 1);
+ sci->tx_start_time = 0;
+ }
+ sci_irq(sci, TXI);
+ sci_irq(sci, TEI);
+ } else {
+ /* Transmitter disable */
+ update_event_time(sci, TXEND, 0);
+ update_event_time(sci, TXEMPTY, 0);
+ }
+ break;
+ case A_TDR:
+ if (IS_SCI(sci)) {
+ sci->tdr = val;
+ if (IS_SCIA(sci)) {
+ if (FIELD_EX16(sci->Xsr, SSR, TEND)) {
+ update_event_time(sci, TXEMPTY, sci->trtime);
+ sci_send_byte(sci);
+ } else {
+ sci->Xsr = FIELD_DP16(sci->Xsr, SSR, TDRE, 0);
+ }
+ sci_irq(sci, TXI);
+ sci_irq(sci, TEI);
+ }
+ } else {
+ if (sci->tx_start_time > 0) {
+ sci->tdcnt -= transmit_byte(sci);
+ } else {
+ sci->tx_start_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ }
+ if (sci->tdcnt >= SCIF_FIFO_DEPTH) {
+ break;
+ }
+ txd = val;
+ if (qemu_chr_fe_backend_connected(&sci->chr)) {
+ qemu_chr_fe_write_all(&sci->chr, &txd, 1);
+ }
+ if (FIELD_EX16(sci->fcr, FCR, LOOP) && can_receive(sci) > 0) {
+ /* Loopback mode */
+ sci_receive(sci, &txd, 1);
+ }
+ sci->tdcnt++;
+ sci->Xsr = FIELD_DP16(sci->Xsr, FSR, TEND, 0);
+ update_event_time(sci, TXEND, sci->tdcnt);
+ if (sci->tdcnt > txtrg) {
+ sci->Xsr = FIELD_DP16(sci->Xsr, FSR, TDFE, 0);
+ update_event_time(sci, TXEMPTY, sci->tdcnt - txtrg + 1);
+ sci_irq(sci, TXI);
+ }
+ }
+ break;
+ case A_FSR: /* A_SSR */
+ if (IS_SCI(sci)) {
+ /* Mask for read only bits */
+ ssr_mask = IS_SCIA(sci) ? 0xc7 : 0x07;
+ sci->Xsr = FIELD_DP16(sci->Xsr, SSR, MPBT,
+ FIELD_EX16(val, SSR, MPBT));
+ sci->Xsr &= (val | ssr_mask);
+ /* Clear ERI */
+ sci_irq(sci, ERI);
+ if (sci->feature == SCI_FEAT_SCI) {
+ tx_start = FIELD_EX16(sci->read_Xsr, SSR, TDRE) &&
+ !FIELD_EX16(sci->Xsr, SSR, TDRE) &&
+ (FIELD_EX16(sci->Xsr, SSR, ERR) == 0);
+ if (tx_start) {
+ sci_send_byte(sci);
+ update_event_time(sci, TXEMPTY, sci->trtime);
+ sci_irq(sci, TXI);
+ }
+ }
+ } else {
+ rxtrg = sci_rtrg[FIELD_EX16(sci->fcr, FCR, RTRG)];
+ ssr_mask = ~(sci->read_Xsr & 0xf3);
+ sci->tdcnt -= transmit_byte(sci);
+ if (sci->tdcnt < txtrg) {
+ ssr_mask = FIELD_DP16(ssr_mask, FSR, TDFE, 1);
+ }
+ if (fifo8_num_used(&sci->rxfifo) >= rxtrg) {
+ ssr_mask = FIELD_DP16(ssr_mask, FSR, RDF, 1);
+ }
+ sci->Xsr &= (val | ssr_mask);
+ sci_irq(sci, ERI);
+ sci_irq(sci, RXI);
+ sci_irq(sci, TXI);
+ }
+ break;
+ case A_RDR:
+ qemu_log_mask(LOG_GUEST_ERROR, "reneas_sci: RDR is read only.\n");
+ break;
+ case A_FCR: /* A_SCMR / A_SPTR */
+ if (IS_SCI(sci)) {
+ if (sci->feature == SCI_FEAT_SCI) {
+ sci->sptr = val;
+ } else {
+ sci->scmr = val;
+ }
+ } else {
+ sci->fcr = val;
+ if (FIELD_EX16(sci->fcr, FCR, RFRST)) {
+ fifo8_reset(&sci->rxfifo);
+ update_event_time(sci, RXTOUT, 0);
+ update_event_time(sci, RXNEXT, 0);
+ }
+ if (FIELD_EX16(sci->fcr, FCR, TFRST)) {
+ sci->tdcnt = 0;
+ }
+ }
+ break;
+ case A_FDR: /* A_SEMR */
+ if (IS_SCI(sci)) {
+ SCI_IS_NOT_SUPPORTED(sci, SEMR);
+ sci->semr = val;
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR, "reneas_sci: FDR is read only.\n");
+ }
+ break;
+ case A_SPTR:
+ if (IS_SCI(sci)) {
+ goto error;
+ } else {
+ sci->sptr = val;
+ }
+ break;
+ case A_LSR:
+ if (IS_SCI(sci)) {
+ goto error;
+ } else {
+ if (FIELD_EX16(sci->read_lsr, LSR, ORER) != 1) {
+ val = FIELD_DP16(val, LSR, ORER, 1);
+ }
+ sci->lsr &= val;
+ sci_irq(sci, ERI);
+ }
+ break;
+ default:
+ error:
+ qemu_log_mask(LOG_UNIMP, "renesas_sci: Register 0x%" HWADDR_PRIX
+ " not implemented\n", addr);
+ }
+}
+
+static uint64_t sci_read(void *opaque, hwaddr addr, unsigned size)
+{
+ RSCIState *sci = RSCI(opaque);
+ uint64_t ret;
+
+ switch (sci->regsize) {
+ case 8:
+ addr <<= 1; break;
+ case 32:
+ addr >>= 1; break;
+ }
+
+ switch (addr) {
+ case A_SMR:
+ return sci->smr;
+ case A_BRR:
+ return sci->brr;
+ case A_SCR:
+ return sci->scr;
+ case A_TDR:
+ if (IS_SCI(sci)) {
+ return sci->tdr;
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR, "reneas_sci: TDR is write only.\n");
+ return UINT64_MAX;
+ }
+ case A_FSR: /* A_SSR */
+ sci->read_Xsr = sci->Xsr;
+ return sci->Xsr;
+ case A_RDR:
+ ret = fifo8_pop(&sci->rxfifo);
+ if (IS_SCIA(sci)) {
+ sci->Xsr = FIELD_DP16(sci->Xsr, SSR, RDRF, 0);
+ }
+ return ret;
+ case A_FCR: /* A_SCMR / A_SPTR */
+ if (IS_SCI(sci)) {
+ if (IS_SCIA(sci)) {
+ return sci->scmr;
+ } else {
+ return sci->sptr;
+ }
+ } else {
+ return sci->fcr & 0x7ff;
+ }
+ case A_FDR: /* A_SEMR */
+ if (IS_SCI(sci)) {
+ SCI_IS_NOT_SUPPORTED(sci, SEMR);
+ return sci->semr;
+ } else {
+ ret = 0;
+ ret = FIELD_DP16(ret, FDR, Rn, fifo8_num_used(&sci->rxfifo));
+ ret = FIELD_DP16(ret, FDR, Tn, sci->tdcnt - transmit_byte(sci));
+ return ret;
+ }
+ case A_SPTR:
+ if (IS_SCI(sci)) {
+ goto error;
+ } else {
+ return sci->sptr;
+ }
+ case A_LSR:
+ if (IS_SCI(sci)) {
+ goto error;
+ } else {
+ sci->read_lsr = sci->lsr;
+ return sci->lsr;
+ }
+ default:
+ error:
+ qemu_log_mask(LOG_UNIMP, "renesas_sci: Register 0x%" HWADDR_PRIX
+ " not implemented.\n", addr);
+ }
+ return UINT64_MAX;
+}
+
+static const MemoryRegionOps sci_ops = {
+ .write = sci_write,
+ .read = sci_read,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ .max_access_size = 4,
+ },
+};
+
+static void sci_register_init(RSCIState *sci)
+{
+ int i;
+ sci->smr = sci->scr = 0x00;
+ sci->brr = 0xff;
+ if (IS_SCI(sci)) {
+ sci->tdr = 0xff;
+ sci->Xsr = 0x84;
+ sci->scmr = 0x00;
+ sci->semr = 0x00;
+ sci->sptr = 0x00;
+ } else {
+ sci->Xsr = 0x0060;
+ sci->fcr = 0x0000;
+ sci->sptr = 0x0000;
+ sci->lsr = 0x0000;
+ }
+ update_trtime(sci);
+ for (i = 0; i < NR_SCI_EVENT; i++) {
+ sci->event[i].time = 0;
+ }
+}
+
+static void sci_event(void *opaque, QEMUChrEvent event)
+{
+ RSCIState *sci = RSCI(opaque);
+ if (event == CHR_EVENT_BREAK) {
+ if (IS_SCI(sci)) {
+ sci->Xsr = FIELD_DP16(sci->Xsr, SSR, FER, 1);
+ } else {
+ sci->Xsr = FIELD_DP16(sci->Xsr, FSR, BRK, 1);
+ }
+ sci_irq(sci, ERI);
+ }
+}
+
+static void rsci_realize(DeviceState *dev, Error **errp)
+{
+ SysBusDevice *d = SYS_BUS_DEVICE(dev);
+ RSCIState *sci = RSCI(dev);
+ int i;
+ int size;
+
+ if (sci->input_freq == 0) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "renesas_sci: input-freq property must be set.");
+ return;
+ }
+ if (sci->regsize != 8 && sci->regsize != 16 && sci->regsize != 32) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "renesas_sci: Invalid regsize.");
+ return;
+ }
+
+ size = IS_SCI(sci) ? 16 : 20;
+ switch (sci->regsize) {
+ case 8:
+ size >>= 1;
+ break;
+ case 32:
+ size <<= 1;
+ break;
+ }
+ memory_region_init_io(&sci->memory, OBJECT(sci), &sci_ops,
+ sci, "renesas-sci", size);
+ sysbus_init_mmio(d, &sci->memory);
+ memory_region_init_alias(&sci->memory_p4, NULL, "renesas-sci-p4",
+ &sci->memory, 0, size);
+ sysbus_init_mmio(d, &sci->memory_p4);
+ memory_region_init_alias(&sci->memory_a7, NULL, "renesas-sci-a7",
+ &sci->memory, 0, size);
+ sysbus_init_mmio(d, &sci->memory_a7);
+
+ for (i = 0; i < SCI_NR_IRQ; i++) {
+ sysbus_init_irq(d, &sci->irq[i]);
+ }
+ sci->event_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sci_timer_event, sci);
+
+ qemu_chr_fe_set_handlers(&sci->chr, can_receive, sci_receive,
+ sci_event, NULL, sci, NULL, true);
+ fifo8_create(&sci->rxfifo, SCIF_FIFO_DEPTH);
+ sci_register_init(sci);
+}
+
+static const VMStateDescription vmstate_rsci = {
+ .name = "renesas-sci",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static Property rsci_properties[] = {
+ DEFINE_PROP_UINT64("input-freq", RSCIState, input_freq, 0),
+ DEFINE_PROP_INT32("register-size", RSCIState, regsize, 8),
+ DEFINE_PROP_INT32("feature", RSCIState, feature, 0),
+ DEFINE_PROP_CHR("chardev", RSCIState, chr),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void rsci_init(Object *obj)
+{
+ RSCIState *sci = RSCI(obj);
+ sci->event[RXTOUT].handler = sci_rx_timeout;
+ sci->event[RXNEXT].handler = sci_rx_next;
+ sci->event[TXEMPTY].handler = sci_tx_empty;
+ sci->event[TXEND].handler = sci_tx_end;
+}
+static void rsci_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = rsci_realize;
+ dc->vmsd = &vmstate_rsci;
+ device_class_set_props(dc, rsci_properties);
+}
+
+static const TypeInfo rsci_info = {
+ .name = TYPE_RENESAS_SCI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(RSCIState),
+ .instance_init = rsci_init,
+ .class_init = rsci_class_init,
+};
+
+static void rsci_register_types(void)
+{
+ type_register_static(&rsci_info);
+}
+
+type_init(rsci_register_types)
diff --git a/hw/char/Kconfig b/hw/char/Kconfig
index 40e7a8b8bb..874627520c 100644
--- a/hw/char/Kconfig
+++ b/hw/char/Kconfig
@@ -46,3 +46,6 @@ config SCLPCONSOLE
config TERMINAL3270
bool
+
+config RENESAS_SCI
+ bool
diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs
index 9e9a6c1aff..b07ce63c6f 100644
--- a/hw/char/Makefile.objs
+++ b/hw/char/Makefile.objs
@@ -16,7 +16,6 @@ common-obj-$(CONFIG_CADENCE) += cadence_uart.o
common-obj-$(CONFIG_EXYNOS4) += exynos4210_uart.o
common-obj-$(CONFIG_COLDFIRE) += mcf_uart.o
common-obj-$(CONFIG_OMAP) += omap_uart.o
-common-obj-$(CONFIG_SH4) += sh_serial.o
common-obj-$(CONFIG_DIGIC) += digic-uart.o
common-obj-$(CONFIG_STM32F2XX_USART) += stm32f2xx_usart.o
common-obj-$(CONFIG_RASPI) += bcm2835_aux.o
@@ -31,6 +30,8 @@ common-obj-$(CONFIG_LM32) += lm32_uart.o
common-obj-$(CONFIG_MILKYMIST) += milkymist-uart.o
common-obj-$(CONFIG_SCLPCONSOLE) += sclpconsole.o sclpconsole-lm.o
+common-obj-$(CONFIG_RENESAS_SCI) += renesas_sci.o
+
obj-$(CONFIG_VIRTIO) += virtio-serial-bus.o
obj-$(CONFIG_PSERIES) += spapr_vty.o
obj-$(CONFIG_TERMINAL3270) += terminal3270.o
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 04/10] hw/char: Renesas SCI module.
2020-05-31 16:24 ` [PATCH 04/10] hw/char: Renesas SCI module Yoshinori Sato
@ 2020-06-05 16:05 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-06-05 16:05 UTC (permalink / raw)
To: Yoshinori Sato, qemu-devel
On 5/31/20 6:24 PM, Yoshinori Sato wrote:
> This module supported SCI / SCIa / SCIF.
>
> Hardware manual.
> SCI / SCIF
> https://www.renesas.com/us/en/doc/products/mpumcu/001/r01uh0457ej0401_sh7751.pdf
> SCIa
> https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> ---
> include/hw/char/renesas_sci.h | 77 ++++
> hw/char/renesas_sci.c | 786 ++++++++++++++++++++++++++++++++++
> hw/char/Kconfig | 3 +
> hw/char/Makefile.objs | 3 +-
> 4 files changed, 868 insertions(+), 1 deletion(-)
> create mode 100644 include/hw/char/renesas_sci.h
> create mode 100644 hw/char/renesas_sci.c
>
> diff --git a/include/hw/char/renesas_sci.h b/include/hw/char/renesas_sci.h
> new file mode 100644
> index 0000000000..9152faff6c
> --- /dev/null
> +++ b/include/hw/char/renesas_sci.h
> @@ -0,0 +1,77 @@
> +/*
> + * Renesas Serial Communication Interface
> + *
> + * Copyright (c) 2020 Yoshinori Sato
> + *
> + * This code is licensed under the GPL version 2 or later.
> + *
> + */
> +
> +#include "chardev/char-fe.h"
> +#include "qemu/timer.h"
> +#include "qemu/fifo8.h"
> +#include "hw/sysbus.h"
> +
> +#define TYPE_RENESAS_SCI "renesas-sci"
> +#define RSCI(obj) OBJECT_CHECK(RSCIState, (obj), TYPE_RENESAS_SCI)
> +
> +enum {
> + ERI = 0,
> + RXI = 1,
> + TXI = 2,
> + TEI = 3,
> + BRI = 3,
So same interrupt number have different meaning for each model.
> + SCI_NR_IRQ = 4,
> +};
> +
> +enum {
> + SCI_FEAT_SCI = 0x00,
> + SCI_FEAT_SCIA = 0x01,
> + SCI_FEAT_SCIF = 0x10,
> +};
> +
> +enum {
> + RXTOUT,
> + RXNEXT,
> + TXEMPTY,
> + TXEND,
> + NR_SCI_EVENT,
> +};
> +
> +typedef struct RSCIState {
> + SysBusDevice parent_obj;
> + MemoryRegion memory;
> + MemoryRegion memory_p4;
> + MemoryRegion memory_a7;
> +
> + /* SCI register */
> + uint8_t smr;
> + uint8_t brr;
> + uint8_t scr;
> + uint8_t tdr;
> + uint16_t Xsr;
> + uint8_t scmr;
> + uint8_t semr;
> + uint16_t fcr;
> + uint16_t sptr;
> + uint16_t lsr;
> +
> + /* internal use */
> + uint16_t read_Xsr;
> + uint16_t read_lsr;
> + int64_t etu;
> + int64_t trtime;
> + int64_t tx_start_time;
> + int tdcnt;
> + int regsize;
> + struct {
> + int64_t time;
> + int64_t (*handler)(struct RSCIState *sci);
> + } event[NR_SCI_EVENT];
> + QEMUTimer *event_timer;
> + CharBackend chr;
> + uint64_t input_freq;
> + int feature;
> + qemu_irq irq[SCI_NR_IRQ];
> + Fifo8 rxfifo;
> +} RSCIState;
> diff --git a/hw/char/renesas_sci.c b/hw/char/renesas_sci.c
> new file mode 100644
> index 0000000000..6b23055a40
> --- /dev/null
> +++ b/hw/char/renesas_sci.c
> @@ -0,0 +1,786 @@
> +/*
> + * Renesas Serial Communication Interface (SCI / SCIa / SCIF)
> + *
> + * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware
> + * (Rev.1.40 R01UH0033EJ0140)
> + * And SH7751 Group, SH7751R Group User's Manual: Hardware
> + * (Rev.4.01 R01UH0457EJ0401)
> + *
> + * Copyright (c) 2020 Yoshinori Sato
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "qapi/error.h"
> +#include "qemu-common.h"
> +#include "hw/hw.h"
> +#include "hw/irq.h"
> +#include "hw/sysbus.h"
> +#include "hw/registerfields.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/char/renesas_sci.h"
> +#include "migration/vmstate.h"
> +#include "qemu/error-report.h"
> +
> +/* SCI register map */
> +REG8(SMR, 0)
> + FIELD(SMR, CKS, 0, 2)
> + FIELD(SMR, MP, 2, 1)
> + FIELD(SMR, STOP, 3, 1)
> + FIELD(SMR, PM, 4, 1)
> + FIELD(SMR, PE, 5, 1)
> + FIELD(SMR, CHR, 6, 1)
> + FIELD(SMR, CM, 7, 1)
> +REG16(BRR, 2)
> +REG16(SCR, 4)
> + FIELD(SCR, CKE, 0, 2)
> + FIELD(SCR, TEIE, 2, 1)
> + FIELD(SCR, MPIE, 3, 1)
> + FIELD(SCR, REIE, 3, 1)
> + FIELD(SCR, RE, 4, 1)
> + FIELD(SCR, TE, 5, 1)
> + FIELD(SCR, RIE, 6, 1)
> + FIELD(SCR, TIE, 7, 1)
> +REG16(TDR, 6)
> +REG16(SSR, 8)
> + FIELD(SSR, MPBT, 0, 1)
> + FIELD(SSR, MPB, 1, 1)
> + FIELD(SSR, TEND, 2, 1)
> + FIELD(SSR, ERR, 3, 3)
> + FIELD(SSR, PER, 3, 1)
> + FIELD(SSR, FER, 4, 1)
> + FIELD(SSR, ORER, 5, 1)
> + FIELD(SSR, RDRF, 6, 1)
> + FIELD(SSR, TDRE, 7, 1)
> +REG16(FSR, 8)
> + FIELD(FSR, DR, 0, 1)
> + FIELD(FSR, RDF, 1, 1)
> + FIELD(FSR, RDF_DR, 0, 2)
> + FIELD(FSR, PER, 2, 1)
> + FIELD(FSR, FER, 3, 1)
> + FIELD(FSR, BRK, 4, 1)
> + FIELD(FSR, TDFE, 5, 1)
> + FIELD(FSR, TEND, 6, 1)
> + FIELD(FSR, ER, 7, 1)
> + FIELD(FSR, FERn, 8, 4)
> + FIELD(FSR, PERn, 12, 4)
> +REG16(RDR, 10)
> +REG16(SCMR, 12)
> + FIELD(SCMR, SMIF, 0, 1)
> + FIELD(SCMR, SINV, 2, 1)
> + FIELD(SCMR, SDIR, 3, 1)
> + FIELD(SCMR, BCP2, 7, 1)
> +REG16(FCR, 12)
> + FIELD(FCR, LOOP, 0, 1)
> + FIELD(FCR, RFRST, 1, 1)
> + FIELD(FCR, TFRST, 2, 1)
> + FIELD(FCR, MCE, 3, 1)
> + FIELD(FCR, TTRG, 4, 2)
> + FIELD(FCR, RTRG, 6, 2)
> + FIELD(FCR, RSTRG, 8, 3)
> +REG16(SEMR, 14)
> + FIELD(SEMR, ACS0, 0, 1)
> + FIELD(SEMR, ABCS, 4, 1)
> +REG16(FDR, 14)
> + FIELD(FDR, Rn, 0, 4)
> + FIELD(FDR, Tn, 8, 4)
> +REG16(SPTR, 16)
> + FIELD(SPTR, SPB2DT, 0, 1)
> + FIELD(SPTR, SPB2IO, 1, 1)
> + FIELD(SPTR, SCKDT, 2, 1)
> + FIELD(SPTR, SCKIO, 3, 1)
> + FIELD(SPTR, CTSDT, 4, 1)
> + FIELD(SPTR, CTSIO, 5, 1)
> + FIELD(SPTR, RTSDT, 6, 1)
> + FIELD(SPTR, RTSIO, 7, 1)
> + FIELD(SPTR, EIO, 7, 1)
> +REG16(LSR, 18)
> + FIELD(LSR, ORER, 0, 1)
> +
> +#define SCIF_FIFO_DEPTH 16
> +#define IS_SCI(sci) (sci->feature < SCI_FEAT_SCIF)
> +#define IS_SCIA(sci) (IS_SCI(sci) && sci->feature >= SCI_FEAT_SCIA)
> +#define IS_SCIF(sci) (!IS_SCI(sci))
> +
> +static const int sci_rtrg[] = {1, 4, 8, 14};
> +
> +static void update_event_time(RSCIState *sci, int evt, int64_t t)
> +{
> + if (t > 0) {
> + t += qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
> + sci->event[evt].time = t;
> + if (timer_expire_time_ns(sci->event_timer) > t) {
> + timer_mod(sci->event_timer, t);
> + }
> + } else {
> + sci->event[evt].time = 0;
> + }
> +}
> +
> +static int sci_is_rxi(RSCIState *sci)
> +{
> + int eio;
> + int enable;
> + enable = FIELD_EX16(sci->scr, SCR, RIE);
> + if (IS_SCI(sci)) {
> + eio = (sci->feature != SCI_FEAT_SCI) ||
> + (FIELD_EX16(sci->sptr, SPTR, EIO) == 0);
> + return FIELD_EX16(sci->Xsr, SSR, RDRF) && enable && eio;
> + } else {
> + return (FIELD_EX16(sci->Xsr, FSR, RDF_DR) != 0) && enable;
> + }
> +}
> +
> +static int sci_is_txi(RSCIState *sci)
> +{
> + int enable = FIELD_EX16(sci->scr, SCR, TIE);
> + if (IS_SCI(sci)) {
> + return enable && FIELD_EX16(sci->Xsr, SSR, TDRE);
> + } else {
> + return enable && FIELD_EX16(sci->Xsr, FSR, TDFE);
> + }
> +}
> +
> +static void sci_irq(RSCIState *sci, int req)
> +{
> + int br;
> + int irq;
> + int rie;
> +
> + switch (req) {
> + case ERI:
> + rie = FIELD_EX16(sci->scr, SCR, RIE);
> + if (IS_SCI(sci)) {
> + irq = rie && (FIELD_EX16(sci->Xsr, SSR, ERR) != 0);
> + } else {
> + irq = (rie || FIELD_EX16(sci->scr, SCR, REIE)) &&
> + FIELD_EX16(sci->Xsr, FSR, ER);
> + }
> + qemu_set_irq(sci->irq[ERI], irq);
> + break;
> + case RXI:
> + if (IS_SCIA(sci)) {
> + if (sci_is_rxi(sci)) {
> + qemu_irq_pulse(sci->irq[RXI]);
> + }
> + } else {
> + qemu_set_irq(sci->irq[RXI], sci_is_rxi(sci));
> + }
> + break;
> + case TXI:
> + if (IS_SCIA(sci)) {
> + if (sci_is_txi(sci)) {
> + qemu_irq_pulse(sci->irq[TXI]);
> + }
> + } else {
> + qemu_set_irq(sci->irq[TXI], sci_is_txi(sci));
> + }
> + break;
> + case BRI: /* TEI */
> + if (IS_SCI(sci)) {
> + qemu_set_irq(sci->irq[TEI],
> + FIELD_EX16(sci->Xsr, SSR, TEND) &&
> + FIELD_EX16(sci->scr, SCR, TEIE));
> + } else {
> + rie = FIELD_EX16(sci->scr, SCR, RIE);
> + br = (rie || FIELD_EX16(sci->scr, SCR, REIE)) &&
> + FIELD_EX16(sci->Xsr, FSR, BRK);
> + qemu_set_irq(sci->irq[BRI], br);
> + }
> + break;
> + }
> +}
> +
> +static int can_receive(void *opaque)
> +{
> + RSCIState *sci = RSCI(opaque);
> + int fifo_free = 0;
> + if (FIELD_EX16(sci->scr, SCR, RE)) {
> + /* Receiver enabled */
> + fifo_free = fifo8_num_free(&sci->rxfifo);
> + if (IS_SCIF(sci) && fifo_free == 0) {
> + /* FIFO overrun */
> + sci->lsr = FIELD_DP16(sci->lsr, LSR, ORER, 1);
> + sci_irq(sci, ERI);
> + }
> + }
> + return fifo_free;
> +}
> +
> +static void sci_receive(void *opaque, const uint8_t *buf, int size)
> +{
> + RSCIState *sci = RSCI(opaque);
> + int rtrg;
> +
> + fifo8_push_all(&sci->rxfifo, buf, size);
> + if (sci->event[RXNEXT].time == 0) {
> + if (IS_SCI(sci)) {
> + sci->Xsr = FIELD_DP16(sci->Xsr, SSR, RDRF, 1);
> + update_event_time(sci, RXNEXT, sci->trtime);
> + } else {
> + rtrg = sci_rtrg[FIELD_EX16(sci->fcr, FCR, RTRG)];
> + if (fifo8_num_used(&sci->rxfifo) >= rtrg) {
> + sci->Xsr = FIELD_DP16(sci->Xsr, FSR, RDF, 1);
> + } else {
> + update_event_time(sci, RXTOUT, 15 * sci->etu);
> + }
> + }
> + sci_irq(sci, RXI);
> + }
> +}
> +
> +static void sci_send_byte(RSCIState *sci)
> +{
> + if (IS_SCI(sci)) {
> + if (qemu_chr_fe_backend_connected(&sci->chr)) {
> + qemu_chr_fe_write_all(&sci->chr, &sci->tdr, 1);
> + }
> + sci->Xsr = FIELD_DP16(sci->Xsr, SSR, TEND, 0);
> + sci->Xsr = FIELD_DP16(sci->Xsr, SSR, TDRE, 1);
> + }
> +}
> +
> +static int transmit_byte(RSCIState *sci)
> +{
> + int64_t elapsed;
> + int byte = 0;
> + if (sci->tx_start_time > 0) {
> + elapsed = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - sci->tx_start_time;
> + byte = elapsed / sci->trtime;
> + if (byte > sci->tdcnt) {
> + byte = sci->tdcnt;
> + }
> + }
> + return byte;
> +}
> +
> +static int64_t sci_rx_timeout(RSCIState *sci)
> +{
> + if (IS_SCIF(sci)) {
> + sci->Xsr = FIELD_DP16(sci->Xsr, FSR, DR, 1);
> + sci_irq(sci, RXI);
> + }
> + return 0;
> +}
> +
> +static int64_t sci_rx_next(RSCIState *sci)
> +{
> + int64_t next_event = 0;
> + if (IS_SCI(sci) && !fifo8_is_empty(&sci->rxfifo)) {
> + if (FIELD_EX16(sci->Xsr, SSR, RDRF)) {
> + /* Receiver overrun */
> + sci->Xsr = FIELD_DP16(sci->Xsr, SSR, ORER, 1);
> + sci_irq(sci, ERI);
> + } else {
> + /* Trigger next event */
> + sci->Xsr = FIELD_DP16(sci->Xsr, SSR, RDRF, 1);
> + sci_irq(sci, RXI);
> + next_event = sci->trtime;
> + }
> + }
> + return next_event;
> +}
> +
> +static int64_t sci_tx_empty(RSCIState *sci)
> +{
> + int64_t ret = 0;
> + if (IS_SCI(sci)) {
> + if (!FIELD_EX16(sci->Xsr, SSR, TDRE)) {
> + sci_send_byte(sci);
> + ret = sci->trtime;
> + sci_irq(sci, TXI);
> + } else {
> + sci->Xsr = FIELD_DP16(sci->Xsr, SSR, TEND, 1);
> + sci_irq(sci, TEI);
> + }
> + } else {
> + sci->tdcnt -= transmit_byte(sci);
> + sci->Xsr = FIELD_DP16(sci->Xsr, FSR, TDFE, 1);
> + sci_irq(sci, TXI);
> + }
> + return ret;
> +}
> +
> +static int64_t sci_tx_end(RSCIState *sci)
> +{
> + if (IS_SCIF(sci)) {
> + sci->tdcnt = 0;
> + sci->Xsr = FIELD_DP16(sci->Xsr, FSR, TEND, 1);
> + sci_irq(sci, TEI);
> + }
> + return 0;
> +}
> +
> +static void sci_timer_event(void *opaque)
> +{
> + RSCIState *sci = RSCI(opaque);
> + int64_t now, next, t;
> + int i;
> +
> + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
> + next = INT64_MAX;
> + for (i = 0; i < NR_SCI_EVENT; i++) {
> + if (sci->event[i].time > 0 && sci->event[i].time <= now) {
> + t = sci->event[i].handler(sci);
> + sci->event[i].time = (t > 0) ? now + t : 0;
> + }
> + if (sci->event[i].time > 0) {
> + next = MIN(next, sci->event[i].time);
> + }
> + }
> + if (next < INT64_MAX) {
> + timer_mod(sci->event_timer, next);
> + } else {
> + timer_del(sci->event_timer);
> + }
> +}
> +
> +static void update_trtime(RSCIState *sci)
> +{
> + int divrate;
> + if (IS_SCIA(sci)) {
> + divrate = 16 * (2 - FIELD_EX8(sci->semr, SEMR, ABCS));
> + } else {
> + divrate = 32;
> + }
> +
> + /* x bit transmit time (divrate * brr) / base freq */
> + sci->etu = divrate * 1 << (2 * FIELD_EX16(sci->smr, SMR, CKS));
> + sci->etu *= sci->brr + 1;
> + sci->etu *= NANOSECONDS_PER_SECOND;
> + sci->etu /= sci->input_freq;
> +
> + /* char per bits */
> + sci->trtime = 8 - FIELD_EX16(sci->smr, SMR, CHR);
> + sci->trtime += FIELD_EX16(sci->smr, SMR, PE);
> + sci->trtime += FIELD_EX16(sci->smr, SMR, STOP) + 1 + 1;
> + sci->trtime *= sci->etu;
> +}
> +
> +#define IS_TR_ENABLED(scr) \
> + (FIELD_EX16(scr, SCR, TE) || FIELD_EX16(scr, SCR, RE))
> +
> +#define SCI_IS_NOT_SUPPORTED(sci, name) \
> + if (sci->feature == SCI_FEAT_SCI) { \
> + qemu_log_mask(LOG_GUEST_ERROR, \
> + "reneas_sci: " #name " is not supported.\n"); \
> + }
> +
> +static void sci_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
> +{
> + RSCIState *sci = RSCI(opaque);
> + int txtrg;
> + int rxtrg;
> + uint8_t txd;
> + uint16_t ssr_mask;
> + bool tx_start = false;
> +
> + if (IS_SCI(sci)) {
> + txtrg = 1;
> + } else {
> + txtrg = 1 << (3 - FIELD_EX16(sci->fcr, FCR, TTRG));
> + }
> + switch (sci->regsize) {
> + case 8:
> + addr <<= 1; break;
> + case 32:
> + addr >>= 1; break;
This should be handled by sci_ops.impl, such:
static const MemoryRegionOps sci_ops = {
.impl = {
.min_access_size = 2,
.max_access_size = 2,
},
.valid = {
.min_access_size = 1,
.max_access_size = 4,
},
...
Then access_with_adjusted_size() will automagically do the conversion
for you.
> + }
> + switch (addr) {
> + case A_SMR:
> + if (IS_SCIA(sci) && IS_TR_ENABLED(sci->scr)) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "reneas_sci: SMR write protected.\n");
> + break;
> + }
> + sci->smr = val;
> + update_trtime(sci);
> + break;
> + case A_BRR:
> + if (IS_SCIA(sci) && IS_TR_ENABLED(sci->scr)) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "reneas_sci: BRR write protected.\n");
> + break;
> + }
> + sci->brr = val;
> + update_trtime(sci);
> + break;
> + case A_SCR:
> + sci->scr = val;
> + if (FIELD_EX16(sci->scr, SCR, TE)) {
> + /* Transmitter enable */
> + if (IS_SCI(sci)) {
> + sci->Xsr = FIELD_DP16(sci->Xsr, SSR, TDRE, 1);
> + sci->Xsr = FIELD_DP16(sci->Xsr, SSR, TEND, 1);
> + } else {
> + sci->Xsr = FIELD_DP16(sci->Xsr, FSR, TEND, 1);
> + sci->Xsr = FIELD_DP16(sci->Xsr, FSR, TDFE, 1);
> + sci->tx_start_time = 0;
> + }
> + sci_irq(sci, TXI);
> + sci_irq(sci, TEI);
> + } else {
> + /* Transmitter disable */
> + update_event_time(sci, TXEND, 0);
> + update_event_time(sci, TXEMPTY, 0);
> + }
> + break;
> + case A_TDR:
> + if (IS_SCI(sci)) {
> + sci->tdr = val;
> + if (IS_SCIA(sci)) {
> + if (FIELD_EX16(sci->Xsr, SSR, TEND)) {
> + update_event_time(sci, TXEMPTY, sci->trtime);
> + sci_send_byte(sci);
> + } else {
> + sci->Xsr = FIELD_DP16(sci->Xsr, SSR, TDRE, 0);
> + }
> + sci_irq(sci, TXI);
> + sci_irq(sci, TEI);
> + }
> + } else {
> + if (sci->tx_start_time > 0) {
> + sci->tdcnt -= transmit_byte(sci);
> + } else {
> + sci->tx_start_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
> + }
> + if (sci->tdcnt >= SCIF_FIFO_DEPTH) {
> + break;
> + }
> + txd = val;
> + if (qemu_chr_fe_backend_connected(&sci->chr)) {
> + qemu_chr_fe_write_all(&sci->chr, &txd, 1);
> + }
> + if (FIELD_EX16(sci->fcr, FCR, LOOP) && can_receive(sci) > 0) {
> + /* Loopback mode */
> + sci_receive(sci, &txd, 1);
> + }
> + sci->tdcnt++;
> + sci->Xsr = FIELD_DP16(sci->Xsr, FSR, TEND, 0);
> + update_event_time(sci, TXEND, sci->tdcnt);
> + if (sci->tdcnt > txtrg) {
> + sci->Xsr = FIELD_DP16(sci->Xsr, FSR, TDFE, 0);
> + update_event_time(sci, TXEMPTY, sci->tdcnt - txtrg + 1);
> + sci_irq(sci, TXI);
> + }
> + }
> + break;
> + case A_FSR: /* A_SSR */
> + if (IS_SCI(sci)) {
> + /* Mask for read only bits */
> + ssr_mask = IS_SCIA(sci) ? 0xc7 : 0x07;
> + sci->Xsr = FIELD_DP16(sci->Xsr, SSR, MPBT,
> + FIELD_EX16(val, SSR, MPBT));
> + sci->Xsr &= (val | ssr_mask);
> + /* Clear ERI */
> + sci_irq(sci, ERI);
> + if (sci->feature == SCI_FEAT_SCI) {
> + tx_start = FIELD_EX16(sci->read_Xsr, SSR, TDRE) &&
> + !FIELD_EX16(sci->Xsr, SSR, TDRE) &&
> + (FIELD_EX16(sci->Xsr, SSR, ERR) == 0);
> + if (tx_start) {
> + sci_send_byte(sci);
> + update_event_time(sci, TXEMPTY, sci->trtime);
> + sci_irq(sci, TXI);
> + }
> + }
> + } else {
> + rxtrg = sci_rtrg[FIELD_EX16(sci->fcr, FCR, RTRG)];
> + ssr_mask = ~(sci->read_Xsr & 0xf3);
> + sci->tdcnt -= transmit_byte(sci);
> + if (sci->tdcnt < txtrg) {
> + ssr_mask = FIELD_DP16(ssr_mask, FSR, TDFE, 1);
> + }
> + if (fifo8_num_used(&sci->rxfifo) >= rxtrg) {
> + ssr_mask = FIELD_DP16(ssr_mask, FSR, RDF, 1);
> + }
> + sci->Xsr &= (val | ssr_mask);
> + sci_irq(sci, ERI);
> + sci_irq(sci, RXI);
> + sci_irq(sci, TXI);
> + }
> + break;
> + case A_RDR:
> + qemu_log_mask(LOG_GUEST_ERROR, "reneas_sci: RDR is read only.\n");
> + break;
> + case A_FCR: /* A_SCMR / A_SPTR */
> + if (IS_SCI(sci)) {
> + if (sci->feature == SCI_FEAT_SCI) {
> + sci->sptr = val;
> + } else {
> + sci->scmr = val;
> + }
> + } else {
> + sci->fcr = val;
> + if (FIELD_EX16(sci->fcr, FCR, RFRST)) {
> + fifo8_reset(&sci->rxfifo);
> + update_event_time(sci, RXTOUT, 0);
> + update_event_time(sci, RXNEXT, 0);
> + }
> + if (FIELD_EX16(sci->fcr, FCR, TFRST)) {
> + sci->tdcnt = 0;
> + }
> + }
> + break;
> + case A_FDR: /* A_SEMR */
> + if (IS_SCI(sci)) {
> + SCI_IS_NOT_SUPPORTED(sci, SEMR);
> + sci->semr = val;
> + } else {
> + qemu_log_mask(LOG_GUEST_ERROR, "reneas_sci: FDR is read only.\n");
> + }
> + break;
> + case A_SPTR:
> + if (IS_SCI(sci)) {
> + goto error;
> + } else {
> + sci->sptr = val;
> + }
> + break;
> + case A_LSR:
> + if (IS_SCI(sci)) {
> + goto error;
> + } else {
> + if (FIELD_EX16(sci->read_lsr, LSR, ORER) != 1) {
> + val = FIELD_DP16(val, LSR, ORER, 1);
> + }
> + sci->lsr &= val;
> + sci_irq(sci, ERI);
> + }
> + break;
> + default:
> + error:
> + qemu_log_mask(LOG_UNIMP, "renesas_sci: Register 0x%" HWADDR_PRIX
> + " not implemented\n", addr);
> + }
> +}
> +
> +static uint64_t sci_read(void *opaque, hwaddr addr, unsigned size)
> +{
> + RSCIState *sci = RSCI(opaque);
> + uint64_t ret;
> +
> + switch (sci->regsize) {
> + case 8:
> + addr <<= 1; break;
> + case 32:
> + addr >>= 1; break;
> + }
> +
> + switch (addr) {
> + case A_SMR:
> + return sci->smr;
> + case A_BRR:
> + return sci->brr;
> + case A_SCR:
> + return sci->scr;
> + case A_TDR:
> + if (IS_SCI(sci)) {
> + return sci->tdr;
> + } else {
> + qemu_log_mask(LOG_GUEST_ERROR, "reneas_sci: TDR is write only.\n");
> + return UINT64_MAX;
> + }
> + case A_FSR: /* A_SSR */
> + sci->read_Xsr = sci->Xsr;
> + return sci->Xsr;
> + case A_RDR:
> + ret = fifo8_pop(&sci->rxfifo);
> + if (IS_SCIA(sci)) {
> + sci->Xsr = FIELD_DP16(sci->Xsr, SSR, RDRF, 0);
> + }
> + return ret;
> + case A_FCR: /* A_SCMR / A_SPTR */
> + if (IS_SCI(sci)) {
> + if (IS_SCIA(sci)) {
> + return sci->scmr;
> + } else {
> + return sci->sptr;
> + }
> + } else {
> + return sci->fcr & 0x7ff;
> + }
> + case A_FDR: /* A_SEMR */
> + if (IS_SCI(sci)) {
> + SCI_IS_NOT_SUPPORTED(sci, SEMR);
> + return sci->semr;
> + } else {
> + ret = 0;
> + ret = FIELD_DP16(ret, FDR, Rn, fifo8_num_used(&sci->rxfifo));
> + ret = FIELD_DP16(ret, FDR, Tn, sci->tdcnt - transmit_byte(sci));
> + return ret;
> + }
> + case A_SPTR:
> + if (IS_SCI(sci)) {
> + goto error;
> + } else {
> + return sci->sptr;
> + }
> + case A_LSR:
> + if (IS_SCI(sci)) {
> + goto error;
> + } else {
> + sci->read_lsr = sci->lsr;
> + return sci->lsr;
> + }
> + default:
> + error:
> + qemu_log_mask(LOG_UNIMP, "renesas_sci: Register 0x%" HWADDR_PRIX
> + " not implemented.\n", addr);
> + }
> + return UINT64_MAX;
> +}
> +
> +static const MemoryRegionOps sci_ops = {
> + .write = sci_write,
> + .read = sci_read,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> + .impl = {
> + .max_access_size = 4,
> + },
> +};
> +
> +static void sci_register_init(RSCIState *sci)
> +{
> + int i;
> + sci->smr = sci->scr = 0x00;
> + sci->brr = 0xff;
> + if (IS_SCI(sci)) {
> + sci->tdr = 0xff;
> + sci->Xsr = 0x84;
> + sci->scmr = 0x00;
> + sci->semr = 0x00;
> + sci->sptr = 0x00;
> + } else {
> + sci->Xsr = 0x0060;
> + sci->fcr = 0x0000;
> + sci->sptr = 0x0000;
> + sci->lsr = 0x0000;
> + }
> + update_trtime(sci);
> + for (i = 0; i < NR_SCI_EVENT; i++) {
> + sci->event[i].time = 0;
> + }
> +}
> +
> +static void sci_event(void *opaque, QEMUChrEvent event)
> +{
> + RSCIState *sci = RSCI(opaque);
> + if (event == CHR_EVENT_BREAK) {
> + if (IS_SCI(sci)) {
> + sci->Xsr = FIELD_DP16(sci->Xsr, SSR, FER, 1);
> + } else {
> + sci->Xsr = FIELD_DP16(sci->Xsr, FSR, BRK, 1);
> + }
> + sci_irq(sci, ERI);
> + }
> +}
> +
> +static void rsci_realize(DeviceState *dev, Error **errp)
> +{
> + SysBusDevice *d = SYS_BUS_DEVICE(dev);
> + RSCIState *sci = RSCI(dev);
> + int i;
> + int size;
> +
> + if (sci->input_freq == 0) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "renesas_sci: input-freq property must be set.");
> + return;
> + }
> + if (sci->regsize != 8 && sci->regsize != 16 && sci->regsize != 32) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "renesas_sci: Invalid regsize.");
> + return;
> + }
> +
> + size = IS_SCI(sci) ? 16 : 20;
> + switch (sci->regsize) {
> + case 8:
> + size >>= 1;
> + break;
> + case 32:
> + size <<= 1;
> + break;
> + }
> + memory_region_init_io(&sci->memory, OBJECT(sci), &sci_ops,
> + sci, "renesas-sci", size);
> + sysbus_init_mmio(d, &sci->memory);
> + memory_region_init_alias(&sci->memory_p4, NULL, "renesas-sci-p4",
> + &sci->memory, 0, size);
> + sysbus_init_mmio(d, &sci->memory_p4);
> + memory_region_init_alias(&sci->memory_a7, NULL, "renesas-sci-a7",
> + &sci->memory, 0, size);
> + sysbus_init_mmio(d, &sci->memory_a7);
> +
> + for (i = 0; i < SCI_NR_IRQ; i++) {
> + sysbus_init_irq(d, &sci->irq[i]);
> + }
> + sci->event_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sci_timer_event, sci);
> +
> + qemu_chr_fe_set_handlers(&sci->chr, can_receive, sci_receive,
> + sci_event, NULL, sci, NULL, true);
> + fifo8_create(&sci->rxfifo, SCIF_FIFO_DEPTH);
> + sci_register_init(sci);
> +}
> +
> +static const VMStateDescription vmstate_rsci = {
> + .name = "renesas-sci",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static Property rsci_properties[] = {
> + DEFINE_PROP_UINT64("input-freq", RSCIState, input_freq, 0),
> + DEFINE_PROP_INT32("register-size", RSCIState, regsize, 8),
> + DEFINE_PROP_INT32("feature", RSCIState, feature, 0),
> + DEFINE_PROP_CHR("chardev", RSCIState, chr),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void rsci_init(Object *obj)
> +{
> + RSCIState *sci = RSCI(obj);
> + sci->event[RXTOUT].handler = sci_rx_timeout;
> + sci->event[RXNEXT].handler = sci_rx_next;
> + sci->event[TXEMPTY].handler = sci_tx_empty;
> + sci->event[TXEND].handler = sci_tx_end;
> +}
> +static void rsci_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->realize = rsci_realize;
> + dc->vmsd = &vmstate_rsci;
> + device_class_set_props(dc, rsci_properties);
> +}
> +
> +static const TypeInfo rsci_info = {
> + .name = TYPE_RENESAS_SCI,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(RSCIState),
> + .instance_init = rsci_init,
> + .class_init = rsci_class_init,
> +};
> +
> +static void rsci_register_types(void)
> +{
> + type_register_static(&rsci_info);
I'd rather register a type for each SCI / SCIa / SCIF models.
TYPE_RENESAS_SCI_COMMON the abstract base,
then i.e. TYPE_RENESAS_SCI_A only implements a SCIa with its register
mapped at correct addresses, no need to use 'if IS_SCI()' all over the
place.
I need more time to review.
> +}
> +
> +type_init(rsci_register_types)
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 05/10] hw/rx: RX MCU and target
2020-05-31 16:24 [PATCH 00/10] Add RX hardware emulation Yoshinori Sato
` (3 preceding siblings ...)
2020-05-31 16:24 ` [PATCH 04/10] hw/char: Renesas SCI module Yoshinori Sato
@ 2020-05-31 16:24 ` Yoshinori Sato
2020-06-05 16:09 ` Philippe Mathieu-Daudé
2020-05-31 16:24 ` [PATCH 06/10] Add rx-softmmu Yoshinori Sato
` (5 subsequent siblings)
10 siblings, 1 reply; 17+ messages in thread
From: Yoshinori Sato @ 2020-05-31 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: Yoshinori Sato
rx62n - RX62N MCU.
rx-virt - RX QEMU virtual target.
This has the same specifications as the gdb simulator.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
include/hw/rx/rx.h | 7 ++
include/hw/rx/rx62n.h | 91 ++++++++++++++++
hw/rx/rx-virt.c | 143 +++++++++++++++++++++++++
hw/rx/rx62n.c | 240 ++++++++++++++++++++++++++++++++++++++++++
hw/rx/Kconfig | 13 +++
hw/rx/Makefile.objs | 2 +
6 files changed, 496 insertions(+)
create mode 100644 include/hw/rx/rx.h
create mode 100644 include/hw/rx/rx62n.h
create mode 100644 hw/rx/rx-virt.c
create mode 100644 hw/rx/rx62n.c
create mode 100644 hw/rx/Kconfig
create mode 100644 hw/rx/Makefile.objs
diff --git a/include/hw/rx/rx.h b/include/hw/rx/rx.h
new file mode 100644
index 0000000000..ff5924b81f
--- /dev/null
+++ b/include/hw/rx/rx.h
@@ -0,0 +1,7 @@
+#ifndef QEMU_RX_H
+#define QEMU_RX_H
+/* Definitions for RX board emulation. */
+
+#include "target/rx/cpu-qom.h"
+
+#endif
diff --git a/include/hw/rx/rx62n.h b/include/hw/rx/rx62n.h
new file mode 100644
index 0000000000..11176eadf3
--- /dev/null
+++ b/include/hw/rx/rx62n.h
@@ -0,0 +1,91 @@
+/*
+ * RX62N MCU Object
+ *
+ * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware
+ * (Rev.1.40 R01UH0033EJ0140)
+ *
+ * Copyright (c) 2019 Yoshinori Sato
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_RX_RX62N_H
+#define HW_RX_RX62N_H
+
+#include "hw/sysbus.h"
+#include "hw/intc/rx_icu.h"
+#include "hw/timer/renesas_8timer.h"
+#include "hw/timer/renesas_timer.h"
+#include "hw/char/renesas_sci.h"
+#include "target/rx/cpu.h"
+#include "qemu/units.h"
+
+#define TYPE_RX62N "rx62n"
+#define RX62N(obj) OBJECT_CHECK(RX62NState, (obj), TYPE_RX62N)
+
+#define RX62N_NR_TMR 2
+#define RX62N_NR_CMT 2
+#define RX62N_NR_SCI 6
+
+typedef struct RX62NState {
+ SysBusDevice parent_obj;
+
+ RXCPU cpu;
+ RXICUState icu;
+ RTMRState tmr[RX62N_NR_TMR];
+ RTIMERState cmt[RX62N_NR_CMT];
+ RSCIState sci[RX62N_NR_SCI];
+
+ MemoryRegion *sysmem;
+ bool kernel;
+
+ MemoryRegion iram;
+ MemoryRegion iomem1;
+ MemoryRegion d_flash;
+ MemoryRegion iomem2;
+ MemoryRegion iomem3;
+ MemoryRegion c_flash;
+ qemu_irq irq[NR_IRQS];
+} RX62NState;
+
+/*
+ * RX62N Peripheral Address
+ * See users manual section 5
+ */
+#define RX62N_ICUBASE 0x00087000
+#define RX62N_TMRBASE 0x00088200
+#define RX62N_CMTBASE 0x00088000
+#define RX62N_SCIBASE 0x00088240
+
+/*
+ * RX62N Peripheral IRQ
+ * See users manual section 11
+ */
+#define RX62N_TMR_IRQBASE 174
+#define RX62N_CMT_IRQBASE 28
+#define RX62N_SCI_IRQBASE 214
+
+/*
+ * RX62N Internal Memory
+ * It is the value of R5F562N8.
+ * Please change the size for R5F562N7.
+ */
+#define RX62N_IRAM_BASE 0x00000000
+#define RX62N_IRAM_SIZE (96 * KiB)
+#define RX62N_DFLASH_BASE 0x00100000
+#define RX62N_DFLASH_SIZE (32 * KiB)
+#define RX62N_CFLASH_BASE 0xfff80000
+#define RX62N_CFLASH_SIZE (512 * KiB)
+
+#define RX62N_PCLK (48 * 1000 * 1000)
+#endif
diff --git a/hw/rx/rx-virt.c b/hw/rx/rx-virt.c
new file mode 100644
index 0000000000..3168a85b83
--- /dev/null
+++ b/hw/rx/rx-virt.c
@@ -0,0 +1,143 @@
+/*
+ * RX QEMU virtual platform
+ *
+ * Copyright (c) 2019 Yoshinori Sato
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "cpu.h"
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "hw/loader.h"
+#include "hw/rx/rx62n.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/qtest.h"
+#include "sysemu/device_tree.h"
+#include "hw/boards.h"
+
+/* Same address of GDB integrated simulator */
+#define SDRAM_BASE 0x01000000
+
+static void rx_load_image(RXCPU *cpu, const char *filename,
+ uint32_t start, uint32_t size)
+{
+ static uint32_t extable[32];
+ long kernel_size;
+ int i;
+
+ kernel_size = load_image_targphys(filename, start, size);
+ if (kernel_size < 0) {
+ fprintf(stderr, "qemu: could not load kernel '%s'\n", filename);
+ exit(1);
+ }
+ cpu->env.pc = start;
+
+ /* setup exception trap trampoline */
+ /* linux kernel only works little-endian mode */
+ for (i = 0; i < ARRAY_SIZE(extable); i++) {
+ extable[i] = cpu_to_le32(0x10 + i * 4);
+ }
+ rom_add_blob_fixed("extable", extable, sizeof(extable), 0xffffff80);
+}
+
+static void rxvirt_init(MachineState *machine)
+{
+ RX62NState *s = g_new(RX62NState, 1);
+ MemoryRegion *sysmem = get_system_memory();
+ MemoryRegion *sdram = g_new(MemoryRegion, 1);
+ const char *kernel_filename = machine->kernel_filename;
+ const char *dtb_filename = machine->dtb;
+ void *dtb = NULL;
+ int dtb_size;
+ ram_addr_t kernel_offset;
+ ram_addr_t dtb_offset;
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
+
+ if (machine->ram_size < mc->default_ram_size) {
+ error_report("Invalid RAM size, should be more than %" PRIi64 " Bytes",
+ mc->default_ram_size);
+ }
+
+ /* Allocate memory space */
+ memory_region_init_ram(sdram, NULL, "rx-virt.sdram", machine->ram_size,
+ &error_fatal);
+ memory_region_add_subregion(sysmem, SDRAM_BASE, sdram);
+
+ /* Initialize MCU */
+ object_initialize_child(OBJECT(machine), "mcu", s,
+ sizeof(RX62NState), TYPE_RX62N,
+ &error_fatal, NULL);
+ object_property_set_link(OBJECT(s), OBJECT(sysmem),
+ "memory", &error_abort);
+ object_property_set_bool(OBJECT(s), kernel_filename != NULL,
+ "load-kernel", &error_abort);
+ object_property_set_bool(OBJECT(s), true, "realized", &error_abort);
+
+ /* Load kernel and dtb */
+ if (kernel_filename) {
+ /*
+ * The kernel image is loaded into
+ * the latter half of the SDRAM space.
+ */
+ kernel_offset = machine->ram_size / 2;
+ rx_load_image(RXCPU(first_cpu), kernel_filename,
+ SDRAM_BASE + kernel_offset, kernel_offset);
+ if (dtb_filename) {
+ dtb = load_device_tree(dtb_filename, &dtb_size);
+ if (dtb == NULL) {
+ error_report("Couldn't open dtb file %s", dtb_filename);
+ exit(1);
+ }
+ if (machine->kernel_cmdline &&
+ qemu_fdt_setprop_string(dtb, "/chosen", "bootargs",
+ machine->kernel_cmdline) < 0) {
+ error_report("Couldn't set /chosen/bootargs");
+ exit(1);
+ }
+ /* DTB is located at the end of SDRAM space. */
+ dtb_offset = machine->ram_size - dtb_size;
+ rom_add_blob_fixed("dtb", dtb, dtb_size,
+ SDRAM_BASE + dtb_offset);
+ /* Set dtb address to R1 */
+ RXCPU(first_cpu)->env.regs[1] = SDRAM_BASE + dtb_offset;
+ }
+ }
+}
+
+static void rxvirt_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "RX QEMU Virtual Target";
+ mc->init = rxvirt_init;
+ mc->is_default = 1;
+ mc->default_cpu_type = TYPE_RX62N_CPU;
+ mc->default_ram_size = 16 * MiB;
+}
+
+static const TypeInfo rxvirt_type = {
+ .name = MACHINE_TYPE_NAME("rx-virt"),
+ .parent = TYPE_MACHINE,
+ .class_init = rxvirt_class_init,
+};
+
+static void rxvirt_machine_init(void)
+{
+ type_register_static(&rxvirt_type);
+}
+
+type_init(rxvirt_machine_init)
diff --git a/hw/rx/rx62n.c b/hw/rx/rx62n.c
new file mode 100644
index 0000000000..effd6d4f12
--- /dev/null
+++ b/hw/rx/rx62n.c
@@ -0,0 +1,240 @@
+/*
+ * RX62N Microcontroller
+ *
+ * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware
+ * (Rev.1.40 R01UH0033EJ0140)
+ *
+ * Copyright (c) 2019 Yoshinori Sato
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/hw.h"
+#include "hw/rx/rx62n.h"
+#include "hw/loader.h"
+#include "hw/sysbus.h"
+#include "hw/qdev-properties.h"
+#include "sysemu/sysemu.h"
+#include "cpu.h"
+
+/*
+ * IRQ -> IPR mapping table
+ * 0x00 - 0x91: IPR no (IPR00 to IPR91)
+ * 0xff: IPR not assigned
+ * See "11.3.1 Interrupt Vector Table" in hardware manual.
+ */
+static const int ipr_table[NR_IRQS] = {
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 15 */
+ 0x00, 0xff, 0xff, 0xff, 0xff, 0x01, 0xff, 0x02,
+ 0xff, 0xff, 0xff, 0x03, 0x04, 0x05, 0x06, 0x07, /* 31 */
+ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x14, 0x14, 0x14, /* 47 */
+ 0x15, 0x15, 0x15, 0x15, 0xff, 0xff, 0xff, 0xff,
+ 0x18, 0x18, 0x18, 0x18, 0x18, 0x1d, 0x1e, 0x1f, /* 63 */
+ 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
+ 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, /* 79 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0x3a, 0x3b, 0x3c, 0xff, 0xff, 0xff, /* 95 */
+ 0x40, 0xff, 0x44, 0x45, 0xff, 0xff, 0x48, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 111 */
+ 0xff, 0xff, 0x51, 0x51, 0x51, 0x51, 0x52, 0x52,
+ 0x52, 0x53, 0x53, 0x54, 0x54, 0x55, 0x55, 0x56, /* 127 */
+ 0x56, 0x57, 0x57, 0x57, 0x57, 0x58, 0x59, 0x59,
+ 0x59, 0x59, 0x5a, 0x5b, 0x5b, 0x5b, 0x5c, 0x5c, /* 143 */
+ 0x5c, 0x5c, 0x5d, 0x5d, 0x5d, 0x5e, 0x5e, 0x5f,
+ 0x5f, 0x60, 0x60, 0x61, 0x61, 0x62, 0x62, 0x62, /* 159 */
+ 0x62, 0x63, 0x64, 0x64, 0x64, 0x64, 0x65, 0x66,
+ 0x66, 0x66, 0x67, 0x67, 0x67, 0x67, 0x68, 0x68, /* 175 */
+ 0x68, 0x69, 0x69, 0x69, 0x6a, 0x6a, 0x6a, 0x6b,
+ 0x6b, 0x6b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 191 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, 0x71,
+ 0x72, 0x73, 0x74, 0x75, 0xff, 0xff, 0xff, 0xff, /* 207 */
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0x80,
+ 0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x82, 0x82, /* 223 */
+ 0x82, 0x82, 0x83, 0x83, 0x83, 0x83, 0xff, 0xff,
+ 0xff, 0xff, 0x85, 0x85, 0x85, 0x85, 0x86, 0x86, /* 239 */
+ 0x86, 0x86, 0xff, 0xff, 0xff, 0xff, 0x88, 0x89,
+ 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, 0x90, 0x91, /* 255 */
+};
+
+/*
+ * Level triggerd IRQ list
+ * Not listed IRQ is Edge trigger.
+ * See "11.3.1 Interrupt Vector Table" in hardware manual.
+ */
+static const uint32_t levelirq[] = {
+ 16, 21, 32, 44, 47, 48, 51, 64, 65, 66,
+ 67, 68, 69, 70, 71, 72, 73, 74, 75, 76,
+ 77, 78, 79, 90, 91, 170, 171, 172, 173, 214,
+ 217, 218, 221, 222, 225, 226, 229, 234, 237, 238,
+ 241, 246, 249, 250, 253,
+};
+
+static void register_icu(RX62NState *s)
+{
+ int i;
+ SysBusDevice *icu;
+
+ object_initialize_child(OBJECT(s), "icu", &s->icu, sizeof(RXICUState),
+ TYPE_RXICU, &error_abort, NULL);
+
+ icu = SYS_BUS_DEVICE(&s->icu);
+ sysbus_mmio_map(SYS_BUS_DEVICE(icu), 0, RX62N_ICUBASE);
+ qdev_prop_set_uint32(DEVICE(icu), "len-ipr-map", NR_IRQS);
+ for (i = 0; i < NR_IRQS; i++) {
+ char propname[32];
+ snprintf(propname, sizeof(propname), "ipr-map[%d]", i);
+ qdev_prop_set_uint32(DEVICE(icu), propname, ipr_table[i]);
+ }
+ qdev_prop_set_uint32(DEVICE(icu), "len-trigger-level",
+ ARRAY_SIZE(levelirq));
+ for (i = 0; i < ARRAY_SIZE(levelirq); i++) {
+ char propname[32];
+ snprintf(propname, sizeof(propname), "trigger-level[%d]", i);
+ qdev_prop_set_uint32(DEVICE(icu), propname, levelirq[i]);
+ }
+
+ for (i = 0; i < NR_IRQS; i++) {
+ s->irq[i] = qdev_get_gpio_in(DEVICE(icu), i);
+ }
+
+ qdev_init_nofail(DEVICE(icu));
+ sysbus_connect_irq(icu, 0, qdev_get_gpio_in(DEVICE(&s->cpu), RX_CPU_IRQ));
+ sysbus_connect_irq(icu, 1, qdev_get_gpio_in(DEVICE(&s->cpu), RX_CPU_FIR));
+ sysbus_connect_irq(icu, 2, s->irq[SWI]);
+
+}
+
+static void register_tmr(RX62NState *s, int unit)
+{
+ SysBusDevice *tmr;
+ int i, irqbase;
+
+ object_initialize_child(OBJECT(s), "tmr[*]", &s->tmr[unit],
+ sizeof(RTMRState), TYPE_RENESAS_8TMR,
+ &error_abort, NULL);
+
+ tmr = SYS_BUS_DEVICE(&s->tmr[unit]);
+ qdev_prop_set_uint64(DEVICE(tmr), "input-freq", RX62N_PCLK);
+
+ qdev_init_nofail(DEVICE(tmr));
+ sysbus_mmio_map(tmr, 0, RX62N_TMRBASE + unit * 0x10);
+ irqbase = RX62N_TMR_IRQBASE + TMR_NR_IRQ * unit;
+ for (i = 0; i < TMR_NR_IRQ; i++) {
+ sysbus_connect_irq(tmr, i, s->irq[irqbase + i]);
+ }
+}
+
+static void register_cmt(RX62NState *s, int unit)
+{
+ SysBusDevice *cmt;
+ int i, irqbase;
+
+ object_initialize_child(OBJECT(s), "cmt[*]", &s->cmt[unit],
+ sizeof(RTIMERState), TYPE_RENESAS_TIMER,
+ &error_abort, NULL);
+
+ cmt = SYS_BUS_DEVICE(&s->cmt[unit]);
+ qdev_prop_set_uint64(DEVICE(cmt), "input-freq", RX62N_PCLK);
+ qdev_prop_set_int32(DEVICE(cmt), "feature", RTIMER_FEAT_CMT);
+ qdev_init_nofail(DEVICE(cmt));
+ sysbus_mmio_map(cmt, 0, RX62N_CMTBASE + unit * 0x10);
+ irqbase = RX62N_CMT_IRQBASE + TIMER_CH_CMT * unit;
+ for (i = 0; i < TIMER_CH_CMT; i++) {
+ sysbus_connect_irq(cmt, i, s->irq[irqbase + i]);
+ }
+}
+
+static void register_sci(RX62NState *s, int unit)
+{
+ SysBusDevice *sci;
+ int i, irqbase;
+
+ object_initialize_child(OBJECT(s), "sci[*]", &s->sci[unit],
+ sizeof(RSCIState), TYPE_RENESAS_SCI,
+ &error_abort, NULL);
+ sci = SYS_BUS_DEVICE(&s->sci[unit]);
+
+ qdev_prop_set_chr(DEVICE(sci), "chardev", serial_hd(unit));
+ qdev_prop_set_uint64(DEVICE(sci), "input-freq", RX62N_PCLK);
+ qdev_prop_set_int32(DEVICE(sci), "feature", SCI_FEAT_SCIA);
+ qdev_prop_set_int32(DEVICE(sci), "register-size", 8);
+ qdev_init_nofail(DEVICE(sci));
+ sysbus_mmio_map(sci, 0, RX62N_SCIBASE + unit * 0x08);
+ irqbase = RX62N_SCI_IRQBASE + SCI_NR_IRQ * unit;
+ for (i = 0; i < SCI_NR_IRQ; i++) {
+ sysbus_connect_irq(sci, i, s->irq[irqbase + i]);
+ }
+}
+
+static void rx62n_realize(DeviceState *dev, Error **errp)
+{
+ RX62NState *s = RX62N(dev);
+
+ memory_region_init_ram(&s->iram, NULL, "iram", RX62N_IRAM_SIZE, errp);
+ memory_region_add_subregion(s->sysmem, RX62N_IRAM_BASE, &s->iram);
+ memory_region_init_rom(&s->d_flash, NULL, "dataflash",
+ RX62N_DFLASH_SIZE, errp);
+ memory_region_add_subregion(s->sysmem, RX62N_DFLASH_BASE, &s->d_flash);
+ memory_region_init_rom(&s->c_flash, NULL, "codeflash",
+ RX62N_CFLASH_SIZE, errp);
+ memory_region_add_subregion(s->sysmem, RX62N_CFLASH_BASE, &s->c_flash);
+ if (!s->kernel) {
+ rom_add_file_fixed(bios_name, RX62N_CFLASH_BASE, 0);
+ }
+
+ /* Initialize CPU */
+ object_initialize_child(OBJECT(s), "cpu", &s->cpu, sizeof(RXCPU),
+ TYPE_RX62N_CPU, errp, NULL);
+
+ register_icu(s);
+ s->cpu.env.ack = qdev_get_gpio_in_named(DEVICE(&s->icu), "ack", 0);
+ register_tmr(s, 0);
+ register_tmr(s, 1);
+ register_cmt(s, 0);
+ register_cmt(s, 1);
+ register_sci(s, 0);
+ object_property_set_bool(OBJECT(&s->cpu), true, "realized", errp);
+}
+
+static Property rx62n_properties[] = {
+ DEFINE_PROP_LINK("memory", RX62NState, sysmem, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+ DEFINE_PROP_BOOL("load-kernel", RX62NState, kernel, false),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void rx62n_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = rx62n_realize;
+ device_class_set_props(dc, rx62n_properties);
+}
+
+static const TypeInfo rx62n_info = {
+ .name = TYPE_RX62N,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(RX62NState),
+ .class_init = rx62n_class_init,
+};
+
+static void rx62n_register_types(void)
+{
+ type_register_static(&rx62n_info);
+}
+
+type_init(rx62n_register_types)
diff --git a/hw/rx/Kconfig b/hw/rx/Kconfig
new file mode 100644
index 0000000000..43af11be46
--- /dev/null
+++ b/hw/rx/Kconfig
@@ -0,0 +1,13 @@
+config RX
+ bool
+
+config RX62N
+ bool
+ select RX
+ select RENESAS_8TMR
+ select RENESAS_TIMER
+ select RENESAS_SCI
+
+config RX_VIRT
+ bool
+ select RX62N
diff --git a/hw/rx/Makefile.objs b/hw/rx/Makefile.objs
new file mode 100644
index 0000000000..63f8be0e82
--- /dev/null
+++ b/hw/rx/Makefile.objs
@@ -0,0 +1,2 @@
+obj-$(CONFIG_RX62N) += rx62n.o
+obj-$(CONFIG_RX_VIRT) += rx-virt.o
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 05/10] hw/rx: RX MCU and target
2020-05-31 16:24 ` [PATCH 05/10] hw/rx: RX MCU and target Yoshinori Sato
@ 2020-06-05 16:09 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-06-05 16:09 UTC (permalink / raw)
To: Yoshinori Sato, qemu-devel
On 5/31/20 6:24 PM, Yoshinori Sato wrote:
> rx62n - RX62N MCU.
> rx-virt - RX QEMU virtual target.
> This has the same specifications as the gdb simulator.
>
> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
> ---
> include/hw/rx/rx.h | 7 ++
> include/hw/rx/rx62n.h | 91 ++++++++++++++++
> hw/rx/rx-virt.c | 143 +++++++++++++++++++++++++
> hw/rx/rx62n.c | 240 ++++++++++++++++++++++++++++++++++++++++++
> hw/rx/Kconfig | 13 +++
> hw/rx/Makefile.objs | 2 +
> 6 files changed, 496 insertions(+)
> create mode 100644 include/hw/rx/rx.h
> create mode 100644 include/hw/rx/rx62n.h
> create mode 100644 hw/rx/rx-virt.c
> create mode 100644 hw/rx/rx62n.c
> create mode 100644 hw/rx/Kconfig
> create mode 100644 hw/rx/Makefile.objs
>
[...]
> +static void register_tmr(RX62NState *s, int unit)
> +{
> + SysBusDevice *tmr;
> + int i, irqbase;
> +
> + object_initialize_child(OBJECT(s), "tmr[*]", &s->tmr[unit],
> + sizeof(RTMRState), TYPE_RENESAS_8TMR,
> + &error_abort, NULL);
> +
> + tmr = SYS_BUS_DEVICE(&s->tmr[unit]);
> + qdev_prop_set_uint64(DEVICE(tmr), "input-freq", RX62N_PCLK);
> +
> + qdev_init_nofail(DEVICE(tmr));
> + sysbus_mmio_map(tmr, 0, RX62N_TMRBASE + unit * 0x10);
> + irqbase = RX62N_TMR_IRQBASE + TMR_NR_IRQ * unit;
> + for (i = 0; i < TMR_NR_IRQ; i++) {
> + sysbus_connect_irq(tmr, i, s->irq[irqbase + i]);
> + }
> +}
> +
> +static void register_cmt(RX62NState *s, int unit)
> +{
> + SysBusDevice *cmt;
> + int i, irqbase;
> +
> + object_initialize_child(OBJECT(s), "cmt[*]", &s->cmt[unit],
> + sizeof(RTIMERState), TYPE_RENESAS_TIMER,
> + &error_abort, NULL);
> +
> + cmt = SYS_BUS_DEVICE(&s->cmt[unit]);
> + qdev_prop_set_uint64(DEVICE(cmt), "input-freq", RX62N_PCLK);
> + qdev_prop_set_int32(DEVICE(cmt), "feature", RTIMER_FEAT_CMT);
OK, single logical change, no problem.
> + qdev_init_nofail(DEVICE(cmt));
> + sysbus_mmio_map(cmt, 0, RX62N_CMTBASE + unit * 0x10);
> + irqbase = RX62N_CMT_IRQBASE + TIMER_CH_CMT * unit;
> + for (i = 0; i < TIMER_CH_CMT; i++) {
> + sysbus_connect_irq(cmt, i, s->irq[irqbase + i]);
> + }
> +}
> +
> +static void register_sci(RX62NState *s, int unit)
> +{
> + SysBusDevice *sci;
> + int i, irqbase;
> +
> + object_initialize_child(OBJECT(s), "sci[*]", &s->sci[unit],
> + sizeof(RSCIState), TYPE_RENESAS_SCI,
> + &error_abort, NULL);
> + sci = SYS_BUS_DEVICE(&s->sci[unit]);
> +
> + qdev_prop_set_chr(DEVICE(sci), "chardev", serial_hd(unit));
> + qdev_prop_set_uint64(DEVICE(sci), "input-freq", RX62N_PCLK);
> + qdev_prop_set_int32(DEVICE(sci), "feature", SCI_FEAT_SCIA);
> + qdev_prop_set_int32(DEVICE(sci), "register-size", 8);
> + qdev_init_nofail(DEVICE(sci));
> + sysbus_mmio_map(sci, 0, RX62N_SCIBASE + unit * 0x08);
> + irqbase = RX62N_SCI_IRQBASE + SCI_NR_IRQ * unit;
> + for (i = 0; i < SCI_NR_IRQ; i++) {
> + sysbus_connect_irq(sci, i, s->irq[irqbase + i]);
> + }
> +}[...]
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 06/10] Add rx-softmmu
2020-05-31 16:24 [PATCH 00/10] Add RX hardware emulation Yoshinori Sato
` (4 preceding siblings ...)
2020-05-31 16:24 ` [PATCH 05/10] hw/rx: RX MCU and target Yoshinori Sato
@ 2020-05-31 16:24 ` Yoshinori Sato
2020-05-31 16:24 ` [PATCH 07/10] hw/sh4: Convert renesas_sci Yoshinori Sato
` (4 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Yoshinori Sato @ 2020-05-31 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Philippe Mathieu-Daudé, Yoshinori Sato
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-Id: <20190607091116.49044-17-ysato@users.sourceforge.jp>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
pick ed65c02993 target/rx: Add RX to SysEmuTarget
pick 01372568ae tests: Add rx to machine-none-test.c
[PMD: Squashed patches from Richard Henderson modifying
qapi/common.json and tests/machine-none-test.c]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
default-configs/rx-softmmu.mak | 1 +
hw/Kconfig | 1 +
2 files changed, 2 insertions(+)
diff --git a/default-configs/rx-softmmu.mak b/default-configs/rx-softmmu.mak
index 7c4eb2c1a0..a3eecefb11 100644
--- a/default-configs/rx-softmmu.mak
+++ b/default-configs/rx-softmmu.mak
@@ -1,2 +1,3 @@
# Default configuration for rx-softmmu
+CONFIG_RX_VIRT=y
diff --git a/hw/Kconfig b/hw/Kconfig
index ecf491bf04..62f9ebdc22 100644
--- a/hw/Kconfig
+++ b/hw/Kconfig
@@ -55,6 +55,7 @@ source nios2/Kconfig
source openrisc/Kconfig
source ppc/Kconfig
source riscv/Kconfig
+source rx/Kconfig
source s390x/Kconfig
source sh4/Kconfig
source sparc/Kconfig
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 07/10] hw/sh4: Convert renesas_sci.
2020-05-31 16:24 [PATCH 00/10] Add RX hardware emulation Yoshinori Sato
` (5 preceding siblings ...)
2020-05-31 16:24 ` [PATCH 06/10] Add rx-softmmu Yoshinori Sato
@ 2020-05-31 16:24 ` Yoshinori Sato
2020-05-31 16:24 ` [PATCH 08/10] hw/char: remove sh_serial.c Yoshinori Sato
` (3 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Yoshinori Sato @ 2020-05-31 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: Yoshinori Sato
Using new implementation SCI module.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
include/hw/sh4/sh.h | 11 -----------
hw/sh4/sh7750.c | 45 +++++++++++++++++++++++++++++++++++++++++----
hw/sh4/Kconfig | 1 +
3 files changed, 42 insertions(+), 15 deletions(-)
diff --git a/include/hw/sh4/sh.h b/include/hw/sh4/sh.h
index 767a2df7e2..e184b4b300 100644
--- a/include/hw/sh4/sh.h
+++ b/include/hw/sh4/sh.h
@@ -38,17 +38,6 @@ void tmu012_init(struct MemoryRegion *sysmem, hwaddr base,
qemu_irq ch2_irq0, qemu_irq ch2_irq1);
-/* sh_serial.c */
-#define SH_SERIAL_FEAT_SCIF (1 << 0)
-void sh_serial_init(MemoryRegion *sysmem,
- hwaddr base, int feat,
- uint32_t freq, Chardev *chr,
- qemu_irq eri_source,
- qemu_irq rxi_source,
- qemu_irq txi_source,
- qemu_irq tei_source,
- qemu_irq bri_source);
-
/* sh7750.c */
qemu_irq sh7750_irl(struct SH7750State *s);
diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c
index d660714443..150d3029f7 100644
--- a/hw/sh4/sh7750.c
+++ b/hw/sh4/sh7750.c
@@ -24,12 +24,15 @@
*/
#include "qemu/osdep.h"
+#include "qapi/error.h"
#include "hw/irq.h"
#include "hw/sh4/sh.h"
#include "sysemu/sysemu.h"
#include "sh7750_regs.h"
#include "sh7750_regnames.h"
#include "hw/sh4/sh_intc.h"
+#include "hw/char/renesas_sci.h"
+#include "hw/qdev-properties.h"
#include "cpu.h"
#include "exec/exec-all.h"
@@ -752,6 +755,40 @@ static const MemoryRegionOps sh7750_mmct_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
+static void sh_serial_init(SH7750State *s, MemoryRegion *sysmem,
+ hwaddr base, int feat,
+ uint32_t freq, Chardev *chr,
+ qemu_irq eri_source,
+ qemu_irq rxi_source,
+ qemu_irq txi_source,
+ qemu_irq tei_source,
+ qemu_irq bri_source)
+{
+ DeviceState *dev;
+ SysBusDevice *sci;
+
+ dev = qdev_create(NULL, TYPE_RENESAS_SCI);
+
+ sci = SYS_BUS_DEVICE(dev);
+
+ qdev_prop_set_chr(dev, "chardev", chr);
+ qdev_prop_set_uint64(dev, "input-freq", freq);
+ qdev_prop_set_int32(dev, "feature", feat);
+ qdev_prop_set_int32(dev, "register-size", 32);
+ qdev_init_nofail(dev);
+ sysbus_mmio_map(sci, 0, base);
+ sysbus_mmio_map(sci, 1, P4ADDR(base));
+ sysbus_mmio_map(sci, 2, A7ADDR(base));
+ sysbus_connect_irq(sci, 0, eri_source);
+ sysbus_connect_irq(sci, 1, rxi_source);
+ sysbus_connect_irq(sci, 2, txi_source);
+ if (feat == SCI_FEAT_SCI) {
+ sysbus_connect_irq(sci, 3, tei_source);
+ } else {
+ sysbus_connect_irq(sci, 3, bri_source);
+ }
+}
+
SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem)
{
SH7750State *s;
@@ -800,15 +837,15 @@ SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem)
cpu->env.intc_handle = &s->intc;
- sh_serial_init(sysmem, 0x1fe00000,
- 0, s->periph_freq, serial_hd(0),
+ sh_serial_init(s, sysmem, 0x1fe00000,
+ SCI_FEAT_SCI, s->periph_freq, serial_hd(0),
s->intc.irqs[SCI1_ERI],
s->intc.irqs[SCI1_RXI],
s->intc.irqs[SCI1_TXI],
s->intc.irqs[SCI1_TEI],
NULL);
- sh_serial_init(sysmem, 0x1fe80000,
- SH_SERIAL_FEAT_SCIF,
+ sh_serial_init(s, sysmem, 0x1fe80000,
+ SCI_FEAT_SCIF,
s->periph_freq, serial_hd(1),
s->intc.irqs[SCIF_ERI],
s->intc.irqs[SCIF_RXI],
diff --git a/hw/sh4/Kconfig b/hw/sh4/Kconfig
index 4cbce3a0ed..38509b7e65 100644
--- a/hw/sh4/Kconfig
+++ b/hw/sh4/Kconfig
@@ -22,3 +22,4 @@ config SH7750
config SH4
bool
select PTIMER
+ select RENESAS_SCI
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 08/10] hw/char: remove sh_serial.c
2020-05-31 16:24 [PATCH 00/10] Add RX hardware emulation Yoshinori Sato
` (6 preceding siblings ...)
2020-05-31 16:24 ` [PATCH 07/10] hw/sh4: Convert renesas_sci Yoshinori Sato
@ 2020-05-31 16:24 ` Yoshinori Sato
2020-05-31 16:24 ` [PATCH 09/10] hw/sh4: Convert to renesas_timer.c Yoshinori Sato
` (2 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Yoshinori Sato @ 2020-05-31 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: Yoshinori Sato
SH4 SCI module convert to renesas_sci.c.
This file is obsolute.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
hw/char/sh_serial.c | 431 --------------------------------------------
1 file changed, 431 deletions(-)
delete mode 100644 hw/char/sh_serial.c
diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c
deleted file mode 100644
index 167f4d8cb9..0000000000
--- a/hw/char/sh_serial.c
+++ /dev/null
@@ -1,431 +0,0 @@
-/*
- * QEMU SCI/SCIF serial port emulation
- *
- * Copyright (c) 2007 Magnus Damm
- *
- * Based on serial.c - QEMU 16450 UART emulation
- * Copyright (c) 2003-2004 Fabrice Bellard
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "qemu/osdep.h"
-#include "hw/irq.h"
-#include "hw/sh4/sh.h"
-#include "chardev/char-fe.h"
-#include "qapi/error.h"
-#include "qemu/timer.h"
-
-//#define DEBUG_SERIAL
-
-#define SH_SERIAL_FLAG_TEND (1 << 0)
-#define SH_SERIAL_FLAG_TDE (1 << 1)
-#define SH_SERIAL_FLAG_RDF (1 << 2)
-#define SH_SERIAL_FLAG_BRK (1 << 3)
-#define SH_SERIAL_FLAG_DR (1 << 4)
-
-#define SH_RX_FIFO_LENGTH (16)
-
-typedef struct {
- MemoryRegion iomem;
- MemoryRegion iomem_p4;
- MemoryRegion iomem_a7;
- uint8_t smr;
- uint8_t brr;
- uint8_t scr;
- uint8_t dr; /* ftdr / tdr */
- uint8_t sr; /* fsr / ssr */
- uint16_t fcr;
- uint8_t sptr;
-
- uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
- uint8_t rx_cnt;
- uint8_t rx_tail;
- uint8_t rx_head;
-
- int freq;
- int feat;
- int flags;
- int rtrg;
-
- CharBackend chr;
- QEMUTimer *fifo_timeout_timer;
- uint64_t etu; /* Elementary Time Unit (ns) */
-
- qemu_irq eri;
- qemu_irq rxi;
- qemu_irq txi;
- qemu_irq tei;
- qemu_irq bri;
-} sh_serial_state;
-
-static void sh_serial_clear_fifo(sh_serial_state * s)
-{
- memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
- s->rx_cnt = 0;
- s->rx_head = 0;
- s->rx_tail = 0;
-}
-
-static void sh_serial_write(void *opaque, hwaddr offs,
- uint64_t val, unsigned size)
-{
- sh_serial_state *s = opaque;
- unsigned char ch;
-
-#ifdef DEBUG_SERIAL
- printf("sh_serial: write offs=0x%02x val=0x%02x\n",
- offs, val);
-#endif
- switch(offs) {
- case 0x00: /* SMR */
- s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
- return;
- case 0x04: /* BRR */
- s->brr = val;
- return;
- case 0x08: /* SCR */
- /* TODO : For SH7751, SCIF mask should be 0xfb. */
- s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
- if (!(val & (1 << 5)))
- s->flags |= SH_SERIAL_FLAG_TEND;
- if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
- qemu_set_irq(s->txi, val & (1 << 7));
- }
- if (!(val & (1 << 6))) {
- qemu_set_irq(s->rxi, 0);
- }
- return;
- case 0x0c: /* FTDR / TDR */
- if (qemu_chr_fe_backend_connected(&s->chr)) {
- ch = val;
- /* XXX this blocks entire thread. Rewrite to use
- * qemu_chr_fe_write and background I/O callbacks */
- qemu_chr_fe_write_all(&s->chr, &ch, 1);
- }
- s->dr = val;
- s->flags &= ~SH_SERIAL_FLAG_TDE;
- return;
-#if 0
- case 0x14: /* FRDR / RDR */
- ret = 0;
- break;
-#endif
- }
- if (s->feat & SH_SERIAL_FEAT_SCIF) {
- switch(offs) {
- case 0x10: /* FSR */
- if (!(val & (1 << 6)))
- s->flags &= ~SH_SERIAL_FLAG_TEND;
- if (!(val & (1 << 5)))
- s->flags &= ~SH_SERIAL_FLAG_TDE;
- if (!(val & (1 << 4)))
- s->flags &= ~SH_SERIAL_FLAG_BRK;
- if (!(val & (1 << 1)))
- s->flags &= ~SH_SERIAL_FLAG_RDF;
- if (!(val & (1 << 0)))
- s->flags &= ~SH_SERIAL_FLAG_DR;
-
- if (!(val & (1 << 1)) || !(val & (1 << 0))) {
- if (s->rxi) {
- qemu_set_irq(s->rxi, 0);
- }
- }
- return;
- case 0x18: /* FCR */
- s->fcr = val;
- switch ((val >> 6) & 3) {
- case 0:
- s->rtrg = 1;
- break;
- case 1:
- s->rtrg = 4;
- break;
- case 2:
- s->rtrg = 8;
- break;
- case 3:
- s->rtrg = 14;
- break;
- }
- if (val & (1 << 1)) {
- sh_serial_clear_fifo(s);
- s->sr &= ~(1 << 1);
- }
-
- return;
- case 0x20: /* SPTR */
- s->sptr = val & 0xf3;
- return;
- case 0x24: /* LSR */
- return;
- }
- }
- else {
- switch(offs) {
-#if 0
- case 0x0c:
- ret = s->dr;
- break;
- case 0x10:
- ret = 0;
- break;
-#endif
- case 0x1c:
- s->sptr = val & 0x8f;
- return;
- }
- }
-
- fprintf(stderr, "sh_serial: unsupported write to 0x%02"
- HWADDR_PRIx "\n", offs);
- abort();
-}
-
-static uint64_t sh_serial_read(void *opaque, hwaddr offs,
- unsigned size)
-{
- sh_serial_state *s = opaque;
- uint32_t ret = ~0;
-
-#if 0
- switch(offs) {
- case 0x00:
- ret = s->smr;
- break;
- case 0x04:
- ret = s->brr;
- break;
- case 0x08:
- ret = s->scr;
- break;
- case 0x14:
- ret = 0;
- break;
- }
-#endif
- if (s->feat & SH_SERIAL_FEAT_SCIF) {
- switch(offs) {
- case 0x00: /* SMR */
- ret = s->smr;
- break;
- case 0x08: /* SCR */
- ret = s->scr;
- break;
- case 0x10: /* FSR */
- ret = 0;
- if (s->flags & SH_SERIAL_FLAG_TEND)
- ret |= (1 << 6);
- if (s->flags & SH_SERIAL_FLAG_TDE)
- ret |= (1 << 5);
- if (s->flags & SH_SERIAL_FLAG_BRK)
- ret |= (1 << 4);
- if (s->flags & SH_SERIAL_FLAG_RDF)
- ret |= (1 << 1);
- if (s->flags & SH_SERIAL_FLAG_DR)
- ret |= (1 << 0);
-
- if (s->scr & (1 << 5))
- s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND;
-
- break;
- case 0x14:
- if (s->rx_cnt > 0) {
- ret = s->rx_fifo[s->rx_tail++];
- s->rx_cnt--;
- if (s->rx_tail == SH_RX_FIFO_LENGTH)
- s->rx_tail = 0;
- if (s->rx_cnt < s->rtrg)
- s->flags &= ~SH_SERIAL_FLAG_RDF;
- }
- break;
- case 0x18:
- ret = s->fcr;
- break;
- case 0x1c:
- ret = s->rx_cnt;
- break;
- case 0x20:
- ret = s->sptr;
- break;
- case 0x24:
- ret = 0;
- break;
- }
- }
- else {
- switch(offs) {
-#if 0
- case 0x0c:
- ret = s->dr;
- break;
- case 0x10:
- ret = 0;
- break;
- case 0x14:
- ret = s->rx_fifo[0];
- break;
-#endif
- case 0x1c:
- ret = s->sptr;
- break;
- }
- }
-#ifdef DEBUG_SERIAL
- printf("sh_serial: read offs=0x%02x val=0x%x\n",
- offs, ret);
-#endif
-
- if (ret & ~((1 << 16) - 1)) {
- fprintf(stderr, "sh_serial: unsupported read from 0x%02"
- HWADDR_PRIx "\n", offs);
- abort();
- }
-
- return ret;
-}
-
-static int sh_serial_can_receive(sh_serial_state *s)
-{
- return s->scr & (1 << 4);
-}
-
-static void sh_serial_receive_break(sh_serial_state *s)
-{
- if (s->feat & SH_SERIAL_FEAT_SCIF)
- s->sr |= (1 << 4);
-}
-
-static int sh_serial_can_receive1(void *opaque)
-{
- sh_serial_state *s = opaque;
- return sh_serial_can_receive(s);
-}
-
-static void sh_serial_timeout_int(void *opaque)
-{
- sh_serial_state *s = opaque;
-
- s->flags |= SH_SERIAL_FLAG_RDF;
- if (s->scr & (1 << 6) && s->rxi) {
- qemu_set_irq(s->rxi, 1);
- }
-}
-
-static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size)
-{
- sh_serial_state *s = opaque;
-
- if (s->feat & SH_SERIAL_FEAT_SCIF) {
- int i;
- for (i = 0; i < size; i++) {
- if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
- s->rx_fifo[s->rx_head++] = buf[i];
- if (s->rx_head == SH_RX_FIFO_LENGTH) {
- s->rx_head = 0;
- }
- s->rx_cnt++;
- if (s->rx_cnt >= s->rtrg) {
- s->flags |= SH_SERIAL_FLAG_RDF;
- if (s->scr & (1 << 6) && s->rxi) {
- timer_del(s->fifo_timeout_timer);
- qemu_set_irq(s->rxi, 1);
- }
- } else {
- timer_mod(s->fifo_timeout_timer,
- qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 15 * s->etu);
- }
- }
- }
- } else {
- s->rx_fifo[0] = buf[0];
- }
-}
-
-static void sh_serial_event(void *opaque, QEMUChrEvent event)
-{
- sh_serial_state *s = opaque;
- if (event == CHR_EVENT_BREAK)
- sh_serial_receive_break(s);
-}
-
-static const MemoryRegionOps sh_serial_ops = {
- .read = sh_serial_read,
- .write = sh_serial_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
-};
-
-void sh_serial_init(MemoryRegion *sysmem,
- hwaddr base, int feat,
- uint32_t freq, Chardev *chr,
- qemu_irq eri_source,
- qemu_irq rxi_source,
- qemu_irq txi_source,
- qemu_irq tei_source,
- qemu_irq bri_source)
-{
- sh_serial_state *s;
-
- s = g_malloc0(sizeof(sh_serial_state));
-
- s->feat = feat;
- s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE;
- s->rtrg = 1;
-
- s->smr = 0;
- s->brr = 0xff;
- s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
- s->sptr = 0;
-
- if (feat & SH_SERIAL_FEAT_SCIF) {
- s->fcr = 0;
- }
- else {
- s->dr = 0xff;
- }
-
- sh_serial_clear_fifo(s);
-
- memory_region_init_io(&s->iomem, NULL, &sh_serial_ops, s,
- "serial", 0x100000000ULL);
-
- memory_region_init_alias(&s->iomem_p4, NULL, "serial-p4", &s->iomem,
- 0, 0x28);
- memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
-
- memory_region_init_alias(&s->iomem_a7, NULL, "serial-a7", &s->iomem,
- 0, 0x28);
- memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
-
- if (chr) {
- qemu_chr_fe_init(&s->chr, chr, &error_abort);
- qemu_chr_fe_set_handlers(&s->chr, sh_serial_can_receive1,
- sh_serial_receive1,
- sh_serial_event, NULL, s, NULL, true);
- }
-
- s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
- sh_serial_timeout_int, s);
- s->etu = NANOSECONDS_PER_SECOND / 9600;
- s->eri = eri_source;
- s->rxi = rxi_source;
- s->txi = txi_source;
- s->tei = tei_source;
- s->bri = bri_source;
-}
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 09/10] hw/sh4: Convert to renesas_timer.c
2020-05-31 16:24 [PATCH 00/10] Add RX hardware emulation Yoshinori Sato
` (7 preceding siblings ...)
2020-05-31 16:24 ` [PATCH 08/10] hw/char: remove sh_serial.c Yoshinori Sato
@ 2020-05-31 16:24 ` Yoshinori Sato
2020-05-31 16:24 ` [PATCH 10/10] hw/timer: remove sh_timer.c Yoshinori Sato
2020-05-31 16:45 ` [PATCH 00/10] Add RX hardware emulation Philippe Mathieu-Daudé
10 siblings, 0 replies; 17+ messages in thread
From: Yoshinori Sato @ 2020-05-31 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: Yoshinori Sato
Using unified TMU/CMT module.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
include/hw/sh4/sh.h | 10 ---------
hw/sh4/sh7750.c | 47 +++++++++++++++++++++++++++++++++---------
hw/sh4/Kconfig | 2 +-
hw/timer/Makefile.objs | 1 -
4 files changed, 38 insertions(+), 22 deletions(-)
diff --git a/include/hw/sh4/sh.h b/include/hw/sh4/sh.h
index e184b4b300..248cc052e1 100644
--- a/include/hw/sh4/sh.h
+++ b/include/hw/sh4/sh.h
@@ -28,16 +28,6 @@ typedef struct {
int sh7750_register_io_device(struct SH7750State *s,
sh7750_io_device * device);
-/* sh_timer.c */
-#define TMU012_FEAT_TOCR (1 << 0)
-#define TMU012_FEAT_3CHAN (1 << 1)
-#define TMU012_FEAT_EXTCLK (1 << 2)
-void tmu012_init(struct MemoryRegion *sysmem, hwaddr base,
- int feat, uint32_t freq,
- qemu_irq ch0_irq, qemu_irq ch1_irq,
- qemu_irq ch2_irq0, qemu_irq ch2_irq1);
-
-
/* sh7750.c */
qemu_irq sh7750_irl(struct SH7750State *s);
diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c
index 150d3029f7..733c4009e1 100644
--- a/hw/sh4/sh7750.c
+++ b/hw/sh4/sh7750.c
@@ -32,6 +32,7 @@
#include "sh7750_regnames.h"
#include "hw/sh4/sh_intc.h"
#include "hw/char/renesas_sci.h"
+#include "hw/timer/renesas_timer.h"
#include "hw/qdev-properties.h"
#include "cpu.h"
#include "exec/exec-all.h"
@@ -756,13 +757,13 @@ static const MemoryRegionOps sh7750_mmct_ops = {
};
static void sh_serial_init(SH7750State *s, MemoryRegion *sysmem,
- hwaddr base, int feat,
- uint32_t freq, Chardev *chr,
- qemu_irq eri_source,
- qemu_irq rxi_source,
- qemu_irq txi_source,
- qemu_irq tei_source,
- qemu_irq bri_source)
+ hwaddr base, int feat,
+ uint32_t freq, Chardev *chr,
+ qemu_irq eri_source,
+ qemu_irq rxi_source,
+ qemu_irq txi_source,
+ qemu_irq tei_source,
+ qemu_irq bri_source)
{
DeviceState *dev;
SysBusDevice *sci;
@@ -789,6 +790,31 @@ static void sh_serial_init(SH7750State *s, MemoryRegion *sysmem,
}
}
+static void tmu012_init(SH7750State *s, MemoryRegion *sysmem, hwaddr base,
+ int feat, uint32_t freq,
+ qemu_irq ch0_irq, qemu_irq ch1_irq,
+ qemu_irq ch2_irq0, qemu_irq ch2_irq1)
+{
+ DeviceState *dev;
+ SysBusDevice *tmu;
+
+ dev = qdev_create(NULL, TYPE_RENESAS_TIMER);
+
+ tmu = SYS_BUS_DEVICE(dev);
+
+ qdev_prop_set_uint64(dev, "input-freq", freq);
+ qdev_prop_set_int32(dev, "feature", feat);
+ qdev_init_nofail(dev);
+ sysbus_mmio_map(tmu, 0, base);
+ sysbus_mmio_map(tmu, 1, P4ADDR(base));
+ sysbus_mmio_map(tmu, 2, A7ADDR(base));
+ sysbus_connect_irq(tmu, 0, ch0_irq);
+ sysbus_connect_irq(tmu, 1, ch1_irq);
+ if (ch2_irq0) {
+ sysbus_connect_irq(tmu, 2, ch2_irq0);
+ }
+}
+
SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem)
{
SH7750State *s;
@@ -853,8 +879,8 @@ SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem)
NULL,
s->intc.irqs[SCIF_BRI]);
- tmu012_init(sysmem, 0x1fd80000,
- TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
+ tmu012_init(s, sysmem, 0x1fd80000,
+ RTIMER_FEAT_TMU_LOW,
s->periph_freq,
s->intc.irqs[TMU0],
s->intc.irqs[TMU1],
@@ -877,7 +903,8 @@ SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem)
sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_tmu34),
NULL, 0);
- tmu012_init(sysmem, 0x1e100000, 0, s->periph_freq,
+ tmu012_init(s, sysmem, 0x1e100000,
+ RTIMER_FEAT_TMU_HIGH, s->periph_freq,
s->intc.irqs[TMU3],
s->intc.irqs[TMU4],
NULL, NULL);
diff --git a/hw/sh4/Kconfig b/hw/sh4/Kconfig
index 38509b7e65..ac21830bb5 100644
--- a/hw/sh4/Kconfig
+++ b/hw/sh4/Kconfig
@@ -21,5 +21,5 @@ config SH7750
config SH4
bool
- select PTIMER
+ select RENESAS_TIMER
select RENESAS_SCI
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index 289b6b03ab..f3918836e4 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -22,7 +22,6 @@ common-obj-$(CONFIG_EXYNOS4) += exynos4210_pwm.o
common-obj-$(CONFIG_OMAP) += omap_gptimer.o
common-obj-$(CONFIG_OMAP) += omap_synctimer.o
common-obj-$(CONFIG_PXA2XX) += pxa2xx_timer.o
-common-obj-$(CONFIG_SH4) += sh_timer.o
common-obj-$(CONFIG_DIGIC) += digic-timer.o
common-obj-$(CONFIG_MIPS_CPS) += mips_gictimer.o
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 10/10] hw/timer: remove sh_timer.c
2020-05-31 16:24 [PATCH 00/10] Add RX hardware emulation Yoshinori Sato
` (8 preceding siblings ...)
2020-05-31 16:24 ` [PATCH 09/10] hw/sh4: Convert to renesas_timer.c Yoshinori Sato
@ 2020-05-31 16:24 ` Yoshinori Sato
2020-05-31 16:45 ` [PATCH 00/10] Add RX hardware emulation Philippe Mathieu-Daudé
10 siblings, 0 replies; 17+ messages in thread
From: Yoshinori Sato @ 2020-05-31 16:24 UTC (permalink / raw)
To: qemu-devel; +Cc: Yoshinori Sato
SH4 TMU using new module. This file is obsolute.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
---
hw/timer/sh_timer.c | 341 --------------------------------------------
1 file changed, 341 deletions(-)
delete mode 100644 hw/timer/sh_timer.c
diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c
deleted file mode 100644
index 13c4051808..0000000000
--- a/hw/timer/sh_timer.c
+++ /dev/null
@@ -1,341 +0,0 @@
-/*
- * SuperH Timer modules.
- *
- * Copyright (c) 2007 Magnus Damm
- * Based on arm_timer.c by Paul Brook
- * Copyright (c) 2005-2006 CodeSourcery.
- *
- * This code is licensed under the GPL.
- */
-
-#include "qemu/osdep.h"
-#include "hw/hw.h"
-#include "hw/irq.h"
-#include "hw/sh4/sh.h"
-#include "qemu/timer.h"
-#include "hw/ptimer.h"
-
-//#define DEBUG_TIMER
-
-#define TIMER_TCR_TPSC (7 << 0)
-#define TIMER_TCR_CKEG (3 << 3)
-#define TIMER_TCR_UNIE (1 << 5)
-#define TIMER_TCR_ICPE (3 << 6)
-#define TIMER_TCR_UNF (1 << 8)
-#define TIMER_TCR_ICPF (1 << 9)
-#define TIMER_TCR_RESERVED (0x3f << 10)
-
-#define TIMER_FEAT_CAPT (1 << 0)
-#define TIMER_FEAT_EXTCLK (1 << 1)
-
-#define OFFSET_TCOR 0
-#define OFFSET_TCNT 1
-#define OFFSET_TCR 2
-#define OFFSET_TCPR 3
-
-typedef struct {
- ptimer_state *timer;
- uint32_t tcnt;
- uint32_t tcor;
- uint32_t tcr;
- uint32_t tcpr;
- int freq;
- int int_level;
- int old_level;
- int feat;
- int enabled;
- qemu_irq irq;
-} sh_timer_state;
-
-/* Check all active timers, and schedule the next timer interrupt. */
-
-static void sh_timer_update(sh_timer_state *s)
-{
- int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE);
-
- if (new_level != s->old_level)
- qemu_set_irq (s->irq, new_level);
-
- s->old_level = s->int_level;
- s->int_level = new_level;
-}
-
-static uint32_t sh_timer_read(void *opaque, hwaddr offset)
-{
- sh_timer_state *s = (sh_timer_state *)opaque;
-
- switch (offset >> 2) {
- case OFFSET_TCOR:
- return s->tcor;
- case OFFSET_TCNT:
- return ptimer_get_count(s->timer);
- case OFFSET_TCR:
- return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0);
- case OFFSET_TCPR:
- if (s->feat & TIMER_FEAT_CAPT)
- return s->tcpr;
- /* fall through */
- default:
- hw_error("sh_timer_read: Bad offset %x\n", (int)offset);
- return 0;
- }
-}
-
-static void sh_timer_write(void *opaque, hwaddr offset,
- uint32_t value)
-{
- sh_timer_state *s = (sh_timer_state *)opaque;
- int freq;
-
- switch (offset >> 2) {
- case OFFSET_TCOR:
- s->tcor = value;
- ptimer_transaction_begin(s->timer);
- ptimer_set_limit(s->timer, s->tcor, 0);
- ptimer_transaction_commit(s->timer);
- break;
- case OFFSET_TCNT:
- s->tcnt = value;
- ptimer_transaction_begin(s->timer);
- ptimer_set_count(s->timer, s->tcnt);
- ptimer_transaction_commit(s->timer);
- break;
- case OFFSET_TCR:
- ptimer_transaction_begin(s->timer);
- if (s->enabled) {
- /* Pause the timer if it is running. This may cause some
- inaccuracy dure to rounding, but avoids a whole lot of other
- messyness. */
- ptimer_stop(s->timer);
- }
- freq = s->freq;
- /* ??? Need to recalculate expiry time after changing divisor. */
- switch (value & TIMER_TCR_TPSC) {
- case 0: freq >>= 2; break;
- case 1: freq >>= 4; break;
- case 2: freq >>= 6; break;
- case 3: freq >>= 8; break;
- case 4: freq >>= 10; break;
- case 6:
- case 7: if (s->feat & TIMER_FEAT_EXTCLK) break;
- default: hw_error("sh_timer_write: Reserved TPSC value\n"); break;
- }
- switch ((value & TIMER_TCR_CKEG) >> 3) {
- case 0: break;
- case 1:
- case 2:
- case 3: if (s->feat & TIMER_FEAT_EXTCLK) break;
- default: hw_error("sh_timer_write: Reserved CKEG value\n"); break;
- }
- switch ((value & TIMER_TCR_ICPE) >> 6) {
- case 0: break;
- case 2:
- case 3: if (s->feat & TIMER_FEAT_CAPT) break;
- default: hw_error("sh_timer_write: Reserved ICPE value\n"); break;
- }
- if ((value & TIMER_TCR_UNF) == 0)
- s->int_level = 0;
-
- value &= ~TIMER_TCR_UNF;
-
- if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT)))
- hw_error("sh_timer_write: Reserved ICPF value\n");
-
- value &= ~TIMER_TCR_ICPF; /* capture not supported */
-
- if (value & TIMER_TCR_RESERVED)
- hw_error("sh_timer_write: Reserved TCR bits set\n");
- s->tcr = value;
- ptimer_set_limit(s->timer, s->tcor, 0);
- ptimer_set_freq(s->timer, freq);
- if (s->enabled) {
- /* Restart the timer if still enabled. */
- ptimer_run(s->timer, 0);
- }
- ptimer_transaction_commit(s->timer);
- break;
- case OFFSET_TCPR:
- if (s->feat & TIMER_FEAT_CAPT) {
- s->tcpr = value;
- break;
- }
- default:
- hw_error("sh_timer_write: Bad offset %x\n", (int)offset);
- }
- sh_timer_update(s);
-}
-
-static void sh_timer_start_stop(void *opaque, int enable)
-{
- sh_timer_state *s = (sh_timer_state *)opaque;
-
-#ifdef DEBUG_TIMER
- printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled);
-#endif
-
- ptimer_transaction_begin(s->timer);
- if (s->enabled && !enable) {
- ptimer_stop(s->timer);
- }
- if (!s->enabled && enable) {
- ptimer_run(s->timer, 0);
- }
- ptimer_transaction_commit(s->timer);
- s->enabled = !!enable;
-
-#ifdef DEBUG_TIMER
- printf("sh_timer_start_stop done %d\n", s->enabled);
-#endif
-}
-
-static void sh_timer_tick(void *opaque)
-{
- sh_timer_state *s = (sh_timer_state *)opaque;
- s->int_level = s->enabled;
- sh_timer_update(s);
-}
-
-static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
-{
- sh_timer_state *s;
-
- s = (sh_timer_state *)g_malloc0(sizeof(sh_timer_state));
- s->freq = freq;
- s->feat = feat;
- s->tcor = 0xffffffff;
- s->tcnt = 0xffffffff;
- s->tcpr = 0xdeadbeef;
- s->tcr = 0;
- s->enabled = 0;
- s->irq = irq;
-
- s->timer = ptimer_init(sh_timer_tick, s, PTIMER_POLICY_DEFAULT);
-
- sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor);
- sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt);
- sh_timer_write(s, OFFSET_TCPR >> 2, s->tcpr);
- sh_timer_write(s, OFFSET_TCR >> 2, s->tcpr);
- /* ??? Save/restore. */
- return s;
-}
-
-typedef struct {
- MemoryRegion iomem;
- MemoryRegion iomem_p4;
- MemoryRegion iomem_a7;
- void *timer[3];
- int level[3];
- uint32_t tocr;
- uint32_t tstr;
- int feat;
-} tmu012_state;
-
-static uint64_t tmu012_read(void *opaque, hwaddr offset,
- unsigned size)
-{
- tmu012_state *s = (tmu012_state *)opaque;
-
-#ifdef DEBUG_TIMER
- printf("tmu012_read 0x%lx\n", (unsigned long) offset);
-#endif
-
- if (offset >= 0x20) {
- if (!(s->feat & TMU012_FEAT_3CHAN))
- hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
- return sh_timer_read(s->timer[2], offset - 0x20);
- }
-
- if (offset >= 0x14)
- return sh_timer_read(s->timer[1], offset - 0x14);
-
- if (offset >= 0x08)
- return sh_timer_read(s->timer[0], offset - 0x08);
-
- if (offset == 4)
- return s->tstr;
-
- if ((s->feat & TMU012_FEAT_TOCR) && offset == 0)
- return s->tocr;
-
- hw_error("tmu012_write: Bad offset %x\n", (int)offset);
- return 0;
-}
-
-static void tmu012_write(void *opaque, hwaddr offset,
- uint64_t value, unsigned size)
-{
- tmu012_state *s = (tmu012_state *)opaque;
-
-#ifdef DEBUG_TIMER
- printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
-#endif
-
- if (offset >= 0x20) {
- if (!(s->feat & TMU012_FEAT_3CHAN))
- hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
- sh_timer_write(s->timer[2], offset - 0x20, value);
- return;
- }
-
- if (offset >= 0x14) {
- sh_timer_write(s->timer[1], offset - 0x14, value);
- return;
- }
-
- if (offset >= 0x08) {
- sh_timer_write(s->timer[0], offset - 0x08, value);
- return;
- }
-
- if (offset == 4) {
- sh_timer_start_stop(s->timer[0], value & (1 << 0));
- sh_timer_start_stop(s->timer[1], value & (1 << 1));
- if (s->feat & TMU012_FEAT_3CHAN)
- sh_timer_start_stop(s->timer[2], value & (1 << 2));
- else
- if (value & (1 << 2))
- hw_error("tmu012_write: Bad channel\n");
-
- s->tstr = value;
- return;
- }
-
- if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) {
- s->tocr = value & (1 << 0);
- }
-}
-
-static const MemoryRegionOps tmu012_ops = {
- .read = tmu012_read,
- .write = tmu012_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
-};
-
-void tmu012_init(MemoryRegion *sysmem, hwaddr base,
- int feat, uint32_t freq,
- qemu_irq ch0_irq, qemu_irq ch1_irq,
- qemu_irq ch2_irq0, qemu_irq ch2_irq1)
-{
- tmu012_state *s;
- int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;
-
- s = (tmu012_state *)g_malloc0(sizeof(tmu012_state));
- s->feat = feat;
- s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
- s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
- if (feat & TMU012_FEAT_3CHAN)
- s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
- ch2_irq0); /* ch2_irq1 not supported */
-
- memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s,
- "timer", 0x100000000ULL);
-
- memory_region_init_alias(&s->iomem_p4, NULL, "timer-p4",
- &s->iomem, 0, 0x1000);
- memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
-
- memory_region_init_alias(&s->iomem_a7, NULL, "timer-a7",
- &s->iomem, 0, 0x1000);
- memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
- /* ??? Save/restore. */
-}
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 00/10] Add RX hardware emulation
2020-05-31 16:24 [PATCH 00/10] Add RX hardware emulation Yoshinori Sato
` (9 preceding siblings ...)
2020-05-31 16:24 ` [PATCH 10/10] hw/timer: remove sh_timer.c Yoshinori Sato
@ 2020-05-31 16:45 ` Philippe Mathieu-Daudé
2020-06-01 14:32 ` Yoshinori Sato
10 siblings, 1 reply; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-05-31 16:45 UTC (permalink / raw)
To: Yoshinori Sato, qemu-devel
On 5/31/20 6:24 PM, Yoshinori Sato wrote:
> Hello.
>
> This series add to hardware emulation module for RX target.
>
> Details below.
> Interrupt controller, 8bit timer, 16bit comapare match timer and
> SCI is RX62N integrated peripheral.
> rx-virt - RX62N MCU and external RAM. It like gdb simulator.
>
> The compare match timer has a CPU interface similar to the SH4 timer.
> sh_timer will be deprecated and integrated into this module.
> SCI is also implemented in sh_serial, but the functionality is omitted.
> I implemented the complete one as renesas_sci.
>
> git repository here.
> git://git.pf.osdn.net/gitroot/y/ys/ysato/qemu.git tags/hw-rx-20200601
Sigh. It is a bit unfortunate and demotivating that we can not
coordinate this. I was going to send a pre-merge for this today.
What is positive is you unified some SH4/RX peripherals.
I'll try to merge both series. If it takes too long, I might send my
current queue for you to review, then go back to this one you just sent.
Regards,
Phil.
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 00/10] Add RX hardware emulation
2020-05-31 16:45 ` [PATCH 00/10] Add RX hardware emulation Philippe Mathieu-Daudé
@ 2020-06-01 14:32 ` Yoshinori Sato
2020-06-02 17:04 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 17+ messages in thread
From: Yoshinori Sato @ 2020-06-01 14:32 UTC (permalink / raw)
To: Philippe Mathieu-Daudé; +Cc: qemu-devel
On Mon, 01 Jun 2020 01:45:47 +0900,
Philippe Mathieu-Daudé wrote:
>
> On 5/31/20 6:24 PM, Yoshinori Sato wrote:
> > Hello.
> >
> > This series add to hardware emulation module for RX target.
> >
> > Details below.
> > Interrupt controller, 8bit timer, 16bit comapare match timer and
> > SCI is RX62N integrated peripheral.
> > rx-virt - RX62N MCU and external RAM. It like gdb simulator.
> >
> > The compare match timer has a CPU interface similar to the SH4 timer.
> > sh_timer will be deprecated and integrated into this module.
> > SCI is also implemented in sh_serial, but the functionality is omitted.
> > I implemented the complete one as renesas_sci.
> >
> > git repository here.
> > git://git.pf.osdn.net/gitroot/y/ys/ysato/qemu.git tags/hw-rx-20200601
>
> Sigh. It is a bit unfortunate and demotivating that we can not
> coordinate this. I was going to send a pre-merge for this today.
>
> What is positive is you unified some SH4/RX peripherals.
>
> I'll try to merge both series. If it takes too long, I might send my
> current queue for you to review, then go back to this one you just sent.
>
> Regards,
>
> Phil.
>
Oh. Sorry.
The old code had some spec differences.
I have fixed those mistakes here.
I would like to merge this if possible.
--
Yosinori Sato
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 00/10] Add RX hardware emulation
2020-06-01 14:32 ` Yoshinori Sato
@ 2020-06-02 17:04 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-06-02 17:04 UTC (permalink / raw)
To: Yoshinori Sato; +Cc: qemu-devel, Richard Henderson
Hi Yoshinori,
On 6/1/20 4:32 PM, Yoshinori Sato wrote:
> On Mon, 01 Jun 2020 01:45:47 +0900,
> Philippe Mathieu-Daudé wrote:
>>
>> On 5/31/20 6:24 PM, Yoshinori Sato wrote:
>>> Hello.
>>>
>>> This series add to hardware emulation module for RX target.
>>>
>>> Details below.
>>> Interrupt controller, 8bit timer, 16bit comapare match timer and
>>> SCI is RX62N integrated peripheral.
>>> rx-virt - RX62N MCU and external RAM. It like gdb simulator.
>>>
>>> The compare match timer has a CPU interface similar to the SH4 timer.
>>> sh_timer will be deprecated and integrated into this module.
>>> SCI is also implemented in sh_serial, but the functionality is omitted.
>>> I implemented the complete one as renesas_sci.
>>>
>>> git repository here.
>>> git://git.pf.osdn.net/gitroot/y/ys/ysato/qemu.git tags/hw-rx-20200601
>>
>> Sigh. It is a bit unfortunate and demotivating that we can not
>> coordinate this. I was going to send a pre-merge for this today.
>>
>> What is positive is you unified some SH4/RX peripherals.
>>
>> I'll try to merge both series. If it takes too long, I might send my
>> current queue for you to review, then go back to this one you just sent.
>>
>> Regards,
>>
>> Phil.
>>
>
> Oh. Sorry.
>
> The old code had some spec differences.
> I have fixed those mistakes here.
Yes, I am glad to see how it evolved, in particular how you merged the
SH4/RX common peripherals :)
>
> I would like to merge this if possible.
I posted the v33 of your v32:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg708317.html
As it is mostly reviewed and tested, it seems more reasonable to merge
what is reviewed, and then apply your latest patches on top. It took us
already a long time to get there, and I'd not start again to review 30
more times this version.
I believe if would be easier this way, you review/ack the v33 and we get
the peripheral cleanup on top. My 2 cents, feel free to disagree and
insist on restarting the whole review process.
Regards,
Phil.
^ permalink raw reply [flat|nested] 17+ messages in thread