* [PATCH] drm/i915/ehl: Inherit Ice Lake conditional code
@ 2019-04-12 18:09 Rodrigo Vivi
2019-04-12 18:48 ` ✓ Fi.CI.BAT: success for drm/i915/ehl: Inherit Ice Lake conditional code (rev2) Patchwork
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Rodrigo Vivi @ 2019-04-12 18:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Bob Paauwe <bob.j.paauwe@intel.com>
Most of the conditional code for ICELAKE also applies to ELKHARTLAKE
so use IS_GEN(dev_priv, 11) even for PM and Workarounds for now.
v2: - Rename commit (Jose)
- Include a wm workaround (Jose and Lucas)
- Include display core init (Jose and Lucas)
v3: Add a missing case of gen greater-than 11 (Jose)
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 6 +++---
drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++----
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8e826a6ab62e..7357bddf9ad9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4530,10 +4530,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
/*
- * Wa_1408961008:icl
+ * Wa_1408961008:icl, ehl
* Underruns with WM1+ disabled
*/
- if (IS_ICELAKE(dev_priv) &&
+ if (IS_GEN(dev_priv, 11) &&
level == 1 && wm->wm[0].plane_en) {
wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
@@ -9573,7 +9573,7 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
*/
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_ICELAKE(dev_priv))
+ if (IS_GEN(dev_priv, 11))
dev_priv->display.init_clock_gating = icl_init_clock_gating;
else if (IS_CANNONLAKE(dev_priv))
dev_priv->display.init_clock_gating = cnl_init_clock_gating;
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 3107a742d8ad..d4f4262d0fee 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3448,7 +3448,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
* The enabling order will be from lower to higher indexed wells,
* the disabling order is reversed.
*/
- if (IS_ICELAKE(dev_priv)) {
+ if (IS_GEN(dev_priv, 11)) {
err = set_power_wells(power_domains, icl_power_wells);
} else if (IS_CANNONLAKE(dev_priv)) {
err = set_power_wells(power_domains, cnl_power_wells);
@@ -4061,7 +4061,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
power_domains->initializing = true;
- if (IS_ICELAKE(i915)) {
+ if (INTEL_GEN(i915) >= 11) {
icl_display_core_init(i915, resume);
} else if (IS_CANNONLAKE(i915)) {
cnl_display_core_init(i915, resume);
@@ -4209,7 +4209,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
intel_power_domains_verify_state(i915);
}
- if (IS_ICELAKE(i915))
+ if (INTEL_GEN(i915) >= 11)
icl_display_core_uninit(i915);
else if (IS_CANNONLAKE(i915))
cnl_display_core_uninit(i915);
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index a04dbc58ec1c..c0977036db79 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -569,7 +569,7 @@ void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
wa_init_start(wal, "context");
- if (IS_ICELAKE(i915))
+ if (IS_GEN(i915, 11))
icl_ctx_workarounds_init(engine);
else if (IS_CANNONLAKE(i915))
cnl_ctx_workarounds_init(engine);
@@ -867,7 +867,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
static void
gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- if (IS_ICELAKE(i915))
+ if (IS_GEN(i915, 11))
icl_gt_workarounds_init(i915, wal);
else if (IS_CANNONLAKE(i915))
cnl_gt_workarounds_init(i915, wal);
@@ -1064,7 +1064,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
wa_init_start(w, "whitelist");
- if (IS_ICELAKE(i915))
+ if (IS_GEN(i915, 11))
icl_whitelist_build(w);
else if (IS_CANNONLAKE(i915))
cnl_whitelist_build(w);
@@ -1112,7 +1112,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
- if (IS_ICELAKE(i915)) {
+ if (IS_GEN(i915, 11)) {
/* This is not an Wa. Enable for better image quality */
wa_masked_en(wal,
_3D_CHICKEN3,
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/ehl: Inherit Ice Lake conditional code (rev2)
2019-04-12 18:09 [PATCH] drm/i915/ehl: Inherit Ice Lake conditional code Rodrigo Vivi
@ 2019-04-12 18:48 ` Patchwork
2019-04-12 19:27 ` [PATCH] drm/i915/ehl: Inherit Ice Lake conditional code Souza, Jose
2019-04-12 21:47 ` ✓ Fi.CI.IGT: success for drm/i915/ehl: Inherit Ice Lake conditional code (rev2) Patchwork
2 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2019-04-12 18:48 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/ehl: Inherit Ice Lake conditional code (rev2)
URL : https://patchwork.freedesktop.org/series/59364/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5923 -> Patchwork_12783
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/59364/revisions/2/mbox/
Known issues
------------
Here are the changes found in Patchwork_12783 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@fork-compute0:
- fi-icl-y: NOTRUN -> SKIP [fdo#109315] +17
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109315] +17
* igt@gem_exec_basic@basic-bsd2:
- fi-icl-y: NOTRUN -> SKIP [fdo#109276] +7
* igt@gem_exec_basic@gtt-bsd1:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109276] +7
* igt@gem_exec_parse@basic-rejected:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109289] +1
- fi-icl-y: NOTRUN -> SKIP [fdo#109289] +1
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]
* igt@i915_selftest@live_hangcheck:
- fi-skl-iommu: PASS -> INCOMPLETE [fdo#108602] / [fdo#108744]
* igt@kms_busy@basic-flip-c:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@dp-crc-fast:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +43
- fi-icl-y: NOTRUN -> SKIP [fdo#109284] +8
* igt@kms_chamelium@hdmi-edid-read:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109284] +8
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-y: NOTRUN -> SKIP [fdo#109285] +3
* igt@kms_force_connector_basic@prune-stale-modes:
- fi-icl-u3: NOTRUN -> SKIP [fdo#109285] +3
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] +1
* igt@kms_psr@primary_mmap_gtt:
- fi-icl-y: NOTRUN -> SKIP [fdo#110189] +3
* igt@prime_vgem@basic-fence-flip:
- fi-icl-y: NOTRUN -> SKIP [fdo#109294]
* igt@runner@aborted:
- fi-skl-iommu: NOTRUN -> FAIL [fdo#104108] / [fdo#108602]
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720]
#### Possible fixes ####
* igt@gem_exec_basic@basic-blt:
- fi-icl-y: INCOMPLETE [fdo#110246] -> PASS
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
* igt@i915_selftest@live_contexts:
- fi-bdw-gvtdvm: DMESG-FAIL [fdo#110235 ] -> PASS
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: FAIL [fdo#103167] -> PASS
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
[fdo#110246]: https://bugs.freedesktop.org/show_bug.cgi?id=110246
Participating hosts (48 -> 43)
------------------------------
Additional (1): fi-icl-u3
Missing (6): fi-kbl-soraka fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus fi-skl-6700k2
Build changes
-------------
* Linux: CI_DRM_5923 -> Patchwork_12783
CI_DRM_5923: 8f69ca66d43ef57be72394ba23c2ff1718d94164 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4945: a52cc643cfe6733465cfc9ccb3d21cbdc4fd7506 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12783: 846746eebfa49b5311b8bd1dc465217e6b941160 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
846746eebfa4 drm/i915/ehl: Inherit Ice Lake conditional code
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12783/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/ehl: Inherit Ice Lake conditional code
2019-04-12 18:09 [PATCH] drm/i915/ehl: Inherit Ice Lake conditional code Rodrigo Vivi
2019-04-12 18:48 ` ✓ Fi.CI.BAT: success for drm/i915/ehl: Inherit Ice Lake conditional code (rev2) Patchwork
@ 2019-04-12 19:27 ` Souza, Jose
2019-04-12 22:18 ` Rodrigo Vivi
2019-04-12 21:47 ` ✓ Fi.CI.IGT: success for drm/i915/ehl: Inherit Ice Lake conditional code (rev2) Patchwork
2 siblings, 1 reply; 9+ messages in thread
From: Souza, Jose @ 2019-04-12 19:27 UTC (permalink / raw)
To: Vivi, Rodrigo, intel-gfx; +Cc: De Marchi, Lucas
[-- Attachment #1.1: Type: text/plain, Size: 5047 bytes --]
On Fri, 2019-04-12 at 11:09 -0700, Rodrigo Vivi wrote:
> From: Bob Paauwe <bob.j.paauwe@intel.com>
>
> Most of the conditional code for ICELAKE also applies to ELKHARTLAKE
> so use IS_GEN(dev_priv, 11) even for PM and Workarounds for now.
>
> v2: - Rename commit (Jose)
> - Include a wm workaround (Jose and Lucas)
> - Include display core init (Jose and Lucas)
> v3: Add a missing case of gen greater-than 11 (Jose)
This is shining now
>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 6 +++---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
> drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++----
> 3 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 8e826a6ab62e..7357bddf9ad9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4530,10 +4530,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> *cstate,
> memset(&wm->wm[level], 0, sizeof(wm-
> >wm[level]));
>
> /*
> - * Wa_1408961008:icl
> + * Wa_1408961008:icl, ehl
> * Underruns with WM1+ disabled
> */
> - if (IS_ICELAKE(dev_priv) &&
> + if (IS_GEN(dev_priv, 11) &&
> level == 1 && wm->wm[0].plane_en) {
> wm->wm[level].plane_res_b = wm-
> >wm[0].plane_res_b;
> wm->wm[level].plane_res_l = wm-
> >wm[0].plane_res_l;
> @@ -9573,7 +9573,7 @@ static void nop_init_clock_gating(struct
> drm_i915_private *dev_priv)
> */
> void intel_init_clock_gating_hooks(struct drm_i915_private
> *dev_priv)
> {
> - if (IS_ICELAKE(dev_priv))
> + if (IS_GEN(dev_priv, 11))
> dev_priv->display.init_clock_gating =
> icl_init_clock_gating;
> else if (IS_CANNONLAKE(dev_priv))
> dev_priv->display.init_clock_gating =
> cnl_init_clock_gating;
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 3107a742d8ad..d4f4262d0fee 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -3448,7 +3448,7 @@ int intel_power_domains_init(struct
> drm_i915_private *dev_priv)
> * The enabling order will be from lower to higher indexed
> wells,
> * the disabling order is reversed.
> */
> - if (IS_ICELAKE(dev_priv)) {
> + if (IS_GEN(dev_priv, 11)) {
> err = set_power_wells(power_domains, icl_power_wells);
> } else if (IS_CANNONLAKE(dev_priv)) {
> err = set_power_wells(power_domains, cnl_power_wells);
> @@ -4061,7 +4061,7 @@ void intel_power_domains_init_hw(struct
> drm_i915_private *i915, bool resume)
>
> power_domains->initializing = true;
>
> - if (IS_ICELAKE(i915)) {
> + if (INTEL_GEN(i915) >= 11) {
> icl_display_core_init(i915, resume);
> } else if (IS_CANNONLAKE(i915)) {
> cnl_display_core_init(i915, resume);
> @@ -4209,7 +4209,7 @@ void intel_power_domains_suspend(struct
> drm_i915_private *i915,
> intel_power_domains_verify_state(i915);
> }
>
> - if (IS_ICELAKE(i915))
> + if (INTEL_GEN(i915) >= 11)
> icl_display_core_uninit(i915);
> else if (IS_CANNONLAKE(i915))
> cnl_display_core_uninit(i915);
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
> b/drivers/gpu/drm/i915/intel_workarounds.c
> index a04dbc58ec1c..c0977036db79 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -569,7 +569,7 @@ void intel_engine_init_ctx_wa(struct
> intel_engine_cs *engine)
>
> wa_init_start(wal, "context");
>
> - if (IS_ICELAKE(i915))
> + if (IS_GEN(i915, 11))
> icl_ctx_workarounds_init(engine);
> else if (IS_CANNONLAKE(i915))
> cnl_ctx_workarounds_init(engine);
> @@ -867,7 +867,7 @@ icl_gt_workarounds_init(struct drm_i915_private
> *i915, struct i915_wa_list *wal)
> static void
> gt_init_workarounds(struct drm_i915_private *i915, struct
> i915_wa_list *wal)
> {
> - if (IS_ICELAKE(i915))
> + if (IS_GEN(i915, 11))
> icl_gt_workarounds_init(i915, wal);
> else if (IS_CANNONLAKE(i915))
> cnl_gt_workarounds_init(i915, wal);
> @@ -1064,7 +1064,7 @@ void intel_engine_init_whitelist(struct
> intel_engine_cs *engine)
>
> wa_init_start(w, "whitelist");
>
> - if (IS_ICELAKE(i915))
> + if (IS_GEN(i915, 11))
> icl_whitelist_build(w);
> else if (IS_CANNONLAKE(i915))
> cnl_whitelist_build(w);
> @@ -1112,7 +1112,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_list *wal)
> {
> struct drm_i915_private *i915 = engine->i915;
>
> - if (IS_ICELAKE(i915)) {
> + if (IS_GEN(i915, 11)) {
> /* This is not an Wa. Enable for better image quality
> */
> wa_masked_en(wal,
> _3D_CHICKEN3,
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/ehl: Inherit Ice Lake conditional code
2019-04-12 19:27 ` [PATCH] drm/i915/ehl: Inherit Ice Lake conditional code Souza, Jose
@ 2019-04-12 22:18 ` Rodrigo Vivi
0 siblings, 0 replies; 9+ messages in thread
From: Rodrigo Vivi @ 2019-04-12 22:18 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx, De Marchi, Lucas
On Fri, Apr 12, 2019 at 12:27:46PM -0700, Souza, Jose wrote:
> On Fri, 2019-04-12 at 11:09 -0700, Rodrigo Vivi wrote:
> > From: Bob Paauwe <bob.j.paauwe@intel.com>
> >
> > Most of the conditional code for ICELAKE also applies to ELKHARTLAKE
> > so use IS_GEN(dev_priv, 11) even for PM and Workarounds for now.
> >
> > v2: - Rename commit (Jose)
> > - Include a wm workaround (Jose and Lucas)
> > - Include display core init (Jose and Lucas)
> > v3: Add a missing case of gen greater-than 11 (Jose)
>
> This is shining now
pushed, thanks
>
> >
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 6 +++---
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
> > drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++----
> > 3 files changed, 10 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 8e826a6ab62e..7357bddf9ad9 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4530,10 +4530,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> > *cstate,
> > memset(&wm->wm[level], 0, sizeof(wm-
> > >wm[level]));
> >
> > /*
> > - * Wa_1408961008:icl
> > + * Wa_1408961008:icl, ehl
> > * Underruns with WM1+ disabled
> > */
> > - if (IS_ICELAKE(dev_priv) &&
> > + if (IS_GEN(dev_priv, 11) &&
> > level == 1 && wm->wm[0].plane_en) {
> > wm->wm[level].plane_res_b = wm-
> > >wm[0].plane_res_b;
> > wm->wm[level].plane_res_l = wm-
> > >wm[0].plane_res_l;
> > @@ -9573,7 +9573,7 @@ static void nop_init_clock_gating(struct
> > drm_i915_private *dev_priv)
> > */
> > void intel_init_clock_gating_hooks(struct drm_i915_private
> > *dev_priv)
> > {
> > - if (IS_ICELAKE(dev_priv))
> > + if (IS_GEN(dev_priv, 11))
> > dev_priv->display.init_clock_gating =
> > icl_init_clock_gating;
> > else if (IS_CANNONLAKE(dev_priv))
> > dev_priv->display.init_clock_gating =
> > cnl_init_clock_gating;
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 3107a742d8ad..d4f4262d0fee 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -3448,7 +3448,7 @@ int intel_power_domains_init(struct
> > drm_i915_private *dev_priv)
> > * The enabling order will be from lower to higher indexed
> > wells,
> > * the disabling order is reversed.
> > */
> > - if (IS_ICELAKE(dev_priv)) {
> > + if (IS_GEN(dev_priv, 11)) {
> > err = set_power_wells(power_domains, icl_power_wells);
> > } else if (IS_CANNONLAKE(dev_priv)) {
> > err = set_power_wells(power_domains, cnl_power_wells);
> > @@ -4061,7 +4061,7 @@ void intel_power_domains_init_hw(struct
> > drm_i915_private *i915, bool resume)
> >
> > power_domains->initializing = true;
> >
> > - if (IS_ICELAKE(i915)) {
> > + if (INTEL_GEN(i915) >= 11) {
> > icl_display_core_init(i915, resume);
> > } else if (IS_CANNONLAKE(i915)) {
> > cnl_display_core_init(i915, resume);
> > @@ -4209,7 +4209,7 @@ void intel_power_domains_suspend(struct
> > drm_i915_private *i915,
> > intel_power_domains_verify_state(i915);
> > }
> >
> > - if (IS_ICELAKE(i915))
> > + if (INTEL_GEN(i915) >= 11)
> > icl_display_core_uninit(i915);
> > else if (IS_CANNONLAKE(i915))
> > cnl_display_core_uninit(i915);
> > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
> > b/drivers/gpu/drm/i915/intel_workarounds.c
> > index a04dbc58ec1c..c0977036db79 100644
> > --- a/drivers/gpu/drm/i915/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> > @@ -569,7 +569,7 @@ void intel_engine_init_ctx_wa(struct
> > intel_engine_cs *engine)
> >
> > wa_init_start(wal, "context");
> >
> > - if (IS_ICELAKE(i915))
> > + if (IS_GEN(i915, 11))
> > icl_ctx_workarounds_init(engine);
> > else if (IS_CANNONLAKE(i915))
> > cnl_ctx_workarounds_init(engine);
> > @@ -867,7 +867,7 @@ icl_gt_workarounds_init(struct drm_i915_private
> > *i915, struct i915_wa_list *wal)
> > static void
> > gt_init_workarounds(struct drm_i915_private *i915, struct
> > i915_wa_list *wal)
> > {
> > - if (IS_ICELAKE(i915))
> > + if (IS_GEN(i915, 11))
> > icl_gt_workarounds_init(i915, wal);
> > else if (IS_CANNONLAKE(i915))
> > cnl_gt_workarounds_init(i915, wal);
> > @@ -1064,7 +1064,7 @@ void intel_engine_init_whitelist(struct
> > intel_engine_cs *engine)
> >
> > wa_init_start(w, "whitelist");
> >
> > - if (IS_ICELAKE(i915))
> > + if (IS_GEN(i915, 11))
> > icl_whitelist_build(w);
> > else if (IS_CANNONLAKE(i915))
> > cnl_whitelist_build(w);
> > @@ -1112,7 +1112,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> > *engine, struct i915_wa_list *wal)
> > {
> > struct drm_i915_private *i915 = engine->i915;
> >
> > - if (IS_ICELAKE(i915)) {
> > + if (IS_GEN(i915, 11)) {
> > /* This is not an Wa. Enable for better image quality
> > */
> > wa_masked_en(wal,
> > _3D_CHICKEN3,
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/ehl: Inherit Ice Lake conditional code (rev2)
2019-04-12 18:09 [PATCH] drm/i915/ehl: Inherit Ice Lake conditional code Rodrigo Vivi
2019-04-12 18:48 ` ✓ Fi.CI.BAT: success for drm/i915/ehl: Inherit Ice Lake conditional code (rev2) Patchwork
2019-04-12 19:27 ` [PATCH] drm/i915/ehl: Inherit Ice Lake conditional code Souza, Jose
@ 2019-04-12 21:47 ` Patchwork
2 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2019-04-12 21:47 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/ehl: Inherit Ice Lake conditional code (rev2)
URL : https://patchwork.freedesktop.org/series/59364/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5923_full -> Patchwork_12783_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_12783_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_tiled_swapping@non-threaded:
- shard-iclb: PASS -> DMESG-WARN [fdo#108686]
* igt@i915_pm_rpm@gem-mmap-gtt:
- shard-skl: PASS -> INCOMPLETE [fdo#107807] +1
* igt@kms_fbcon_fbt@fbc:
- shard-iclb: PASS -> DMESG-WARN [fdo#109593]
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: NOTRUN -> FAIL [fdo#103833]
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: PASS -> DMESG-WARN [fdo#108566] +2
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +141
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- shard-iclb: PASS -> FAIL [fdo#103167] +5
- shard-skl: NOTRUN -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff:
- shard-iclb: PASS -> FAIL [fdo#109247] +12
* igt@kms_lease@cursor_implicit_plane:
- shard-skl: NOTRUN -> FAIL [fdo#110278]
* igt@kms_lease@page_flip_implicit_plane:
- shard-skl: NOTRUN -> FAIL [fdo#110281]
* igt@kms_panel_fitting@legacy:
- shard-skl: NOTRUN -> FAIL [fdo#105456]
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: PASS -> FAIL [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +5
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: PASS -> FAIL [fdo#103166]
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: PASS -> SKIP [fdo#109441] +1
* igt@kms_psr@sprite_blt:
- shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215] +1
* igt@kms_sysfs_edid_timing:
- shard-skl: NOTRUN -> FAIL [fdo#100047]
* igt@kms_universal_plane@disable-primary-vs-flip-pipe-f:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +15
* igt@runner@aborted:
- shard-iclb: NOTRUN -> FAIL [fdo#109593]
#### Possible fixes ####
* igt@gem_softpin@noreloc-s3:
- shard-kbl: DMESG-WARN [fdo#103313] -> PASS
* igt@i915_pm_rpm@universal-planes:
- shard-skl: INCOMPLETE [fdo#107807] -> PASS
* igt@i915_suspend@sysfs-reader:
- shard-apl: DMESG-WARN [fdo#108566] -> PASS +4
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: SKIP [fdo#109349] -> PASS
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: FAIL [fdo#105363] -> PASS +1
- shard-glk: FAIL [fdo#105363] -> PASS
* igt@kms_flip@flip-vs-suspend:
- shard-skl: INCOMPLETE [fdo#109507] -> PASS
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt:
- shard-iclb: FAIL [fdo#109247] -> PASS +12
* igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
- shard-iclb: FAIL [fdo#103167] -> PASS +2
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: FAIL [fdo#108145] -> PASS
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: FAIL [fdo#110403] -> PASS
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: FAIL [fdo#103166] -> PASS
* igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format:
- shard-glk: SKIP [fdo#109271] / [fdo#109278] -> PASS +1
* igt@kms_psr2_su@page_flip:
- shard-iclb: SKIP [fdo#109642] -> PASS
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: SKIP [fdo#109441] -> PASS +1
* igt@kms_psr@suspend:
- shard-skl: INCOMPLETE [fdo#107773] -> PASS
- shard-iclb: FAIL [fdo#107383] / [fdo#110215] -> PASS
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: DMESG-FAIL [fdo#105763] -> PASS
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: FAIL [fdo#109016] -> PASS
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
* igt@tools_test@tools_test:
- shard-snb: SKIP [fdo#109271] -> PASS
#### Warnings ####
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-skl: INCOMPLETE [fdo#107807] -> SKIP [fdo#109271]
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
[fdo#103833]: https://bugs.freedesktop.org/show_bug.cgi?id=103833
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105456]: https://bugs.freedesktop.org/show_bug.cgi?id=105456
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
[fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#109593]: https://bugs.freedesktop.org/show_bug.cgi?id=109593
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110215]: https://bugs.freedesktop.org/show_bug.cgi?id=110215
[fdo#110278]: https://bugs.freedesktop.org/show_bug.cgi?id=110278
[fdo#110281]: https://bugs.freedesktop.org/show_bug.cgi?id=110281
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 9)
------------------------------
Missing (1): shard-hsw
Build changes
-------------
* Linux: CI_DRM_5923 -> Patchwork_12783
CI_DRM_5923: 8f69ca66d43ef57be72394ba23c2ff1718d94164 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4945: a52cc643cfe6733465cfc9ccb3d21cbdc4fd7506 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12783: 846746eebfa49b5311b8bd1dc465217e6b941160 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12783/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH] drm/i915/ehl: Inherit Ice Lake conditional code
@ 2019-04-11 23:08 Rodrigo Vivi
2019-04-11 23:16 ` Souza, Jose
0 siblings, 1 reply; 9+ messages in thread
From: Rodrigo Vivi @ 2019-04-11 23:08 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Bob Paauwe <bob.j.paauwe@intel.com>
Most of the conditional code for ICELAKE also applies to ELKHARTLAKE
so use IS_GEN(dev_priv, 11) even for PM and Workarounds for now.
v2: - Rename commit (Jose)
- Include a wm workaround (Jose and Lucas)
- Include display core init (Jose and Lucas)
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 6 +++---
drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++----
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8e826a6ab62e..7357bddf9ad9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4530,10 +4530,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
/*
- * Wa_1408961008:icl
+ * Wa_1408961008:icl, ehl
* Underruns with WM1+ disabled
*/
- if (IS_ICELAKE(dev_priv) &&
+ if (IS_GEN(dev_priv, 11) &&
level == 1 && wm->wm[0].plane_en) {
wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
@@ -9573,7 +9573,7 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
*/
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_ICELAKE(dev_priv))
+ if (IS_GEN(dev_priv, 11))
dev_priv->display.init_clock_gating = icl_init_clock_gating;
else if (IS_CANNONLAKE(dev_priv))
dev_priv->display.init_clock_gating = cnl_init_clock_gating;
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 3107a742d8ad..fcd388e8978b 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3448,7 +3448,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
* The enabling order will be from lower to higher indexed wells,
* the disabling order is reversed.
*/
- if (IS_ICELAKE(dev_priv)) {
+ if (IS_GEN(dev_priv, 11)) {
err = set_power_wells(power_domains, icl_power_wells);
} else if (IS_CANNONLAKE(dev_priv)) {
err = set_power_wells(power_domains, cnl_power_wells);
@@ -4061,7 +4061,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
power_domains->initializing = true;
- if (IS_ICELAKE(i915)) {
+ if (INTEL_GEN(i915) >= 11) {
icl_display_core_init(i915, resume);
} else if (IS_CANNONLAKE(i915)) {
cnl_display_core_init(i915, resume);
@@ -4209,7 +4209,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
intel_power_domains_verify_state(i915);
}
- if (IS_ICELAKE(i915))
+ if (IS_GEN(i915, 11))
icl_display_core_uninit(i915);
else if (IS_CANNONLAKE(i915))
cnl_display_core_uninit(i915);
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index a04dbc58ec1c..c0977036db79 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -569,7 +569,7 @@ void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
wa_init_start(wal, "context");
- if (IS_ICELAKE(i915))
+ if (IS_GEN(i915, 11))
icl_ctx_workarounds_init(engine);
else if (IS_CANNONLAKE(i915))
cnl_ctx_workarounds_init(engine);
@@ -867,7 +867,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
static void
gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
{
- if (IS_ICELAKE(i915))
+ if (IS_GEN(i915, 11))
icl_gt_workarounds_init(i915, wal);
else if (IS_CANNONLAKE(i915))
cnl_gt_workarounds_init(i915, wal);
@@ -1064,7 +1064,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
wa_init_start(w, "whitelist");
- if (IS_ICELAKE(i915))
+ if (IS_GEN(i915, 11))
icl_whitelist_build(w);
else if (IS_CANNONLAKE(i915))
cnl_whitelist_build(w);
@@ -1112,7 +1112,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
- if (IS_ICELAKE(i915)) {
+ if (IS_GEN(i915, 11)) {
/* This is not an Wa. Enable for better image quality */
wa_masked_en(wal,
_3D_CHICKEN3,
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/ehl: Inherit Ice Lake conditional code
2019-04-11 23:08 [PATCH] drm/i915/ehl: Inherit Ice Lake conditional code Rodrigo Vivi
@ 2019-04-11 23:16 ` Souza, Jose
2019-04-11 23:51 ` Rodrigo Vivi
0 siblings, 1 reply; 9+ messages in thread
From: Souza, Jose @ 2019-04-11 23:16 UTC (permalink / raw)
To: Vivi, Rodrigo, intel-gfx; +Cc: De Marchi, Lucas
[-- Attachment #1.1: Type: text/plain, Size: 5041 bytes --]
On Thu, 2019-04-11 at 16:08 -0700, Rodrigo Vivi wrote:
> From: Bob Paauwe <bob.j.paauwe@intel.com>
>
> Most of the conditional code for ICELAKE also applies to ELKHARTLAKE
> so use IS_GEN(dev_priv, 11) even for PM and Workarounds for now.
>
> v2: - Rename commit (Jose)
> - Include a wm workaround (Jose and Lucas)
> - Include display core init (Jose and Lucas)
>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 6 +++---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
> drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++----
> 3 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 8e826a6ab62e..7357bddf9ad9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4530,10 +4530,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> *cstate,
> memset(&wm->wm[level], 0, sizeof(wm-
> >wm[level]));
>
> /*
> - * Wa_1408961008:icl
> + * Wa_1408961008:icl, ehl
> * Underruns with WM1+ disabled
> */
> - if (IS_ICELAKE(dev_priv) &&
> + if (IS_GEN(dev_priv, 11) &&
> level == 1 && wm->wm[0].plane_en) {
> wm->wm[level].plane_res_b = wm-
> >wm[0].plane_res_b;
> wm->wm[level].plane_res_l = wm-
> >wm[0].plane_res_l;
> @@ -9573,7 +9573,7 @@ static void nop_init_clock_gating(struct
> drm_i915_private *dev_priv)
> */
> void intel_init_clock_gating_hooks(struct drm_i915_private
> *dev_priv)
> {
> - if (IS_ICELAKE(dev_priv))
> + if (IS_GEN(dev_priv, 11))
> dev_priv->display.init_clock_gating =
> icl_init_clock_gating;
> else if (IS_CANNONLAKE(dev_priv))
> dev_priv->display.init_clock_gating =
> cnl_init_clock_gating;
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 3107a742d8ad..fcd388e8978b 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -3448,7 +3448,7 @@ int intel_power_domains_init(struct
> drm_i915_private *dev_priv)
> * The enabling order will be from lower to higher indexed
> wells,
> * the disabling order is reversed.
> */
> - if (IS_ICELAKE(dev_priv)) {
> + if (IS_GEN(dev_priv, 11)) {
> err = set_power_wells(power_domains, icl_power_wells);
> } else if (IS_CANNONLAKE(dev_priv)) {
> err = set_power_wells(power_domains, cnl_power_wells);
> @@ -4061,7 +4061,7 @@ void intel_power_domains_init_hw(struct
> drm_i915_private *i915, bool resume)
>
> power_domains->initializing = true;
>
> - if (IS_ICELAKE(i915)) {
> + if (INTEL_GEN(i915) >= 11) {
> icl_display_core_init(i915, resume);
> } else if (IS_CANNONLAKE(i915)) {
> cnl_display_core_init(i915, resume);
> @@ -4209,7 +4209,7 @@ void intel_power_domains_suspend(struct
> drm_i915_private *i915,
> intel_power_domains_verify_state(i915);
> }
>
> - if (IS_ICELAKE(i915))
> + if (IS_GEN(i915, 11))
To be consistent with init: if (INTEL_GEN(i915) >= 11)
Other than that:
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> icl_display_core_uninit(i915);
> else if (IS_CANNONLAKE(i915))
> cnl_display_core_uninit(i915);
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
> b/drivers/gpu/drm/i915/intel_workarounds.c
> index a04dbc58ec1c..c0977036db79 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -569,7 +569,7 @@ void intel_engine_init_ctx_wa(struct
> intel_engine_cs *engine)
>
> wa_init_start(wal, "context");
>
> - if (IS_ICELAKE(i915))
> + if (IS_GEN(i915, 11))
> icl_ctx_workarounds_init(engine);
> else if (IS_CANNONLAKE(i915))
> cnl_ctx_workarounds_init(engine);
> @@ -867,7 +867,7 @@ icl_gt_workarounds_init(struct drm_i915_private
> *i915, struct i915_wa_list *wal)
> static void
> gt_init_workarounds(struct drm_i915_private *i915, struct
> i915_wa_list *wal)
> {
> - if (IS_ICELAKE(i915))
> + if (IS_GEN(i915, 11))
> icl_gt_workarounds_init(i915, wal);
> else if (IS_CANNONLAKE(i915))
> cnl_gt_workarounds_init(i915, wal);
> @@ -1064,7 +1064,7 @@ void intel_engine_init_whitelist(struct
> intel_engine_cs *engine)
>
> wa_init_start(w, "whitelist");
>
> - if (IS_ICELAKE(i915))
> + if (IS_GEN(i915, 11))
> icl_whitelist_build(w);
> else if (IS_CANNONLAKE(i915))
> cnl_whitelist_build(w);
> @@ -1112,7 +1112,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_list *wal)
> {
> struct drm_i915_private *i915 = engine->i915;
>
> - if (IS_ICELAKE(i915)) {
> + if (IS_GEN(i915, 11)) {
> /* This is not an Wa. Enable for better image quality
> */
> wa_masked_en(wal,
> _3D_CHICKEN3,
[-- Attachment #1.2: This is a digitally signed message part --]
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[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/ehl: Inherit Ice Lake conditional code
2019-04-11 23:16 ` Souza, Jose
@ 2019-04-11 23:51 ` Rodrigo Vivi
2019-04-12 14:32 ` Souza, Jose
0 siblings, 1 reply; 9+ messages in thread
From: Rodrigo Vivi @ 2019-04-11 23:51 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx, De Marchi, Lucas
On Thu, Apr 11, 2019 at 04:16:41PM -0700, Souza, Jose wrote:
> On Thu, 2019-04-11 at 16:08 -0700, Rodrigo Vivi wrote:
> > From: Bob Paauwe <bob.j.paauwe@intel.com>
> >
> > Most of the conditional code for ICELAKE also applies to ELKHARTLAKE
> > so use IS_GEN(dev_priv, 11) even for PM and Workarounds for now.
> >
> > v2: - Rename commit (Jose)
> > - Include a wm workaround (Jose and Lucas)
> > - Include display core init (Jose and Lucas)
> >
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 6 +++---
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
> > drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++----
> > 3 files changed, 10 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 8e826a6ab62e..7357bddf9ad9 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4530,10 +4530,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> > *cstate,
> > memset(&wm->wm[level], 0, sizeof(wm-
> > >wm[level]));
> >
> > /*
> > - * Wa_1408961008:icl
> > + * Wa_1408961008:icl, ehl
> > * Underruns with WM1+ disabled
> > */
> > - if (IS_ICELAKE(dev_priv) &&
> > + if (IS_GEN(dev_priv, 11) &&
> > level == 1 && wm->wm[0].plane_en) {
> > wm->wm[level].plane_res_b = wm-
> > >wm[0].plane_res_b;
> > wm->wm[level].plane_res_l = wm-
> > >wm[0].plane_res_l;
> > @@ -9573,7 +9573,7 @@ static void nop_init_clock_gating(struct
> > drm_i915_private *dev_priv)
> > */
> > void intel_init_clock_gating_hooks(struct drm_i915_private
> > *dev_priv)
> > {
> > - if (IS_ICELAKE(dev_priv))
> > + if (IS_GEN(dev_priv, 11))
> > dev_priv->display.init_clock_gating =
> > icl_init_clock_gating;
> > else if (IS_CANNONLAKE(dev_priv))
> > dev_priv->display.init_clock_gating =
> > cnl_init_clock_gating;
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 3107a742d8ad..fcd388e8978b 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -3448,7 +3448,7 @@ int intel_power_domains_init(struct
> > drm_i915_private *dev_priv)
> > * The enabling order will be from lower to higher indexed
> > wells,
> > * the disabling order is reversed.
> > */
> > - if (IS_ICELAKE(dev_priv)) {
> > + if (IS_GEN(dev_priv, 11)) {
> > err = set_power_wells(power_domains, icl_power_wells);
> > } else if (IS_CANNONLAKE(dev_priv)) {
> > err = set_power_wells(power_domains, cnl_power_wells);
> > @@ -4061,7 +4061,7 @@ void intel_power_domains_init_hw(struct
> > drm_i915_private *i915, bool resume)
> >
> > power_domains->initializing = true;
> >
> > - if (IS_ICELAKE(i915)) {
> > + if (INTEL_GEN(i915) >= 11) {
> > icl_display_core_init(i915, resume);
> > } else if (IS_CANNONLAKE(i915)) {
> > cnl_display_core_init(i915, resume);
> > @@ -4209,7 +4209,7 @@ void intel_power_domains_suspend(struct
> > drm_i915_private *i915,
> > intel_power_domains_verify_state(i915);
> > }
> >
> > - if (IS_ICELAKE(i915))
> > + if (IS_GEN(i915, 11))
>
> To be consistent with init: if (INTEL_GEN(i915) >= 11)
hmmm... I tried to keep power well stuff not using this
greater-than behaviour on purpose... Because so far all
platforms had different wells, besides gen9_bc group of course...
But even display_10 glk and cnl are different on display wells :/
>
> Other than that:
>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> > icl_display_core_uninit(i915);
> > else if (IS_CANNONLAKE(i915))
> > cnl_display_core_uninit(i915);
> > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
> > b/drivers/gpu/drm/i915/intel_workarounds.c
> > index a04dbc58ec1c..c0977036db79 100644
> > --- a/drivers/gpu/drm/i915/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> > @@ -569,7 +569,7 @@ void intel_engine_init_ctx_wa(struct
> > intel_engine_cs *engine)
> >
> > wa_init_start(wal, "context");
> >
> > - if (IS_ICELAKE(i915))
> > + if (IS_GEN(i915, 11))
> > icl_ctx_workarounds_init(engine);
> > else if (IS_CANNONLAKE(i915))
> > cnl_ctx_workarounds_init(engine);
> > @@ -867,7 +867,7 @@ icl_gt_workarounds_init(struct drm_i915_private
> > *i915, struct i915_wa_list *wal)
> > static void
> > gt_init_workarounds(struct drm_i915_private *i915, struct
> > i915_wa_list *wal)
> > {
> > - if (IS_ICELAKE(i915))
> > + if (IS_GEN(i915, 11))
> > icl_gt_workarounds_init(i915, wal);
> > else if (IS_CANNONLAKE(i915))
> > cnl_gt_workarounds_init(i915, wal);
> > @@ -1064,7 +1064,7 @@ void intel_engine_init_whitelist(struct
> > intel_engine_cs *engine)
> >
> > wa_init_start(w, "whitelist");
> >
> > - if (IS_ICELAKE(i915))
> > + if (IS_GEN(i915, 11))
> > icl_whitelist_build(w);
> > else if (IS_CANNONLAKE(i915))
> > cnl_whitelist_build(w);
> > @@ -1112,7 +1112,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> > *engine, struct i915_wa_list *wal)
> > {
> > struct drm_i915_private *i915 = engine->i915;
> >
> > - if (IS_ICELAKE(i915)) {
> > + if (IS_GEN(i915, 11)) {
> > /* This is not an Wa. Enable for better image quality
> > */
> > wa_masked_en(wal,
> > _3D_CHICKEN3,
_______________________________________________
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/ehl: Inherit Ice Lake conditional code
2019-04-11 23:51 ` Rodrigo Vivi
@ 2019-04-12 14:32 ` Souza, Jose
0 siblings, 0 replies; 9+ messages in thread
From: Souza, Jose @ 2019-04-12 14:32 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: intel-gfx, De Marchi, Lucas
[-- Attachment #1.1: Type: text/plain, Size: 6388 bytes --]
On Thu, 2019-04-11 at 16:51 -0700, Rodrigo Vivi wrote:
> On Thu, Apr 11, 2019 at 04:16:41PM -0700, Souza, Jose wrote:
> > On Thu, 2019-04-11 at 16:08 -0700, Rodrigo Vivi wrote:
> > > From: Bob Paauwe <bob.j.paauwe@intel.com>
> > >
> > > Most of the conditional code for ICELAKE also applies to
> > > ELKHARTLAKE
> > > so use IS_GEN(dev_priv, 11) even for PM and Workarounds for now.
> > >
> > > v2: - Rename commit (Jose)
> > > - Include a wm workaround (Jose and Lucas)
> > > - Include display core init (Jose and Lucas)
> > >
> > > Cc: José Roberto de Souza <jose.souza@intel.com>
> > > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_pm.c | 6 +++---
> > > drivers/gpu/drm/i915/intel_runtime_pm.c | 6 +++---
> > > drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++----
> > > 3 files changed, 10 insertions(+), 10 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > b/drivers/gpu/drm/i915/intel_pm.c
> > > index 8e826a6ab62e..7357bddf9ad9 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -4530,10 +4530,10 @@ skl_allocate_pipe_ddb(struct
> > > intel_crtc_state
> > > *cstate,
> > > memset(&wm->wm[level], 0, sizeof(wm-
> > > > wm[level]));
> > >
> > > /*
> > > - * Wa_1408961008:icl
> > > + * Wa_1408961008:icl, ehl
> > > * Underruns with WM1+ disabled
> > > */
> > > - if (IS_ICELAKE(dev_priv) &&
> > > + if (IS_GEN(dev_priv, 11) &&
> > > level == 1 && wm->wm[0].plane_en) {
> > > wm->wm[level].plane_res_b = wm-
> > > > wm[0].plane_res_b;
> > > wm->wm[level].plane_res_l = wm-
> > > > wm[0].plane_res_l;
> > > @@ -9573,7 +9573,7 @@ static void nop_init_clock_gating(struct
> > > drm_i915_private *dev_priv)
> > > */
> > > void intel_init_clock_gating_hooks(struct drm_i915_private
> > > *dev_priv)
> > > {
> > > - if (IS_ICELAKE(dev_priv))
> > > + if (IS_GEN(dev_priv, 11))
> > > dev_priv->display.init_clock_gating =
> > > icl_init_clock_gating;
> > > else if (IS_CANNONLAKE(dev_priv))
> > > dev_priv->display.init_clock_gating =
> > > cnl_init_clock_gating;
> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > index 3107a742d8ad..fcd388e8978b 100644
> > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > @@ -3448,7 +3448,7 @@ int intel_power_domains_init(struct
> > > drm_i915_private *dev_priv)
> > > * The enabling order will be from lower to higher indexed
> > > wells,
> > > * the disabling order is reversed.
> > > */
> > > - if (IS_ICELAKE(dev_priv)) {
> > > + if (IS_GEN(dev_priv, 11)) {
> > > err = set_power_wells(power_domains, icl_power_wells);
> > > } else if (IS_CANNONLAKE(dev_priv)) {
> > > err = set_power_wells(power_domains, cnl_power_wells);
> > > @@ -4061,7 +4061,7 @@ void intel_power_domains_init_hw(struct
> > > drm_i915_private *i915, bool resume)
> > >
> > > power_domains->initializing = true;
> > >
> > > - if (IS_ICELAKE(i915)) {
> > > + if (INTEL_GEN(i915) >= 11) {
> > > icl_display_core_init(i915, resume);
> > > } else if (IS_CANNONLAKE(i915)) {
> > > cnl_display_core_init(i915, resume);
> > > @@ -4209,7 +4209,7 @@ void intel_power_domains_suspend(struct
> > > drm_i915_private *i915,
> > > intel_power_domains_verify_state(i915);
> > > }
> > >
> > > - if (IS_ICELAKE(i915))
> > > + if (IS_GEN(i915, 11))
> >
> > To be consistent with init: if (INTEL_GEN(i915) >= 11)
>
> hmmm... I tried to keep power well stuff not using this
> greater-than behaviour on purpose... Because so far all
> platforms had different wells, besides gen9_bc group of course...
>
> But even display_10 glk and cnl are different on display wells :/
I guess you are talking about different things, I'm talking about the
icl_display_core_uninit() call.
if (INTEL_GEN(i915) >= 11) {
icl_display_core_init(i915, resume);
if (IS_GEN(i915, 11))
icl_display_core_uninit(i915);
And for core_init/uninit we are able to share the sequence between
several platforms of the same GEN.
>
> > Other than that:
> >
> > Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> >
> > > icl_display_core_uninit(i915);
> > > else if (IS_CANNONLAKE(i915))
> > > cnl_display_core_uninit(i915);
> > > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
> > > b/drivers/gpu/drm/i915/intel_workarounds.c
> > > index a04dbc58ec1c..c0977036db79 100644
> > > --- a/drivers/gpu/drm/i915/intel_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> > > @@ -569,7 +569,7 @@ void intel_engine_init_ctx_wa(struct
> > > intel_engine_cs *engine)
> > >
> > > wa_init_start(wal, "context");
> > >
> > > - if (IS_ICELAKE(i915))
> > > + if (IS_GEN(i915, 11))
> > > icl_ctx_workarounds_init(engine);
> > > else if (IS_CANNONLAKE(i915))
> > > cnl_ctx_workarounds_init(engine);
> > > @@ -867,7 +867,7 @@ icl_gt_workarounds_init(struct
> > > drm_i915_private
> > > *i915, struct i915_wa_list *wal)
> > > static void
> > > gt_init_workarounds(struct drm_i915_private *i915, struct
> > > i915_wa_list *wal)
> > > {
> > > - if (IS_ICELAKE(i915))
> > > + if (IS_GEN(i915, 11))
> > > icl_gt_workarounds_init(i915, wal);
> > > else if (IS_CANNONLAKE(i915))
> > > cnl_gt_workarounds_init(i915, wal);
> > > @@ -1064,7 +1064,7 @@ void intel_engine_init_whitelist(struct
> > > intel_engine_cs *engine)
> > >
> > > wa_init_start(w, "whitelist");
> > >
> > > - if (IS_ICELAKE(i915))
> > > + if (IS_GEN(i915, 11))
> > > icl_whitelist_build(w);
> > > else if (IS_CANNONLAKE(i915))
> > > cnl_whitelist_build(w);
> > > @@ -1112,7 +1112,7 @@ rcs_engine_wa_init(struct intel_engine_cs
> > > *engine, struct i915_wa_list *wal)
> > > {
> > > struct drm_i915_private *i915 = engine->i915;
> > >
> > > - if (IS_ICELAKE(i915)) {
> > > + if (IS_GEN(i915, 11)) {
> > > /* This is not an Wa. Enable for better image quality
> > > */
> > > wa_masked_en(wal,
> > > _3D_CHICKEN3,
>
>
[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
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^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2019-04-12 22:17 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-04-12 18:09 [PATCH] drm/i915/ehl: Inherit Ice Lake conditional code Rodrigo Vivi
2019-04-12 18:48 ` ✓ Fi.CI.BAT: success for drm/i915/ehl: Inherit Ice Lake conditional code (rev2) Patchwork
2019-04-12 19:27 ` [PATCH] drm/i915/ehl: Inherit Ice Lake conditional code Souza, Jose
2019-04-12 22:18 ` Rodrigo Vivi
2019-04-12 21:47 ` ✓ Fi.CI.IGT: success for drm/i915/ehl: Inherit Ice Lake conditional code (rev2) Patchwork
-- strict thread matches above, loose matches on Subject: below --
2019-04-11 23:08 [PATCH] drm/i915/ehl: Inherit Ice Lake conditional code Rodrigo Vivi
2019-04-11 23:16 ` Souza, Jose
2019-04-11 23:51 ` Rodrigo Vivi
2019-04-12 14:32 ` Souza, Jose
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