[PATCH 0/8] target/mips: Use tcg_constant_*

[PATCH 0/8] target/mips: Use tcg_constant_*

[Philippe Mathieu-Daudé]

Replace temporary TCG registers by tcg_constant_*() when possible.

Philippe Mathieu-Daudé (8):
  target/mips: Remove unused register from MSA 2R/2RF instruction format
  target/mips: Use tcg_constant_i32() in gen_msa_elm_df()
  target/mips: Use tcg_constant_i32() in gen_msa_2rf()
  target/mips: Use tcg_constant_i32() in gen_msa_2r()
  target/mips: Use tcg_constant_i32() in gen_msa_3rf()
  target/mips: Use explicit extract32() calls in gen_msa_i5()
  target/mips: Use tcg_constant_i32() in gen_msa_i5()
  target/mips: Use tcg_constant_tl() in gen_compute_compact_branch()

 target/mips/tcg/msa_translate.c | 87 +++++++++++++++++----------------
 target/mips/tcg/translate.c     |  4 +-
 2 files changed, 45 insertions(+), 46 deletions(-)

-- 
2.31.1

[PATCH 1/8] target/mips: Remove unused register from MSA 2R/2RF instruction format

[Philippe Mathieu-Daudé]

Commits cbe50b9a8e7 ("target-mips: add MSA VEC/2R format instructions")
and 3bdeb68866e ("target-mips: add MSA 2RF format instructions") added
the MSA 2R/2RF instructions. However these instructions don't use any
target vector register, so remove the unused TCG temporaries.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2: Reworded, removing the Fixes: tag.
---
 target/mips/tcg/msa_translate.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 8170a8df26b..ee6424126f7 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -1942,13 +1942,11 @@ static void gen_msa_2r(DisasContext *ctx)
 {
 #define MASK_MSA_2R(op)     (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
                             (op & (0x7 << 18)))
-    uint8_t wt = (ctx->opcode >> 16) & 0x1f;
     uint8_t ws = (ctx->opcode >> 11) & 0x1f;
     uint8_t wd = (ctx->opcode >> 6) & 0x1f;
     uint8_t df = (ctx->opcode >> 16) & 0x3;
     TCGv_i32 twd = tcg_const_i32(wd);
     TCGv_i32 tws = tcg_const_i32(ws);
-    TCGv_i32 twt = tcg_const_i32(wt);
     TCGv_i32 tdf = tcg_const_i32(df);
 
     switch (MASK_MSA_2R(ctx->opcode)) {
@@ -2018,7 +2016,6 @@ static void gen_msa_2r(DisasContext *ctx)
 
     tcg_temp_free_i32(twd);
     tcg_temp_free_i32(tws);
-    tcg_temp_free_i32(twt);
     tcg_temp_free_i32(tdf);
 }
 
@@ -2026,13 +2023,11 @@ static void gen_msa_2rf(DisasContext *ctx)
 {
 #define MASK_MSA_2RF(op)    (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
                             (op & (0xf << 17)))
-    uint8_t wt = (ctx->opcode >> 16) & 0x1f;
     uint8_t ws = (ctx->opcode >> 11) & 0x1f;
     uint8_t wd = (ctx->opcode >> 6) & 0x1f;
     uint8_t df = (ctx->opcode >> 16) & 0x1;
     TCGv_i32 twd = tcg_const_i32(wd);
     TCGv_i32 tws = tcg_const_i32(ws);
-    TCGv_i32 twt = tcg_const_i32(wt);
     /* adjust df value for floating-point instruction */
     TCGv_i32 tdf = tcg_const_i32(df + 2);
 
@@ -2089,7 +2084,6 @@ static void gen_msa_2rf(DisasContext *ctx)
 
     tcg_temp_free_i32(twd);
     tcg_temp_free_i32(tws);
-    tcg_temp_free_i32(twt);
     tcg_temp_free_i32(tdf);
 }
 
-- 
2.31.1

[PATCH 2/8] target/mips: Use tcg_constant_i32() in gen_msa_elm_df()

[Philippe Mathieu-Daudé]

Data Format is a 2-bit constant value.
Avoid using a TCG temporary by moving it to the constant pool.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa_translate.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index ee6424126f7..20036ae4968 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -1650,7 +1650,7 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
     TCGv_i32 tws = tcg_const_i32(ws);
     TCGv_i32 twd = tcg_const_i32(wd);
     TCGv_i32 tn  = tcg_const_i32(n);
-    TCGv_i32 tdf = tcg_const_i32(df);
+    TCGv_i32 tdf = tcg_constant_i32(df);
 
     switch (MASK_MSA_ELM(ctx->opcode)) {
     case OPC_SLDI_df:
@@ -1748,7 +1748,6 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
     tcg_temp_free_i32(twd);
     tcg_temp_free_i32(tws);
     tcg_temp_free_i32(tn);
-    tcg_temp_free_i32(tdf);
 }
 
 static void gen_msa_elm(DisasContext *ctx)
-- 
2.31.1

[PATCH 3/8] target/mips: Use tcg_constant_i32() in gen_msa_2rf()

[Philippe Mathieu-Daudé]

Avoid using a TCG temporary by moving Data Format to the constant pool.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa_translate.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 20036ae4968..5e8f80f2f23 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -2028,7 +2028,7 @@ static void gen_msa_2rf(DisasContext *ctx)
     TCGv_i32 twd = tcg_const_i32(wd);
     TCGv_i32 tws = tcg_const_i32(ws);
     /* adjust df value for floating-point instruction */
-    TCGv_i32 tdf = tcg_const_i32(df + 2);
+    TCGv_i32 tdf = tcg_constant_i32(df + 2);
 
     switch (MASK_MSA_2RF(ctx->opcode)) {
     case OPC_FCLASS_df:
@@ -2083,7 +2083,6 @@ static void gen_msa_2rf(DisasContext *ctx)
 
     tcg_temp_free_i32(twd);
     tcg_temp_free_i32(tws);
-    tcg_temp_free_i32(tdf);
 }
 
 static void gen_msa_vec_v(DisasContext *ctx)
-- 
2.31.1

[PATCH 4/8] target/mips: Use tcg_constant_i32() in gen_msa_2r()

[Philippe Mathieu-Daudé]

Avoid using a TCG temporary by moving Data Format to the constant pool.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa_translate.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 5e8f80f2f23..bbe9146513a 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -1946,7 +1946,6 @@ static void gen_msa_2r(DisasContext *ctx)
     uint8_t df = (ctx->opcode >> 16) & 0x3;
     TCGv_i32 twd = tcg_const_i32(wd);
     TCGv_i32 tws = tcg_const_i32(ws);
-    TCGv_i32 tdf = tcg_const_i32(df);
 
     switch (MASK_MSA_2R(ctx->opcode)) {
     case OPC_FILL_df:
@@ -1957,7 +1956,8 @@ static void gen_msa_2r(DisasContext *ctx)
             break;
         }
 #endif
-        gen_helper_msa_fill_df(cpu_env, tdf, twd, tws); /* trs */
+        gen_helper_msa_fill_df(cpu_env, tcg_constant_i32(df),
+                               twd, tws); /* trs */
         break;
     case OPC_NLOC_df:
         switch (df) {
@@ -2015,7 +2015,6 @@ static void gen_msa_2r(DisasContext *ctx)
 
     tcg_temp_free_i32(twd);
     tcg_temp_free_i32(tws);
-    tcg_temp_free_i32(tdf);
 }
 
 static void gen_msa_2rf(DisasContext *ctx)
-- 
2.31.1

[PATCH 5/8] target/mips: Use tcg_constant_i32() in gen_msa_3rf()

[Philippe Mathieu-Daudé]

Avoid using a TCG temporary by moving Data Format to the constant pool.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa_translate.c | 23 ++++++++++++++---------
 1 file changed, 14 insertions(+), 9 deletions(-)

diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index bbe9146513a..e107cad57ee 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -1790,10 +1790,22 @@ static void gen_msa_3rf(DisasContext *ctx)
     TCGv_i32 twd = tcg_const_i32(wd);
     TCGv_i32 tws = tcg_const_i32(ws);
     TCGv_i32 twt = tcg_const_i32(wt);
-    TCGv_i32 tdf = tcg_temp_new_i32();
+    TCGv_i32 tdf;
 
     /* adjust df value for floating-point instruction */
-    tcg_gen_movi_i32(tdf, df + 2);
+    switch (MASK_MSA_3RF(ctx->opcode)) {
+    case OPC_MUL_Q_df:
+    case OPC_MADD_Q_df:
+    case OPC_MSUB_Q_df:
+    case OPC_MULR_Q_df:
+    case OPC_MADDR_Q_df:
+    case OPC_MSUBR_Q_df:
+        tdf = tcg_constant_i32(df + 1);
+        break;
+    default:
+        tdf = tcg_constant_i32(df + 2);
+        break;
+    }
 
     switch (MASK_MSA_3RF(ctx->opcode)) {
     case OPC_FCAF_df:
@@ -1836,7 +1848,6 @@ static void gen_msa_3rf(DisasContext *ctx)
         gen_helper_msa_fmadd_df(cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_MUL_Q_df:
-        tcg_gen_movi_i32(tdf, df + 1);
         gen_helper_msa_mul_q_df(cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FCULT_df:
@@ -1846,14 +1857,12 @@ static void gen_msa_3rf(DisasContext *ctx)
         gen_helper_msa_fmsub_df(cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_MADD_Q_df:
-        tcg_gen_movi_i32(tdf, df + 1);
         gen_helper_msa_madd_q_df(cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FCLE_df:
         gen_helper_msa_fcle_df(cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_MSUB_Q_df:
-        tcg_gen_movi_i32(tdf, df + 1);
         gen_helper_msa_msub_q_df(cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FCULE_df:
@@ -1896,7 +1905,6 @@ static void gen_msa_3rf(DisasContext *ctx)
         gen_helper_msa_fmin_df(cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_MULR_Q_df:
-        tcg_gen_movi_i32(tdf, df + 1);
         gen_helper_msa_mulr_q_df(cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FSULT_df:
@@ -1906,7 +1914,6 @@ static void gen_msa_3rf(DisasContext *ctx)
         gen_helper_msa_fmin_a_df(cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_MADDR_Q_df:
-        tcg_gen_movi_i32(tdf, df + 1);
         gen_helper_msa_maddr_q_df(cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FSLE_df:
@@ -1916,7 +1923,6 @@ static void gen_msa_3rf(DisasContext *ctx)
         gen_helper_msa_fmax_df(cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_MSUBR_Q_df:
-        tcg_gen_movi_i32(tdf, df + 1);
         gen_helper_msa_msubr_q_df(cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FSULE_df:
@@ -1934,7 +1940,6 @@ static void gen_msa_3rf(DisasContext *ctx)
     tcg_temp_free_i32(twd);
     tcg_temp_free_i32(tws);
     tcg_temp_free_i32(twt);
-    tcg_temp_free_i32(tdf);
 }
 
 static void gen_msa_2r(DisasContext *ctx)
-- 
2.31.1

[PATCH 6/8] target/mips: Use explicit extract32() calls in gen_msa_i5()

[Philippe Mathieu-Daudé]

We already use sextract32(), use extract32() for completeness
instead of open-coding it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa_translate.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index e107cad57ee..3ef912da6b8 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -473,15 +473,12 @@ static void gen_msa_i8(DisasContext *ctx)
 static void gen_msa_i5(DisasContext *ctx)
 {
 #define MASK_MSA_I5(op)    (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
-    uint8_t df = (ctx->opcode >> 21) & 0x3;
     int8_t s5 = (int8_t) sextract32(ctx->opcode, 16, 5);
-    uint8_t u5 = (ctx->opcode >> 16) & 0x1f;
-    uint8_t ws = (ctx->opcode >> 11) & 0x1f;
-    uint8_t wd = (ctx->opcode >> 6) & 0x1f;
+    uint8_t u5 = extract32(ctx->opcode, 16, 5);
 
-    TCGv_i32 tdf = tcg_const_i32(df);
-    TCGv_i32 twd = tcg_const_i32(wd);
-    TCGv_i32 tws = tcg_const_i32(ws);
+    TCGv_i32 tdf = tcg_const_i32(extract32(ctx->opcode, 21, 2));
+    TCGv_i32 twd = tcg_const_i32(extract32(ctx->opcode, 11, 5));
+    TCGv_i32 tws = tcg_const_i32(extract32(ctx->opcode, 6, 5));
     TCGv_i32 timm = tcg_temp_new_i32();
     tcg_gen_movi_i32(timm, u5);
 
-- 
2.31.1

[PATCH 7/8] target/mips: Use tcg_constant_i32() in gen_msa_i5()

[Philippe Mathieu-Daudé]

Avoid using a TCG temporary by moving Data Format to the constant pool.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/msa_translate.c | 40 ++++++++++++++++++++-------------
 1 file changed, 24 insertions(+), 16 deletions(-)

diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 3ef912da6b8..3ede2f643c0 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -473,14 +473,32 @@ static void gen_msa_i8(DisasContext *ctx)
 static void gen_msa_i5(DisasContext *ctx)
 {
 #define MASK_MSA_I5(op)    (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
-    int8_t s5 = (int8_t) sextract32(ctx->opcode, 16, 5);
-    uint8_t u5 = extract32(ctx->opcode, 16, 5);
-
     TCGv_i32 tdf = tcg_const_i32(extract32(ctx->opcode, 21, 2));
     TCGv_i32 twd = tcg_const_i32(extract32(ctx->opcode, 11, 5));
     TCGv_i32 tws = tcg_const_i32(extract32(ctx->opcode, 6, 5));
-    TCGv_i32 timm = tcg_temp_new_i32();
-    tcg_gen_movi_i32(timm, u5);
+    TCGv_i32 timm;
+
+    switch (MASK_MSA_I5(ctx->opcode)) {
+    case OPC_ADDVI_df:
+    case OPC_MAXI_U_df:
+    case OPC_MINI_U_df:
+    case OPC_CLTI_U_df:
+    case OPC_CLEI_U_df:
+        timm = tcg_constant_i32(extract32(ctx->opcode, 16, 5));
+        break;
+    case OPC_MAXI_S_df:
+    case OPC_MINI_S_df:
+    case OPC_CEQI_df:
+    case OPC_CLTI_S_df:
+    case OPC_CLEI_S_df:
+        timm = tcg_constant_i32(sextract32(ctx->opcode, 16, 5));
+        break;
+    case OPC_LDI_df:
+        timm = tcg_constant_i32(sextract32(ctx->opcode, 11, 10));
+        break;
+    default:
+        break;
+    }
 
     switch (MASK_MSA_I5(ctx->opcode)) {
     case OPC_ADDVI_df:
@@ -490,43 +508,34 @@ static void gen_msa_i5(DisasContext *ctx)
         gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_MAXI_S_df:
-        tcg_gen_movi_i32(timm, s5);
         gen_helper_msa_maxi_s_df(cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_MAXI_U_df:
         gen_helper_msa_maxi_u_df(cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_MINI_S_df:
-        tcg_gen_movi_i32(timm, s5);
         gen_helper_msa_mini_s_df(cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_MINI_U_df:
         gen_helper_msa_mini_u_df(cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_CEQI_df:
-        tcg_gen_movi_i32(timm, s5);
         gen_helper_msa_ceqi_df(cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_CLTI_S_df:
-        tcg_gen_movi_i32(timm, s5);
         gen_helper_msa_clti_s_df(cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_CLTI_U_df:
         gen_helper_msa_clti_u_df(cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_CLEI_S_df:
-        tcg_gen_movi_i32(timm, s5);
         gen_helper_msa_clei_s_df(cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_CLEI_U_df:
         gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_LDI_df:
-        {
-            int32_t s10 = sextract32(ctx->opcode, 11, 10);
-            tcg_gen_movi_i32(timm, s10);
-            gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm);
-        }
+        gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm);
         break;
     default:
         MIPS_INVAL("MSA instruction");
@@ -537,7 +546,6 @@ static void gen_msa_i5(DisasContext *ctx)
     tcg_temp_free_i32(tdf);
     tcg_temp_free_i32(twd);
     tcg_temp_free_i32(tws);
-    tcg_temp_free_i32(timm);
 }
 
 static void gen_msa_bit(DisasContext *ctx)
-- 
2.31.1

[PATCH 8/8] target/mips: Use tcg_constant_tl() in gen_compute_compact_branch()

[Philippe Mathieu-Daudé]

The offset is constant and read-only: move it to the constant pool.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/translate.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 148afec9dc0..d4e0fbd35be 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -11866,13 +11866,11 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
         } else {
             /* OPC_JIC, OPC_JIALC */
             TCGv tbase = tcg_temp_new();
-            TCGv toffset = tcg_temp_new();
+            TCGv toffset = tcg_constant_tl(offset);
 
             gen_load_gpr(tbase, rt);
-            tcg_gen_movi_tl(toffset, offset);
             gen_op_addr_add(ctx, btarget, tbase, toffset);
             tcg_temp_free(tbase);
-            tcg_temp_free(toffset);
         }
         break;
     default:
-- 
2.31.1

Re: [PATCH 2/8] target/mips: Use tcg_constant_i32() in gen_msa_elm_df()

[Richard Henderson]

On 10/3/21 1:57 PM, Philippe Mathieu-Daudé wrote:
> Data Format is a 2-bit constant value.
> Avoid using a TCG temporary by moving it to the constant pool.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/tcg/msa_translate.c | 3 +--
>   1 file changed, 1 insertion(+), 2 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 3/8] target/mips: Use tcg_constant_i32() in gen_msa_2rf()

[Richard Henderson]

On 10/3/21 1:57 PM, Philippe Mathieu-Daudé wrote:
> Avoid using a TCG temporary by moving Data Format to the constant pool.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/tcg/msa_translate.c | 3 +--
>   1 file changed, 1 insertion(+), 2 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 4/8] target/mips: Use tcg_constant_i32() in gen_msa_2r()

[Richard Henderson]

On 10/3/21 1:57 PM, Philippe Mathieu-Daudé wrote:
> Avoid using a TCG temporary by moving Data Format to the constant pool.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/tcg/msa_translate.c | 5 ++---
>   1 file changed, 2 insertions(+), 3 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 5/8] target/mips: Use tcg_constant_i32() in gen_msa_3rf()

[Richard Henderson]

On 10/3/21 1:57 PM, Philippe Mathieu-Daudé wrote:
>       /* adjust df value for floating-point instruction */
> -    tcg_gen_movi_i32(tdf, df + 2);
> +    switch (MASK_MSA_3RF(ctx->opcode)) {
> +    case OPC_MUL_Q_df:
> +    case OPC_MADD_Q_df:
> +    case OPC_MSUB_Q_df:
> +    case OPC_MULR_Q_df:
> +    case OPC_MADDR_Q_df:
> +    case OPC_MSUBR_Q_df:
> +        tdf = tcg_constant_i32(df + 1);
> +        break;
> +    default:
> +        tdf = tcg_constant_i32(df + 2);
> +        break;
> +    }

Is a second switch really worth it, maintenance wise?
It doesn't hurt to put an unused constant into the pool...

But it looks ok,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 6/8] target/mips: Use explicit extract32() calls in gen_msa_i5()

[Richard Henderson]

On 10/3/21 1:57 PM, Philippe Mathieu-Daudé wrote:
> We already use sextract32(), use extract32() for completeness
> instead of open-coding it.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/tcg/msa_translate.c | 11 ++++-------
>   1 file changed, 4 insertions(+), 7 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 7/8] target/mips: Use tcg_constant_i32() in gen_msa_i5()

[Richard Henderson]

On 10/3/21 1:57 PM, Philippe Mathieu-Daudé wrote:
> +    switch (MASK_MSA_I5(ctx->opcode)) {
> +    case OPC_ADDVI_df:
> +    case OPC_MAXI_U_df:
> +    case OPC_MINI_U_df:
> +    case OPC_CLTI_U_df:
> +    case OPC_CLEI_U_df:
> +        timm = tcg_constant_i32(extract32(ctx->opcode, 16, 5));
> +        break;
> +    case OPC_MAXI_S_df:
> +    case OPC_MINI_S_df:
> +    case OPC_CEQI_df:
> +    case OPC_CLTI_S_df:
> +    case OPC_CLEI_S_df:
> +        timm = tcg_constant_i32(sextract32(ctx->opcode, 16, 5));
> +        break;
> +    case OPC_LDI_df:
> +        timm = tcg_constant_i32(sextract32(ctx->opcode, 11, 10));
> +        break;
> +    default:
> +        break;
> +    }

Same comment wrt duplicating the switch, but,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 8/8] target/mips: Use tcg_constant_tl() in gen_compute_compact_branch()

[Richard Henderson]

On 10/3/21 1:57 PM, Philippe Mathieu-Daudé wrote:
> The offset is constant and read-only: move it to the constant pool.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>   target/mips/tcg/translate.c | 4 +---
>   1 file changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 0/8] target/mips: Use tcg_constant_*

[Philippe Mathieu-Daudé]

On 10/3/21 19:57, Philippe Mathieu-Daudé wrote:
> Replace temporary TCG registers by tcg_constant_*() when possible.
> 
> Philippe Mathieu-Daudé (8):
>   target/mips: Remove unused register from MSA 2R/2RF instruction format
>   target/mips: Use tcg_constant_i32() in gen_msa_elm_df()
>   target/mips: Use tcg_constant_i32() in gen_msa_2rf()
>   target/mips: Use tcg_constant_i32() in gen_msa_2r()
>   target/mips: Use tcg_constant_i32() in gen_msa_3rf()
>   target/mips: Use explicit extract32() calls in gen_msa_i5()
>   target/mips: Use tcg_constant_i32() in gen_msa_i5()
>   target/mips: Use tcg_constant_tl() in gen_compute_compact_branch()
> 
>  target/mips/tcg/msa_translate.c | 87 +++++++++++++++++----------------
>  target/mips/tcg/translate.c     |  4 +-
>  2 files changed, 45 insertions(+), 46 deletions(-)

Thanks, series applied to mips-next tree.