From: Paolo Bonzini <pbonzini@redhat.com> To: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>, Ingo Molnar <mingo@redhat.com>, Thomas Gleixner <tglx@linutronix.de>, "H. Peter Anvin" <hpa@zytor.com>, Andy Lutomirski <luto@kernel.org>, Borislav Petkov <bp@suse.de> Cc: Peter Zijlstra <peterz@infradead.org>, Andrew Morton <akpm@linux-foundation.org>, Brian Gerst <brgerst@gmail.com>, Chris Metcalf <cmetcalf@mellanox.com>, Dave Hansen <dave.hansen@linux.intel.com>, Liang Z Li <liang.z.li@intel.com>, Masami Hiramatsu <mhiramat@kernel.org>, Huang Rui <ray.huang@amd.com>, Jiri Slaby <jslaby@suse.cz>, Jonathan Corbet <corbet@lwn.net>, "Michael S. Tsirkin" <mst@redhat.com>, Paul Gortmaker <paul.gortmaker@windriver.com>, Vlastimil Babka <vbabka@suse.cz>, Chen Yucong <slaoub@gmail.com>, Alexandre Julliard <julliard@winehq.org>, Stas Sergeev <stsp@list.ru>, Fenghua Yu <fenghua.yu@intel.com>, "Ravi V. Shankar" <ravi.v.shankar@intel.com>, Shuah Khan <shuah@kernel.org>, linux-kernel@vger.kernel.org, x86@kernel.org, linux-msdos@vger.kernel.org, wine-devel@winehq.org, Tony Luck <tony.luck@intel.com> Subject: Re: [PATCH v7 20/26] x86/cpufeature: Add User-Mode Instruction Prevention definitions Date: Sat, 6 May 2017 11:04:41 +0200 [thread overview] Message-ID: <97a69db6-4321-2d22-07f6-ba4b9400c688@redhat.com> (raw) In-Reply-To: <20170505181724.55000-21-ricardo.neri-calderon@linux.intel.com> On 05/05/2017 20:17, Ricardo Neri wrote: > User-Mode Instruction Prevention is a security feature present in new > Intel processors that, when set, prevents the execution of a subset of > instructions if such instructions are executed in user mode (CPL > 0). > Attempting to execute such instructions causes a general protection > exception. > > The subset of instructions comprises: > > * SGDT - Store Global Descriptor Table > * SIDT - Store Interrupt Descriptor Table > * SLDT - Store Local Descriptor Table > * SMSW - Store Machine Status Word > * STR - Store Task Register > > This feature is also added to the list of disabled-features to allow > a cleaner handling of build-time configuration. > > Cc: Andy Lutomirski <luto@kernel.org> > Cc: Andrew Morton <akpm@linux-foundation.org> > Cc: H. Peter Anvin <hpa@zytor.com> > Cc: Borislav Petkov <bp@suse.de> > Cc: Brian Gerst <brgerst@gmail.com> > Cc: Chen Yucong <slaoub@gmail.com> > Cc: Chris Metcalf <cmetcalf@mellanox.com> > Cc: Dave Hansen <dave.hansen@linux.intel.com> > Cc: Fenghua Yu <fenghua.yu@intel.com> > Cc: Huang Rui <ray.huang@amd.com> > Cc: Jiri Slaby <jslaby@suse.cz> > Cc: Jonathan Corbet <corbet@lwn.net> > Cc: Michael S. Tsirkin <mst@redhat.com> > Cc: Paul Gortmaker <paul.gortmaker@windriver.com> > Cc: Peter Zijlstra <peterz@infradead.org> > Cc: Ravi V. Shankar <ravi.v.shankar@intel.com> > Cc: Shuah Khan <shuah@kernel.org> > Cc: Vlastimil Babka <vbabka@suse.cz> > Cc: Tony Luck <tony.luck@intel.com> > Cc: Paolo Bonzini <pbonzini@redhat.com> > Cc: Liang Z. Li <liang.z.li@intel.com> > Cc: Alexandre Julliard <julliard@winehq.org> > Cc: Stas Sergeev <stsp@list.ru> > Cc: x86@kernel.org > Cc: linux-msdos@vger.kernel.org > > Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com> Would it be possible to have this patch in a topic branch for KVM's consumption? Thanks, Paolo > --- > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/include/asm/disabled-features.h | 8 +++++++- > arch/x86/include/uapi/asm/processor-flags.h | 2 ++ > 3 files changed, 10 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 2701e5f..f1d61d2 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -289,6 +289,7 @@ > > /* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */ > #define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/ > +#define X86_FEATURE_UMIP (16*32+ 2) /* User Mode Instruction Protection */ > #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ > #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ > #define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */ > diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h > index 5dff775..7adaef7 100644 > --- a/arch/x86/include/asm/disabled-features.h > +++ b/arch/x86/include/asm/disabled-features.h > @@ -16,6 +16,12 @@ > # define DISABLE_MPX (1<<(X86_FEATURE_MPX & 31)) > #endif > > +#ifdef CONFIG_X86_INTEL_UMIP > +# define DISABLE_UMIP 0 > +#else > +# define DISABLE_UMIP (1<<(X86_FEATURE_UMIP & 31)) > +#endif > + > #ifdef CONFIG_X86_64 > # define DISABLE_VME (1<<(X86_FEATURE_VME & 31)) > # define DISABLE_K6_MTRR (1<<(X86_FEATURE_K6_MTRR & 31)) > @@ -61,7 +67,7 @@ > #define DISABLED_MASK13 0 > #define DISABLED_MASK14 0 > #define DISABLED_MASK15 0 > -#define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57) > +#define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP) > #define DISABLED_MASK17 0 > #define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18) > > diff --git a/arch/x86/include/uapi/asm/processor-flags.h b/arch/x86/include/uapi/asm/processor-flags.h > index 567de50..d2c2af8 100644 > --- a/arch/x86/include/uapi/asm/processor-flags.h > +++ b/arch/x86/include/uapi/asm/processor-flags.h > @@ -104,6 +104,8 @@ > #define X86_CR4_OSFXSR _BITUL(X86_CR4_OSFXSR_BIT) > #define X86_CR4_OSXMMEXCPT_BIT 10 /* enable unmasked SSE exceptions */ > #define X86_CR4_OSXMMEXCPT _BITUL(X86_CR4_OSXMMEXCPT_BIT) > +#define X86_CR4_UMIP_BIT 11 /* enable UMIP support */ > +#define X86_CR4_UMIP _BITUL(X86_CR4_UMIP_BIT) > #define X86_CR4_VMXE_BIT 13 /* enable VMX virtualization */ > #define X86_CR4_VMXE _BITUL(X86_CR4_VMXE_BIT) > #define X86_CR4_SMXE_BIT 14 /* enable safer mode (TXT) */ >
WARNING: multiple messages have this Message-ID (diff)
From: Paolo Bonzini <pbonzini@redhat.com> To: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>, Ingo Molnar <mingo@redhat.com>, Thomas Gleixner <tglx@linutronix.de>, "H. Peter Anvin" <hpa@zytor.com>, Andy Lutomirski <luto@kernel.org>, Borislav Petkov <bp@suse.de> Cc: Peter Zijlstra <peterz@infradead.org>, Andrew Morton <akpm@linux-foundation.org>, Brian Gerst <brgerst@gmail.com>, Chris Metcalf <cmetcalf@mellanox.com>, Dave Hansen <dave.hansen@linux.intel.com>, Liang Z Li <liang.z.li@intel.com>, Masami Hiramatsu <mhiramat@kernel.org>, Huang Rui <ray.huang@amd.com>, Jiri Slaby <jslaby@suse.cz>, Jonathan Corbet <corbet@lwn.net>, "Michael S. Tsirkin" <mst@redhat.com>, Paul Gortmaker <paul.gortmaker@windriver.com>, Vlastimil Babka <vbabka@suse.cz>, Chen Yucong <slaoub@gmail.com>, Alexandre Julliard <julliard@winehq.org>, Stas Sergeev <stsp@list.ru>, Fenghua Yu <fenghua.yu@intel.com>, "Ravi V. Shankar" <ravi.v.shankar@intel.com>, Shuah Khan <shuah@kernel.org>, linux-kernel@vger.kernel.org, x86@kernel.org, linux-msdos@v Subject: Re: [PATCH v7 20/26] x86/cpufeature: Add User-Mode Instruction Prevention definitions Date: Sat, 6 May 2017 11:04:41 +0200 [thread overview] Message-ID: <97a69db6-4321-2d22-07f6-ba4b9400c688@redhat.com> (raw) In-Reply-To: <20170505181724.55000-21-ricardo.neri-calderon@linux.intel.com> On 05/05/2017 20:17, Ricardo Neri wrote: > User-Mode Instruction Prevention is a security feature present in new > Intel processors that, when set, prevents the execution of a subset of > instructions if such instructions are executed in user mode (CPL > 0). > Attempting to execute such instructions causes a general protection > exception. > > The subset of instructions comprises: > > * SGDT - Store Global Descriptor Table > * SIDT - Store Interrupt Descriptor Table > * SLDT - Store Local Descriptor Table > * SMSW - Store Machine Status Word > * STR - Store Task Register > > This feature is also added to the list of disabled-features to allow > a cleaner handling of build-time configuration. > > Cc: Andy Lutomirski <luto@kernel.org> > Cc: Andrew Morton <akpm@linux-foundation.org> > Cc: H. Peter Anvin <hpa@zytor.com> > Cc: Borislav Petkov <bp@suse.de> > Cc: Brian Gerst <brgerst@gmail.com> > Cc: Chen Yucong <slaoub@gmail.com> > Cc: Chris Metcalf <cmetcalf@mellanox.com> > Cc: Dave Hansen <dave.hansen@linux.intel.com> > Cc: Fenghua Yu <fenghua.yu@intel.com> > Cc: Huang Rui <ray.huang@amd.com> > Cc: Jiri Slaby <jslaby@suse.cz> > Cc: Jonathan Corbet <corbet@lwn.net> > Cc: Michael S. Tsirkin <mst@redhat.com> > Cc: Paul Gortmaker <paul.gortmaker@windriver.com> > Cc: Peter Zijlstra <peterz@infradead.org> > Cc: Ravi V. Shankar <ravi.v.shankar@intel.com> > Cc: Shuah Khan <shuah@kernel.org> > Cc: Vlastimil Babka <vbabka@suse.cz> > Cc: Tony Luck <tony.luck@intel.com> > Cc: Paolo Bonzini <pbonzini@redhat.com> > Cc: Liang Z. Li <liang.z.li@intel.com> > Cc: Alexandre Julliard <julliard@winehq.org> > Cc: Stas Sergeev <stsp@list.ru> > Cc: x86@kernel.org > Cc: linux-msdos@vger.kernel.org > > Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com> Would it be possible to have this patch in a topic branch for KVM's consumption? Thanks, Paolo > --- > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/include/asm/disabled-features.h | 8 +++++++- > arch/x86/include/uapi/asm/processor-flags.h | 2 ++ > 3 files changed, 10 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 2701e5f..f1d61d2 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -289,6 +289,7 @@ > > /* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */ > #define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/ > +#define X86_FEATURE_UMIP (16*32+ 2) /* User Mode Instruction Protection */ > #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ > #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ > #define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */ > diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h > index 5dff775..7adaef7 100644 > --- a/arch/x86/include/asm/disabled-features.h > +++ b/arch/x86/include/asm/disabled-features.h > @@ -16,6 +16,12 @@ > # define DISABLE_MPX (1<<(X86_FEATURE_MPX & 31)) > #endif > > +#ifdef CONFIG_X86_INTEL_UMIP > +# define DISABLE_UMIP 0 > +#else > +# define DISABLE_UMIP (1<<(X86_FEATURE_UMIP & 31)) > +#endif > + > #ifdef CONFIG_X86_64 > # define DISABLE_VME (1<<(X86_FEATURE_VME & 31)) > # define DISABLE_K6_MTRR (1<<(X86_FEATURE_K6_MTRR & 31)) > @@ -61,7 +67,7 @@ > #define DISABLED_MASK13 0 > #define DISABLED_MASK14 0 > #define DISABLED_MASK15 0 > -#define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57) > +#define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP) > #define DISABLED_MASK17 0 > #define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18) > > diff --git a/arch/x86/include/uapi/asm/processor-flags.h b/arch/x86/include/uapi/asm/processor-flags.h > index 567de50..d2c2af8 100644 > --- a/arch/x86/include/uapi/asm/processor-flags.h > +++ b/arch/x86/include/uapi/asm/processor-flags.h > @@ -104,6 +104,8 @@ > #define X86_CR4_OSFXSR _BITUL(X86_CR4_OSFXSR_BIT) > #define X86_CR4_OSXMMEXCPT_BIT 10 /* enable unmasked SSE exceptions */ > #define X86_CR4_OSXMMEXCPT _BITUL(X86_CR4_OSXMMEXCPT_BIT) > +#define X86_CR4_UMIP_BIT 11 /* enable UMIP support */ > +#define X86_CR4_UMIP _BITUL(X86_CR4_UMIP_BIT) > #define X86_CR4_VMXE_BIT 13 /* enable VMX virtualization */ > #define X86_CR4_VMXE _BITUL(X86_CR4_VMXE_BIT) > #define X86_CR4_SMXE_BIT 14 /* enable safer mode (TXT) */ >
next prev parent reply other threads:[~2017-05-06 9:04 UTC|newest] Thread overview: 164+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-05-05 18:16 [PATCH v7 00/26] x86: Enable User-Mode Instruction Prevention Ricardo Neri 2017-05-05 18:16 ` Ricardo Neri 2017-05-05 18:16 ` [PATCH v7 01/26] ptrace,x86: Make user_64bit_mode() available to 32-bit builds Ricardo Neri 2017-05-05 18:16 ` Ricardo Neri 2017-05-21 14:19 ` Borislav Petkov 2017-05-21 14:19 ` Borislav Petkov 2017-05-05 18:17 ` [PATCH v7 02/26] x86/mm: Relocate page fault error codes to traps.h Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-05-21 14:23 ` Borislav Petkov 2017-05-21 14:23 ` Borislav Petkov 2017-05-27 3:40 ` Ricardo Neri 2017-05-27 3:40 ` Ricardo Neri 2017-05-27 10:13 ` Borislav Petkov 2017-05-27 10:13 ` Borislav Petkov 2017-06-01 3:09 ` Ricardo Neri 2017-06-01 3:09 ` Ricardo Neri 2017-05-05 18:17 ` [PATCH v7 03/26] x86/mpx: Use signed variables to compute effective addresses Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-05-05 18:17 ` [PATCH v7 04/26] x86/mpx: Do not use SIB.index if its value is 100b and ModRM.mod is not 11b Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-05-24 13:37 ` Borislav Petkov 2017-05-24 13:37 ` Borislav Petkov 2017-05-27 3:36 ` Ricardo Neri 2017-05-27 3:36 ` Ricardo Neri 2017-05-05 18:17 ` [PATCH v7 05/26] x86/mpx: Do not use SIB.base if its value is 101b and ModRM.mod = 0 Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-05-29 13:07 ` Borislav Petkov 2017-05-29 13:07 ` Borislav Petkov 2017-06-06 6:08 ` Ricardo Neri 2017-06-06 6:08 ` Ricardo Neri 2017-05-05 18:17 ` [PATCH v7 06/26] x86/mpx, x86/insn: Relocate insn util functions to a new insn-eval file Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-05-05 18:17 ` [PATCH v7 07/26] x86/insn-eval: Do not BUG on invalid register type Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-05-29 16:37 ` Borislav Petkov 2017-05-29 16:37 ` Borislav Petkov 2017-06-06 6:06 ` Ricardo Neri 2017-06-06 6:06 ` Ricardo Neri 2017-06-06 11:58 ` Borislav Petkov 2017-06-06 11:58 ` Borislav Petkov 2017-06-07 0:28 ` Ricardo Neri 2017-06-07 0:28 ` Ricardo Neri 2017-06-07 12:21 ` Borislav Petkov 2017-06-07 12:21 ` Borislav Petkov 2017-06-07 18:54 ` Stas Sergeev 2017-06-27 19:03 ` Ricardo Neri 2017-05-05 18:17 ` [PATCH v7 08/26] x86/insn-eval: Add a utility function to get register offsets Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-05-29 17:16 ` Borislav Petkov 2017-05-29 17:16 ` Borislav Petkov 2017-06-06 6:02 ` Ricardo Neri 2017-06-06 6:02 ` Ricardo Neri 2017-05-05 18:17 ` [PATCH v7 09/26] x86/insn-eval: Add utility function to identify string instructions Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-05-29 21:48 ` Borislav Petkov 2017-05-29 21:48 ` Borislav Petkov 2017-06-06 6:01 ` Ricardo Neri 2017-06-06 6:01 ` Ricardo Neri 2017-06-06 12:04 ` Borislav Petkov 2017-06-06 12:04 ` Borislav Petkov 2017-05-05 18:17 ` [PATCH v7 10/26] x86/insn-eval: Add utility functions to get segment selector Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-05-30 10:35 ` Borislav Petkov 2017-05-30 10:35 ` Borislav Petkov 2017-06-15 18:37 ` Ricardo Neri 2017-06-15 18:37 ` Ricardo Neri 2017-06-15 19:04 ` Ricardo Neri 2017-06-15 19:04 ` Ricardo Neri 2017-06-19 15:29 ` Borislav Petkov 2017-06-19 15:29 ` Borislav Petkov 2017-06-19 15:37 ` Borislav Petkov 2017-06-19 15:37 ` Borislav Petkov 2017-05-05 18:17 ` [PATCH v7 11/26] x86/insn-eval: Add utility function to get segment descriptor Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-05-05 18:17 ` [PATCH v7 12/26] x86/insn-eval: Add utility functions to get segment descriptor base address and limit Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-05-31 16:58 ` Borislav Petkov 2017-05-31 16:58 ` Borislav Petkov 2017-06-03 17:23 ` Ricardo Neri 2017-06-03 17:23 ` Ricardo Neri 2017-05-05 18:17 ` [PATCH v7 13/26] x86/insn-eval: Add function to get default params of code segment Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-06-07 12:59 ` Borislav Petkov 2017-06-07 12:59 ` Borislav Petkov 2017-06-15 19:24 ` Ricardo Neri 2017-06-15 19:24 ` Ricardo Neri 2017-06-19 17:11 ` Borislav Petkov 2017-06-19 17:11 ` Borislav Petkov 2017-05-05 18:17 ` [PATCH v7 14/26] x86/insn-eval: Indicate a 32-bit displacement if ModRM.mod is 0 and ModRM.rm is 5 Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-06-07 13:15 ` Borislav Petkov 2017-06-07 13:15 ` Borislav Petkov 2017-06-15 19:36 ` Ricardo Neri 2017-06-15 19:36 ` Ricardo Neri 2017-05-05 18:17 ` [PATCH v7 15/26] x86/insn-eval: Incorporate segment base and limit in linear address computation Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-05-05 18:17 ` [PATCH v7 16/26] x86/insn-eval: Support both signed 32-bit and 64-bit effective addresses Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-06-07 15:48 ` Borislav Petkov 2017-06-07 15:48 ` Borislav Petkov 2017-07-25 23:48 ` Ricardo Neri 2017-07-25 23:48 ` Ricardo Neri 2017-07-27 13:26 ` Borislav Petkov 2017-07-27 13:26 ` Borislav Petkov 2017-07-28 2:04 ` Ricardo Neri 2017-07-28 2:04 ` Ricardo Neri 2017-07-28 6:50 ` Borislav Petkov 2017-07-28 6:50 ` Borislav Petkov 2017-06-07 15:49 ` Borislav Petkov 2017-06-07 15:49 ` Borislav Petkov 2017-06-15 19:58 ` Ricardo Neri 2017-06-15 19:58 ` Ricardo Neri 2017-05-05 18:17 ` [PATCH v7 17/26] x86/insn-eval: Handle 32-bit address encodings in virtual-8086 mode Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-05-05 18:17 ` [PATCH v7 18/26] x86/insn-eval: Add support to resolve 16-bit addressing encodings Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-06-07 16:28 ` Borislav Petkov 2017-06-07 16:28 ` Borislav Petkov 2017-06-15 21:50 ` Ricardo Neri 2017-06-15 21:50 ` Ricardo Neri 2017-05-05 18:17 ` [PATCH v7 19/26] x86/insn-eval: Add wrapper function for 16-bit and 32-bit address encodings Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-05-05 18:17 ` [PATCH v7 20/26] x86/cpufeature: Add User-Mode Instruction Prevention definitions Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-05-06 9:04 ` Paolo Bonzini [this message] 2017-05-06 9:04 ` Paolo Bonzini 2017-05-11 3:23 ` Ricardo Neri 2017-05-11 3:23 ` Ricardo Neri 2017-06-07 18:24 ` Borislav Petkov 2017-06-07 18:24 ` Borislav Petkov 2017-05-05 18:17 ` [PATCH v7 21/26] x86: Add emulation code for UMIP instructions Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-06-08 18:38 ` Borislav Petkov 2017-06-08 18:38 ` Borislav Petkov 2017-06-17 1:34 ` Ricardo Neri 2017-06-17 1:34 ` Ricardo Neri 2017-05-05 18:17 ` [PATCH v7 22/26] x86/umip: Force a page fault when unable to copy emulated result to user Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-06-09 11:02 ` Borislav Petkov 2017-06-09 11:02 ` Borislav Petkov 2017-07-25 23:50 ` Ricardo Neri 2017-07-25 23:50 ` Ricardo Neri 2017-05-05 18:17 ` [PATCH v7 23/26] x86/traps: Fixup general protection faults caused by UMIP Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-06-09 13:02 ` Borislav Petkov 2017-06-09 13:02 ` Borislav Petkov 2017-07-25 23:51 ` Ricardo Neri 2017-07-25 23:51 ` Ricardo Neri 2017-05-05 18:17 ` [PATCH v7 24/26] x86: Enable User-Mode Instruction Prevention Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-06-09 16:10 ` Borislav Petkov 2017-06-09 16:10 ` Borislav Petkov 2017-07-26 0:44 ` Ricardo Neri 2017-07-26 0:44 ` Ricardo Neri 2017-07-27 13:57 ` Borislav Petkov 2017-07-27 13:57 ` Borislav Petkov 2017-05-05 18:17 ` [PATCH v7 25/26] selftests/x86: Add tests for " Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-05-05 18:17 ` [PATCH v7 26/26] selftests/x86: Add tests for instruction str and sldt Ricardo Neri 2017-05-05 18:17 ` Ricardo Neri 2017-05-17 18:42 ` [PATCH v7 00/26] x86: Enable User-Mode Instruction Prevention Ricardo Neri 2017-05-17 18:42 ` Ricardo Neri 2017-05-27 3:49 ` Neri, Ricardo 2017-05-27 3:49 ` Neri, Ricardo
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