From: Randy Dunlap <rdunlap@infradead.org> To: Punit Agrawal <punit.agrawal@arm.com>, linux-doc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, steve.capper@arm.com, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will.deacon@arm.com>, Jonathan Corbet <corbet@lwn.net> Subject: Re: [PATCH] Documentation/arm64: HugeTLB page implementation Date: Sat, 6 Oct 2018 09:30:19 -0700 [thread overview] Message-ID: <97e4e5fb-24ed-0545-414a-6a0c0116e6b8@infradead.org> (raw) In-Reply-To: <20181005143458.17875-1-punit.agrawal@arm.com> Hi, Just some minor stuff (below). On 10/5/18 7:34 AM, Punit Agrawal wrote: > Arm v8 architecture supports multiple page sizes - 4k, 16k and > 64k. Based on the active page size, the Linux port supports > corresponding hugepage sizes at PMD and PUD(4k only) levels. > > In addition, the architecture also supports caching larger sized > ranges (composed of multiple entries) at the PTE and PMD level in the > TLBs using the contiguous bit. The Linux port makes use of this > architectural support to enable additional hugepage sizes. > > Describe the two different types of hugepages supported by the arm64 > kernel and the hugepage sizes enabled by each. > > Signed-off-by: Punit Agrawal <punit.agrawal@arm.com> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will.deacon@arm.com> > Cc: Jonathan Corbet <corbet@lwn.net> > --- > Documentation/arm64/hugetlbpage.txt | 39 +++++++++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > create mode 100644 Documentation/arm64/hugetlbpage.txt > > diff --git a/Documentation/arm64/hugetlbpage.txt b/Documentation/arm64/hugetlbpage.txt > new file mode 100644 > index 000000000000..64ee24b88d27 > --- /dev/null > +++ b/Documentation/arm64/hugetlbpage.txt > @@ -0,0 +1,39 @@ > +HugeTLBpage on ARM64 > +==================== > + > +Hugepage relies on making efficient use of TLBs to improve performance of > +address translations. The benefit depends on both - > + > + - the size of hugepages > + - size of entries supported by the TLBs > + > +The ARM64 port supports two flavours of hugepages. > + > +1) Block mappings at the pud/pmd level > +-------------------------------------- > + > +These are regular hugepages where a pmd or a pud page table entry points to a > +block of memory. Regardless of the supported size of entries in TLB, block > +mappings reduces the depth of page table walk needed to translate hugepage reduce > +addresses. > + > +2) Using the Contiguous bit > +--------------------------- > + > +The architecture provides a contiguous bit in the translation table entries > +(D4.5.3, ARM DDI 0487C.a) that hints to the mmu to indicate that it is one of a preferably MMU > +contiguous set of entries that can be cached in a single TLB entry. > + > +The contiguous bit is used in Linux to increase the mapping size at the pmd and > +pte (last) level. The number of supported contiguous entries vary by page size varies > +and level of the page table. > + > + > + > +The following hugepage sizes are supported - > + > + CONT PTE PMD CONT PMD PUD > + -------- --- -------- --- > + 4K: 64K 2M 32M 1G > + 16K: 2M 32M 1G > + 64K: 2M 512M 16G > thanks, -- ~Randy
WARNING: multiple messages have this Message-ID (diff)
From: rdunlap@infradead.org (Randy Dunlap) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] Documentation/arm64: HugeTLB page implementation Date: Sat, 6 Oct 2018 09:30:19 -0700 [thread overview] Message-ID: <97e4e5fb-24ed-0545-414a-6a0c0116e6b8@infradead.org> (raw) In-Reply-To: <20181005143458.17875-1-punit.agrawal@arm.com> Hi, Just some minor stuff (below). On 10/5/18 7:34 AM, Punit Agrawal wrote: > Arm v8 architecture supports multiple page sizes - 4k, 16k and > 64k. Based on the active page size, the Linux port supports > corresponding hugepage sizes at PMD and PUD(4k only) levels. > > In addition, the architecture also supports caching larger sized > ranges (composed of multiple entries) at the PTE and PMD level in the > TLBs using the contiguous bit. The Linux port makes use of this > architectural support to enable additional hugepage sizes. > > Describe the two different types of hugepages supported by the arm64 > kernel and the hugepage sizes enabled by each. > > Signed-off-by: Punit Agrawal <punit.agrawal@arm.com> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will.deacon@arm.com> > Cc: Jonathan Corbet <corbet@lwn.net> > --- > Documentation/arm64/hugetlbpage.txt | 39 +++++++++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > create mode 100644 Documentation/arm64/hugetlbpage.txt > > diff --git a/Documentation/arm64/hugetlbpage.txt b/Documentation/arm64/hugetlbpage.txt > new file mode 100644 > index 000000000000..64ee24b88d27 > --- /dev/null > +++ b/Documentation/arm64/hugetlbpage.txt > @@ -0,0 +1,39 @@ > +HugeTLBpage on ARM64 > +==================== > + > +Hugepage relies on making efficient use of TLBs to improve performance of > +address translations. The benefit depends on both - > + > + - the size of hugepages > + - size of entries supported by the TLBs > + > +The ARM64 port supports two flavours of hugepages. > + > +1) Block mappings at the pud/pmd level > +-------------------------------------- > + > +These are regular hugepages where a pmd or a pud page table entry points to a > +block of memory. Regardless of the supported size of entries in TLB, block > +mappings reduces the depth of page table walk needed to translate hugepage reduce > +addresses. > + > +2) Using the Contiguous bit > +--------------------------- > + > +The architecture provides a contiguous bit in the translation table entries > +(D4.5.3, ARM DDI 0487C.a) that hints to the mmu to indicate that it is one of a preferably MMU > +contiguous set of entries that can be cached in a single TLB entry. > + > +The contiguous bit is used in Linux to increase the mapping size at the pmd and > +pte (last) level. The number of supported contiguous entries vary by page size varies > +and level of the page table. > + > + > + > +The following hugepage sizes are supported - > + > + CONT PTE PMD CONT PMD PUD > + -------- --- -------- --- > + 4K: 64K 2M 32M 1G > + 16K: 2M 32M 1G > + 64K: 2M 512M 16G > thanks, -- ~Randy
next prev parent reply other threads:[~2018-10-06 16:30 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-10-05 14:34 [PATCH] Documentation/arm64: HugeTLB page implementation Punit Agrawal 2018-10-05 14:34 ` Punit Agrawal 2018-10-06 16:30 ` Randy Dunlap [this message] 2018-10-06 16:30 ` Randy Dunlap 2018-10-08 9:39 ` Punit Agrawal 2018-10-08 9:39 ` Punit Agrawal 2018-10-08 10:03 ` [PATCH v2] " Punit Agrawal 2018-10-08 10:03 ` Punit Agrawal 2018-10-08 19:49 ` Randy Dunlap 2018-10-08 19:49 ` Randy Dunlap 2018-10-09 10:02 ` Punit Agrawal 2018-10-09 10:02 ` Punit Agrawal 2018-10-09 11:50 ` Will Deacon 2018-10-09 11:50 ` Will Deacon 2018-10-10 17:08 ` Catalin Marinas 2018-10-10 17:08 ` Catalin Marinas
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=97e4e5fb-24ed-0545-414a-6a0c0116e6b8@infradead.org \ --to=rdunlap@infradead.org \ --cc=catalin.marinas@arm.com \ --cc=corbet@lwn.net \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-doc@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=punit.agrawal@arm.com \ --cc=steve.capper@arm.com \ --cc=will.deacon@arm.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.