From: Jon Masters <jcm@jonmasters.org>
To: Florian Fainelli <f.fainelli@gmail.com>,
Timur Tabi <timur@codeaurora.org>,
linux-arm-kernel@lists.infradead.org
Cc: tchalamarla@cavium.com, rrichter@cavium.com, opendmb@gmail.com,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] arm64: Make L1_CACHE_SHIFT configurable
Date: Mon, 19 Feb 2018 18:46:14 -0500 [thread overview]
Message-ID: <9a5190d1-eb8d-0275-d8d9-39de622a679c@jonmasters.org> (raw)
In-Reply-To: <126b2cc2-a61e-b30d-1ff9-ea30af7abf57@gmail.com>
On 02/12/2018 07:17 PM, Florian Fainelli wrote:
> On 02/12/2018 04:10 PM, Timur Tabi wrote:
>> On 02/12/2018 05:57 PM, Florian Fainelli wrote:
>>> That is debatable, is there a good publicly available table of what the
>>> typical L1 cache line size is on ARMv8 platforms?
With a server hat on...
There are many ARMv8 server platforms that do 64b today, but future
designs are likely to head toward 128b (for a variety of reasons). Many
of the earlier designs were 64b because that's what certain other arches
were using in their server cores. I doubt Vulcan will remain a unique
and special case for very long. On the CCIX side of things, I've been
trying to push people to go with 128b lines in future designs too.
Jon.
WARNING: multiple messages have this Message-ID (diff)
From: jcm@jonmasters.org (Jon Masters)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] arm64: Make L1_CACHE_SHIFT configurable
Date: Mon, 19 Feb 2018 18:46:14 -0500 [thread overview]
Message-ID: <9a5190d1-eb8d-0275-d8d9-39de622a679c@jonmasters.org> (raw)
In-Reply-To: <126b2cc2-a61e-b30d-1ff9-ea30af7abf57@gmail.com>
On 02/12/2018 07:17 PM, Florian Fainelli wrote:
> On 02/12/2018 04:10 PM, Timur Tabi wrote:
>> On 02/12/2018 05:57 PM, Florian Fainelli wrote:
>>> That is debatable, is there a good publicly available table of what the
>>> typical L1 cache line size is on ARMv8 platforms?
With a server hat on...
There are many ARMv8 server platforms that do 64b today, but future
designs are likely to head toward 128b (for a variety of reasons). Many
of the earlier designs were 64b because that's what certain other arches
were using in their server cores. I doubt Vulcan will remain a unique
and special case for very long. On the CCIX side of things, I've been
trying to push people to go with 128b lines in future designs too.
Jon.
next prev parent reply other threads:[~2018-02-19 23:46 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-12 23:45 [PATCH] arm64: Make L1_CACHE_SHIFT configurable Florian Fainelli
2018-02-12 23:45 ` Florian Fainelli
2018-02-12 23:52 ` Timur Tabi
2018-02-12 23:52 ` Timur Tabi
2018-02-12 23:57 ` Florian Fainelli
2018-02-12 23:57 ` Florian Fainelli
2018-02-13 0:10 ` Timur Tabi
2018-02-13 0:10 ` Timur Tabi
2018-02-13 0:17 ` Florian Fainelli
2018-02-13 0:17 ` Florian Fainelli
2018-02-19 23:46 ` Jon Masters [this message]
2018-02-19 23:46 ` Jon Masters
2018-02-13 11:57 ` Catalin Marinas
2018-02-13 11:57 ` Catalin Marinas
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