* [PATCH 01/16] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
@ 2018-02-14 4:57 ` Vidya Srinivas
2018-02-14 4:57 ` [PATCH 02/16] drm/i915/skl+: refactor WM calculation for NV12 Vidya Srinivas
` (25 subsequent siblings)
26 siblings, 0 replies; 52+ messages in thread
From: Vidya Srinivas @ 2018-02-14 4:57 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
skl_wm_values struct contains values of pipe/plane DDB only.
so rename it for better readability of code. Similarly
skl_copy_wm_for_pipe copies DDB values.
s/skl_wm_values/skl_ddb_values
s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe
Changes since V1:
- also change name of skl_copy_wm_for_pipe
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 14 +++++++-------
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c06d412..564a364 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1447,7 +1447,7 @@ struct skl_ddb_allocation {
struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
};
-struct skl_wm_values {
+struct skl_ddb_values {
unsigned dirty_pipes;
struct skl_ddb_allocation ddb;
};
@@ -2143,7 +2143,7 @@ struct drm_i915_private {
/* current hardware state */
union {
struct ilk_wm_values hw;
- struct skl_wm_values skl_hw;
+ struct skl_ddb_values skl_hw;
struct vlv_wm_values vlv;
struct g4x_wm_values g4x;
};
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 898064e..e74efb4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -480,7 +480,7 @@ struct intel_atomic_state {
bool skip_intermediate_wm;
/* Gen9+ only */
- struct skl_wm_values wm_results;
+ struct skl_ddb_values wm_results;
struct i915_sw_fence commit_ready;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7e15b26..6fec748 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5044,8 +5044,8 @@ skl_compute_ddb(struct drm_atomic_state *state)
}
static void
-skl_copy_wm_for_pipe(struct skl_wm_values *dst,
- struct skl_wm_values *src,
+skl_copy_ddb_for_pipe(struct skl_ddb_values *dst,
+ struct skl_ddb_values *src,
enum pipe pipe)
{
memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
@@ -5097,7 +5097,7 @@ skl_compute_wm(struct drm_atomic_state *state)
struct drm_crtc *crtc;
struct drm_crtc_state *cstate;
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
- struct skl_wm_values *results = &intel_state->wm_results;
+ struct skl_ddb_values *results = &intel_state->wm_results;
struct drm_device *dev = state->dev;
struct skl_pipe_wm *pipe_wm;
bool changed = false;
@@ -5199,8 +5199,8 @@ static void skl_initial_wm(struct intel_atomic_state *state,
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
struct drm_device *dev = intel_crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct skl_wm_values *results = &state->wm_results;
- struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
+ struct skl_ddb_values *results = &state->wm_results;
+ struct skl_ddb_values *hw_vals = &dev_priv->wm.skl_hw;
enum pipe pipe = intel_crtc->pipe;
if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
@@ -5211,7 +5211,7 @@ static void skl_initial_wm(struct intel_atomic_state *state,
if (cstate->base.active_changed)
skl_atomic_update_crtc_wm(state, cstate);
- skl_copy_wm_for_pipe(hw_vals, results, pipe);
+ skl_copy_ddb_for_pipe(hw_vals, results, pipe);
mutex_unlock(&dev_priv->wm.wm_mutex);
}
@@ -5343,7 +5343,7 @@ void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
void skl_wm_get_hw_state(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
+ struct skl_ddb_values *hw = &dev_priv->wm.skl_hw;
struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
struct drm_crtc *crtc;
struct intel_crtc *intel_crtc;
--
2.7.4
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^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 02/16] drm/i915/skl+: refactor WM calculation for NV12
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
2018-02-14 4:57 ` [PATCH 01/16] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values Vidya Srinivas
@ 2018-02-14 4:57 ` Vidya Srinivas
2018-02-14 4:57 ` [PATCH 03/16] drm/i915/skl+: add NV12 in skl_format_to_fourcc Vidya Srinivas
` (24 subsequent siblings)
26 siblings, 0 replies; 52+ messages in thread
From: Vidya Srinivas @ 2018-02-14 4:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
From: Mahesh Kumar <mahesh1.kumar@intel.com>
Current code calculates DDB for planar formats in such a way that we
store DDB of plane-0 in plane 1 & vice-versa.
In order to make this clean this patch refactors WM/DDB calculation for
NV12 planar formats.
v2: Addressed review comments by Maarten
v3: Rebased and addressed review comments by Maarten
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 5 +-
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 121 ++++++++++++++++++++-------------------
3 files changed, 66 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 564a364..b9914bb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1443,8 +1443,9 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
}
struct skl_ddb_allocation {
- struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
- struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
+ /* packed/y */
+ struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
+ struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
};
struct skl_ddb_values {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e74efb4..70447c6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -595,6 +595,7 @@ struct intel_pipe_wm {
struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level trans_wm;
+ bool is_planar;
};
struct skl_pipe_wm {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6fec748..0537567 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4012,9 +4012,9 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
static unsigned int
skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
const struct drm_plane_state *pstate,
- int y)
+ const int plane)
{
- struct intel_plane *plane = to_intel_plane(pstate->plane);
+ struct intel_plane *intel_plane = to_intel_plane(pstate->plane);
struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
uint32_t data_rate;
uint32_t width = 0, height = 0;
@@ -4028,9 +4028,9 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
fb = pstate->fb;
format = fb->format->format;
- if (plane->id == PLANE_CURSOR)
+ if (intel_plane->id == PLANE_CURSOR)
return 0;
- if (y && format != DRM_FORMAT_NV12)
+ if (plane == 1 && format != DRM_FORMAT_NV12)
return 0;
/*
@@ -4041,19 +4041,14 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
width = drm_rect_width(&intel_pstate->base.src) >> 16;
height = drm_rect_height(&intel_pstate->base.src) >> 16;
- /* for planar format */
- if (format == DRM_FORMAT_NV12) {
- if (y) /* y-plane data rate */
- data_rate = width * height *
- fb->format->cpp[0];
- else /* uv-plane data rate */
- data_rate = (width / 2) * (height / 2) *
- fb->format->cpp[1];
- } else {
- /* for packed formats */
- data_rate = width * height * fb->format->cpp[0];
+ /* UV plane does 1/2 pixel sub-sampling */
+ if (plane == 1 && format == DRM_FORMAT_NV12) {
+ width /= 2;
+ height /= 2;
}
+ data_rate = width * height * fb->format->cpp[plane];
+
down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);
return mul_round_up_u32_fixed16(data_rate, down_scale_amount);
@@ -4066,8 +4061,8 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
*/
static unsigned int
skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
- unsigned *plane_data_rate,
- unsigned *plane_y_data_rate)
+ unsigned int *plane_data_rate,
+ unsigned int *uv_plane_data_rate)
{
struct drm_crtc_state *cstate = &intel_cstate->base;
struct drm_atomic_state *state = cstate->state;
@@ -4083,17 +4078,17 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
enum plane_id plane_id = to_intel_plane(plane)->id;
unsigned int rate;
- /* packed/uv */
+ /* packed/y */
rate = skl_plane_relative_data_rate(intel_cstate,
pstate, 0);
plane_data_rate[plane_id] = rate;
total_data_rate += rate;
- /* y-plane */
+ /* uv-plane */
rate = skl_plane_relative_data_rate(intel_cstate,
pstate, 1);
- plane_y_data_rate[plane_id] = rate;
+ uv_plane_data_rate[plane_id] = rate;
total_data_rate += rate;
}
@@ -4102,8 +4097,7 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
}
static uint16_t
-skl_ddb_min_alloc(const struct drm_plane_state *pstate,
- const int y)
+skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
{
struct drm_framebuffer *fb = pstate->fb;
struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
@@ -4114,8 +4108,8 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate,
if (WARN_ON(!fb))
return 0;
- /* For packed formats, no y-plane, return 0 */
- if (y && fb->format->format != DRM_FORMAT_NV12)
+ /* For packed formats, and uv-plane, return 0 */
+ if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
return 0;
/* For Non Y-tile return 8-blocks */
@@ -4134,15 +4128,12 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate,
src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
/* Halve UV plane width and height for NV12 */
- if (fb->format->format == DRM_FORMAT_NV12 && !y) {
+ if (plane == 1) {
src_w /= 2;
src_h /= 2;
}
- if (fb->format->format == DRM_FORMAT_NV12 && !y)
- plane_bpp = fb->format->cpp[1];
- else
- plane_bpp = fb->format->cpp[0];
+ plane_bpp = fb->format->cpp[plane];
if (drm_rotation_90_or_270(pstate->rotation)) {
switch (plane_bpp) {
@@ -4170,7 +4161,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate,
static void
skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
- uint16_t *minimum, uint16_t *y_minimum)
+ uint16_t *minimum, uint16_t *uv_minimum)
{
const struct drm_plane_state *pstate;
struct drm_plane *plane;
@@ -4185,7 +4176,7 @@ skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
continue;
minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
- y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
+ uv_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
}
minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
@@ -4203,17 +4194,17 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
uint16_t alloc_size, start;
uint16_t minimum[I915_MAX_PLANES] = {};
- uint16_t y_minimum[I915_MAX_PLANES] = {};
+ uint16_t uv_minimum[I915_MAX_PLANES] = {};
unsigned int total_data_rate;
enum plane_id plane_id;
int num_active;
- unsigned plane_data_rate[I915_MAX_PLANES] = {};
- unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
+ unsigned int plane_data_rate[I915_MAX_PLANES] = {};
+ unsigned int uv_plane_data_rate[I915_MAX_PLANES] = {};
uint16_t total_min_blocks = 0;
/* Clear the partitioning for disabled planes. */
memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
- memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
+ memset(ddb->uv_plane[pipe], 0, sizeof(ddb->uv_plane[pipe]));
if (WARN_ON(!state))
return 0;
@@ -4228,7 +4219,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
if (alloc_size == 0)
return 0;
- skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
+ skl_ddb_calc_min(cstate, num_active, minimum, uv_minimum);
/*
* 1. Allocate the mininum required blocks for each active plane
@@ -4238,7 +4229,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
for_each_plane_id_on_crtc(intel_crtc, plane_id) {
total_min_blocks += minimum[plane_id];
- total_min_blocks += y_minimum[plane_id];
+ total_min_blocks += uv_minimum[plane_id];
}
if (total_min_blocks > alloc_size) {
@@ -4260,14 +4251,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
*/
total_data_rate = skl_get_total_relative_data_rate(cstate,
plane_data_rate,
- plane_y_data_rate);
+ uv_plane_data_rate);
if (total_data_rate == 0)
return 0;
start = alloc->start;
for_each_plane_id_on_crtc(intel_crtc, plane_id) {
- unsigned int data_rate, y_data_rate;
- uint16_t plane_blocks, y_plane_blocks = 0;
+ unsigned int data_rate, uv_data_rate;
+ uint16_t plane_blocks, uv_plane_blocks;
if (plane_id == PLANE_CURSOR)
continue;
@@ -4291,21 +4282,20 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
start += plane_blocks;
- /*
- * allocation for y_plane part of planar format:
- */
- y_data_rate = plane_y_data_rate[plane_id];
+ /* Allocate DDB for UV plane for planar format/NV12 */
+ uv_data_rate = uv_plane_data_rate[plane_id];
- y_plane_blocks = y_minimum[plane_id];
- y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
- total_data_rate);
+ uv_plane_blocks = uv_minimum[plane_id];
+ uv_plane_blocks += div_u64((uint64_t)alloc_size * uv_data_rate,
+ total_data_rate);
- if (y_data_rate) {
- ddb->y_plane[pipe][plane_id].start = start;
- ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks;
+ if (uv_data_rate) {
+ ddb->uv_plane[pipe][plane_id].start = start;
+ ddb->uv_plane[pipe][plane_id].end =
+ start + uv_plane_blocks;
}
- start += y_plane_blocks;
+ start += uv_plane_blocks;
}
return 0;
@@ -4433,8 +4423,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
wp->width = drm_rect_width(&intel_pstate->base.src) >> 16;
}
- wp->cpp = (fb->format->format == DRM_FORMAT_NV12) ? fb->format->cpp[1] :
- fb->format->cpp[0];
+ wp->cpp = fb->format->cpp[0];
wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
intel_pstate);
@@ -4663,6 +4652,9 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
return ret;
}
+ if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
+ wm->is_nv12 = true;
+
return 0;
}
@@ -4835,10 +4827,21 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
&ddb->plane[pipe][plane_id]);
- if (INTEL_GEN(dev_priv) < 11)
+ if (INTEL_GEN(dev_priv) >= 11)
+ return skl_ddb_entry_write(dev_priv,
+ PLANE_BUF_CFG(pipe, plane_id),
+ &ddb->plane[pipe][plane_id]);
+ if (wm->is_nv12) {
+ skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
+ &ddb->uv_plane[pipe][plane_id]);
skl_ddb_entry_write(dev_priv,
PLANE_NV12_BUF_CFG(pipe, plane_id),
- &ddb->y_plane[pipe][plane_id]);
+ &ddb->plane[pipe][plane_id]);
+ } else {
+ skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
+ &ddb->plane[pipe][plane_id]);
+ I915_WRITE(PLANE_NV12_BUF_CFG(pipe, plane_id), 0x0);
+ }
}
static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
@@ -4953,8 +4956,8 @@ skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
&new_ddb->plane[pipe][plane_id]) &&
- skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id],
- &new_ddb->y_plane[pipe][plane_id]))
+ skl_ddb_entry_equal(&cur_ddb->uv_plane[pipe][plane_id],
+ &new_ddb->uv_plane[pipe][plane_id]))
continue;
plane_state = drm_atomic_get_plane_state(state, plane);
@@ -5048,8 +5051,8 @@ skl_copy_ddb_for_pipe(struct skl_ddb_values *dst,
struct skl_ddb_values *src,
enum pipe pipe)
{
- memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
- sizeof(dst->ddb.y_plane[pipe]));
+ memcpy(dst->ddb.uv_plane[pipe], src->ddb.uv_plane[pipe],
+ sizeof(dst->ddb.uv_plane[pipe]));
memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
sizeof(dst->ddb.plane[pipe]));
}
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 03/16] drm/i915/skl+: add NV12 in skl_format_to_fourcc
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
2018-02-14 4:57 ` [PATCH 01/16] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values Vidya Srinivas
2018-02-14 4:57 ` [PATCH 02/16] drm/i915/skl+: refactor WM calculation for NV12 Vidya Srinivas
@ 2018-02-14 4:57 ` Vidya Srinivas
2018-02-14 4:57 ` [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12 Vidya Srinivas
` (23 subsequent siblings)
26 siblings, 0 replies; 52+ messages in thread
From: Vidya Srinivas @ 2018-02-14 4:57 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
Add support of recognizing DRM_FORMAT_NV12 from plane_format
register value.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 30e38cb..1617692 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2626,6 +2626,8 @@ static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
switch (format) {
case PLANE_CTL_FORMAT_RGB_565:
return DRM_FORMAT_RGB565;
+ case PLANE_CTL_FORMAT_NV12:
+ return DRM_FORMAT_NV12;
default:
case PLANE_CTL_FORMAT_XRGB_8888:
if (rgb_order) {
--
2.7.4
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^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
` (2 preceding siblings ...)
2018-02-14 4:57 ` [PATCH 03/16] drm/i915/skl+: add NV12 in skl_format_to_fourcc Vidya Srinivas
@ 2018-02-14 4:57 ` Vidya Srinivas
2018-02-14 9:36 ` Sharma, Shashank
2018-02-14 4:57 ` [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM Vidya Srinivas
` (22 subsequent siblings)
26 siblings, 1 reply; 52+ messages in thread
From: Vidya Srinivas @ 2018-02-14 4:57 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
For YUV 420 Planar formats like NV12,
buffer allocation is done for Y and UV surfaces separately.
For NV12 plane formats, the UV buffer
allocation must be programmed in the Plane Buffer Config register
and the Y buffer allocation must be programmed in the
Plane NV12 Buffer Config register. Both register values
should be verified during verify_wm_state.
v2: Addressed review comments by Maarten.
v2: Addressed review comments by Shashank Sharma.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 51 +++++++++++++++++++++++++++++-------
3 files changed, 43 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1617692..971bd04 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2621,7 +2621,7 @@ static int i9xx_format_to_fourcc(int format)
}
}
-static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
+int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
{
switch (format) {
case PLANE_CTL_FORMAT_RGB_565:
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 70447c6..f13decc 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1597,6 +1597,7 @@ u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state);
int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
+int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
/* intel_csr.c */
void intel_csr_ucode_init(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0537567..bc0e2bf 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3828,6 +3828,44 @@ static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
entry->end += 1;
}
+static void
+skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
+ const enum pipe pipe,
+ const enum plane_id plane_id,
+ struct skl_ddb_allocation *ddb /* out */)
+{
+ u32 val, val2 = 0;
+ int fourcc, pixel_format;
+
+ /* Cursor doesn't support NV12/planar, so no extra calculation needed */
+ if (plane_id == PLANE_CURSOR) {
+ val = I915_READ(CUR_BUF_CFG(pipe));
+ skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
+ return;
+ }
+
+ val = I915_READ(PLANE_CTL(pipe, plane_id));
+
+ /* No DDB allocated for disabled planes */
+ if (!(val & PLANE_CTL_ENABLE))
+ return;
+
+ pixel_format = val & PLANE_CTL_FORMAT_MASK;
+ fourcc = skl_format_to_fourcc(pixel_format,
+ val & PLANE_CTL_ORDER_RGBX,
+ val & PLANE_CTL_ALPHA_MASK);
+
+ val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
+ val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
+
+ if (fourcc == DRM_FORMAT_NV12) {
+ skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val2);
+ skl_ddb_entry_init_from_hw(&ddb->uv_plane[pipe][plane_id], val);
+ } else {
+ skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
+ }
+}
+
void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
struct skl_ddb_allocation *ddb /* out */)
{
@@ -3844,16 +3882,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
continue;
- for_each_plane_id_on_crtc(crtc, plane_id) {
- u32 val;
-
- if (plane_id != PLANE_CURSOR)
- val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
- else
- val = I915_READ(CUR_BUF_CFG(pipe));
-
- skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
- }
+ for_each_plane_id_on_crtc(crtc, plane_id)
+ skl_ddb_get_hw_plane_state(dev_priv, pipe,
+ plane_id, ddb);
intel_display_power_put(dev_priv, power_domain);
}
--
2.7.4
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^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12
2018-02-14 4:57 ` [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12 Vidya Srinivas
@ 2018-02-14 9:36 ` Sharma, Shashank
0 siblings, 0 replies; 52+ messages in thread
From: Sharma, Shashank @ 2018-02-14 9:36 UTC (permalink / raw)
To: Vidya Srinivas, intel-gfx
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Regards
Shashank
On 2/14/2018 10:27 AM, Vidya Srinivas wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> For YUV 420 Planar formats like NV12,
> buffer allocation is done for Y and UV surfaces separately.
> For NV12 plane formats, the UV buffer
> allocation must be programmed in the Plane Buffer Config register
> and the Y buffer allocation must be programmed in the
> Plane NV12 Buffer Config register. Both register values
> should be verified during verify_wm_state.
>
> v2: Addressed review comments by Maarten.
>
> v2: Addressed review comments by Shashank Sharma.
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 51 +++++++++++++++++++++++++++++-------
> 3 files changed, 43 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 1617692..971bd04 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2621,7 +2621,7 @@ static int i9xx_format_to_fourcc(int format)
> }
> }
>
> -static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> +int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> {
> switch (format) {
> case PLANE_CTL_FORMAT_RGB_565:
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 70447c6..f13decc 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1597,6 +1597,7 @@ u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
> int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
> struct intel_plane_state *plane_state);
> int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
> +int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
>
> /* intel_csr.c */
> void intel_csr_ucode_init(struct drm_i915_private *);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0537567..bc0e2bf 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3828,6 +3828,44 @@ static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
> entry->end += 1;
> }
>
> +static void
> +skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
> + const enum pipe pipe,
> + const enum plane_id plane_id,
> + struct skl_ddb_allocation *ddb /* out */)
> +{
> + u32 val, val2 = 0;
> + int fourcc, pixel_format;
> +
> + /* Cursor doesn't support NV12/planar, so no extra calculation needed */
> + if (plane_id == PLANE_CURSOR) {
> + val = I915_READ(CUR_BUF_CFG(pipe));
> + skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
> + return;
> + }
> +
> + val = I915_READ(PLANE_CTL(pipe, plane_id));
> +
> + /* No DDB allocated for disabled planes */
> + if (!(val & PLANE_CTL_ENABLE))
> + return;
> +
> + pixel_format = val & PLANE_CTL_FORMAT_MASK;
> + fourcc = skl_format_to_fourcc(pixel_format,
> + val & PLANE_CTL_ORDER_RGBX,
> + val & PLANE_CTL_ALPHA_MASK);
> +
> + val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
> + val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
> +
> + if (fourcc == DRM_FORMAT_NV12) {
> + skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val2);
> + skl_ddb_entry_init_from_hw(&ddb->uv_plane[pipe][plane_id], val);
> + } else {
> + skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
> + }
> +}
> +
> void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
> struct skl_ddb_allocation *ddb /* out */)
> {
> @@ -3844,16 +3882,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
> if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
> continue;
>
> - for_each_plane_id_on_crtc(crtc, plane_id) {
> - u32 val;
> -
> - if (plane_id != PLANE_CURSOR)
> - val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
> - else
> - val = I915_READ(CUR_BUF_CFG(pipe));
> -
> - skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
> - }
> + for_each_plane_id_on_crtc(crtc, plane_id)
> + skl_ddb_get_hw_plane_state(dev_priv, pipe,
> + plane_id, ddb);
>
> intel_display_power_put(dev_priv, power_domain);
> }
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
` (3 preceding siblings ...)
2018-02-14 4:57 ` [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12 Vidya Srinivas
@ 2018-02-14 4:57 ` Vidya Srinivas
2018-02-14 9:41 ` Sharma, Shashank
2018-02-14 4:57 ` [PATCH 06/16] drm/i915/skl+: pass skl_wm_level struct to wm compute func Vidya Srinivas
` (21 subsequent siblings)
26 siblings, 1 reply; 52+ messages in thread
From: Vidya Srinivas @ 2018-02-14 4:57 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.
v2: Addressed review comments from Shashank Sharma.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 55 +++++++++++++++++++++++++++++++---------
3 files changed, 45 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b9914bb..9a9a645 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1463,6 +1463,7 @@ struct skl_wm_level {
struct skl_wm_params {
bool x_tiled, y_tiled;
bool rc_surface;
+ bool is_planar;
uint32_t width;
uint8_t cpp;
uint32_t plane_pixel_rate;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f13decc..6402d6d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -594,6 +594,7 @@ struct intel_pipe_wm {
struct skl_plane_wm {
struct skl_wm_level wm[8];
+ struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
bool is_planar;
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bc0e2bf..2a0cc0b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4422,7 +4422,7 @@ static int
skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
struct intel_crtc_state *cstate,
const struct intel_plane_state *intel_pstate,
- struct skl_wm_params *wp)
+ struct skl_wm_params *wp, int plane_num)
{
struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
const struct drm_plane_state *pstate = &intel_pstate->base;
@@ -4435,6 +4435,12 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
if (!intel_wm_plane_visible(cstate, intel_pstate))
return 0;
+ /* only NV12 format has two planes */
+ if (plane_num == 1 && fb->format->format != DRM_FORMAT_NV12) {
+ DRM_DEBUG_KMS("Non NV12 format have single plane\n");
+ return -EINVAL;
+ }
+
wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
@@ -4442,6 +4448,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+ wp->is_planar = fb->format->format == DRM_FORMAT_NV12;
if (plane->id == PLANE_CURSOR) {
wp->width = intel_pstate->base.crtc_w;
@@ -4454,7 +4461,10 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
wp->width = drm_rect_width(&intel_pstate->base.src) >> 16;
}
- wp->cpp = fb->format->cpp[0];
+ if (plane_num == 1 && wp->is_planar)
+ wp->width /= 2;
+
+ wp->cpp = fb->format->cpp[plane_num];
wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
intel_pstate);
@@ -4652,7 +4662,8 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
struct intel_crtc_state *cstate,
const struct intel_plane_state *intel_pstate,
const struct skl_wm_params *wm_params,
- struct skl_plane_wm *wm)
+ struct skl_plane_wm *wm,
+ int plane_num)
{
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
struct drm_plane *plane = intel_pstate->base.plane;
@@ -4660,15 +4671,19 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
uint16_t ddb_blocks;
enum pipe pipe = intel_crtc->pipe;
int level, max_level = ilk_wm_max_level(dev_priv);
+ enum plane_id plane_id = intel_plane->id;
int ret;
if (WARN_ON(!intel_pstate->base.fb))
return -EINVAL;
- ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
+ ddb_blocks = plane_num ?
+ skl_ddb_entry_size(&ddb->uv_plane[pipe][plane_id]) :
+ skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
for (level = 0; level <= max_level; level++) {
- struct skl_wm_level *result = &wm->wm[level];
+ struct skl_wm_level *result = plane_num ? &wm->uv_wm[level] :
+ &wm->wm[level];
ret = skl_compute_plane_wm(dev_priv,
cstate,
@@ -4683,9 +4698,6 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
return ret;
}
- if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
- wm->is_nv12 = true;
-
return 0;
}
@@ -4794,20 +4806,39 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
wm = &pipe_wm->planes[plane_id];
ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
- memset(&wm_params, 0, sizeof(struct skl_wm_params));
ret = skl_compute_plane_wm_params(dev_priv, cstate,
- intel_pstate, &wm_params);
+ intel_pstate, &wm_params, 0);
if (ret)
return ret;
ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
- intel_pstate, &wm_params, wm);
+ intel_pstate, &wm_params, wm, 0);
if (ret)
return ret;
+
skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0],
ddb_blocks, &wm->trans_wm);
+
+ /* uv plane watermarks must also be validated for NV12/Planar */
+ if (wm_params.is_planar) {
+ memset(&wm_params, 0, sizeof(struct skl_wm_params));
+ wm->is_planar = true;
+
+ ret = skl_compute_plane_wm_params(dev_priv, cstate,
+ intel_pstate,
+ &wm_params, 1);
+ if (ret)
+ return ret;
+
+ ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
+ intel_pstate, &wm_params,
+ wm, 1);
+ if (ret)
+ return ret;
+ }
}
+
pipe_wm->linetime = skl_compute_linetime_wm(cstate);
return 0;
@@ -4862,7 +4893,7 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
return skl_ddb_entry_write(dev_priv,
PLANE_BUF_CFG(pipe, plane_id),
&ddb->plane[pipe][plane_id]);
- if (wm->is_nv12) {
+ if (wm->is_planar) {
skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
&ddb->uv_plane[pipe][plane_id]);
skl_ddb_entry_write(dev_priv,
--
2.7.4
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^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM
2018-02-14 4:57 ` [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM Vidya Srinivas
@ 2018-02-14 9:41 ` Sharma, Shashank
0 siblings, 0 replies; 52+ messages in thread
From: Sharma, Shashank @ 2018-02-14 9:41 UTC (permalink / raw)
To: Vidya Srinivas, intel-gfx
Ideal case would have been an enum for nv12 planes with y and uv
parameters, to indicate in code, but I will at least prefer the
plane_num variable should be replaced by plane_id, as plane_number 0 and
1 confuses.
With that change, feel free to use:
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Regards
Shashank
On 2/14/2018 10:27 AM, Vidya Srinivas wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> NV12 requires WM calculation for UV plane as well.
> UV plane WM should also fulfill all the WM related restrictions.
>
> v2: Addressed review comments from Shashank Sharma.
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 55 +++++++++++++++++++++++++++++++---------
> 3 files changed, 45 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b9914bb..9a9a645 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1463,6 +1463,7 @@ struct skl_wm_level {
> struct skl_wm_params {
> bool x_tiled, y_tiled;
> bool rc_surface;
> + bool is_planar;
> uint32_t width;
> uint8_t cpp;
> uint32_t plane_pixel_rate;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index f13decc..6402d6d 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -594,6 +594,7 @@ struct intel_pipe_wm {
>
> struct skl_plane_wm {
> struct skl_wm_level wm[8];
> + struct skl_wm_level uv_wm[8];
> struct skl_wm_level trans_wm;
> bool is_planar;
> };
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index bc0e2bf..2a0cc0b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4422,7 +4422,7 @@ static int
> skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
> struct intel_crtc_state *cstate,
> const struct intel_plane_state *intel_pstate,
> - struct skl_wm_params *wp)
> + struct skl_wm_params *wp, int plane_num)
> {
> struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
> const struct drm_plane_state *pstate = &intel_pstate->base;
> @@ -4435,6 +4435,12 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
> if (!intel_wm_plane_visible(cstate, intel_pstate))
> return 0;
>
> + /* only NV12 format has two planes */
> + if (plane_num == 1 && fb->format->format != DRM_FORMAT_NV12) {
> + DRM_DEBUG_KMS("Non NV12 format have single plane\n");
> + return -EINVAL;
> + }
> +
> wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
> fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
> fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> @@ -4442,6 +4448,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
> wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
> wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> + wp->is_planar = fb->format->format == DRM_FORMAT_NV12;
>
> if (plane->id == PLANE_CURSOR) {
> wp->width = intel_pstate->base.crtc_w;
> @@ -4454,7 +4461,10 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
> wp->width = drm_rect_width(&intel_pstate->base.src) >> 16;
> }
>
> - wp->cpp = fb->format->cpp[0];
> + if (plane_num == 1 && wp->is_planar)
> + wp->width /= 2;
> +
> + wp->cpp = fb->format->cpp[plane_num];
> wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
> intel_pstate);
>
> @@ -4652,7 +4662,8 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
> struct intel_crtc_state *cstate,
> const struct intel_plane_state *intel_pstate,
> const struct skl_wm_params *wm_params,
> - struct skl_plane_wm *wm)
> + struct skl_plane_wm *wm,
> + int plane_num)
> {
> struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
> struct drm_plane *plane = intel_pstate->base.plane;
> @@ -4660,15 +4671,19 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
> uint16_t ddb_blocks;
> enum pipe pipe = intel_crtc->pipe;
> int level, max_level = ilk_wm_max_level(dev_priv);
> + enum plane_id plane_id = intel_plane->id;
> int ret;
>
> if (WARN_ON(!intel_pstate->base.fb))
> return -EINVAL;
>
> - ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
> + ddb_blocks = plane_num ?
> + skl_ddb_entry_size(&ddb->uv_plane[pipe][plane_id]) :
> + skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
>
> for (level = 0; level <= max_level; level++) {
> - struct skl_wm_level *result = &wm->wm[level];
> + struct skl_wm_level *result = plane_num ? &wm->uv_wm[level] :
> + &wm->wm[level];
>
> ret = skl_compute_plane_wm(dev_priv,
> cstate,
> @@ -4683,9 +4698,6 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
> return ret;
> }
>
> - if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
> - wm->is_nv12 = true;
> -
> return 0;
> }
>
> @@ -4794,20 +4806,39 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
>
> wm = &pipe_wm->planes[plane_id];
> ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
> - memset(&wm_params, 0, sizeof(struct skl_wm_params));
>
> ret = skl_compute_plane_wm_params(dev_priv, cstate,
> - intel_pstate, &wm_params);
> + intel_pstate, &wm_params, 0);
> if (ret)
> return ret;
>
> ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
> - intel_pstate, &wm_params, wm);
> + intel_pstate, &wm_params, wm, 0);
> if (ret)
> return ret;
> +
> skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0],
> ddb_blocks, &wm->trans_wm);
> +
> + /* uv plane watermarks must also be validated for NV12/Planar */
> + if (wm_params.is_planar) {
> + memset(&wm_params, 0, sizeof(struct skl_wm_params));
> + wm->is_planar = true;
> +
> + ret = skl_compute_plane_wm_params(dev_priv, cstate,
> + intel_pstate,
> + &wm_params, 1);
> + if (ret)
> + return ret;
> +
> + ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
> + intel_pstate, &wm_params,
> + wm, 1);
> + if (ret)
> + return ret;
> + }
> }
> +
> pipe_wm->linetime = skl_compute_linetime_wm(cstate);
>
> return 0;
> @@ -4862,7 +4893,7 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
> return skl_ddb_entry_write(dev_priv,
> PLANE_BUF_CFG(pipe, plane_id),
> &ddb->plane[pipe][plane_id]);
> - if (wm->is_nv12) {
> + if (wm->is_planar) {
> skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
> &ddb->uv_plane[pipe][plane_id]);
> skl_ddb_entry_write(dev_priv,
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^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 06/16] drm/i915/skl+: pass skl_wm_level struct to wm compute func
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
` (4 preceding siblings ...)
2018-02-14 4:57 ` [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM Vidya Srinivas
@ 2018-02-14 4:57 ` Vidya Srinivas
2018-02-14 4:57 ` [PATCH 07/16] drm/i915/skl+: make sure higher latency level has higher wm value Vidya Srinivas
` (20 subsequent siblings)
26 siblings, 0 replies; 52+ messages in thread
From: Vidya Srinivas @ 2018-02-14 4:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
From: Mahesh Kumar <mahesh1.kumar@intel.com>
This patch passes skl_wm_level structure itself to watermark
computation function skl_compute_plane_wm function (instead
of its internal parameters). It reduces number of arguments
required to be passed.
v2: Addressed review comments by Shashank Sharma
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 18 +++++++-----------
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2a0cc0b..f6ad1bf 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4532,9 +4532,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
uint16_t ddb_allocation,
int level,
const struct skl_wm_params *wp,
- uint16_t *out_blocks, /* out */
- uint8_t *out_lines, /* out */
- bool *enabled /* out */)
+ struct skl_wm_level *result /* out */)
{
const struct drm_plane_state *pstate = &intel_pstate->base;
uint32_t latency = dev_priv->wm.skl_latency[level];
@@ -4548,7 +4546,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
if (latency == 0 ||
!intel_wm_plane_visible(cstate, intel_pstate)) {
- *enabled = false;
+ result->plane_en = false;
return 0;
}
@@ -4629,7 +4627,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
if ((level > 0 && res_lines > 31) ||
res_blocks >= ddb_allocation ||
min_disp_buf_needed >= ddb_allocation) {
- *enabled = false;
+ result->plane_en = false;
/*
* If there are no valid level 0 watermarks, then we can't
@@ -4649,9 +4647,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
}
/* The number of lines are ignored for the level 0 watermark. */
- *out_lines = level ? res_lines : 0;
- *out_blocks = res_blocks;
- *enabled = true;
+ result->plane_res_b = res_blocks;
+ result->plane_res_l = res_lines;
+ result->plane_en = true;
return 0;
}
@@ -4691,9 +4689,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
ddb_blocks,
level,
wm_params,
- &result->plane_res_b,
- &result->plane_res_l,
- &result->plane_en);
+ result);
if (ret)
return ret;
}
--
2.7.4
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^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 07/16] drm/i915/skl+: make sure higher latency level has higher wm value
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
` (5 preceding siblings ...)
2018-02-14 4:57 ` [PATCH 06/16] drm/i915/skl+: pass skl_wm_level struct to wm compute func Vidya Srinivas
@ 2018-02-14 4:57 ` Vidya Srinivas
2018-02-14 4:57 ` [PATCH 08/16] drm/i915/skl+: nv12 workaround disable WM level 1-7 Vidya Srinivas
` (19 subsequent siblings)
26 siblings, 0 replies; 52+ messages in thread
From: Vidya Srinivas @ 2018-02-14 4:57 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
DDB allocation optimization algorithm requires/assumes ddb allocation for
any memory C-state level DDB value to be as high as level below the
current level. Render decompression requires level WM to be as high as
wm level-0. This patch fulfils both the requirements.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f6ad1bf..d617fee 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4532,6 +4532,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
uint16_t ddb_allocation,
int level,
const struct skl_wm_params *wp,
+ const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */)
{
const struct drm_plane_state *pstate = &intel_pstate->base;
@@ -4599,6 +4600,15 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
} else {
res_blocks++;
}
+
+ /*
+ * Make sure result blocks for higher latency levels are atleast
+ * as high as level below the current level.
+ * Assumption in DDB algorithm optimization for special cases.
+ * Also covers Display WA #1125 for RC.
+ */
+ if (result_prev->plane_res_b > res_blocks)
+ res_blocks = result_prev->plane_res_b;
}
if (INTEL_GEN(dev_priv) >= 11) {
@@ -4682,6 +4692,13 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = plane_num ? &wm->uv_wm[level] :
&wm->wm[level];
+ struct skl_wm_level *result_prev;
+
+ if (level)
+ result_prev = plane_num ? &wm->uv_wm[level - 1] :
+ &wm->wm[level - 1];
+ else
+ result_prev = plane_num ? &wm->uv_wm[0] : &wm->wm[0];
ret = skl_compute_plane_wm(dev_priv,
cstate,
@@ -4689,6 +4706,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
ddb_blocks,
level,
wm_params,
+ result_prev,
result);
if (ret)
return ret;
--
2.7.4
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^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 08/16] drm/i915/skl+: nv12 workaround disable WM level 1-7
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
` (6 preceding siblings ...)
2018-02-14 4:57 ` [PATCH 07/16] drm/i915/skl+: make sure higher latency level has higher wm value Vidya Srinivas
@ 2018-02-14 4:57 ` Vidya Srinivas
2018-02-14 9:47 ` Sharma, Shashank
2018-02-14 4:57 ` [PATCH 09/16] drm/i915/skl: split skl_compute_ddb function Vidya Srinivas
` (18 subsequent siblings)
26 siblings, 1 reply; 52+ messages in thread
From: Vidya Srinivas @ 2018-02-14 4:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
From: Mahesh Kumar <mahesh1.kumar@intel.com>
Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A)
Hardware sometimes fails to wake memory from pkg C states fetching the
last few lines of planar YUV 420 (NV12) planes. This causes
intermittent underflow and corruption.
WA: Disable package C states or do not enable latency levels 1 through 7
(WM1 - WM7) on NV12 planes.
v2: Addressed review comments by Maarten.
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d617fee..d9f6563 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4656,6 +4656,17 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
}
}
+ /*
+ * Display WA #826 (SKL:ALL, BXT:ALL) & #1059 (CNL:A)
+ * disable wm level 1-7 on NV12 planes
+ */
+ if (wp->is_planar && (level >= 1) &&
+ (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
+ IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {
+ result->plane_en = false;
+ return 0;
+ }
+
/* The number of lines are ignored for the level 0 watermark. */
result->plane_res_b = res_blocks;
result->plane_res_l = res_lines;
--
2.7.4
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^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 08/16] drm/i915/skl+: nv12 workaround disable WM level 1-7
2018-02-14 4:57 ` [PATCH 08/16] drm/i915/skl+: nv12 workaround disable WM level 1-7 Vidya Srinivas
@ 2018-02-14 9:47 ` Sharma, Shashank
0 siblings, 0 replies; 52+ messages in thread
From: Sharma, Shashank @ 2018-02-14 9:47 UTC (permalink / raw)
To: Vidya Srinivas, intel-gfx
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Regards
Shashank
On 2/14/2018 10:27 AM, Vidya Srinivas wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A)
> Hardware sometimes fails to wake memory from pkg C states fetching the
> last few lines of planar YUV 420 (NV12) planes. This causes
> intermittent underflow and corruption.
> WA: Disable package C states or do not enable latency levels 1 through 7
> (WM1 - WM7) on NV12 planes.
>
> v2: Addressed review comments by Maarten.
>
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d617fee..d9f6563 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4656,6 +4656,17 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> }
> }
>
> + /*
> + * Display WA #826 (SKL:ALL, BXT:ALL) & #1059 (CNL:A)
> + * disable wm level 1-7 on NV12 planes
> + */
> + if (wp->is_planar && (level >= 1) &&
> + (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
> + IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {
> + result->plane_en = false;
> + return 0;
> + }
> +
> /* The number of lines are ignored for the level 0 watermark. */
> result->plane_res_b = res_blocks;
> result->plane_res_l = res_lines;
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^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 09/16] drm/i915/skl: split skl_compute_ddb function
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
` (7 preceding siblings ...)
2018-02-14 4:57 ` [PATCH 08/16] drm/i915/skl+: nv12 workaround disable WM level 1-7 Vidya Srinivas
@ 2018-02-14 4:57 ` Vidya Srinivas
2018-02-14 10:02 ` Sharma, Shashank
2018-02-14 4:57 ` [PATCH 10/16] drm/i915: Set scaler mode for NV12 Vidya Srinivas
` (17 subsequent siblings)
26 siblings, 1 reply; 52+ messages in thread
From: Vidya Srinivas @ 2018-02-14 4:57 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
This patch splits skl_compute_wm/ddb functions into two parts.
One adds all affected pipes after the commit to atomic_state structure
and second part does compute the DDB.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 157 ++++++++++++++++++++++------------------
1 file changed, 88 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d9f6563..ca3a783 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5058,69 +5058,16 @@ skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
static int
skl_compute_ddb(struct drm_atomic_state *state)
{
- struct drm_device *dev = state->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ const struct drm_i915_private *dev_priv = to_i915(state->dev);
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
- struct intel_crtc *intel_crtc;
struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
- uint32_t realloc_pipes = pipes_modified(state);
- int ret;
-
- /*
- * If this is our first atomic update following hardware readout,
- * we can't trust the DDB that the BIOS programmed for us. Let's
- * pretend that all pipes switched active status so that we'll
- * ensure a full DDB recompute.
- */
- if (dev_priv->wm.distrust_bios_wm) {
- ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
- state->acquire_ctx);
- if (ret)
- return ret;
-
- intel_state->active_pipe_changes = ~0;
-
- /*
- * We usually only initialize intel_state->active_crtcs if we
- * we're doing a modeset; make sure this field is always
- * initialized during the sanitization process that happens
- * on the first commit too.
- */
- if (!intel_state->modeset)
- intel_state->active_crtcs = dev_priv->active_crtcs;
- }
-
- /*
- * If the modeset changes which CRTC's are active, we need to
- * recompute the DDB allocation for *all* active pipes, even
- * those that weren't otherwise being modified in any way by this
- * atomic commit. Due to the shrinking of the per-pipe allocations
- * when new active CRTC's are added, it's possible for a pipe that
- * we were already using and aren't changing at all here to suddenly
- * become invalid if its DDB needs exceeds its new allocation.
- *
- * Note that if we wind up doing a full DDB recompute, we can't let
- * any other display updates race with this transaction, so we need
- * to grab the lock on *all* CRTC's.
- */
- if (intel_state->active_pipe_changes) {
- realloc_pipes = ~0;
- intel_state->wm_results.dirty_pipes = ~0;
- }
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *cstate;
+ int ret, i;
- /*
- * We're not recomputing for the pipes not included in the commit, so
- * make sure we start with the current state.
- */
memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
- for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
- struct intel_crtc_state *cstate;
-
- cstate = intel_atomic_get_crtc_state(state, intel_crtc);
- if (IS_ERR(cstate))
- return PTR_ERR(cstate);
-
+ for_each_new_intel_crtc_in_state(intel_state, crtc, cstate, i) {
ret = skl_allocate_pipe_ddb(cstate, ddb);
if (ret)
return ret;
@@ -5182,23 +5129,23 @@ skl_print_wm_changes(const struct drm_atomic_state *state)
}
static int
-skl_compute_wm(struct drm_atomic_state *state)
+skl_ddb_add_affected_pipes(struct drm_atomic_state *state, bool *changed)
{
- struct drm_crtc *crtc;
- struct drm_crtc_state *cstate;
- struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
- struct skl_ddb_values *results = &intel_state->wm_results;
struct drm_device *dev = state->dev;
- struct skl_pipe_wm *pipe_wm;
- bool changed = false;
+ const struct drm_i915_private *dev_priv = to_i915(dev);
+ const struct drm_crtc *crtc;
+ const struct drm_crtc_state *cstate;
+ struct intel_crtc *intel_crtc;
+ struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+ uint32_t realloc_pipes = pipes_modified(state);
int ret, i;
/*
* When we distrust bios wm we always need to recompute to set the
* expected DDB allocations for each CRTC.
*/
- if (to_i915(dev)->wm.distrust_bios_wm)
- changed = true;
+ if (dev_priv->wm.distrust_bios_wm)
+ *changed = true;
/*
* If this transaction isn't actually touching any CRTC's, don't
@@ -5209,14 +5156,86 @@ skl_compute_wm(struct drm_atomic_state *state)
* hold _all_ CRTC state mutexes.
*/
for_each_new_crtc_in_state(state, crtc, cstate, i)
- changed = true;
+ *changed = true;
- if (!changed)
+ if (!*changed)
return 0;
+ /*
+ * If this is our first atomic update following hardware readout,
+ * we can't trust the DDB that the BIOS programmed for us. Let's
+ * pretend that all pipes switched active status so that we'll
+ * ensure a full DDB recompute.
+ */
+ if (dev_priv->wm.distrust_bios_wm) {
+ ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
+ state->acquire_ctx);
+ if (ret)
+ return ret;
+
+ intel_state->active_pipe_changes = ~0;
+
+ /*
+ * We usually only initialize intel_state->active_crtcs if we
+ * we're doing a modeset; make sure this field is always
+ * initialized during the sanitization process that happens
+ * on the first commit too.
+ */
+ if (!intel_state->modeset)
+ intel_state->active_crtcs = dev_priv->active_crtcs;
+ }
+
+ /*
+ * If the modeset changes which CRTC's are active, we need to
+ * recompute the DDB allocation for *all* active pipes, even
+ * those that weren't otherwise being modified in any way by this
+ * atomic commit. Due to the shrinking of the per-pipe allocations
+ * when new active CRTC's are added, it's possible for a pipe that
+ * we were already using and aren't changing at all here to suddenly
+ * become invalid if its DDB needs exceeds its new allocation.
+ *
+ * Note that if we wind up doing a full DDB recompute, we can't let
+ * any other display updates race with this transaction, so we need
+ * to grab the lock on *all* CRTC's.
+ */
+ if (intel_state->active_pipe_changes) {
+ realloc_pipes = ~0;
+ intel_state->wm_results.dirty_pipes = ~0;
+ }
+
+ /*
+ * We're not recomputing for the pipes not included in the commit, so
+ * make sure we start with the current state.
+ */
+ for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
+ struct intel_crtc_state *cstate;
+
+ cstate = intel_atomic_get_crtc_state(state, intel_crtc);
+ if (IS_ERR(cstate))
+ return PTR_ERR(cstate);
+ }
+
+ return 0;
+}
+
+static int
+skl_compute_wm(struct drm_atomic_state *state)
+{
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *cstate;
+ struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+ struct skl_ddb_values *results = &intel_state->wm_results;
+ struct skl_pipe_wm *pipe_wm;
+ bool changed = false;
+ int ret, i;
+
/* Clear all dirty flags */
results->dirty_pipes = 0;
+ ret = skl_ddb_add_affected_pipes(state, &changed);
+ if (ret || !changed)
+ return ret;
+
ret = skl_compute_ddb(state);
if (ret)
return ret;
--
2.7.4
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^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 09/16] drm/i915/skl: split skl_compute_ddb function
2018-02-14 4:57 ` [PATCH 09/16] drm/i915/skl: split skl_compute_ddb function Vidya Srinivas
@ 2018-02-14 10:02 ` Sharma, Shashank
0 siblings, 0 replies; 52+ messages in thread
From: Sharma, Shashank @ 2018-02-14 10:02 UTC (permalink / raw)
To: Vidya Srinivas, intel-gfx
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Regards
Shashank
On 2/14/2018 10:27 AM, Vidya Srinivas wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> This patch splits skl_compute_wm/ddb functions into two parts.
> One adds all affected pipes after the commit to atomic_state structure
> and second part does compute the DDB.
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 157 ++++++++++++++++++++++------------------
> 1 file changed, 88 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d9f6563..ca3a783 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5058,69 +5058,16 @@ skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
> static int
> skl_compute_ddb(struct drm_atomic_state *state)
> {
> - struct drm_device *dev = state->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + const struct drm_i915_private *dev_priv = to_i915(state->dev);
> struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> - struct intel_crtc *intel_crtc;
> struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
> - uint32_t realloc_pipes = pipes_modified(state);
> - int ret;
> -
> - /*
> - * If this is our first atomic update following hardware readout,
> - * we can't trust the DDB that the BIOS programmed for us. Let's
> - * pretend that all pipes switched active status so that we'll
> - * ensure a full DDB recompute.
> - */
> - if (dev_priv->wm.distrust_bios_wm) {
> - ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
> - state->acquire_ctx);
> - if (ret)
> - return ret;
> -
> - intel_state->active_pipe_changes = ~0;
> -
> - /*
> - * We usually only initialize intel_state->active_crtcs if we
> - * we're doing a modeset; make sure this field is always
> - * initialized during the sanitization process that happens
> - * on the first commit too.
> - */
> - if (!intel_state->modeset)
> - intel_state->active_crtcs = dev_priv->active_crtcs;
> - }
> -
> - /*
> - * If the modeset changes which CRTC's are active, we need to
> - * recompute the DDB allocation for *all* active pipes, even
> - * those that weren't otherwise being modified in any way by this
> - * atomic commit. Due to the shrinking of the per-pipe allocations
> - * when new active CRTC's are added, it's possible for a pipe that
> - * we were already using and aren't changing at all here to suddenly
> - * become invalid if its DDB needs exceeds its new allocation.
> - *
> - * Note that if we wind up doing a full DDB recompute, we can't let
> - * any other display updates race with this transaction, so we need
> - * to grab the lock on *all* CRTC's.
> - */
> - if (intel_state->active_pipe_changes) {
> - realloc_pipes = ~0;
> - intel_state->wm_results.dirty_pipes = ~0;
> - }
> + struct intel_crtc *crtc;
> + struct intel_crtc_state *cstate;
> + int ret, i;
>
> - /*
> - * We're not recomputing for the pipes not included in the commit, so
> - * make sure we start with the current state.
> - */
> memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
>
> - for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
> - struct intel_crtc_state *cstate;
> -
> - cstate = intel_atomic_get_crtc_state(state, intel_crtc);
> - if (IS_ERR(cstate))
> - return PTR_ERR(cstate);
> -
> + for_each_new_intel_crtc_in_state(intel_state, crtc, cstate, i) {
> ret = skl_allocate_pipe_ddb(cstate, ddb);
> if (ret)
> return ret;
> @@ -5182,23 +5129,23 @@ skl_print_wm_changes(const struct drm_atomic_state *state)
> }
>
> static int
> -skl_compute_wm(struct drm_atomic_state *state)
> +skl_ddb_add_affected_pipes(struct drm_atomic_state *state, bool *changed)
> {
> - struct drm_crtc *crtc;
> - struct drm_crtc_state *cstate;
> - struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> - struct skl_ddb_values *results = &intel_state->wm_results;
> struct drm_device *dev = state->dev;
> - struct skl_pipe_wm *pipe_wm;
> - bool changed = false;
> + const struct drm_i915_private *dev_priv = to_i915(dev);
> + const struct drm_crtc *crtc;
> + const struct drm_crtc_state *cstate;
> + struct intel_crtc *intel_crtc;
> + struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> + uint32_t realloc_pipes = pipes_modified(state);
> int ret, i;
>
> /*
> * When we distrust bios wm we always need to recompute to set the
> * expected DDB allocations for each CRTC.
> */
> - if (to_i915(dev)->wm.distrust_bios_wm)
> - changed = true;
> + if (dev_priv->wm.distrust_bios_wm)
> + *changed = true;
>
> /*
> * If this transaction isn't actually touching any CRTC's, don't
> @@ -5209,14 +5156,86 @@ skl_compute_wm(struct drm_atomic_state *state)
> * hold _all_ CRTC state mutexes.
> */
> for_each_new_crtc_in_state(state, crtc, cstate, i)
> - changed = true;
> + *changed = true;
>
> - if (!changed)
> + if (!*changed)
> return 0;
>
> + /*
> + * If this is our first atomic update following hardware readout,
> + * we can't trust the DDB that the BIOS programmed for us. Let's
> + * pretend that all pipes switched active status so that we'll
> + * ensure a full DDB recompute.
> + */
> + if (dev_priv->wm.distrust_bios_wm) {
> + ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
> + state->acquire_ctx);
> + if (ret)
> + return ret;
> +
> + intel_state->active_pipe_changes = ~0;
> +
> + /*
> + * We usually only initialize intel_state->active_crtcs if we
> + * we're doing a modeset; make sure this field is always
> + * initialized during the sanitization process that happens
> + * on the first commit too.
> + */
> + if (!intel_state->modeset)
> + intel_state->active_crtcs = dev_priv->active_crtcs;
> + }
> +
> + /*
> + * If the modeset changes which CRTC's are active, we need to
> + * recompute the DDB allocation for *all* active pipes, even
> + * those that weren't otherwise being modified in any way by this
> + * atomic commit. Due to the shrinking of the per-pipe allocations
> + * when new active CRTC's are added, it's possible for a pipe that
> + * we were already using and aren't changing at all here to suddenly
> + * become invalid if its DDB needs exceeds its new allocation.
> + *
> + * Note that if we wind up doing a full DDB recompute, we can't let
> + * any other display updates race with this transaction, so we need
> + * to grab the lock on *all* CRTC's.
> + */
> + if (intel_state->active_pipe_changes) {
> + realloc_pipes = ~0;
> + intel_state->wm_results.dirty_pipes = ~0;
> + }
> +
> + /*
> + * We're not recomputing for the pipes not included in the commit, so
> + * make sure we start with the current state.
> + */
> + for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
> + struct intel_crtc_state *cstate;
> +
> + cstate = intel_atomic_get_crtc_state(state, intel_crtc);
> + if (IS_ERR(cstate))
> + return PTR_ERR(cstate);
> + }
> +
> + return 0;
> +}
> +
> +static int
> +skl_compute_wm(struct drm_atomic_state *state)
> +{
> + struct drm_crtc *crtc;
> + struct drm_crtc_state *cstate;
> + struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> + struct skl_ddb_values *results = &intel_state->wm_results;
> + struct skl_pipe_wm *pipe_wm;
> + bool changed = false;
> + int ret, i;
> +
> /* Clear all dirty flags */
> results->dirty_pipes = 0;
>
> + ret = skl_ddb_add_affected_pipes(state, &changed);
> + if (ret || !changed)
> + return ret;
> +
> ret = skl_compute_ddb(state);
> if (ret)
> return ret;
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 10/16] drm/i915: Set scaler mode for NV12
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
` (8 preceding siblings ...)
2018-02-14 4:57 ` [PATCH 09/16] drm/i915/skl: split skl_compute_ddb function Vidya Srinivas
@ 2018-02-14 4:57 ` Vidya Srinivas
2018-02-15 6:32 ` Sharma, Shashank
2018-02-14 4:57 ` [PATCH 11/16] drm/i915: Update format_is_yuv() to include NV12 Vidya Srinivas
` (16 subsequent siblings)
26 siblings, 1 reply; 52+ messages in thread
From: Vidya Srinivas @ 2018-02-14 4:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
From: Chandra Konduru <chandra.konduru@intel.com>
This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling
v2: Review comments from Ville addressed
NV12 case to be checked first for setting
the scaler
v3: Rebased (me)
v4: Rebased (me)
v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
v6: Rebased (me)
v7: Rebased (me)
v8: Rebased (me)
Restricting the NV12 change for scaler to BXT and KBL
in this series.
v9: Rebased (me)
v10: As of now, NV12 has been tested on Gen9 and Gen10. However,
code is applicable to all GEN >= 9. Hence making
that change to keep it generic.
Comments under v8 is not valid anymore.
v11: Addressed review comments by Shashank Sharma.
For Gen10+, the scaler mode to be set it planar or normal
(single bit). Changed the code to be applicable to all
Gen.
Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_atomic.c | 8 ++++++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f6afa5e..10edacc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6732,6 +6732,7 @@ enum {
#define PS_SCALER_MODE_MASK (3 << 28)
#define PS_SCALER_MODE_DYN (0 << 28)
#define PS_SCALER_MODE_HQ (1 << 28)
+#define PS_SCALER_MODE_PLANAR (1 << 29)
#define PS_PLANE_SEL_MASK (7 << 25)
#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
#define PS_FILTER_MASK (3 << 23)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index d452c32..7ae4f48 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -327,8 +327,12 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
}
/* set scaler mode */
- if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
- scaler_state->scalers[*scaler_id].mode = 0;
+ if ((INTEL_GEN(dev_priv) >= 9) &&
+ plane_state && plane_state->base.fb &&
+ plane_state->base.fb->format->format ==
+ DRM_FORMAT_NV12) {
+ scaler_state->scalers[*scaler_id].mode =
+ PS_SCALER_MODE_PLANAR;
} else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
/*
* when only 1 scaler is in use on either pipe A or B,
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 10/16] drm/i915: Set scaler mode for NV12
2018-02-14 4:57 ` [PATCH 10/16] drm/i915: Set scaler mode for NV12 Vidya Srinivas
@ 2018-02-15 6:32 ` Sharma, Shashank
2018-02-15 9:28 ` Srinivas, Vidya
0 siblings, 1 reply; 52+ messages in thread
From: Sharma, Shashank @ 2018-02-15 6:32 UTC (permalink / raw)
To: Vidya Srinivas, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 3330 bytes --]
My previous review comments are not addressed on this patch.
I made a comment which is about programming bits *29:28* on *PS_CTRL for
(GEN>=9) *blindly*.
*
This is not valid for all GEN9 and above, in fact bit 29:28 as scalar
mode is only valid for SKL.
Bit 28 is not supported for GLK, bspec clearly mentions do not program
this.
Also from GEN10 onward bit 28 is NOT for scaler mode, its for adaptive
filtering.
Regards
Shashank
On 2/14/2018 10:27 AM, Vidya Srinivas wrote:
> From: Chandra Konduru <chandra.konduru@intel.com>
>
> This patch sets appropriate scaler mode for NV12 format.
> In this mode, skylake scaler does either chroma-upsampling or
> chroma-upsampling and resolution scaling
>
> v2: Review comments from Ville addressed
> NV12 case to be checked first for setting
> the scaler
>
> v3: Rebased (me)
>
> v4: Rebased (me)
>
> v5: Missed the Tested-by/Reviewed-by in the previous series
> Adding the same to commit message in this version.
>
> v6: Rebased (me)
>
> v7: Rebased (me)
>
> v8: Rebased (me)
> Restricting the NV12 change for scaler to BXT and KBL
> in this series.
>
> v9: Rebased (me)
>
> v10: As of now, NV12 has been tested on Gen9 and Gen10. However,
> code is applicable to all GEN >= 9. Hence making
> that change to keep it generic.
> Comments under v8 is not valid anymore.
>
> v11: Addressed review comments by Shashank Sharma.
> For Gen10+, the scaler mode to be set it planar or normal
> (single bit). Changed the code to be applicable to all
> Gen.
>
> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_atomic.c | 8 ++++++--
> 2 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f6afa5e..10edacc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6732,6 +6732,7 @@ enum {
> #define PS_SCALER_MODE_MASK (3 << 28)
> #define PS_SCALER_MODE_DYN (0 << 28)
> #define PS_SCALER_MODE_HQ (1 << 28)
> +#define PS_SCALER_MODE_PLANAR (1 << 29)
> #define PS_PLANE_SEL_MASK (7 << 25)
> #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
> #define PS_FILTER_MASK (3 << 23)
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> index d452c32..7ae4f48 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -327,8 +327,12 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
> }
>
> /* set scaler mode */
> - if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> - scaler_state->scalers[*scaler_id].mode = 0;
> + if ((INTEL_GEN(dev_priv) >= 9) &&
> + plane_state && plane_state->base.fb &&
> + plane_state->base.fb->format->format ==
> + DRM_FORMAT_NV12) {
> + scaler_state->scalers[*scaler_id].mode =
> + PS_SCALER_MODE_PLANAR;
> } else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
> /*
> * when only 1 scaler is in use on either pipe A or B,
[-- Attachment #1.2: Type: text/html, Size: 4321 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH 10/16] drm/i915: Set scaler mode for NV12
2018-02-15 6:32 ` Sharma, Shashank
@ 2018-02-15 9:28 ` Srinivas, Vidya
0 siblings, 0 replies; 52+ messages in thread
From: Srinivas, Vidya @ 2018-02-15 9:28 UTC (permalink / raw)
To: Sharma, Shashank, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4495 bytes --]
I addressed it with PS_SCALER_MODE_PLANAR (1 << 29) to keep it generic.
But as you mentioned that wouldn't be the right way.
I need to keep GEN9 and GEN10+ separate.
Will fix it in the next push. Thank you.
Vidya
From: Sharma, Shashank
Sent: Thursday, February 15, 2018 12:03 PM
To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-gfx@lists.freedesktop.org
Cc: maarten.lankhorst@linux.intel.com; Kamath, Sunil <sunil.kamath@intel.com>; Shankar, Uma <uma.shankar@intel.com>; Konduru, Chandra <chandra.konduru@intel.com>; Maiti, Nabendu Bikash <nabendu.bikash.maiti@intel.com>
Subject: Re: [PATCH 10/16] drm/i915: Set scaler mode for NV12
My previous review comments are not addressed on this patch.
I made a comment which is about programming bits 29:28 on PS_CTRL for (GEN>=9) blindly.
This is not valid for all GEN9 and above, in fact bit 29:28 as scalar mode is only valid for SKL.
Bit 28 is not supported for GLK, bspec clearly mentions do not program this.
Also from GEN10 onward bit 28 is NOT for scaler mode, its for adaptive filtering.
Regards
Shashank
On 2/14/2018 10:27 AM, Vidya Srinivas wrote:
From: Chandra Konduru <chandra.konduru@intel.com><mailto:chandra.konduru@intel.com>
This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling
v2: Review comments from Ville addressed
NV12 case to be checked first for setting
the scaler
v3: Rebased (me)
v4: Rebased (me)
v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
v6: Rebased (me)
v7: Rebased (me)
v8: Rebased (me)
Restricting the NV12 change for scaler to BXT and KBL
in this series.
v9: Rebased (me)
v10: As of now, NV12 has been tested on Gen9 and Gen10. However,
code is applicable to all GEN >= 9. Hence making
that change to keep it generic.
Comments under v8 is not valid anymore.
v11: Addressed review comments by Shashank Sharma.
For Gen10+, the scaler mode to be set it planar or normal
(single bit). Changed the code to be applicable to all
Gen.
Tested-by: Clinton Taylor <clinton.a.taylor@intel.com><mailto:clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com><mailto:clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com><mailto:chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com><mailto:nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com><mailto:vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_atomic.c | 8 ++++++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f6afa5e..10edacc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6732,6 +6732,7 @@ enum {
#define PS_SCALER_MODE_MASK (3 << 28)
#define PS_SCALER_MODE_DYN (0 << 28)
#define PS_SCALER_MODE_HQ (1 << 28)
+#define PS_SCALER_MODE_PLANAR (1 << 29)
#define PS_PLANE_SEL_MASK (7 << 25)
#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
#define PS_FILTER_MASK (3 << 23)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index d452c32..7ae4f48 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -327,8 +327,12 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
}
/* set scaler mode */
- if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
- scaler_state->scalers[*scaler_id].mode = 0;
+ if ((INTEL_GEN(dev_priv) >= 9) &&
+ plane_state && plane_state->base.fb &&
+ plane_state->base.fb->format->format ==
+ DRM_FORMAT_NV12) {
+ scaler_state->scalers[*scaler_id].mode =
+ PS_SCALER_MODE_PLANAR;
} else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
/*
* when only 1 scaler is in use on either pipe A or B,
[-- Attachment #1.2: Type: text/html, Size: 11811 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
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^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 11/16] drm/i915: Update format_is_yuv() to include NV12
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
` (9 preceding siblings ...)
2018-02-14 4:57 ` [PATCH 10/16] drm/i915: Set scaler mode for NV12 Vidya Srinivas
@ 2018-02-14 4:57 ` Vidya Srinivas
2018-02-15 6:34 ` Sharma, Shashank
2018-02-14 4:57 ` [PATCH 12/16] drm/i915: Upscale scaler max scale for NV12 Vidya Srinivas
` (15 subsequent siblings)
26 siblings, 1 reply; 52+ messages in thread
From: Vidya Srinivas @ 2018-02-14 4:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
From: Chandra Konduru <chandra.konduru@intel.com>
This patch adds NV12 to format_is_yuv() function
for sprite planes.
v2:
-Use intel_ prefix for format_is_yuv (Ville)
v3: Rebased (me)
v4: Rebased and addressed review comments from Clinton A Taylor.
"static function in intel_sprite.c is not available
to the primary plane functions".
Changed commit message - function modified for
sprite planes.
v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
v6: Rebased (me)
v7: Rebased (me)
v8: Rebased (me)
v9: Rebased (me)
v10: Changed intel_format_is_yuv function from
static to non-static. We need to use it later from
other files for check.
Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_sprite.c | 8 ++++----
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6402d6d..8d4988b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2034,6 +2034,7 @@ void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
bool skl_plane_get_hw_state(struct intel_plane *plane);
bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
enum pipe pipe, enum plane_id plane_id);
+bool intel_format_is_yuv(uint32_t format);
/* intel_tv.c */
void intel_tv_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index e098e4b..2c51d8a 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -41,14 +41,14 @@
#include <drm/i915_drm.h>
#include "i915_drv.h"
-static bool
-format_is_yuv(uint32_t format)
+bool intel_format_is_yuv(uint32_t format)
{
switch (format) {
case DRM_FORMAT_YUYV:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_YVYU:
+ case DRM_FORMAT_NV12:
return true;
default:
return false;
@@ -352,7 +352,7 @@ chv_update_csc(struct intel_plane *plane, uint32_t format)
enum plane_id plane_id = plane->id;
/* Seems RGB data bypasses the CSC always */
- if (!format_is_yuv(format))
+ if (!intel_format_is_yuv(format))
return;
/*
@@ -979,7 +979,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
src_y = src->y1 >> 16;
src_h = drm_rect_height(src) >> 16;
- if (format_is_yuv(fb->format->format)) {
+ if (intel_format_is_yuv(fb->format->format)) {
src_x &= ~1;
src_w &= ~1;
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 11/16] drm/i915: Update format_is_yuv() to include NV12
2018-02-14 4:57 ` [PATCH 11/16] drm/i915: Update format_is_yuv() to include NV12 Vidya Srinivas
@ 2018-02-15 6:34 ` Sharma, Shashank
2018-02-15 9:25 ` Srinivas, Vidya
0 siblings, 1 reply; 52+ messages in thread
From: Sharma, Shashank @ 2018-02-15 6:34 UTC (permalink / raw)
To: Vidya Srinivas, intel-gfx
My previous review comments is neither acknowledged nor addressed.
Regards
Shashank
On 2/14/2018 10:27 AM, Vidya Srinivas wrote:
> From: Chandra Konduru <chandra.konduru@intel.com>
>
> This patch adds NV12 to format_is_yuv() function
> for sprite planes.
>
> v2:
> -Use intel_ prefix for format_is_yuv (Ville)
>
> v3: Rebased (me)
>
> v4: Rebased and addressed review comments from Clinton A Taylor.
> "static function in intel_sprite.c is not available
> to the primary plane functions".
> Changed commit message - function modified for
> sprite planes.
>
> v5: Missed the Tested-by/Reviewed-by in the previous series
> Adding the same to commit message in this version.
>
> v6: Rebased (me)
>
> v7: Rebased (me)
>
> v8: Rebased (me)
>
> v9: Rebased (me)
>
> v10: Changed intel_format_is_yuv function from
> static to non-static. We need to use it later from
> other files for check.
>
> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_sprite.c | 8 ++++----
> 2 files changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 6402d6d..8d4988b 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -2034,6 +2034,7 @@ void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
> bool skl_plane_get_hw_state(struct intel_plane *plane);
> bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
> enum pipe pipe, enum plane_id plane_id);
> +bool intel_format_is_yuv(uint32_t format);
>
> /* intel_tv.c */
> void intel_tv_init(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index e098e4b..2c51d8a 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -41,14 +41,14 @@
> #include <drm/i915_drm.h>
> #include "i915_drv.h"
>
> -static bool
> -format_is_yuv(uint32_t format)
> +bool intel_format_is_yuv(uint32_t format)
> {
> switch (format) {
> case DRM_FORMAT_YUYV:
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> case DRM_FORMAT_YVYU:
> + case DRM_FORMAT_NV12:
> return true;
> default:
> return false;
> @@ -352,7 +352,7 @@ chv_update_csc(struct intel_plane *plane, uint32_t format)
> enum plane_id plane_id = plane->id;
>
> /* Seems RGB data bypasses the CSC always */
> - if (!format_is_yuv(format))
> + if (!intel_format_is_yuv(format))
> return;
>
> /*
> @@ -979,7 +979,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
> src_y = src->y1 >> 16;
> src_h = drm_rect_height(src) >> 16;
>
> - if (format_is_yuv(fb->format->format)) {
> + if (intel_format_is_yuv(fb->format->format)) {
> src_x &= ~1;
> src_w &= ~1;
>
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH 11/16] drm/i915: Update format_is_yuv() to include NV12
2018-02-15 6:34 ` Sharma, Shashank
@ 2018-02-15 9:25 ` Srinivas, Vidya
0 siblings, 0 replies; 52+ messages in thread
From: Srinivas, Vidya @ 2018-02-15 9:25 UTC (permalink / raw)
To: Sharma, Shashank, intel-gfx
Sorry about this. Will fix it in the next push. Thanks.
Vidya
> -----Original Message-----
> From: Sharma, Shashank
> Sent: Thursday, February 15, 2018 12:05 PM
> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: maarten.lankhorst@linux.intel.com; Kamath, Sunil
> <sunil.kamath@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> Konduru, Chandra <chandra.konduru@intel.com>; Maiti, Nabendu Bikash
> <nabendu.bikash.maiti@intel.com>
> Subject: Re: [PATCH 11/16] drm/i915: Update format_is_yuv() to include
> NV12
>
> My previous review comments is neither acknowledged nor addressed.
>
> Regards
> Shashank
> On 2/14/2018 10:27 AM, Vidya Srinivas wrote:
> > From: Chandra Konduru <chandra.konduru@intel.com>
> >
> > This patch adds NV12 to format_is_yuv() function for sprite planes.
> >
> > v2:
> > -Use intel_ prefix for format_is_yuv (Ville)
> >
> > v3: Rebased (me)
> >
> > v4: Rebased and addressed review comments from Clinton A Taylor.
> > "static function in intel_sprite.c is not available to the primary
> > plane functions".
> > Changed commit message - function modified for sprite planes.
> >
> > v5: Missed the Tested-by/Reviewed-by in the previous series Adding the
> > same to commit message in this version.
> >
> > v6: Rebased (me)
> >
> > v7: Rebased (me)
> >
> > v8: Rebased (me)
> >
> > v9: Rebased (me)
> >
> > v10: Changed intel_format_is_yuv function from static to non-static.
> > We need to use it later from other files for check.
> >
> > Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> > Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> > Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
> > Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> > Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> > Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_drv.h | 1 +
> > drivers/gpu/drm/i915/intel_sprite.c | 8 ++++----
> > 2 files changed, 5 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 6402d6d..8d4988b 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -2034,6 +2034,7 @@ void skl_disable_plane(struct intel_plane
> *plane, struct intel_crtc *crtc);
> > bool skl_plane_get_hw_state(struct intel_plane *plane);
> > bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
> > enum pipe pipe, enum plane_id plane_id);
> > +bool intel_format_is_yuv(uint32_t format);
> >
> > /* intel_tv.c */
> > void intel_tv_init(struct drm_i915_private *dev_priv); diff --git
> > a/drivers/gpu/drm/i915/intel_sprite.c
> > b/drivers/gpu/drm/i915/intel_sprite.c
> > index e098e4b..2c51d8a 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -41,14 +41,14 @@
> > #include <drm/i915_drm.h>
> > #include "i915_drv.h"
> >
> > -static bool
> > -format_is_yuv(uint32_t format)
> > +bool intel_format_is_yuv(uint32_t format)
> > {
> > switch (format) {
> > case DRM_FORMAT_YUYV:
> > case DRM_FORMAT_UYVY:
> > case DRM_FORMAT_VYUY:
> > case DRM_FORMAT_YVYU:
> > + case DRM_FORMAT_NV12:
> > return true;
> > default:
> > return false;
> > @@ -352,7 +352,7 @@ chv_update_csc(struct intel_plane *plane,
> uint32_t format)
> > enum plane_id plane_id = plane->id;
> >
> > /* Seems RGB data bypasses the CSC always */
> > - if (!format_is_yuv(format))
> > + if (!intel_format_is_yuv(format))
> > return;
> >
> > /*
> > @@ -979,7 +979,7 @@ intel_check_sprite_plane(struct intel_plane
> *plane,
> > src_y = src->y1 >> 16;
> > src_h = drm_rect_height(src) >> 16;
> >
> > - if (format_is_yuv(fb->format->format)) {
> > + if (intel_format_is_yuv(fb->format->format)) {
> > src_x &= ~1;
> > src_w &= ~1;
> >
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 12/16] drm/i915: Upscale scaler max scale for NV12
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
` (10 preceding siblings ...)
2018-02-14 4:57 ` [PATCH 11/16] drm/i915: Update format_is_yuv() to include NV12 Vidya Srinivas
@ 2018-02-14 4:57 ` Vidya Srinivas
2018-02-14 4:57 ` [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane Vidya Srinivas
` (14 subsequent siblings)
26 siblings, 0 replies; 52+ messages in thread
From: Vidya Srinivas @ 2018-02-14 4:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
From: Chandra Konduru <chandra.konduru@intel.com>
This patch updates scaler max limit support for NV12
v2: Rebased (me)
v3: Rebased (me)
v4: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
v5: Addressed review comments from Ville and rebased
- calculation of max_scale to be made
less convoluted by splitting it up a bit
- Indentation errors to be fixed in the series
v6: Rebased (me)
Fixed review comments from Paauwe, Bob J
Previous version, where a split of calculation
was done, was wrong. Fixed that issue here.
v7: Rebased (me)
v8: Rebased (me)
v9: Rebased (me)
v10: Rebased (me)
v11: Addressed review comments from Shashank Sharma
v12: Fixed failure in IGT debugfs_test.
fb is NULL in skl_update_scaler_plane
Due to this, accessing fb->format caused failure.
Patch checks fb before using.
Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 40 ++++++++++++++++++++++++++----------
drivers/gpu/drm/i915/intel_drv.h | 3 ++-
drivers/gpu/drm/i915/intel_sprite.c | 3 ++-
3 files changed, 33 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 971bd04..ac8279a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3435,6 +3435,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
case DRM_FORMAT_VYUY:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
+ case DRM_FORMAT_NV12:
+ return PLANE_CTL_FORMAT_NV12;
default:
MISSING_CASE(pixel_format);
}
@@ -4658,7 +4660,9 @@ static void cpt_verify_modeset(struct drm_device *dev, int pipe)
static int
skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
unsigned int scaler_user, int *scaler_id,
- int src_w, int src_h, int dst_w, int dst_h)
+ int src_w, int src_h, int dst_w, int dst_h,
+ bool plane_scaler_check,
+ uint32_t pixel_format)
{
struct intel_crtc_scaler_state *scaler_state =
&crtc_state->scaler_state;
@@ -4676,6 +4680,9 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
*/
need_scaling = src_w != dst_w || src_h != dst_h;
+ if (plane_scaler_check)
+ need_scaling = pixel_format == DRM_FORMAT_NV12;
+
if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
need_scaling = true;
@@ -4751,9 +4758,10 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state)
const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
- &state->scaler_state.scaler_id,
- state->pipe_src_w, state->pipe_src_h,
- adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
+ &state->scaler_state.scaler_id,
+ state->pipe_src_w, state->pipe_src_h,
+ adjusted_mode->crtc_hdisplay,
+ adjusted_mode->crtc_vdisplay, false, 0);
}
/**
@@ -4783,7 +4791,8 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
drm_rect_width(&plane_state->base.src) >> 16,
drm_rect_height(&plane_state->base.src) >> 16,
drm_rect_width(&plane_state->base.dst),
- drm_rect_height(&plane_state->base.dst));
+ drm_rect_height(&plane_state->base.dst),
+ fb ? true : false, fb ? fb->format->format : 0);
if (ret || plane_state->scaler_id < 0)
return ret;
@@ -4809,6 +4818,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+ case DRM_FORMAT_NV12:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
@@ -12775,11 +12785,13 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
}
int
-skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
+skl_max_scale(struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *crtc_state,
+ uint32_t pixel_format)
{
struct drm_i915_private *dev_priv;
- int max_scale;
- int crtc_clock, max_dotclk;
+ int max_scale, mult;
+ int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
if (!intel_crtc || !crtc_state->base.enable)
return DRM_PLANE_HELPER_NO_SCALING;
@@ -12801,8 +12813,10 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state
* or
* cdclk/crtc_clock
*/
- max_scale = min((1 << 16) * 3 - 1,
- (1 << 8) * ((max_dotclk << 8) / crtc_clock));
+ mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
+ tmpclk1 = (1 << 16) * mult - 1;
+ tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
+ max_scale = min(tmpclk1, tmpclk2);
return max_scale;
}
@@ -12819,12 +12833,16 @@ intel_check_primary_plane(struct intel_plane *plane,
bool can_position = false;
struct drm_rect clip = {};
int ret;
+ uint32_t pixel_format = 0;
if (INTEL_GEN(dev_priv) >= 9) {
/* use scaler when colorkey is not required */
if (!state->ckey.flags) {
min_scale = 1;
- max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
+ if (state->base.fb)
+ pixel_format = state->base.fb->format->format;
+ max_scale = skl_max_scale(to_intel_crtc(crtc),
+ crtc_state, pixel_format);
}
can_position = true;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8d4988b..700c176 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1582,7 +1582,8 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
struct intel_crtc_state *pipe_config);
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
-int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
+int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
+ uint32_t pixel_format);
static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
{
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 2c51d8a..77a5433 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -897,7 +897,8 @@ intel_check_sprite_plane(struct intel_plane *plane,
if (!state->ckey.flags) {
can_scale = 1;
min_scale = 1;
- max_scale = skl_max_scale(crtc, crtc_state);
+ max_scale = skl_max_scale(crtc, crtc_state,
+ fb->format->format);
} else {
can_scale = 0;
min_scale = DRM_PLANE_HELPER_NO_SCALING;
--
2.7.4
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^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
` (11 preceding siblings ...)
2018-02-14 4:57 ` [PATCH 12/16] drm/i915: Upscale scaler max scale for NV12 Vidya Srinivas
@ 2018-02-14 4:57 ` Vidya Srinivas
2018-02-14 4:57 ` [PATCH 14/16] drm/i915: Add NV12 as supported format for sprite plane Vidya Srinivas
` (13 subsequent siblings)
26 siblings, 0 replies; 52+ messages in thread
From: Vidya Srinivas @ 2018-02-14 4:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
From: Chandra Konduru <chandra.konduru@intel.com>
This patch adds NV12 to list of supported formats for
primary plane
v2: Rebased (Chandra Konduru)
v3: Rebased (me)
v4: Review comments by Ville addressed
Removed the skl_primary_formats_with_nv12 and
added NV12 case in existing skl_primary_formats
v5: Rebased (me)
v6: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
v7: Review comments by Ville addressed
Restricting the NV12 for BXT and on PIPE A and B
Rebased (me)
v8: Rebased (me)
Modified restricting the NV12 support for both BXT and KBL.
v9: Rebased (me)
v10: Addressed review comments from Maarten.
Adding NV12 inside skl_primary_formats itself.
Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ac8279a..6f43d72 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
};
static const uint64_t skl_format_modifiers_noccs[] = {
@@ -13255,6 +13256,10 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
intel_primary_formats = skl_primary_formats;
num_formats = ARRAY_SIZE(skl_primary_formats);
+ if ((INTEL_GEN(dev_priv) == 9 && (pipe == PIPE_C)) &&
+ !IS_GEMINILAKE(dev_priv))
+ num_formats -= 1;
+
if (skl_plane_has_ccs(dev_priv, pipe, PLANE_PRIMARY))
modifiers = skl_format_modifiers_ccs;
else
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* [PATCH 14/16] drm/i915: Add NV12 as supported format for sprite plane
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
` (12 preceding siblings ...)
2018-02-14 4:57 ` [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane Vidya Srinivas
@ 2018-02-14 4:57 ` Vidya Srinivas
2018-02-15 8:53 ` Sharma, Shashank
2018-02-14 4:57 ` [PATCH 15/16] drm/i915: Add NV12 support to intel_framebuffer_init Vidya Srinivas
` (12 subsequent siblings)
26 siblings, 1 reply; 52+ messages in thread
From: Vidya Srinivas @ 2018-02-14 4:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
From: Chandra Konduru <chandra.konduru@intel.com>
This patch adds NV12 to list of supported formats for sprite plane.
v2: Rebased (me)
v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12 case in existing skl_plane_formats
- Added the 10bpc RGB formats
v4: Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Removed 10bit RGB formats added previously with NV12 series
v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Previous version has 10bit RGB format removed from VLV formats
by mistake. Fixing that in this version.
Removed 10bit RGB formats added previously with NV12 series
for SKL.
v6: Addressed review comments by Ville
Restricting the NV12 to BXT and PIPE A and B
v7: Rebased (me)
v8: Rebased (me)
Restricting NV12 changes to BXT and KBL
Restricting NV12 changes for plane 0 (overlay)
v9: Rebased (me)
v10: Addressed review comments from Maarten.
Adding NV12 to skl_plane_formats itself.
v11: Addressed review comments from Shashank Sharma
Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/intel_sprite.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 77a5433..4290a23 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1171,6 +1171,7 @@ static uint32_t skl_plane_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
};
static const uint64_t skl_plane_format_modifiers_noccs[] = {
@@ -1369,6 +1370,12 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
plane_formats = skl_plane_formats;
num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+ if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) &&
+ (plane != 0 || pipe == PIPE_C)) ||
+ ((INTEL_GEN(dev_priv) == 10 ||
+ IS_GEMINILAKE(dev_priv)) && plane != 0))
+ num_plane_formats -= 1;
+
if (skl_plane_has_ccs(dev_priv, pipe, PLANE_SPRITE0 + plane))
modifiers = skl_plane_format_modifiers_ccs;
else
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 14/16] drm/i915: Add NV12 as supported format for sprite plane
2018-02-14 4:57 ` [PATCH 14/16] drm/i915: Add NV12 as supported format for sprite plane Vidya Srinivas
@ 2018-02-15 8:53 ` Sharma, Shashank
2018-02-15 9:18 ` Srinivas, Vidya
0 siblings, 1 reply; 52+ messages in thread
From: Sharma, Shashank @ 2018-02-15 8:53 UTC (permalink / raw)
To: Vidya Srinivas, intel-gfx
Regards
Shashank
On 2/14/2018 10:27 AM, Vidya Srinivas wrote:
> + if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) &&
> + (plane != 0 || pipe == PIPE_C)) ||
> + ((INTEL_GEN(dev_priv) == 10 ||
> + IS_GEMINILAKE(dev_priv)) && plane != 0))
> + num_plane_formats -= 1;
Please correct me if I am wrong, but as far as I see, this whole complex
if(cond) can be replaced by more readable if's like:
if (IS_GEMINILAKE(dev_priv) || IS_GEN10(dev_priv)) {
if (plane != 0)
num_planes_format -=1;
} else { /* GEN9 */
if (plane != 0 || pipe != PIPE_C)
num_planes_format -=1;
}
Or May be even below:
if (IS_GEN9(dev_priv) && pipe == PIPE_C)
num_planes_format -=1;
else if (plane != 0)
num_planes_format -=1;
Regards
Shashank
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH 14/16] drm/i915: Add NV12 as supported format for sprite plane
2018-02-15 8:53 ` Sharma, Shashank
@ 2018-02-15 9:18 ` Srinivas, Vidya
0 siblings, 0 replies; 52+ messages in thread
From: Srinivas, Vidya @ 2018-02-15 9:18 UTC (permalink / raw)
To: Sharma, Shashank, intel-gfx
> -----Original Message-----
> From: Sharma, Shashank
> Sent: Thursday, February 15, 2018 2:24 PM
> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: maarten.lankhorst@linux.intel.com; Kamath, Sunil
> <sunil.kamath@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> Konduru, Chandra <chandra.konduru@intel.com>; Maiti, Nabendu Bikash
> <nabendu.bikash.maiti@intel.com>
> Subject: Re: [PATCH 14/16] drm/i915: Add NV12 as supported format for
> sprite plane
>
> Regards
>
> Shashank
>
>
> On 2/14/2018 10:27 AM, Vidya Srinivas wrote:
> > + if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)
> &&
> > + (plane != 0 || pipe == PIPE_C)) ||
> > + ((INTEL_GEN(dev_priv) == 10 ||
> > + IS_GEMINILAKE(dev_priv)) && plane != 0))
> > + num_plane_formats -= 1;
> Please correct me if I am wrong, but as far as I see, this whole complex
> if(cond) can be replaced by more readable if's like:
> if (IS_GEMINILAKE(dev_priv) || IS_GEN10(dev_priv)) {
> if (plane != 0)
> num_planes_format -=1;
> } else { /* GEN9 */
> if (plane != 0 || pipe != PIPE_C)
> num_planes_format -=1;
> }
Agree :) Thanks. Will fix it.
Regards
Vidya
>
> Or May be even below:
>
> if (IS_GEN9(dev_priv) && pipe == PIPE_C)
> num_planes_format -=1;
> else if (plane != 0)
> num_planes_format -=1;
>
> Regards
> Shashank
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 15/16] drm/i915: Add NV12 support to intel_framebuffer_init
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
` (13 preceding siblings ...)
2018-02-14 4:57 ` [PATCH 14/16] drm/i915: Add NV12 as supported format for sprite plane Vidya Srinivas
@ 2018-02-14 4:57 ` Vidya Srinivas
2018-02-15 9:22 ` Sharma, Shashank
2018-02-14 4:57 ` [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg Vidya Srinivas
` (11 subsequent siblings)
26 siblings, 1 reply; 52+ messages in thread
From: Vidya Srinivas @ 2018-02-14 4:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
From: Chandra Konduru <chandra.konduru@intel.com>
This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (Chandra Konduru)
v3: rebased (me)
v4: Review comments by Ville addressed
Added platform check for NV12 in intel_framebuffer_init
Removed offset checks for NV12 case
v5: Addressed review comments by Clinton A Taylor
This NV12 support only correctly works on SKL.
Plane color space conversion is different on GLK and later platforms
causing the colors to display incorrectly.
Ville's plane color space property patch series
in review will fix this issue.
- Restricted the NV12 case in intel_framebuffer_init to
SKL and BXT only.
v6: Rebased (me)
v7: Addressed review comments by Ville
Restricting the NV12 to BXT for now.
v8: Rebased (me)
Restricting the NV12 changes to BXT and KBL for now.
v9: Rebased (me)
v10: NV12 supported by all GEN >= 9.
Making this change in intel_framebuffer_init. This is
part of addressing Maarten's review comments.
Comment under v8 no longer applicable
v11: Addressed review comments from Shashank Sharma
Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6f43d72..42ec089 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14063,6 +14063,14 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
goto err;
}
break;
+ case DRM_FORMAT_NV12:
+ if (INTEL_GEN(dev_priv) < 9) {
+ DRM_DEBUG_KMS("unsupported pixel format: %s\n",
+ drm_get_format_name(mode_cmd->pixel_format,
+ &format_name));
+ goto err;
+ }
+ break;
default:
DRM_DEBUG_KMS("unsupported pixel format: %s\n",
drm_get_format_name(mode_cmd->pixel_format, &format_name));
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 15/16] drm/i915: Add NV12 support to intel_framebuffer_init
2018-02-14 4:57 ` [PATCH 15/16] drm/i915: Add NV12 support to intel_framebuffer_init Vidya Srinivas
@ 2018-02-15 9:22 ` Sharma, Shashank
0 siblings, 0 replies; 52+ messages in thread
From: Sharma, Shashank @ 2018-02-15 9:22 UTC (permalink / raw)
To: Vidya Srinivas, intel-gfx
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Regards
Shashank
On 2/14/2018 10:27 AM, Vidya Srinivas wrote:
> From: Chandra Konduru <chandra.konduru@intel.com>
>
> This patch adds NV12 as supported format
> to intel_framebuffer_init and performs various checks.
>
> v2:
> -Fix an issue in checks added (Chandra Konduru)
>
> v3: rebased (me)
>
> v4: Review comments by Ville addressed
> Added platform check for NV12 in intel_framebuffer_init
> Removed offset checks for NV12 case
>
> v5: Addressed review comments by Clinton A Taylor
> This NV12 support only correctly works on SKL.
> Plane color space conversion is different on GLK and later platforms
> causing the colors to display incorrectly.
> Ville's plane color space property patch series
> in review will fix this issue.
> - Restricted the NV12 case in intel_framebuffer_init to
> SKL and BXT only.
>
> v6: Rebased (me)
>
> v7: Addressed review comments by Ville
> Restricting the NV12 to BXT for now.
>
> v8: Rebased (me)
> Restricting the NV12 changes to BXT and KBL for now.
>
> v9: Rebased (me)
>
> v10: NV12 supported by all GEN >= 9.
> Making this change in intel_framebuffer_init. This is
> part of addressing Maarten's review comments.
> Comment under v8 no longer applicable
>
> v11: Addressed review comments from Shashank Sharma
>
> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 6f43d72..42ec089 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -14063,6 +14063,14 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> goto err;
> }
> break;
> + case DRM_FORMAT_NV12:
> + if (INTEL_GEN(dev_priv) < 9) {
> + DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> + drm_get_format_name(mode_cmd->pixel_format,
> + &format_name));
> + goto err;
> + }
> + break;
> default:
> DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> drm_get_format_name(mode_cmd->pixel_format, &format_name));
_______________________________________________
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^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
` (14 preceding siblings ...)
2018-02-14 4:57 ` [PATCH 15/16] drm/i915: Add NV12 support to intel_framebuffer_init Vidya Srinivas
@ 2018-02-14 4:57 ` Vidya Srinivas
2018-02-15 11:03 ` Sharma, Shashank
2018-02-15 11:05 ` Sharma, Shashank
2018-02-14 5:24 ` [PATCH 00/16] Adding NV12 support Kristian Høgsberg
` (10 subsequent siblings)
26 siblings, 2 replies; 52+ messages in thread
From: Vidya Srinivas @ 2018-02-14 4:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
If the fb format is YUV, enable the plane CSC mode bits
for the conversion.
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
drivers/gpu/drm/i915/intel_display.c | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 10edacc..baf197b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6453,6 +6453,12 @@ enum {
#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30)
#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23)
+#define PLANE_COLOR_CSC_MASK (0x7 << 17)
+#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
+#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17)
+#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17)
+#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17)
+#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
#define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
#define PLANE_COLOR_ALPHA_MASK (0x3 << 4)
#define PLANE_COLOR_ALPHA_DISABLE (0 << 4)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 42ec089..6c43eef 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3577,6 +3577,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
+ if (fb && intel_format_is_yuv(fb->format->format))
+ plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
return plane_color_ctl;
}
--
2.7.4
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^ permalink raw reply related [flat|nested] 52+ messages in thread* Re: [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
2018-02-14 4:57 ` [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg Vidya Srinivas
@ 2018-02-15 11:03 ` Sharma, Shashank
2018-02-15 11:05 ` Sharma, Shashank
1 sibling, 0 replies; 52+ messages in thread
From: Sharma, Shashank @ 2018-02-15 11:03 UTC (permalink / raw)
To: Vidya Srinivas, intel-gfx
My previous review comment for alignment has not been addressed in this
series
Regards
Shashank
On 2/14/2018 10:27 AM, Vidya Srinivas wrote:
> If the fb format is YUV, enable the plane CSC mode bits
> for the conversion.
>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
> drivers/gpu/drm/i915/intel_display.c | 2 ++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 10edacc..baf197b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6453,6 +6453,12 @@ enum {
> #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
> #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30)
> #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23)
> +#define PLANE_COLOR_CSC_MASK (0x7 << 17)
> +#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
> +#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17)
> +#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17)
> +#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17)
> +#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
> #define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
> #define PLANE_COLOR_ALPHA_MASK (0x3 << 4)
> #define PLANE_COLOR_ALPHA_DISABLE (0 << 4)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 42ec089..6c43eef 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3577,6 +3577,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
> plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
> plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
> plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
> + if (fb && intel_format_is_yuv(fb->format->format))
> + plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
>
> return plane_color_ctl;
> }
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
2018-02-14 4:57 ` [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg Vidya Srinivas
2018-02-15 11:03 ` Sharma, Shashank
@ 2018-02-15 11:05 ` Sharma, Shashank
1 sibling, 0 replies; 52+ messages in thread
From: Sharma, Shashank @ 2018-02-15 11:05 UTC (permalink / raw)
To: Vidya Srinivas, intel-gfx
My previous review comment for alignment is not addressed in this patch.
Regards
Shashank
On 2/14/2018 10:27 AM, Vidya Srinivas wrote:
> If the fb format is YUV, enable the plane CSC mode bits
> for the conversion.
>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
> drivers/gpu/drm/i915/intel_display.c | 2 ++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 10edacc..baf197b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6453,6 +6453,12 @@ enum {
> #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
> #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30)
> #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23)
> +#define PLANE_COLOR_CSC_MASK (0x7 << 17)
> +#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
> +#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17)
> +#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17)
> +#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17)
> +#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
> #define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
> #define PLANE_COLOR_ALPHA_MASK (0x3 << 4)
> #define PLANE_COLOR_ALPHA_DISABLE (0 << 4)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 42ec089..6c43eef 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3577,6 +3577,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
> plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
> plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
> plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
> + if (fb && intel_format_is_yuv(fb->format->format))
> + plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
>
> return plane_color_ctl;
> }
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [PATCH 00/16] Adding NV12 support
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
` (15 preceding siblings ...)
2018-02-14 4:57 ` [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg Vidya Srinivas
@ 2018-02-14 5:24 ` Kristian Høgsberg
2018-02-14 8:32 ` Srinivas, Vidya
2018-02-14 5:46 ` ✗ Fi.CI.BAT: failure for Adding NV12 support (rev10) Patchwork
` (9 subsequent siblings)
26 siblings, 1 reply; 52+ messages in thread
From: Kristian Høgsberg @ 2018-02-14 5:24 UTC (permalink / raw)
To: Vidya Srinivas; +Cc: intel-gfx
On Tue, Feb 13, 2018 at 8:59 PM Vidya Srinivas <vidya.srinivas@intel.com>
wrote:
> This patch series is adding NV12 support for Broxton display after
rebasing on
> latest drm-tip.
> Initial series of the patches can be found here:
> https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html
I still don't see support for advertising modifiers in this patch set. The
series should handle NV12 in the supported_modifiers function to indicate
which tiling and/or compression modifiers are supported for NV12
framebuffers.
Kristian
> Previous revision history:
> The first version of patches were reviewed when floated by Chandra in 2015
> but currently there was a design change with respect to
> - the way fb offset is handled
> - the way rotation is handled
> Current NV12 patch series has been ported as per the
> current changes on drm-tip
> Review comments from Ville (12th June 2017) have been addressed Review
> comments from Clinton A Taylor (7th July 2017) have been addressed
> Review comments from Clinton A Taylor (10th July 2017)
> have been addressed. Had missed out tested-by/reviewed-by in the
patches.
> Fixed that error in this series.
> Review comments from Ville (11th July 2017) addressed.
> Review comments from Paauwe, Bob (29th July 2017) addressed.
> Update from rev 28 Aug 2017
> Rebased the series.
> Tested with IGT for rotation, sprite and tiling combinations.
> IGT Links:
> https://patchwork.kernel.org/patch/9995943/
> https://patchwork.kernel.org/patch/9995945/
> Review comments by Maarten are addressed in this series.
> NV12 enabled for Gen10.
> Review comments from Shashank Sharma are addressed.
> Update from last rev:
> IGT debug_fs test failure fixed.
> Chandra Konduru (6):
> drm/i915: Set scaler mode for NV12
> drm/i915: Update format_is_yuv() to include NV12
> drm/i915: Upscale scaler max scale for NV12
> drm/i915: Add NV12 as supported format for primary plane
> drm/i915: Add NV12 as supported format for sprite plane
> drm/i915: Add NV12 support to intel_framebuffer_init
> Mahesh Kumar (9):
> drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
> drm/i915/skl+: refactor WM calculation for NV12
> drm/i915/skl+: add NV12 in skl_format_to_fourcc
> drm/i915/skl+: support verification of DDB HW state for NV12
> drm/i915/skl+: NV12 related changes for WM
> drm/i915/skl+: pass skl_wm_level struct to wm compute func
> drm/i915/skl+: make sure higher latency level has higher wm value
> drm/i915/skl+: nv12 workaround disable WM level 1-7
> drm/i915/skl: split skl_compute_ddb function
> Vidya Srinivas (1):
> drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
> drivers/gpu/drm/i915/i915_drv.h | 10 +-
> drivers/gpu/drm/i915/i915_reg.h | 7 +
> drivers/gpu/drm/i915/intel_atomic.c | 8 +-
> drivers/gpu/drm/i915/intel_display.c | 59 ++++-
> drivers/gpu/drm/i915/intel_drv.h | 9 +-
> drivers/gpu/drm/i915/intel_pm.c | 433
++++++++++++++++++++++-------------
> drivers/gpu/drm/i915/intel_sprite.c | 18 +-
> 7 files changed, 357 insertions(+), 187 deletions(-)
> --
> 2.7.4
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: [PATCH 00/16] Adding NV12 support
2018-02-14 5:24 ` [PATCH 00/16] Adding NV12 support Kristian Høgsberg
@ 2018-02-14 8:32 ` Srinivas, Vidya
0 siblings, 0 replies; 52+ messages in thread
From: Srinivas, Vidya @ 2018-02-14 8:32 UTC (permalink / raw)
To: Kristian Høgsberg; +Cc: intel-gfx
> -----Original Message-----
> From: Kristian Høgsberg [mailto:hoegsberg@gmail.com]
> Sent: Wednesday, February 14, 2018 10:54 AM
> To: Srinivas, Vidya <vidya.srinivas@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 00/16] Adding NV12 support
>
> On Tue, Feb 13, 2018 at 8:59 PM Vidya Srinivas <vidya.srinivas@intel.com>
> wrote:
>
> > This patch series is adding NV12 support for Broxton display after
> rebasing on
> > latest drm-tip.
> > Initial series of the patches can be found here:
> > https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html
>
> I still don't see support for advertising modifiers in this patch set. The series
> should handle NV12 in the supported_modifiers function to indicate which
> tiling and/or compression modifiers are supported for NV12 framebuffers.
>
> Kristian
>
Thank you. Apologies. Will address this as an additional patch once
These base series get merged. Would that be okay?
Regards
Vidya
>
>
>
> > Previous revision history:
> > The first version of patches were reviewed when floated by Chandra in
> > 2015 but currently there was a design change with respect to
> > - the way fb offset is handled
> > - the way rotation is handled
> > Current NV12 patch series has been ported as per the current changes
> > on drm-tip
>
> > Review comments from Ville (12th June 2017) have been addressed
> Review
> > comments from Clinton A Taylor (7th July 2017) have been addressed
>
> > Review comments from Clinton A Taylor (10th July 2017)
> > have been addressed. Had missed out tested-by/reviewed-by in
> > the
> patches.
>
> > Fixed that error in this series.
> > Review comments from Ville (11th July 2017) addressed.
> > Review comments from Paauwe, Bob (29th July 2017) addressed.
>
> > Update from rev 28 Aug 2017
> > Rebased the series.
> > Tested with IGT for rotation, sprite and tiling combinations.
> > IGT Links:
> > https://patchwork.kernel.org/patch/9995943/
> > https://patchwork.kernel.org/patch/9995945/
> > Review comments by Maarten are addressed in this series.
> > NV12 enabled for Gen10.
> > Review comments from Shashank Sharma are addressed.
>
> > Update from last rev:
> > IGT debug_fs test failure fixed.
>
> > Chandra Konduru (6):
> > drm/i915: Set scaler mode for NV12
> > drm/i915: Update format_is_yuv() to include NV12
> > drm/i915: Upscale scaler max scale for NV12
> > drm/i915: Add NV12 as supported format for primary plane
> > drm/i915: Add NV12 as supported format for sprite plane
> > drm/i915: Add NV12 support to intel_framebuffer_init
>
> > Mahesh Kumar (9):
> > drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
> > drm/i915/skl+: refactor WM calculation for NV12
> > drm/i915/skl+: add NV12 in skl_format_to_fourcc
> > drm/i915/skl+: support verification of DDB HW state for NV12
> > drm/i915/skl+: NV12 related changes for WM
> > drm/i915/skl+: pass skl_wm_level struct to wm compute func
> > drm/i915/skl+: make sure higher latency level has higher wm value
> > drm/i915/skl+: nv12 workaround disable WM level 1-7
> > drm/i915/skl: split skl_compute_ddb function
>
> > Vidya Srinivas (1):
> > drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
>
> > drivers/gpu/drm/i915/i915_drv.h | 10 +-
> > drivers/gpu/drm/i915/i915_reg.h | 7 +
> > drivers/gpu/drm/i915/intel_atomic.c | 8 +-
> > drivers/gpu/drm/i915/intel_display.c | 59 ++++-
> > drivers/gpu/drm/i915/intel_drv.h | 9 +-
> > drivers/gpu/drm/i915/intel_pm.c | 433
> ++++++++++++++++++++++-------------
> > drivers/gpu/drm/i915/intel_sprite.c | 18 +-
> > 7 files changed, 357 insertions(+), 187 deletions(-)
>
> > --
> > 2.7.4
>
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* ✗ Fi.CI.BAT: failure for Adding NV12 support (rev10)
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
` (16 preceding siblings ...)
2018-02-14 5:24 ` [PATCH 00/16] Adding NV12 support Kristian Høgsberg
@ 2018-02-14 5:46 ` Patchwork
2018-02-14 12:33 ` ✗ Fi.CI.CHECKPATCH: warning " Patchwork
` (8 subsequent siblings)
26 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2018-02-14 5:46 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
== Series Details ==
Series: Adding NV12 support (rev10)
URL : https://patchwork.freedesktop.org/series/28103/
State : failure
== Summary ==
Series 28103v10 Adding NV12 support
https://patchwork.freedesktop.org/api/1.0/series/28103/revisions/10/mbox/
Test debugfs_test:
Subgroup read_all_entries:
pass -> INCOMPLETE (fi-snb-2520m) fdo#103713
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS (fi-cnl-y3) fdo#105058
Test prime_vgem:
Subgroup basic-fence-flip:
pass -> FAIL (fi-ilk-650) fdo#104008
pass -> FAIL (fi-byt-j1900)
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#105058 https://bugs.freedesktop.org/show_bug.cgi?id=105058
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fi-bdw-5557u total:288 pass:265 dwarn:0 dfail:0 fail:2 skip:21 time:440s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:427s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:378s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:505s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:290s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:487s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:493s
fi-byt-j1900 total:288 pass:252 dwarn:0 dfail:0 fail:1 skip:35 time:475s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:460s
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:570s
fi-cnl-y3 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:581s
fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:415s
fi-gdg-551 total:288 pass:180 dwarn:0 dfail:0 fail:0 skip:108 time:286s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:518s
fi-hsw-4770 total:288 pass:259 dwarn:0 dfail:0 fail:2 skip:27 time:412s
fi-ilk-650 total:288 pass:227 dwarn:0 dfail:0 fail:1 skip:60 time:415s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:453s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:415s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:458s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:499s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:502s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:588s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:430s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:509s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:530s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:487s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:488s
fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:415s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:429s
fi-snb-2520m total:3 pass:2 dwarn:0 dfail:0 fail:0 skip:0
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:403s
Blacklisted hosts:
fi-glk-dsi total:288 pass:179 dwarn:1 dfail:4 fail:0 skip:104 time:770s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:455s
e404d341ffdd255f9a7d8e4461170694edcb3e25 drm-tip: 2018y-02m-14d-01h-12m-17s UTC integration manifest
bac1533d3799 drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
202c444f5119 drm/i915: Add NV12 support to intel_framebuffer_init
f4d627003336 drm/i915: Add NV12 as supported format for sprite plane
8db281883112 drm/i915: Add NV12 as supported format for primary plane
2874a9ba97dd drm/i915: Upscale scaler max scale for NV12
7f1c808ee544 drm/i915: Update format_is_yuv() to include NV12
d4b570fb0893 drm/i915: Set scaler mode for NV12
36bfc5f50a6e drm/i915/skl: split skl_compute_ddb function
06783624255b drm/i915/skl+: nv12 workaround disable WM level 1-7
e33de151b777 drm/i915/skl+: make sure higher latency level has higher wm value
b9bab8ca6a9b drm/i915/skl+: pass skl_wm_level struct to wm compute func
397ec133feb7 drm/i915/skl+: NV12 related changes for WM
08d914614bee drm/i915/skl+: support verification of DDB HW state for NV12
503a7a63f12b drm/i915/skl+: add NV12 in skl_format_to_fourcc
7f00f60fcd67 drm/i915/skl+: refactor WM calculation for NV12
a232d90783ac drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8005/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for Adding NV12 support (rev10)
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
` (17 preceding siblings ...)
2018-02-14 5:46 ` ✗ Fi.CI.BAT: failure for Adding NV12 support (rev10) Patchwork
@ 2018-02-14 12:33 ` Patchwork
2018-02-14 12:37 ` ✗ Fi.CI.SPARSE: " Patchwork
` (7 subsequent siblings)
26 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2018-02-14 12:33 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
== Series Details ==
Series: Adding NV12 support (rev10)
URL : https://patchwork.freedesktop.org/series/28103/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
456856281e51 drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
-:65: CHECK: Alignment should match open parenthesis
#65: FILE: drivers/gpu/drm/i915/intel_pm.c:5048:
+skl_copy_ddb_for_pipe(struct skl_ddb_values *dst,
+ struct skl_ddb_values *src,
total: 0 errors, 0 warnings, 1 checks, 68 lines checked
448d14acd781 drm/i915/skl+: refactor WM calculation for NV12
-:177: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#177: FILE: drivers/gpu/drm/i915/intel_pm.c:4164:
+ uint16_t *minimum, uint16_t *uv_minimum)
-:195: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#195: FILE: drivers/gpu/drm/i915/intel_pm.c:4197:
+ uint16_t uv_minimum[I915_MAX_PLANES] = {};
-:244: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#244: FILE: drivers/gpu/drm/i915/intel_pm.c:4261:
+ uint16_t plane_blocks, uv_plane_blocks;
total: 0 errors, 0 warnings, 3 checks, 293 lines checked
9a8439d2524e drm/i915/skl+: add NV12 in skl_format_to_fourcc
7e5eb3afc28b drm/i915/skl+: support verification of DDB HW state for NV12
269e643e134d drm/i915/skl+: NV12 related changes for WM
034ae546bd95 drm/i915/skl+: pass skl_wm_level struct to wm compute func
13ec9ecbca28 drm/i915/skl+: make sure higher latency level has higher wm value
39a79f30bc12 drm/i915/skl+: nv12 workaround disable WM level 1-7
-:32: CHECK: Unnecessary parentheses around 'level >= 1'
#32: FILE: drivers/gpu/drm/i915/intel_pm.c:4663:
+ if (wp->is_planar && (level >= 1) &&
+ (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
+ IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {
-:33: CHECK: Alignment should match open parenthesis
#33: FILE: drivers/gpu/drm/i915/intel_pm.c:4664:
+ if (wp->is_planar && (level >= 1) &&
+ (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
total: 0 errors, 0 warnings, 2 checks, 17 lines checked
f64fdc96aeb0 drm/i915/skl: split skl_compute_ddb function
-:111: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#111: FILE: drivers/gpu/drm/i915/intel_pm.c:5140:
+ uint32_t realloc_pipes = pipes_modified(state);
-:130: CHECK: spaces preferred around that '*' (ctx:ExV)
#130: FILE: drivers/gpu/drm/i915/intel_pm.c:5159:
+ *changed = true;
^
total: 0 errors, 0 warnings, 2 checks, 194 lines checked
9fac16ad058f drm/i915: Set scaler mode for NV12
-:55: CHECK: Prefer using the BIT macro
#55: FILE: drivers/gpu/drm/i915/i915_reg.h:6735:
+#define PS_SCALER_MODE_PLANAR (1 << 29)
total: 0 errors, 0 warnings, 1 checks, 21 lines checked
292d4032e5ec drm/i915: Update format_is_yuv() to include NV12
3fd146f643dd drm/i915: Upscale scaler max scale for NV12
-:146: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#146: FILE: drivers/gpu/drm/i915/intel_display.c:12836:
+ uint32_t pixel_format = 0;
total: 0 errors, 0 warnings, 1 checks, 119 lines checked
52665035876b drm/i915: Add NV12 as supported format for primary plane
-:57: CHECK: Unnecessary parentheses around 'pipe == PIPE_C'
#57: FILE: drivers/gpu/drm/i915/intel_display.c:13259:
+ if ((INTEL_GEN(dev_priv) == 9 && (pipe == PIPE_C)) &&
+ !IS_GEMINILAKE(dev_priv))
-:58: CHECK: Alignment should match open parenthesis
#58: FILE: drivers/gpu/drm/i915/intel_display.c:13260:
+ if ((INTEL_GEN(dev_priv) == 9 && (pipe == PIPE_C)) &&
+ !IS_GEMINILAKE(dev_priv))
total: 0 errors, 0 warnings, 2 checks, 17 lines checked
5e5dd29d273e drm/i915: Add NV12 as supported format for sprite plane
-:71: CHECK: Alignment should match open parenthesis
#71: FILE: drivers/gpu/drm/i915/intel_sprite.c:1374:
+ if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) &&
+ (plane != 0 || pipe == PIPE_C)) ||
total: 0 errors, 0 warnings, 1 checks, 19 lines checked
44dab66b56ea drm/i915: Add NV12 support to intel_framebuffer_init
-:61: WARNING: line over 80 characters
#61: FILE: drivers/gpu/drm/i915/intel_display.c:14069:
+ drm_get_format_name(mode_cmd->pixel_format,
-:62: CHECK: Alignment should match open parenthesis
#62: FILE: drivers/gpu/drm/i915/intel_display.c:14070:
+ drm_get_format_name(mode_cmd->pixel_format,
+ &format_name));
total: 0 errors, 1 warnings, 1 checks, 14 lines checked
ee9ab23cfc89 drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
-:21: CHECK: Prefer using the BIT macro
#21: FILE: drivers/gpu/drm/i915/i915_reg.h:6458:
+#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17)
total: 0 errors, 0 warnings, 1 checks, 20 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* ✗ Fi.CI.SPARSE: warning for Adding NV12 support (rev10)
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
` (18 preceding siblings ...)
2018-02-14 12:33 ` ✗ Fi.CI.CHECKPATCH: warning " Patchwork
@ 2018-02-14 12:37 ` Patchwork
2018-02-14 13:07 ` Maarten Lankhorst
2018-02-14 12:48 ` ✓ Fi.CI.BAT: success " Patchwork
` (6 subsequent siblings)
26 siblings, 1 reply; 52+ messages in thread
From: Patchwork @ 2018-02-14 12:37 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
== Series Details ==
Series: Adding NV12 support (rev10)
URL : https://patchwork.freedesktop.org/series/28103/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
Okay!
Commit: drm/i915/skl+: refactor WM calculation for NV12
-drivers/gpu/drm/i915/gvt/mmio.c:256:23: warning: memcpy with byte count of 279040
-drivers/gpu/drm/i915/gvt/mmio.c:257:23: warning: memcpy with byte count of 279040
+ ^~
+ ^~
-drivers/gpu/drm/i915/i915_perf.c:1366:15: warning: memset with byte count of 16777216
-drivers/gpu/drm/i915/i915_perf.c:1424:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/intel_pm.c:4656:19: error: no member 'is_nv12' in struct skl_plane_wm
+drivers/gpu/drm/i915/intel_pm.c:4656:19: warning: generating address of non-lvalue (8)
+drivers/gpu/drm/i915/intel_pm.c:4656:5: error: ‘struct skl_plane_wm’ has no member named ‘is_nv12’
+drivers/gpu/drm/i915/intel_pm.c:4834:15: error: no member 'is_nv12' in struct skl_plane_wm
+drivers/gpu/drm/i915/intel_pm.c:4834:15: warning: unknown expression (8 46)
+drivers/gpu/drm/i915/intel_pm.c:4834:8: error: ‘const struct skl_plane_wm’ has no member named ‘is_nv12’
+drivers/gpu/drm/i915/intel_pm.c: In function ‘skl_compute_wm_levels’:
+drivers/gpu/drm/i915/intel_pm.c: In function ‘skl_write_plane_wm’:
+ if (wm->is_nv12) {
+make[1]: *** [drivers/gpu/drm/i915] Error 2
+make[2]: *** [drivers/gpu/drm/i915/intel_pm.o] Error 1
+make[2]: *** Waiting for unfinished jobs....
+make[2]: *** wait: No child processes. Stop.
+make: *** [drivers/gpu/drm/] Error 2
+ wm->is_nv12 = true;
Commit: drm/i915/skl+: add NV12 in skl_format_to_fourcc
-drivers/gpu/drm/i915/i915_perf.c:1366:15: warning: memset with byte count of 16777216
-drivers/gpu/drm/i915/i915_perf.c:1424:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/gvt/mmio.c:256:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/gvt/mmio.c:257:23: warning: memcpy with byte count of 279040
Commit: drm/i915/skl+: support verification of DDB HW state for NV12
-make[2]: *** wait: No child processes. Stop.
Commit: drm/i915/skl+: NV12 related changes for WM
- ^~
- ^~
+drivers/gpu/drm/i915/gvt/mmio.c:256:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/gvt/mmio.c:257:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1366:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1424:15: warning: memset with byte count of 16777216
-O:drivers/gpu/drm/i915/intel_pm.c:4687:19: error: no member 'is_nv12' in struct skl_plane_wm
-O:drivers/gpu/drm/i915/intel_pm.c:4687:19: warning: generating address of non-lvalue (8)
-O:drivers/gpu/drm/i915/intel_pm.c:4687:5: error: ‘struct skl_plane_wm’ has no member named ‘is_nv12’
-O:drivers/gpu/drm/i915/intel_pm.c:4865:15: error: no member 'is_nv12' in struct skl_plane_wm
-O:drivers/gpu/drm/i915/intel_pm.c:4865:15: warning: unknown expression (8 46)
-O:drivers/gpu/drm/i915/intel_pm.c:4865:8: error: ‘const struct skl_plane_wm’ has no member named ‘is_nv12’
-drivers/gpu/drm/i915/intel_pm.c: In function ‘skl_compute_wm_levels’:
-drivers/gpu/drm/i915/intel_pm.c: In function ‘skl_write_plane_wm’:
- if (wm->is_nv12) {
-make[1]: *** [drivers/gpu/drm/i915] Error 2
-make[2]: *** [drivers/gpu/drm/i915/intel_pm.o] Error 1
-make[2]: *** Waiting for unfinished jobs....
-make[2]: *** wait: No child processes. Stop.
-make: *** [drivers/gpu/drm/] Error 2
- wm->is_nv12 = true;
Commit: drm/i915/skl+: pass skl_wm_level struct to wm compute func
Okay!
Commit: drm/i915/skl+: make sure higher latency level has higher wm value
Okay!
Commit: drm/i915/skl+: nv12 workaround disable WM level 1-7
Okay!
Commit: drm/i915/skl: split skl_compute_ddb function
Okay!
Commit: drm/i915: Set scaler mode for NV12
Okay!
Commit: drm/i915: Update format_is_yuv() to include NV12
Okay!
Commit: drm/i915: Upscale scaler max scale for NV12
Okay!
Commit: drm/i915: Add NV12 as supported format for primary plane
Okay!
Commit: drm/i915: Add NV12 as supported format for sprite plane
Okay!
Commit: drm/i915: Add NV12 support to intel_framebuffer_init
Okay!
Commit: drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: ✗ Fi.CI.SPARSE: warning for Adding NV12 support (rev10)
2018-02-14 12:37 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2018-02-14 13:07 ` Maarten Lankhorst
2018-02-14 14:03 ` Arkadiusz Hiler
0 siblings, 1 reply; 52+ messages in thread
From: Maarten Lankhorst @ 2018-02-14 13:07 UTC (permalink / raw)
To: Vidya Srinivas; +Cc: intel-gfx
Op 14-02-18 om 13:37 schreef Patchwork:
> == Series Details ==
>
> Series: Adding NV12 support (rev10)
> URL : https://patchwork.freedesktop.org/series/28103/
> State : warning
>
> == Summary ==
>
> $ dim sparse origin/drm-tip
> Commit: drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
> Okay!
>
> Commit: drm/i915/skl+: refactor WM calculation for NV12
> -drivers/gpu/drm/i915/gvt/mmio.c:256:23: warning: memcpy with byte count of 279040
> -drivers/gpu/drm/i915/gvt/mmio.c:257:23: warning: memcpy with byte count of 279040
> + ^~
> + ^~
> -drivers/gpu/drm/i915/i915_perf.c:1366:15: warning: memset with byte count of 16777216
> -drivers/gpu/drm/i915/i915_perf.c:1424:15: warning: memset with byte count of 16777216
> +drivers/gpu/drm/i915/intel_pm.c:4656:19: error: no member 'is_nv12' in struct skl_plane_wm
> +drivers/gpu/drm/i915/intel_pm.c:4656:19: warning: generating address of non-lvalue (8)
> +drivers/gpu/drm/i915/intel_pm.c:4656:5: error: ‘struct skl_plane_wm’ has no member named ‘is_nv12’
> +drivers/gpu/drm/i915/intel_pm.c:4834:15: error: no member 'is_nv12' in struct skl_plane_wm
> +drivers/gpu/drm/i915/intel_pm.c:4834:15: warning: unknown expression (8 46)
> +drivers/gpu/drm/i915/intel_pm.c:4834:8: error: ‘const struct skl_plane_wm’ has no member named ‘is_nv12’
> +drivers/gpu/drm/i915/intel_pm.c: In function ‘skl_compute_wm_levels’:
> +drivers/gpu/drm/i915/intel_pm.c: In function ‘skl_write_plane_wm’:
> + if (wm->is_nv12) {
> +make[1]: *** [drivers/gpu/drm/i915] Error 2
> +make[2]: *** [drivers/gpu/drm/i915/intel_pm.o] Error 1
> +make[2]: *** Waiting for unfinished jobs....
> +make[2]: *** wait: No child processes. Stop.
> +make: *** [drivers/gpu/drm/] Error 2
> + wm->is_nv12 = true;
>
> Commit: drm/i915/skl+: add NV12 in skl_format_to_fourcc
> -drivers/gpu/drm/i915/i915_perf.c:1366:15: warning: memset with byte count of 16777216
> -drivers/gpu/drm/i915/i915_perf.c:1424:15: warning: memset with byte count of 16777216
> +drivers/gpu/drm/i915/gvt/mmio.c:256:23: warning: memcpy with byte count of 279040
> +drivers/gpu/drm/i915/gvt/mmio.c:257:23: warning: memcpy with byte count of 279040
>
> Commit: drm/i915/skl+: support verification of DDB HW state for NV12
> -make[2]: *** wait: No child processes. Stop.
>
> Commit: drm/i915/skl+: NV12 related changes for WM
> - ^~
> - ^~
> +drivers/gpu/drm/i915/gvt/mmio.c:256:23: warning: memcpy with byte count of 279040
> +drivers/gpu/drm/i915/gvt/mmio.c:257:23: warning: memcpy with byte count of 279040
> +drivers/gpu/drm/i915/i915_perf.c:1366:15: warning: memset with byte count of 16777216
> +drivers/gpu/drm/i915/i915_perf.c:1424:15: warning: memset with byte count of 16777216
> -O:drivers/gpu/drm/i915/intel_pm.c:4687:19: error: no member 'is_nv12' in struct skl_plane_wm
> -O:drivers/gpu/drm/i915/intel_pm.c:4687:19: warning: generating address of non-lvalue (8)
> -O:drivers/gpu/drm/i915/intel_pm.c:4687:5: error: ‘struct skl_plane_wm’ has no member named ‘is_nv12’
> -O:drivers/gpu/drm/i915/intel_pm.c:4865:15: error: no member 'is_nv12' in struct skl_plane_wm
> -O:drivers/gpu/drm/i915/intel_pm.c:4865:15: warning: unknown expression (8 46)
> -O:drivers/gpu/drm/i915/intel_pm.c:4865:8: error: ‘const struct skl_plane_wm’ has no member named ‘is_nv12’
> -drivers/gpu/drm/i915/intel_pm.c: In function ‘skl_compute_wm_levels’:
> -drivers/gpu/drm/i915/intel_pm.c: In function ‘skl_write_plane_wm’:
> - if (wm->is_nv12) {
> -make[1]: *** [drivers/gpu/drm/i915] Error 2
> -make[2]: *** [drivers/gpu/drm/i915/intel_pm.o] Error 1
> -make[2]: *** Waiting for unfinished jobs....
> -make[2]: *** wait: No child processes. Stop.
> -make: *** [drivers/gpu/drm/] Error 2
> - wm->is_nv12 = true;
Looks like not all commits compile on their own?
~Maarten
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* Re: ✗ Fi.CI.SPARSE: warning for Adding NV12 support (rev10)
2018-02-14 13:07 ` Maarten Lankhorst
@ 2018-02-14 14:03 ` Arkadiusz Hiler
0 siblings, 0 replies; 52+ messages in thread
From: Arkadiusz Hiler @ 2018-02-14 14:03 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx, Vidya Srinivas
On Wed, Feb 14, 2018 at 02:07:49PM +0100, Maarten Lankhorst wrote:
> Op 14-02-18 om 13:37 schreef Patchwork:
> > == Series Details ==
> >
> > Series: Adding NV12 support (rev10)
> > URL : https://patchwork.freedesktop.org/series/28103/
> > State : warning
> >
> > == Summary ==
> >
> > $ dim sparse origin/drm-tip
> > Commit: drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
> > Okay!
> >
> > Commit: drm/i915/skl+: refactor WM calculation for NV12
> > -drivers/gpu/drm/i915/gvt/mmio.c:256:23: warning: memcpy with byte count of 279040
> > -drivers/gpu/drm/i915/gvt/mmio.c:257:23: warning: memcpy with byte count of 279040
> > + ^~
> > + ^~
> > -drivers/gpu/drm/i915/i915_perf.c:1366:15: warning: memset with byte count of 16777216
> > -drivers/gpu/drm/i915/i915_perf.c:1424:15: warning: memset with byte count of 16777216
> > +drivers/gpu/drm/i915/intel_pm.c:4656:19: error: no member 'is_nv12' in struct skl_plane_wm
> > +drivers/gpu/drm/i915/intel_pm.c:4656:19: warning: generating address of non-lvalue (8)
> > +drivers/gpu/drm/i915/intel_pm.c:4656:5: error: ‘struct skl_plane_wm’ has no member named ‘is_nv12’
> > +drivers/gpu/drm/i915/intel_pm.c:4834:15: error: no member 'is_nv12' in struct skl_plane_wm
> > +drivers/gpu/drm/i915/intel_pm.c:4834:15: warning: unknown expression (8 46)
> > +drivers/gpu/drm/i915/intel_pm.c:4834:8: error: ‘const struct skl_plane_wm’ has no member named ‘is_nv12’
> > +drivers/gpu/drm/i915/intel_pm.c: In function ‘skl_compute_wm_levels’:
> > +drivers/gpu/drm/i915/intel_pm.c: In function ‘skl_write_plane_wm’:
> > + if (wm->is_nv12) {
> > +make[1]: *** [drivers/gpu/drm/i915] Error 2
> > +make[2]: *** [drivers/gpu/drm/i915/intel_pm.o] Error 1
> > +make[2]: *** Waiting for unfinished jobs....
> > +make[2]: *** wait: No child processes. Stop.
> > +make: *** [drivers/gpu/drm/] Error 2
> > + wm->is_nv12 = true;
> >
> > Commit: drm/i915/skl+: add NV12 in skl_format_to_fourcc
> > -drivers/gpu/drm/i915/i915_perf.c:1366:15: warning: memset with byte count of 16777216
> > -drivers/gpu/drm/i915/i915_perf.c:1424:15: warning: memset with byte count of 16777216
> > +drivers/gpu/drm/i915/gvt/mmio.c:256:23: warning: memcpy with byte count of 279040
> > +drivers/gpu/drm/i915/gvt/mmio.c:257:23: warning: memcpy with byte count of 279040
> >
> > Commit: drm/i915/skl+: support verification of DDB HW state for NV12
> > -make[2]: *** wait: No child processes. Stop.
> >
> > Commit: drm/i915/skl+: NV12 related changes for WM
> > - ^~
> > - ^~
> > +drivers/gpu/drm/i915/gvt/mmio.c:256:23: warning: memcpy with byte count of 279040
> > +drivers/gpu/drm/i915/gvt/mmio.c:257:23: warning: memcpy with byte count of 279040
> > +drivers/gpu/drm/i915/i915_perf.c:1366:15: warning: memset with byte count of 16777216
> > +drivers/gpu/drm/i915/i915_perf.c:1424:15: warning: memset with byte count of 16777216
> > -O:drivers/gpu/drm/i915/intel_pm.c:4687:19: error: no member 'is_nv12' in struct skl_plane_wm
> > -O:drivers/gpu/drm/i915/intel_pm.c:4687:19: warning: generating address of non-lvalue (8)
> > -O:drivers/gpu/drm/i915/intel_pm.c:4687:5: error: ‘struct skl_plane_wm’ has no member named ‘is_nv12’
> > -O:drivers/gpu/drm/i915/intel_pm.c:4865:15: error: no member 'is_nv12' in struct skl_plane_wm
> > -O:drivers/gpu/drm/i915/intel_pm.c:4865:15: warning: unknown expression (8 46)
> > -O:drivers/gpu/drm/i915/intel_pm.c:4865:8: error: ‘const struct skl_plane_wm’ has no member named ‘is_nv12’
> > -drivers/gpu/drm/i915/intel_pm.c: In function ‘skl_compute_wm_levels’:
> > -drivers/gpu/drm/i915/intel_pm.c: In function ‘skl_write_plane_wm’:
> > - if (wm->is_nv12) {
> > -make[1]: *** [drivers/gpu/drm/i915] Error 2
> > -make[2]: *** [drivers/gpu/drm/i915/intel_pm.o] Error 1
> > -make[2]: *** Waiting for unfinished jobs....
> > -make[2]: *** wait: No child processes. Stop.
> > -make: *** [drivers/gpu/drm/] Error 2
> > - wm->is_nv12 = true;
> Looks like not all commits compile on their own?
> ~Maarten
Yep. That is exactly the case. We run sparse build incrementally, i.e.
applying one patch after another, building and looking for any
difference in what is reported.
Patch
> Commit: drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
breaks compilation.
Please fix that. You can check your series locally with something like:
git rebase HEAD~12 --exec make
--
Cheers,
Arek
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread
* ✓ Fi.CI.BAT: success for Adding NV12 support (rev10)
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
` (19 preceding siblings ...)
2018-02-14 12:37 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2018-02-14 12:48 ` Patchwork
2018-02-14 14:10 ` ✗ Fi.CI.CHECKPATCH: warning " Patchwork
` (5 subsequent siblings)
26 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2018-02-14 12:48 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
== Series Details ==
Series: Adding NV12 support (rev10)
URL : https://patchwork.freedesktop.org/series/28103/
State : success
== Summary ==
Series 28103v10 Adding NV12 support
https://patchwork.freedesktop.org/api/1.0/series/28103/revisions/10/mbox/
Test prime_vgem:
Subgroup basic-fence-flip:
pass -> FAIL (fi-ilk-650) fdo#104008
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:416s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:429s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:375s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:487s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:290s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:483s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:469s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:454s
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:570s
fi-cnl-y3 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:576s
fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:410s
fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:280s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:509s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:388s
fi-ilk-650 total:288 pass:227 dwarn:0 dfail:0 fail:1 skip:60 time:409s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:461s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:413s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:459s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:493s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:501s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:590s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:426s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:504s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:528s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:495s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:471s
fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:417s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:430s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:530s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:394s
Blacklisted hosts:
fi-glk-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:465s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:455s
fi-bxt-dsi failed to collect. IGT log at Patchwork_8013/fi-bxt-dsi/run0.log
e34af189963498c5168b4b5ba0a9be7aa96f69e1 drm-tip: 2018y-02m-14d-11h-50m-53s UTC integration manifest
ee9ab23cfc89 drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
44dab66b56ea drm/i915: Add NV12 support to intel_framebuffer_init
5e5dd29d273e drm/i915: Add NV12 as supported format for sprite plane
52665035876b drm/i915: Add NV12 as supported format for primary plane
3fd146f643dd drm/i915: Upscale scaler max scale for NV12
292d4032e5ec drm/i915: Update format_is_yuv() to include NV12
9fac16ad058f drm/i915: Set scaler mode for NV12
f64fdc96aeb0 drm/i915/skl: split skl_compute_ddb function
39a79f30bc12 drm/i915/skl+: nv12 workaround disable WM level 1-7
13ec9ecbca28 drm/i915/skl+: make sure higher latency level has higher wm value
034ae546bd95 drm/i915/skl+: pass skl_wm_level struct to wm compute func
269e643e134d drm/i915/skl+: NV12 related changes for WM
7e5eb3afc28b drm/i915/skl+: support verification of DDB HW state for NV12
9a8439d2524e drm/i915/skl+: add NV12 in skl_format_to_fourcc
448d14acd781 drm/i915/skl+: refactor WM calculation for NV12
456856281e51 drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8013/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for Adding NV12 support (rev10)
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
` (20 preceding siblings ...)
2018-02-14 12:48 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-02-14 14:10 ` Patchwork
2018-02-14 14:14 ` ✗ Fi.CI.SPARSE: " Patchwork
` (4 subsequent siblings)
26 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2018-02-14 14:10 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
== Series Details ==
Series: Adding NV12 support (rev10)
URL : https://patchwork.freedesktop.org/series/28103/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6e8ea1c042eb drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
-:65: CHECK: Alignment should match open parenthesis
#65: FILE: drivers/gpu/drm/i915/intel_pm.c:5048:
+skl_copy_ddb_for_pipe(struct skl_ddb_values *dst,
+ struct skl_ddb_values *src,
total: 0 errors, 0 warnings, 1 checks, 68 lines checked
30eb3a788144 drm/i915/skl+: refactor WM calculation for NV12
-:177: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#177: FILE: drivers/gpu/drm/i915/intel_pm.c:4164:
+ uint16_t *minimum, uint16_t *uv_minimum)
-:195: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#195: FILE: drivers/gpu/drm/i915/intel_pm.c:4197:
+ uint16_t uv_minimum[I915_MAX_PLANES] = {};
-:244: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#244: FILE: drivers/gpu/drm/i915/intel_pm.c:4261:
+ uint16_t plane_blocks, uv_plane_blocks;
total: 0 errors, 0 warnings, 3 checks, 293 lines checked
e8d4aa625cc3 drm/i915/skl+: add NV12 in skl_format_to_fourcc
f995dc9b92e0 drm/i915/skl+: support verification of DDB HW state for NV12
a41cb6ea7434 drm/i915/skl+: NV12 related changes for WM
c1d175ff311e drm/i915/skl+: pass skl_wm_level struct to wm compute func
63822fee142a drm/i915/skl+: make sure higher latency level has higher wm value
59a9d6928dbf drm/i915/skl+: nv12 workaround disable WM level 1-7
-:32: CHECK: Unnecessary parentheses around 'level >= 1'
#32: FILE: drivers/gpu/drm/i915/intel_pm.c:4663:
+ if (wp->is_planar && (level >= 1) &&
+ (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
+ IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {
-:33: CHECK: Alignment should match open parenthesis
#33: FILE: drivers/gpu/drm/i915/intel_pm.c:4664:
+ if (wp->is_planar && (level >= 1) &&
+ (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
total: 0 errors, 0 warnings, 2 checks, 17 lines checked
1b76997e221e drm/i915/skl: split skl_compute_ddb function
-:111: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#111: FILE: drivers/gpu/drm/i915/intel_pm.c:5140:
+ uint32_t realloc_pipes = pipes_modified(state);
-:130: CHECK: spaces preferred around that '*' (ctx:ExV)
#130: FILE: drivers/gpu/drm/i915/intel_pm.c:5159:
+ *changed = true;
^
total: 0 errors, 0 warnings, 2 checks, 194 lines checked
03a7f4c2c145 drm/i915: Set scaler mode for NV12
-:55: CHECK: Prefer using the BIT macro
#55: FILE: drivers/gpu/drm/i915/i915_reg.h:6735:
+#define PS_SCALER_MODE_PLANAR (1 << 29)
total: 0 errors, 0 warnings, 1 checks, 21 lines checked
3a9703128148 drm/i915: Update format_is_yuv() to include NV12
01f0c6f70548 drm/i915: Upscale scaler max scale for NV12
-:146: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#146: FILE: drivers/gpu/drm/i915/intel_display.c:12836:
+ uint32_t pixel_format = 0;
total: 0 errors, 0 warnings, 1 checks, 119 lines checked
f1903a03f713 drm/i915: Add NV12 as supported format for primary plane
-:57: CHECK: Unnecessary parentheses around 'pipe == PIPE_C'
#57: FILE: drivers/gpu/drm/i915/intel_display.c:13259:
+ if ((INTEL_GEN(dev_priv) == 9 && (pipe == PIPE_C)) &&
+ !IS_GEMINILAKE(dev_priv))
-:58: CHECK: Alignment should match open parenthesis
#58: FILE: drivers/gpu/drm/i915/intel_display.c:13260:
+ if ((INTEL_GEN(dev_priv) == 9 && (pipe == PIPE_C)) &&
+ !IS_GEMINILAKE(dev_priv))
total: 0 errors, 0 warnings, 2 checks, 17 lines checked
ae5ae7ff03c9 drm/i915: Add NV12 as supported format for sprite plane
-:71: CHECK: Alignment should match open parenthesis
#71: FILE: drivers/gpu/drm/i915/intel_sprite.c:1374:
+ if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) &&
+ (plane != 0 || pipe == PIPE_C)) ||
total: 0 errors, 0 warnings, 1 checks, 19 lines checked
ce89283213c8 drm/i915: Add NV12 support to intel_framebuffer_init
-:61: WARNING: line over 80 characters
#61: FILE: drivers/gpu/drm/i915/intel_display.c:14069:
+ drm_get_format_name(mode_cmd->pixel_format,
-:62: CHECK: Alignment should match open parenthesis
#62: FILE: drivers/gpu/drm/i915/intel_display.c:14070:
+ drm_get_format_name(mode_cmd->pixel_format,
+ &format_name));
total: 0 errors, 1 warnings, 1 checks, 14 lines checked
cbd0c912abc5 drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
-:21: CHECK: Prefer using the BIT macro
#21: FILE: drivers/gpu/drm/i915/i915_reg.h:6458:
+#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17)
total: 0 errors, 0 warnings, 1 checks, 20 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* ✗ Fi.CI.SPARSE: warning for Adding NV12 support (rev10)
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
` (21 preceding siblings ...)
2018-02-14 14:10 ` ✗ Fi.CI.CHECKPATCH: warning " Patchwork
@ 2018-02-14 14:14 ` Patchwork
2018-02-14 14:26 ` ✓ Fi.CI.BAT: success " Patchwork
` (3 subsequent siblings)
26 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2018-02-14 14:14 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
== Series Details ==
Series: Adding NV12 support (rev10)
URL : https://patchwork.freedesktop.org/series/28103/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
Okay!
Commit: drm/i915/skl+: refactor WM calculation for NV12
-drivers/gpu/drm/i915/gvt/mmio.c:256:23: warning: memcpy with byte count of 279040
-drivers/gpu/drm/i915/gvt/mmio.c:257:23: warning: memcpy with byte count of 279040
+ ^~
+ ^~
-drivers/gpu/drm/i915/i915_perf.c:1366:15: warning: memset with byte count of 16777216
-drivers/gpu/drm/i915/i915_perf.c:1424:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/intel_pm.c:4656:19: error: no member 'is_nv12' in struct skl_plane_wm
+drivers/gpu/drm/i915/intel_pm.c:4656:19: warning: generating address of non-lvalue (8)
+drivers/gpu/drm/i915/intel_pm.c:4656:5: error: ‘struct skl_plane_wm’ has no member named ‘is_nv12’
+drivers/gpu/drm/i915/intel_pm.c:4834:15: error: no member 'is_nv12' in struct skl_plane_wm
+drivers/gpu/drm/i915/intel_pm.c:4834:15: warning: unknown expression (8 46)
+drivers/gpu/drm/i915/intel_pm.c:4834:8: error: ‘const struct skl_plane_wm’ has no member named ‘is_nv12’
+drivers/gpu/drm/i915/intel_pm.c: In function ‘skl_compute_wm_levels’:
+drivers/gpu/drm/i915/intel_pm.c: In function ‘skl_write_plane_wm’:
+ if (wm->is_nv12) {
+make[1]: *** [drivers/gpu/drm/i915] Error 2
+make[2]: *** [drivers/gpu/drm/i915/intel_pm.o] Error 1
+make[2]: *** Waiting for unfinished jobs....
+make[2]: *** wait: No child processes. Stop.
+make: *** [drivers/gpu/drm/] Error 2
+ wm->is_nv12 = true;
Commit: drm/i915/skl+: add NV12 in skl_format_to_fourcc
-drivers/gpu/drm/i915/gvt/mmio.c:256:23: warning: memcpy with byte count of 279040
-drivers/gpu/drm/i915/gvt/mmio.c:257:23: warning: memcpy with byte count of 279040
-drivers/gpu/drm/i915/i915_perf.c:1366:15: warning: memset with byte count of 16777216
-drivers/gpu/drm/i915/i915_perf.c:1424:15: warning: memset with byte count of 16777216
Commit: drm/i915/skl+: support verification of DDB HW state for NV12
Okay!
Commit: drm/i915/skl+: NV12 related changes for WM
- ^~
- ^~
+drivers/gpu/drm/i915/gvt/mmio.c:256:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/gvt/mmio.c:257:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1366:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1424:15: warning: memset with byte count of 16777216
-O:drivers/gpu/drm/i915/intel_pm.c:4687:19: error: no member 'is_nv12' in struct skl_plane_wm
-O:drivers/gpu/drm/i915/intel_pm.c:4687:19: warning: generating address of non-lvalue (8)
-O:drivers/gpu/drm/i915/intel_pm.c:4687:5: error: ‘struct skl_plane_wm’ has no member named ‘is_nv12’
-O:drivers/gpu/drm/i915/intel_pm.c:4865:15: error: no member 'is_nv12' in struct skl_plane_wm
-O:drivers/gpu/drm/i915/intel_pm.c:4865:15: warning: unknown expression (8 46)
-O:drivers/gpu/drm/i915/intel_pm.c:4865:8: error: ‘const struct skl_plane_wm’ has no member named ‘is_nv12’
-drivers/gpu/drm/i915/intel_pm.c: In function ‘skl_compute_wm_levels’:
-drivers/gpu/drm/i915/intel_pm.c: In function ‘skl_write_plane_wm’:
- if (wm->is_nv12) {
-make[1]: *** [drivers/gpu/drm/i915] Error 2
-make[2]: *** [drivers/gpu/drm/i915/intel_pm.o] Error 1
-make[2]: *** Waiting for unfinished jobs....
-make[2]: *** wait: No child processes. Stop.
-make: *** [drivers/gpu/drm/] Error 2
- wm->is_nv12 = true;
Commit: drm/i915/skl+: pass skl_wm_level struct to wm compute func
Okay!
Commit: drm/i915/skl+: make sure higher latency level has higher wm value
Okay!
Commit: drm/i915/skl+: nv12 workaround disable WM level 1-7
Okay!
Commit: drm/i915/skl: split skl_compute_ddb function
Okay!
Commit: drm/i915: Set scaler mode for NV12
Okay!
Commit: drm/i915: Update format_is_yuv() to include NV12
Okay!
Commit: drm/i915: Upscale scaler max scale for NV12
Okay!
Commit: drm/i915: Add NV12 as supported format for primary plane
Okay!
Commit: drm/i915: Add NV12 as supported format for sprite plane
Okay!
Commit: drm/i915: Add NV12 support to intel_framebuffer_init
Okay!
Commit: drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* ✓ Fi.CI.BAT: success for Adding NV12 support (rev10)
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
` (22 preceding siblings ...)
2018-02-14 14:14 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2018-02-14 14:26 ` Patchwork
2018-02-14 14:29 ` ✓ Fi.CI.IGT: " Patchwork
` (2 subsequent siblings)
26 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2018-02-14 14:26 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
== Series Details ==
Series: Adding NV12 support (rev10)
URL : https://patchwork.freedesktop.org/series/28103/
State : success
== Summary ==
Series 28103v10 Adding NV12 support
https://patchwork.freedesktop.org/api/1.0/series/28103/revisions/10/mbox/
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> INCOMPLETE (fi-snb-2520m) fdo#103713
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:423s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:425s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:374s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:495s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:287s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:484s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:468s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:464s
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:579s
fi-cnl-y3 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:582s
fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:417s
fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:281s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:508s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:389s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:413s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:469s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:413s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:455s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:495s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:500s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:590s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:431s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:506s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:525s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:482s
fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:416s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:430s
fi-snb-2520m total:245 pass:211 dwarn:0 dfail:0 fail:0 skip:33
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:399s
Blacklisted hosts:
fi-glk-dsi total:117 pass:104 dwarn:0 dfail:0 fail:0 skip:12
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:451s
8ee739e0bcde50bd5ce8d40d57a1a146e167756d drm-tip: 2018y-02m-14d-13h-29m-07s UTC integration manifest
cbd0c912abc5 drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
ce89283213c8 drm/i915: Add NV12 support to intel_framebuffer_init
ae5ae7ff03c9 drm/i915: Add NV12 as supported format for sprite plane
f1903a03f713 drm/i915: Add NV12 as supported format for primary plane
01f0c6f70548 drm/i915: Upscale scaler max scale for NV12
3a9703128148 drm/i915: Update format_is_yuv() to include NV12
03a7f4c2c145 drm/i915: Set scaler mode for NV12
1b76997e221e drm/i915/skl: split skl_compute_ddb function
59a9d6928dbf drm/i915/skl+: nv12 workaround disable WM level 1-7
63822fee142a drm/i915/skl+: make sure higher latency level has higher wm value
c1d175ff311e drm/i915/skl+: pass skl_wm_level struct to wm compute func
a41cb6ea7434 drm/i915/skl+: NV12 related changes for WM
f995dc9b92e0 drm/i915/skl+: support verification of DDB HW state for NV12
e8d4aa625cc3 drm/i915/skl+: add NV12 in skl_format_to_fourcc
30eb3a788144 drm/i915/skl+: refactor WM calculation for NV12
6e8ea1c042eb drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8017/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* ✓ Fi.CI.IGT: success for Adding NV12 support (rev10)
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
` (23 preceding siblings ...)
2018-02-14 14:26 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-02-14 14:29 ` Patchwork
2018-02-14 14:48 ` Maarten Lankhorst
2018-02-14 18:53 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-02-14 20:02 ` ✗ Fi.CI.IGT: warning " Patchwork
26 siblings, 1 reply; 52+ messages in thread
From: Patchwork @ 2018-02-14 14:29 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
== Series Details ==
Series: Adding NV12 support (rev10)
URL : https://patchwork.freedesktop.org/series/28103/
State : success
== Summary ==
Blacklisted hosts:
shard-glkb total:3427 pass:1715 dwarn:7 dfail:0 fail:190 skip:1515 time:16731s
shard-kbl total:3370 pass:1869 dwarn:3 dfail:0 fail:23 skip:1474 time:10922s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8005/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 52+ messages in thread* ✗ Fi.CI.IGT: failure for Adding NV12 support (rev10)
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
` (24 preceding siblings ...)
2018-02-14 14:29 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-02-14 18:53 ` Patchwork
2018-02-14 20:02 ` ✗ Fi.CI.IGT: warning " Patchwork
26 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2018-02-14 18:53 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
== Series Details ==
Series: Adding NV12 support (rev10)
URL : https://patchwork.freedesktop.org/series/28103/
State : failure
== Summary ==
Test gem_eio:
Subgroup in-flight-contexts:
pass -> DMESG-WARN (shard-snb) fdo#104058
Test kms_cursor_legacy:
Subgroup flip-vs-cursor-crc-atomic:
pass -> FAIL (shard-apl) fdo#102670
Subgroup 2x-long-flip-vs-cursor-legacy:
fail -> PASS (shard-hsw) fdo#104873
Test kms_flip:
Subgroup 2x-plain-flip-ts-check:
pass -> FAIL (shard-hsw) fdo#100368 +1
Subgroup flip-vs-modeset-vs-hang:
pass -> DMESG-WARN (shard-snb) fdo#103821
Subgroup 2x-dpms-vs-vblank-race-interruptible:
fail -> PASS (shard-hsw) fdo#103060
Test kms_plane_scaling:
Subgroup pipe-b-scaler-with-rotation:
pass -> DMESG-WARN (shard-apl)
Subgroup pipe-a-scaler-with-rotation:
pass -> DMESG-WARN (shard-apl)
Test gem_softpin:
Subgroup noreloc-s3:
skip -> PASS (shard-snb) fdo#103375
Test perf:
Subgroup buffer-fill:
fail -> PASS (shard-apl) fdo#103755
Test kms_vblank:
Subgroup pipe-b-ts-continuation-suspend:
pass -> INCOMPLETE (shard-hsw)
Test kms_plane:
Subgroup pixel-format-pipe-b-planes:
pass -> DMESG-WARN (shard-apl)
fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058
fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670
fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103821 https://bugs.freedesktop.org/show_bug.cgi?id=103821
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755
shard-apl total:3346 pass:1734 dwarn:4 dfail:0 fail:21 skip:1586 time:13958s
shard-hsw total:3350 pass:1720 dwarn:1 dfail:0 fail:13 skip:1614 time:14108s
shard-snb total:3427 pass:1347 dwarn:3 dfail:0 fail:10 skip:2067 time:7681s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8013/shards.html
_______________________________________________
Intel-gfx mailing list
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^ permalink raw reply [flat|nested] 52+ messages in thread* ✗ Fi.CI.IGT: warning for Adding NV12 support (rev10)
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
` (25 preceding siblings ...)
2018-02-14 18:53 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2018-02-14 20:02 ` Patchwork
26 siblings, 0 replies; 52+ messages in thread
From: Patchwork @ 2018-02-14 20:02 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx
== Series Details ==
Series: Adding NV12 support (rev10)
URL : https://patchwork.freedesktop.org/series/28103/
State : warning
== Summary ==
Test kms_color:
Subgroup pipe-a-degamma:
pass -> FAIL (shard-apl) fdo#104782
Test kms_plane_scaling:
Subgroup pipe-b-scaler-with-rotation:
pass -> DMESG-WARN (shard-apl)
Subgroup pipe-a-scaler-with-rotation:
pass -> DMESG-WARN (shard-apl)
Test kms_flip:
Subgroup plain-flip-ts-check:
pass -> FAIL (shard-snb) fdo#100368
Test kms_plane_lowres:
Subgroup pipe-a-tiling-yf:
fail -> PASS (shard-apl)
Test kms_setmode:
Subgroup basic:
pass -> FAIL (shard-hsw) fdo#99912
Test perf:
Subgroup oa-exponents:
fail -> PASS (shard-apl) fdo#102254
Subgroup polling:
pass -> FAIL (shard-hsw) fdo#102252
Test perf_pmu:
Subgroup busy-start-vcs0:
fail -> PASS (shard-snb)
Test kms_sysfs_edid_timing:
warn -> PASS (shard-apl) fdo#100047
fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
shard-apl total:3346 pass:1734 dwarn:3 dfail:0 fail:22 skip:1586 time:13990s
shard-hsw total:3427 pass:1757 dwarn:1 dfail:0 fail:12 skip:1656 time:14635s
shard-snb total:3427 pass:1347 dwarn:1 dfail:0 fail:11 skip:2068 time:7595s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8017/shards.html
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