From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> To: Konrad Dybcio <konrad.dybcio@linaro.org>, Rob Clark <robdclark@gmail.com>, Abhinav Kumar <quic_abhinavk@quicinc.com>, Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch> Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/5] drm/msm/a2xx: Implement .gpu_busy Date: Thu, 23 Feb 2023 00:24:02 +0200 [thread overview] Message-ID: <9b535af0-7159-14b3-560f-197c7153b78c@linaro.org> (raw) In-Reply-To: <20230222-konrad-longbois-next-v1-2-01021425781b@linaro.org> On 22/02/2023 23:47, Konrad Dybcio wrote: > Implement gpu_busy based on the downstream msm-3.4 code [1]. This > allows us to use devfreq on this old old old hardware! > > [1] https://github.com/LineageOS/android_kernel_sony_apq8064/blob/lineage-16.0/drivers/gpu/msm/adreno_a2xx.c#L1975 > > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 28 ++++++++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c > index c67089a7ebc1..6258c98e5a88 100644 > --- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c > @@ -481,6 +481,33 @@ a2xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) > return aspace; > } > > +/* While the precise size of this field is unknown, it holds at least these three values.. */ > +#define PERF_MODE_CNT GENMASK(2, 0) > + #define PERF_STATE_RESET 0x0 > + #define PERF_STATE_ENABLE 0x1 > + #define PERF_STATE_FREEZE 0x2 These should go into a2xx.xml.h LGTM otherwise. > +static u64 a2xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) > +{ > + u64 busy_cycles; > + > + /* Freeze the counter */ > + gpu_write(gpu, REG_A2XX_CP_PERFMON_CNTL, FIELD_PREP(PERF_MODE_CNT, PERF_STATE_FREEZE)); > + > + busy_cycles = gpu_read64(gpu, REG_A2XX_RBBM_PERFCOUNTER1_LO); > + > + /* Reset the counter */ > + gpu_write(gpu, REG_A2XX_CP_PERFMON_CNTL, FIELD_PREP(PERF_MODE_CNT, PERF_STATE_RESET)); > + > + /* Re-enable the performance monitors */ > + gpu_rmw(gpu, REG_A2XX_RBBM_PM_OVERRIDE2, BIT(6), BIT(6)); > + gpu_write(gpu, REG_A2XX_RBBM_PERFCOUNTER1_SELECT, 1); > + gpu_write(gpu, REG_A2XX_CP_PERFMON_CNTL, FIELD_PREP(PERF_MODE_CNT, PERF_STATE_ENABLE)); > + > + *out_sample_rate = clk_get_rate(gpu->core_clk); > + > + return busy_cycles; > +} > + > static u32 a2xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) > { > ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR); > @@ -502,6 +529,7 @@ static const struct adreno_gpu_funcs funcs = { > #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) > .show = adreno_show, > #endif > + .gpu_busy = a2xx_gpu_busy, > .gpu_state_get = a2xx_gpu_state_get, > .gpu_state_put = adreno_gpu_state_put, > .create_address_space = a2xx_create_address_space, > -- With best wishes Dmitry
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> To: Konrad Dybcio <konrad.dybcio@linaro.org>, Rob Clark <robdclark@gmail.com>, Abhinav Kumar <quic_abhinavk@quicinc.com>, Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch> Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: Re: [PATCH 2/5] drm/msm/a2xx: Implement .gpu_busy Date: Thu, 23 Feb 2023 00:24:02 +0200 [thread overview] Message-ID: <9b535af0-7159-14b3-560f-197c7153b78c@linaro.org> (raw) In-Reply-To: <20230222-konrad-longbois-next-v1-2-01021425781b@linaro.org> On 22/02/2023 23:47, Konrad Dybcio wrote: > Implement gpu_busy based on the downstream msm-3.4 code [1]. This > allows us to use devfreq on this old old old hardware! > > [1] https://github.com/LineageOS/android_kernel_sony_apq8064/blob/lineage-16.0/drivers/gpu/msm/adreno_a2xx.c#L1975 > > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 28 ++++++++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c > index c67089a7ebc1..6258c98e5a88 100644 > --- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c > @@ -481,6 +481,33 @@ a2xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) > return aspace; > } > > +/* While the precise size of this field is unknown, it holds at least these three values.. */ > +#define PERF_MODE_CNT GENMASK(2, 0) > + #define PERF_STATE_RESET 0x0 > + #define PERF_STATE_ENABLE 0x1 > + #define PERF_STATE_FREEZE 0x2 These should go into a2xx.xml.h LGTM otherwise. > +static u64 a2xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) > +{ > + u64 busy_cycles; > + > + /* Freeze the counter */ > + gpu_write(gpu, REG_A2XX_CP_PERFMON_CNTL, FIELD_PREP(PERF_MODE_CNT, PERF_STATE_FREEZE)); > + > + busy_cycles = gpu_read64(gpu, REG_A2XX_RBBM_PERFCOUNTER1_LO); > + > + /* Reset the counter */ > + gpu_write(gpu, REG_A2XX_CP_PERFMON_CNTL, FIELD_PREP(PERF_MODE_CNT, PERF_STATE_RESET)); > + > + /* Re-enable the performance monitors */ > + gpu_rmw(gpu, REG_A2XX_RBBM_PM_OVERRIDE2, BIT(6), BIT(6)); > + gpu_write(gpu, REG_A2XX_RBBM_PERFCOUNTER1_SELECT, 1); > + gpu_write(gpu, REG_A2XX_CP_PERFMON_CNTL, FIELD_PREP(PERF_MODE_CNT, PERF_STATE_ENABLE)); > + > + *out_sample_rate = clk_get_rate(gpu->core_clk); > + > + return busy_cycles; > +} > + > static u32 a2xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) > { > ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR); > @@ -502,6 +529,7 @@ static const struct adreno_gpu_funcs funcs = { > #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) > .show = adreno_show, > #endif > + .gpu_busy = a2xx_gpu_busy, > .gpu_state_get = a2xx_gpu_state_get, > .gpu_state_put = adreno_gpu_state_put, > .create_address_space = a2xx_create_address_space, > -- With best wishes Dmitry
next prev parent reply other threads:[~2023-02-22 22:24 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-02-22 21:47 [PATCH 0/5] OPP and devfreq for all Adrenos Konrad Dybcio 2023-02-22 21:47 ` Konrad Dybcio 2023-02-22 21:47 ` [PATCH 1/5] drm/msm/adreno: Use OPP for every GPU generation Konrad Dybcio 2023-02-22 21:47 ` Konrad Dybcio 2023-02-22 22:38 ` Dmitry Baryshkov 2023-02-22 22:38 ` Dmitry Baryshkov 2023-02-22 22:40 ` Konrad Dybcio 2023-02-22 22:40 ` Konrad Dybcio 2023-02-22 23:16 ` Dmitry Baryshkov 2023-02-22 23:16 ` Dmitry Baryshkov 2023-02-23 1:02 ` Konrad Dybcio 2023-02-23 1:02 ` Konrad Dybcio 2023-02-22 21:47 ` [PATCH 2/5] drm/msm/a2xx: Implement .gpu_busy Konrad Dybcio 2023-02-22 21:47 ` Konrad Dybcio 2023-02-22 22:24 ` Dmitry Baryshkov [this message] 2023-02-22 22:24 ` Dmitry Baryshkov 2023-02-22 21:47 ` [PATCH 3/5] drm/msm/a3xx: " Konrad Dybcio 2023-02-22 21:47 ` Konrad Dybcio 2023-02-22 22:10 ` Dmitry Baryshkov 2023-02-22 22:10 ` Dmitry Baryshkov 2023-02-22 21:47 ` [PATCH 4/5] drm/msm/a4xx: " Konrad Dybcio 2023-02-22 21:47 ` Konrad Dybcio 2023-02-22 22:22 ` Dmitry Baryshkov 2023-02-22 22:22 ` Dmitry Baryshkov 2023-02-22 21:47 ` [PATCH 5/5] drm/msm/a5xx: Enable optional icc voting from OPP tables Konrad Dybcio 2023-02-22 21:47 ` Konrad Dybcio 2023-02-22 22:12 ` Dmitry Baryshkov 2023-02-22 22:12 ` Dmitry Baryshkov 2023-02-22 22:14 ` Konrad Dybcio 2023-02-22 22:14 ` Konrad Dybcio 2023-02-22 22:22 ` Dmitry Baryshkov 2023-02-22 22:22 ` Dmitry Baryshkov
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