* [Qemu-devel] [PATCH v4 00/38] target-microblaze: Add support for Extended Addressing
@ 2018-05-23 22:47 Edgar E. Iglesias
2018-05-23 22:47 ` [Qemu-devel] [PATCH v4 09/38] target-microblaze: Conditionalize setting of PVR11_USE_MMU Edgar E. Iglesias
0 siblings, 1 reply; 4+ messages in thread
From: Edgar E. Iglesias @ 2018-05-23 22:47 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, richard.henderson, frederic.konrad, alistair,
frasse.iglesias, sstabellini, sai.pavan.boddu, edgar.iglesias
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
This series adds support for Extended Addressing to our MicroBlaze
models. It adds both the non-MMU load/store EA and the extended MMU
addressing.
There are several ways to implement this but since there are further
64-bit extensions in the pipe, I've chosen to convert the cpu_SR
special regs to 64-bit. Both non-EA and EA enabled cores run out of
the same build with TARGET_LONG_BITS=64.
Comments?
The following lacks review:
$ grep -L Reviewed v4/patches/*
v4/patches/0000-cover-letter.patch
v4/patches/0009-target-microblaze-Conditionalize-setting-of-PVR11_US.patch
This time I'm only sending out patch #9.
Thanks & Best regards,
Edgar
ChangeLog:
v3 -> v4:
* Add parenthese in PVR_USE_MMU setting
* Tweak comment in compute_ldst_address
v2 -> v3:
* Add patch to consolidate MMU enabled checks
* Remove patch to convert env_btaken to 64bits
* Add patch to plug tcg_const leakage
* Fix TLBLO access patch to avoid leaking tcg consts
v1 -> v2:
* Add patch to simplify address computation using tcg_gen_addi_i32()
* Add patches to cleanup eval_cond_jmp using tcg_gen_movcond_i32()
* Add patch to cleanup microblaze MMU logs
* Correct trap_userspace() usage when adding Extended Addressing
* Correct name for special register sr13 to redr
Edgar E. Iglesias (38):
target-microblaze: dec_load: Use bool instead of unsigned int
target-microblaze: dec_store: Use bool instead of unsigned int
target-microblaze: compute_ldst_addr: Use bool instead of int
target-microblaze: Fallback to our latest CPU version
target-microblaze: Correct special register array sizes
target-microblaze: Correct the PVR array size
target-microblaze: Tighten up TCGv_i32 vs TCGv type usage
target-microblaze: Remove USE_MMU PVR checks
target-microblaze: Conditionalize setting of PVR11_USE_MMU
target-microblaze: Bypass MMU with MMU_NOMMU_IDX
target-microblaze: Make compute_ldst_addr always use a temp
target-microblaze: Remove pointer indirection for ld/st addresses
target-microblaze: Use TCGv for load/store addresses
target-microblaze: Name special registers we support
target-microblaze: Break out trap_userspace()
target-microblaze: Break out trap_illegal()
target-microblaze: dec_msr: Use bool and extract32
target-microblaze: dec_msr: Reuse more code when reg-decoding
target-microblaze: dec_msr: Fix MTS to FSR
target-microblaze: Make special registers 64-bit
target-microblaze: Setup for 64bit addressing
target-microblaze: Add Extended Addressing
target-microblaze: Implement MFSE EAR
target-microblaze: mmu: Add R_TBLX_MISS macros
target-microblaze: mmu: Remove unused register state
target-microblaze: mmu: Prepare for 64-bit addresses
target-microblaze: mmu: Add a configurable output address mask
target-microblaze: dec_msr: Plug a temp leak
target-microblaze: Add support for extended access to TLBLO
target-microblaze: Allow address sizes between 32 and 64 bits
target-microblaze: Simplify address computation using
tcg_gen_addi_i32()
target-microblaze: mmu: Cleanup debug log messages
target-microblaze: Use table based condition-codes conversion
target-microblaze: Remove argument b in eval_cc()
target-microblaze: Convert env_btarget to i64
target-microblaze: Use tcg_gen_movcond in eval_cond_jmp
target-microblaze: cpu_mmu_index: Fixup indentation
target-microblaze: Consolidate MMU enabled checks
configure | 1 +
linux-user/microblaze/cpu_loop.c | 4 +-
target/microblaze/cpu.c | 30 +-
target/microblaze/cpu.h | 34 +-
target/microblaze/helper.c | 32 +-
target/microblaze/helper.h | 8 +-
target/microblaze/mmu.c | 81 ++--
target/microblaze/mmu.h | 17 +-
target/microblaze/op_helper.c | 30 +-
target/microblaze/translate.c | 930 +++++++++++++++++++--------------------
10 files changed, 598 insertions(+), 569 deletions(-)
--
2.14.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [Qemu-devel] [PATCH v4 09/38] target-microblaze: Conditionalize setting of PVR11_USE_MMU
2018-05-23 22:47 [Qemu-devel] [PATCH v4 00/38] target-microblaze: Add support for Extended Addressing Edgar E. Iglesias
@ 2018-05-23 22:47 ` Edgar E. Iglesias
2018-05-23 22:56 ` Alistair Francis
2018-05-25 14:10 ` Richard Henderson
0 siblings, 2 replies; 4+ messages in thread
From: Edgar E. Iglesias @ 2018-05-23 22:47 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, richard.henderson, frederic.konrad, alistair,
frasse.iglesias, sstabellini, sai.pavan.boddu, edgar.iglesias
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Conditionalize setting of PVR11_USE_MMU on the use_mmu
CPU property, otherwise we may incorrectly advertise an
MMU via PVR when the core in fact has none.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target/microblaze/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 06476f6efc..a6f1ce6549 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -201,7 +201,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
PVR5_DCACHE_WRITEBACK_MASK : 0;
env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
- env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
+ env->pvr.regs[11] = (cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) |
+ 16 << 17;
mcc->parent_realize(dev, errp);
}
--
2.14.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [PATCH v4 09/38] target-microblaze: Conditionalize setting of PVR11_USE_MMU
2018-05-23 22:47 ` [Qemu-devel] [PATCH v4 09/38] target-microblaze: Conditionalize setting of PVR11_USE_MMU Edgar E. Iglesias
@ 2018-05-23 22:56 ` Alistair Francis
2018-05-25 14:10 ` Richard Henderson
1 sibling, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2018-05-23 22:56 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: qemu-devel@nongnu.org Developers, Edgar Iglesias, Peter Maydell,
Stefano Stabellini, Sai Pavan Boddu, Francisco Iglesias,
Alistair Francis, Richard Henderson, KONRAD Frederic
On Wed, May 23, 2018 at 3:47 PM, Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Conditionalize setting of PVR11_USE_MMU on the use_mmu
> CPU property, otherwise we may incorrectly advertise an
> MMU via PVR when the core in fact has none.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/microblaze/cpu.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 06476f6efc..a6f1ce6549 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -201,7 +201,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
> PVR5_DCACHE_WRITEBACK_MASK : 0;
>
> env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
> - env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
> + env->pvr.regs[11] = (cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) |
> + 16 << 17;
>
> mcc->parent_realize(dev, errp);
> }
> --
> 2.14.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [PATCH v4 09/38] target-microblaze: Conditionalize setting of PVR11_USE_MMU
2018-05-23 22:47 ` [Qemu-devel] [PATCH v4 09/38] target-microblaze: Conditionalize setting of PVR11_USE_MMU Edgar E. Iglesias
2018-05-23 22:56 ` Alistair Francis
@ 2018-05-25 14:10 ` Richard Henderson
1 sibling, 0 replies; 4+ messages in thread
From: Richard Henderson @ 2018-05-25 14:10 UTC (permalink / raw)
To: Edgar E. Iglesias, qemu-devel
Cc: peter.maydell, frederic.konrad, alistair, frasse.iglesias,
sstabellini, sai.pavan.boddu, edgar.iglesias
On 05/23/2018 03:47 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Conditionalize setting of PVR11_USE_MMU on the use_mmu
> CPU property, otherwise we may incorrectly advertise an
> MMU via PVR when the core in fact has none.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> target/microblaze/cpu.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-05-25 14:10 UTC | newest]
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2018-05-23 22:47 [Qemu-devel] [PATCH v4 00/38] target-microblaze: Add support for Extended Addressing Edgar E. Iglesias
2018-05-23 22:47 ` [Qemu-devel] [PATCH v4 09/38] target-microblaze: Conditionalize setting of PVR11_USE_MMU Edgar E. Iglesias
2018-05-23 22:56 ` Alistair Francis
2018-05-25 14:10 ` Richard Henderson
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