From: "Liu, Yi L" <yi.l.liu-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> To: Peter Xu <peterx-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>, "Liu, Yi L" <yi.l.liu-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> Cc: "Lan, Tianyu" <tianyu.lan-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>, "Tian, Kevin" <kevin.tian-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>, "kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" <kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>, "jasowang-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org" <jasowang-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>, "iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org" <iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>, "qemu-devel-qX2TKyscuCcdnm+yROfE0A@public.gmane.org" <qemu-devel-qX2TKyscuCcdnm+yROfE0A@public.gmane.org>, "Pan, Jacob jun" <jacob.jun.pan-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> Subject: RE: [RFC PATCH 03/20] intel_iommu: add "svm" option Date: Mon, 8 May 2017 10:38:09 +0000 [thread overview] Message-ID: <A2975661238FB949B60364EF0F2C25743906890D@shsmsx102.ccr.corp.intel.com> (raw) In-Reply-To: <20170427105317.GE1542-QJIicYCqamqhazCxEpVPD9i2O/JbrIOy@public.gmane.org> On Thu, 27 Apr 2017 18:53:17 +0800 Peter Xu <peterx@redhat.com> wrote: > On Wed, Apr 26, 2017 at 06:06:33PM +0800, Liu, Yi L wrote: > > Expose "Shared Virtual Memory" to guest by using "svm" option. > > Also use "svm" to expose SVM related capabilities to guest. > > e.g. "-device intel-iommu, svm=on" > > > > Signed-off-by: Liu, Yi L <yi.l.liu@linux.intel.com> > > --- > > hw/i386/intel_iommu.c | 10 ++++++++++ > > hw/i386/intel_iommu_internal.h | 5 +++++ > > include/hw/i386/intel_iommu.h | 1 + > > 3 files changed, 16 insertions(+) > > > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index > > bf98fa5..ba1e7eb 100644 > > --- a/hw/i386/intel_iommu.c > > +++ b/hw/i386/intel_iommu.c > > @@ -2453,6 +2453,7 @@ static Property vtd_properties[] = { > > DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState, buggy_eim, false), > > DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, > FALSE), > > DEFINE_PROP_BOOL("ecs", IntelIOMMUState, ecs, FALSE), > > + DEFINE_PROP_BOOL("svm", IntelIOMMUState, svm, FALSE), > > DEFINE_PROP_END_OF_LIST(), > > }; > > > > @@ -2973,6 +2974,15 @@ static void vtd_init(IntelIOMMUState *s) > > s->ecap |= VTD_ECAP_ECS; > > } > > > > + if (s->svm) { > > + if (!s->ecs || !x86_iommu->pt_supported || !s->caching_mode) { > > + error_report("Need to set ecs, pt, caching-mode for svm"); > > + exit(1); > > + } > > + s->cap |= VTD_CAP_DWD | VTD_CAP_DRD; > > + s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PTS | VTD_ECAP_PASID28; > > + } > > + > > if (s->caching_mode) { > > s->cap |= VTD_CAP_CM; > > } > > diff --git a/hw/i386/intel_iommu_internal.h > > b/hw/i386/intel_iommu_internal.h index 71a1c1e..f2a7d12 100644 > > --- a/hw/i386/intel_iommu_internal.h > > +++ b/hw/i386/intel_iommu_internal.h > > @@ -191,6 +191,9 @@ > > #define VTD_ECAP_PT (1ULL << 6) > > #define VTD_ECAP_MHMV (15ULL << 20) > > #define VTD_ECAP_ECS (1ULL << 24) > > +#define VTD_ECAP_PASID28 (1ULL << 28) > > Could I ask what's this bit? On my spec, it says this bit is reserved and defunct (spec > version: June 2016). As Ashok confirmed, yes it should be bit 40. would update it. > > +#define VTD_ECAP_PRS (1ULL << 29) > > +#define VTD_ECAP_PTS (0xeULL << 35) > > Would it better we avoid using 0xe here, or at least add some comment? For this value, it must be no more than the bits host supports. So it may be better to have a default value and meanwhile expose an option to let user set it. how about your opinion? > > > > > /* CAP_REG */ > > /* (offset >> 4) << 24 */ > > @@ -207,6 +210,8 @@ > > #define VTD_CAP_PSI (1ULL << 39) > > #define VTD_CAP_SLLPS ((1ULL << 34) | (1ULL << 35)) > > #define VTD_CAP_CM (1ULL << 7) > > +#define VTD_CAP_DWD (1ULL << 54) > > +#define VTD_CAP_DRD (1ULL << 55) > > Just to confirm: after this series, we should support drain read/write then, right? I haven’t done special process against it in IOMMU emulator. It's set to keep consistence with VT-d spec since DWD and DRW is required capability when PASID it reported as Set. However, I think it should be fine if guest issue QI with drain read/write set in the descriptor. Host should be able to process it. Thanks, Yi L > > > > /* Supported Adjusted Guest Address Widths */ > > #define VTD_CAP_SAGAW_SHIFT 8 > > diff --git a/include/hw/i386/intel_iommu.h > > b/include/hw/i386/intel_iommu.h index ae21fe5..8981615 100644 > > --- a/include/hw/i386/intel_iommu.h > > +++ b/include/hw/i386/intel_iommu.h > > @@ -267,6 +267,7 @@ struct IntelIOMMUState { > > > > bool caching_mode; /* RO - is cap CM enabled? */ > > bool ecs; /* Extended Context Support */ > > + bool svm; /* Shared Virtual Memory */ > > > > dma_addr_t root; /* Current root table pointer */ > > bool root_extended; /* Type of root table (extended or not) */ > > -- > > 1.9.1 > > > > -- > Peter Xu _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
WARNING: multiple messages have this Message-ID (diff)
From: "Liu, Yi L" <yi.l.liu@intel.com> To: Peter Xu <peterx@redhat.com>, "Liu, Yi L" <yi.l.liu@linux.intel.com> Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>, "alex.williamson@redhat.com" <alex.williamson@redhat.com>, "kvm@vger.kernel.org" <kvm@vger.kernel.org>, "jasowang@redhat.com" <jasowang@redhat.com>, "iommu@lists.linux-foundation.org" <iommu@lists.linux-foundation.org>, "Tian, Kevin" <kevin.tian@intel.com>, "Raj, Ashok" <ashok.raj@intel.com>, "Pan, Jacob jun" <jacob.jun.pan@intel.com>, "Lan, Tianyu" <tianyu.lan@intel.com>, "jean-philippe.brucker@arm.com" <jean-philippe.brucker@arm.com> Subject: Re: [Qemu-devel] [RFC PATCH 03/20] intel_iommu: add "svm" option Date: Mon, 8 May 2017 10:38:09 +0000 [thread overview] Message-ID: <A2975661238FB949B60364EF0F2C25743906890D@shsmsx102.ccr.corp.intel.com> (raw) In-Reply-To: <20170427105317.GE1542@pxdev.xzpeter.org> On Thu, 27 Apr 2017 18:53:17 +0800 Peter Xu <peterx@redhat.com> wrote: > On Wed, Apr 26, 2017 at 06:06:33PM +0800, Liu, Yi L wrote: > > Expose "Shared Virtual Memory" to guest by using "svm" option. > > Also use "svm" to expose SVM related capabilities to guest. > > e.g. "-device intel-iommu, svm=on" > > > > Signed-off-by: Liu, Yi L <yi.l.liu@linux.intel.com> > > --- > > hw/i386/intel_iommu.c | 10 ++++++++++ > > hw/i386/intel_iommu_internal.h | 5 +++++ > > include/hw/i386/intel_iommu.h | 1 + > > 3 files changed, 16 insertions(+) > > > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index > > bf98fa5..ba1e7eb 100644 > > --- a/hw/i386/intel_iommu.c > > +++ b/hw/i386/intel_iommu.c > > @@ -2453,6 +2453,7 @@ static Property vtd_properties[] = { > > DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState, buggy_eim, false), > > DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, > FALSE), > > DEFINE_PROP_BOOL("ecs", IntelIOMMUState, ecs, FALSE), > > + DEFINE_PROP_BOOL("svm", IntelIOMMUState, svm, FALSE), > > DEFINE_PROP_END_OF_LIST(), > > }; > > > > @@ -2973,6 +2974,15 @@ static void vtd_init(IntelIOMMUState *s) > > s->ecap |= VTD_ECAP_ECS; > > } > > > > + if (s->svm) { > > + if (!s->ecs || !x86_iommu->pt_supported || !s->caching_mode) { > > + error_report("Need to set ecs, pt, caching-mode for svm"); > > + exit(1); > > + } > > + s->cap |= VTD_CAP_DWD | VTD_CAP_DRD; > > + s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PTS | VTD_ECAP_PASID28; > > + } > > + > > if (s->caching_mode) { > > s->cap |= VTD_CAP_CM; > > } > > diff --git a/hw/i386/intel_iommu_internal.h > > b/hw/i386/intel_iommu_internal.h index 71a1c1e..f2a7d12 100644 > > --- a/hw/i386/intel_iommu_internal.h > > +++ b/hw/i386/intel_iommu_internal.h > > @@ -191,6 +191,9 @@ > > #define VTD_ECAP_PT (1ULL << 6) > > #define VTD_ECAP_MHMV (15ULL << 20) > > #define VTD_ECAP_ECS (1ULL << 24) > > +#define VTD_ECAP_PASID28 (1ULL << 28) > > Could I ask what's this bit? On my spec, it says this bit is reserved and defunct (spec > version: June 2016). As Ashok confirmed, yes it should be bit 40. would update it. > > +#define VTD_ECAP_PRS (1ULL << 29) > > +#define VTD_ECAP_PTS (0xeULL << 35) > > Would it better we avoid using 0xe here, or at least add some comment? For this value, it must be no more than the bits host supports. So it may be better to have a default value and meanwhile expose an option to let user set it. how about your opinion? > > > > > /* CAP_REG */ > > /* (offset >> 4) << 24 */ > > @@ -207,6 +210,8 @@ > > #define VTD_CAP_PSI (1ULL << 39) > > #define VTD_CAP_SLLPS ((1ULL << 34) | (1ULL << 35)) > > #define VTD_CAP_CM (1ULL << 7) > > +#define VTD_CAP_DWD (1ULL << 54) > > +#define VTD_CAP_DRD (1ULL << 55) > > Just to confirm: after this series, we should support drain read/write then, right? I haven’t done special process against it in IOMMU emulator. It's set to keep consistence with VT-d spec since DWD and DRW is required capability when PASID it reported as Set. However, I think it should be fine if guest issue QI with drain read/write set in the descriptor. Host should be able to process it. Thanks, Yi L > > > > /* Supported Adjusted Guest Address Widths */ > > #define VTD_CAP_SAGAW_SHIFT 8 > > diff --git a/include/hw/i386/intel_iommu.h > > b/include/hw/i386/intel_iommu.h index ae21fe5..8981615 100644 > > --- a/include/hw/i386/intel_iommu.h > > +++ b/include/hw/i386/intel_iommu.h > > @@ -267,6 +267,7 @@ struct IntelIOMMUState { > > > > bool caching_mode; /* RO - is cap CM enabled? */ > > bool ecs; /* Extended Context Support */ > > + bool svm; /* Shared Virtual Memory */ > > > > dma_addr_t root; /* Current root table pointer */ > > bool root_extended; /* Type of root table (extended or not) */ > > -- > > 1.9.1 > > > > -- > Peter Xu
next prev parent reply other threads:[~2017-05-08 10:38 UTC|newest] Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-04-26 10:06 [RFC PATCH 00/20] Qemu: Extend intel_iommu emulator to support Shared Virtual Memory Liu, Yi L 2017-04-26 10:06 ` [Qemu-devel] " Liu, Yi L 2017-04-26 10:06 ` [RFC PATCH 01/20] intel_iommu: add "ecs" option Liu, Yi L 2017-04-26 10:06 ` [Qemu-devel] " Liu, Yi L 2017-04-26 10:06 ` [RFC PATCH 02/20] intel_iommu: exposed extended-context mode to guest Liu, Yi L 2017-04-26 10:06 ` [Qemu-devel] " Liu, Yi L [not found] ` <1493201210-14357-3-git-send-email-yi.l.liu-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> 2017-04-27 10:32 ` Peter Xu 2017-04-27 10:32 ` [Qemu-devel] " Peter Xu 2017-04-28 6:00 ` Lan Tianyu 2017-04-28 6:00 ` [Qemu-devel] " Lan Tianyu [not found] ` <a7cd779f-2cd6-3a3f-7e73-e79a49c48961-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> 2017-04-28 9:56 ` Liu, Yi L 2017-04-28 9:56 ` [Qemu-devel] " Liu, Yi L [not found] ` <20170427103221.GD1542-QJIicYCqamqhazCxEpVPD9i2O/JbrIOy@public.gmane.org> 2017-04-28 9:55 ` Liu, Yi L 2017-04-28 9:55 ` Liu, Yi L 2017-04-26 10:06 ` [RFC PATCH 03/20] intel_iommu: add "svm" option Liu, Yi L 2017-04-26 10:06 ` [Qemu-devel] " Liu, Yi L [not found] ` <1493201210-14357-4-git-send-email-yi.l.liu-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> 2017-04-27 10:53 ` Peter Xu 2017-04-27 10:53 ` [Qemu-devel] " Peter Xu [not found] ` <20170427105317.GE1542-QJIicYCqamqhazCxEpVPD9i2O/JbrIOy@public.gmane.org> 2017-05-04 20:28 ` Alex Williamson 2017-05-04 20:28 ` [Qemu-devel] " Alex Williamson [not found] ` <20170504142853.1537028c-1yVPhWWZRC1BDLzU/O5InQ@public.gmane.org> 2017-05-04 20:37 ` Raj, Ashok 2017-05-04 20:37 ` [Qemu-devel] " Raj, Ashok 2017-05-08 10:38 ` Liu, Yi L [this message] 2017-05-08 10:38 ` Liu, Yi L [not found] ` <A2975661238FB949B60364EF0F2C25743906890D-E2R4CRU6q/6iAffOGbnezLfspsVTdybXVpNB7YpNyf8@public.gmane.org> 2017-05-08 11:20 ` Peter Xu 2017-05-08 11:20 ` [Qemu-devel] " Peter Xu [not found] ` <20170508112034.GE2820-QJIicYCqamqhazCxEpVPD9i2O/JbrIOy@public.gmane.org> 2017-05-08 8:15 ` Liu, Yi L 2017-05-08 8:15 ` Liu, Yi L 2017-04-26 10:06 ` [RFC PATCH 04/20] Memory: modify parameter in IOMMUNotifier func Liu, Yi L 2017-04-26 10:06 ` [Qemu-devel] " Liu, Yi L 2017-04-26 10:06 ` [RFC PATCH 05/20] VFIO: add new IOCTL for svm bind tasks Liu, Yi L 2017-04-26 10:06 ` [Qemu-devel] " Liu, Yi L 2017-04-26 10:06 ` [RFC PATCH 06/20] VFIO: add new notifier for binding PASID table Liu, Yi L 2017-04-26 10:06 ` [Qemu-devel] " Liu, Yi L 2017-04-26 10:06 ` [RFC PATCH 07/20] VFIO: check notifier flag in region_del() Liu, Yi L 2017-04-26 10:06 ` [Qemu-devel] " Liu, Yi L 2017-04-26 10:06 ` [RFC PATCH 08/20] Memory: add notifier flag check in memory_replay() Liu, Yi L 2017-04-26 10:06 ` [Qemu-devel] " Liu, Yi L 2017-04-26 10:06 ` [RFC PATCH 09/20] Memory: introduce iommu_ops->record_device Liu, Yi L 2017-04-26 10:06 ` [Qemu-devel] " Liu, Yi L [not found] ` <1493201210-14357-10-git-send-email-yi.l.liu-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> 2017-04-28 6:46 ` Lan Tianyu 2017-04-28 6:46 ` [Qemu-devel] " Lan Tianyu 2017-05-19 5:23 ` Liu, Yi L 2017-05-19 5:23 ` Liu, Yi L 2017-05-19 5:23 ` Liu, Yi L 2017-05-19 9:07 ` Tian, Kevin 2017-05-19 9:07 ` Tian, Kevin 2017-05-19 9:35 ` Liu, Yi L 2017-04-26 10:06 ` [RFC PATCH 10/20] VFIO: notify vIOMMU emulator when device is assigned Liu, Yi L 2017-04-26 10:06 ` [Qemu-devel] " Liu, Yi L 2017-04-26 10:06 ` [RFC PATCH 11/20] intel_iommu: provide iommu_ops->record_device Liu, Yi L 2017-04-26 10:06 ` [Qemu-devel] " Liu, Yi L 2017-04-26 10:06 ` [RFC PATCH 12/20] Memory: Add func to fire pasidt_bind notifier Liu, Yi L 2017-04-26 10:06 ` [Qemu-devel] " Liu, Yi L [not found] ` <1493201210-14357-13-git-send-email-yi.l.liu-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> 2017-04-26 13:50 ` Paolo Bonzini 2017-04-26 13:50 ` [Qemu-devel] " Paolo Bonzini 2017-04-27 2:37 ` Liu, Yi L 2017-04-27 6:14 ` Peter Xu 2017-04-27 6:14 ` Peter Xu 2017-04-27 10:09 ` Peter Xu [not found] ` <20170427061427.GA1542-QJIicYCqamqhazCxEpVPD9i2O/JbrIOy@public.gmane.org> 2017-04-27 10:25 ` Liu, Yi L 2017-04-27 10:25 ` Liu, Yi L 2017-04-27 10:51 ` Peter Xu 2017-04-26 10:06 ` [RFC PATCH 13/20] IOMMU: add pasid_table_info for guest pasid table Liu, Yi L 2017-04-26 10:06 ` [Qemu-devel] " Liu, Yi L 2017-04-26 10:06 ` [RFC PATCH 14/20] intel_iommu: add FOR_EACH_ASSIGN_DEVICE macro Liu, Yi L 2017-04-26 10:06 ` [Qemu-devel] " Liu, Yi L [not found] ` <1493201210-14357-15-git-send-email-yi.l.liu-VuQAYsv1563Yd54FQh9/CA@public.gmane.org> 2017-04-28 7:33 ` Lan Tianyu 2017-04-28 7:33 ` [Qemu-devel] " Lan Tianyu 2017-04-26 10:06 ` [RFC PATCH 15/20] intel_iommu: link whole guest pasid table to host Liu, Yi L 2017-04-26 10:06 ` [Qemu-devel] " Liu, Yi L 2017-04-26 10:06 ` [RFC PATCH 16/20] VFIO: Add notifier for propagating IOMMU TLB invalidate Liu, Yi L 2017-04-26 10:06 ` [Qemu-devel] " Liu, Yi L 2017-04-26 10:06 ` [RFC PATCH 17/20] Memory: Add func to fire TLB invalidate notifier Liu, Yi L 2017-04-26 10:06 ` [Qemu-devel] " Liu, Yi L 2017-04-26 10:06 ` [RFC PATCH 18/20] intel_iommu: propagate Extended-IOTLB invalidate to host Liu, Yi L 2017-04-26 10:06 ` [Qemu-devel] " Liu, Yi L 2017-04-26 10:06 ` [RFC PATCH 19/20] intel_iommu: propagate PASID-Cache " Liu, Yi L 2017-04-26 10:06 ` [Qemu-devel] " Liu, Yi L 2017-04-26 10:06 ` [RFC PATCH 20/20] intel_iommu: propagate Ext-Device-TLB " Liu, Yi L 2017-04-26 10:06 ` [Qemu-devel] " Liu, Yi L
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=A2975661238FB949B60364EF0F2C25743906890D@shsmsx102.ccr.corp.intel.com \ --to=yi.l.liu-ral2jqcrhueavxtiumwx3w@public.gmane.org \ --cc=iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org \ --cc=jacob.jun.pan-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org \ --cc=jasowang-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org \ --cc=kevin.tian-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org \ --cc=kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \ --cc=peterx-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org \ --cc=qemu-devel-qX2TKyscuCcdnm+yROfE0A@public.gmane.org \ --cc=tianyu.lan-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org \ --cc=yi.l.liu-VuQAYsv1563Yd54FQh9/CA@public.gmane.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.