Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Jeff Chua]

On Sun, Feb 6, 2011 at 2:24 AM, Rafael J. Wysocki <rjw@sisk.pl> wrote:
>> The suspend monster is back! The suspend-to-ram is fine, but upon
>> resume, screen is blank. Haven't bisected in case someone has also
>> done so.
>
> BTW, please don't reply to messages containing patches with reports of problems
> that aren't caused by those patches.  It's confusing at best and at worst it
> may result in the patches being rejected.

Sorry. New subject now:)


On Sun, Feb 6, 2011 at 2:51 AM, Linus Torvalds
<torvalds@linux-foundation.org> wrote:
>> It's very recent. ... between commit
>> 831d52bc153971b70e64eccfbed2b232394f22f8 and
>> 44f2c5c841da1b1e0864d768197ab1497b5c2cc1.
>
> Hmm. It's almost certainly one of the DRI patches, but which one? I
> think bisection is the only way to figure it out. It shouldn't be too
> bad, since there's only 120 commits in that range.
>
> In fact, you can almost certainly just bisect from 89840966c579 to
> bb5b583b5279, which is just 31 commits and should get you bisected in
> just five tries or so.

Yea, I've just done that. It came down to the following commit.
Reverting it solves the problem. I've gone thru a few cycles, and
notebook still survives.

Thanks,
Jeff


commit 500f7147cf5bafd139056d521536b10c2bc2e154
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Mon Jan 24 15:14:41 2011 +0000

    drm/i915: Reset state after a GPU reset or resume

    Call drm_mode_config_reset() after an invalidation event to restore any
    cached state to unknown.

    Tested-by: Takashi Iwai <tiwai@suse.de>
    Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Marc Koschewski]

Hi,

* Jeff Chua <jeff.chua.linux@gmail.com> [2011-02-06 09:50:51 +0800]:
> On Sun, Feb 6, 2011 at 2:24 AM, Rafael J. Wysocki <rjw@sisk.pl> wrote:
> >> The suspend monster is back! The suspend-to-ram is fine, but upon
> >> resume, screen is blank. Haven't bisected in case someone has also
> >> done so.
> >
> > BTW, please don't reply to messages containing patches with reports of problems
> > that aren't caused by those patches.  It's confusing at best and at worst it
> > may result in the patches being rejected.
> 
> Sorry. New subject now:)
> 
> 
> On Sun, Feb 6, 2011 at 2:51 AM, Linus Torvalds
> <torvalds@linux-foundation.org> wrote:
> >> It's very recent. ... between commit
> >> 831d52bc153971b70e64eccfbed2b232394f22f8 and
> >> 44f2c5c841da1b1e0864d768197ab1497b5c2cc1.
> >
> > Hmm. It's almost certainly one of the DRI patches, but which one? I
> > think bisection is the only way to figure it out. It shouldn't be too
> > bad, since there's only 120 commits in that range.
> >
> > In fact, you can almost certainly just bisect from 89840966c579 to
> > bb5b583b5279, which is just 31 commits and should get you bisected in
> > just five tries or so.
> 
> Yea, I've just done that. It came down to the following commit.
> Reverting it solves the problem. I've gone thru a few cycles, and
> notebook still survives.
> 
> Thanks,
> Jeff

I reverted the specified commit and my box still suffers the
resume-turns-into-cold-boot behavior. Retried two times with the commit reverted
on top of HEAD...

Regards,
Marc

> 
> 
> commit 500f7147cf5bafd139056d521536b10c2bc2e154
> Author: Chris Wilson <chris@chris-wilson.co.uk>
> Date:   Mon Jan 24 15:14:41 2011 +0000
> 
>     drm/i915: Reset state after a GPU reset or resume
> 
>     Call drm_mode_config_reset() after an invalidation event to restore any
>     cached state to unknown.
> 
>     Tested-by: Takashi Iwai <tiwai@suse.de>
>     Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/
> 
> 

-- 
Marc Koschewski

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Takashi Iwai]

At Sun, 6 Feb 2011 09:50:51 +0800,
Jeff Chua wrote:
> 
> On Sun, Feb 6, 2011 at 2:24 AM, Rafael J. Wysocki <rjw@sisk.pl> wrote:
> >> The suspend monster is back! The suspend-to-ram is fine, but upon
> >> resume, screen is blank. Haven't bisected in case someone has also
> >> done so.
> >
> > BTW, please don't reply to messages containing patches with reports of problems
> > that aren't caused by those patches.  It's confusing at best and at worst it
> > may result in the patches being rejected.
> 
> Sorry. New subject now:)
> 
> 
> On Sun, Feb 6, 2011 at 2:51 AM, Linus Torvalds
> <torvalds@linux-foundation.org> wrote:
> >> It's very recent. ... between commit
> >> 831d52bc153971b70e64eccfbed2b232394f22f8 and
> >> 44f2c5c841da1b1e0864d768197ab1497b5c2cc1.
> >
> > Hmm. It's almost certainly one of the DRI patches, but which one? I
> > think bisection is the only way to figure it out. It shouldn't be too
> > bad, since there's only 120 commits in that range.
> >
> > In fact, you can almost certainly just bisect from 89840966c579 to
> > bb5b583b5279, which is just 31 commits and should get you bisected in
> > just five tries or so.
> 
> Yea, I've just done that. It came down to the following commit.
> Reverting it solves the problem. I've gone thru a few cycles, and
> notebook still survives.

Hrm, what is the symptom?  I couldn't find it because you cut off the
thread, and it's not cited.

The commit you mentioned just adds an interface, and the the callbacks
aren't defined.  The real change is either in
  commit f3269058e7a80083dcdf89698bfcd1a6c6f8fd12
    drm/i915/crt: Force the initial probe after reset
or
  commit 5d1d0cc87fc0887921993ea0742932e0c8adeda0
    drm/i915: Reset crtc after resume

Also the fix might interact with
  commit 811aaa55ba21ab37407018cfc01770d6b037d3fb
    drm: Only set DPMS ON when actually configuring a mode


thanks,

Takashi

> 
> Thanks,
> Jeff
> 
> 
> commit 500f7147cf5bafd139056d521536b10c2bc2e154
> Author: Chris Wilson <chris@chris-wilson.co.uk>
> Date:   Mon Jan 24 15:14:41 2011 +0000
> 
>     drm/i915: Reset state after a GPU reset or resume
> 
>     Call drm_mode_config_reset() after an invalidation event to restore any
>     cached state to unknown.
> 
>     Tested-by: Takashi Iwai <tiwai@suse.de>
>     Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> 

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Takashi Iwai]

At Sun, 6 Feb 2011 09:19:51 +0100,
Marc Koschewski wrote:
> 
> Hi,
> 
> * Jeff Chua <jeff.chua.linux@gmail.com> [2011-02-06 09:50:51 +0800]:
> > On Sun, Feb 6, 2011 at 2:24 AM, Rafael J. Wysocki <rjw@sisk.pl> wrote:
> > >> The suspend monster is back! The suspend-to-ram is fine, but upon
> > >> resume, screen is blank. Haven't bisected in case someone has also
> > >> done so.
> > >
> > > BTW, please don't reply to messages containing patches with reports of problems
> > > that aren't caused by those patches.  It's confusing at best and at worst it
> > > may result in the patches being rejected.
> > 
> > Sorry. New subject now:)
> > 
> > 
> > On Sun, Feb 6, 2011 at 2:51 AM, Linus Torvalds
> > <torvalds@linux-foundation.org> wrote:
> > >> It's very recent. ... between commit
> > >> 831d52bc153971b70e64eccfbed2b232394f22f8 and
> > >> 44f2c5c841da1b1e0864d768197ab1497b5c2cc1.
> > >
> > > Hmm. It's almost certainly one of the DRI patches, but which one? I
> > > think bisection is the only way to figure it out. It shouldn't be too
> > > bad, since there's only 120 commits in that range.
> > >
> > > In fact, you can almost certainly just bisect from 89840966c579 to
> > > bb5b583b5279, which is just 31 commits and should get you bisected in
> > > just five tries or so.
> > 
> > Yea, I've just done that. It came down to the following commit.
> > Reverting it solves the problem. I've gone thru a few cycles, and
> > notebook still survives.
> > 
> > Thanks,
> > Jeff
> 
> I reverted the specified commit and my box still suffers the
> resume-turns-into-cold-boot behavior. Retried two times with the commit reverted
> on top of HEAD...

The cold-boot problem is very likely irrelevant with i915 patches.
I've got the same issue with and without the i915 fix patches on test
machines here.


thanks,

Takashi

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Dave Airlie]

>>
>> I reverted the specified commit and my box still suffers the
>> resume-turns-into-cold-boot behavior. Retried two times with the commit reverted
>> on top of HEAD...
>
> The cold-boot problem is very likely irrelevant with i915 patches.
> I've got the same issue with and without the i915 fix patches on test
> machines here.
>
Yeah its the 32-bit NX stuff most likely if you are using 32-bit kernels.

Dave.

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Marc Koschewski]

I've the NX stuff disabled, so to say DEBUG_RODATA=n and it doesn't resume... so
what's next?

I use an i7 with 32bit code as I think 64bit is a) useless for me and b) I just
plugged my old HDD into my new machine.

Marc

* Dave Airlie <airlied@gmail.com> [2011-02-06 21:06:18 +1000]:

> >>
> >> I reverted the specified commit and my box still suffers the
> >> resume-turns-into-cold-boot behavior. Retried two times with the commit reverted
> >> on top of HEAD...
> >
> > The cold-boot problem is very likely irrelevant with i915 patches.
> > I've got the same issue with and without the i915 fix patches on test
> > machines here.
> >
> Yeah its the 32-bit NX stuff most likely if you are using 32-bit kernels.
> 
> Dave.
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/
> 
> 

-- 
Marc Koschewski

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Marc Koschewski]

Read this

	[REGRESSION g01539ba] Hibernate broken on T510i

or this

	[REGRESSION] S3 resume on SandyBridge doesn't work with NX protection (5bd5a45)

Marc

* Takashi Iwai <tiwai@suse.de> [2011-02-06 12:00:15 +0100]:

> At Sun, 6 Feb 2011 09:50:51 +0800,
> Jeff Chua wrote:
> > 
> > On Sun, Feb 6, 2011 at 2:24 AM, Rafael J. Wysocki <rjw@sisk.pl> wrote:
> > >> The suspend monster is back! The suspend-to-ram is fine, but upon
> > >> resume, screen is blank. Haven't bisected in case someone has also
> > >> done so.
> > >
> > > BTW, please don't reply to messages containing patches with reports of problems
> > > that aren't caused by those patches.  It's confusing at best and at worst it
> > > may result in the patches being rejected.
> > 
> > Sorry. New subject now:)
> > 
> > 
> > On Sun, Feb 6, 2011 at 2:51 AM, Linus Torvalds
> > <torvalds@linux-foundation.org> wrote:
> > >> It's very recent. ... between commit
> > >> 831d52bc153971b70e64eccfbed2b232394f22f8 and
> > >> 44f2c5c841da1b1e0864d768197ab1497b5c2cc1.
> > >
> > > Hmm. It's almost certainly one of the DRI patches, but which one? I
> > > think bisection is the only way to figure it out. It shouldn't be too
> > > bad, since there's only 120 commits in that range.
> > >
> > > In fact, you can almost certainly just bisect from 89840966c579 to
> > > bb5b583b5279, which is just 31 commits and should get you bisected in
> > > just five tries or so.
> > 
> > Yea, I've just done that. It came down to the following commit.
> > Reverting it solves the problem. I've gone thru a few cycles, and
> > notebook still survives.
> 
> Hrm, what is the symptom?  I couldn't find it because you cut off the
> thread, and it's not cited.
> 
> The commit you mentioned just adds an interface, and the the callbacks
> aren't defined.  The real change is either in
>   commit f3269058e7a80083dcdf89698bfcd1a6c6f8fd12
>     drm/i915/crt: Force the initial probe after reset
> or
>   commit 5d1d0cc87fc0887921993ea0742932e0c8adeda0
>     drm/i915: Reset crtc after resume
> 
> Also the fix might interact with
>   commit 811aaa55ba21ab37407018cfc01770d6b037d3fb
>     drm: Only set DPMS ON when actually configuring a mode
> 
> 
> thanks,
> 
> Takashi
> 
> > 
> > Thanks,
> > Jeff
> > 
> > 
> > commit 500f7147cf5bafd139056d521536b10c2bc2e154
> > Author: Chris Wilson <chris@chris-wilson.co.uk>
> > Date:   Mon Jan 24 15:14:41 2011 +0000
> > 
> >     drm/i915: Reset state after a GPU reset or resume
> > 
> >     Call drm_mode_config_reset() after an invalidation event to restore any
> >     cached state to unknown.
> > 
> >     Tested-by: Takashi Iwai <tiwai@suse.de>
> >     Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/
> 
> 

-- 
Marc Koschewski

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Rafael J. Wysocki]

On Sunday, February 06, 2011, Marc Koschewski wrote:
> I've the NX stuff disabled, so to say DEBUG_RODATA=n and it doesn't resume... so
> what's next?

Did you actually try to revert the NX commits or go back to the version of the
kernel where they aren't present?

Also, what's the last known working kernel?

> I use an i7 with 32bit code as I think 64bit is a) useless for me

You're most probably wrong, because memory management is mush simpler in the
64-bit mode.  Basically, if your machine supports 64-bitness, you should use
it.

> and b) I just plugged my old HDD into my new machine.

Well, that's a good reason to stay backwards-compatible.

Thanks,
Rafael


> > >> I reverted the specified commit and my box still suffers the
> > >> resume-turns-into-cold-boot behavior. Retried two times with the commit reverted
> > >> on top of HEAD...
> > >
> > > The cold-boot problem is very likely irrelevant with i915 patches.
> > > I've got the same issue with and without the i915 fix patches on test
> > > machines here.
> > >
> > Yeah its the 32-bit NX stuff most likely if you are using 32-bit kernels.

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Takashi Iwai]

At Sun, 6 Feb 2011 13:24:08 +0100,
Marc Koschewski wrote:
> 
> Read this
> 
> 	[REGRESSION g01539ba] Hibernate broken on T510i
> 
> or this
> 
> 	[REGRESSION] S3 resume on SandyBridge doesn't work with NX protection (5bd5a45)

But this should be definitely irrelevant with i915 fixes I've been
involved with.  The NX problem already existed in rc1, IIRC.

I wonder what problem is fixed for Jeff.


thanks,

Takashi


Takashi

> 
> Marc
> 
> * Takashi Iwai <tiwai@suse.de> [2011-02-06 12:00:15 +0100]:
> 
> > At Sun, 6 Feb 2011 09:50:51 +0800,
> > Jeff Chua wrote:
> > > 
> > > On Sun, Feb 6, 2011 at 2:24 AM, Rafael J. Wysocki <rjw@sisk.pl> wrote:
> > > >> The suspend monster is back! The suspend-to-ram is fine, but upon
> > > >> resume, screen is blank. Haven't bisected in case someone has also
> > > >> done so.
> > > >
> > > > BTW, please don't reply to messages containing patches with reports of problems
> > > > that aren't caused by those patches.  It's confusing at best and at worst it
> > > > may result in the patches being rejected.
> > > 
> > > Sorry. New subject now:)
> > > 
> > > 
> > > On Sun, Feb 6, 2011 at 2:51 AM, Linus Torvalds
> > > <torvalds@linux-foundation.org> wrote:
> > > >> It's very recent. ... between commit
> > > >> 831d52bc153971b70e64eccfbed2b232394f22f8 and
> > > >> 44f2c5c841da1b1e0864d768197ab1497b5c2cc1.
> > > >
> > > > Hmm. It's almost certainly one of the DRI patches, but which one? I
> > > > think bisection is the only way to figure it out. It shouldn't be too
> > > > bad, since there's only 120 commits in that range.
> > > >
> > > > In fact, you can almost certainly just bisect from 89840966c579 to
> > > > bb5b583b5279, which is just 31 commits and should get you bisected in
> > > > just five tries or so.
> > > 
> > > Yea, I've just done that. It came down to the following commit.
> > > Reverting it solves the problem. I've gone thru a few cycles, and
> > > notebook still survives.
> > 
> > Hrm, what is the symptom?  I couldn't find it because you cut off the
> > thread, and it's not cited.
> > 
> > The commit you mentioned just adds an interface, and the the callbacks
> > aren't defined.  The real change is either in
> >   commit f3269058e7a80083dcdf89698bfcd1a6c6f8fd12
> >     drm/i915/crt: Force the initial probe after reset
> > or
> >   commit 5d1d0cc87fc0887921993ea0742932e0c8adeda0
> >     drm/i915: Reset crtc after resume
> > 
> > Also the fix might interact with
> >   commit 811aaa55ba21ab37407018cfc01770d6b037d3fb
> >     drm: Only set DPMS ON when actually configuring a mode
> > 
> > 
> > thanks,
> > 
> > Takashi
> > 
> > > 
> > > Thanks,
> > > Jeff
> > > 
> > > 
> > > commit 500f7147cf5bafd139056d521536b10c2bc2e154
> > > Author: Chris Wilson <chris@chris-wilson.co.uk>
> > > Date:   Mon Jan 24 15:14:41 2011 +0000
> > > 
> > >     drm/i915: Reset state after a GPU reset or resume
> > > 
> > >     Call drm_mode_config_reset() after an invalidation event to restore any
> > >     cached state to unknown.
> > > 
> > >     Tested-by: Takashi Iwai <tiwai@suse.de>
> > >     Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > 
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
> > Please read the FAQ at  http://www.tux.org/lkml/
> > 
> > 
> 
> -- 
> Marc Koschewski
> 

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Marc Koschewski]

* Rafael J. Wysocki <rjw@sisk.pl> [2011-02-06 14:04:23 +0100]:

> On Sunday, February 06, 2011, Marc Koschewski wrote:
> > I've the NX stuff disabled, so to say DEBUG_RODATA=n and it doesn't resume... so
> > what's next?
> 
> Did you actually try to revert the NX commits or go back to the version of the
> kernel where they aren't present?
> 
> Also, what's the last known working kernel?

2.6.37 works perfectly. After the first chunk of code after the release of
2.6.37 (so to say 2.6.37 + some stuff, but not 2.6.38-rc1) is broke.

I did not bisect it down to something. But it seems many people have trapped
into it and have pointed at some things that probably broke it - see the
SandyBridge thread.

> 
> > I use an i7 with 32bit code as I think 64bit is a) useless for me
> 
> You're most probably wrong, because memory management is mush simpler in the
> 64-bit mode.  Basically, if your machine supports 64-bitness, you should use
> it.

I didn't see any advantage in 64 bit from what I've read. And I ignore the ~1% overhead
of PAE. The hardware is fat enough...

> 
> > and b) I just plugged my old HDD into my new machine.
> 
> Well, that's a good reason to stay backwards-compatible.
> 
> Thanks,
> Rafael
> 
> 
> > > >> I reverted the specified commit and my box still suffers the
> > > >> resume-turns-into-cold-boot behavior. Retried two times with the commit reverted
> > > >> on top of HEAD...
> > > >
> > > > The cold-boot problem is very likely irrelevant with i915 patches.
> > > > I've got the same issue with and without the i915 fix patches on test
> > > > machines here.
> > > >
> > > Yeah its the 32-bit NX stuff most likely if you are using 32-bit kernels.
> 
> 

-- 
Marc Koschewski

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Rafael J. Wysocki]

On Sunday, February 06, 2011, Marc Koschewski wrote:
> * Rafael J. Wysocki <rjw@sisk.pl> [2011-02-06 14:04:23 +0100]:
> 
> > On Sunday, February 06, 2011, Marc Koschewski wrote:
> > > I've the NX stuff disabled, so to say DEBUG_RODATA=n and it doesn't resume... so
> > > what's next?
> > 
> > Did you actually try to revert the NX commits or go back to the version of the
> > kernel where they aren't present?
> > 
> > Also, what's the last known working kernel?
> 
> 2.6.37 works perfectly. After the first chunk of code after the release of
> 2.6.37 (so to say 2.6.37 + some stuff, but not 2.6.38-rc1) is broke.
> 
> I did not bisect it down to something. But it seems many people have trapped
> into it and have pointed at some things that probably broke it - see the
> SandyBridge thread.

I saw it, but it's not conclusive.  You're the last person reporting a suspend
problem which doesn't seem to be related to the NX patches and no one else
seems to be able to reproduce it (obviously including me).

If you suspend what might broke it, why don't you just try to confirm your
suspicions?

> > > I use an i7 with 32bit code as I think 64bit is a) useless for me
> > 
> > You're most probably wrong, because memory management is mush simpler in the
> > 64-bit mode.  Basically, if your machine supports 64-bitness, you should use
> > it.
> 
> I didn't see any advantage in 64 bit from what I've read.

Well, with all due respect to what you have read ...

> And I ignore the ~1% overhead of PAE. The hardware is fat enough...

... what about the kernel memory being confined to the first 1/4 of virtual
address space?  The fact that we have to use highmem on 32 bits is a good
enough reason to switch to 64 bits IMnsHO.

Thanks,
Rafael

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Jeff Chua]

On Sun, Feb 6, 2011 at 7:00 PM, Takashi Iwai <tiwai@suse.de> wrote:
> At Sun, 6 Feb 2011 09:50:51 +0800,
> Jeff Chua wrote:
>>
>> On Sun, Feb 6, 2011 at 2:24 AM, Rafael J. Wysocki <rjw@sisk.pl> wrote:
>> >> The suspend monster is back! The suspend-to-ram is fine, but upon
>> >> resume, screen is blank. Haven't bisected in case someone has also
>> >> done so.

> Hrm, what is the symptom?  I couldn't find it because you cut off the
> thread, and it's not cited.

Takashi-san,

It's the commit below. I've checked it twice. Reverting it solves the
problem. Suspend to Ram ok. Upon resume, screen is blank. Keyboard
hangs. Had to do a hard reset.

My notebook is the Lenovo X201s, 64-bit. Part of Xorg.0.log here ...

[  8492.036] (II) LoadModule: "intel"
[  8492.036] (II) Loading /usr/X11/lib/xorg/modules/drivers/intel_drv.so
[  8492.036] (II) Module intel: vendor="X.Org Foundation"
[  8492.036]    compiled for 1.9.99.901, module version = 2.14.0
[  8492.036]    Module class: X.Org Video Driver
[  8492.036]    ABI class: X.Org Video Driver, version 9.0


Thanks,
Jeff


>> commit 500f7147cf5bafd139056d521536b10c2bc2e154
>> Author: Chris Wilson <chris@chris-wilson.co.uk>
>> Date:   Mon Jan 24 15:14:41 2011 +0000
>>
>>     drm/i915: Reset state after a GPU reset or resume
>>
>>     Call drm_mode_config_reset() after an invalidation event to restore any
>>     cached state to unknown.
>>
>>     Tested-by: Takashi Iwai <tiwai@suse.de>
>>     Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Chris Wilson]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 798 bytes --]

On Sun, 6 Feb 2011 22:01:22 +0800, Jeff Chua <jeff.chua.linux@gmail.com> wrote:
> It's the commit below. I've checked it twice. Reverting it solves the
> problem. Suspend to Ram ok. Upon resume, screen is blank. Keyboard
> hangs. Had to do a hard reset.

> >> commit 500f7147cf5bafd139056d521536b10c2bc2e154
> >> Author: Chris Wilson <chris@chris-wilson.co.uk>
> >> Date:   Mon Jan 24 15:14:41 2011 +0000
> >>
> >>     drm/i915: Reset state after a GPU reset or resume

Makes no difference to my x201s.

I would have thought a bisection would have resulted in either
f3269058e7a80083dcdf89698bfcd1a6c6f8fd12 or 
5d1d0cc87fc0887921993ea0742932e0c8adeda0

Can you try reverting those two to see if either of those is the true
culprit?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Jeff Chua]

On Sun, Feb 6, 2011 at 10:01 PM, Jeff Chua <jeff.chua.linux@gmail.com> wrote:
> On Sun, Feb 6, 2011 at 7:00 PM, Takashi Iwai <tiwai@suse.de> wrote:
>> At Sun, 6 Feb 2011 09:50:51 +0800,
>> Jeff Chua wrote:
>>>
>>> On Sun, Feb 6, 2011 at 2:24 AM, Rafael J. Wysocki <rjw@sisk.pl> wrote:
>>> >> The suspend monster is back! The suspend-to-ram is fine, but upon
>>> >> resume, screen is blank. Haven't bisected in case someone has also
>>> >> done so.
>
>> Hrm, what is the symptom?  I couldn't find it because you cut off the
>> thread, and it's not cited.
>
> Takashi-san,
>
> It's the commit below. I've checked it twice. Reverting it solves the
> problem. Suspend to Ram ok. Upon resume, screen is blank. Keyboard
> hangs. Had to do a hard reset.

> The commit you mentioned just adds an interface, and the the callbacks
> aren't defined.  The real change is either in
>  commit f3269058e7a80083dcdf89698bfcd1a6c6f8fd12
>    drm/i915/crt: Force the initial probe after reset
> or
>  commit 5d1d0cc87fc0887921993ea0742932e0c8adeda0
>    drm/i915: Reset crtc after resume

uh, Sorry, misread your original post. I've retest it, and it's the 2nd one.

commit 5d1d0cc87fc0887921993ea0742932e0c8adeda0
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Mon Jan 24 15:02:15 2011 +0000

    drm/i915: Reset crtc after resume

    Based on a patch by Takashi Iwai.


I wasn't really doing a bisect last night. Just reverting those
patches that seems to be the problem last night. Just arrived in Tokyo
last night. Long flight, too tired to do the bisect. By luck, the
commit I reverted worked, but you caught me!

This time. it down to the root cause!

Thanks,
Jeff.

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Jeff Chua]

On Sun, Feb 6, 2011 at 10:47 PM, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> On Sun, 6 Feb 2011 22:01:22 +0800, Jeff Chua <jeff.chua.linux@gmail.com> wrote:
>> It's the commit below. I've checked it twice. Reverting it solves the
>> problem. Suspend to Ram ok. Upon resume, screen is blank. Keyboard
>> hangs. Had to do a hard reset.
>
>> >> commit 500f7147cf5bafd139056d521536b10c2bc2e154
>> >> Author: Chris Wilson <chris@chris-wilson.co.uk>
>> >> Date:   Mon Jan 24 15:14:41 2011 +0000
>> >>
>> >>     drm/i915: Reset state after a GPU reset or resume
>
> Makes no difference to my x201s.
>
> I would have thought a bisection would have resulted in either
> f3269058e7a80083dcdf89698bfcd1a6c6f8fd12 or
> 5d1d0cc87fc0887921993ea0742932e0c8adeda0
>
> Can you try reverting those two to see if either of those is the true
> culprit?

You're too fast. It's the commit below.

commit 5d1d0cc87fc0887921993ea0742932e0c8adeda0
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Mon Jan 24 15:02:15 2011 +0000

    drm/i915: Reset crtc after resume

    Based on a patch by Takashi Iwai.

    Reported-by: Matthias Hopf <mat@mshopf.de>
    Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=27272
    Tested-by: Takashi Iwai <tiwai@suse.de>
    Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>


Thanks,
Jeff.

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Chris Wilson]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 2451 bytes --]

On Sun, 6 Feb 2011 22:49:38 +0800, Jeff Chua <jeff.chua.linux@gmail.com> wrote:
> On Sun, Feb 6, 2011 at 10:01 PM, Jeff Chua <jeff.chua.linux@gmail.com> wrote:
> > On Sun, Feb 6, 2011 at 7:00 PM, Takashi Iwai <tiwai@suse.de> wrote:
> >> At Sun, 6 Feb 2011 09:50:51 +0800,
> >> Jeff Chua wrote:
> >>>
> >>> On Sun, Feb 6, 2011 at 2:24 AM, Rafael J. Wysocki <rjw@sisk.pl> wrote:
> >>> >> The suspend monster is back! The suspend-to-ram is fine, but upon
> >>> >> resume, screen is blank. Haven't bisected in case someone has also
> >>> >> done so.
> >
> >> Hrm, what is the symptom?  I couldn't find it because you cut off the
> >> thread, and it's not cited.
> >
> > Takashi-san,
> >
> > It's the commit below. I've checked it twice. Reverting it solves the
> > problem. Suspend to Ram ok. Upon resume, screen is blank. Keyboard
> > hangs. Had to do a hard reset.
> 
> > The commit you mentioned just adds an interface, and the the callbacks
> > aren't defined.  The real change is either in
> >  commit f3269058e7a80083dcdf89698bfcd1a6c6f8fd12
> >    drm/i915/crt: Force the initial probe after reset
> > or
> >  commit 5d1d0cc87fc0887921993ea0742932e0c8adeda0
> >    drm/i915: Reset crtc after resume
> 
> uh, Sorry, misread your original post. I've retest it, and it's the 2nd one.
> 
> commit 5d1d0cc87fc0887921993ea0742932e0c8adeda0
> Author: Chris Wilson <chris@chris-wilson.co.uk>
> Date:   Mon Jan 24 15:02:15 2011 +0000
> 
>     drm/i915: Reset crtc after resume
> 
>     Based on a patch by Takashi Iwai.
> 
> 
> I wasn't really doing a bisect last night. Just reverting those
> patches that seems to be the problem last night. Just arrived in Tokyo
> last night. Long flight, too tired to do the bisect. By luck, the
> commit I reverted worked, but you caught me!
> 
> This time. it down to the root cause!

One last step: move contents of intel_crtc_reset() back to
intel_crtc_init() one by one.

The active flag is my suspicion. I was thinking that we brought up the
outputs in a similar manner upon resume as upon initial boot. On
reflection, this is the not case.

However, the first action we take inside modesetting is to disable the
outputs about to be reconfigured. So setting active should be the right
course of action so that cleanup any residual state from resume.

So I am intrigued as to which line is the cause, and just where the
machine becomes unresponsive...
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Jeff Chua]

On Sun, Feb 6, 2011 at 11:27 PM, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> One last step: move contents of intel_crtc_reset() back to
> intel_crtc_init() one by one.
>
> The active flag is my suspicion. I was thinking that we brought up the
> outputs in a similar manner upon resume as upon initial boot. On
> reflection, this is the not case.
>
> However, the first action we take inside modesetting is to disable the
> outputs about to be reconfigured. So setting active should be the right
> course of action so that cleanup any residual state from resume.
>
> So I am intrigued as to which line is the cause, and just where the
> machine becomes unresponsive...

It's this line causing the problem.

intel_crtc->active = true; /* force the pipe off on setup_init_config */


When it's called before entering intel_crtc_reset(&intel_crtc->base),
it works, but if called within the function, it doesn't work. Strange.
Not sure whether is passing the correct value to to_intel_crtc(crtc)?


Jeff

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Jeff Chua]

On Mon, Feb 7, 2011 at 12:48 PM, Jeff Chua <jeff.chua.linux@gmail.com> wrote:
> On Sun, Feb 6, 2011 at 11:27 PM, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>> One last step: move contents of intel_crtc_reset() back to
>> intel_crtc_init() one by one.
>>
>> The active flag is my suspicion. I was thinking that we brought up the
>> outputs in a similar manner upon resume as upon initial boot. On
>> reflection, this is the not case.
>>
>> However, the first action we take inside modesetting is to disable the
>> outputs about to be reconfigured. So setting active should be the right
>> course of action so that cleanup any residual state from resume.
>>
>> So I am intrigued as to which line is the cause, and just where the
>> machine becomes unresponsive...
>
> It's this line causing the problem.
>
> intel_crtc->active = true; /* force the pipe off on setup_init_config */
>
>
> When it's called before entering intel_crtc_reset(&intel_crtc->base),
> it works, but if called within the function, it doesn't work. Strange.
> Not sure whether is passing the correct value to to_intel_crtc(crtc)?

I've added printk() below and the function returns a different value
of intel_crtc.


static void intel_crtc_reset(struct drm_crtc *crtc)
{
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        printk("intel_crtc %p\n", intel_crtc); ===> intel_crtc ffff8802349d1000

}

printk("intel_crtc %p\n", intel_crtc); ===> intel_crtc ffff8802349d0000
intel_crtc_reset(&intel_crtc->base);


Jeff

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Takashi Iwai]

At Mon, 7 Feb 2011 13:02:46 +0800,
Jeff Chua wrote:
> 
> On Mon, Feb 7, 2011 at 12:48 PM, Jeff Chua <jeff.chua.linux@gmail.com> wrote:
> > On Sun, Feb 6, 2011 at 11:27 PM, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> >> One last step: move contents of intel_crtc_reset() back to
> >> intel_crtc_init() one by one.
> >>
> >> The active flag is my suspicion. I was thinking that we brought up the
> >> outputs in a similar manner upon resume as upon initial boot. On
> >> reflection, this is the not case.
> >>
> >> However, the first action we take inside modesetting is to disable the
> >> outputs about to be reconfigured. So setting active should be the right
> >> course of action so that cleanup any residual state from resume.
> >>
> >> So I am intrigued as to which line is the cause, and just where the
> >> machine becomes unresponsive...
> >
> > It's this line causing the problem.
> >
> > intel_crtc->active = true; /* force the pipe off on setup_init_config */
> >
> >
> > When it's called before entering intel_crtc_reset(&intel_crtc->base),
> > it works, but if called within the function, it doesn't work. Strange.
> > Not sure whether is passing the correct value to to_intel_crtc(crtc)?
> 
> I've added printk() below and the function returns a different value
> of intel_crtc.
> 
> 
> static void intel_crtc_reset(struct drm_crtc *crtc)
> {
>         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>         printk("intel_crtc %p\n", intel_crtc); ===> intel_crtc ffff8802349d1000
> 
> }
> 
> printk("intel_crtc %p\n", intel_crtc); ===> intel_crtc ffff8802349d0000
> intel_crtc_reset(&intel_crtc->base);

That's weird.  Since base is the first member, both intel_crtc and crtc
must be identical.


Takashi

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Jeff Chua]

[-- Attachment #1: Type: text/plain, Size: 1957 bytes --]

On Mon, Feb 7, 2011 at 4:25 PM, Takashi Iwai <tiwai@suse.de> wrote:
> At Mon, 7 Feb 2011 13:02:46 +0800,
> Jeff Chua wrote:
>>
>> On Mon, Feb 7, 2011 at 12:48 PM, Jeff Chua <jeff.chua.linux@gmail.com> wrote:
>> > On Sun, Feb 6, 2011 at 11:27 PM, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>> >> One last step: move contents of intel_crtc_reset() back to
>> >> intel_crtc_init() one by one.
>> >>
>> >> The active flag is my suspicion. I was thinking that we brought up the
>> >> outputs in a similar manner upon resume as upon initial boot. On
>> >> reflection, this is the not case.
>> >>
>> >> However, the first action we take inside modesetting is to disable the
>> >> outputs about to be reconfigured. So setting active should be the right
>> >> course of action so that cleanup any residual state from resume.
>> >>
>> >> So I am intrigued as to which line is the cause, and just where the
>> >> machine becomes unresponsive...
>> >
>> > It's this line causing the problem.
>> >
>> > intel_crtc->active = true; /* force the pipe off on setup_init_config */
>> >
>> >
>> > When it's called before entering intel_crtc_reset(&intel_crtc->base),
>> > it works, but if called within the function, it doesn't work. Strange.
>> > Not sure whether is passing the correct value to to_intel_crtc(crtc)?
>>
>> I've added printk() below and the function returns a different value
>> of intel_crtc.
>>
>>
>> static void intel_crtc_reset(struct drm_crtc *crtc)
>> {
>>         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>>         printk("intel_crtc %p\n", intel_crtc); ===> intel_crtc ffff8802349d1000
>>
>> }
>>
>> printk("intel_crtc %p\n", intel_crtc); ===> intel_crtc ffff8802349d0000
>> intel_crtc_reset(&intel_crtc->base);
>
> That's weird.  Since base is the first member, both intel_crtc and crtc
> must be identical.

In case I'm messing something up, here's my intel_display.c

Thanks,
Jeff

[-- Attachment #2: intel_display.c --]
[-- Type: text/x-csrc, Size: 202316 bytes --]

/*
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 */

#include <linux/module.h>
#include <linux/input.h>
#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/vgaarb.h>
#include "drmP.h"
#include "intel_drv.h"
#include "i915_drm.h"
#include "i915_drv.h"
#include "i915_trace.h"
#include "drm_dp_helper.h"

#include "drm_crtc_helper.h"

#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))

bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
static void intel_update_watermarks(struct drm_device *dev);
static void intel_increase_pllclock(struct drm_crtc *crtc);
static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);

typedef struct {
    /* given values */
    int n;
    int m1, m2;
    int p1, p2;
    /* derived values */
    int	dot;
    int	vco;
    int	m;
    int	p;
} intel_clock_t;

typedef struct {
    int	min, max;
} intel_range_t;

typedef struct {
    int	dot_limit;
    int	p2_slow, p2_fast;
} intel_p2_t;

#define INTEL_P2_NUM		      2
typedef struct intel_limit intel_limit_t;
struct intel_limit {
    intel_range_t   dot, vco, n, m, m1, m2, p, p1;
    intel_p2_t	    p2;
    bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
		      int, int, intel_clock_t *);
};

#define I8XX_DOT_MIN		  25000
#define I8XX_DOT_MAX		 350000
#define I8XX_VCO_MIN		 930000
#define I8XX_VCO_MAX		1400000
#define I8XX_N_MIN		      3
#define I8XX_N_MAX		     16
#define I8XX_M_MIN		     96
#define I8XX_M_MAX		    140
#define I8XX_M1_MIN		     18
#define I8XX_M1_MAX		     26
#define I8XX_M2_MIN		      6
#define I8XX_M2_MAX		     16
#define I8XX_P_MIN		      4
#define I8XX_P_MAX		    128
#define I8XX_P1_MIN		      2
#define I8XX_P1_MAX		     33
#define I8XX_P1_LVDS_MIN	      1
#define I8XX_P1_LVDS_MAX	      6
#define I8XX_P2_SLOW		      4
#define I8XX_P2_FAST		      2
#define I8XX_P2_LVDS_SLOW	      14
#define I8XX_P2_LVDS_FAST	      7
#define I8XX_P2_SLOW_LIMIT	 165000

#define I9XX_DOT_MIN		  20000
#define I9XX_DOT_MAX		 400000
#define I9XX_VCO_MIN		1400000
#define I9XX_VCO_MAX		2800000
#define PINEVIEW_VCO_MIN		1700000
#define PINEVIEW_VCO_MAX		3500000
#define I9XX_N_MIN		      1
#define I9XX_N_MAX		      6
/* Pineview's Ncounter is a ring counter */
#define PINEVIEW_N_MIN		      3
#define PINEVIEW_N_MAX		      6
#define I9XX_M_MIN		     70
#define I9XX_M_MAX		    120
#define PINEVIEW_M_MIN		      2
#define PINEVIEW_M_MAX		    256
#define I9XX_M1_MIN		     10
#define I9XX_M1_MAX		     22
#define I9XX_M2_MIN		      5
#define I9XX_M2_MAX		      9
/* Pineview M1 is reserved, and must be 0 */
#define PINEVIEW_M1_MIN		      0
#define PINEVIEW_M1_MAX		      0
#define PINEVIEW_M2_MIN		      0
#define PINEVIEW_M2_MAX		      254
#define I9XX_P_SDVO_DAC_MIN	      5
#define I9XX_P_SDVO_DAC_MAX	     80
#define I9XX_P_LVDS_MIN		      7
#define I9XX_P_LVDS_MAX		     98
#define PINEVIEW_P_LVDS_MIN		      7
#define PINEVIEW_P_LVDS_MAX		     112
#define I9XX_P1_MIN		      1
#define I9XX_P1_MAX		      8
#define I9XX_P2_SDVO_DAC_SLOW		     10
#define I9XX_P2_SDVO_DAC_FAST		      5
#define I9XX_P2_SDVO_DAC_SLOW_LIMIT	 200000
#define I9XX_P2_LVDS_SLOW		     14
#define I9XX_P2_LVDS_FAST		      7
#define I9XX_P2_LVDS_SLOW_LIMIT		 112000

/*The parameter is for SDVO on G4x platform*/
#define G4X_DOT_SDVO_MIN           25000
#define G4X_DOT_SDVO_MAX           270000
#define G4X_VCO_MIN                1750000
#define G4X_VCO_MAX                3500000
#define G4X_N_SDVO_MIN             1
#define G4X_N_SDVO_MAX             4
#define G4X_M_SDVO_MIN             104
#define G4X_M_SDVO_MAX             138
#define G4X_M1_SDVO_MIN            17
#define G4X_M1_SDVO_MAX            23
#define G4X_M2_SDVO_MIN            5
#define G4X_M2_SDVO_MAX            11
#define G4X_P_SDVO_MIN             10
#define G4X_P_SDVO_MAX             30
#define G4X_P1_SDVO_MIN            1
#define G4X_P1_SDVO_MAX            3
#define G4X_P2_SDVO_SLOW           10
#define G4X_P2_SDVO_FAST           10
#define G4X_P2_SDVO_LIMIT          270000

/*The parameter is for HDMI_DAC on G4x platform*/
#define G4X_DOT_HDMI_DAC_MIN           22000
#define G4X_DOT_HDMI_DAC_MAX           400000
#define G4X_N_HDMI_DAC_MIN             1
#define G4X_N_HDMI_DAC_MAX             4
#define G4X_M_HDMI_DAC_MIN             104
#define G4X_M_HDMI_DAC_MAX             138
#define G4X_M1_HDMI_DAC_MIN            16
#define G4X_M1_HDMI_DAC_MAX            23
#define G4X_M2_HDMI_DAC_MIN            5
#define G4X_M2_HDMI_DAC_MAX            11
#define G4X_P_HDMI_DAC_MIN             5
#define G4X_P_HDMI_DAC_MAX             80
#define G4X_P1_HDMI_DAC_MIN            1
#define G4X_P1_HDMI_DAC_MAX            8
#define G4X_P2_HDMI_DAC_SLOW           10
#define G4X_P2_HDMI_DAC_FAST           5
#define G4X_P2_HDMI_DAC_LIMIT          165000

/*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
#define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
#define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
#define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
#define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
#define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
#define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
#define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
#define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
#define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
#define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
#define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
#define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
#define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
#define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
#define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
#define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
#define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0

/*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
#define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
#define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
#define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
#define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
#define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
#define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
#define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
#define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
#define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
#define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
#define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
#define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
#define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
#define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
#define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
#define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
#define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0

/*The parameter is for DISPLAY PORT on G4x platform*/
#define G4X_DOT_DISPLAY_PORT_MIN           161670
#define G4X_DOT_DISPLAY_PORT_MAX           227000
#define G4X_N_DISPLAY_PORT_MIN             1
#define G4X_N_DISPLAY_PORT_MAX             2
#define G4X_M_DISPLAY_PORT_MIN             97
#define G4X_M_DISPLAY_PORT_MAX             108
#define G4X_M1_DISPLAY_PORT_MIN            0x10
#define G4X_M1_DISPLAY_PORT_MAX            0x12
#define G4X_M2_DISPLAY_PORT_MIN            0x05
#define G4X_M2_DISPLAY_PORT_MAX            0x06
#define G4X_P_DISPLAY_PORT_MIN             10
#define G4X_P_DISPLAY_PORT_MAX             20
#define G4X_P1_DISPLAY_PORT_MIN            1
#define G4X_P1_DISPLAY_PORT_MAX            2
#define G4X_P2_DISPLAY_PORT_SLOW           10
#define G4X_P2_DISPLAY_PORT_FAST           10
#define G4X_P2_DISPLAY_PORT_LIMIT          0

/* Ironlake / Sandybridge */
/* as we calculate clock using (register_value + 2) for
   N/M1/M2, so here the range value for them is (actual_value-2).
 */
#define IRONLAKE_DOT_MIN         25000
#define IRONLAKE_DOT_MAX         350000
#define IRONLAKE_VCO_MIN         1760000
#define IRONLAKE_VCO_MAX         3510000
#define IRONLAKE_M1_MIN          12
#define IRONLAKE_M1_MAX          22
#define IRONLAKE_M2_MIN          5
#define IRONLAKE_M2_MAX          9
#define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */

/* We have parameter ranges for different type of outputs. */

/* DAC & HDMI Refclk 120Mhz */
#define IRONLAKE_DAC_N_MIN	1
#define IRONLAKE_DAC_N_MAX	5
#define IRONLAKE_DAC_M_MIN	79
#define IRONLAKE_DAC_M_MAX	127
#define IRONLAKE_DAC_P_MIN	5
#define IRONLAKE_DAC_P_MAX	80
#define IRONLAKE_DAC_P1_MIN	1
#define IRONLAKE_DAC_P1_MAX	8
#define IRONLAKE_DAC_P2_SLOW	10
#define IRONLAKE_DAC_P2_FAST	5

/* LVDS single-channel 120Mhz refclk */
#define IRONLAKE_LVDS_S_N_MIN	1
#define IRONLAKE_LVDS_S_N_MAX	3
#define IRONLAKE_LVDS_S_M_MIN	79
#define IRONLAKE_LVDS_S_M_MAX	118
#define IRONLAKE_LVDS_S_P_MIN	28
#define IRONLAKE_LVDS_S_P_MAX	112
#define IRONLAKE_LVDS_S_P1_MIN	2
#define IRONLAKE_LVDS_S_P1_MAX	8
#define IRONLAKE_LVDS_S_P2_SLOW	14
#define IRONLAKE_LVDS_S_P2_FAST	14

/* LVDS dual-channel 120Mhz refclk */
#define IRONLAKE_LVDS_D_N_MIN	1
#define IRONLAKE_LVDS_D_N_MAX	3
#define IRONLAKE_LVDS_D_M_MIN	79
#define IRONLAKE_LVDS_D_M_MAX	127
#define IRONLAKE_LVDS_D_P_MIN	14
#define IRONLAKE_LVDS_D_P_MAX	56
#define IRONLAKE_LVDS_D_P1_MIN	2
#define IRONLAKE_LVDS_D_P1_MAX	8
#define IRONLAKE_LVDS_D_P2_SLOW	7
#define IRONLAKE_LVDS_D_P2_FAST	7

/* LVDS single-channel 100Mhz refclk */
#define IRONLAKE_LVDS_S_SSC_N_MIN	1
#define IRONLAKE_LVDS_S_SSC_N_MAX	2
#define IRONLAKE_LVDS_S_SSC_M_MIN	79
#define IRONLAKE_LVDS_S_SSC_M_MAX	126
#define IRONLAKE_LVDS_S_SSC_P_MIN	28
#define IRONLAKE_LVDS_S_SSC_P_MAX	112
#define IRONLAKE_LVDS_S_SSC_P1_MIN	2
#define IRONLAKE_LVDS_S_SSC_P1_MAX	8
#define IRONLAKE_LVDS_S_SSC_P2_SLOW	14
#define IRONLAKE_LVDS_S_SSC_P2_FAST	14

/* LVDS dual-channel 100Mhz refclk */
#define IRONLAKE_LVDS_D_SSC_N_MIN	1
#define IRONLAKE_LVDS_D_SSC_N_MAX	3
#define IRONLAKE_LVDS_D_SSC_M_MIN	79
#define IRONLAKE_LVDS_D_SSC_M_MAX	126
#define IRONLAKE_LVDS_D_SSC_P_MIN	14
#define IRONLAKE_LVDS_D_SSC_P_MAX	42
#define IRONLAKE_LVDS_D_SSC_P1_MIN	2
#define IRONLAKE_LVDS_D_SSC_P1_MAX	6
#define IRONLAKE_LVDS_D_SSC_P2_SLOW	7
#define IRONLAKE_LVDS_D_SSC_P2_FAST	7

/* DisplayPort */
#define IRONLAKE_DP_N_MIN		1
#define IRONLAKE_DP_N_MAX		2
#define IRONLAKE_DP_M_MIN		81
#define IRONLAKE_DP_M_MAX		90
#define IRONLAKE_DP_P_MIN		10
#define IRONLAKE_DP_P_MAX		20
#define IRONLAKE_DP_P2_FAST		10
#define IRONLAKE_DP_P2_SLOW		10
#define IRONLAKE_DP_P2_LIMIT		0
#define IRONLAKE_DP_P1_MIN		1
#define IRONLAKE_DP_P1_MAX		2

/* FDI */
#define IRONLAKE_FDI_FREQ		2700000 /* in kHz for mode->clock */

static bool
intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
		    int target, int refclk, intel_clock_t *best_clock);
static bool
intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
			int target, int refclk, intel_clock_t *best_clock);

static bool
intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
		      int target, int refclk, intel_clock_t *best_clock);
static bool
intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
			   int target, int refclk, intel_clock_t *best_clock);

static inline u32 /* units of 100MHz */
intel_fdi_link_freq(struct drm_device *dev)
{
	if (IS_GEN5(dev)) {
		struct drm_i915_private *dev_priv = dev->dev_private;
		return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
	} else
		return 27;
}

static const intel_limit_t intel_limits_i8xx_dvo = {
        .dot = { .min = I8XX_DOT_MIN,		.max = I8XX_DOT_MAX },
        .vco = { .min = I8XX_VCO_MIN,		.max = I8XX_VCO_MAX },
        .n   = { .min = I8XX_N_MIN,		.max = I8XX_N_MAX },
        .m   = { .min = I8XX_M_MIN,		.max = I8XX_M_MAX },
        .m1  = { .min = I8XX_M1_MIN,		.max = I8XX_M1_MAX },
        .m2  = { .min = I8XX_M2_MIN,		.max = I8XX_M2_MAX },
        .p   = { .min = I8XX_P_MIN,		.max = I8XX_P_MAX },
        .p1  = { .min = I8XX_P1_MIN,		.max = I8XX_P1_MAX },
	.p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
		 .p2_slow = I8XX_P2_SLOW,	.p2_fast = I8XX_P2_FAST },
	.find_pll = intel_find_best_PLL,
};

static const intel_limit_t intel_limits_i8xx_lvds = {
        .dot = { .min = I8XX_DOT_MIN,		.max = I8XX_DOT_MAX },
        .vco = { .min = I8XX_VCO_MIN,		.max = I8XX_VCO_MAX },
        .n   = { .min = I8XX_N_MIN,		.max = I8XX_N_MAX },
        .m   = { .min = I8XX_M_MIN,		.max = I8XX_M_MAX },
        .m1  = { .min = I8XX_M1_MIN,		.max = I8XX_M1_MAX },
        .m2  = { .min = I8XX_M2_MIN,		.max = I8XX_M2_MAX },
        .p   = { .min = I8XX_P_MIN,		.max = I8XX_P_MAX },
        .p1  = { .min = I8XX_P1_LVDS_MIN,	.max = I8XX_P1_LVDS_MAX },
	.p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
		 .p2_slow = I8XX_P2_LVDS_SLOW,	.p2_fast = I8XX_P2_LVDS_FAST },
	.find_pll = intel_find_best_PLL,
};
	
static const intel_limit_t intel_limits_i9xx_sdvo = {
        .dot = { .min = I9XX_DOT_MIN,		.max = I9XX_DOT_MAX },
        .vco = { .min = I9XX_VCO_MIN,		.max = I9XX_VCO_MAX },
        .n   = { .min = I9XX_N_MIN,		.max = I9XX_N_MAX },
        .m   = { .min = I9XX_M_MIN,		.max = I9XX_M_MAX },
        .m1  = { .min = I9XX_M1_MIN,		.max = I9XX_M1_MAX },
        .m2  = { .min = I9XX_M2_MIN,		.max = I9XX_M2_MAX },
        .p   = { .min = I9XX_P_SDVO_DAC_MIN,	.max = I9XX_P_SDVO_DAC_MAX },
        .p1  = { .min = I9XX_P1_MIN,		.max = I9XX_P1_MAX },
	.p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
		 .p2_slow = I9XX_P2_SDVO_DAC_SLOW,	.p2_fast = I9XX_P2_SDVO_DAC_FAST },
	.find_pll = intel_find_best_PLL,
};

static const intel_limit_t intel_limits_i9xx_lvds = {
        .dot = { .min = I9XX_DOT_MIN,		.max = I9XX_DOT_MAX },
        .vco = { .min = I9XX_VCO_MIN,		.max = I9XX_VCO_MAX },
        .n   = { .min = I9XX_N_MIN,		.max = I9XX_N_MAX },
        .m   = { .min = I9XX_M_MIN,		.max = I9XX_M_MAX },
        .m1  = { .min = I9XX_M1_MIN,		.max = I9XX_M1_MAX },
        .m2  = { .min = I9XX_M2_MIN,		.max = I9XX_M2_MAX },
        .p   = { .min = I9XX_P_LVDS_MIN,	.max = I9XX_P_LVDS_MAX },
        .p1  = { .min = I9XX_P1_MIN,		.max = I9XX_P1_MAX },
	/* The single-channel range is 25-112Mhz, and dual-channel
	 * is 80-224Mhz.  Prefer single channel as much as possible.
	 */
	.p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
		 .p2_slow = I9XX_P2_LVDS_SLOW,	.p2_fast = I9XX_P2_LVDS_FAST },
	.find_pll = intel_find_best_PLL,
};

    /* below parameter and function is for G4X Chipset Family*/
static const intel_limit_t intel_limits_g4x_sdvo = {
	.dot = { .min = G4X_DOT_SDVO_MIN,	.max = G4X_DOT_SDVO_MAX },
	.vco = { .min = G4X_VCO_MIN,	        .max = G4X_VCO_MAX},
	.n   = { .min = G4X_N_SDVO_MIN,	        .max = G4X_N_SDVO_MAX },
	.m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
	.m1  = { .min = G4X_M1_SDVO_MIN,	.max = G4X_M1_SDVO_MAX },
	.m2  = { .min = G4X_M2_SDVO_MIN,	.max = G4X_M2_SDVO_MAX },
	.p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
	.p1  = { .min = G4X_P1_SDVO_MIN,	.max = G4X_P1_SDVO_MAX},
	.p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
		 .p2_slow = G4X_P2_SDVO_SLOW,
		 .p2_fast = G4X_P2_SDVO_FAST
	},
	.find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_g4x_hdmi = {
	.dot = { .min = G4X_DOT_HDMI_DAC_MIN,	.max = G4X_DOT_HDMI_DAC_MAX },
	.vco = { .min = G4X_VCO_MIN,	        .max = G4X_VCO_MAX},
	.n   = { .min = G4X_N_HDMI_DAC_MIN,	.max = G4X_N_HDMI_DAC_MAX },
	.m   = { .min = G4X_M_HDMI_DAC_MIN,	.max = G4X_M_HDMI_DAC_MAX },
	.m1  = { .min = G4X_M1_HDMI_DAC_MIN,	.max = G4X_M1_HDMI_DAC_MAX },
	.m2  = { .min = G4X_M2_HDMI_DAC_MIN,	.max = G4X_M2_HDMI_DAC_MAX },
	.p   = { .min = G4X_P_HDMI_DAC_MIN,	.max = G4X_P_HDMI_DAC_MAX },
	.p1  = { .min = G4X_P1_HDMI_DAC_MIN,	.max = G4X_P1_HDMI_DAC_MAX},
	.p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
		 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
		 .p2_fast = G4X_P2_HDMI_DAC_FAST
	},
	.find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
	.dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
		 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
	.vco = { .min = G4X_VCO_MIN,
		 .max = G4X_VCO_MAX },
	.n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
		 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
	.m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
		 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
	.m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
		 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
	.m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
		 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
	.p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
		 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
	.p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
		 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
	.p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
		 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
		 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
	},
	.find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
	.dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
		 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
	.vco = { .min = G4X_VCO_MIN,
		 .max = G4X_VCO_MAX },
	.n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
		 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
	.m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
		 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
	.m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
		 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
	.m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
		 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
	.p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
		 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
	.p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
		 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
	.p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
		 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
		 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
	},
	.find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_g4x_display_port = {
        .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
                 .max = G4X_DOT_DISPLAY_PORT_MAX },
        .vco = { .min = G4X_VCO_MIN,
                 .max = G4X_VCO_MAX},
        .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
                 .max = G4X_N_DISPLAY_PORT_MAX },
        .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
                 .max = G4X_M_DISPLAY_PORT_MAX },
        .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
                 .max = G4X_M1_DISPLAY_PORT_MAX },
        .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
                 .max = G4X_M2_DISPLAY_PORT_MAX },
        .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
                 .max = G4X_P_DISPLAY_PORT_MAX },
        .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
                 .max = G4X_P1_DISPLAY_PORT_MAX},
        .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
                 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
                 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
        .find_pll = intel_find_pll_g4x_dp,
};

static const intel_limit_t intel_limits_pineview_sdvo = {
        .dot = { .min = I9XX_DOT_MIN,		.max = I9XX_DOT_MAX},
        .vco = { .min = PINEVIEW_VCO_MIN,		.max = PINEVIEW_VCO_MAX },
        .n   = { .min = PINEVIEW_N_MIN,		.max = PINEVIEW_N_MAX },
        .m   = { .min = PINEVIEW_M_MIN,		.max = PINEVIEW_M_MAX },
        .m1  = { .min = PINEVIEW_M1_MIN,		.max = PINEVIEW_M1_MAX },
        .m2  = { .min = PINEVIEW_M2_MIN,		.max = PINEVIEW_M2_MAX },
        .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
        .p1  = { .min = I9XX_P1_MIN,		.max = I9XX_P1_MAX },
	.p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
		 .p2_slow = I9XX_P2_SDVO_DAC_SLOW,	.p2_fast = I9XX_P2_SDVO_DAC_FAST },
	.find_pll = intel_find_best_PLL,
};

static const intel_limit_t intel_limits_pineview_lvds = {
        .dot = { .min = I9XX_DOT_MIN,		.max = I9XX_DOT_MAX },
        .vco = { .min = PINEVIEW_VCO_MIN,		.max = PINEVIEW_VCO_MAX },
        .n   = { .min = PINEVIEW_N_MIN,		.max = PINEVIEW_N_MAX },
        .m   = { .min = PINEVIEW_M_MIN,		.max = PINEVIEW_M_MAX },
        .m1  = { .min = PINEVIEW_M1_MIN,		.max = PINEVIEW_M1_MAX },
        .m2  = { .min = PINEVIEW_M2_MIN,		.max = PINEVIEW_M2_MAX },
        .p   = { .min = PINEVIEW_P_LVDS_MIN,	.max = PINEVIEW_P_LVDS_MAX },
        .p1  = { .min = I9XX_P1_MIN,		.max = I9XX_P1_MAX },
	/* Pineview only supports single-channel mode. */
	.p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
		 .p2_slow = I9XX_P2_LVDS_SLOW,	.p2_fast = I9XX_P2_LVDS_SLOW },
	.find_pll = intel_find_best_PLL,
};

static const intel_limit_t intel_limits_ironlake_dac = {
	.dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
	.vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
	.n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
	.m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
	.m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
	.m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
	.p   = { .min = IRONLAKE_DAC_P_MIN,	   .max = IRONLAKE_DAC_P_MAX },
	.p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
	.p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
		 .p2_slow = IRONLAKE_DAC_P2_SLOW,
		 .p2_fast = IRONLAKE_DAC_P2_FAST },
	.find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_ironlake_single_lvds = {
	.dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
	.vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
	.n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
	.m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
	.m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
	.m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
	.p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
	.p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
	.p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
		 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
		 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
	.find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_ironlake_dual_lvds = {
	.dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
	.vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
	.n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
	.m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
	.m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
	.m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
	.p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
	.p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
	.p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
		 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
		 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
	.find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
	.dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
	.vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
	.n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
	.m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
	.m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
	.m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
	.p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
	.p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
	.p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
		 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
		 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
	.find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
	.dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
	.vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
	.n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
	.m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
	.m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
	.m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
	.p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
	.p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
	.p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
		 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
		 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
	.find_pll = intel_g4x_find_best_PLL,
};

static const intel_limit_t intel_limits_ironlake_display_port = {
        .dot = { .min = IRONLAKE_DOT_MIN,
                 .max = IRONLAKE_DOT_MAX },
        .vco = { .min = IRONLAKE_VCO_MIN,
                 .max = IRONLAKE_VCO_MAX},
        .n   = { .min = IRONLAKE_DP_N_MIN,
                 .max = IRONLAKE_DP_N_MAX },
        .m   = { .min = IRONLAKE_DP_M_MIN,
                 .max = IRONLAKE_DP_M_MAX },
        .m1  = { .min = IRONLAKE_M1_MIN,
                 .max = IRONLAKE_M1_MAX },
        .m2  = { .min = IRONLAKE_M2_MIN,
                 .max = IRONLAKE_M2_MAX },
        .p   = { .min = IRONLAKE_DP_P_MIN,
                 .max = IRONLAKE_DP_P_MAX },
        .p1  = { .min = IRONLAKE_DP_P1_MIN,
                 .max = IRONLAKE_DP_P1_MAX},
        .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
                 .p2_slow = IRONLAKE_DP_P2_SLOW,
                 .p2_fast = IRONLAKE_DP_P2_FAST },
        .find_pll = intel_find_pll_ironlake_dp,
};

static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
						int refclk)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	const intel_limit_t *limit;

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
		    LVDS_CLKB_POWER_UP) {
			/* LVDS dual channel */
			if (refclk == 100000)
				limit = &intel_limits_ironlake_dual_lvds_100m;
			else
				limit = &intel_limits_ironlake_dual_lvds;
		} else {
			if (refclk == 100000)
				limit = &intel_limits_ironlake_single_lvds_100m;
			else
				limit = &intel_limits_ironlake_single_lvds;
		}
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
			HAS_eDP)
		limit = &intel_limits_ironlake_display_port;
	else
		limit = &intel_limits_ironlake_dac;

	return limit;
}

static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	const intel_limit_t *limit;

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
		    LVDS_CLKB_POWER_UP)
			/* LVDS with dual channel */
			limit = &intel_limits_g4x_dual_channel_lvds;
		else
			/* LVDS with dual channel */
			limit = &intel_limits_g4x_single_channel_lvds;
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
		   intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
		limit = &intel_limits_g4x_hdmi;
	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
		limit = &intel_limits_g4x_sdvo;
	} else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		limit = &intel_limits_g4x_display_port;
	} else /* The option is for other outputs */
		limit = &intel_limits_i9xx_sdvo;

	return limit;
}

static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
{
	struct drm_device *dev = crtc->dev;
	const intel_limit_t *limit;

	if (HAS_PCH_SPLIT(dev))
		limit = intel_ironlake_limit(crtc, refclk);
	else if (IS_G4X(dev)) {
		limit = intel_g4x_limit(crtc);
	} else if (IS_PINEVIEW(dev)) {
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
			limit = &intel_limits_pineview_lvds;
		else
			limit = &intel_limits_pineview_sdvo;
	} else if (!IS_GEN2(dev)) {
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
			limit = &intel_limits_i9xx_lvds;
		else
			limit = &intel_limits_i9xx_sdvo;
	} else {
		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
			limit = &intel_limits_i8xx_lvds;
		else
			limit = &intel_limits_i8xx_dvo;
	}
	return limit;
}

/* m1 is reserved as 0 in Pineview, n is a ring counter */
static void pineview_clock(int refclk, intel_clock_t *clock)
{
	clock->m = clock->m2 + 2;
	clock->p = clock->p1 * clock->p2;
	clock->vco = refclk * clock->m / clock->n;
	clock->dot = clock->vco / clock->p;
}

static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
{
	if (IS_PINEVIEW(dev)) {
		pineview_clock(refclk, clock);
		return;
	}
	clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
	clock->p = clock->p1 * clock->p2;
	clock->vco = refclk * clock->m / (clock->n + 2);
	clock->dot = clock->vco / clock->p;
}

/**
 * Returns whether any output on the specified pipe is of the specified type
 */
bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
{
	struct drm_device *dev = crtc->dev;
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct intel_encoder *encoder;

	list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
		if (encoder->base.crtc == crtc && encoder->type == type)
			return true;

	return false;
}

#define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
/**
 * Returns whether the given set of divisors are valid for a given refclk with
 * the given connectors.
 */

static bool intel_PLL_is_valid(struct drm_device *dev,
			       const intel_limit_t *limit,
			       const intel_clock_t *clock)
{
	if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
		INTELPllInvalid ("p1 out of range\n");
	if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
		INTELPllInvalid ("p out of range\n");
	if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
		INTELPllInvalid ("m2 out of range\n");
	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
		INTELPllInvalid ("m1 out of range\n");
	if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
		INTELPllInvalid ("m1 <= m2\n");
	if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
		INTELPllInvalid ("m out of range\n");
	if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
		INTELPllInvalid ("n out of range\n");
	if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
		INTELPllInvalid ("vco out of range\n");
	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
	 * connector, etc., rather than just a single range.
	 */
	if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
		INTELPllInvalid ("dot out of range\n");

	return true;
}

static bool
intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
		    int target, int refclk, intel_clock_t *best_clock)

{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	intel_clock_t clock;
	int err = target;

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
	    (I915_READ(LVDS)) != 0) {
		/*
		 * For LVDS, if the panel is on, just rely on its current
		 * settings for dual-channel.  We haven't figured out how to
		 * reliably set up different single/dual channel state, if we
		 * even can.
		 */
		if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
		    LVDS_CLKB_POWER_UP)
			clock.p2 = limit->p2.p2_fast;
		else
			clock.p2 = limit->p2.p2_slow;
	} else {
		if (target < limit->p2.dot_limit)
			clock.p2 = limit->p2.p2_slow;
		else
			clock.p2 = limit->p2.p2_fast;
	}

	memset (best_clock, 0, sizeof (*best_clock));

	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
	     clock.m1++) {
		for (clock.m2 = limit->m2.min;
		     clock.m2 <= limit->m2.max; clock.m2++) {
			/* m1 is always 0 in Pineview */
			if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
				break;
			for (clock.n = limit->n.min;
			     clock.n <= limit->n.max; clock.n++) {
				for (clock.p1 = limit->p1.min;
					clock.p1 <= limit->p1.max; clock.p1++) {
					int this_err;

					intel_clock(dev, refclk, &clock);
					if (!intel_PLL_is_valid(dev, limit,
								&clock))
						continue;

					this_err = abs(clock.dot - target);
					if (this_err < err) {
						*best_clock = clock;
						err = this_err;
					}
				}
			}
		}
	}

	return (err != target);
}

static bool
intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
			int target, int refclk, intel_clock_t *best_clock)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	intel_clock_t clock;
	int max_n;
	bool found;
	/* approximately equals target * 0.00585 */
	int err_most = (target >> 8) + (target >> 9);
	found = false;

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		int lvds_reg;

		if (HAS_PCH_SPLIT(dev))
			lvds_reg = PCH_LVDS;
		else
			lvds_reg = LVDS;
		if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
		    LVDS_CLKB_POWER_UP)
			clock.p2 = limit->p2.p2_fast;
		else
			clock.p2 = limit->p2.p2_slow;
	} else {
		if (target < limit->p2.dot_limit)
			clock.p2 = limit->p2.p2_slow;
		else
			clock.p2 = limit->p2.p2_fast;
	}

	memset(best_clock, 0, sizeof(*best_clock));
	max_n = limit->n.max;
	/* based on hardware requirement, prefer smaller n to precision */
	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
		/* based on hardware requirement, prefere larger m1,m2 */
		for (clock.m1 = limit->m1.max;
		     clock.m1 >= limit->m1.min; clock.m1--) {
			for (clock.m2 = limit->m2.max;
			     clock.m2 >= limit->m2.min; clock.m2--) {
				for (clock.p1 = limit->p1.max;
				     clock.p1 >= limit->p1.min; clock.p1--) {
					int this_err;

					intel_clock(dev, refclk, &clock);
					if (!intel_PLL_is_valid(dev, limit,
								&clock))
						continue;

					this_err = abs(clock.dot - target);
					if (this_err < err_most) {
						*best_clock = clock;
						err_most = this_err;
						max_n = clock.n;
						found = true;
					}
				}
			}
		}
	}
	return found;
}

static bool
intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
			   int target, int refclk, intel_clock_t *best_clock)
{
	struct drm_device *dev = crtc->dev;
	intel_clock_t clock;

	if (target < 200000) {
		clock.n = 1;
		clock.p1 = 2;
		clock.p2 = 10;
		clock.m1 = 12;
		clock.m2 = 9;
	} else {
		clock.n = 2;
		clock.p1 = 1;
		clock.p2 = 10;
		clock.m1 = 14;
		clock.m2 = 8;
	}
	intel_clock(dev, refclk, &clock);
	memcpy(best_clock, &clock, sizeof(intel_clock_t));
	return true;
}

/* DisplayPort has only two frequencies, 162MHz and 270MHz */
static bool
intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
		      int target, int refclk, intel_clock_t *best_clock)
{
	intel_clock_t clock;
	if (target < 200000) {
		clock.p1 = 2;
		clock.p2 = 10;
		clock.n = 2;
		clock.m1 = 23;
		clock.m2 = 8;
	} else {
		clock.p1 = 1;
		clock.p2 = 10;
		clock.n = 1;
		clock.m1 = 14;
		clock.m2 = 2;
	}
	clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
	clock.p = (clock.p1 * clock.p2);
	clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
	clock.vco = 0;
	memcpy(best_clock, &clock, sizeof(intel_clock_t));
	return true;
}

/**
 * intel_wait_for_vblank - wait for vblank on a given pipe
 * @dev: drm device
 * @pipe: pipe to wait for
 *
 * Wait for vblank to occur on a given pipe.  Needed for various bits of
 * mode setting code.
 */
void intel_wait_for_vblank(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);

	/* Clear existing vblank status. Note this will clear any other
	 * sticky status fields as well.
	 *
	 * This races with i915_driver_irq_handler() with the result
	 * that either function could miss a vblank event.  Here it is not
	 * fatal, as we will either wait upon the next vblank interrupt or
	 * timeout.  Generally speaking intel_wait_for_vblank() is only
	 * called during modeset at which time the GPU should be idle and
	 * should *not* be performing page flips and thus not waiting on
	 * vblanks...
	 * Currently, the result of us stealing a vblank from the irq
	 * handler is that a single frame will be skipped during swapbuffers.
	 */
	I915_WRITE(pipestat_reg,
		   I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);

	/* Wait for vblank interrupt bit to set */
	if (wait_for(I915_READ(pipestat_reg) &
		     PIPE_VBLANK_INTERRUPT_STATUS,
		     50))
		DRM_DEBUG_KMS("vblank wait timed out\n");
}

/*
 * intel_wait_for_pipe_off - wait for pipe to turn off
 * @dev: drm device
 * @pipe: pipe to wait for
 *
 * After disabling a pipe, we can't wait for vblank in the usual way,
 * spinning on the vblank interrupt status bit, since we won't actually
 * see an interrupt when the pipe is disabled.
 *
 * On Gen4 and above:
 *   wait for the pipe register state bit to turn off
 *
 * Otherwise:
 *   wait for the display line value to settle (it usually
 *   ends up stopping at the start of the next frame).
 *
 */
void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (INTEL_INFO(dev)->gen >= 4) {
		int reg = PIPECONF(pipe);

		/* Wait for the Pipe State to go off */
		if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
			     100))
			DRM_DEBUG_KMS("pipe_off wait timed out\n");
	} else {
		u32 last_line;
		int reg = PIPEDSL(pipe);
		unsigned long timeout = jiffies + msecs_to_jiffies(100);

		/* Wait for the display line to settle */
		do {
			last_line = I915_READ(reg) & DSL_LINEMASK;
			mdelay(5);
		} while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
			 time_after(timeout, jiffies));
		if (time_after(jiffies, timeout))
			DRM_DEBUG_KMS("pipe_off wait timed out\n");
	}
}

static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_framebuffer *fb = crtc->fb;
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
	struct drm_i915_gem_object *obj = intel_fb->obj;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int plane, i;
	u32 fbc_ctl, fbc_ctl2;

	if (fb->pitch == dev_priv->cfb_pitch &&
	    obj->fence_reg == dev_priv->cfb_fence &&
	    intel_crtc->plane == dev_priv->cfb_plane &&
	    I915_READ(FBC_CONTROL) & FBC_CTL_EN)
		return;

	i8xx_disable_fbc(dev);

	dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;

	if (fb->pitch < dev_priv->cfb_pitch)
		dev_priv->cfb_pitch = fb->pitch;

	/* FBC_CTL wants 64B units */
	dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
	dev_priv->cfb_fence = obj->fence_reg;
	dev_priv->cfb_plane = intel_crtc->plane;
	plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;

	/* Clear old tags */
	for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
		I915_WRITE(FBC_TAG + (i * 4), 0);

	/* Set it up... */
	fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
	if (obj->tiling_mode != I915_TILING_NONE)
		fbc_ctl2 |= FBC_CTL_CPU_FENCE;
	I915_WRITE(FBC_CONTROL2, fbc_ctl2);
	I915_WRITE(FBC_FENCE_OFF, crtc->y);

	/* enable it... */
	fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
	if (IS_I945GM(dev))
		fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
	fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
	fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
	if (obj->tiling_mode != I915_TILING_NONE)
		fbc_ctl |= dev_priv->cfb_fence;
	I915_WRITE(FBC_CONTROL, fbc_ctl);

	DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
		      dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
}

void i8xx_disable_fbc(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 fbc_ctl;

	/* Disable compression */
	fbc_ctl = I915_READ(FBC_CONTROL);
	if ((fbc_ctl & FBC_CTL_EN) == 0)
		return;

	fbc_ctl &= ~FBC_CTL_EN;
	I915_WRITE(FBC_CONTROL, fbc_ctl);

	/* Wait for compressing bit to clear */
	if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
		DRM_DEBUG_KMS("FBC idle timed out\n");
		return;
	}

	DRM_DEBUG_KMS("disabled FBC\n");
}

static bool i8xx_fbc_enabled(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
}

static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_framebuffer *fb = crtc->fb;
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
	struct drm_i915_gem_object *obj = intel_fb->obj;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
	unsigned long stall_watermark = 200;
	u32 dpfc_ctl;

	dpfc_ctl = I915_READ(DPFC_CONTROL);
	if (dpfc_ctl & DPFC_CTL_EN) {
		if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
		    dev_priv->cfb_fence == obj->fence_reg &&
		    dev_priv->cfb_plane == intel_crtc->plane &&
		    dev_priv->cfb_y == crtc->y)
			return;

		I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
		POSTING_READ(DPFC_CONTROL);
		intel_wait_for_vblank(dev, intel_crtc->pipe);
	}

	dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
	dev_priv->cfb_fence = obj->fence_reg;
	dev_priv->cfb_plane = intel_crtc->plane;
	dev_priv->cfb_y = crtc->y;

	dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
	if (obj->tiling_mode != I915_TILING_NONE) {
		dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
		I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
	} else {
		I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
	}

	I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
		   (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
		   (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
	I915_WRITE(DPFC_FENCE_YOFF, crtc->y);

	/* enable it... */
	I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);

	DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
}

void g4x_disable_fbc(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpfc_ctl;

	/* Disable compression */
	dpfc_ctl = I915_READ(DPFC_CONTROL);
	if (dpfc_ctl & DPFC_CTL_EN) {
		dpfc_ctl &= ~DPFC_CTL_EN;
		I915_WRITE(DPFC_CONTROL, dpfc_ctl);

		DRM_DEBUG_KMS("disabled FBC\n");
	}
}

static bool g4x_fbc_enabled(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
}

static void sandybridge_blit_fbc_update(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 blt_ecoskpd;

	/* Make sure blitter notifies FBC of writes */
	__gen6_force_wake_get(dev_priv);
	blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
	blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
		GEN6_BLITTER_LOCK_SHIFT;
	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
	blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
	blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
			 GEN6_BLITTER_LOCK_SHIFT);
	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
	POSTING_READ(GEN6_BLITTER_ECOSKPD);
	__gen6_force_wake_put(dev_priv);
}

static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_framebuffer *fb = crtc->fb;
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
	struct drm_i915_gem_object *obj = intel_fb->obj;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
	unsigned long stall_watermark = 200;
	u32 dpfc_ctl;

	dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
	if (dpfc_ctl & DPFC_CTL_EN) {
		if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
		    dev_priv->cfb_fence == obj->fence_reg &&
		    dev_priv->cfb_plane == intel_crtc->plane &&
		    dev_priv->cfb_offset == obj->gtt_offset &&
		    dev_priv->cfb_y == crtc->y)
			return;

		I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
		POSTING_READ(ILK_DPFC_CONTROL);
		intel_wait_for_vblank(dev, intel_crtc->pipe);
	}

	dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
	dev_priv->cfb_fence = obj->fence_reg;
	dev_priv->cfb_plane = intel_crtc->plane;
	dev_priv->cfb_offset = obj->gtt_offset;
	dev_priv->cfb_y = crtc->y;

	dpfc_ctl &= DPFC_RESERVED;
	dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
	if (obj->tiling_mode != I915_TILING_NONE) {
		dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
		I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
	} else {
		I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
	}

	I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
		   (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
		   (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
	I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
	I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
	/* enable it... */
	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);

	if (IS_GEN6(dev)) {
		I915_WRITE(SNB_DPFC_CTL_SA,
			   SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
		I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
		sandybridge_blit_fbc_update(dev);
	}

	DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
}

void ironlake_disable_fbc(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpfc_ctl;

	/* Disable compression */
	dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
	if (dpfc_ctl & DPFC_CTL_EN) {
		dpfc_ctl &= ~DPFC_CTL_EN;
		I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);

		DRM_DEBUG_KMS("disabled FBC\n");
	}
}

static bool ironlake_fbc_enabled(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
}

bool intel_fbc_enabled(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!dev_priv->display.fbc_enabled)
		return false;

	return dev_priv->display.fbc_enabled(dev);
}

void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
{
	struct drm_i915_private *dev_priv = crtc->dev->dev_private;

	if (!dev_priv->display.enable_fbc)
		return;

	dev_priv->display.enable_fbc(crtc, interval);
}

void intel_disable_fbc(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!dev_priv->display.disable_fbc)
		return;

	dev_priv->display.disable_fbc(dev);
}

/**
 * intel_update_fbc - enable/disable FBC as needed
 * @dev: the drm_device
 *
 * Set up the framebuffer compression hardware at mode set time.  We
 * enable it if possible:
 *   - plane A only (on pre-965)
 *   - no pixel mulitply/line duplication
 *   - no alpha buffer discard
 *   - no dual wide
 *   - framebuffer <= 2048 in width, 1536 in height
 *
 * We can't assume that any compression will take place (worst case),
 * so the compressed buffer has to be the same size as the uncompressed
 * one.  It also must reside (along with the line length buffer) in
 * stolen memory.
 *
 * We need to enable/disable FBC on a global basis.
 */
static void intel_update_fbc(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = NULL, *tmp_crtc;
	struct intel_crtc *intel_crtc;
	struct drm_framebuffer *fb;
	struct intel_framebuffer *intel_fb;
	struct drm_i915_gem_object *obj;

	DRM_DEBUG_KMS("\n");

	if (!i915_powersave)
		return;

	if (!I915_HAS_FBC(dev))
		return;

	/*
	 * If FBC is already on, we just have to verify that we can
	 * keep it that way...
	 * Need to disable if:
	 *   - more than one pipe is active
	 *   - changing FBC params (stride, fence, mode)
	 *   - new fb is too large to fit in compressed buffer
	 *   - going to an unsupported config (interlace, pixel multiply, etc.)
	 */
	list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
		if (tmp_crtc->enabled) {
			if (crtc) {
				DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
				dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
				goto out_disable;
			}
			crtc = tmp_crtc;
		}
	}

	if (!crtc || crtc->fb == NULL) {
		DRM_DEBUG_KMS("no output, disabling\n");
		dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
		goto out_disable;
	}

	intel_crtc = to_intel_crtc(crtc);
	fb = crtc->fb;
	intel_fb = to_intel_framebuffer(fb);
	obj = intel_fb->obj;

	if (intel_fb->obj->base.size > dev_priv->cfb_size) {
		DRM_DEBUG_KMS("framebuffer too large, disabling "
			      "compression\n");
		dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
		goto out_disable;
	}
	if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
	    (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
		DRM_DEBUG_KMS("mode incompatible with compression, "
			      "disabling\n");
		dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
		goto out_disable;
	}
	if ((crtc->mode.hdisplay > 2048) ||
	    (crtc->mode.vdisplay > 1536)) {
		DRM_DEBUG_KMS("mode too large for compression, disabling\n");
		dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
		goto out_disable;
	}
	if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
		DRM_DEBUG_KMS("plane not 0, disabling compression\n");
		dev_priv->no_fbc_reason = FBC_BAD_PLANE;
		goto out_disable;
	}
	if (obj->tiling_mode != I915_TILING_X) {
		DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
		dev_priv->no_fbc_reason = FBC_NOT_TILED;
		goto out_disable;
	}

	/* If the kernel debugger is active, always disable compression */
	if (in_dbg_master())
		goto out_disable;

	intel_enable_fbc(crtc, 500);
	return;

out_disable:
	/* Multiple disables should be harmless */
	if (intel_fbc_enabled(dev)) {
		DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
		intel_disable_fbc(dev);
	}
}

int
intel_pin_and_fence_fb_obj(struct drm_device *dev,
			   struct drm_i915_gem_object *obj,
			   struct intel_ring_buffer *pipelined)
{
	u32 alignment;
	int ret;

	switch (obj->tiling_mode) {
	case I915_TILING_NONE:
		if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
			alignment = 128 * 1024;
		else if (INTEL_INFO(dev)->gen >= 4)
			alignment = 4 * 1024;
		else
			alignment = 64 * 1024;
		break;
	case I915_TILING_X:
		/* pin() will align the object as required by fence */
		alignment = 0;
		break;
	case I915_TILING_Y:
		/* FIXME: Is this true? */
		DRM_ERROR("Y tiled not allowed for scan out buffers\n");
		return -EINVAL;
	default:
		BUG();
	}

	ret = i915_gem_object_pin(obj, alignment, true);
	if (ret)
		return ret;

	ret = i915_gem_object_set_to_display_plane(obj, pipelined);
	if (ret)
		goto err_unpin;

	/* Install a fence for tiled scan-out. Pre-i965 always needs a
	 * fence, whereas 965+ only requires a fence if using
	 * framebuffer compression.  For simplicity, we always install
	 * a fence as the cost is not that onerous.
	 */
	if (obj->tiling_mode != I915_TILING_NONE) {
		ret = i915_gem_object_get_fence(obj, pipelined, false);
		if (ret)
			goto err_unpin;
	}

	return 0;

err_unpin:
	i915_gem_object_unpin(obj);
	return ret;
}

/* Assume fb object is pinned & idle & fenced and just update base pointers */
static int
intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
			   int x, int y, enum mode_set_atomic state)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_framebuffer *intel_fb;
	struct drm_i915_gem_object *obj;
	int plane = intel_crtc->plane;
	unsigned long Start, Offset;
	u32 dspcntr;
	u32 reg;

	switch (plane) {
	case 0:
	case 1:
		break;
	default:
		DRM_ERROR("Can't update plane %d in SAREA\n", plane);
		return -EINVAL;
	}

	intel_fb = to_intel_framebuffer(fb);
	obj = intel_fb->obj;

	reg = DSPCNTR(plane);
	dspcntr = I915_READ(reg);
	/* Mask out pixel format bits in case we change it */
	dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
	switch (fb->bits_per_pixel) {
	case 8:
		dspcntr |= DISPPLANE_8BPP;
		break;
	case 16:
		if (fb->depth == 15)
			dspcntr |= DISPPLANE_15_16BPP;
		else
			dspcntr |= DISPPLANE_16BPP;
		break;
	case 24:
	case 32:
		dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
		break;
	default:
		DRM_ERROR("Unknown color depth\n");
		return -EINVAL;
	}
	if (INTEL_INFO(dev)->gen >= 4) {
		if (obj->tiling_mode != I915_TILING_NONE)
			dspcntr |= DISPPLANE_TILED;
		else
			dspcntr &= ~DISPPLANE_TILED;
	}

	if (HAS_PCH_SPLIT(dev))
		/* must disable */
		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;

	I915_WRITE(reg, dspcntr);

	Start = obj->gtt_offset;
	Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);

	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
		      Start, Offset, x, y, fb->pitch);
	I915_WRITE(DSPSTRIDE(plane), fb->pitch);
	if (INTEL_INFO(dev)->gen >= 4) {
		I915_WRITE(DSPSURF(plane), Start);
		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
		I915_WRITE(DSPADDR(plane), Offset);
	} else
		I915_WRITE(DSPADDR(plane), Start + Offset);
	POSTING_READ(reg);

	intel_update_fbc(dev);
	intel_increase_pllclock(crtc);

	return 0;
}

static int
intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
		    struct drm_framebuffer *old_fb)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_master_private *master_priv;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int ret;

	/* no fb bound */
	if (!crtc->fb) {
		DRM_DEBUG_KMS("No FB bound\n");
		return 0;
	}

	switch (intel_crtc->plane) {
	case 0:
	case 1:
		break;
	default:
		return -EINVAL;
	}

	mutex_lock(&dev->struct_mutex);
	ret = intel_pin_and_fence_fb_obj(dev,
					 to_intel_framebuffer(crtc->fb)->obj,
					 NULL);
	if (ret != 0) {
		mutex_unlock(&dev->struct_mutex);
		return ret;
	}

	if (old_fb) {
		struct drm_i915_private *dev_priv = dev->dev_private;
		struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;

		wait_event(dev_priv->pending_flip_queue,
			   atomic_read(&obj->pending_flip) == 0);

		/* Big Hammer, we also need to ensure that any pending
		 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
		 * current scanout is retired before unpinning the old
		 * framebuffer.
		 */
		ret = i915_gem_object_flush_gpu(obj, false);
		if (ret) {
			i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
			mutex_unlock(&dev->struct_mutex);
			return ret;
		}
	}

	ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
					 LEAVE_ATOMIC_MODE_SET);
	if (ret) {
		i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
		mutex_unlock(&dev->struct_mutex);
		return ret;
	}

	if (old_fb) {
		intel_wait_for_vblank(dev, intel_crtc->pipe);
		i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
	}

	mutex_unlock(&dev->struct_mutex);

	if (!dev->primary->master)
		return 0;

	master_priv = dev->primary->master->driver_priv;
	if (!master_priv->sarea_priv)
		return 0;

	if (intel_crtc->pipe) {
		master_priv->sarea_priv->pipeB_x = x;
		master_priv->sarea_priv->pipeB_y = y;
	} else {
		master_priv->sarea_priv->pipeA_x = x;
		master_priv->sarea_priv->pipeA_y = y;
	}

	return 0;
}

static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
	dpa_ctl = I915_READ(DP_A);
	dpa_ctl &= ~DP_PLL_FREQ_MASK;

	if (clock < 200000) {
		u32 temp;
		dpa_ctl |= DP_PLL_FREQ_160MHZ;
		/* workaround for 160Mhz:
		   1) program 0x4600c bits 15:0 = 0x8124
		   2) program 0x46010 bit 0 = 1
		   3) program 0x46034 bit 24 = 1
		   4) program 0x64000 bit 14 = 1
		   */
		temp = I915_READ(0x4600c);
		temp &= 0xffff0000;
		I915_WRITE(0x4600c, temp | 0x8124);

		temp = I915_READ(0x46010);
		I915_WRITE(0x46010, temp | 1);

		temp = I915_READ(0x46034);
		I915_WRITE(0x46034, temp | (1 << 24));
	} else {
		dpa_ctl |= DP_PLL_FREQ_270MHZ;
	}
	I915_WRITE(DP_A, dpa_ctl);

	POSTING_READ(DP_A);
	udelay(500);
}

static void intel_fdi_normal_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	u32 reg, temp;

	/* enable normal train */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
	I915_WRITE(reg, temp);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_NORMAL_CPT;
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_NONE;
	}
	I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);

	/* wait one idle pattern time */
	POSTING_READ(reg);
	udelay(1000);
}

/* The FDI link training functions for ILK/Ibexpeak. */
static void ironlake_fdi_link_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	u32 reg, temp, tries;

	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
	   for train result */
	reg = FDI_RX_IMR(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_RX_SYMBOL_LOCK;
	temp &= ~FDI_RX_BIT_LOCK;
	I915_WRITE(reg, temp);
	I915_READ(reg);
	udelay(150);

	/* enable CPU FDI TX and PCH FDI RX */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~(7 << 19);
	temp |= (intel_crtc->fdi_lanes - 1) << 19;
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_1;
	I915_WRITE(reg, temp | FDI_TX_ENABLE);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_1;
	I915_WRITE(reg, temp | FDI_RX_ENABLE);

	POSTING_READ(reg);
	udelay(150);

	/* Ironlake workaround, enable clock pointer after FDI enable*/
	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);

	reg = FDI_RX_IIR(pipe);
	for (tries = 0; tries < 5; tries++) {
		temp = I915_READ(reg);
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

		if ((temp & FDI_RX_BIT_LOCK)) {
			DRM_DEBUG_KMS("FDI train 1 done.\n");
			I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
			break;
		}
	}
	if (tries == 5)
		DRM_ERROR("FDI train 1 fail!\n");

	/* Train 2 */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_2;
	I915_WRITE(reg, temp);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_2;
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
	udelay(150);

	reg = FDI_RX_IIR(pipe);
	for (tries = 0; tries < 5; tries++) {
		temp = I915_READ(reg);
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

		if (temp & FDI_RX_SYMBOL_LOCK) {
			I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
			DRM_DEBUG_KMS("FDI train 2 done.\n");
			break;
		}
	}
	if (tries == 5)
		DRM_ERROR("FDI train 2 fail!\n");

	DRM_DEBUG_KMS("FDI train done\n");

}

static const int const snb_b_fdi_train_param [] = {
	FDI_LINK_TRAIN_400MV_0DB_SNB_B,
	FDI_LINK_TRAIN_400MV_6DB_SNB_B,
	FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
	FDI_LINK_TRAIN_800MV_0DB_SNB_B,
};

/* The FDI link training functions for SNB/Cougarpoint. */
static void gen6_fdi_link_train(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	u32 reg, temp, i;

	/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
	   for train result */
	reg = FDI_RX_IMR(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_RX_SYMBOL_LOCK;
	temp &= ~FDI_RX_BIT_LOCK;
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
	udelay(150);

	/* enable CPU FDI TX and PCH FDI RX */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~(7 << 19);
	temp |= (intel_crtc->fdi_lanes - 1) << 19;
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_1;
	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
	/* SNB-B */
	temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
	I915_WRITE(reg, temp | FDI_TX_ENABLE);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_PATTERN_1;
	}
	I915_WRITE(reg, temp | FDI_RX_ENABLE);

	POSTING_READ(reg);
	udelay(150);

	for (i = 0; i < 4; i++ ) {
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		temp |= snb_b_fdi_train_param[i];
		I915_WRITE(reg, temp);

		POSTING_READ(reg);
		udelay(500);

		reg = FDI_RX_IIR(pipe);
		temp = I915_READ(reg);
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

		if (temp & FDI_RX_BIT_LOCK) {
			I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
			DRM_DEBUG_KMS("FDI train 1 done.\n");
			break;
		}
	}
	if (i == 4)
		DRM_ERROR("FDI train 1 fail!\n");

	/* Train 2 */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_2;
	if (IS_GEN6(dev)) {
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		/* SNB-B */
		temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
	}
	I915_WRITE(reg, temp);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_PATTERN_2;
	}
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
	udelay(150);

	for (i = 0; i < 4; i++ ) {
		reg = FDI_TX_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
		temp |= snb_b_fdi_train_param[i];
		I915_WRITE(reg, temp);

		POSTING_READ(reg);
		udelay(500);

		reg = FDI_RX_IIR(pipe);
		temp = I915_READ(reg);
		DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

		if (temp & FDI_RX_SYMBOL_LOCK) {
			I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
			DRM_DEBUG_KMS("FDI train 2 done.\n");
			break;
		}
	}
	if (i == 4)
		DRM_ERROR("FDI train 2 fail!\n");

	DRM_DEBUG_KMS("FDI train done.\n");
}

static void ironlake_fdi_enable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	u32 reg, temp;

	/* Write the TU size bits so error detection works */
	I915_WRITE(FDI_RX_TUSIZE1(pipe),
		   I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);

	/* enable PCH FDI RX PLL, wait warmup plus DMI latency */
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~((0x7 << 19) | (0x7 << 16));
	temp |= (intel_crtc->fdi_lanes - 1) << 19;
	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
	I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);

	POSTING_READ(reg);
	udelay(200);

	/* Switch from Rawclk to PCDclk */
	temp = I915_READ(reg);
	I915_WRITE(reg, temp | FDI_PCDCLK);

	POSTING_READ(reg);
	udelay(200);

	/* Enable CPU FDI TX PLL, always on for Ironlake */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	if ((temp & FDI_TX_PLL_ENABLE) == 0) {
		I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);

		POSTING_READ(reg);
		udelay(100);
	}
}

static void intel_flush_display_plane(struct drm_device *dev,
				      int plane)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 reg = DSPADDR(plane);
	I915_WRITE(reg, I915_READ(reg));
}

/*
 * When we disable a pipe, we need to clear any pending scanline wait events
 * to avoid hanging the ring, which we assume we are waiting on.
 */
static void intel_clear_scanline_wait(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_ring_buffer *ring;
	u32 tmp;

	if (IS_GEN2(dev))
		/* Can't break the hang on i8xx */
		return;

	ring = LP_RING(dev_priv);
	tmp = I915_READ_CTL(ring);
	if (tmp & RING_WAIT)
		I915_WRITE_CTL(ring, tmp);
}

static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
{
	struct drm_i915_gem_object *obj;
	struct drm_i915_private *dev_priv;

	if (crtc->fb == NULL)
		return;

	obj = to_intel_framebuffer(crtc->fb)->obj;
	dev_priv = crtc->dev->dev_private;
	wait_event(dev_priv->pending_flip_queue,
		   atomic_read(&obj->pending_flip) == 0);
}

static void ironlake_crtc_enable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
	u32 reg, temp;

	if (intel_crtc->active)
		return;

	intel_crtc->active = true;
	intel_update_watermarks(dev);

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		temp = I915_READ(PCH_LVDS);
		if ((temp & LVDS_PORT_EN) == 0)
			I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
	}

	ironlake_fdi_enable(crtc);

	/* Enable panel fitting for LVDS */
	if (dev_priv->pch_pf_size &&
	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
		/* Force use of hard-coded filter coefficients
		 * as some pre-programmed values are broken,
		 * e.g. x201.
		 */
		I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
			   PF_ENABLE | PF_FILTER_MED_3x3);
		I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
			   dev_priv->pch_pf_pos);
		I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
			   dev_priv->pch_pf_size);
	}

	/* Enable CPU pipe */
	reg = PIPECONF(pipe);
	temp = I915_READ(reg);
	if ((temp & PIPECONF_ENABLE) == 0) {
		I915_WRITE(reg, temp | PIPECONF_ENABLE);
		POSTING_READ(reg);
		intel_wait_for_vblank(dev, intel_crtc->pipe);
	}

	/* configure and enable CPU plane */
	reg = DSPCNTR(plane);
	temp = I915_READ(reg);
	if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
		I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
		intel_flush_display_plane(dev, plane);
	}

	/* For PCH output, training FDI link */
	if (IS_GEN6(dev))
		gen6_fdi_link_train(crtc);
	else
		ironlake_fdi_link_train(crtc);

	/* enable PCH DPLL */
	reg = PCH_DPLL(pipe);
	temp = I915_READ(reg);
	if ((temp & DPLL_VCO_ENABLE) == 0) {
		I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
		POSTING_READ(reg);
		udelay(200);
	}

	if (HAS_PCH_CPT(dev)) {
		/* Be sure PCH DPLL SEL is set */
		temp = I915_READ(PCH_DPLL_SEL);
		if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
			temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
		else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
			temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
		I915_WRITE(PCH_DPLL_SEL, temp);
	}

	/* set transcoder timing */
	I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
	I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
	I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));

	I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
	I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
	I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));

	intel_fdi_normal_train(crtc);

	/* For PCH DP, enable TRANS_DP_CTL */
	if (HAS_PCH_CPT(dev) &&
	    intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
		reg = TRANS_DP_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~(TRANS_DP_PORT_SEL_MASK |
			  TRANS_DP_SYNC_MASK |
			  TRANS_DP_BPC_MASK);
		temp |= (TRANS_DP_OUTPUT_ENABLE |
			 TRANS_DP_ENH_FRAMING);
		temp |= TRANS_DP_8BPC;

		if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
			temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
		if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
			temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;

		switch (intel_trans_dp_port_sel(crtc)) {
		case PCH_DP_B:
			temp |= TRANS_DP_PORT_SEL_B;
			break;
		case PCH_DP_C:
			temp |= TRANS_DP_PORT_SEL_C;
			break;
		case PCH_DP_D:
			temp |= TRANS_DP_PORT_SEL_D;
			break;
		default:
			DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
			temp |= TRANS_DP_PORT_SEL_B;
			break;
		}

		I915_WRITE(reg, temp);
	}

	/* enable PCH transcoder */
	reg = TRANSCONF(pipe);
	temp = I915_READ(reg);
	/*
	 * make the BPC in transcoder be consistent with
	 * that in pipeconf reg.
	 */
	temp &= ~PIPE_BPC_MASK;
	temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
	I915_WRITE(reg, temp | TRANS_ENABLE);
	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
		DRM_ERROR("failed to enable transcoder %d\n", pipe);

	intel_crtc_load_lut(crtc);
	intel_update_fbc(dev);
	intel_crtc_update_cursor(crtc, true);
}

static void ironlake_crtc_disable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
	u32 reg, temp;

	if (!intel_crtc->active)
		return;

	intel_crtc_wait_for_pending_flips(crtc);
	drm_vblank_off(dev, pipe);
	intel_crtc_update_cursor(crtc, false);

	/* Disable display plane */
	reg = DSPCNTR(plane);
	temp = I915_READ(reg);
	if (temp & DISPLAY_PLANE_ENABLE) {
		I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
		intel_flush_display_plane(dev, plane);
	}

	if (dev_priv->cfb_plane == plane &&
	    dev_priv->display.disable_fbc)
		dev_priv->display.disable_fbc(dev);

	/* disable cpu pipe, disable after all planes disabled */
	reg = PIPECONF(pipe);
	temp = I915_READ(reg);
	if (temp & PIPECONF_ENABLE) {
		I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
		POSTING_READ(reg);
		/* wait for cpu pipe off, pipe state */
		intel_wait_for_pipe_off(dev, intel_crtc->pipe);
	}

	/* Disable PF */
	I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
	I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);

	/* disable CPU FDI tx and PCH FDI rx */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
	POSTING_READ(reg);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~(0x7 << 16);
	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);

	POSTING_READ(reg);
	udelay(100);

	/* Ironlake workaround, disable clock pointer after downing FDI */
	if (HAS_PCH_IBX(dev))
		I915_WRITE(FDI_RX_CHICKEN(pipe),
			   I915_READ(FDI_RX_CHICKEN(pipe) &
				     ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));

	/* still set train pattern 1 */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	temp &= ~FDI_LINK_TRAIN_NONE;
	temp |= FDI_LINK_TRAIN_PATTERN_1;
	I915_WRITE(reg, temp);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	if (HAS_PCH_CPT(dev)) {
		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
	} else {
		temp &= ~FDI_LINK_TRAIN_NONE;
		temp |= FDI_LINK_TRAIN_PATTERN_1;
	}
	/* BPC in FDI rx is consistent with that in PIPECONF */
	temp &= ~(0x07 << 16);
	temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
	I915_WRITE(reg, temp);

	POSTING_READ(reg);
	udelay(100);

	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
		temp = I915_READ(PCH_LVDS);
		if (temp & LVDS_PORT_EN) {
			I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
			POSTING_READ(PCH_LVDS);
			udelay(100);
		}
	}

	/* disable PCH transcoder */
	reg = TRANSCONF(plane);
	temp = I915_READ(reg);
	if (temp & TRANS_ENABLE) {
		I915_WRITE(reg, temp & ~TRANS_ENABLE);
		/* wait for PCH transcoder off, transcoder state */
		if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
			DRM_ERROR("failed to disable transcoder\n");
	}

	if (HAS_PCH_CPT(dev)) {
		/* disable TRANS_DP_CTL */
		reg = TRANS_DP_CTL(pipe);
		temp = I915_READ(reg);
		temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
		I915_WRITE(reg, temp);

		/* disable DPLL_SEL */
		temp = I915_READ(PCH_DPLL_SEL);
		if (pipe == 0)
			temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
		else
			temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
		I915_WRITE(PCH_DPLL_SEL, temp);
	}

	/* disable PCH DPLL */
	reg = PCH_DPLL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);

	/* Switch from PCDclk to Rawclk */
	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~FDI_PCDCLK);

	/* Disable CPU FDI TX PLL */
	reg = FDI_TX_CTL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);

	POSTING_READ(reg);
	udelay(100);

	reg = FDI_RX_CTL(pipe);
	temp = I915_READ(reg);
	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);

	/* Wait for the clocks to turn off. */
	POSTING_READ(reg);
	udelay(100);

	intel_crtc->active = false;
	intel_update_watermarks(dev);
	intel_update_fbc(dev);
	intel_clear_scanline_wait(dev);
}

static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;

	/* XXX: When our outputs are all unaware of DPMS modes other than off
	 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
	 */
	switch (mode) {
	case DRM_MODE_DPMS_ON:
	case DRM_MODE_DPMS_STANDBY:
	case DRM_MODE_DPMS_SUSPEND:
		DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
		ironlake_crtc_enable(crtc);
		break;

	case DRM_MODE_DPMS_OFF:
		DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
		ironlake_crtc_disable(crtc);
		break;
	}
}

static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
{
	if (!enable && intel_crtc->overlay) {
		struct drm_device *dev = intel_crtc->base.dev;

		mutex_lock(&dev->struct_mutex);
		(void) intel_overlay_switch_off(intel_crtc->overlay, false);
		mutex_unlock(&dev->struct_mutex);
	}

	/* Let userspace switch the overlay on again. In most cases userspace
	 * has to recompute where to put it anyway.
	 */
}

static void i9xx_crtc_enable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
	u32 reg, temp;

	if (intel_crtc->active)
		return;

	intel_crtc->active = true;
	intel_update_watermarks(dev);

	/* Enable the DPLL */
	reg = DPLL(pipe);
	temp = I915_READ(reg);
	if ((temp & DPLL_VCO_ENABLE) == 0) {
		I915_WRITE(reg, temp);

		/* Wait for the clocks to stabilize. */
		POSTING_READ(reg);
		udelay(150);

		I915_WRITE(reg, temp | DPLL_VCO_ENABLE);

		/* Wait for the clocks to stabilize. */
		POSTING_READ(reg);
		udelay(150);

		I915_WRITE(reg, temp | DPLL_VCO_ENABLE);

		/* Wait for the clocks to stabilize. */
		POSTING_READ(reg);
		udelay(150);
	}

	/* Enable the pipe */
	reg = PIPECONF(pipe);
	temp = I915_READ(reg);
	if ((temp & PIPECONF_ENABLE) == 0)
		I915_WRITE(reg, temp | PIPECONF_ENABLE);

	/* Enable the plane */
	reg = DSPCNTR(plane);
	temp = I915_READ(reg);
	if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
		I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
		intel_flush_display_plane(dev, plane);
	}

	intel_crtc_load_lut(crtc);
	intel_update_fbc(dev);

	/* Give the overlay scaler a chance to enable if it's on this pipe */
	intel_crtc_dpms_overlay(intel_crtc, true);
	intel_crtc_update_cursor(crtc, true);
}

static void i9xx_crtc_disable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
	u32 reg, temp;

	if (!intel_crtc->active)
		return;

	/* Give the overlay scaler a chance to disable if it's on this pipe */
	intel_crtc_wait_for_pending_flips(crtc);
	drm_vblank_off(dev, pipe);
	intel_crtc_dpms_overlay(intel_crtc, false);
	intel_crtc_update_cursor(crtc, false);

	if (dev_priv->cfb_plane == plane &&
	    dev_priv->display.disable_fbc)
		dev_priv->display.disable_fbc(dev);

	/* Disable display plane */
	reg = DSPCNTR(plane);
	temp = I915_READ(reg);
	if (temp & DISPLAY_PLANE_ENABLE) {
		I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
		/* Flush the plane changes */
		intel_flush_display_plane(dev, plane);

		/* Wait for vblank for the disable to take effect */
		if (IS_GEN2(dev))
			intel_wait_for_vblank(dev, pipe);
	}

	/* Don't disable pipe A or pipe A PLLs if needed */
	if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		goto done;

	/* Next, disable display pipes */
	reg = PIPECONF(pipe);
	temp = I915_READ(reg);
	if (temp & PIPECONF_ENABLE) {
		I915_WRITE(reg, temp & ~PIPECONF_ENABLE);

		/* Wait for the pipe to turn off */
		POSTING_READ(reg);
		intel_wait_for_pipe_off(dev, pipe);
	}

	reg = DPLL(pipe);
	temp = I915_READ(reg);
	if (temp & DPLL_VCO_ENABLE) {
		I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);

		/* Wait for the clocks to turn off. */
		POSTING_READ(reg);
		udelay(150);
	}

done:
	intel_crtc->active = false;
	intel_update_fbc(dev);
	intel_update_watermarks(dev);
	intel_clear_scanline_wait(dev);
}

static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
{
	/* XXX: When our outputs are all unaware of DPMS modes other than off
	 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
	 */
	switch (mode) {
	case DRM_MODE_DPMS_ON:
	case DRM_MODE_DPMS_STANDBY:
	case DRM_MODE_DPMS_SUSPEND:
		i9xx_crtc_enable(crtc);
		break;
	case DRM_MODE_DPMS_OFF:
		i9xx_crtc_disable(crtc);
		break;
	}
}

/**
 * Sets the power management mode of the pipe and plane.
 */
static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_master_private *master_priv;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	bool enabled;

	if (intel_crtc->dpms_mode == mode)
		return;

	intel_crtc->dpms_mode = mode;

	dev_priv->display.dpms(crtc, mode);

	if (!dev->primary->master)
		return;

	master_priv = dev->primary->master->driver_priv;
	if (!master_priv->sarea_priv)
		return;

	enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;

	switch (pipe) {
	case 0:
		master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
		master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
		break;
	case 1:
		master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
		master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
		break;
	default:
		DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
		break;
	}
}

static void intel_crtc_disable(struct drm_crtc *crtc)
{
	struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
	struct drm_device *dev = crtc->dev;

	crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);

	if (crtc->fb) {
		mutex_lock(&dev->struct_mutex);
		i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
		mutex_unlock(&dev->struct_mutex);
	}
}

/* Prepare for a mode set.
 *
 * Note we could be a lot smarter here.  We need to figure out which outputs
 * will be enabled, which disabled (in short, how the config will changes)
 * and perform the minimum necessary steps to accomplish that, e.g. updating
 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
 * panel fitting is in the proper state, etc.
 */
static void i9xx_crtc_prepare(struct drm_crtc *crtc)
{
	i9xx_crtc_disable(crtc);
}

static void i9xx_crtc_commit(struct drm_crtc *crtc)
{
	i9xx_crtc_enable(crtc);
}

static void ironlake_crtc_prepare(struct drm_crtc *crtc)
{
	ironlake_crtc_disable(crtc);
}

static void ironlake_crtc_commit(struct drm_crtc *crtc)
{
	ironlake_crtc_enable(crtc);
}

void intel_encoder_prepare (struct drm_encoder *encoder)
{
	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
	/* lvds has its own version of prepare see intel_lvds_prepare */
	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
}

void intel_encoder_commit (struct drm_encoder *encoder)
{
	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
	/* lvds has its own version of commit see intel_lvds_commit */
	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
}

void intel_encoder_destroy(struct drm_encoder *encoder)
{
	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);

	drm_encoder_cleanup(encoder);
	kfree(intel_encoder);
}

static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
				  struct drm_display_mode *mode,
				  struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = crtc->dev;

	if (HAS_PCH_SPLIT(dev)) {
		/* FDI link clock is fixed at 2.7G */
		if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
			return false;
	}

	/* XXX some encoders set the crtcinfo, others don't.
	 * Obviously we need some form of conflict resolution here...
	 */
	if (adjusted_mode->crtc_htotal == 0)
		drm_mode_set_crtcinfo(adjusted_mode, 0);

	return true;
}

static int i945_get_display_clock_speed(struct drm_device *dev)
{
	return 400000;
}

static int i915_get_display_clock_speed(struct drm_device *dev)
{
	return 333000;
}

static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
{
	return 200000;
}

static int i915gm_get_display_clock_speed(struct drm_device *dev)
{
	u16 gcfgc = 0;

	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);

	if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
		return 133000;
	else {
		switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
		case GC_DISPLAY_CLOCK_333_MHZ:
			return 333000;
		default:
		case GC_DISPLAY_CLOCK_190_200_MHZ:
			return 190000;
		}
	}
}

static int i865_get_display_clock_speed(struct drm_device *dev)
{
	return 266000;
}

static int i855_get_display_clock_speed(struct drm_device *dev)
{
	u16 hpllcc = 0;
	/* Assume that the hardware is in the high speed state.  This
	 * should be the default.
	 */
	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
	case GC_CLOCK_133_200:
	case GC_CLOCK_100_200:
		return 200000;
	case GC_CLOCK_166_250:
		return 250000;
	case GC_CLOCK_100_133:
		return 133000;
	}

	/* Shouldn't happen */
	return 0;
}

static int i830_get_display_clock_speed(struct drm_device *dev)
{
	return 133000;
}

struct fdi_m_n {
	u32        tu;
	u32        gmch_m;
	u32        gmch_n;
	u32        link_m;
	u32        link_n;
};

static void
fdi_reduce_ratio(u32 *num, u32 *den)
{
	while (*num > 0xffffff || *den > 0xffffff) {
		*num >>= 1;
		*den >>= 1;
	}
}

static void
ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
		     int link_clock, struct fdi_m_n *m_n)
{
	m_n->tu = 64; /* default size */

	/* BUG_ON(pixel_clock > INT_MAX / 36); */
	m_n->gmch_m = bits_per_pixel * pixel_clock;
	m_n->gmch_n = link_clock * nlanes * 8;
	fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);

	m_n->link_m = pixel_clock;
	m_n->link_n = link_clock;
	fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
}


struct intel_watermark_params {
	unsigned long fifo_size;
	unsigned long max_wm;
	unsigned long default_wm;
	unsigned long guard_size;
	unsigned long cacheline_size;
};

/* Pineview has different values for various configs */
static struct intel_watermark_params pineview_display_wm = {
	PINEVIEW_DISPLAY_FIFO,
	PINEVIEW_MAX_WM,
	PINEVIEW_DFT_WM,
	PINEVIEW_GUARD_WM,
	PINEVIEW_FIFO_LINE_SIZE
};
static struct intel_watermark_params pineview_display_hplloff_wm = {
	PINEVIEW_DISPLAY_FIFO,
	PINEVIEW_MAX_WM,
	PINEVIEW_DFT_HPLLOFF_WM,
	PINEVIEW_GUARD_WM,
	PINEVIEW_FIFO_LINE_SIZE
};
static struct intel_watermark_params pineview_cursor_wm = {
	PINEVIEW_CURSOR_FIFO,
	PINEVIEW_CURSOR_MAX_WM,
	PINEVIEW_CURSOR_DFT_WM,
	PINEVIEW_CURSOR_GUARD_WM,
	PINEVIEW_FIFO_LINE_SIZE,
};
static struct intel_watermark_params pineview_cursor_hplloff_wm = {
	PINEVIEW_CURSOR_FIFO,
	PINEVIEW_CURSOR_MAX_WM,
	PINEVIEW_CURSOR_DFT_WM,
	PINEVIEW_CURSOR_GUARD_WM,
	PINEVIEW_FIFO_LINE_SIZE
};
static struct intel_watermark_params g4x_wm_info = {
	G4X_FIFO_SIZE,
	G4X_MAX_WM,
	G4X_MAX_WM,
	2,
	G4X_FIFO_LINE_SIZE,
};
static struct intel_watermark_params g4x_cursor_wm_info = {
	I965_CURSOR_FIFO,
	I965_CURSOR_MAX_WM,
	I965_CURSOR_DFT_WM,
	2,
	G4X_FIFO_LINE_SIZE,
};
static struct intel_watermark_params i965_cursor_wm_info = {
	I965_CURSOR_FIFO,
	I965_CURSOR_MAX_WM,
	I965_CURSOR_DFT_WM,
	2,
	I915_FIFO_LINE_SIZE,
};
static struct intel_watermark_params i945_wm_info = {
	I945_FIFO_SIZE,
	I915_MAX_WM,
	1,
	2,
	I915_FIFO_LINE_SIZE
};
static struct intel_watermark_params i915_wm_info = {
	I915_FIFO_SIZE,
	I915_MAX_WM,
	1,
	2,
	I915_FIFO_LINE_SIZE
};
static struct intel_watermark_params i855_wm_info = {
	I855GM_FIFO_SIZE,
	I915_MAX_WM,
	1,
	2,
	I830_FIFO_LINE_SIZE
};
static struct intel_watermark_params i830_wm_info = {
	I830_FIFO_SIZE,
	I915_MAX_WM,
	1,
	2,
	I830_FIFO_LINE_SIZE
};

static struct intel_watermark_params ironlake_display_wm_info = {
	ILK_DISPLAY_FIFO,
	ILK_DISPLAY_MAXWM,
	ILK_DISPLAY_DFTWM,
	2,
	ILK_FIFO_LINE_SIZE
};

static struct intel_watermark_params ironlake_cursor_wm_info = {
	ILK_CURSOR_FIFO,
	ILK_CURSOR_MAXWM,
	ILK_CURSOR_DFTWM,
	2,
	ILK_FIFO_LINE_SIZE
};

static struct intel_watermark_params ironlake_display_srwm_info = {
	ILK_DISPLAY_SR_FIFO,
	ILK_DISPLAY_MAX_SRWM,
	ILK_DISPLAY_DFT_SRWM,
	2,
	ILK_FIFO_LINE_SIZE
};

static struct intel_watermark_params ironlake_cursor_srwm_info = {
	ILK_CURSOR_SR_FIFO,
	ILK_CURSOR_MAX_SRWM,
	ILK_CURSOR_DFT_SRWM,
	2,
	ILK_FIFO_LINE_SIZE
};

static struct intel_watermark_params sandybridge_display_wm_info = {
	SNB_DISPLAY_FIFO,
	SNB_DISPLAY_MAXWM,
	SNB_DISPLAY_DFTWM,
	2,
	SNB_FIFO_LINE_SIZE
};

static struct intel_watermark_params sandybridge_cursor_wm_info = {
	SNB_CURSOR_FIFO,
	SNB_CURSOR_MAXWM,
	SNB_CURSOR_DFTWM,
	2,
	SNB_FIFO_LINE_SIZE
};

static struct intel_watermark_params sandybridge_display_srwm_info = {
	SNB_DISPLAY_SR_FIFO,
	SNB_DISPLAY_MAX_SRWM,
	SNB_DISPLAY_DFT_SRWM,
	2,
	SNB_FIFO_LINE_SIZE
};

static struct intel_watermark_params sandybridge_cursor_srwm_info = {
	SNB_CURSOR_SR_FIFO,
	SNB_CURSOR_MAX_SRWM,
	SNB_CURSOR_DFT_SRWM,
	2,
	SNB_FIFO_LINE_SIZE
};


/**
 * intel_calculate_wm - calculate watermark level
 * @clock_in_khz: pixel clock
 * @wm: chip FIFO params
 * @pixel_size: display pixel size
 * @latency_ns: memory latency for the platform
 *
 * Calculate the watermark level (the level at which the display plane will
 * start fetching from memory again).  Each chip has a different display
 * FIFO size and allocation, so the caller needs to figure that out and pass
 * in the correct intel_watermark_params structure.
 *
 * As the pixel clock runs, the FIFO will be drained at a rate that depends
 * on the pixel size.  When it reaches the watermark level, it'll start
 * fetching FIFO line sized based chunks from memory until the FIFO fills
 * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 * will occur, and a display engine hang could result.
 */
static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
					struct intel_watermark_params *wm,
					int pixel_size,
					unsigned long latency_ns)
{
	long entries_required, wm_size;

	/*
	 * Note: we need to make sure we don't overflow for various clock &
	 * latency values.
	 * clocks go from a few thousand to several hundred thousand.
	 * latency is usually a few thousand
	 */
	entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
		1000;
	entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);

	DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);

	wm_size = wm->fifo_size - (entries_required + wm->guard_size);

	DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);

	/* Don't promote wm_size to unsigned... */
	if (wm_size > (long)wm->max_wm)
		wm_size = wm->max_wm;
	if (wm_size <= 0)
		wm_size = wm->default_wm;
	return wm_size;
}

struct cxsr_latency {
	int is_desktop;
	int is_ddr3;
	unsigned long fsb_freq;
	unsigned long mem_freq;
	unsigned long display_sr;
	unsigned long display_hpll_disable;
	unsigned long cursor_sr;
	unsigned long cursor_hpll_disable;
};

static const struct cxsr_latency cxsr_latency_table[] = {
	{1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
	{1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
	{1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
	{1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
	{1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */

	{1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
	{1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
	{1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
	{1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
	{1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */

	{1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
	{1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
	{1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
	{1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
	{1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */

	{0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
	{0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
	{0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
	{0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
	{0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */

	{0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
	{0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
	{0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
	{0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
	{0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */

	{0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
	{0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
	{0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
	{0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
	{0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
};

static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
							 int is_ddr3,
							 int fsb,
							 int mem)
{
	const struct cxsr_latency *latency;
	int i;

	if (fsb == 0 || mem == 0)
		return NULL;

	for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
		latency = &cxsr_latency_table[i];
		if (is_desktop == latency->is_desktop &&
		    is_ddr3 == latency->is_ddr3 &&
		    fsb == latency->fsb_freq && mem == latency->mem_freq)
			return latency;
	}

	DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");

	return NULL;
}

static void pineview_disable_cxsr(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	/* deactivate cxsr */
	I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
}

/*
 * Latency for FIFO fetches is dependent on several factors:
 *   - memory configuration (speed, channels)
 *   - chipset
 *   - current MCH state
 * It can be fairly high in some situations, so here we assume a fairly
 * pessimal value.  It's a tradeoff between extra memory fetches (if we
 * set this value too high, the FIFO will fetch frequently to stay full)
 * and power consumption (set it too low to save power and we might see
 * FIFO underruns and display "flicker").
 *
 * A value of 5us seems to be a good balance; safe for very low end
 * platforms but not overly aggressive on lower latency configs.
 */
static const int latency_ns = 5000;

static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dsparb = I915_READ(DSPARB);
	int size;

	size = dsparb & 0x7f;
	if (plane)
		size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;

	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
		      plane ? "B" : "A", size);

	return size;
}

static int i85x_get_fifo_size(struct drm_device *dev, int plane)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dsparb = I915_READ(DSPARB);
	int size;

	size = dsparb & 0x1ff;
	if (plane)
		size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
	size >>= 1; /* Convert to cachelines */

	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
		      plane ? "B" : "A", size);

	return size;
}

static int i845_get_fifo_size(struct drm_device *dev, int plane)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dsparb = I915_READ(DSPARB);
	int size;

	size = dsparb & 0x7f;
	size >>= 2; /* Convert to cachelines */

	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
		      plane ? "B" : "A",
		      size);

	return size;
}

static int i830_get_fifo_size(struct drm_device *dev, int plane)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dsparb = I915_READ(DSPARB);
	int size;

	size = dsparb & 0x7f;
	size >>= 1; /* Convert to cachelines */

	DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
		      plane ? "B" : "A", size);

	return size;
}

static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
			       int planeb_clock, int sr_hdisplay, int unused,
			       int pixel_size)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	const struct cxsr_latency *latency;
	u32 reg;
	unsigned long wm;
	int sr_clock;

	latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
					 dev_priv->fsb_freq, dev_priv->mem_freq);
	if (!latency) {
		DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
		pineview_disable_cxsr(dev);
		return;
	}

	if (!planea_clock || !planeb_clock) {
		sr_clock = planea_clock ? planea_clock : planeb_clock;

		/* Display SR */
		wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
					pixel_size, latency->display_sr);
		reg = I915_READ(DSPFW1);
		reg &= ~DSPFW_SR_MASK;
		reg |= wm << DSPFW_SR_SHIFT;
		I915_WRITE(DSPFW1, reg);
		DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);

		/* cursor SR */
		wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
					pixel_size, latency->cursor_sr);
		reg = I915_READ(DSPFW3);
		reg &= ~DSPFW_CURSOR_SR_MASK;
		reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
		I915_WRITE(DSPFW3, reg);

		/* Display HPLL off SR */
		wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
					pixel_size, latency->display_hpll_disable);
		reg = I915_READ(DSPFW3);
		reg &= ~DSPFW_HPLL_SR_MASK;
		reg |= wm & DSPFW_HPLL_SR_MASK;
		I915_WRITE(DSPFW3, reg);

		/* cursor HPLL off SR */
		wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
					pixel_size, latency->cursor_hpll_disable);
		reg = I915_READ(DSPFW3);
		reg &= ~DSPFW_HPLL_CURSOR_MASK;
		reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
		I915_WRITE(DSPFW3, reg);
		DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);

		/* activate cxsr */
		I915_WRITE(DSPFW3,
			   I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
		DRM_DEBUG_KMS("Self-refresh is enabled\n");
	} else {
		pineview_disable_cxsr(dev);
		DRM_DEBUG_KMS("Self-refresh is disabled\n");
	}
}

static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
			  int planeb_clock, int sr_hdisplay, int sr_htotal,
			  int pixel_size)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int total_size, cacheline_size;
	int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
	struct intel_watermark_params planea_params, planeb_params;
	unsigned long line_time_us;
	int sr_clock, sr_entries = 0, entries_required;

	/* Create copies of the base settings for each pipe */
	planea_params = planeb_params = g4x_wm_info;

	/* Grab a couple of global values before we overwrite them */
	total_size = planea_params.fifo_size;
	cacheline_size = planea_params.cacheline_size;

	/*
	 * Note: we need to make sure we don't overflow for various clock &
	 * latency values.
	 * clocks go from a few thousand to several hundred thousand.
	 * latency is usually a few thousand
	 */
	entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
		1000;
	entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
	planea_wm = entries_required + planea_params.guard_size;

	entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
		1000;
	entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
	planeb_wm = entries_required + planeb_params.guard_size;

	cursora_wm = cursorb_wm = 16;
	cursor_sr = 32;

	DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);

	/* Calc sr entries for one plane configs */
	if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
		/* self-refresh has much higher latency */
		static const int sr_latency_ns = 12000;

		sr_clock = planea_clock ? planea_clock : planeb_clock;
		line_time_us = ((sr_htotal * 1000) / sr_clock);

		/* Use ns/us then divide to preserve precision */
		sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
			pixel_size * sr_hdisplay;
		sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);

		entries_required = (((sr_latency_ns / line_time_us) +
				     1000) / 1000) * pixel_size * 64;
		entries_required = DIV_ROUND_UP(entries_required,
						g4x_cursor_wm_info.cacheline_size);
		cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;

		if (cursor_sr > g4x_cursor_wm_info.max_wm)
			cursor_sr = g4x_cursor_wm_info.max_wm;
		DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
			      "cursor %d\n", sr_entries, cursor_sr);

		I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
	} else {
		/* Turn off self refresh if both pipes are enabled */
		I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
			   & ~FW_BLC_SELF_EN);
	}

	DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
		  planea_wm, planeb_wm, sr_entries);

	planea_wm &= 0x3f;
	planeb_wm &= 0x3f;

	I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
		   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
		   (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
	I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
		   (cursora_wm << DSPFW_CURSORA_SHIFT));
	/* HPLL off in SR has some issues on G4x... disable it */
	I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
		   (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
}

static void i965_update_wm(struct drm_device *dev, int planea_clock,
			   int planeb_clock, int sr_hdisplay, int sr_htotal,
			   int pixel_size)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long line_time_us;
	int sr_clock, sr_entries, srwm = 1;
	int cursor_sr = 16;

	/* Calc sr entries for one plane configs */
	if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
		/* self-refresh has much higher latency */
		static const int sr_latency_ns = 12000;

		sr_clock = planea_clock ? planea_clock : planeb_clock;
		line_time_us = ((sr_htotal * 1000) / sr_clock);

		/* Use ns/us then divide to preserve precision */
		sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
			pixel_size * sr_hdisplay;
		sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
		DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
		srwm = I965_FIFO_SIZE - sr_entries;
		if (srwm < 0)
			srwm = 1;
		srwm &= 0x1ff;

		sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
			pixel_size * 64;
		sr_entries = DIV_ROUND_UP(sr_entries,
					  i965_cursor_wm_info.cacheline_size);
		cursor_sr = i965_cursor_wm_info.fifo_size -
			(sr_entries + i965_cursor_wm_info.guard_size);

		if (cursor_sr > i965_cursor_wm_info.max_wm)
			cursor_sr = i965_cursor_wm_info.max_wm;

		DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
			      "cursor %d\n", srwm, cursor_sr);

		if (IS_CRESTLINE(dev))
			I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
	} else {
		/* Turn off self refresh if both pipes are enabled */
		if (IS_CRESTLINE(dev))
			I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
				   & ~FW_BLC_SELF_EN);
	}

	DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
		      srwm);

	/* 965 has limitations... */
	I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
		   (8 << 0));
	I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
	/* update cursor SR watermark */
	I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
}

static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
			   int planeb_clock, int sr_hdisplay, int sr_htotal,
			   int pixel_size)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t fwater_lo;
	uint32_t fwater_hi;
	int total_size, cacheline_size, cwm, srwm = 1;
	int planea_wm, planeb_wm;
	struct intel_watermark_params planea_params, planeb_params;
	unsigned long line_time_us;
	int sr_clock, sr_entries = 0;

	/* Create copies of the base settings for each pipe */
	if (IS_CRESTLINE(dev) || IS_I945GM(dev))
		planea_params = planeb_params = i945_wm_info;
	else if (!IS_GEN2(dev))
		planea_params = planeb_params = i915_wm_info;
	else
		planea_params = planeb_params = i855_wm_info;

	/* Grab a couple of global values before we overwrite them */
	total_size = planea_params.fifo_size;
	cacheline_size = planea_params.cacheline_size;

	/* Update per-plane FIFO sizes */
	planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
	planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);

	planea_wm = intel_calculate_wm(planea_clock, &planea_params,
				       pixel_size, latency_ns);
	planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
				       pixel_size, latency_ns);
	DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);

	/*
	 * Overlay gets an aggressive default since video jitter is bad.
	 */
	cwm = 2;

	/* Calc sr entries for one plane configs */
	if (HAS_FW_BLC(dev) && sr_hdisplay &&
	    (!planea_clock || !planeb_clock)) {
		/* self-refresh has much higher latency */
		static const int sr_latency_ns = 6000;

		sr_clock = planea_clock ? planea_clock : planeb_clock;
		line_time_us = ((sr_htotal * 1000) / sr_clock);

		/* Use ns/us then divide to preserve precision */
		sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
			pixel_size * sr_hdisplay;
		sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
		DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
		srwm = total_size - sr_entries;
		if (srwm < 0)
			srwm = 1;

		if (IS_I945G(dev) || IS_I945GM(dev))
			I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
		else if (IS_I915GM(dev)) {
			/* 915M has a smaller SRWM field */
			I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
			I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
		}
	} else {
		/* Turn off self refresh if both pipes are enabled */
		if (IS_I945G(dev) || IS_I945GM(dev)) {
			I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
				   & ~FW_BLC_SELF_EN);
		} else if (IS_I915GM(dev)) {
			I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
		}
	}

	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
		      planea_wm, planeb_wm, cwm, srwm);

	fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
	fwater_hi = (cwm & 0x1f);

	/* Set request length to 8 cachelines per fetch */
	fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
	fwater_hi = fwater_hi | (1 << 8);

	I915_WRITE(FW_BLC, fwater_lo);
	I915_WRITE(FW_BLC2, fwater_hi);
}

static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
			   int unused2, int unused3, int pixel_size)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
	int planea_wm;

	i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);

	planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
				       pixel_size, latency_ns);
	fwater_lo |= (3<<8) | planea_wm;

	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);

	I915_WRITE(FW_BLC, fwater_lo);
}

#define ILK_LP0_PLANE_LATENCY		700
#define ILK_LP0_CURSOR_LATENCY		1300

static bool ironlake_compute_wm0(struct drm_device *dev,
				 int pipe,
				 const struct intel_watermark_params *display,
				 int display_latency_ns,
				 const struct intel_watermark_params *cursor,
				 int cursor_latency_ns,
				 int *plane_wm,
				 int *cursor_wm)
{
	struct drm_crtc *crtc;
	int htotal, hdisplay, clock, pixel_size;
	int line_time_us, line_count;
	int entries, tlb_miss;

	crtc = intel_get_crtc_for_pipe(dev, pipe);
	if (crtc->fb == NULL || !crtc->enabled)
		return false;

	htotal = crtc->mode.htotal;
	hdisplay = crtc->mode.hdisplay;
	clock = crtc->mode.clock;
	pixel_size = crtc->fb->bits_per_pixel / 8;

	/* Use the small buffer method to calculate plane watermark */
	entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
	tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
	if (tlb_miss > 0)
		entries += tlb_miss;
	entries = DIV_ROUND_UP(entries, display->cacheline_size);
	*plane_wm = entries + display->guard_size;
	if (*plane_wm > (int)display->max_wm)
		*plane_wm = display->max_wm;

	/* Use the large buffer method to calculate cursor watermark */
	line_time_us = ((htotal * 1000) / clock);
	line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
	entries = line_count * 64 * pixel_size;
	tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
	if (tlb_miss > 0)
		entries += tlb_miss;
	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
	*cursor_wm = entries + cursor->guard_size;
	if (*cursor_wm > (int)cursor->max_wm)
		*cursor_wm = (int)cursor->max_wm;

	return true;
}

/*
 * Check the wm result.
 *
 * If any calculated watermark values is larger than the maximum value that
 * can be programmed into the associated watermark register, that watermark
 * must be disabled.
 */
static bool ironlake_check_srwm(struct drm_device *dev, int level,
				int fbc_wm, int display_wm, int cursor_wm,
				const struct intel_watermark_params *display,
				const struct intel_watermark_params *cursor)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
		      " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);

	if (fbc_wm > SNB_FBC_MAX_SRWM) {
		DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
			      fbc_wm, SNB_FBC_MAX_SRWM, level);

		/* fbc has it's own way to disable FBC WM */
		I915_WRITE(DISP_ARB_CTL,
			   I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
		return false;
	}

	if (display_wm > display->max_wm) {
		DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
			      display_wm, SNB_DISPLAY_MAX_SRWM, level);
		return false;
	}

	if (cursor_wm > cursor->max_wm) {
		DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
			      cursor_wm, SNB_CURSOR_MAX_SRWM, level);
		return false;
	}

	if (!(fbc_wm || display_wm || cursor_wm)) {
		DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
		return false;
	}

	return true;
}

/*
 * Compute watermark values of WM[1-3],
 */
static bool ironlake_compute_srwm(struct drm_device *dev, int level,
				  int hdisplay, int htotal,
				  int pixel_size, int clock, int latency_ns,
				  const struct intel_watermark_params *display,
				  const struct intel_watermark_params *cursor,
				  int *fbc_wm, int *display_wm, int *cursor_wm)
{

	unsigned long line_time_us;
	int line_count, line_size;
	int small, large;
	int entries;

	if (!latency_ns) {
		*fbc_wm = *display_wm = *cursor_wm = 0;
		return false;
	}

	line_time_us = (htotal * 1000) / clock;
	line_count = (latency_ns / line_time_us + 1000) / 1000;
	line_size = hdisplay * pixel_size;

	/* Use the minimum of the small and large buffer method for primary */
	small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
	large = line_count * line_size;

	entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
	*display_wm = entries + display->guard_size;

	/*
	 * Spec says:
	 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
	 */
	*fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;

	/* calculate the self-refresh watermark for display cursor */
	entries = line_count * pixel_size * 64;
	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
	*cursor_wm = entries + cursor->guard_size;

	return ironlake_check_srwm(dev, level,
				   *fbc_wm, *display_wm, *cursor_wm,
				   display, cursor);
}

static void ironlake_update_wm(struct drm_device *dev,
			       int planea_clock, int planeb_clock,
			       int hdisplay, int htotal,
			       int pixel_size)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int fbc_wm, plane_wm, cursor_wm, enabled;
	int clock;

	enabled = 0;
	if (ironlake_compute_wm0(dev, 0,
				 &ironlake_display_wm_info,
				 ILK_LP0_PLANE_LATENCY,
				 &ironlake_cursor_wm_info,
				 ILK_LP0_CURSOR_LATENCY,
				 &plane_wm, &cursor_wm)) {
		I915_WRITE(WM0_PIPEA_ILK,
			   (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
		DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
			      " plane %d, " "cursor: %d\n",
			      plane_wm, cursor_wm);
		enabled++;
	}

	if (ironlake_compute_wm0(dev, 1,
				 &ironlake_display_wm_info,
				 ILK_LP0_PLANE_LATENCY,
				 &ironlake_cursor_wm_info,
				 ILK_LP0_CURSOR_LATENCY,
				 &plane_wm, &cursor_wm)) {
		I915_WRITE(WM0_PIPEB_ILK,
			   (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
		DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
			      " plane %d, cursor: %d\n",
			      plane_wm, cursor_wm);
		enabled++;
	}

	/*
	 * Calculate and update the self-refresh watermark only when one
	 * display plane is used.
	 */
	I915_WRITE(WM3_LP_ILK, 0);
	I915_WRITE(WM2_LP_ILK, 0);
	I915_WRITE(WM1_LP_ILK, 0);

	if (enabled != 1)
		return;

	clock = planea_clock ? planea_clock : planeb_clock;

	/* WM1 */
	if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size,
				   clock, ILK_READ_WM1_LATENCY() * 500,
				   &ironlake_display_srwm_info,
				   &ironlake_cursor_srwm_info,
				   &fbc_wm, &plane_wm, &cursor_wm))
		return;

	I915_WRITE(WM1_LP_ILK,
		   WM1_LP_SR_EN |
		   (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
		   (fbc_wm << WM1_LP_FBC_SHIFT) |
		   (plane_wm << WM1_LP_SR_SHIFT) |
		   cursor_wm);

	/* WM2 */
	if (!ironlake_compute_srwm(dev, 2, hdisplay, htotal, pixel_size,
				   clock, ILK_READ_WM2_LATENCY() * 500,
				   &ironlake_display_srwm_info,
				   &ironlake_cursor_srwm_info,
				   &fbc_wm, &plane_wm, &cursor_wm))
		return;

	I915_WRITE(WM2_LP_ILK,
		   WM2_LP_EN |
		   (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
		   (fbc_wm << WM1_LP_FBC_SHIFT) |
		   (plane_wm << WM1_LP_SR_SHIFT) |
		   cursor_wm);

	/*
	 * WM3 is unsupported on ILK, probably because we don't have latency
	 * data for that power state
	 */
}

static void sandybridge_update_wm(struct drm_device *dev,
			       int planea_clock, int planeb_clock,
			       int hdisplay, int htotal,
			       int pixel_size)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int latency = SNB_READ_WM0_LATENCY() * 100;	/* In unit 0.1us */
	int fbc_wm, plane_wm, cursor_wm, enabled;
	int clock;

	enabled = 0;
	if (ironlake_compute_wm0(dev, 0,
				 &sandybridge_display_wm_info, latency,
				 &sandybridge_cursor_wm_info, latency,
				 &plane_wm, &cursor_wm)) {
		I915_WRITE(WM0_PIPEA_ILK,
			   (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
		DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
			      " plane %d, " "cursor: %d\n",
			      plane_wm, cursor_wm);
		enabled++;
	}

	if (ironlake_compute_wm0(dev, 1,
				 &sandybridge_display_wm_info, latency,
				 &sandybridge_cursor_wm_info, latency,
				 &plane_wm, &cursor_wm)) {
		I915_WRITE(WM0_PIPEB_ILK,
			   (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
		DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
			      " plane %d, cursor: %d\n",
			      plane_wm, cursor_wm);
		enabled++;
	}

	/*
	 * Calculate and update the self-refresh watermark only when one
	 * display plane is used.
	 *
	 * SNB support 3 levels of watermark.
	 *
	 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
	 * and disabled in the descending order
	 *
	 */
	I915_WRITE(WM3_LP_ILK, 0);
	I915_WRITE(WM2_LP_ILK, 0);
	I915_WRITE(WM1_LP_ILK, 0);

	if (enabled != 1)
		return;

	clock = planea_clock ? planea_clock : planeb_clock;

	/* WM1 */
	if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size,
				   clock, SNB_READ_WM1_LATENCY() * 500,
				   &sandybridge_display_srwm_info,
				   &sandybridge_cursor_srwm_info,
				   &fbc_wm, &plane_wm, &cursor_wm))
		return;

	I915_WRITE(WM1_LP_ILK,
		   WM1_LP_SR_EN |
		   (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
		   (fbc_wm << WM1_LP_FBC_SHIFT) |
		   (plane_wm << WM1_LP_SR_SHIFT) |
		   cursor_wm);

	/* WM2 */
	if (!ironlake_compute_srwm(dev, 2,
				   hdisplay, htotal, pixel_size,
				   clock, SNB_READ_WM2_LATENCY() * 500,
				   &sandybridge_display_srwm_info,
				   &sandybridge_cursor_srwm_info,
				   &fbc_wm, &plane_wm, &cursor_wm))
		return;

	I915_WRITE(WM2_LP_ILK,
		   WM2_LP_EN |
		   (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
		   (fbc_wm << WM1_LP_FBC_SHIFT) |
		   (plane_wm << WM1_LP_SR_SHIFT) |
		   cursor_wm);

	/* WM3 */
	if (!ironlake_compute_srwm(dev, 3,
				   hdisplay, htotal, pixel_size,
				   clock, SNB_READ_WM3_LATENCY() * 500,
				   &sandybridge_display_srwm_info,
				   &sandybridge_cursor_srwm_info,
				   &fbc_wm, &plane_wm, &cursor_wm))
		return;

	I915_WRITE(WM3_LP_ILK,
		   WM3_LP_EN |
		   (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
		   (fbc_wm << WM1_LP_FBC_SHIFT) |
		   (plane_wm << WM1_LP_SR_SHIFT) |
		   cursor_wm);
}

/**
 * intel_update_watermarks - update FIFO watermark values based on current modes
 *
 * Calculate watermark values for the various WM regs based on current mode
 * and plane configuration.
 *
 * There are several cases to deal with here:
 *   - normal (i.e. non-self-refresh)
 *   - self-refresh (SR) mode
 *   - lines are large relative to FIFO size (buffer can hold up to 2)
 *   - lines are small relative to FIFO size (buffer can hold more than 2
 *     lines), so need to account for TLB latency
 *
 *   The normal calculation is:
 *     watermark = dotclock * bytes per pixel * latency
 *   where latency is platform & configuration dependent (we assume pessimal
 *   values here).
 *
 *   The SR calculation is:
 *     watermark = (trunc(latency/line time)+1) * surface width *
 *       bytes per pixel
 *   where
 *     line time = htotal / dotclock
 *     surface width = hdisplay for normal plane and 64 for cursor
 *   and latency is assumed to be high, as above.
 *
 * The final value programmed to the register should always be rounded up,
 * and include an extra 2 entries to account for clock crossings.
 *
 * We don't use the sprite, so we can ignore that.  And on Crestline we have
 * to set the non-SR watermarks to 8.
 */
static void intel_update_watermarks(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	int sr_hdisplay = 0;
	unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
	int enabled = 0, pixel_size = 0;
	int sr_htotal = 0;

	if (!dev_priv->display.update_wm)
		return;

	/* Get the clock config from both planes */
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
		if (intel_crtc->active) {
			enabled++;
			if (intel_crtc->plane == 0) {
				DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
					      intel_crtc->pipe, crtc->mode.clock);
				planea_clock = crtc->mode.clock;
			} else {
				DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
					      intel_crtc->pipe, crtc->mode.clock);
				planeb_clock = crtc->mode.clock;
			}
			sr_hdisplay = crtc->mode.hdisplay;
			sr_clock = crtc->mode.clock;
			sr_htotal = crtc->mode.htotal;
			if (crtc->fb)
				pixel_size = crtc->fb->bits_per_pixel / 8;
			else
				pixel_size = 4; /* by default */
		}
	}

	if (enabled <= 0)
		return;

	dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
				    sr_hdisplay, sr_htotal, pixel_size);
}

static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
{
	return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
}

static int intel_crtc_mode_set(struct drm_crtc *crtc,
			       struct drm_display_mode *mode,
			       struct drm_display_mode *adjusted_mode,
			       int x, int y,
			       struct drm_framebuffer *old_fb)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	int plane = intel_crtc->plane;
	u32 fp_reg, dpll_reg;
	int refclk, num_connectors = 0;
	intel_clock_t clock, reduced_clock;
	u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
	bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
	bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
	struct intel_encoder *has_edp_encoder = NULL;
	struct drm_mode_config *mode_config = &dev->mode_config;
	struct intel_encoder *encoder;
	const intel_limit_t *limit;
	int ret;
	struct fdi_m_n m_n = {0};
	u32 reg, temp;
	int target_clock;

	drm_vblank_pre_modeset(dev, pipe);

	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
		if (encoder->base.crtc != crtc)
			continue;

		switch (encoder->type) {
		case INTEL_OUTPUT_LVDS:
			is_lvds = true;
			break;
		case INTEL_OUTPUT_SDVO:
		case INTEL_OUTPUT_HDMI:
			is_sdvo = true;
			if (encoder->needs_tv_clock)
				is_tv = true;
			break;
		case INTEL_OUTPUT_DVO:
			is_dvo = true;
			break;
		case INTEL_OUTPUT_TVOUT:
			is_tv = true;
			break;
		case INTEL_OUTPUT_ANALOG:
			is_crt = true;
			break;
		case INTEL_OUTPUT_DISPLAYPORT:
			is_dp = true;
			break;
		case INTEL_OUTPUT_EDP:
			has_edp_encoder = encoder;
			break;
		}

		num_connectors++;
	}

	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
		refclk = dev_priv->lvds_ssc_freq * 1000;
		DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
			      refclk / 1000);
	} else if (!IS_GEN2(dev)) {
		refclk = 96000;
		if (HAS_PCH_SPLIT(dev) &&
		    (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
			refclk = 120000; /* 120Mhz refclk */
	} else {
		refclk = 48000;
	}

	/*
	 * Returns a set of divisors for the desired target clock with the given
	 * refclk, or FALSE.  The returned values represent the clock equation:
	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
	 */
	limit = intel_limit(crtc, refclk);
	ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
	if (!ok) {
		DRM_ERROR("Couldn't find PLL settings for mode!\n");
		drm_vblank_post_modeset(dev, pipe);
		return -EINVAL;
	}

	/* Ensure that the cursor is valid for the new mode before changing... */
	intel_crtc_update_cursor(crtc, true);

	if (is_lvds && dev_priv->lvds_downclock_avail) {
		has_reduced_clock = limit->find_pll(limit, crtc,
						    dev_priv->lvds_downclock,
						    refclk,
						    &reduced_clock);
		if (has_reduced_clock && (clock.p != reduced_clock.p)) {
			/*
			 * If the different P is found, it means that we can't
			 * switch the display clock by using the FP0/FP1.
			 * In such case we will disable the LVDS downclock
			 * feature.
			 */
			DRM_DEBUG_KMS("Different P is found for "
				      "LVDS clock/downclock\n");
			has_reduced_clock = 0;
		}
	}
	/* SDVO TV has fixed PLL values depend on its clock range,
	   this mirrors vbios setting. */
	if (is_sdvo && is_tv) {
		if (adjusted_mode->clock >= 100000
		    && adjusted_mode->clock < 140500) {
			clock.p1 = 2;
			clock.p2 = 10;
			clock.n = 3;
			clock.m1 = 16;
			clock.m2 = 8;
		} else if (adjusted_mode->clock >= 140500
			   && adjusted_mode->clock <= 200000) {
			clock.p1 = 1;
			clock.p2 = 10;
			clock.n = 6;
			clock.m1 = 12;
			clock.m2 = 8;
		}
	}

	/* FDI link */
	if (HAS_PCH_SPLIT(dev)) {
		int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
		int lane = 0, link_bw, bpp;
		/* CPU eDP doesn't require FDI link, so just set DP M/N
		   according to current link config */
		if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
			target_clock = mode->clock;
			intel_edp_link_config(has_edp_encoder,
					      &lane, &link_bw);
		} else {
			/* [e]DP over FDI requires target mode clock
			   instead of link clock */
			if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
				target_clock = mode->clock;
			else
				target_clock = adjusted_mode->clock;

			/* FDI is a binary signal running at ~2.7GHz, encoding
			 * each output octet as 10 bits. The actual frequency
			 * is stored as a divider into a 100MHz clock, and the
			 * mode pixel clock is stored in units of 1KHz.
			 * Hence the bw of each lane in terms of the mode signal
			 * is:
			 */
			link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
		}

		/* determine panel color depth */
		temp = I915_READ(PIPECONF(pipe));
		temp &= ~PIPE_BPC_MASK;
		if (is_lvds) {
			/* the BPC will be 6 if it is 18-bit LVDS panel */
			if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
				temp |= PIPE_8BPC;
			else
				temp |= PIPE_6BPC;
		} else if (has_edp_encoder) {
			switch (dev_priv->edp.bpp/3) {
			case 8:
				temp |= PIPE_8BPC;
				break;
			case 10:
				temp |= PIPE_10BPC;
				break;
			case 6:
				temp |= PIPE_6BPC;
				break;
			case 12:
				temp |= PIPE_12BPC;
				break;
			}
		} else
			temp |= PIPE_8BPC;
		I915_WRITE(PIPECONF(pipe), temp);

		switch (temp & PIPE_BPC_MASK) {
		case PIPE_8BPC:
			bpp = 24;
			break;
		case PIPE_10BPC:
			bpp = 30;
			break;
		case PIPE_6BPC:
			bpp = 18;
			break;
		case PIPE_12BPC:
			bpp = 36;
			break;
		default:
			DRM_ERROR("unknown pipe bpc value\n");
			bpp = 24;
		}

		if (!lane) {
			/* 
			 * Account for spread spectrum to avoid
			 * oversubscribing the link. Max center spread
			 * is 2.5%; use 5% for safety's sake.
			 */
			u32 bps = target_clock * bpp * 21 / 20;
			lane = bps / (link_bw * 8) + 1;
		}

		intel_crtc->fdi_lanes = lane;

		if (pixel_multiplier > 1)
			link_bw *= pixel_multiplier;
		ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
	}

	/* Ironlake: try to setup display ref clock before DPLL
	 * enabling. This is only under driver's control after
	 * PCH B stepping, previous chipset stepping should be
	 * ignoring this setting.
	 */
	if (HAS_PCH_SPLIT(dev)) {
		temp = I915_READ(PCH_DREF_CONTROL);
		/* Always enable nonspread source */
		temp &= ~DREF_NONSPREAD_SOURCE_MASK;
		temp |= DREF_NONSPREAD_SOURCE_ENABLE;
		temp &= ~DREF_SSC_SOURCE_MASK;
		temp |= DREF_SSC_SOURCE_ENABLE;
		I915_WRITE(PCH_DREF_CONTROL, temp);

		POSTING_READ(PCH_DREF_CONTROL);
		udelay(200);

		if (has_edp_encoder) {
			if (intel_panel_use_ssc(dev_priv)) {
				temp |= DREF_SSC1_ENABLE;
				I915_WRITE(PCH_DREF_CONTROL, temp);

				POSTING_READ(PCH_DREF_CONTROL);
				udelay(200);
			}
			temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;

			/* Enable CPU source on CPU attached eDP */
			if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
				if (intel_panel_use_ssc(dev_priv))
					temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
				else
					temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
			} else {
				/* Enable SSC on PCH eDP if needed */
				if (intel_panel_use_ssc(dev_priv)) {
					DRM_ERROR("enabling SSC on PCH\n");
					temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
				}
			}
			I915_WRITE(PCH_DREF_CONTROL, temp);
			POSTING_READ(PCH_DREF_CONTROL);
			udelay(200);
		}
	}

	if (IS_PINEVIEW(dev)) {
		fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
		if (has_reduced_clock)
			fp2 = (1 << reduced_clock.n) << 16 |
				reduced_clock.m1 << 8 | reduced_clock.m2;
	} else {
		fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
		if (has_reduced_clock)
			fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
				reduced_clock.m2;
	}

	/* Enable autotuning of the PLL clock (if permissible) */
	if (HAS_PCH_SPLIT(dev)) {
		int factor = 21;

		if (is_lvds) {
			if ((intel_panel_use_ssc(dev_priv) &&
			     dev_priv->lvds_ssc_freq == 100) ||
			    (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
				factor = 25;
		} else if (is_sdvo && is_tv)
			factor = 20;

		if (clock.m1 < factor * clock.n)
			fp |= FP_CB_TUNE;
	}

	dpll = 0;
	if (!HAS_PCH_SPLIT(dev))
		dpll = DPLL_VGA_MODE_DIS;

	if (!IS_GEN2(dev)) {
		if (is_lvds)
			dpll |= DPLLB_MODE_LVDS;
		else
			dpll |= DPLLB_MODE_DAC_SERIAL;
		if (is_sdvo) {
			int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
			if (pixel_multiplier > 1) {
				if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
					dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
				else if (HAS_PCH_SPLIT(dev))
					dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
			}
			dpll |= DPLL_DVO_HIGH_SPEED;
		}
		if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
			dpll |= DPLL_DVO_HIGH_SPEED;

		/* compute bitmask from p1 value */
		if (IS_PINEVIEW(dev))
			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
		else {
			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
			/* also FPA1 */
			if (HAS_PCH_SPLIT(dev))
				dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
			if (IS_G4X(dev) && has_reduced_clock)
				dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
		}
		switch (clock.p2) {
		case 5:
			dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
			break;
		case 7:
			dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
			break;
		case 10:
			dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
			break;
		case 14:
			dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
			break;
		}
		if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
			dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
	} else {
		if (is_lvds) {
			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
		} else {
			if (clock.p1 == 2)
				dpll |= PLL_P1_DIVIDE_BY_TWO;
			else
				dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
			if (clock.p2 == 4)
				dpll |= PLL_P2_DIVIDE_BY_4;
		}
	}

	if (is_sdvo && is_tv)
		dpll |= PLL_REF_INPUT_TVCLKINBC;
	else if (is_tv)
		/* XXX: just matching BIOS for now */
		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
		dpll |= 3;
	else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
	else
		dpll |= PLL_REF_INPUT_DREFCLK;

	/* setup pipeconf */
	pipeconf = I915_READ(PIPECONF(pipe));

	/* Set up the display plane register */
	dspcntr = DISPPLANE_GAMMA_ENABLE;

	/* Ironlake's plane is forced to pipe, bit 24 is to
	   enable color space conversion */
	if (!HAS_PCH_SPLIT(dev)) {
		if (pipe == 0)
			dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
		else
			dspcntr |= DISPPLANE_SEL_PIPE_B;
	}

	if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
		/* Enable pixel doubling when the dot clock is > 90% of the (display)
		 * core speed.
		 *
		 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
		 * pipe == 0 check?
		 */
		if (mode->clock >
		    dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
			pipeconf |= PIPECONF_DOUBLE_WIDE;
		else
			pipeconf &= ~PIPECONF_DOUBLE_WIDE;
	}

	dspcntr |= DISPLAY_PLANE_ENABLE;
	pipeconf |= PIPECONF_ENABLE;
	dpll |= DPLL_VCO_ENABLE;

	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
	drm_mode_debug_printmodeline(mode);

	/* assign to Ironlake registers */
	if (HAS_PCH_SPLIT(dev)) {
		fp_reg = PCH_FP0(pipe);
		dpll_reg = PCH_DPLL(pipe);
	} else {
		fp_reg = FP0(pipe);
		dpll_reg = DPLL(pipe);
	}

	/* PCH eDP needs FDI, but CPU eDP does not */
	if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
		I915_WRITE(fp_reg, fp);
		I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);

		POSTING_READ(dpll_reg);
		udelay(150);
	}

	/* enable transcoder DPLL */
	if (HAS_PCH_CPT(dev)) {
		temp = I915_READ(PCH_DPLL_SEL);
		if (pipe == 0)
			temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
		else
			temp |=	TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
		I915_WRITE(PCH_DPLL_SEL, temp);

		POSTING_READ(PCH_DPLL_SEL);
		udelay(150);
	}

	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
	 * This is an exception to the general rule that mode_set doesn't turn
	 * things on.
	 */
	if (is_lvds) {
		reg = LVDS;
		if (HAS_PCH_SPLIT(dev))
			reg = PCH_LVDS;

		temp = I915_READ(reg);
		temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
		if (pipe == 1) {
			if (HAS_PCH_CPT(dev))
				temp |= PORT_TRANS_B_SEL_CPT;
			else
				temp |= LVDS_PIPEB_SELECT;
		} else {
			if (HAS_PCH_CPT(dev))
				temp &= ~PORT_TRANS_SEL_MASK;
			else
				temp &= ~LVDS_PIPEB_SELECT;
		}
		/* set the corresponsding LVDS_BORDER bit */
		temp |= dev_priv->lvds_border_bits;
		/* Set the B0-B3 data pairs corresponding to whether we're going to
		 * set the DPLLs for dual-channel mode or not.
		 */
		if (clock.p2 == 7)
			temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
		else
			temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);

		/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
		 * appropriately here, but we need to look more thoroughly into how
		 * panels behave in the two modes.
		 */
		/* set the dithering flag on non-PCH LVDS as needed */
		if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
			if (dev_priv->lvds_dither)
				temp |= LVDS_ENABLE_DITHER;
			else
				temp &= ~LVDS_ENABLE_DITHER;
		}
		I915_WRITE(reg, temp);
	}

	/* set the dithering flag and clear for anything other than a panel. */
	if (HAS_PCH_SPLIT(dev)) {
		pipeconf &= ~PIPECONF_DITHER_EN;
		pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
		if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
			pipeconf |= PIPECONF_DITHER_EN;
			pipeconf |= PIPECONF_DITHER_TYPE_ST1;
		}
	}

	if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
		intel_dp_set_m_n(crtc, mode, adjusted_mode);
	} else if (HAS_PCH_SPLIT(dev)) {
		/* For non-DP output, clear any trans DP clock recovery setting.*/
		if (pipe == 0) {
			I915_WRITE(TRANSA_DATA_M1, 0);
			I915_WRITE(TRANSA_DATA_N1, 0);
			I915_WRITE(TRANSA_DP_LINK_M1, 0);
			I915_WRITE(TRANSA_DP_LINK_N1, 0);
		} else {
			I915_WRITE(TRANSB_DATA_M1, 0);
			I915_WRITE(TRANSB_DATA_N1, 0);
			I915_WRITE(TRANSB_DP_LINK_M1, 0);
			I915_WRITE(TRANSB_DP_LINK_N1, 0);
		}
	}

	if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
		I915_WRITE(dpll_reg, dpll);

		/* Wait for the clocks to stabilize. */
		POSTING_READ(dpll_reg);
		udelay(150);

		if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
			temp = 0;
			if (is_sdvo) {
				temp = intel_mode_get_pixel_multiplier(adjusted_mode);
				if (temp > 1)
					temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
				else
					temp = 0;
			}
			I915_WRITE(DPLL_MD(pipe), temp);
		} else {
			/* The pixel multiplier can only be updated once the
			 * DPLL is enabled and the clocks are stable.
			 *
			 * So write it again.
			 */
			I915_WRITE(dpll_reg, dpll);
		}
	}

	intel_crtc->lowfreq_avail = false;
	if (is_lvds && has_reduced_clock && i915_powersave) {
		I915_WRITE(fp_reg + 4, fp2);
		intel_crtc->lowfreq_avail = true;
		if (HAS_PIPE_CXSR(dev)) {
			DRM_DEBUG_KMS("enabling CxSR downclocking\n");
			pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
		}
	} else {
		I915_WRITE(fp_reg + 4, fp);
		if (HAS_PIPE_CXSR(dev)) {
			DRM_DEBUG_KMS("disabling CxSR downclocking\n");
			pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
		}
	}

	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
		pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
		/* the chip adds 2 halflines automatically */
		adjusted_mode->crtc_vdisplay -= 1;
		adjusted_mode->crtc_vtotal -= 1;
		adjusted_mode->crtc_vblank_start -= 1;
		adjusted_mode->crtc_vblank_end -= 1;
		adjusted_mode->crtc_vsync_end -= 1;
		adjusted_mode->crtc_vsync_start -= 1;
	} else
		pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */

	I915_WRITE(HTOTAL(pipe),
		   (adjusted_mode->crtc_hdisplay - 1) |
		   ((adjusted_mode->crtc_htotal - 1) << 16));
	I915_WRITE(HBLANK(pipe),
		   (adjusted_mode->crtc_hblank_start - 1) |
		   ((adjusted_mode->crtc_hblank_end - 1) << 16));
	I915_WRITE(HSYNC(pipe),
		   (adjusted_mode->crtc_hsync_start - 1) |
		   ((adjusted_mode->crtc_hsync_end - 1) << 16));

	I915_WRITE(VTOTAL(pipe),
		   (adjusted_mode->crtc_vdisplay - 1) |
		   ((adjusted_mode->crtc_vtotal - 1) << 16));
	I915_WRITE(VBLANK(pipe),
		   (adjusted_mode->crtc_vblank_start - 1) |
		   ((adjusted_mode->crtc_vblank_end - 1) << 16));
	I915_WRITE(VSYNC(pipe),
		   (adjusted_mode->crtc_vsync_start - 1) |
		   ((adjusted_mode->crtc_vsync_end - 1) << 16));

	/* pipesrc and dspsize control the size that is scaled from,
	 * which should always be the user's requested size.
	 */
	if (!HAS_PCH_SPLIT(dev)) {
		I915_WRITE(DSPSIZE(plane),
			   ((mode->vdisplay - 1) << 16) |
			   (mode->hdisplay - 1));
		I915_WRITE(DSPPOS(plane), 0);
	}
	I915_WRITE(PIPESRC(pipe),
		   ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));

	if (HAS_PCH_SPLIT(dev)) {
		I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
		I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
		I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
		I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);

		if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
			ironlake_set_pll_edp(crtc, adjusted_mode->clock);
		}
	}

	I915_WRITE(PIPECONF(pipe), pipeconf);
	POSTING_READ(PIPECONF(pipe));

	intel_wait_for_vblank(dev, pipe);

	if (IS_GEN5(dev)) {
		/* enable address swizzle for tiling buffer */
		temp = I915_READ(DISP_ARB_CTL);
		I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
	}

	I915_WRITE(DSPCNTR(plane), dspcntr);

	ret = intel_pipe_set_base(crtc, x, y, old_fb);

	intel_update_watermarks(dev);

	drm_vblank_post_modeset(dev, pipe);

	return ret;
}

/** Loads the palette/gamma unit for the CRTC with the prepared values */
void intel_crtc_load_lut(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
	int i;

	/* The clocks have to be on to load the palette. */
	if (!crtc->enabled)
		return;

	/* use legacy palette for Ironlake */
	if (HAS_PCH_SPLIT(dev))
		palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
						   LGC_PALETTE_B;

	for (i = 0; i < 256; i++) {
		I915_WRITE(palreg + 4 * i,
			   (intel_crtc->lut_r[i] << 16) |
			   (intel_crtc->lut_g[i] << 8) |
			   intel_crtc->lut_b[i]);
	}
}

static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	bool visible = base != 0;
	u32 cntl;

	if (intel_crtc->cursor_visible == visible)
		return;

	cntl = I915_READ(CURACNTR);
	if (visible) {
		/* On these chipsets we can only modify the base whilst
		 * the cursor is disabled.
		 */
		I915_WRITE(CURABASE, base);

		cntl &= ~(CURSOR_FORMAT_MASK);
		/* XXX width must be 64, stride 256 => 0x00 << 28 */
		cntl |= CURSOR_ENABLE |
			CURSOR_GAMMA_ENABLE |
			CURSOR_FORMAT_ARGB;
	} else
		cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
	I915_WRITE(CURACNTR, cntl);

	intel_crtc->cursor_visible = visible;
}

static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	bool visible = base != 0;

	if (intel_crtc->cursor_visible != visible) {
		uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
		if (base) {
			cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
			cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
			cntl |= pipe << 28; /* Connect to correct pipe */
		} else {
			cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
			cntl |= CURSOR_MODE_DISABLE;
		}
		I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);

		intel_crtc->cursor_visible = visible;
	}
	/* and commit changes on next vblank */
	I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
}

/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
static void intel_crtc_update_cursor(struct drm_crtc *crtc,
				     bool on)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	int x = intel_crtc->cursor_x;
	int y = intel_crtc->cursor_y;
	u32 base, pos;
	bool visible;

	pos = 0;

	if (on && crtc->enabled && crtc->fb) {
		base = intel_crtc->cursor_addr;
		if (x > (int) crtc->fb->width)
			base = 0;

		if (y > (int) crtc->fb->height)
			base = 0;
	} else
		base = 0;

	if (x < 0) {
		if (x + intel_crtc->cursor_width < 0)
			base = 0;

		pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
		x = -x;
	}
	pos |= x << CURSOR_X_SHIFT;

	if (y < 0) {
		if (y + intel_crtc->cursor_height < 0)
			base = 0;

		pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
		y = -y;
	}
	pos |= y << CURSOR_Y_SHIFT;

	visible = base != 0;
	if (!visible && !intel_crtc->cursor_visible)
		return;

	I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
	if (IS_845G(dev) || IS_I865G(dev))
		i845_update_cursor(crtc, base);
	else
		i9xx_update_cursor(crtc, base);

	if (visible)
		intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
}

static int intel_crtc_cursor_set(struct drm_crtc *crtc,
				 struct drm_file *file,
				 uint32_t handle,
				 uint32_t width, uint32_t height)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct drm_i915_gem_object *obj;
	uint32_t addr;
	int ret;

	DRM_DEBUG_KMS("\n");

	/* if we want to turn off the cursor ignore width and height */
	if (!handle) {
		DRM_DEBUG_KMS("cursor off\n");
		addr = 0;
		obj = NULL;
		mutex_lock(&dev->struct_mutex);
		goto finish;
	}

	/* Currently we only support 64x64 cursors */
	if (width != 64 || height != 64) {
		DRM_ERROR("we currently only support 64x64 cursors\n");
		return -EINVAL;
	}

	obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
	if (!obj)
		return -ENOENT;

	if (obj->base.size < width * height * 4) {
		DRM_ERROR("buffer is to small\n");
		ret = -ENOMEM;
		goto fail;
	}

	/* we only need to pin inside GTT if cursor is non-phy */
	mutex_lock(&dev->struct_mutex);
	if (!dev_priv->info->cursor_needs_physical) {
		if (obj->tiling_mode) {
			DRM_ERROR("cursor cannot be tiled\n");
			ret = -EINVAL;
			goto fail_locked;
		}

		ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
		if (ret) {
			DRM_ERROR("failed to pin cursor bo\n");
			goto fail_locked;
		}

		ret = i915_gem_object_set_to_gtt_domain(obj, 0);
		if (ret) {
			DRM_ERROR("failed to move cursor bo into the GTT\n");
			goto fail_unpin;
		}

		ret = i915_gem_object_put_fence(obj);
		if (ret) {
			DRM_ERROR("failed to move cursor bo into the GTT\n");
			goto fail_unpin;
		}

		addr = obj->gtt_offset;
	} else {
		int align = IS_I830(dev) ? 16 * 1024 : 256;
		ret = i915_gem_attach_phys_object(dev, obj,
						  (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
						  align);
		if (ret) {
			DRM_ERROR("failed to attach phys object\n");
			goto fail_locked;
		}
		addr = obj->phys_obj->handle->busaddr;
	}

	if (IS_GEN2(dev))
		I915_WRITE(CURSIZE, (height << 12) | width);

 finish:
	if (intel_crtc->cursor_bo) {
		if (dev_priv->info->cursor_needs_physical) {
			if (intel_crtc->cursor_bo != obj)
				i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
		} else
			i915_gem_object_unpin(intel_crtc->cursor_bo);
		drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
	}

	mutex_unlock(&dev->struct_mutex);

	intel_crtc->cursor_addr = addr;
	intel_crtc->cursor_bo = obj;
	intel_crtc->cursor_width = width;
	intel_crtc->cursor_height = height;

	intel_crtc_update_cursor(crtc, true);

	return 0;
fail_unpin:
	i915_gem_object_unpin(obj);
fail_locked:
	mutex_unlock(&dev->struct_mutex);
fail:
	drm_gem_object_unreference_unlocked(&obj->base);
	return ret;
}

static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	intel_crtc->cursor_x = x;
	intel_crtc->cursor_y = y;

	intel_crtc_update_cursor(crtc, true);

	return 0;
}

/** Sets the color ramps on behalf of RandR */
void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
				 u16 blue, int regno)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	intel_crtc->lut_r[regno] = red >> 8;
	intel_crtc->lut_g[regno] = green >> 8;
	intel_crtc->lut_b[regno] = blue >> 8;
}

void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
			     u16 *blue, int regno)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	*red = intel_crtc->lut_r[regno] << 8;
	*green = intel_crtc->lut_g[regno] << 8;
	*blue = intel_crtc->lut_b[regno] << 8;
}

static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
				 u16 *blue, uint32_t start, uint32_t size)
{
	int end = (start + size > 256) ? 256 : start + size, i;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	for (i = start; i < end; i++) {
		intel_crtc->lut_r[i] = red[i] >> 8;
		intel_crtc->lut_g[i] = green[i] >> 8;
		intel_crtc->lut_b[i] = blue[i] >> 8;
	}

	intel_crtc_load_lut(crtc);
}

/**
 * Get a pipe with a simple mode set on it for doing load-based monitor
 * detection.
 *
 * It will be up to the load-detect code to adjust the pipe as appropriate for
 * its requirements.  The pipe will be connected to no other encoders.
 *
 * Currently this code will only succeed if there is a pipe with no encoders
 * configured for it.  In the future, it could choose to temporarily disable
 * some outputs to free up a pipe for its use.
 *
 * \return crtc, or NULL if no pipes are available.
 */

/* VESA 640x480x72Hz mode to set on the pipe */
static struct drm_display_mode load_detect_mode = {
	DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
		 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
};

struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
					    struct drm_connector *connector,
					    struct drm_display_mode *mode,
					    int *dpms_mode)
{
	struct intel_crtc *intel_crtc;
	struct drm_crtc *possible_crtc;
	struct drm_crtc *supported_crtc =NULL;
	struct drm_encoder *encoder = &intel_encoder->base;
	struct drm_crtc *crtc = NULL;
	struct drm_device *dev = encoder->dev;
	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
	struct drm_crtc_helper_funcs *crtc_funcs;
	int i = -1;

	/*
	 * Algorithm gets a little messy:
	 *   - if the connector already has an assigned crtc, use it (but make
	 *     sure it's on first)
	 *   - try to find the first unused crtc that can drive this connector,
	 *     and use that if we find one
	 *   - if there are no unused crtcs available, try to use the first
	 *     one we found that supports the connector
	 */

	/* See if we already have a CRTC for this connector */
	if (encoder->crtc) {
		crtc = encoder->crtc;
		/* Make sure the crtc and connector are running */
		intel_crtc = to_intel_crtc(crtc);
		*dpms_mode = intel_crtc->dpms_mode;
		if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
			crtc_funcs = crtc->helper_private;
			crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
			encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
		}
		return crtc;
	}

	/* Find an unused one (if possible) */
	list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
		i++;
		if (!(encoder->possible_crtcs & (1 << i)))
			continue;
		if (!possible_crtc->enabled) {
			crtc = possible_crtc;
			break;
		}
		if (!supported_crtc)
			supported_crtc = possible_crtc;
	}

	/*
	 * If we didn't find an unused CRTC, don't use any.
	 */
	if (!crtc) {
		return NULL;
	}

	encoder->crtc = crtc;
	connector->encoder = encoder;
	intel_encoder->load_detect_temp = true;

	intel_crtc = to_intel_crtc(crtc);
	*dpms_mode = intel_crtc->dpms_mode;

	if (!crtc->enabled) {
		if (!mode)
			mode = &load_detect_mode;
		drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
	} else {
		if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
			crtc_funcs = crtc->helper_private;
			crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
		}

		/* Add this connector to the crtc */
		encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
		encoder_funcs->commit(encoder);
	}
	/* let the connector get through one full cycle before testing */
	intel_wait_for_vblank(dev, intel_crtc->pipe);

	return crtc;
}

void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
				    struct drm_connector *connector, int dpms_mode)
{
	struct drm_encoder *encoder = &intel_encoder->base;
	struct drm_device *dev = encoder->dev;
	struct drm_crtc *crtc = encoder->crtc;
	struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
	struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;

	if (intel_encoder->load_detect_temp) {
		encoder->crtc = NULL;
		connector->encoder = NULL;
		intel_encoder->load_detect_temp = false;
		crtc->enabled = drm_helper_crtc_in_use(crtc);
		drm_helper_disable_unused_functions(dev);
	}

	/* Switch crtc and encoder back off if necessary */
	if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
		if (encoder->crtc == crtc)
			encoder_funcs->dpms(encoder, dpms_mode);
		crtc_funcs->dpms(crtc, dpms_mode);
	}
}

/* Returns the clock of the currently programmed mode of the given pipe. */
static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
	u32 fp;
	intel_clock_t clock;

	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
		fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
	else
		fp = I915_READ((pipe == 0) ? FPA1 : FPB1);

	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
	if (IS_PINEVIEW(dev)) {
		clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
		clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
	} else {
		clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
		clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
	}

	if (!IS_GEN2(dev)) {
		if (IS_PINEVIEW(dev))
			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
				DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
		else
			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
			       DPLL_FPA01_P1_POST_DIV_SHIFT);

		switch (dpll & DPLL_MODE_MASK) {
		case DPLLB_MODE_DAC_SERIAL:
			clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
				5 : 10;
			break;
		case DPLLB_MODE_LVDS:
			clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
				7 : 14;
			break;
		default:
			DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
				  "mode\n", (int)(dpll & DPLL_MODE_MASK));
			return 0;
		}

		/* XXX: Handle the 100Mhz refclk */
		intel_clock(dev, 96000, &clock);
	} else {
		bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);

		if (is_lvds) {
			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
				       DPLL_FPA01_P1_POST_DIV_SHIFT);
			clock.p2 = 14;

			if ((dpll & PLL_REF_INPUT_MASK) ==
			    PLLB_REF_INPUT_SPREADSPECTRUMIN) {
				/* XXX: might not be 66MHz */
				intel_clock(dev, 66000, &clock);
			} else
				intel_clock(dev, 48000, &clock);
		} else {
			if (dpll & PLL_P1_DIVIDE_BY_TWO)
				clock.p1 = 2;
			else {
				clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
					    DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
			}
			if (dpll & PLL_P2_DIVIDE_BY_4)
				clock.p2 = 4;
			else
				clock.p2 = 2;

			intel_clock(dev, 48000, &clock);
		}
	}

	/* XXX: It would be nice to validate the clocks, but we can't reuse
	 * i830PllIsValid() because it relies on the xf86_config connector
	 * configuration being accurate, which it isn't necessarily.
	 */

	return clock.dot;
}

/** Returns the currently programmed mode of the given pipe. */
struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
					     struct drm_crtc *crtc)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	struct drm_display_mode *mode;
	int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
	int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
	int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
	int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);

	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
	if (!mode)
		return NULL;

	mode->clock = intel_crtc_clock_get(dev, crtc);
	mode->hdisplay = (htot & 0xffff) + 1;
	mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
	mode->hsync_start = (hsync & 0xffff) + 1;
	mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
	mode->vdisplay = (vtot & 0xffff) + 1;
	mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
	mode->vsync_start = (vsync & 0xffff) + 1;
	mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;

	drm_mode_set_name(mode);
	drm_mode_set_crtcinfo(mode, 0);

	return mode;
}

#define GPU_IDLE_TIMEOUT 500 /* ms */

/* When this timer fires, we've been idle for awhile */
static void intel_gpu_idle_timer(unsigned long arg)
{
	struct drm_device *dev = (struct drm_device *)arg;
	drm_i915_private_t *dev_priv = dev->dev_private;

	if (!list_empty(&dev_priv->mm.active_list)) {
		/* Still processing requests, so just re-arm the timer. */
		mod_timer(&dev_priv->idle_timer, jiffies +
			  msecs_to_jiffies(GPU_IDLE_TIMEOUT));
		return;
	}

	dev_priv->busy = false;
	queue_work(dev_priv->wq, &dev_priv->idle_work);
}

#define CRTC_IDLE_TIMEOUT 1000 /* ms */

static void intel_crtc_idle_timer(unsigned long arg)
{
	struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
	struct drm_crtc *crtc = &intel_crtc->base;
	drm_i915_private_t *dev_priv = crtc->dev->dev_private;
	struct intel_framebuffer *intel_fb;

	intel_fb = to_intel_framebuffer(crtc->fb);
	if (intel_fb && intel_fb->obj->active) {
		/* The framebuffer is still being accessed by the GPU. */
		mod_timer(&intel_crtc->idle_timer, jiffies +
			  msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
		return;
	}

	intel_crtc->busy = false;
	queue_work(dev_priv->wq, &dev_priv->idle_work);
}

static void intel_increase_pllclock(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	int dpll_reg = DPLL(pipe);
	int dpll;

	if (HAS_PCH_SPLIT(dev))
		return;

	if (!dev_priv->lvds_downclock_avail)
		return;

	dpll = I915_READ(dpll_reg);
	if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
		DRM_DEBUG_DRIVER("upclocking LVDS\n");

		/* Unlock panel regs */
		I915_WRITE(PP_CONTROL,
			   I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);

		dpll &= ~DISPLAY_RATE_SELECT_FPA1;
		I915_WRITE(dpll_reg, dpll);
		POSTING_READ(dpll_reg);
		intel_wait_for_vblank(dev, pipe);

		dpll = I915_READ(dpll_reg);
		if (dpll & DISPLAY_RATE_SELECT_FPA1)
			DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");

		/* ...and lock them again */
		I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
	}

	/* Schedule downclock */
	mod_timer(&intel_crtc->idle_timer, jiffies +
		  msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
}

static void intel_decrease_pllclock(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int pipe = intel_crtc->pipe;
	int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
	int dpll = I915_READ(dpll_reg);

	if (HAS_PCH_SPLIT(dev))
		return;

	if (!dev_priv->lvds_downclock_avail)
		return;

	/*
	 * Since this is called by a timer, we should never get here in
	 * the manual case.
	 */
	if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
		DRM_DEBUG_DRIVER("downclocking LVDS\n");

		/* Unlock panel regs */
		I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
			   PANEL_UNLOCK_REGS);

		dpll |= DISPLAY_RATE_SELECT_FPA1;
		I915_WRITE(dpll_reg, dpll);
		dpll = I915_READ(dpll_reg);
		intel_wait_for_vblank(dev, pipe);
		dpll = I915_READ(dpll_reg);
		if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
			DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");

		/* ...and lock them again */
		I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
	}

}

/**
 * intel_idle_update - adjust clocks for idleness
 * @work: work struct
 *
 * Either the GPU or display (or both) went idle.  Check the busy status
 * here and adjust the CRTC and GPU clocks as necessary.
 */
static void intel_idle_update(struct work_struct *work)
{
	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
						    idle_work);
	struct drm_device *dev = dev_priv->dev;
	struct drm_crtc *crtc;
	struct intel_crtc *intel_crtc;
	int enabled = 0;

	if (!i915_powersave)
		return;

	mutex_lock(&dev->struct_mutex);

	i915_update_gfx_val(dev_priv);

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		/* Skip inactive CRTCs */
		if (!crtc->fb)
			continue;

		enabled++;
		intel_crtc = to_intel_crtc(crtc);
		if (!intel_crtc->busy)
			intel_decrease_pllclock(crtc);
	}

	if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
		DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
		I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
	}

	mutex_unlock(&dev->struct_mutex);
}

/**
 * intel_mark_busy - mark the GPU and possibly the display busy
 * @dev: drm device
 * @obj: object we're operating on
 *
 * Callers can use this function to indicate that the GPU is busy processing
 * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
 * buffer), we'll also mark the display as busy, so we know to increase its
 * clock frequency.
 */
void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = NULL;
	struct intel_framebuffer *intel_fb;
	struct intel_crtc *intel_crtc;

	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		return;

	if (!dev_priv->busy) {
		if (IS_I945G(dev) || IS_I945GM(dev)) {
			u32 fw_blc_self;

			DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
			fw_blc_self = I915_READ(FW_BLC_SELF);
			fw_blc_self &= ~FW_BLC_SELF_EN;
			I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
		}
		dev_priv->busy = true;
	} else
		mod_timer(&dev_priv->idle_timer, jiffies +
			  msecs_to_jiffies(GPU_IDLE_TIMEOUT));

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		if (!crtc->fb)
			continue;

		intel_crtc = to_intel_crtc(crtc);
		intel_fb = to_intel_framebuffer(crtc->fb);
		if (intel_fb->obj == obj) {
			if (!intel_crtc->busy) {
				if (IS_I945G(dev) || IS_I945GM(dev)) {
					u32 fw_blc_self;

					DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
					fw_blc_self = I915_READ(FW_BLC_SELF);
					fw_blc_self &= ~FW_BLC_SELF_EN;
					I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
				}
				/* Non-busy -> busy, upclock */
				intel_increase_pllclock(crtc);
				intel_crtc->busy = true;
			} else {
				/* Busy -> busy, put off timer */
				mod_timer(&intel_crtc->idle_timer, jiffies +
					  msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
			}
		}
	}
}

static void intel_crtc_destroy(struct drm_crtc *crtc)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct intel_unpin_work *work;
	unsigned long flags;

	spin_lock_irqsave(&dev->event_lock, flags);
	work = intel_crtc->unpin_work;
	intel_crtc->unpin_work = NULL;
	spin_unlock_irqrestore(&dev->event_lock, flags);

	if (work) {
		cancel_work_sync(&work->work);
		kfree(work);
	}

	drm_crtc_cleanup(crtc);

	kfree(intel_crtc);
}

static void intel_unpin_work_fn(struct work_struct *__work)
{
	struct intel_unpin_work *work =
		container_of(__work, struct intel_unpin_work, work);

	mutex_lock(&work->dev->struct_mutex);
	i915_gem_object_unpin(work->old_fb_obj);
	drm_gem_object_unreference(&work->pending_flip_obj->base);
	drm_gem_object_unreference(&work->old_fb_obj->base);

	mutex_unlock(&work->dev->struct_mutex);
	kfree(work);
}

static void do_intel_finish_page_flip(struct drm_device *dev,
				      struct drm_crtc *crtc)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_unpin_work *work;
	struct drm_i915_gem_object *obj;
	struct drm_pending_vblank_event *e;
	struct timeval tnow, tvbl;
	unsigned long flags;

	/* Ignore early vblank irqs */
	if (intel_crtc == NULL)
		return;

	do_gettimeofday(&tnow);

	spin_lock_irqsave(&dev->event_lock, flags);
	work = intel_crtc->unpin_work;
	if (work == NULL || !work->pending) {
		spin_unlock_irqrestore(&dev->event_lock, flags);
		return;
	}

	intel_crtc->unpin_work = NULL;

	if (work->event) {
		e = work->event;
		e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);

		/* Called before vblank count and timestamps have
		 * been updated for the vblank interval of flip
		 * completion? Need to increment vblank count and
		 * add one videorefresh duration to returned timestamp
		 * to account for this. We assume this happened if we
		 * get called over 0.9 frame durations after the last
		 * timestamped vblank.
		 *
		 * This calculation can not be used with vrefresh rates
		 * below 5Hz (10Hz to be on the safe side) without
		 * promoting to 64 integers.
		 */
		if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
		    9 * crtc->framedur_ns) {
			e->event.sequence++;
			tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
					     crtc->framedur_ns);
		}

		e->event.tv_sec = tvbl.tv_sec;
		e->event.tv_usec = tvbl.tv_usec;

		list_add_tail(&e->base.link,
			      &e->base.file_priv->event_list);
		wake_up_interruptible(&e->base.file_priv->event_wait);
	}

	drm_vblank_put(dev, intel_crtc->pipe);

	spin_unlock_irqrestore(&dev->event_lock, flags);

	obj = work->old_fb_obj;

	atomic_clear_mask(1 << intel_crtc->plane,
			  &obj->pending_flip.counter);
	if (atomic_read(&obj->pending_flip) == 0)
		wake_up(&dev_priv->pending_flip_queue);

	schedule_work(&work->work);

	trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
}

void intel_finish_page_flip(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];

	do_intel_finish_page_flip(dev, crtc);
}

void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];

	do_intel_finish_page_flip(dev, crtc);
}

void intel_prepare_page_flip(struct drm_device *dev, int plane)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
	unsigned long flags;

	spin_lock_irqsave(&dev->event_lock, flags);
	if (intel_crtc->unpin_work) {
		if ((++intel_crtc->unpin_work->pending) > 1)
			DRM_ERROR("Prepared flip multiple times\n");
	} else {
		DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
	}
	spin_unlock_irqrestore(&dev->event_lock, flags);
}

static int intel_crtc_page_flip(struct drm_crtc *crtc,
				struct drm_framebuffer *fb,
				struct drm_pending_vblank_event *event)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_framebuffer *intel_fb;
	struct drm_i915_gem_object *obj;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_unpin_work *work;
	unsigned long flags, offset;
	int pipe = intel_crtc->pipe;
	u32 pf, pipesrc;
	int ret;

	work = kzalloc(sizeof *work, GFP_KERNEL);
	if (work == NULL)
		return -ENOMEM;

	work->event = event;
	work->dev = crtc->dev;
	intel_fb = to_intel_framebuffer(crtc->fb);
	work->old_fb_obj = intel_fb->obj;
	INIT_WORK(&work->work, intel_unpin_work_fn);

	/* We borrow the event spin lock for protecting unpin_work */
	spin_lock_irqsave(&dev->event_lock, flags);
	if (intel_crtc->unpin_work) {
		spin_unlock_irqrestore(&dev->event_lock, flags);
		kfree(work);

		DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
		return -EBUSY;
	}
	intel_crtc->unpin_work = work;
	spin_unlock_irqrestore(&dev->event_lock, flags);

	intel_fb = to_intel_framebuffer(fb);
	obj = intel_fb->obj;

	mutex_lock(&dev->struct_mutex);
	ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
	if (ret)
		goto cleanup_work;

	/* Reference the objects for the scheduled work. */
	drm_gem_object_reference(&work->old_fb_obj->base);
	drm_gem_object_reference(&obj->base);

	crtc->fb = fb;

	ret = drm_vblank_get(dev, intel_crtc->pipe);
	if (ret)
		goto cleanup_objs;

	if (IS_GEN3(dev) || IS_GEN2(dev)) {
		u32 flip_mask;

		/* Can't queue multiple flips, so wait for the previous
		 * one to finish before executing the next.
		 */
		ret = BEGIN_LP_RING(2);
		if (ret)
			goto cleanup_objs;

		if (intel_crtc->plane)
			flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
		else
			flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
		OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
		OUT_RING(MI_NOOP);
		ADVANCE_LP_RING();
	}

	work->pending_flip_obj = obj;

	work->enable_stall_check = true;

	/* Offset into the new buffer for cases of shared fbs between CRTCs */
	offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;

	ret = BEGIN_LP_RING(4);
	if (ret)
		goto cleanup_objs;

	/* Block clients from rendering to the new back buffer until
	 * the flip occurs and the object is no longer visible.
	 */
	atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);

	switch (INTEL_INFO(dev)->gen) {
	case 2:
		OUT_RING(MI_DISPLAY_FLIP |
			 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		OUT_RING(fb->pitch);
		OUT_RING(obj->gtt_offset + offset);
		OUT_RING(MI_NOOP);
		break;

	case 3:
		OUT_RING(MI_DISPLAY_FLIP_I915 |
			 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		OUT_RING(fb->pitch);
		OUT_RING(obj->gtt_offset + offset);
		OUT_RING(MI_NOOP);
		break;

	case 4:
	case 5:
		/* i965+ uses the linear or tiled offsets from the
		 * Display Registers (which do not change across a page-flip)
		 * so we need only reprogram the base address.
		 */
		OUT_RING(MI_DISPLAY_FLIP |
			 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		OUT_RING(fb->pitch);
		OUT_RING(obj->gtt_offset | obj->tiling_mode);

		/* XXX Enabling the panel-fitter across page-flip is so far
		 * untested on non-native modes, so ignore it for now.
		 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
		 */
		pf = 0;
		pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
		OUT_RING(pf | pipesrc);
		break;

	case 6:
		OUT_RING(MI_DISPLAY_FLIP |
			 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
		OUT_RING(fb->pitch | obj->tiling_mode);
		OUT_RING(obj->gtt_offset);

		pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
		pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
		OUT_RING(pf | pipesrc);
		break;
	}
	ADVANCE_LP_RING();

	mutex_unlock(&dev->struct_mutex);

	trace_i915_flip_request(intel_crtc->plane, obj);

	return 0;

cleanup_objs:
	drm_gem_object_unreference(&work->old_fb_obj->base);
	drm_gem_object_unreference(&obj->base);
cleanup_work:
	mutex_unlock(&dev->struct_mutex);

	spin_lock_irqsave(&dev->event_lock, flags);
	intel_crtc->unpin_work = NULL;
	spin_unlock_irqrestore(&dev->event_lock, flags);

	kfree(work);

	return ret;
}

static void intel_crtc_reset(struct drm_crtc *crtc)
{
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	/* Reset flags back to the 'unknown' status so that they
	 * will be correctly set on the initial modeset.
	 */
	intel_crtc->cursor_addr = 0;
	intel_crtc->dpms_mode = -1;

	printk("intel_crtc %p\n", intel_crtc);

	//intel_crtc->active = true; // force the pipe off on setup_init_config
}

static struct drm_crtc_helper_funcs intel_helper_funcs = {
	.dpms = intel_crtc_dpms,
	.mode_fixup = intel_crtc_mode_fixup,
	.mode_set = intel_crtc_mode_set,
	.mode_set_base = intel_pipe_set_base,
	.mode_set_base_atomic = intel_pipe_set_base_atomic,
	.load_lut = intel_crtc_load_lut,
	.disable = intel_crtc_disable,
};

static const struct drm_crtc_funcs intel_crtc_funcs = {
	.reset = intel_crtc_reset,
	.cursor_set = intel_crtc_cursor_set,
	.cursor_move = intel_crtc_cursor_move,
	.gamma_set = intel_crtc_gamma_set,
	.set_config = drm_crtc_helper_set_config,
	.destroy = intel_crtc_destroy,
	.page_flip = intel_crtc_page_flip,
};

static void intel_sanitize_modesetting(struct drm_device *dev,
				       int pipe, int plane)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 reg, val;

	if (HAS_PCH_SPLIT(dev))
		return;

	/* Who knows what state these registers were left in by the BIOS or
	 * grub?
	 *
	 * If we leave the registers in a conflicting state (e.g. with the
	 * display plane reading from the other pipe than the one we intend
	 * to use) then when we attempt to teardown the active mode, we will
	 * not disable the pipes and planes in the correct order -- leaving
	 * a plane reading from a disabled pipe and possibly leading to
	 * undefined behaviour.
	 */

	reg = DSPCNTR(plane);
	val = I915_READ(reg);

	if ((val & DISPLAY_PLANE_ENABLE) == 0)
		return;
	if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
		return;

	/* This display plane is active and attached to the other CPU pipe. */
	pipe = !pipe;

	/* Disable the plane and wait for it to stop reading from the pipe. */
	I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
	intel_flush_display_plane(dev, plane);

	if (IS_GEN2(dev))
		intel_wait_for_vblank(dev, pipe);

	if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
		return;

	/* Switch off the pipe. */
	reg = PIPECONF(pipe);
	val = I915_READ(reg);
	if (val & PIPECONF_ENABLE) {
		I915_WRITE(reg, val & ~PIPECONF_ENABLE);
		intel_wait_for_pipe_off(dev, pipe);
	}
}

static void intel_crtc_init(struct drm_device *dev, int pipe)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc;
	int i;

	intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
	if (intel_crtc == NULL)
		return;

	drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);

	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
	for (i = 0; i < 256; i++) {
		intel_crtc->lut_r[i] = i;
		intel_crtc->lut_g[i] = i;
		intel_crtc->lut_b[i] = i;
	}

	/* Swap pipes & planes for FBC on pre-965 */
	intel_crtc->pipe = pipe;
	intel_crtc->plane = pipe;
	if (IS_MOBILE(dev) && IS_GEN3(dev)) {
		DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
		intel_crtc->plane = !pipe;
	}

	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
	       dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;

	//intel_crtc->cursor_addr = 0;
	//intel_crtc->dpms_mode = -1;
	intel_crtc->active = true; // force the pipe off on setup_init_config

	printk("intel_crtc %p\n", intel_crtc);

	intel_crtc_reset(&intel_crtc->base);

	if (HAS_PCH_SPLIT(dev)) {
		intel_helper_funcs.prepare = ironlake_crtc_prepare;
		intel_helper_funcs.commit = ironlake_crtc_commit;
	} else {
		intel_helper_funcs.prepare = i9xx_crtc_prepare;
		intel_helper_funcs.commit = i9xx_crtc_commit;
	}

	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);

	intel_crtc->busy = false;

	setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
		    (unsigned long)intel_crtc);

	intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
}

int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
				struct drm_file *file)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
	struct drm_mode_object *drmmode_obj;
	struct intel_crtc *crtc;

	if (!dev_priv) {
		DRM_ERROR("called with no initialization\n");
		return -EINVAL;
	}

	drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
			DRM_MODE_OBJECT_CRTC);

	if (!drmmode_obj) {
		DRM_ERROR("no such CRTC id\n");
		return -EINVAL;
	}

	crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
	pipe_from_crtc_id->pipe = crtc->pipe;

	return 0;
}

static int intel_encoder_clones(struct drm_device *dev, int type_mask)
{
	struct intel_encoder *encoder;
	int index_mask = 0;
	int entry = 0;

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		if (type_mask & encoder->clone_mask)
			index_mask |= (1 << entry);
		entry++;
	}

	return index_mask;
}

static bool has_edp_a(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!IS_MOBILE(dev))
		return false;

	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
		return false;

	if (IS_GEN5(dev) &&
	    (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
		return false;

	return true;
}

static void intel_setup_outputs(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *encoder;
	bool dpd_is_edp = false;
	bool has_lvds = false;

	if (IS_MOBILE(dev) && !IS_I830(dev))
		has_lvds = intel_lvds_init(dev);
	if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
		/* disable the panel fitter on everything but LVDS */
		I915_WRITE(PFIT_CONTROL, 0);
	}

	if (HAS_PCH_SPLIT(dev)) {
		dpd_is_edp = intel_dpd_is_edp(dev);

		if (has_edp_a(dev))
			intel_dp_init(dev, DP_A);

		if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
			intel_dp_init(dev, PCH_DP_D);
	}

	intel_crt_init(dev);

	if (HAS_PCH_SPLIT(dev)) {
		int found;

		if (I915_READ(HDMIB) & PORT_DETECTED) {
			/* PCH SDVOB multiplex with HDMIB */
			found = intel_sdvo_init(dev, PCH_SDVOB);
			if (!found)
				intel_hdmi_init(dev, HDMIB);
			if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
				intel_dp_init(dev, PCH_DP_B);
		}

		if (I915_READ(HDMIC) & PORT_DETECTED)
			intel_hdmi_init(dev, HDMIC);

		if (I915_READ(HDMID) & PORT_DETECTED)
			intel_hdmi_init(dev, HDMID);

		if (I915_READ(PCH_DP_C) & DP_DETECTED)
			intel_dp_init(dev, PCH_DP_C);

		if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
			intel_dp_init(dev, PCH_DP_D);

	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
		bool found = false;

		if (I915_READ(SDVOB) & SDVO_DETECTED) {
			DRM_DEBUG_KMS("probing SDVOB\n");
			found = intel_sdvo_init(dev, SDVOB);
			if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
				DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
				intel_hdmi_init(dev, SDVOB);
			}

			if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
				DRM_DEBUG_KMS("probing DP_B\n");
				intel_dp_init(dev, DP_B);
			}
		}

		/* Before G4X SDVOC doesn't have its own detect register */

		if (I915_READ(SDVOB) & SDVO_DETECTED) {
			DRM_DEBUG_KMS("probing SDVOC\n");
			found = intel_sdvo_init(dev, SDVOC);
		}

		if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {

			if (SUPPORTS_INTEGRATED_HDMI(dev)) {
				DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
				intel_hdmi_init(dev, SDVOC);
			}
			if (SUPPORTS_INTEGRATED_DP(dev)) {
				DRM_DEBUG_KMS("probing DP_C\n");
				intel_dp_init(dev, DP_C);
			}
		}

		if (SUPPORTS_INTEGRATED_DP(dev) &&
		    (I915_READ(DP_D) & DP_DETECTED)) {
			DRM_DEBUG_KMS("probing DP_D\n");
			intel_dp_init(dev, DP_D);
		}
	} else if (IS_GEN2(dev))
		intel_dvo_init(dev);

	if (SUPPORTS_TV(dev))
		intel_tv_init(dev);

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		encoder->base.possible_crtcs = encoder->crtc_mask;
		encoder->base.possible_clones =
			intel_encoder_clones(dev, encoder->clone_mask);
	}

	intel_panel_setup_backlight(dev);
}

static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
{
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);

	drm_framebuffer_cleanup(fb);
	drm_gem_object_unreference_unlocked(&intel_fb->obj->base);

	kfree(intel_fb);
}

static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
						struct drm_file *file,
						unsigned int *handle)
{
	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
	struct drm_i915_gem_object *obj = intel_fb->obj;

	return drm_gem_handle_create(file, &obj->base, handle);
}

static const struct drm_framebuffer_funcs intel_fb_funcs = {
	.destroy = intel_user_framebuffer_destroy,
	.create_handle = intel_user_framebuffer_create_handle,
};

int intel_framebuffer_init(struct drm_device *dev,
			   struct intel_framebuffer *intel_fb,
			   struct drm_mode_fb_cmd *mode_cmd,
			   struct drm_i915_gem_object *obj)
{
	int ret;

	if (obj->tiling_mode == I915_TILING_Y)
		return -EINVAL;

	if (mode_cmd->pitch & 63)
		return -EINVAL;

	switch (mode_cmd->bpp) {
	case 8:
	case 16:
	case 24:
	case 32:
		break;
	default:
		return -EINVAL;
	}

	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
	if (ret) {
		DRM_ERROR("framebuffer init failed %d\n", ret);
		return ret;
	}

	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
	intel_fb->obj = obj;
	return 0;
}

static struct drm_framebuffer *
intel_user_framebuffer_create(struct drm_device *dev,
			      struct drm_file *filp,
			      struct drm_mode_fb_cmd *mode_cmd)
{
	struct drm_i915_gem_object *obj;
	struct intel_framebuffer *intel_fb;
	int ret;

	obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
	if (!obj)
		return ERR_PTR(-ENOENT);

	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
	if (!intel_fb)
		return ERR_PTR(-ENOMEM);

	ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
	if (ret) {
		drm_gem_object_unreference_unlocked(&obj->base);
		kfree(intel_fb);
		return ERR_PTR(ret);
	}

	return &intel_fb->base;
}

static const struct drm_mode_config_funcs intel_mode_funcs = {
	.fb_create = intel_user_framebuffer_create,
	.output_poll_changed = intel_fb_output_poll_changed,
};

static struct drm_i915_gem_object *
intel_alloc_context_page(struct drm_device *dev)
{
	struct drm_i915_gem_object *ctx;
	int ret;

	ctx = i915_gem_alloc_object(dev, 4096);
	if (!ctx) {
		DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
		return NULL;
	}

	mutex_lock(&dev->struct_mutex);
	ret = i915_gem_object_pin(ctx, 4096, true);
	if (ret) {
		DRM_ERROR("failed to pin power context: %d\n", ret);
		goto err_unref;
	}

	ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
	if (ret) {
		DRM_ERROR("failed to set-domain on power context: %d\n", ret);
		goto err_unpin;
	}
	mutex_unlock(&dev->struct_mutex);

	return ctx;

err_unpin:
	i915_gem_object_unpin(ctx);
err_unref:
	drm_gem_object_unreference(&ctx->base);
	mutex_unlock(&dev->struct_mutex);
	return NULL;
}

bool ironlake_set_drps(struct drm_device *dev, u8 val)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u16 rgvswctl;

	rgvswctl = I915_READ16(MEMSWCTL);
	if (rgvswctl & MEMCTL_CMD_STS) {
		DRM_DEBUG("gpu busy, RCS change rejected\n");
		return false; /* still busy with another command */
	}

	rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
		(val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
	I915_WRITE16(MEMSWCTL, rgvswctl);
	POSTING_READ16(MEMSWCTL);

	rgvswctl |= MEMCTL_CMD_STS;
	I915_WRITE16(MEMSWCTL, rgvswctl);

	return true;
}

void ironlake_enable_drps(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 rgvmodectl = I915_READ(MEMMODECTL);
	u8 fmax, fmin, fstart, vstart;

	/* Enable temp reporting */
	I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
	I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);

	/* 100ms RC evaluation intervals */
	I915_WRITE(RCUPEI, 100000);
	I915_WRITE(RCDNEI, 100000);

	/* Set max/min thresholds to 90ms and 80ms respectively */
	I915_WRITE(RCBMAXAVG, 90000);
	I915_WRITE(RCBMINAVG, 80000);

	I915_WRITE(MEMIHYST, 1);

	/* Set up min, max, and cur for interrupt handling */
	fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
	fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
	fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
		MEMMODE_FSTART_SHIFT;

	vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
		PXVFREQ_PX_SHIFT;

	dev_priv->fmax = fmax; /* IPS callback will increase this */
	dev_priv->fstart = fstart;

	dev_priv->max_delay = fstart;
	dev_priv->min_delay = fmin;
	dev_priv->cur_delay = fstart;

	DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
			 fmax, fmin, fstart);

	I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);

	/*
	 * Interrupts will be enabled in ironlake_irq_postinstall
	 */

	I915_WRITE(VIDSTART, vstart);
	POSTING_READ(VIDSTART);

	rgvmodectl |= MEMMODE_SWMODE_EN;
	I915_WRITE(MEMMODECTL, rgvmodectl);

	if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
		DRM_ERROR("stuck trying to change perf mode\n");
	msleep(1);

	ironlake_set_drps(dev, fstart);

	dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
		I915_READ(0x112e0);
	dev_priv->last_time1 = jiffies_to_msecs(jiffies);
	dev_priv->last_count2 = I915_READ(0x112f4);
	getrawmonotonic(&dev_priv->last_time2);
}

void ironlake_disable_drps(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u16 rgvswctl = I915_READ16(MEMSWCTL);

	/* Ack interrupts, disable EFC interrupt */
	I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
	I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
	I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
	I915_WRITE(DEIIR, DE_PCU_EVENT);
	I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);

	/* Go back to the starting frequency */
	ironlake_set_drps(dev, dev_priv->fstart);
	msleep(1);
	rgvswctl |= MEMCTL_CMD_STS;
	I915_WRITE(MEMSWCTL, rgvswctl);
	msleep(1);

}

void gen6_set_rps(struct drm_device *dev, u8 val)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 swreq;

	swreq = (val & 0x3ff) << 25;
	I915_WRITE(GEN6_RPNSWREQ, swreq);
}

void gen6_disable_rps(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
	I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
	I915_WRITE(GEN6_PMIER, 0);
	I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
}

static unsigned long intel_pxfreq(u32 vidfreq)
{
	unsigned long freq;
	int div = (vidfreq & 0x3f0000) >> 16;
	int post = (vidfreq & 0x3000) >> 12;
	int pre = (vidfreq & 0x7);

	if (!pre)
		return 0;

	freq = ((div * 133333) / ((1<<post) * pre));

	return freq;
}

void intel_init_emon(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 lcfuse;
	u8 pxw[16];
	int i;

	/* Disable to program */
	I915_WRITE(ECR, 0);
	POSTING_READ(ECR);

	/* Program energy weights for various events */
	I915_WRITE(SDEW, 0x15040d00);
	I915_WRITE(CSIEW0, 0x007f0000);
	I915_WRITE(CSIEW1, 0x1e220004);
	I915_WRITE(CSIEW2, 0x04000004);

	for (i = 0; i < 5; i++)
		I915_WRITE(PEW + (i * 4), 0);
	for (i = 0; i < 3; i++)
		I915_WRITE(DEW + (i * 4), 0);

	/* Program P-state weights to account for frequency power adjustment */
	for (i = 0; i < 16; i++) {
		u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
		unsigned long freq = intel_pxfreq(pxvidfreq);
		unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
			PXVFREQ_PX_SHIFT;
		unsigned long val;

		val = vid * vid;
		val *= (freq / 1000);
		val *= 255;
		val /= (127*127*900);
		if (val > 0xff)
			DRM_ERROR("bad pxval: %ld\n", val);
		pxw[i] = val;
	}
	/* Render standby states get 0 weight */
	pxw[14] = 0;
	pxw[15] = 0;

	for (i = 0; i < 4; i++) {
		u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
			(pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
		I915_WRITE(PXW + (i * 4), val);
	}

	/* Adjust magic regs to magic values (more experimental results) */
	I915_WRITE(OGW0, 0);
	I915_WRITE(OGW1, 0);
	I915_WRITE(EG0, 0x00007f00);
	I915_WRITE(EG1, 0x0000000e);
	I915_WRITE(EG2, 0x000e0000);
	I915_WRITE(EG3, 0x68000300);
	I915_WRITE(EG4, 0x42000000);
	I915_WRITE(EG5, 0x00140031);
	I915_WRITE(EG6, 0);
	I915_WRITE(EG7, 0);

	for (i = 0; i < 8; i++)
		I915_WRITE(PXWL + (i * 4), 0);

	/* Enable PMON + select events */
	I915_WRITE(ECR, 0x80000019);

	lcfuse = I915_READ(LCFUSE02);

	dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
}

void gen6_enable_rps(struct drm_i915_private *dev_priv)
{
	u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
	u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
	u32 pcu_mbox;
	int cur_freq, min_freq, max_freq;
	int i;

	/* Here begins a magic sequence of register writes to enable
	 * auto-downclocking.
	 *
	 * Perhaps there might be some value in exposing these to
	 * userspace...
	 */
	I915_WRITE(GEN6_RC_STATE, 0);
	__gen6_force_wake_get(dev_priv);

	/* disable the counters and set deterministic thresholds */
	I915_WRITE(GEN6_RC_CONTROL, 0);

	I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
	I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);

	for (i = 0; i < I915_NUM_RINGS; i++)
		I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);

	I915_WRITE(GEN6_RC_SLEEP, 0);
	I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
	I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
	I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
	I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */

	I915_WRITE(GEN6_RC_CONTROL,
		   GEN6_RC_CTL_RC6p_ENABLE |
		   GEN6_RC_CTL_RC6_ENABLE |
		   GEN6_RC_CTL_EI_MODE(1) |
		   GEN6_RC_CTL_HW_ENABLE);

	I915_WRITE(GEN6_RPNSWREQ,
		   GEN6_FREQUENCY(10) |
		   GEN6_OFFSET(0) |
		   GEN6_AGGRESSIVE_TURBO);
	I915_WRITE(GEN6_RC_VIDEO_FREQ,
		   GEN6_FREQUENCY(12));

	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
		   18 << 24 |
		   6 << 16);
	I915_WRITE(GEN6_RP_UP_THRESHOLD, 90000);
	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 100000);
	I915_WRITE(GEN6_RP_UP_EI, 100000);
	I915_WRITE(GEN6_RP_DOWN_EI, 300000);
	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
	I915_WRITE(GEN6_RP_CONTROL,
		   GEN6_RP_MEDIA_TURBO |
		   GEN6_RP_USE_NORMAL_FREQ |
		   GEN6_RP_MEDIA_IS_GFX |
		   GEN6_RP_ENABLE |
		   GEN6_RP_UP_BUSY_MAX |
		   GEN6_RP_DOWN_BUSY_MIN);

	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
		     500))
		DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");

	I915_WRITE(GEN6_PCODE_DATA, 0);
	I915_WRITE(GEN6_PCODE_MAILBOX,
		   GEN6_PCODE_READY |
		   GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
		     500))
		DRM_ERROR("timeout waiting for pcode mailbox to finish\n");

	min_freq = (rp_state_cap & 0xff0000) >> 16;
	max_freq = rp_state_cap & 0xff;
	cur_freq = (gt_perf_status & 0xff00) >> 8;

	/* Check for overclock support */
	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
		     500))
		DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
	I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
	pcu_mbox = I915_READ(GEN6_PCODE_DATA);
	if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
		     500))
		DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
	if (pcu_mbox & (1<<31)) { /* OC supported */
		max_freq = pcu_mbox & 0xff;
		DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 100);
	}

	/* In units of 100MHz */
	dev_priv->max_delay = max_freq;
	dev_priv->min_delay = min_freq;
	dev_priv->cur_delay = cur_freq;

	/* requires MSI enabled */
	I915_WRITE(GEN6_PMIER,
		   GEN6_PM_MBOX_EVENT |
		   GEN6_PM_THERMAL_EVENT |
		   GEN6_PM_RP_DOWN_TIMEOUT |
		   GEN6_PM_RP_UP_THRESHOLD |
		   GEN6_PM_RP_DOWN_THRESHOLD |
		   GEN6_PM_RP_UP_EI_EXPIRED |
		   GEN6_PM_RP_DOWN_EI_EXPIRED);
	I915_WRITE(GEN6_PMIMR, 0);
	/* enable all PM interrupts */
	I915_WRITE(GEN6_PMINTRMSK, 0);

	__gen6_force_wake_put(dev_priv);
}

void intel_enable_clock_gating(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	/*
	 * Disable clock gating reported to work incorrectly according to the
	 * specs, but enable as much else as we can.
	 */
	if (HAS_PCH_SPLIT(dev)) {
		uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;

		if (IS_GEN5(dev)) {
			/* Required for FBC */
			dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
				DPFCRUNIT_CLOCK_GATE_DISABLE |
				DPFDUNIT_CLOCK_GATE_DISABLE;
			/* Required for CxSR */
			dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;

			I915_WRITE(PCH_3DCGDIS0,
				   MARIUNIT_CLOCK_GATE_DISABLE |
				   SVSMUNIT_CLOCK_GATE_DISABLE);
			I915_WRITE(PCH_3DCGDIS1,
				   VFMUNIT_CLOCK_GATE_DISABLE);
		}

		I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);

		/*
		 * On Ibex Peak and Cougar Point, we need to disable clock
		 * gating for the panel power sequencer or it will fail to
		 * start up when no ports are active.
		 */
		I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);

		/*
		 * According to the spec the following bits should be set in
		 * order to enable memory self-refresh
		 * The bit 22/21 of 0x42004
		 * The bit 5 of 0x42020
		 * The bit 15 of 0x45000
		 */
		if (IS_GEN5(dev)) {
			I915_WRITE(ILK_DISPLAY_CHICKEN2,
					(I915_READ(ILK_DISPLAY_CHICKEN2) |
					ILK_DPARB_GATE | ILK_VSDPFD_FULL));
			I915_WRITE(ILK_DSPCLK_GATE,
					(I915_READ(ILK_DSPCLK_GATE) |
						ILK_DPARB_CLK_GATE));
			I915_WRITE(DISP_ARB_CTL,
					(I915_READ(DISP_ARB_CTL) |
						DISP_FBC_WM_DIS));
			I915_WRITE(WM3_LP_ILK, 0);
			I915_WRITE(WM2_LP_ILK, 0);
			I915_WRITE(WM1_LP_ILK, 0);
		}
		/*
		 * Based on the document from hardware guys the following bits
		 * should be set unconditionally in order to enable FBC.
		 * The bit 22 of 0x42000
		 * The bit 22 of 0x42004
		 * The bit 7,8,9 of 0x42020.
		 */
		if (IS_IRONLAKE_M(dev)) {
			I915_WRITE(ILK_DISPLAY_CHICKEN1,
				   I915_READ(ILK_DISPLAY_CHICKEN1) |
				   ILK_FBCQ_DIS);
			I915_WRITE(ILK_DISPLAY_CHICKEN2,
				   I915_READ(ILK_DISPLAY_CHICKEN2) |
				   ILK_DPARB_GATE);
			I915_WRITE(ILK_DSPCLK_GATE,
				   I915_READ(ILK_DSPCLK_GATE) |
				   ILK_DPFC_DIS1 |
				   ILK_DPFC_DIS2 |
				   ILK_CLK_FBC);
		}

		I915_WRITE(ILK_DISPLAY_CHICKEN2,
			   I915_READ(ILK_DISPLAY_CHICKEN2) |
			   ILK_ELPIN_409_SELECT);

		if (IS_GEN5(dev)) {
			I915_WRITE(_3D_CHICKEN2,
				   _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
				   _3D_CHICKEN2_WM_READ_PIPELINED);
		}

		if (IS_GEN6(dev)) {
			I915_WRITE(WM3_LP_ILK, 0);
			I915_WRITE(WM2_LP_ILK, 0);
			I915_WRITE(WM1_LP_ILK, 0);

			/*
			 * According to the spec the following bits should be
			 * set in order to enable memory self-refresh and fbc:
			 * The bit21 and bit22 of 0x42000
			 * The bit21 and bit22 of 0x42004
			 * The bit5 and bit7 of 0x42020
			 * The bit14 of 0x70180
			 * The bit14 of 0x71180
			 */
			I915_WRITE(ILK_DISPLAY_CHICKEN1,
				   I915_READ(ILK_DISPLAY_CHICKEN1) |
				   ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
			I915_WRITE(ILK_DISPLAY_CHICKEN2,
				   I915_READ(ILK_DISPLAY_CHICKEN2) |
				   ILK_DPARB_GATE | ILK_VSDPFD_FULL);
			I915_WRITE(ILK_DSPCLK_GATE,
				   I915_READ(ILK_DSPCLK_GATE) |
				   ILK_DPARB_CLK_GATE  |
				   ILK_DPFD_CLK_GATE);

			I915_WRITE(DSPACNTR,
				   I915_READ(DSPACNTR) |
				   DISPPLANE_TRICKLE_FEED_DISABLE);
			I915_WRITE(DSPBCNTR,
				   I915_READ(DSPBCNTR) |
				   DISPPLANE_TRICKLE_FEED_DISABLE);
		}
	} else if (IS_G4X(dev)) {
		uint32_t dspclk_gate;
		I915_WRITE(RENCLK_GATE_D1, 0);
		I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
		       GS_UNIT_CLOCK_GATE_DISABLE |
		       CL_UNIT_CLOCK_GATE_DISABLE);
		I915_WRITE(RAMCLK_GATE_D, 0);
		dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
			OVRUNIT_CLOCK_GATE_DISABLE |
			OVCUNIT_CLOCK_GATE_DISABLE;
		if (IS_GM45(dev))
			dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
		I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
	} else if (IS_CRESTLINE(dev)) {
		I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
		I915_WRITE(RENCLK_GATE_D2, 0);
		I915_WRITE(DSPCLK_GATE_D, 0);
		I915_WRITE(RAMCLK_GATE_D, 0);
		I915_WRITE16(DEUC, 0);
	} else if (IS_BROADWATER(dev)) {
		I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
		       I965_RCC_CLOCK_GATE_DISABLE |
		       I965_RCPB_CLOCK_GATE_DISABLE |
		       I965_ISC_CLOCK_GATE_DISABLE |
		       I965_FBC_CLOCK_GATE_DISABLE);
		I915_WRITE(RENCLK_GATE_D2, 0);
	} else if (IS_GEN3(dev)) {
		u32 dstate = I915_READ(D_STATE);

		dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
			DSTATE_DOT_CLOCK_GATING;
		I915_WRITE(D_STATE, dstate);
	} else if (IS_I85X(dev) || IS_I865G(dev)) {
		I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
	} else if (IS_I830(dev)) {
		I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
	}
}

void intel_disable_clock_gating(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (dev_priv->renderctx) {
		struct drm_i915_gem_object *obj = dev_priv->renderctx;

		I915_WRITE(CCID, 0);
		POSTING_READ(CCID);

		i915_gem_object_unpin(obj);
		drm_gem_object_unreference(&obj->base);
		dev_priv->renderctx = NULL;
	}

	if (dev_priv->pwrctx) {
		struct drm_i915_gem_object *obj = dev_priv->pwrctx;

		I915_WRITE(PWRCTXA, 0);
		POSTING_READ(PWRCTXA);

		i915_gem_object_unpin(obj);
		drm_gem_object_unreference(&obj->base);
		dev_priv->pwrctx = NULL;
	}
}

static void ironlake_disable_rc6(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	/* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
	I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
	wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
		 10);
	POSTING_READ(CCID);
	I915_WRITE(PWRCTXA, 0);
	POSTING_READ(PWRCTXA);
	I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
	POSTING_READ(RSTDBYCTL);
	i915_gem_object_unpin(dev_priv->renderctx);
	drm_gem_object_unreference(&dev_priv->renderctx->base);
	dev_priv->renderctx = NULL;
	i915_gem_object_unpin(dev_priv->pwrctx);
	drm_gem_object_unreference(&dev_priv->pwrctx->base);
	dev_priv->pwrctx = NULL;
}

void ironlake_enable_rc6(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	/*
	 * GPU can automatically power down the render unit if given a page
	 * to save state.
	 */
	ret = BEGIN_LP_RING(6);
	if (ret) {
		ironlake_disable_rc6(dev);
		return;
	}
	OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
	OUT_RING(MI_SET_CONTEXT);
	OUT_RING(dev_priv->renderctx->gtt_offset |
		 MI_MM_SPACE_GTT |
		 MI_SAVE_EXT_STATE_EN |
		 MI_RESTORE_EXT_STATE_EN |
		 MI_RESTORE_INHIBIT);
	OUT_RING(MI_SUSPEND_FLUSH);
	OUT_RING(MI_NOOP);
	OUT_RING(MI_FLUSH);
	ADVANCE_LP_RING();

	I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
	I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
}

/* Set up chip specific display functions */
static void intel_init_display(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	/* We always want a DPMS function */
	if (HAS_PCH_SPLIT(dev))
		dev_priv->display.dpms = ironlake_crtc_dpms;
	else
		dev_priv->display.dpms = i9xx_crtc_dpms;

	if (I915_HAS_FBC(dev)) {
		if (HAS_PCH_SPLIT(dev)) {
			dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
			dev_priv->display.enable_fbc = ironlake_enable_fbc;
			dev_priv->display.disable_fbc = ironlake_disable_fbc;
		} else if (IS_GM45(dev)) {
			dev_priv->display.fbc_enabled = g4x_fbc_enabled;
			dev_priv->display.enable_fbc = g4x_enable_fbc;
			dev_priv->display.disable_fbc = g4x_disable_fbc;
		} else if (IS_CRESTLINE(dev)) {
			dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
			dev_priv->display.enable_fbc = i8xx_enable_fbc;
			dev_priv->display.disable_fbc = i8xx_disable_fbc;
		}
		/* 855GM needs testing */
	}

	/* Returns the core display clock speed */
	if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
		dev_priv->display.get_display_clock_speed =
			i945_get_display_clock_speed;
	else if (IS_I915G(dev))
		dev_priv->display.get_display_clock_speed =
			i915_get_display_clock_speed;
	else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
		dev_priv->display.get_display_clock_speed =
			i9xx_misc_get_display_clock_speed;
	else if (IS_I915GM(dev))
		dev_priv->display.get_display_clock_speed =
			i915gm_get_display_clock_speed;
	else if (IS_I865G(dev))
		dev_priv->display.get_display_clock_speed =
			i865_get_display_clock_speed;
	else if (IS_I85X(dev))
		dev_priv->display.get_display_clock_speed =
			i855_get_display_clock_speed;
	else /* 852, 830 */
		dev_priv->display.get_display_clock_speed =
			i830_get_display_clock_speed;

	/* For FIFO watermark updates */
	if (HAS_PCH_SPLIT(dev)) {
		if (IS_GEN5(dev)) {
			if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
				dev_priv->display.update_wm = ironlake_update_wm;
			else {
				DRM_DEBUG_KMS("Failed to get proper latency. "
					      "Disable CxSR\n");
				dev_priv->display.update_wm = NULL;
			}
		} else if (IS_GEN6(dev)) {
			if (SNB_READ_WM0_LATENCY()) {
				dev_priv->display.update_wm = sandybridge_update_wm;
			} else {
				DRM_DEBUG_KMS("Failed to read display plane latency. "
					      "Disable CxSR\n");
				dev_priv->display.update_wm = NULL;
			}
		} else
			dev_priv->display.update_wm = NULL;
	} else if (IS_PINEVIEW(dev)) {
		if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
					    dev_priv->is_ddr3,
					    dev_priv->fsb_freq,
					    dev_priv->mem_freq)) {
			DRM_INFO("failed to find known CxSR latency "
				 "(found ddr%s fsb freq %d, mem freq %d), "
				 "disabling CxSR\n",
				 (dev_priv->is_ddr3 == 1) ? "3": "2",
				 dev_priv->fsb_freq, dev_priv->mem_freq);
			/* Disable CxSR and never update its watermark again */
			pineview_disable_cxsr(dev);
			dev_priv->display.update_wm = NULL;
		} else
			dev_priv->display.update_wm = pineview_update_wm;
	} else if (IS_G4X(dev))
		dev_priv->display.update_wm = g4x_update_wm;
	else if (IS_GEN4(dev))
		dev_priv->display.update_wm = i965_update_wm;
	else if (IS_GEN3(dev)) {
		dev_priv->display.update_wm = i9xx_update_wm;
		dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
	} else if (IS_I85X(dev)) {
		dev_priv->display.update_wm = i9xx_update_wm;
		dev_priv->display.get_fifo_size = i85x_get_fifo_size;
	} else {
		dev_priv->display.update_wm = i830_update_wm;
		if (IS_845G(dev))
			dev_priv->display.get_fifo_size = i845_get_fifo_size;
		else
			dev_priv->display.get_fifo_size = i830_get_fifo_size;
	}
}

/*
 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
 * resume, or other times.  This quirk makes sure that's the case for
 * affected systems.
 */
static void quirk_pipea_force (struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	dev_priv->quirks |= QUIRK_PIPEA_FORCE;
	DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
}

struct intel_quirk {
	int device;
	int subsystem_vendor;
	int subsystem_device;
	void (*hook)(struct drm_device *dev);
};

struct intel_quirk intel_quirks[] = {
	/* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
	{ 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
	/* HP Mini needs pipe A force quirk (LP: #322104) */
	{ 0x27ae,0x103c, 0x361a, quirk_pipea_force },

	/* Thinkpad R31 needs pipe A force quirk */
	{ 0x3577, 0x1014, 0x0505, quirk_pipea_force },
	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },

	/* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
	{ 0x3577,  0x1014, 0x0513, quirk_pipea_force },
	/* ThinkPad X40 needs pipe A force quirk */

	/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
	{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },

	/* 855 & before need to leave pipe A & dpll A up */
	{ 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
	{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
};

static void intel_init_quirks(struct drm_device *dev)
{
	struct pci_dev *d = dev->pdev;
	int i;

	for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
		struct intel_quirk *q = &intel_quirks[i];

		if (d->device == q->device &&
		    (d->subsystem_vendor == q->subsystem_vendor ||
		     q->subsystem_vendor == PCI_ANY_ID) &&
		    (d->subsystem_device == q->subsystem_device ||
		     q->subsystem_device == PCI_ANY_ID))
			q->hook(dev);
	}
}

/* Disable the VGA plane that we never use */
static void i915_disable_vga(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u8 sr1;
	u32 vga_reg;

	if (HAS_PCH_SPLIT(dev))
		vga_reg = CPU_VGACNTRL;
	else
		vga_reg = VGACNTRL;

	vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
	outb(1, VGA_SR_INDEX);
	sr1 = inb(VGA_SR_DATA);
	outb(sr1 | 1<<5, VGA_SR_DATA);
	vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
	udelay(300);

	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
	POSTING_READ(vga_reg);
}

void intel_modeset_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	drm_mode_config_init(dev);

	dev->mode_config.min_width = 0;
	dev->mode_config.min_height = 0;

	dev->mode_config.funcs = (void *)&intel_mode_funcs;

	intel_init_quirks(dev);

	intel_init_display(dev);

	if (IS_GEN2(dev)) {
		dev->mode_config.max_width = 2048;
		dev->mode_config.max_height = 2048;
	} else if (IS_GEN3(dev)) {
		dev->mode_config.max_width = 4096;
		dev->mode_config.max_height = 4096;
	} else {
		dev->mode_config.max_width = 8192;
		dev->mode_config.max_height = 8192;
	}
	dev->mode_config.fb_base = dev->agp->base;

	if (IS_MOBILE(dev) || !IS_GEN2(dev))
		dev_priv->num_pipe = 2;
	else
		dev_priv->num_pipe = 1;
	DRM_DEBUG_KMS("%d display pipe%s available.\n",
		      dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");

	for (i = 0; i < dev_priv->num_pipe; i++) {
		intel_crtc_init(dev, i);
	}

	intel_setup_outputs(dev);

	intel_enable_clock_gating(dev);

	/* Just disable it once at startup */
	i915_disable_vga(dev);

	if (IS_IRONLAKE_M(dev)) {
		ironlake_enable_drps(dev);
		intel_init_emon(dev);
	}

	if (IS_GEN6(dev))
		gen6_enable_rps(dev_priv);

	if (IS_IRONLAKE_M(dev)) {
		dev_priv->renderctx = intel_alloc_context_page(dev);
		if (!dev_priv->renderctx)
			goto skip_rc6;
		dev_priv->pwrctx = intel_alloc_context_page(dev);
		if (!dev_priv->pwrctx) {
			i915_gem_object_unpin(dev_priv->renderctx);
			drm_gem_object_unreference(&dev_priv->renderctx->base);
			dev_priv->renderctx = NULL;
			goto skip_rc6;
		}
		ironlake_enable_rc6(dev);
	}

skip_rc6:
	INIT_WORK(&dev_priv->idle_work, intel_idle_update);
	setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
		    (unsigned long)dev);

	intel_setup_overlay(dev);
}

void intel_modeset_cleanup(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	struct intel_crtc *intel_crtc;

	drm_kms_helper_poll_fini(dev);
	mutex_lock(&dev->struct_mutex);

	intel_unregister_dsm_handler();


	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		/* Skip inactive CRTCs */
		if (!crtc->fb)
			continue;

		intel_crtc = to_intel_crtc(crtc);
		intel_increase_pllclock(crtc);
	}

	if (dev_priv->display.disable_fbc)
		dev_priv->display.disable_fbc(dev);

	if (IS_IRONLAKE_M(dev))
		ironlake_disable_drps(dev);
	if (IS_GEN6(dev))
		gen6_disable_rps(dev);

	if (IS_IRONLAKE_M(dev))
		ironlake_disable_rc6(dev);

	mutex_unlock(&dev->struct_mutex);

	/* Disable the irq before mode object teardown, for the irq might
	 * enqueue unpin/hotplug work. */
	drm_irq_uninstall(dev);
	cancel_work_sync(&dev_priv->hotplug_work);

	/* Shut off idle work before the crtcs get freed. */
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		intel_crtc = to_intel_crtc(crtc);
		del_timer_sync(&intel_crtc->idle_timer);
	}
	del_timer_sync(&dev_priv->idle_timer);
	cancel_work_sync(&dev_priv->idle_work);

	drm_mode_config_cleanup(dev);
}

/*
 * Return which encoder is currently attached for connector.
 */
struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
{
	return &intel_attached_encoder(connector)->base;
}

void intel_connector_attach_encoder(struct intel_connector *connector,
				    struct intel_encoder *encoder)
{
	connector->encoder = encoder;
	drm_mode_connector_attach_encoder(&connector->base,
					  &encoder->base);
}

/*
 * set vga decode state - true == enable VGA decode
 */
int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u16 gmch_ctrl;

	pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
	if (state)
		gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
	else
		gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
	pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
	return 0;
}

#ifdef CONFIG_DEBUG_FS
#include <linux/seq_file.h>

struct intel_display_error_state {
	struct intel_cursor_error_state {
		u32 control;
		u32 position;
		u32 base;
		u32 size;
	} cursor[2];

	struct intel_pipe_error_state {
		u32 conf;
		u32 source;

		u32 htotal;
		u32 hblank;
		u32 hsync;
		u32 vtotal;
		u32 vblank;
		u32 vsync;
	} pipe[2];

	struct intel_plane_error_state {
		u32 control;
		u32 stride;
		u32 size;
		u32 pos;
		u32 addr;
		u32 surface;
		u32 tile_offset;
	} plane[2];
};

struct intel_display_error_state *
intel_display_capture_error_state(struct drm_device *dev)
{
        drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_display_error_state *error;
	int i;

	error = kmalloc(sizeof(*error), GFP_ATOMIC);
	if (error == NULL)
		return NULL;

	for (i = 0; i < 2; i++) {
		error->cursor[i].control = I915_READ(CURCNTR(i));
		error->cursor[i].position = I915_READ(CURPOS(i));
		error->cursor[i].base = I915_READ(CURBASE(i));

		error->plane[i].control = I915_READ(DSPCNTR(i));
		error->plane[i].stride = I915_READ(DSPSTRIDE(i));
		error->plane[i].size = I915_READ(DSPSIZE(i));
		error->plane[i].pos= I915_READ(DSPPOS(i));
		error->plane[i].addr = I915_READ(DSPADDR(i));
		if (INTEL_INFO(dev)->gen >= 4) {
			error->plane[i].surface = I915_READ(DSPSURF(i));
			error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
		}

		error->pipe[i].conf = I915_READ(PIPECONF(i));
		error->pipe[i].source = I915_READ(PIPESRC(i));
		error->pipe[i].htotal = I915_READ(HTOTAL(i));
		error->pipe[i].hblank = I915_READ(HBLANK(i));
		error->pipe[i].hsync = I915_READ(HSYNC(i));
		error->pipe[i].vtotal = I915_READ(VTOTAL(i));
		error->pipe[i].vblank = I915_READ(VBLANK(i));
		error->pipe[i].vsync = I915_READ(VSYNC(i));
	}

	return error;
}

void
intel_display_print_error_state(struct seq_file *m,
				struct drm_device *dev,
				struct intel_display_error_state *error)
{
	int i;

	for (i = 0; i < 2; i++) {
		seq_printf(m, "Pipe [%d]:\n", i);
		seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
		seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
		seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
		seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
		seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
		seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
		seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
		seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);

		seq_printf(m, "Plane [%d]:\n", i);
		seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
		seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
		seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
		seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
		seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
		if (INTEL_INFO(dev)->gen >= 4) {
			seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
			seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
		}

		seq_printf(m, "Cursor [%d]:\n", i);
		seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
		seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
		seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
	}
}
#endif

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Jeff Chua]

On Mon, Feb 7, 2011 at 4:36 PM, Jeff Chua <jeff.chua.linux@gmail.com> wrote:
> On Mon, Feb 7, 2011 at 4:25 PM, Takashi Iwai <tiwai@suse.de> wrote:
>> At Mon, 7 Feb 2011 13:02:46 +0800,
>> Jeff Chua wrote:
>>>
>>> On Mon, Feb 7, 2011 at 12:48 PM, Jeff Chua <jeff.chua.linux@gmail.com> wrote:
>>> > On Sun, Feb 6, 2011 at 11:27 PM, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>>> >> One last step: move contents of intel_crtc_reset() back to
>>> >> intel_crtc_init() one by one.
>>> >>
>>> >> The active flag is my suspicion. I was thinking that we brought up the
>>> >> outputs in a similar manner upon resume as upon initial boot. On
>>> >> reflection, this is the not case.
>>> >>
>>> >> However, the first action we take inside modesetting is to disable the
>>> >> outputs about to be reconfigured. So setting active should be the right
>>> >> course of action so that cleanup any residual state from resume.
>>> >>
>>> >> So I am intrigued as to which line is the cause, and just where the
>>> >> machine becomes unresponsive...
>>> >
>>> > It's this line causing the problem.
>>> >
>>> > intel_crtc->active = true; /* force the pipe off on setup_init_config */
>>> >
>>> >
>>> > When it's called before entering intel_crtc_reset(&intel_crtc->base),
>>> > it works, but if called within the function, it doesn't work. Strange.
>>> > Not sure whether is passing the correct value to to_intel_crtc(crtc)?
>>>
>>> I've added printk() below and the function returns a different value
>>> of intel_crtc.
>>>
>>>
>>> static void intel_crtc_reset(struct drm_crtc *crtc)
>>> {
>>>         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>>>         printk("intel_crtc %p\n", intel_crtc); ===> intel_crtc ffff8802349d1000
>>>
>>> }
>>>
>>> printk("intel_crtc %p\n", intel_crtc); ===> intel_crtc ffff8802349d0000
>>> intel_crtc_reset(&intel_crtc->base);
>>
>> That's weird.  Since base is the first member, both intel_crtc and crtc
>> must be identical.
>
> In case I'm messing something up, here's my intel_display.c

Why not just pass intel_crtc as in

- static void intel_crtc_reset(struct drm_crtc *crtc)
+ static void intel_crtc_reset(struct intel_crtc *intel_crtc)

Jeff.

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Takashi Iwai]

At Mon, 7 Feb 2011 16:36:33 +0800,
Jeff Chua wrote:
> 
> On Mon, Feb 7, 2011 at 4:25 PM, Takashi Iwai <tiwai@suse.de> wrote:
> > At Mon, 7 Feb 2011 13:02:46 +0800,
> > Jeff Chua wrote:
> >>
> >> On Mon, Feb 7, 2011 at 12:48 PM, Jeff Chua <jeff.chua.linux@gmail.com> wrote:
> >> > On Sun, Feb 6, 2011 at 11:27 PM, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> >> >> One last step: move contents of intel_crtc_reset() back to
> >> >> intel_crtc_init() one by one.
> >> >>
> >> >> The active flag is my suspicion. I was thinking that we brought up the
> >> >> outputs in a similar manner upon resume as upon initial boot. On
> >> >> reflection, this is the not case.
> >> >>
> >> >> However, the first action we take inside modesetting is to disable the
> >> >> outputs about to be reconfigured. So setting active should be the right
> >> >> course of action so that cleanup any residual state from resume.
> >> >>
> >> >> So I am intrigued as to which line is the cause, and just where the
> >> >> machine becomes unresponsive...
> >> >
> >> > It's this line causing the problem.
> >> >
> >> > intel_crtc->active = true; /* force the pipe off on setup_init_config */
> >> >
> >> >
> >> > When it's called before entering intel_crtc_reset(&intel_crtc->base),
> >> > it works, but if called within the function, it doesn't work. Strange.
> >> > Not sure whether is passing the correct value to to_intel_crtc(crtc)?
> >>
> >> I've added printk() below and the function returns a different value
> >> of intel_crtc.
> >>
> >>
> >> static void intel_crtc_reset(struct drm_crtc *crtc)
> >> {
> >>         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> >>         printk("intel_crtc %p\n", intel_crtc); ===> intel_crtc ffff8802349d1000
> >>
> >> }
> >>
> >> printk("intel_crtc %p\n", intel_crtc); ===> intel_crtc ffff8802349d0000
> >> intel_crtc_reset(&intel_crtc->base);
> >
> > That's weird.  Since base is the first member, both intel_crtc and crtc
> > must be identical.
> 
> In case I'm messing something up, here's my intel_display.c

Thanks, that looks good.  What about other files?  Did you change
(especially intel_drv.h) from Linus git tree?

I'll also check later to be sure (now I have no machine for testing).


thanks,

Takashi

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Takashi Iwai]

At Mon, 7 Feb 2011 16:45:16 +0800,
Jeff Chua wrote:
> 
> On Mon, Feb 7, 2011 at 4:36 PM, Jeff Chua <jeff.chua.linux@gmail.com> wrote:
> > On Mon, Feb 7, 2011 at 4:25 PM, Takashi Iwai <tiwai@suse.de> wrote:
> >> At Mon, 7 Feb 2011 13:02:46 +0800,
> >> Jeff Chua wrote:
> >>>
> >>> On Mon, Feb 7, 2011 at 12:48 PM, Jeff Chua <jeff.chua.linux@gmail.com> wrote:
> >>> > On Sun, Feb 6, 2011 at 11:27 PM, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> >>> >> One last step: move contents of intel_crtc_reset() back to
> >>> >> intel_crtc_init() one by one.
> >>> >>
> >>> >> The active flag is my suspicion. I was thinking that we brought up the
> >>> >> outputs in a similar manner upon resume as upon initial boot. On
> >>> >> reflection, this is the not case.
> >>> >>
> >>> >> However, the first action we take inside modesetting is to disable the
> >>> >> outputs about to be reconfigured. So setting active should be the right
> >>> >> course of action so that cleanup any residual state from resume.
> >>> >>
> >>> >> So I am intrigued as to which line is the cause, and just where the
> >>> >> machine becomes unresponsive...
> >>> >
> >>> > It's this line causing the problem.
> >>> >
> >>> > intel_crtc->active = true; /* force the pipe off on setup_init_config */
> >>> >
> >>> >
> >>> > When it's called before entering intel_crtc_reset(&intel_crtc->base),
> >>> > it works, but if called within the function, it doesn't work. Strange.
> >>> > Not sure whether is passing the correct value to to_intel_crtc(crtc)?
> >>>
> >>> I've added printk() below and the function returns a different value
> >>> of intel_crtc.
> >>>
> >>>
> >>> static void intel_crtc_reset(struct drm_crtc *crtc)
> >>> {
> >>>         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> >>>         printk("intel_crtc %p\n", intel_crtc); ===> intel_crtc ffff8802349d1000
> >>>
> >>> }
> >>>
> >>> printk("intel_crtc %p\n", intel_crtc); ===> intel_crtc ffff8802349d0000
> >>> intel_crtc_reset(&intel_crtc->base);
> >>
> >> That's weird.  Since base is the first member, both intel_crtc and crtc
> >> must be identical.
> >
> > In case I'm messing something up, here's my intel_display.c
> 
> Why not just pass intel_crtc as in
> 
> - static void intel_crtc_reset(struct drm_crtc *crtc)
> + static void intel_crtc_reset(struct intel_crtc *intel_crtc)

Because it's called from drm_crtc.c that has no idea about the
driver-local type :)


Takashi

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Marc Koschewski]

Takashi,

is this potentially breaking S3 resume with nouveau cards, too?

Regards,
Marc

* Takashi Iwai <tiwai@suse.de> [2011-02-07 09:25:42 +0100]:

> At Mon, 7 Feb 2011 13:02:46 +0800,
> Jeff Chua wrote:
> > 
> > On Mon, Feb 7, 2011 at 12:48 PM, Jeff Chua <jeff.chua.linux@gmail.com> wrote:
> > > On Sun, Feb 6, 2011 at 11:27 PM, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > >> One last step: move contents of intel_crtc_reset() back to
> > >> intel_crtc_init() one by one.
> > >>
> > >> The active flag is my suspicion. I was thinking that we brought up the
> > >> outputs in a similar manner upon resume as upon initial boot. On
> > >> reflection, this is the not case.
> > >>
> > >> However, the first action we take inside modesetting is to disable the
> > >> outputs about to be reconfigured. So setting active should be the right
> > >> course of action so that cleanup any residual state from resume.
> > >>
> > >> So I am intrigued as to which line is the cause, and just where the
> > >> machine becomes unresponsive...
> > >
> > > It's this line causing the problem.
> > >
> > > intel_crtc->active = true; /* force the pipe off on setup_init_config */
> > >
> > >
> > > When it's called before entering intel_crtc_reset(&intel_crtc->base),
> > > it works, but if called within the function, it doesn't work. Strange.
> > > Not sure whether is passing the correct value to to_intel_crtc(crtc)?
> > 
> > I've added printk() below and the function returns a different value
> > of intel_crtc.
> > 
> > 
> > static void intel_crtc_reset(struct drm_crtc *crtc)
> > {
> >         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> >         printk("intel_crtc %p\n", intel_crtc); ===> intel_crtc ffff8802349d1000
> > 
> > }
> > 
> > printk("intel_crtc %p\n", intel_crtc); ===> intel_crtc ffff8802349d0000
> > intel_crtc_reset(&intel_crtc->base);
> 
> That's weird.  Since base is the first member, both intel_crtc and crtc
> must be identical.
> 
> 
> Takashi
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/
> 
> 

-- 
Marc Koschewski

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Takashi Iwai]

At Mon, 7 Feb 2011 11:02:10 +0100,
Marc Koschewski wrote:
> 
> Takashi,
> 
> is this potentially breaking S3 resume with nouveau cards, too?

There is no reset callback except for i915, so there shouldn't be any
change for nouveau regarding these commits.


Takashi

> Regards,
> Marc
> 
> * Takashi Iwai <tiwai@suse.de> [2011-02-07 09:25:42 +0100]:
> 
> > At Mon, 7 Feb 2011 13:02:46 +0800,
> > Jeff Chua wrote:
> > > 
> > > On Mon, Feb 7, 2011 at 12:48 PM, Jeff Chua <jeff.chua.linux@gmail.com> wrote:
> > > > On Sun, Feb 6, 2011 at 11:27 PM, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > > >> One last step: move contents of intel_crtc_reset() back to
> > > >> intel_crtc_init() one by one.
> > > >>
> > > >> The active flag is my suspicion. I was thinking that we brought up the
> > > >> outputs in a similar manner upon resume as upon initial boot. On
> > > >> reflection, this is the not case.
> > > >>
> > > >> However, the first action we take inside modesetting is to disable the
> > > >> outputs about to be reconfigured. So setting active should be the right
> > > >> course of action so that cleanup any residual state from resume.
> > > >>
> > > >> So I am intrigued as to which line is the cause, and just where the
> > > >> machine becomes unresponsive...
> > > >
> > > > It's this line causing the problem.
> > > >
> > > > intel_crtc->active = true; /* force the pipe off on setup_init_config */
> > > >
> > > >
> > > > When it's called before entering intel_crtc_reset(&intel_crtc->base),
> > > > it works, but if called within the function, it doesn't work. Strange.
> > > > Not sure whether is passing the correct value to to_intel_crtc(crtc)?
> > > 
> > > I've added printk() below and the function returns a different value
> > > of intel_crtc.
> > > 
> > > 
> > > static void intel_crtc_reset(struct drm_crtc *crtc)
> > > {
> > >         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > >         printk("intel_crtc %p\n", intel_crtc); ===> intel_crtc ffff8802349d1000
> > > 
> > > }
> > > 
> > > printk("intel_crtc %p\n", intel_crtc); ===> intel_crtc ffff8802349d0000
> > > intel_crtc_reset(&intel_crtc->base);
> > 
> > That's weird.  Since base is the first member, both intel_crtc and crtc
> > must be identical.
> > 
> > 
> > Takashi
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
> > Please read the FAQ at  http://www.tux.org/lkml/
> > 
> > 
> 
> -- 
> Marc Koschewski
> 

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Marc Koschewski]

* Takashi Iwai <tiwai@suse.de> [2011-02-07 11:06:45 +0100]:

OK,

seems like there's a fix for ACPI wakeup memory in tip/urgent. Maybe the fix relates to
this resume issue as well.

Marc

> At Mon, 7 Feb 2011 11:02:10 +0100,
> Marc Koschewski wrote:
> > 
> > Takashi,
> > 
> > is this potentially breaking S3 resume with nouveau cards, too?
> 
> There is no reset callback except for i915, so there shouldn't be any
> change for nouveau regarding these commits.
> 
> 
> Takashi
> 
> > Regards,
> > Marc
> > 
> > * Takashi Iwai <tiwai@suse.de> [2011-02-07 09:25:42 +0100]:
> > 
> > > At Mon, 7 Feb 2011 13:02:46 +0800,
> > > Jeff Chua wrote:
> > > > 
> > > > On Mon, Feb 7, 2011 at 12:48 PM, Jeff Chua <jeff.chua.linux@gmail.com> wrote:
> > > > > On Sun, Feb 6, 2011 at 11:27 PM, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > > > >> One last step: move contents of intel_crtc_reset() back to
> > > > >> intel_crtc_init() one by one.
> > > > >>
> > > > >> The active flag is my suspicion. I was thinking that we brought up the
> > > > >> outputs in a similar manner upon resume as upon initial boot. On
> > > > >> reflection, this is the not case.
> > > > >>
> > > > >> However, the first action we take inside modesetting is to disable the
> > > > >> outputs about to be reconfigured. So setting active should be the right
> > > > >> course of action so that cleanup any residual state from resume.
> > > > >>
> > > > >> So I am intrigued as to which line is the cause, and just where the
> > > > >> machine becomes unresponsive...
> > > > >
> > > > > It's this line causing the problem.
> > > > >
> > > > > intel_crtc->active = true; /* force the pipe off on setup_init_config */
> > > > >
> > > > >
> > > > > When it's called before entering intel_crtc_reset(&intel_crtc->base),
> > > > > it works, but if called within the function, it doesn't work. Strange.
> > > > > Not sure whether is passing the correct value to to_intel_crtc(crtc)?
> > > > 
> > > > I've added printk() below and the function returns a different value
> > > > of intel_crtc.
> > > > 
> > > > 
> > > > static void intel_crtc_reset(struct drm_crtc *crtc)
> > > > {
> > > >         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > > >         printk("intel_crtc %p\n", intel_crtc); ===> intel_crtc ffff8802349d1000
> > > > 
> > > > }
> > > > 
> > > > printk("intel_crtc %p\n", intel_crtc); ===> intel_crtc ffff8802349d0000
> > > > intel_crtc_reset(&intel_crtc->base);
> > > 
> > > That's weird.  Since base is the first member, both intel_crtc and crtc
> > > must be identical.
> > > 
> > > 
> > > Takashi
> > > --
> > > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> > > the body of a message to majordomo@vger.kernel.org
> > > More majordomo info at  http://vger.kernel.org/majordomo-info.html
> > > Please read the FAQ at  http://www.tux.org/lkml/
> > > 
> > > 
> > 
> > -- 
> > Marc Koschewski
> > 
> 
> 

-- 
Marc Koschewski

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Takashi Iwai]

At Mon, 07 Feb 2011 09:52:55 +0100,
Takashi Iwai wrote:
> 
> At Mon, 7 Feb 2011 16:36:33 +0800,
> Jeff Chua wrote:
> > 
> > On Mon, Feb 7, 2011 at 4:25 PM, Takashi Iwai <tiwai@suse.de> wrote:
> > > At Mon, 7 Feb 2011 13:02:46 +0800,
> > > Jeff Chua wrote:
> > >>
> > >> On Mon, Feb 7, 2011 at 12:48 PM, Jeff Chua <jeff.chua.linux@gmail.com> wrote:
> > >> > On Sun, Feb 6, 2011 at 11:27 PM, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > >> >> One last step: move contents of intel_crtc_reset() back to
> > >> >> intel_crtc_init() one by one.
> > >> >>
> > >> >> The active flag is my suspicion. I was thinking that we brought up the
> > >> >> outputs in a similar manner upon resume as upon initial boot. On
> > >> >> reflection, this is the not case.
> > >> >>
> > >> >> However, the first action we take inside modesetting is to disable the
> > >> >> outputs about to be reconfigured. So setting active should be the right
> > >> >> course of action so that cleanup any residual state from resume.
> > >> >>
> > >> >> So I am intrigued as to which line is the cause, and just where the
> > >> >> machine becomes unresponsive...
> > >> >
> > >> > It's this line causing the problem.
> > >> >
> > >> > intel_crtc->active = true; /* force the pipe off on setup_init_config */
> > >> >
> > >> >
> > >> > When it's called before entering intel_crtc_reset(&intel_crtc->base),
> > >> > it works, but if called within the function, it doesn't work. Strange.
> > >> > Not sure whether is passing the correct value to to_intel_crtc(crtc)?
> > >>
> > >> I've added printk() below and the function returns a different value
> > >> of intel_crtc.
> > >>
> > >>
> > >> static void intel_crtc_reset(struct drm_crtc *crtc)
> > >> {
> > >>         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > >>         printk("intel_crtc %p\n", intel_crtc); ===> intel_crtc ffff8802349d1000
> > >>
> > >> }
> > >>
> > >> printk("intel_crtc %p\n", intel_crtc); ===> intel_crtc ffff8802349d0000
> > >> intel_crtc_reset(&intel_crtc->base);
> > >
> > > That's weird.  Since base is the first member, both intel_crtc and crtc
> > > must be identical.
> > 
> > In case I'm messing something up, here's my intel_display.c
> 
> Thanks, that looks good.  What about other files?  Did you change
> (especially intel_drv.h) from Linus git tree?
> 
> I'll also check later to be sure (now I have no machine for testing).

I don't see any problem with my machine (but running in 32bit).

Are you sure that you are seeing the same CRTC?  There are two active
CRTCs on Intel, and both are initialized and set up.


Takashi

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Jeff Chua]

On Mon, Feb 7, 2011 at 6:15 PM, Takashi Iwai <tiwai@suse.de> wrote:
>> Thanks, that looks good.  What about other files?  Did you change
>> (especially intel_drv.h) from Linus git tree?

I will try again  from a fresh build tonight.

>> I'll also check later to be sure (now I have no machine for testing).
> I don't see any problem with my machine (but running in 32bit).
>
> Are you sure that you are seeing the same CRTC?  There are two active
> CRTCs on Intel, and both are initialized and set up.

I don't know about that. Even when I attempt to just the pointer
directly as in "static void intel_crtc_reset(struct intel_crtc
*intel_crtc)", it ended up getting a different value. Strange.

intel_crtc ffff880239aa5800
intel_crtc ffff880239aa5000


I'm building everything fresh now.

Jeff

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Jeff Chua]

On Mon, Feb 7, 2011 at 9:38 PM, Jeff Chua <jeff.chua.linux@gmail.com> wrote:
> On Mon, Feb 7, 2011 at 6:15 PM, Takashi Iwai <tiwai@suse.de> wrote:
>>> Thanks, that looks good.  What about other files?  Did you change
>>> (especially intel_drv.h) from Linus git tree?
>
> I will try again  from a fresh build tonight.
>
>>> I'll also check later to be sure (now I have no machine for testing).
>> I don't see any problem with my machine (but running in 32bit).
>>
>> Are you sure that you are seeing the same CRTC?  There are two active
>> CRTCs on Intel, and both are initialized and set up.
>
> I don't know about that. Even when I attempt to just the pointer
> directly as in "static void intel_crtc_reset(struct intel_crtc
> *intel_crtc)", it ended up getting a different value. Strange.
>
> intel_crtc ffff880239aa5800
> intel_crtc ffff880239aa5000
>
>
> I'm building everything fresh now.

Same issue encountered even after a fresh build.

Jeff

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Rafael J. Wysocki]

On Monday, February 07, 2011, Jeff Chua wrote:
> On Mon, Feb 7, 2011 at 9:38 PM, Jeff Chua <jeff.chua.linux@gmail.com> wrote:
> > On Mon, Feb 7, 2011 at 6:15 PM, Takashi Iwai <tiwai@suse.de> wrote:
> >>> Thanks, that looks good.  What about other files?  Did you change
> >>> (especially intel_drv.h) from Linus git tree?
> >
> > I will try again  from a fresh build tonight.
> >
> >>> I'll also check later to be sure (now I have no machine for testing).
> >> I don't see any problem with my machine (but running in 32bit).
> >>
> >> Are you sure that you are seeing the same CRTC?  There are two active
> >> CRTCs on Intel, and both are initialized and set up.
> >
> > I don't know about that. Even when I attempt to just the pointer
> > directly as in "static void intel_crtc_reset(struct intel_crtc
> > *intel_crtc)", it ended up getting a different value. Strange.
> >
> > intel_crtc ffff880239aa5800
> > intel_crtc ffff880239aa5000
> >
> >
> > I'm building everything fresh now.
> 
> Same issue encountered even after a fresh build.

So, can you confirm that on your machine the issue is 100% reproducible and
it goes away after reverting

commit 5d1d0cc87fc0887921993ea0742932e0c8adeda0
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Mon Jan 24 15:02:15 2011 +0000

    drm/i915: Reset crtc after resume

?

Rafael

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Jeff Chua]

On Tue, Feb 8, 2011 at 5:20 AM, Rafael J. Wysocki <rjw@sisk.pl> wrote:
> On Monday, February 07, 2011, Jeff Chua wrote:
>> Same issue encountered even after a fresh build.
>
> So, can you confirm that on your machine the issue is 100% reproducible and
> it goes away after reverting
>
> commit 5d1d0cc87fc0887921993ea0742932e0c8adeda0
> Author: Chris Wilson <chris@chris-wilson.co.uk>
> Date:   Mon Jan 24 15:02:15 2011 +0000
>
>    drm/i915: Reset crtc after resume

100% confirmed that it works after reverting.

Jeff.

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Chris Wilson]

On Mon, 7 Feb 2011 22:11:29 +0800, Jeff Chua <jeff.chua.linux@gmail.com> wrote:
> Same issue encountered even after a fresh build.

I've been testing on the same hardware (x201s, 64bit, with and without
external DP) and I've not encountered the same issue. Every time I look
at the code, by not setting crtc->active we may incorrectly skip disabling
an active output after resume. If the output is inactive, then disabling it
*should* be a no-op, and thus safe. So I am still at a loss to understand
what fails here and so whether we have a bigger problem on our hands.

Please can you add drm.debug=0xe to your boot parameters (or echo 0xe >
/sys/module/drm/parameters/debug might just be enough) and attach the
dmesg whilst resuming. Also attaching the failing Xorg.0.log would be
useful to rule out any other issues.
-Chris
-- 
Chris Wilson, Intel Open Source Technology Centre

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Jeff Chua]

[-- Attachment #1: Type: text/plain, Size: 1231 bytes --]

On Tue, Feb 8, 2011 at 9:36 PM, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> On Mon, 7 Feb 2011 22:11:29 +0800, Jeff Chua <jeff.chua.linux@gmail.com> wrote:
>> Same issue encountered even after a fresh build.
>
> I've been testing on the same hardware (x201s, 64bit, with and without
> external DP) and I've not encountered the same issue. Every time I look
> at the code, by not setting crtc->active we may incorrectly skip disabling
> an active output after resume. If the output is inactive, then disabling it
> *should* be a no-op, and thus safe. So I am still at a loss to understand
> what fails here and so whether we have a bigger problem on our hands.

Same X201s ... that's good. I'm using "echo mem >/sys/power/state" to suspend.
>
> Please can you add drm.debug=0xe to your boot parameters (or echo 0xe >
> /sys/module/drm/parameters/debug might just be enough) and attach the
> dmesg whilst resuming. Also attaching the failing Xorg.0.log would be
> useful to rule out any other issues.

Attached. The Xorg.0.log didn't log anything after resume because the
system hanged, and kernel log is "partially" logged. I've attached my
kernel .config as well.

And the console hangs even without starting X.

Thanks,
Jeff

[-- Attachment #2: kernel --]
[-- Type: application/octet-stream, Size: 146185 bytes --]


<suspending to ram now>

2011-02-09T08:41:16.943639+08:00 boston kernel: CPU 1 is now offline
2011-02-09T08:41:16.963638+08:00 boston kernel: coretemp coretemp.3: TjMax is 105 C.
2011-02-09T08:41:17.134419+08:00 boston kernel: CPU 2 is now offline
2011-02-09T08:41:17.143637+08:00 boston kernel: CPU 3 MCA banks CMCI:2 CMCI:3 CMCI:5
2011-02-09T08:41:17.223644+08:00 boston kernel: CPU 3 is now offline
2011-02-09T08:41:17.223668+08:00 boston kernel: SMP alternatives: switching to UP code
2011-02-09T08:41:17.263661+08:00 boston kernel: PM: Syncing filesystems ... done.
2011-02-09T08:41:17.273642+08:00 boston kernel: [drm:intel_crtc_cursor_set], 
2011-02-09T08:41:17.273662+08:00 boston kernel: [drm:intel_crtc_cursor_set], cursor off
2011-02-09T08:41:21.972337+08:00 boston kernel: [drm:drm_crtc_helper_set_config], 
2011-02-09T08:41:21.972364+08:00 boston kernel: [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:9] #connectors=1 (x y) (0 0)
2011-02-09T08:41:21.972367+08:00 boston kernel: [drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:3]
2011-02-09T08:41:21.972369+08:00 boston kernel: [drm:intel_pipe_set_base_atomic], Writing base 00045000 00000000 0 0 5760
2011-02-09T08:41:21.972371+08:00 boston kernel: [drm:intel_update_fbc], 
2011-02-09T08:41:21.972373+08:00 boston kernel: [drm:intel_prepare_page_flip], preparing flip with no unpin work?
2011-02-09T08:41:21.972374+08:00 boston kernel: [drm:intel_wait_for_vblank], vblank wait timed out
2011-02-09T08:41:21.972376+08:00 boston kernel: [drm:drm_crtc_helper_set_config], 
2011-02-09T08:41:21.972377+08:00 boston kernel: [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:9] #connectors=1 (x y) (0 0)
2011-02-09T08:41:21.972379+08:00 boston kernel: [drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:3]
2011-02-09T08:41:21.972380+08:00 boston kernel: [drm:drm_crtc_helper_set_config], 
2011-02-09T08:41:21.972382+08:00 boston kernel: [drm:drm_crtc_helper_set_config], [CRTC:4] [NOFB]
2011-02-09T08:41:21.972384+08:00 boston kernel: [drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:3]
2011-02-09T08:41:21.972385+08:00 boston kernel: [drm:drm_crtc_helper_set_config], 
2011-02-09T08:41:21.972387+08:00 boston kernel: [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:9] #connectors=1 (x y) (0 0)
2011-02-09T08:41:21.972389+08:00 boston kernel: [drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:3]
2011-02-09T08:41:21.972390+08:00 boston kernel: [drm:drm_crtc_helper_set_config], 
2011-02-09T08:41:21.972392+08:00 boston kernel: [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:9] #connectors=1 (x y) (0 0)
2011-02-09T08:41:21.972394+08:00 boston kernel: [drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:3]
2011-02-09T08:41:21.972494+08:00 boston kernel: Freezing user space processes ... (elapsed 0.01 seconds) done.
2011-02-09T08:41:21.972496+08:00 boston kernel: Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done.
2011-02-09T08:41:21.972498+08:00 boston kernel: Suspending console(s) (use no_console_suspend to debug)
2011-02-09T08:41:21.972499+08:00 boston kernel: sd 0:0:0:0: [sda] Synchronizing SCSI cache
2011-02-09T08:41:21.972501+08:00 boston kernel: sd 0:0:0:0: [sda] Stopping disk
2011-02-09T08:41:21.972502+08:00 boston kernel: [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe 1
2011-02-09T08:41:21.972504+08:00 boston kernel: ehci_hcd 0000:00:1d.0: PCI INT D disabled
2011-02-09T08:41:21.972505+08:00 boston kernel: i915 0000:00:02.0: power state changed by ACPI to D3
2011-02-09T08:41:21.972507+08:00 boston kernel: ehci_hcd 0000:00:1a.0: PCI INT D disabled
2011-02-09T08:41:21.972508+08:00 boston kernel: HDA Intel 0000:00:1b.0: PCI INT B disabled
2011-02-09T08:41:21.972509+08:00 boston kernel: PM: suspend of devices complete after 249.507 msecs
2011-02-09T08:41:21.972511+08:00 boston kernel: ehci_hcd 0000:00:1d.0: power state changed by ACPI to D3
2011-02-09T08:41:21.972512+08:00 boston kernel: ehci_hcd 0000:00:1a.0: power state changed by ACPI to D3
2011-02-09T08:41:21.972514+08:00 boston kernel: PM: late suspend of devices complete after 90.103 msecs
2011-02-09T08:41:21.972515+08:00 boston kernel: ACPI: Preparing to enter system sleep state S3
2011-02-09T08:41:21.972516+08:00 boston kernel: PM: Saving platform NVS memory
2011-02-09T08:41:21.972518+08:00 boston kernel: Disabling non-boot CPUs ...
2011-02-09T08:41:21.972519+08:00 boston kernel: Extended CMOS year: 2000
2011-02-09T08:41:21.972520+08:00 boston kernel: Back to C!
2011-02-09T08:41:21.972522+08:00 boston kernel: PM: Restoring platform NVS memory
2011-02-09T08:41:21.972523+08:00 boston kernel: Extended CMOS year: 2000
2011-02-09T08:41:21.972524+08:00 boston kernel: ACPI: Waking up from system sleep state S3
2011-02-09T08:41:21.972526+08:00 boston kernel: agpgart-intel 0000:00:00.0: restoring config space at offset 0x1 (was 0x900006, writing 0x20900006)
2011-02-09T08:41:21.972528+08:00 boston kernel: i915 0000:00:02.0: restoring config space at offset 0x1 (was 0x900007, writing 0x900407)
2011-02-09T08:41:21.972529+08:00 boston kernel: ehci_hcd 0000:00:1a.0: restoring config space at offset 0xf (was 0x400, writing 0x40b)
2011-02-09T08:41:21.972531+08:00 boston kernel: ehci_hcd 0000:00:1a.0: restoring config space at offset 0x4 (was 0x0, writing 0xf2728000)
2011-02-09T08:41:21.972533+08:00 boston kernel: ehci_hcd 0000:00:1a.0: restoring config space at offset 0x1 (was 0x2900000, writing 0x2900102)
2011-02-09T08:41:21.972534+08:00 boston kernel: ehci_hcd 0000:00:1a.0: power state changed by ACPI to D0
2011-02-09T08:41:21.972536+08:00 boston kernel: ehci_hcd 0000:00:1a.0: power state changed by ACPI to D0
2011-02-09T08:41:21.972537+08:00 boston kernel: pcieport 0000:00:1c.0: restoring config space at offset 0x7 (was 0xf0, writing 0x200000f0)
2011-02-09T08:41:21.972539+08:00 boston kernel: pcieport 0000:00:1c.4: restoring config space at offset 0xf (was 0x100, writing 0x4010b)
2011-02-09T08:41:21.972541+08:00 boston kernel: pcieport 0000:00:1c.4: restoring config space at offset 0x9 (was 0x10001, writing 0x1fff1)
2011-02-09T08:41:21.972543+08:00 boston kernel: pcieport 0000:00:1c.4: restoring config space at offset 0x8 (was 0x0, writing 0xf240f240)
2011-02-09T08:41:21.972544+08:00 boston kernel: pcieport 0000:00:1c.4: restoring config space at offset 0x7 (was 0x0, writing 0x200000f0)
2011-02-09T08:41:21.972546+08:00 boston kernel: pcieport 0000:00:1c.4: restoring config space at offset 0x3 (was 0x810000, writing 0x810010)
2011-02-09T08:41:21.972548+08:00 boston kernel: pcieport 0000:00:1c.4: restoring config space at offset 0x1 (was 0x100000, writing 0x100107)
2011-02-09T08:41:21.972549+08:00 boston kernel: ehci_hcd 0000:00:1d.0: restoring config space at offset 0xf (was 0x400, writing 0x40b)
2011-02-09T08:41:21.972551+08:00 boston kernel: ehci_hcd 0000:00:1d.0: restoring config space at offset 0x4 (was 0x0, writing 0xf2728400)
2011-02-09T08:41:21.972553+08:00 boston kernel: ehci_hcd 0000:00:1d.0: restoring config space at offset 0x1 (was 0x2900000, writing 0x2900102)
2011-02-09T08:41:21.972554+08:00 boston kernel: ehci_hcd 0000:00:1d.0: power state changed by ACPI to D0
2011-02-09T08:41:21.972556+08:00 boston kernel: ehci_hcd 0000:00:1d.0: power state changed by ACPI to D0
2011-02-09T08:41:21.972557+08:00 boston kernel: ahci 0000:00:1f.2: restoring config space at offset 0x1 (was 0x2b00007, writing 0x2b00407)
2011-02-09T08:41:21.972559+08:00 boston kernel: pci 0000:00:1f.6: restoring config space at offset 0xf (was 0x400, writing 0x40b)
2011-02-09T08:41:21.972561+08:00 boston kernel: pci 0000:00:1f.6: restoring config space at offset 0x1 (was 0x100000, writing 0x100002)
2011-02-09T08:41:21.972562+08:00 boston kernel: PM: early resume of devices complete after 50.687 msecs
2011-02-09T08:41:21.972563+08:00 boston kernel: i915 0000:00:02.0: power state changed by ACPI to D0
2011-02-09T08:41:21.972565+08:00 boston kernel: i915 0000:00:02.0: power state changed by ACPI to D0
2011-02-09T08:41:21.972566+08:00 boston kernel: i915 0000:00:02.0: setting latency timer to 64
2011-02-09T08:41:21.972568+08:00 boston kernel: ehci_hcd 0000:00:1a.0: power state changed by ACPI to D0
2011-02-09T08:41:21.972569+08:00 boston kernel: ehci_hcd 0000:00:1a.0: power state changed by ACPI to D0
2011-02-09T08:41:21.972570+08:00 boston kernel: ehci_hcd 0000:00:1a.0: PCI INT D -> GSI 23 (level, low) -> IRQ 23
2011-02-09T08:41:21.972572+08:00 boston kernel: ehci_hcd 0000:00:1a.0: setting latency timer to 64
2011-02-09T08:41:21.972573+08:00 boston kernel: HDA Intel 0000:00:1b.0: PCI INT B -> GSI 17 (level, low) -> IRQ 17
2011-02-09T08:41:21.972575+08:00 boston kernel: HDA Intel 0000:00:1b.0: setting latency timer to 64
2011-02-09T08:41:21.972576+08:00 boston kernel: HDA Intel 0000:00:1b.0: irq 41 for MSI/MSI-X
2011-02-09T08:41:21.972578+08:00 boston kernel: ehci_hcd 0000:00:1d.0: power state changed by ACPI to D0
2011-02-09T08:41:21.972579+08:00 boston kernel: ehci_hcd 0000:00:1d.0: power state changed by ACPI to D0
2011-02-09T08:41:21.972581+08:00 boston kernel: ehci_hcd 0000:00:1d.0: PCI INT D -> GSI 19 (level, low) -> IRQ 19
2011-02-09T08:41:21.972582+08:00 boston kernel: ehci_hcd 0000:00:1d.0: setting latency timer to 64
2011-02-09T08:41:21.972584+08:00 boston kernel: pci 0000:00:1e.0: setting latency timer to 64
2011-02-09T08:41:21.972585+08:00 boston kernel: ahci 0000:00:1f.2: setting latency timer to 64
2011-02-09T08:41:21.972586+08:00 boston kernel: sd 0:0:0:0: [sda] Starting disk
2011-02-09T08:41:21.972588+08:00 boston kernel: [drm:ironlake_enable_drps], fmax: 0, fmin: 9, fstart: 9
2011-02-09T08:41:21.972589+08:00 boston kernel: [drm:intel_opregion_setup], graphic opregion physical addr: 0xbb77e018
2011-02-09T08:41:21.972654+08:00 boston kernel: [drm:intel_opregion_setup], Public ACPI methods supported
2011-02-09T08:41:21.972656+08:00 boston kernel: [drm:intel_opregion_setup], SWSCI supported
2011-02-09T08:41:21.972657+08:00 boston kernel: [drm:intel_opregion_setup], ASLE supported
2011-02-09T08:41:21.972659+08:00 boston kernel: [drm:init_status_page], render ring hws offset: 0x00000000
2011-02-09T08:41:21.972661+08:00 boston kernel: [drm:init_status_page], bsd ring hws offset: 0x00022000
2011-02-09T08:41:21.972662+08:00 boston kernel: [drm:drm_crtc_helper_set_mode], [CRTC:3]
2011-02-09T08:41:21.972664+08:00 boston kernel: [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe 0
2011-02-09T08:41:21.972665+08:00 boston kernel: [drm:i915_get_crtc_scanoutpos], trying to get scanoutpos for disabled pipe 0
2011-02-09T08:41:21.972667+08:00 boston kernel: [drm:gm45_get_vblank_counter], trying to get vblank count for disabled pipe 0
2011-02-09T08:41:21.972668+08:00 boston kernel: [drm:intel_update_fbc], 
2011-02-09T08:41:21.972670+08:00 boston kernel: [drm:intel_crtc_mode_set], using SSC reference clock of 120 MHz
2011-02-09T08:41:21.972671+08:00 boston kernel: [drm:intel_crtc_mode_set], Mode for pipe A:
2011-02-09T08:41:21.972673+08:00 boston kernel: [drm:drm_mode_debug_printmodeline], Modeline 8:"1440x900" 50 74080 1440 1464 1480 1600 900 903 909 926 0x48 0xa
2011-02-09T08:41:21.972676+08:00 boston kernel: [drm:intel_wait_for_vblank], vblank wait timed out
2011-02-09T08:41:21.972677+08:00 boston kernel: [drm:intel_pipe_set_base_atomic], Writing base 00045000 00000000 0 0 5760
2011-02-09T08:41:21.972678+08:00 boston kernel: [drm:intel_update_fbc], 
2011-02-09T08:41:21.972680+08:00 boston kernel: [drm:intel_wait_for_vblank], vblank wait timed out
2011-02-09T08:41:21.972682+08:00 boston kernel: [drm:drm_crtc_helper_set_mode], [ENCODER:6:LVDS-6] set [MODE:8:1440x900]
2011-02-09T08:41:21.972683+08:00 boston kernel: [drm:intel_update_watermarks], plane A (pipe 0) clock: 74080
2011-02-09T08:41:21.972685+08:00 boston kernel: [drm:ironlake_update_wm], FIFO watermarks For pipe A - plane 6, cursor: 6
2011-02-09T08:41:21.972686+08:00 boston kernel: [drm:ironlake_check_srwm], watermark 1: display plane 26, fbc lines 3, cursor 6
2011-02-09T08:41:21.972688+08:00 boston kernel: [drm:ironlake_check_srwm], watermark 2: display plane 81, fbc lines 3, cursor 6
2011-02-09T08:41:21.972690+08:00 boston kernel: [drm:pch_irq_handler], PCH FDI RX interrupt; FDI RXA IIR: 0x00000100, FDI RXB IIR: 0x00000000
2011-02-09T08:41:21.972691+08:00 boston kernel: [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x100
2011-02-09T08:41:21.972693+08:00 boston kernel: [drm:ironlake_fdi_link_train], FDI train 1 done.
2011-02-09T08:41:21.972694+08:00 boston kernel: [drm:pch_irq_handler], PCH FDI RX interrupt; FDI RXA IIR: 0x00000600, FDI RXB IIR: 0x00000000
2011-02-09T08:41:21.972696+08:00 boston kernel: [drm:ironlake_fdi_link_train], FDI_RX_IIR 0x600
2011-02-09T08:41:21.972697+08:00 boston kernel: [drm:ironlake_fdi_link_train], FDI train 2 done.
2011-02-09T08:41:21.972699+08:00 boston kernel: [drm:ironlake_fdi_link_train], FDI train done
2011-02-09T08:41:21.972700+08:00 boston kernel: [drm:intel_prepare_page_flip], preparing flip with no unpin work?
2011-02-09T08:41:21.972702+08:00 boston kernel: [drm:intel_update_fbc], 
2011-02-09T08:41:21.972703+08:00 boston kernel: [drm:intel_panel_set_backlight], set backlight PWM = 1785
2011-02-09T08:41:21.972704+08:00 boston kernel: [drm:ironlake_crtc_dpms], crtc 1/1 dpms off
2011-02-09T08:41:21.972706+08:00 boston kernel: No ACPI video bus found
2011-02-09T08:41:21.972707+08:00 boston kernel: ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
2011-02-09T08:41:21.972708+08:00 boston kernel: ata5: SATA link down (SStatus 0 SControl 300)
2011-02-09T08:41:21.972710+08:00 boston kernel: ata6: SATA link down (SStatus 0 SControl 300)
2011-02-09T08:41:21.972711+08:00 boston kernel: ata1.00: ACPI cmd ef/02:00:00:00:00:a0 (unknown) succeeded
2011-02-09T08:41:21.972713+08:00 boston kernel: ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (unknown) filtered out
2011-02-09T08:41:21.972714+08:00 boston kernel: ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (unknown) filtered out
2011-02-09T08:41:21.972716+08:00 boston kernel: ata1.00: ACPI cmd ef/02:00:00:00:00:a0 (unknown) succeeded
2011-02-09T08:41:21.972717+08:00 boston kernel: ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (unknown) filtered out
2011-02-09T08:41:21.972718+08:00 boston kernel: ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (unknown) filtered out
2011-02-09T08:41:21.972720+08:00 boston kernel: ata1.00: configured for UDMA/100
2011-02-09T08:41:21.972721+08:00 boston kernel: PM: resume of devices complete after 641.443 msecs
2011-02-09T08:41:21.978922+08:00 boston kernel: Restarting tasks ... done.
2011-02-09T08:41:21.978931+08:00 boston kernel: [drm:drm_mode_setcrtc], [CRTC:3]
2011-02-09T08:41:21.978933+08:00 boston kernel: [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1]
2011-02-09T08:41:21.978935+08:00 boston kernel: [drm:drm_crtc_helper_set_config], 
2011-02-09T08:41:21.978937+08:00 boston kernel: [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:20] #connectors=1 (x y) (0 0)
2011-02-09T08:41:21.978938+08:00 boston kernel: [drm:drm_crtc_helper_set_config], [CONNECTOR:5:LVDS-1] to [CRTC:3]
2011-02-09T08:41:21.978940+08:00 boston kernel: [drm:intel_pipe_set_base_atomic], Writing base 0053B000 00000000 0 0 6144
2011-02-09T08:41:21.978941+08:00 boston kernel: [drm:intel_update_fbc], 
2011-02-09T08:41:21.988952+08:00 boston kernel: [drm:intel_prepare_page_flip], preparing flip with no unpin work?
2011-02-09T08:41:22.008910+08:00 boston kernel: SMP alternatives: switching to SMP code
2011-02-09T08:41:22.008919+08:00 boston kernel: Booting Node 0 Processor 1 APIC 0x1
2011-02-09T08:41:22.038955+08:00 boston kernel: [drm:intel_wait_for_vblank], vblank wait timed out
2011-02-09T08:41:22.038980+08:00 boston kernel: [drm:drm_mode_getconnector], [CONNECTOR:5:?]
2011-02-09T08:41:22.038984+08:00 boston kernel: [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
2011-02-09T08:41:22.038987+08:00 boston kernel: [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes :
2011-02-09T08:41:22.038990+08:00 boston kernel: [drm:drm_mode_debug_printmodeline], Modeline 21:"1440x900" 50 74080 1440 1464 1480 1600 900 903 909 926 0x48 0xa
2011-02-09T08:41:22.038993+08:00 boston kernel: [drm:drm_mode_getconnector], [CONNECTOR:5:?]
2011-02-09T08:41:22.038995+08:00 boston kernel: [drm:drm_mode_getconnector], [CONNECTOR:12:?]
2011-02-09T08:41:22.038998+08:00 boston kernel: [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:12:VGA-1]
2011-02-09T08:41:22.039001+08:00 boston kernel: [drm:intel_ironlake_crt_detect_hotplug], trigger hotplug detect cycle: adpa=0xf40000
2011-02-09T08:41:22.058976+08:00 boston kernel: [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40000, result 0
2011-02-09T08:41:22.058985+08:00 boston kernel: [drm:intel_crt_detect], CRT not detected via hotplug
2011-02-09T08:41:22.058988+08:00 boston kernel: [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:12:VGA-1] disconnected
2011-02-09T08:41:22.058991+08:00 boston kernel: [drm:drm_mode_getconnector], [CONNECTOR:12:?]
2011-02-09T08:41:22.058994+08:00 boston kernel: [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:12:VGA-1]
2011-02-09T08:41:22.058997+08:00 boston kernel: [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40000, result 0
2011-02-09T08:41:22.058999+08:00 boston kernel: [drm:intel_crt_detect], CRT not detected via hotplug
2011-02-09T08:41:22.059002+08:00 boston kernel: [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:12:VGA-1] disconnected
2011-02-09T08:41:22.059005+08:00 boston kernel: [drm:drm_mode_getconnector], [CONNECTOR:15:?]
2011-02-09T08:41:22.059007+08:00 boston kernel: [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:HDMI-A-1]
2011-02-09T08:41:22.059011+08:00 boston kernel: [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:HDMI-A-1] disconnected
2011-02-09T08:41:22.059013+08:00 boston kernel: [drm:drm_mode_getconnector], [CONNECTOR:15:?]
2011-02-09T08:41:22.059016+08:00 boston kernel: [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:HDMI-A-1]
2011-02-09T08:41:22.059019+08:00 boston kernel: [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:HDMI-A-1] disconnected
2011-02-09T08:41:22.059021+08:00 boston kernel: [drm:drm_mode_getconnector], [CONNECTOR:17:?]
2011-02-09T08:41:22.059024+08:00 boston kernel: [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:DP-1]
2011-02-09T08:41:22.059027+08:00 boston kernel: [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003e
2011-02-09T08:41:22.059029+08:00 boston kernel: [drm:ironlake_dp_detect], DPCD: 0000
2011-02-09T08:41:22.059032+08:00 boston kernel: [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:DP-1] disconnected
2011-02-09T08:41:22.059034+08:00 boston kernel: [drm:drm_mode_getconnector], [CONNECTOR:17:?]
2011-02-09T08:41:22.059037+08:00 boston kernel: [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:DP-1]
2011-02-09T08:41:22.059040+08:00 boston kernel: [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003e
2011-02-09T08:41:22.059042+08:00 boston kernel: [drm:ironlake_dp_detect], DPCD: 0000
2011-02-09T08:41:22.059045+08:00 boston kernel: [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:DP-1] disconnected
2011-02-09T08:41:22.068907+08:00 boston kernel: [drm:intel_crtc_cursor_set], 
2011-02-09T08:41:22.198994+08:00 boston kernel: Switched to NOHz mode on CPU #1
2011-02-09T08:41:22.348949+08:00 boston kernel: Booting Node 0 Processor 2 APIC 0x4
2011-02-09T08:41:22.539011+08:00 boston kernel: Switched to NOHz mode on CPU #2
2011-02-09T08:41:22.728928+08:00 boston kernel: coretemp coretemp.2: TjMax is 105 C.
2011-02-09T08:41:22.758922+08:00 boston kernel: Booting Node 0 Processor 3 APIC 0x5
2011-02-09T08:41:22.949030+08:00 boston kernel: Switched to NOHz mode on CPU #3
2011-02-09T08:41:31.529031+08:00 boston kernel: [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40000, result 0
2011-02-09T08:41:31.529058+08:00 boston kernel: [drm:intel_crt_detect], CRT not detected via hotplug
2011-02-09T08:41:31.529063+08:00 boston kernel: [drm:output_poll_execute], [CONNECTOR:12:VGA-1] status updated from 2 to 2
2011-02-09T08:41:31.529067+08:00 boston kernel: [drm:output_poll_execute], [CONNECTOR:15:HDMI-A-1] status updated from 2 to 2
2011-02-09T08:41:31.529070+08:00 boston kernel: [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003e
2011-02-09T08:41:31.529072+08:00 boston kernel: [drm:ironlake_dp_detect], DPCD: 0000
2011-02-09T08:41:31.529076+08:00 boston kernel: [drm:output_poll_execute], [CONNECTOR:17:DP-1] status updated from 2 to 2
2011-02-09T08:41:37.286047+08:00 boston kernel: Kernel logging (proc) stopped.


<hang ... rebooted>


2011-02-09T08:42:05.431361+08:00 boston kernel: imklog 5.6.2, log source = /proc/kmsg started.
2011-02-09T08:42:05.431649+08:00 boston kernel: I: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
2011-02-09T08:42:05.431658+08:00 boston kernel: ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1])
2011-02-09T08:42:05.431661+08:00 boston kernel: ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1])
2011-02-09T08:42:05.431667+08:00 boston kernel: ACPI: IOAPIC (id[0x01] address[0xfec00000] gsi_base[0])
2011-02-09T08:42:05.431671+08:00 boston kernel: IOAPIC[0]: apic_id 1, version 32, address 0xfec00000, GSI 0-23
2011-02-09T08:42:05.431674+08:00 boston kernel: ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
2011-02-09T08:42:05.431676+08:00 boston kernel: ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
2011-02-09T08:42:05.431679+08:00 boston kernel: ACPI: IRQ0 used by override.
2011-02-09T08:42:05.431681+08:00 boston kernel: ACPI: IRQ2 used by override.
2011-02-09T08:42:05.431683+08:00 boston kernel: ACPI: IRQ9 used by override.
2011-02-09T08:42:05.431688+08:00 boston kernel: Using ACPI (MADT) for SMP configuration information
2011-02-09T08:42:05.431691+08:00 boston kernel: ACPI: HPET id: 0x8086a701 base: 0xfed00000
2011-02-09T08:42:05.431693+08:00 boston kernel: SMP: Allowing 4 CPUs, 0 hotplug CPUs
2011-02-09T08:42:05.431695+08:00 boston kernel: nr_irqs_gsi: 40
2011-02-09T08:42:05.431697+08:00 boston kernel: PM: Registered nosave memory: 000000000009e000 - 000000000009f000
2011-02-09T08:42:05.431700+08:00 boston kernel: PM: Registered nosave memory: 000000000009f000 - 00000000000a0000
2011-02-09T08:42:05.431703+08:00 boston kernel: PM: Registered nosave memory: 00000000000a0000 - 00000000000dc000
2011-02-09T08:42:05.431705+08:00 boston kernel: PM: Registered nosave memory: 00000000000dc000 - 0000000000100000
2011-02-09T08:42:05.431726+08:00 boston kernel: PM: Registered nosave memory: 00000000bb27c000 - 00000000bb282000
2011-02-09T08:42:05.431731+08:00 boston kernel: PM: Registered nosave memory: 00000000bb35f000 - 00000000bb371000
2011-02-09T08:42:05.431734+08:00 boston kernel: PM: Registered nosave memory: 00000000bb371000 - 00000000bb3f2000
2011-02-09T08:42:05.431737+08:00 boston kernel: PM: Registered nosave memory: 00000000bb3f2000 - 00000000bb40f000
2011-02-09T08:42:05.431740+08:00 boston kernel: PM: Registered nosave memory: 00000000bb46f000 - 00000000bb668000
2011-02-09T08:42:05.431743+08:00 boston kernel: PM: Registered nosave memory: 00000000bb668000 - 00000000bb6e8000
2011-02-09T08:42:05.431746+08:00 boston kernel: PM: Registered nosave memory: 00000000bb6e8000 - 00000000bb70f000
2011-02-09T08:42:05.431751+08:00 boston kernel: PM: Registered nosave memory: 00000000bb717000 - 00000000bb71f000
2011-02-09T08:42:05.431754+08:00 boston kernel: PM: Registered nosave memory: 00000000bb76b000 - 00000000bb777000
2011-02-09T08:42:05.431757+08:00 boston kernel: PM: Registered nosave memory: 00000000bb777000 - 00000000bb77a000
2011-02-09T08:42:05.431759+08:00 boston kernel: PM: Registered nosave memory: 00000000bb77a000 - 00000000bb781000
2011-02-09T08:42:05.431762+08:00 boston kernel: PM: Registered nosave memory: 00000000bb781000 - 00000000bb782000
2011-02-09T08:42:05.431765+08:00 boston kernel: PM: Registered nosave memory: 00000000bb782000 - 00000000bb78b000
2011-02-09T08:42:05.431767+08:00 boston kernel: PM: Registered nosave memory: 00000000bb78b000 - 00000000bb78c000
2011-02-09T08:42:05.431770+08:00 boston kernel: PM: Registered nosave memory: 00000000bb78c000 - 00000000bb79f000
2011-02-09T08:42:05.431775+08:00 boston kernel: PM: Registered nosave memory: 00000000bb79f000 - 00000000bb7ff000
2011-02-09T08:42:05.431777+08:00 boston kernel: PM: Registered nosave memory: 00000000bb800000 - 00000000c0000000
2011-02-09T08:42:05.431780+08:00 boston kernel: PM: Registered nosave memory: 00000000c0000000 - 00000000e0000000
2011-02-09T08:42:05.431783+08:00 boston kernel: PM: Registered nosave memory: 00000000e0000000 - 00000000f0000000
2011-02-09T08:42:05.431786+08:00 boston kernel: PM: Registered nosave memory: 00000000f0000000 - 00000000feaff000
2011-02-09T08:42:05.431788+08:00 boston kernel: PM: Registered nosave memory: 00000000feaff000 - 00000000feb00000
2011-02-09T08:42:05.431791+08:00 boston kernel: PM: Registered nosave memory: 00000000feb00000 - 00000000fec00000
2011-02-09T08:42:05.431796+08:00 boston kernel: PM: Registered nosave memory: 00000000fec00000 - 00000000fec10000
2011-02-09T08:42:05.431799+08:00 boston kernel: PM: Registered nosave memory: 00000000fec10000 - 00000000fed00000
2011-02-09T08:42:05.431801+08:00 boston kernel: PM: Registered nosave memory: 00000000fed00000 - 00000000fed1c000
2011-02-09T08:42:05.431803+08:00 boston kernel: PM: Registered nosave memory: 00000000fed1c000 - 00000000fed90000
2011-02-09T08:42:05.431806+08:00 boston kernel: PM: Registered nosave memory: 00000000fed90000 - 00000000fee00000
2011-02-09T08:42:05.431809+08:00 boston kernel: PM: Registered nosave memory: 00000000fee00000 - 00000000fee01000
2011-02-09T08:42:05.431811+08:00 boston kernel: PM: Registered nosave memory: 00000000fee01000 - 00000000ff000000
2011-02-09T08:42:05.431817+08:00 boston kernel: PM: Registered nosave memory: 00000000ff000000 - 0000000100000000
2011-02-09T08:42:05.431821+08:00 boston kernel: PM: Registered nosave memory: 00000001fc000000 - 0000000200000000
2011-02-09T08:42:05.431823+08:00 boston kernel: Allocating PCI resources starting at c0000000 (gap: c0000000:20000000)
2011-02-09T08:42:05.431827+08:00 boston kernel: Booting paravirtualized kernel on bare hardware
2011-02-09T08:42:05.431831+08:00 boston kernel: setup_percpu: NR_CPUS:16 nr_cpumask_bits:16 nr_cpu_ids:4 nr_node_ids:1
2011-02-09T08:42:05.431834+08:00 boston kernel: PERCPU: Embedded 26 pages/cpu @ffff8800bb000000 s75392 r8192 d22912 u524288
2011-02-09T08:42:05.431837+08:00 boston kernel: pcpu-alloc: s75392 r8192 d22912 u524288 alloc=1*2097152
2011-02-09T08:42:05.431843+08:00 boston kernel: pcpu-alloc: [0] 0 1 2 3 
2011-02-09T08:42:05.431849+08:00 boston kernel: Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 2012790
2011-02-09T08:42:05.431851+08:00 boston kernel: Policy zone: Normal
2011-02-09T08:42:05.431858+08:00 boston kernel: Kernel command line: BOOT_IMAGE=(hd0,14)/linux/bzc1 root=/dev/sda2 ro resume=/dev/sda3 reboot=bios mce x11 snd-hda-intel.model=lenovo-x200 nf_conntrack_sip.sip_direct_signalling=0 nf_conntrack_sip.sip_direct_media=0 testing_only=\"this is got to be good. Now I can send in a very long line just like 2.4 and need not worry about the line being too long. What a great way to start a great year!!! Cool!\"
2011-02-09T08:42:05.431861+08:00 boston kernel: PID hash table entries: 4096 (order: 3, 32768 bytes)
2011-02-09T08:42:05.431863+08:00 boston kernel: Checking aperture...
2011-02-09T08:42:05.431866+08:00 boston kernel: No AGP bridge found
2011-02-09T08:42:05.432004+08:00 boston kernel: Memory: 7989592k/9371648k available (4737k kernel code, 1192336k absent, 189720k reserved, 2573k data, 576k init)
2011-02-09T08:42:05.432009+08:00 boston kernel: SLUB: Genslabs=15, HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
2011-02-09T08:42:05.432011+08:00 boston kernel: Preemptable hierarchical RCU implementation.
2011-02-09T08:42:05.432014+08:00 boston kernel: 	CONFIG_RCU_FANOUT set to non-default value of 32
2011-02-09T08:42:05.432017+08:00 boston kernel: 	RCU-based detection of stalled CPUs is disabled.
2011-02-09T08:42:05.432019+08:00 boston kernel: 	Verbose stalled-CPUs detection is disabled.
2011-02-09T08:42:05.432021+08:00 boston kernel: NR_IRQS:768
2011-02-09T08:42:05.432026+08:00 boston kernel: Extended CMOS year: 2000
2011-02-09T08:42:05.432029+08:00 boston kernel: Console: colour dummy device 80x25
2011-02-09T08:42:05.432031+08:00 boston kernel: console [tty0] enabled
2011-02-09T08:42:05.432033+08:00 boston kernel: hpet clockevent registered
2011-02-09T08:42:05.432035+08:00 boston kernel: Fast TSC calibration using PIT
2011-02-09T08:42:05.432038+08:00 boston kernel: Detected 2128.469 MHz processor.
2011-02-09T08:42:05.432041+08:00 boston kernel: Calibrating delay loop (skipped), value calculated using timer frequency.. 4256.93 BogoMIPS (lpj=21284690)
2011-02-09T08:42:05.432048+08:00 boston kernel: pid_max: default: 32768 minimum: 301
2011-02-09T08:42:05.432051+08:00 boston kernel: Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes)
2011-02-09T08:42:05.432054+08:00 boston kernel: Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes)
2011-02-09T08:42:05.432056+08:00 boston kernel: Mount-cache hash table entries: 256
2011-02-09T08:42:05.432058+08:00 boston kernel: CPU: Physical Processor ID: 0
2011-02-09T08:42:05.432060+08:00 boston kernel: CPU: Processor Core ID: 0
2011-02-09T08:42:05.432063+08:00 boston kernel: mce: CPU supports 9 MCE banks
2011-02-09T08:42:05.432065+08:00 boston kernel: CPU0: Thermal monitoring enabled (TM1)
2011-02-09T08:42:05.432069+08:00 boston kernel: using mwait in idle threads.
2011-02-09T08:42:05.432072+08:00 boston kernel: ACPI: Core revision 20110112
2011-02-09T08:42:05.432074+08:00 boston kernel: Setting APIC routing to flat
2011-02-09T08:42:05.432076+08:00 boston kernel: ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
2011-02-09T08:42:05.432079+08:00 boston kernel: CPU0: Intel(R) Core(TM) i7 CPU       L 640  @ 2.13GHz stepping 02
2011-02-09T08:42:05.432082+08:00 boston kernel: Performance Events: PEBS fmt1+, Westmere events, Intel PMU driver.
2011-02-09T08:42:05.432084+08:00 boston kernel: ... version:                3
2011-02-09T08:42:05.432086+08:00 boston kernel: ... bit width:              48
2011-02-09T08:42:05.432090+08:00 boston kernel: ... generic registers:      4
2011-02-09T08:42:05.432093+08:00 boston kernel: ... value mask:             0000ffffffffffff
2011-02-09T08:42:05.432095+08:00 boston kernel: ... max period:             000000007fffffff
2011-02-09T08:42:05.432098+08:00 boston kernel: ... fixed-purpose events:   3
2011-02-09T08:42:05.432101+08:00 boston kernel: ... event mask:             000000070000000f
2011-02-09T08:42:05.432103+08:00 boston kernel: Booting Node   0, Processors  #1 #2 #3 Ok.
2011-02-09T08:42:05.432105+08:00 boston kernel: Brought up 4 CPUs
2011-02-09T08:42:05.432110+08:00 boston kernel: Total of 4 processors activated (17024.85 BogoMIPS).
2011-02-09T08:42:05.432113+08:00 boston kernel: NET: Registered protocol family 16
2011-02-09T08:42:05.432116+08:00 boston kernel: ACPI FADT declares the system doesn't support PCIe ASPM, so disable it
2011-02-09T08:42:05.432119+08:00 boston kernel: ACPI: bus type pci registered
2011-02-09T08:42:05.432121+08:00 boston kernel: PCI: Using configuration type 1 for base access
2011-02-09T08:42:05.432135+08:00 boston kernel: bio: create slab <bio-0> at 0
2011-02-09T08:42:05.432140+08:00 boston kernel: ACPI: EC: EC description table is found, configuring boot EC
2011-02-09T08:42:05.432143+08:00 boston kernel: [Firmware Bug]: ACPI: BIOS _OSI(Linux) query ignored
2011-02-09T08:42:05.432146+08:00 boston kernel: ACPI: SSDT 00000000bb71a918 003EB (v01  PmRef  Cpu0Ist 00003000 INTL 20050513)
2011-02-09T08:42:05.432149+08:00 boston kernel: ACPI: Dynamic OEM Table Load:
2011-02-09T08:42:05.432154+08:00 boston kernel: ACPI: SSDT           (null) 003EB (v01  PmRef  Cpu0Ist 00003000 INTL 20050513)
2011-02-09T08:42:05.432158+08:00 boston kernel: ACPI: SSDT 00000000bb718718 006B2 (v01  PmRef  Cpu0Cst 00003001 INTL 20050513)
2011-02-09T08:42:05.432160+08:00 boston kernel: ACPI: Dynamic OEM Table Load:
2011-02-09T08:42:05.432163+08:00 boston kernel: ACPI: SSDT           (null) 006B2 (v01  PmRef  Cpu0Cst 00003001 INTL 20050513)
2011-02-09T08:42:05.432166+08:00 boston kernel: ACPI: SSDT 00000000bb719a98 00303 (v01  PmRef    ApIst 00003000 INTL 20050513)
2011-02-09T08:42:05.432168+08:00 boston kernel: ACPI: Dynamic OEM Table Load:
2011-02-09T08:42:05.432171+08:00 boston kernel: ACPI: SSDT           (null) 00303 (v01  PmRef    ApIst 00003000 INTL 20050513)
2011-02-09T08:42:05.432177+08:00 boston kernel: ACPI: SSDT 00000000bb717d98 00119 (v01  PmRef    ApCst 00003000 INTL 20050513)
2011-02-09T08:42:05.432180+08:00 boston kernel: ACPI: Dynamic OEM Table Load:
2011-02-09T08:42:05.432183+08:00 boston kernel: ACPI: SSDT           (null) 00119 (v01  PmRef    ApCst 00003000 INTL 20050513)
2011-02-09T08:42:05.432186+08:00 boston kernel: ACPI: Interpreter enabled
2011-02-09T08:42:05.432189+08:00 boston kernel: ACPI: (supports S0 S3 S4 S5)
2011-02-09T08:42:05.432191+08:00 boston kernel: ACPI: Using IOAPIC for interrupt routing
2011-02-09T08:42:05.432193+08:00 boston kernel: ACPI: Power Resource [PUBS] (on)
2011-02-09T08:42:05.432196+08:00 boston kernel: ACPI: EC: GPE = 0x11, I/O: command/status = 0x66, data = 0x62
2011-02-09T08:42:05.432202+08:00 boston kernel: ACPI: ACPI Dock Station Driver: 3 docks/bays found
2011-02-09T08:42:05.432204+08:00 boston kernel: HEST: Table not found.
2011-02-09T08:42:05.432208+08:00 boston kernel: PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
2011-02-09T08:42:05.432211+08:00 boston kernel: ACPI: PCI Root Bridge [UNCR] (domain 0000 [bus ff])
2011-02-09T08:42:05.432213+08:00 boston kernel: pci 0000:ff:00.0: [8086:2c62] type 0 class 0x000600
2011-02-09T08:42:05.432216+08:00 boston kernel: pci 0000:ff:00.1: [8086:2d01] type 0 class 0x000600
2011-02-09T08:42:05.432218+08:00 boston kernel: pci 0000:ff:02.0: [8086:2d10] type 0 class 0x000600
2011-02-09T08:42:05.432224+08:00 boston kernel: pci 0000:ff:02.1: [8086:2d11] type 0 class 0x000600
2011-02-09T08:42:05.432226+08:00 boston kernel: pci 0000:ff:02.2: [8086:2d12] type 0 class 0x000600
2011-02-09T08:42:05.432229+08:00 boston kernel: pci 0000:ff:02.3: [8086:2d13] type 0 class 0x000600
2011-02-09T08:42:05.432232+08:00 boston kernel: ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-fe])
2011-02-09T08:42:05.432235+08:00 boston kernel: pci_root PNP0A08:00: host bridge window [io  0x0000-0x0cf7]
2011-02-09T08:42:05.432238+08:00 boston kernel: pci_root PNP0A08:00: host bridge window [io  0x0d00-0xffff]
2011-02-09T08:42:05.432241+08:00 boston kernel: pci_root PNP0A08:00: host bridge window [mem 0x000a0000-0x000bffff]
2011-02-09T08:42:05.432244+08:00 boston kernel: pci_root PNP0A08:00: host bridge window [mem 0x000d0000-0x000d3fff]
2011-02-09T08:42:05.432249+08:00 boston kernel: pci_root PNP0A08:00: host bridge window [mem 0x000d4000-0x000d7fff]
2011-02-09T08:42:05.432264+08:00 boston kernel: pci_root PNP0A08:00: host bridge window [mem 0x000d8000-0x000dbfff]
2011-02-09T08:42:05.432423+08:00 boston kernel: pci_root PNP0A08:00: host bridge window [mem 0xc0000000-0xfebfffff]
2011-02-09T08:42:05.432429+08:00 boston kernel: pci 0000:00:00.0: [8086:0044] type 0 class 0x000600
2011-02-09T08:42:05.432432+08:00 boston kernel: pci 0000:00:02.0: [8086:0046] type 0 class 0x000300
2011-02-09T08:42:05.432435+08:00 boston kernel: pci 0000:00:02.0: reg 10: [mem 0xf2000000-0xf23fffff 64bit]
2011-02-09T08:42:05.432438+08:00 boston kernel: pci 0000:00:02.0: reg 18: [mem 0xd0000000-0xdfffffff 64bit pref]
2011-02-09T08:42:05.432441+08:00 boston kernel: pci 0000:00:02.0: reg 20: [io  0x1800-0x1807]
2011-02-09T08:42:05.432444+08:00 boston kernel: pci 0000:00:16.0: [8086:3b64] type 0 class 0x000780
2011-02-09T08:42:05.432446+08:00 boston kernel: pci 0000:00:16.0: reg 10: [mem 0xf2727800-0xf272780f 64bit]
2011-02-09T08:42:05.432449+08:00 boston kernel: pci 0000:00:16.0: PME# supported from D0 D3hot D3cold
2011-02-09T08:42:05.432451+08:00 boston kernel: pci 0000:00:16.0: PME# disabled
2011-02-09T08:42:05.432454+08:00 boston kernel: pci 0000:00:19.0: [8086:10ea] type 0 class 0x000200
2011-02-09T08:42:05.432457+08:00 boston kernel: pci 0000:00:19.0: reg 10: [mem 0xf2500000-0xf251ffff]
2011-02-09T08:42:05.432460+08:00 boston kernel: pci 0000:00:19.0: reg 14: [mem 0xf2525000-0xf2525fff]
2011-02-09T08:42:05.432463+08:00 boston kernel: pci 0000:00:19.0: reg 18: [io  0x1820-0x183f]
2011-02-09T08:42:05.432465+08:00 boston kernel: pci 0000:00:19.0: PME# supported from D0 D3hot D3cold
2011-02-09T08:42:05.432468+08:00 boston kernel: pci 0000:00:19.0: PME# disabled
2011-02-09T08:42:05.432470+08:00 boston kernel: pci 0000:00:1a.0: [8086:3b3c] type 0 class 0x000c03
2011-02-09T08:42:05.432473+08:00 boston kernel: pci 0000:00:1a.0: reg 10: [mem 0xf2728000-0xf27283ff]
2011-02-09T08:42:05.432476+08:00 boston kernel: pci 0000:00:1a.0: PME# supported from D0 D3hot D3cold
2011-02-09T08:42:05.432478+08:00 boston kernel: pci 0000:00:1a.0: PME# disabled
2011-02-09T08:42:05.432481+08:00 boston kernel: pci 0000:00:1b.0: [8086:3b56] type 0 class 0x000403
2011-02-09T08:42:05.432484+08:00 boston kernel: pci 0000:00:1b.0: reg 10: [mem 0xf2520000-0xf2523fff 64bit]
2011-02-09T08:42:05.432486+08:00 boston kernel: pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold
2011-02-09T08:42:05.432489+08:00 boston kernel: pci 0000:00:1b.0: PME# disabled
2011-02-09T08:42:05.432492+08:00 boston kernel: pci 0000:00:1c.0: [8086:3b42] type 1 class 0x000604
2011-02-09T08:42:05.432494+08:00 boston kernel: pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
2011-02-09T08:42:05.432497+08:00 boston kernel: pci 0000:00:1c.0: PME# disabled
2011-02-09T08:42:05.432499+08:00 boston kernel: pci 0000:00:1c.3: [8086:3b48] type 1 class 0x000604
2011-02-09T08:42:05.432515+08:00 boston kernel: pci 0000:00:1c.3: PME# supported from D0 D3hot D3cold
2011-02-09T08:42:05.432519+08:00 boston kernel: pci 0000:00:1c.3: PME# disabled
2011-02-09T08:42:05.432521+08:00 boston kernel: pci 0000:00:1c.4: [8086:3b4a] type 1 class 0x000604
2011-02-09T08:42:05.432524+08:00 boston kernel: pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold
2011-02-09T08:42:05.432527+08:00 boston kernel: pci 0000:00:1c.4: PME# disabled
2011-02-09T08:42:05.432529+08:00 boston kernel: pci 0000:00:1d.0: [8086:3b34] type 0 class 0x000c03
2011-02-09T08:42:05.432532+08:00 boston kernel: pci 0000:00:1d.0: reg 10: [mem 0xf2728400-0xf27287ff]
2011-02-09T08:42:05.432534+08:00 boston kernel: pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold
2011-02-09T08:42:05.432537+08:00 boston kernel: pci 0000:00:1d.0: PME# disabled
2011-02-09T08:42:05.432540+08:00 boston kernel: pci 0000:00:1e.0: [8086:2448] type 1 class 0x000604
2011-02-09T08:42:05.432543+08:00 boston kernel: pci 0000:00:1f.0: [8086:3b07] type 0 class 0x000601
2011-02-09T08:42:05.432545+08:00 boston kernel: pci 0000:00:1f.2: [8086:3b2f] type 0 class 0x000106
2011-02-09T08:42:05.432548+08:00 boston kernel: pci 0000:00:1f.2: reg 10: [io  0x1860-0x1867]
2011-02-09T08:42:05.432551+08:00 boston kernel: pci 0000:00:1f.2: reg 14: [io  0x1814-0x1817]
2011-02-09T08:42:05.432554+08:00 boston kernel: pci 0000:00:1f.2: reg 18: [io  0x1818-0x181f]
2011-02-09T08:42:05.432556+08:00 boston kernel: pci 0000:00:1f.2: reg 1c: [io  0x1810-0x1813]
2011-02-09T08:42:05.432559+08:00 boston kernel: pci 0000:00:1f.2: reg 20: [io  0x1840-0x185f]
2011-02-09T08:42:05.432562+08:00 boston kernel: pci 0000:00:1f.2: reg 24: [mem 0xf2727000-0xf27277ff]
2011-02-09T08:42:05.432565+08:00 boston kernel: pci 0000:00:1f.2: PME# supported from D3hot
2011-02-09T08:42:05.432567+08:00 boston kernel: pci 0000:00:1f.2: PME# disabled
2011-02-09T08:42:05.432570+08:00 boston kernel: pci 0000:00:1f.3: [8086:3b30] type 0 class 0x000c05
2011-02-09T08:42:05.432573+08:00 boston kernel: pci 0000:00:1f.3: reg 10: [mem 0xf2728800-0xf27288ff 64bit]
2011-02-09T08:42:05.432575+08:00 boston kernel: pci 0000:00:1f.3: reg 20: [io  0x1880-0x189f]
2011-02-09T08:42:05.432578+08:00 boston kernel: pci 0000:00:1f.6: [8086:3b32] type 0 class 0x001180
2011-02-09T08:42:05.432580+08:00 boston kernel: pci 0000:00:1f.6: reg 10: [mem 0xf2526000-0xf2526fff 64bit]
2011-02-09T08:42:05.432583+08:00 boston kernel: pci 0000:00:1c.0: PCI bridge to [bus 0d-0d]
2011-02-09T08:42:05.432586+08:00 boston kernel: pci 0000:00:1c.0:   bridge window [io  0xf000-0x0000] (disabled)
2011-02-09T08:42:05.432589+08:00 boston kernel: pci 0000:00:1c.0:   bridge window [mem 0xfff00000-0x000fffff] (disabled)
2011-02-09T08:42:05.432592+08:00 boston kernel: pci 0000:00:1c.0:   bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
2011-02-09T08:42:05.432595+08:00 boston kernel: pci 0000:00:1c.3: PCI bridge to [bus 05-0c]
2011-02-09T08:42:05.432598+08:00 boston kernel: pci 0000:00:1c.3:   bridge window [io  0x2000-0x2fff]
2011-02-09T08:42:05.432600+08:00 boston kernel: pci 0000:00:1c.3:   bridge window [mem 0xf0000000-0xf1ffffff]
2011-02-09T08:42:05.432603+08:00 boston kernel: pci 0000:00:1c.3:   bridge window [mem 0xf2800000-0xf28fffff 64bit pref]
2011-02-09T08:42:05.432606+08:00 boston kernel: pci 0000:02:00.0: [8086:4239] type 0 class 0x000280
2011-02-09T08:42:05.432609+08:00 boston kernel: pci 0000:02:00.0: reg 10: [mem 0xf2400000-0xf2401fff 64bit]
2011-02-09T08:42:05.432611+08:00 boston kernel: pci 0000:02:00.0: PME# supported from D0 D3hot D3cold
2011-02-09T08:42:05.432614+08:00 boston kernel: pci 0000:02:00.0: PME# disabled
2011-02-09T08:42:05.432616+08:00 boston kernel: pci 0000:00:1c.4: PCI bridge to [bus 02-02]
2011-02-09T08:42:05.432619+08:00 boston kernel: pci 0000:00:1c.4:   bridge window [io  0xf000-0x0000] (disabled)
2011-02-09T08:42:05.432622+08:00 boston kernel: pci 0000:00:1c.4:   bridge window [mem 0xf2400000-0xf24fffff]
2011-02-09T08:42:05.432625+08:00 boston kernel: pci 0000:00:1c.4:   bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
2011-02-09T08:42:05.432628+08:00 boston kernel: pci 0000:00:1e.0: PCI bridge to [bus 0e-0e] (subtractive decode)
2011-02-09T08:42:05.432631+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [io  0xf000-0x0000] (disabled)
2011-02-09T08:42:05.432646+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem 0xfff00000-0x000fffff] (disabled)
2011-02-09T08:42:05.432650+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
2011-02-09T08:42:05.432810+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [io  0x0000-0x0cf7] (subtractive decode)
2011-02-09T08:42:05.432816+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [io  0x0d00-0xffff] (subtractive decode)
2011-02-09T08:42:05.432819+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem 0x000a0000-0x000bffff] (subtractive decode)
2011-02-09T08:42:05.432822+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem 0x000d0000-0x000d3fff] (subtractive decode)
2011-02-09T08:42:05.432825+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem 0x000d4000-0x000d7fff] (subtractive decode)
2011-02-09T08:42:05.432828+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem 0x000d8000-0x000dbfff] (subtractive decode)
2011-02-09T08:42:05.432831+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem 0xc0000000-0xfebfffff] (subtractive decode)
2011-02-09T08:42:05.432834+08:00 boston kernel: ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
2011-02-09T08:42:05.432837+08:00 boston kernel: ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.EXP1._PRT]
2011-02-09T08:42:05.432839+08:00 boston kernel: ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.EXP4._PRT]
2011-02-09T08:42:05.432842+08:00 boston kernel: ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.EXP5._PRT]
2011-02-09T08:42:05.432845+08:00 boston kernel: ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 9 10 *11)
2011-02-09T08:42:05.432848+08:00 boston kernel: ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 9 10 *11)
2011-02-09T08:42:05.432851+08:00 boston kernel: ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 9 10 11) *0, disabled.
2011-02-09T08:42:05.432867+08:00 boston kernel: ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 9 10 *11)
2011-02-09T08:42:05.432871+08:00 boston kernel: ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 9 10 *11)
2011-02-09T08:42:05.432874+08:00 boston kernel: ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 9 10 11) *0, disabled.
2011-02-09T08:42:05.432877+08:00 boston kernel: ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 9 10 11) *0, disabled.
2011-02-09T08:42:05.432880+08:00 boston kernel: ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 9 10 *11)
2011-02-09T08:42:05.432883+08:00 boston kernel: vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none
2011-02-09T08:42:05.432885+08:00 boston kernel: vgaarb: loaded
2011-02-09T08:42:05.432887+08:00 boston kernel: SCSI subsystem initialized
2011-02-09T08:42:05.432890+08:00 boston kernel: libata version 3.00 loaded.
2011-02-09T08:42:05.432893+08:00 boston kernel: usbcore: registered new interface driver usbfs
2011-02-09T08:42:05.432895+08:00 boston kernel: usbcore: registered new interface driver hub
2011-02-09T08:42:05.432897+08:00 boston kernel: usbcore: registered new device driver usb
2011-02-09T08:42:05.432900+08:00 boston kernel: Advanced Linux Sound Architecture Driver Version 1.0.23.
2011-02-09T08:42:05.432903+08:00 boston kernel: PCI: Using ACPI for IRQ routing
2011-02-09T08:42:05.432906+08:00 boston kernel: PCI: pci_cache_line_size set to 64 bytes
2011-02-09T08:42:05.432909+08:00 boston kernel: reserve RAM buffer: 000000000009e800 - 000000000009ffff 
2011-02-09T08:42:05.432912+08:00 boston kernel: reserve RAM buffer: 00000000bb27c000 - 00000000bbffffff 
2011-02-09T08:42:05.432915+08:00 boston kernel: reserve RAM buffer: 00000000bb35f000 - 00000000bbffffff 
2011-02-09T08:42:05.432917+08:00 boston kernel: reserve RAM buffer: 00000000bb46f000 - 00000000bbffffff 
2011-02-09T08:42:05.432920+08:00 boston kernel: reserve RAM buffer: 00000000bb717000 - 00000000bbffffff 
2011-02-09T08:42:05.432922+08:00 boston kernel: reserve RAM buffer: 00000000bb76b000 - 00000000bbffffff 
2011-02-09T08:42:05.432925+08:00 boston kernel: reserve RAM buffer: 00000000bb800000 - 00000000bbffffff 
2011-02-09T08:42:05.432927+08:00 boston kernel: Switching to clocksource hpet
2011-02-09T08:42:05.432930+08:00 boston kernel: pnp: PnP ACPI init
2011-02-09T08:42:05.432932+08:00 boston kernel: ACPI: bus type pnp registered
2011-02-09T08:42:05.432935+08:00 boston kernel: pnp 00:00: [mem 0x00000000-0x0009ffff]
2011-02-09T08:42:05.432937+08:00 boston kernel: pnp 00:00: [mem 0x000c0000-0x000c3fff]
2011-02-09T08:42:05.432940+08:00 boston kernel: pnp 00:00: [mem 0x000c4000-0x000c7fff]
2011-02-09T08:42:05.432943+08:00 boston kernel: pnp 00:00: [mem 0x000c8000-0x000cbfff]
2011-02-09T08:42:05.432945+08:00 boston kernel: pnp 00:00: [mem 0x000cc000-0x000cffff]
2011-02-09T08:42:05.432948+08:00 boston kernel: pnp 00:00: [mem 0x000d0000-0x000cffff disabled]
2011-02-09T08:42:05.432950+08:00 boston kernel: pnp 00:00: [mem 0x000d4000-0x000d3fff disabled]
2011-02-09T08:42:05.432953+08:00 boston kernel: pnp 00:00: [mem 0x000d8000-0x000d7fff disabled]
2011-02-09T08:42:05.432955+08:00 boston kernel: pnp 00:00: [mem 0x000dc000-0x000dffff]
2011-02-09T08:42:05.432958+08:00 boston kernel: pnp 00:00: [mem 0x000e0000-0x000e3fff]
2011-02-09T08:42:05.432961+08:00 boston kernel: pnp 00:00: [mem 0x000e4000-0x000e7fff]
2011-02-09T08:42:05.432963+08:00 boston kernel: pnp 00:00: [mem 0x000e8000-0x000ebfff]
2011-02-09T08:42:05.432966+08:00 boston kernel: pnp 00:00: [mem 0x000ec000-0x000effff]
2011-02-09T08:42:05.432968+08:00 boston kernel: pnp 00:00: [mem 0x000f0000-0x000fffff]
2011-02-09T08:42:05.432971+08:00 boston kernel: pnp 00:00: [mem 0x00100000-0xbfffffff]
2011-02-09T08:42:05.432973+08:00 boston kernel: pnp 00:00: [mem 0xfec00000-0xfed3ffff]
2011-02-09T08:42:05.432976+08:00 boston kernel: pnp 00:00: [mem 0xfed4c000-0xffffffff]
2011-02-09T08:42:05.432978+08:00 boston kernel: system 00:00: [mem 0x00000000-0x0009ffff] could not be reserved
2011-02-09T08:42:05.432981+08:00 boston kernel: system 00:00: [mem 0x000c0000-0x000c3fff] has been reserved
2011-02-09T08:42:05.432996+08:00 boston kernel: system 00:00: [mem 0x000c4000-0x000c7fff] has been reserved
2011-02-09T08:42:05.433000+08:00 boston kernel: system 00:00: [mem 0x000c8000-0x000cbfff] has been reserved
2011-02-09T08:42:05.433003+08:00 boston kernel: system 00:00: [mem 0x000cc000-0x000cffff] has been reserved
2011-02-09T08:42:05.433006+08:00 boston kernel: system 00:00: [mem 0x000dc000-0x000dffff] could not be reserved
2011-02-09T08:42:05.433009+08:00 boston kernel: system 00:00: [mem 0x000e0000-0x000e3fff] could not be reserved
2011-02-09T08:42:05.433012+08:00 boston kernel: system 00:00: [mem 0x000e4000-0x000e7fff] could not be reserved
2011-02-09T08:42:05.433014+08:00 boston kernel: system 00:00: [mem 0x000e8000-0x000ebfff] could not be reserved
2011-02-09T08:42:05.433017+08:00 boston kernel: system 00:00: [mem 0x000ec000-0x000effff] could not be reserved
2011-02-09T08:42:05.433020+08:00 boston kernel: system 00:00: [mem 0x000f0000-0x000fffff] could not be reserved
2011-02-09T08:42:05.433023+08:00 boston kernel: system 00:00: [mem 0x00100000-0xbfffffff] could not be reserved
2011-02-09T08:42:05.433026+08:00 boston kernel: system 00:00: [mem 0xfec00000-0xfed3ffff] could not be reserved
2011-02-09T08:42:05.433029+08:00 boston kernel: system 00:00: [mem 0xfed4c000-0xffffffff] could not be reserved
2011-02-09T08:42:05.433032+08:00 boston kernel: system 00:00: Plug and Play ACPI device, IDs PNP0c01 (active)
2011-02-09T08:42:05.433034+08:00 boston kernel: pnp 00:01: [bus ff]
2011-02-09T08:42:05.433037+08:00 boston kernel: pnp 00:01: Plug and Play ACPI device, IDs PNP0a03 (active)
2011-02-09T08:42:05.433040+08:00 boston kernel: pnp 00:02: [bus 00-fe]
2011-02-09T08:42:05.433199+08:00 boston kernel: pnp 00:02: [io  0x0cf8-0x0cff]
2011-02-09T08:42:05.433204+08:00 boston kernel: pnp 00:02: [io  0x0000-0x0cf7 window]
2011-02-09T08:42:05.433207+08:00 boston kernel: pnp 00:02: [io  0x0d00-0xffff window]
2011-02-09T08:42:05.433209+08:00 boston kernel: pnp 00:02: [mem 0x000a0000-0x000bffff window]
2011-02-09T08:42:05.433212+08:00 boston kernel: pnp 00:02: [mem 0x000c0000-0x000c3fff window]
2011-02-09T08:42:05.433214+08:00 boston kernel: pnp 00:02: [mem 0x000c4000-0x000c7fff window]
2011-02-09T08:42:05.433217+08:00 boston kernel: pnp 00:02: [mem 0x000c8000-0x000cbfff window]
2011-02-09T08:42:05.433231+08:00 boston kernel: pnp 00:02: [mem 0x000cc000-0x000cffff window]
2011-02-09T08:42:05.433235+08:00 boston kernel: pnp 00:02: [mem 0x000d0000-0x000d3fff window]
2011-02-09T08:42:05.433238+08:00 boston kernel: pnp 00:02: [mem 0x000d4000-0x000d7fff window]
2011-02-09T08:42:05.433240+08:00 boston kernel: pnp 00:02: [mem 0x000d8000-0x000dbfff window]
2011-02-09T08:42:05.433243+08:00 boston kernel: pnp 00:02: [mem 0x000dc000-0x000dffff window]
2011-02-09T08:42:05.433245+08:00 boston kernel: pnp 00:02: [mem 0x000e0000-0x000e3fff window]
2011-02-09T08:42:05.433248+08:00 boston kernel: pnp 00:02: [mem 0x000e4000-0x000e7fff window]
2011-02-09T08:42:05.433250+08:00 boston kernel: pnp 00:02: [mem 0x000e8000-0x000ebfff window]
2011-02-09T08:42:05.433253+08:00 boston kernel: pnp 00:02: [mem 0x000ec000-0x000effff window]
2011-02-09T08:42:05.433255+08:00 boston kernel: pnp 00:02: [mem 0xc0000000-0xfebfffff window]
2011-02-09T08:42:05.433258+08:00 boston kernel: pnp 00:02: [mem 0xfed40000-0xfed4bfff window]
2011-02-09T08:42:05.433261+08:00 boston kernel: pnp 00:02: Plug and Play ACPI device, IDs PNP0a08 PNP0a03 (active)
2011-02-09T08:42:05.433266+08:00 boston kernel: pnp 00:03: [io  0x0010-0x001f]
2011-02-09T08:42:05.433269+08:00 boston kernel: pnp 00:03: [io  0x0090-0x009f]
2011-02-09T08:42:05.433271+08:00 boston kernel: pnp 00:03: [io  0x0024-0x0025]
2011-02-09T08:42:05.433274+08:00 boston kernel: pnp 00:03: [io  0x0028-0x0029]
2011-02-09T08:42:05.433276+08:00 boston kernel: pnp 00:03: [io  0x002c-0x002d]
2011-02-09T08:42:05.433279+08:00 boston kernel: pnp 00:03: [io  0x0030-0x0031]
2011-02-09T08:42:05.433281+08:00 boston kernel: pnp 00:03: [io  0x0034-0x0035]
2011-02-09T08:42:05.433284+08:00 boston kernel: pnp 00:03: [io  0x0038-0x0039]
2011-02-09T08:42:05.433286+08:00 boston kernel: pnp 00:03: [io  0x003c-0x003d]
2011-02-09T08:42:05.433289+08:00 boston kernel: pnp 00:03: [io  0x00a4-0x00a5]
2011-02-09T08:42:05.433291+08:00 boston kernel: pnp 00:03: [io  0x00a8-0x00a9]
2011-02-09T08:42:05.433293+08:00 boston kernel: pnp 00:03: [io  0x00ac-0x00ad]
2011-02-09T08:42:05.433296+08:00 boston kernel: pnp 00:03: [io  0x00b0-0x00b5]
2011-02-09T08:42:05.433298+08:00 boston kernel: pnp 00:03: [io  0x00b8-0x00b9]
2011-02-09T08:42:05.433300+08:00 boston kernel: pnp 00:03: [io  0x00bc-0x00bd]
2011-02-09T08:42:05.433303+08:00 boston kernel: pnp 00:03: [io  0x0050-0x0053]
2011-02-09T08:42:05.433305+08:00 boston kernel: pnp 00:03: [io  0x0072-0x0077]
2011-02-09T08:42:05.433308+08:00 boston kernel: pnp 00:03: [io  0x164e-0x164f]
2011-02-09T08:42:05.433310+08:00 boston kernel: pnp 00:03: [io  0x002e-0x002f]
2011-02-09T08:42:05.433319+08:00 boston kernel: pnp 00:03: [io  0x1000-0x107f]
2011-02-09T08:42:05.433322+08:00 boston kernel: pnp 00:03: [io  0x1180-0x11ff]
2011-02-09T08:42:05.433325+08:00 boston kernel: pnp 00:03: [io  0x0800-0x080f]
2011-02-09T08:42:05.433327+08:00 boston kernel: pnp 00:03: [io  0x15e0-0x15ef]
2011-02-09T08:42:05.433330+08:00 boston kernel: pnp 00:03: [io  0x1600-0x1641]
2011-02-09T08:42:05.433332+08:00 boston kernel: pnp 00:03: [io  0x1644-0x167f]
2011-02-09T08:42:05.433335+08:00 boston kernel: pnp 00:03: [mem 0xe0000000-0xefffffff]
2011-02-09T08:42:05.433338+08:00 boston kernel: pnp 00:03: [mem 0xfeaff000-0xfeafffff]
2011-02-09T08:42:05.433340+08:00 boston kernel: pnp 00:03: [mem 0xfed1c000-0xfed1ffff]
2011-02-09T08:42:05.433342+08:00 boston kernel: pnp 00:03: [mem 0xfed10000-0xfed13fff]
2011-02-09T08:42:05.433345+08:00 boston kernel: pnp 00:03: [mem 0xfed18000-0xfed18fff]
2011-02-09T08:42:05.433347+08:00 boston kernel: pnp 00:03: [mem 0xfed19000-0xfed19fff]
2011-02-09T08:42:05.433350+08:00 boston kernel: pnp 00:03: [mem 0xfed45000-0xfed4bfff]
2011-02-09T08:42:05.433353+08:00 boston kernel: system 00:03: [io  0x164e-0x164f] has been reserved
2011-02-09T08:42:05.433356+08:00 boston kernel: system 00:03: [io  0x1000-0x107f] has been reserved
2011-02-09T08:42:05.433359+08:00 boston kernel: system 00:03: [io  0x1180-0x11ff] has been reserved
2011-02-09T08:42:05.433361+08:00 boston kernel: system 00:03: [io  0x0800-0x080f] has been reserved
2011-02-09T08:42:05.433364+08:00 boston kernel: system 00:03: [io  0x15e0-0x15ef] has been reserved
2011-02-09T08:42:05.433367+08:00 boston kernel: system 00:03: [io  0x1600-0x1641] has been reserved
2011-02-09T08:42:05.433369+08:00 boston kernel: system 00:03: [io  0x1644-0x167f] could not be reserved
2011-02-09T08:42:05.433372+08:00 boston kernel: system 00:03: [mem 0xe0000000-0xefffffff] has been reserved
2011-02-09T08:42:05.433375+08:00 boston kernel: system 00:03: [mem 0xfeaff000-0xfeafffff] has been reserved
2011-02-09T08:42:05.433378+08:00 boston kernel: system 00:03: [mem 0xfed1c000-0xfed1ffff] has been reserved
2011-02-09T08:42:05.433381+08:00 boston kernel: system 00:03: [mem 0xfed10000-0xfed13fff] has been reserved
2011-02-09T08:42:05.433384+08:00 boston kernel: system 00:03: [mem 0xfed18000-0xfed18fff] has been reserved
2011-02-09T08:42:05.433386+08:00 boston kernel: system 00:03: [mem 0xfed19000-0xfed19fff] has been reserved
2011-02-09T08:42:05.433389+08:00 boston kernel: system 00:03: [mem 0xfed45000-0xfed4bfff] has been reserved
2011-02-09T08:42:05.433392+08:00 boston kernel: system 00:03: Plug and Play ACPI device, IDs PNP0c02 (active)
2011-02-09T08:42:05.433403+08:00 boston kernel: pnp 00:04: [mem 0xfed00000-0xfed003ff]
2011-02-09T08:42:05.433407+08:00 boston kernel: pnp 00:04: Plug and Play ACPI device, IDs PNP0103 (active)
2011-02-09T08:42:05.433410+08:00 boston kernel: pnp 00:05: [io  0x0000-0x000f]
2011-02-09T08:42:05.433412+08:00 boston kernel: pnp 00:05: [io  0x0080-0x008f]
2011-02-09T08:42:05.433414+08:00 boston kernel: pnp 00:05: [io  0x00c0-0x00df]
2011-02-09T08:42:05.433417+08:00 boston kernel: pnp 00:05: [dma 4]
2011-02-09T08:42:05.433419+08:00 boston kernel: pnp 00:05: Plug and Play ACPI device, IDs PNP0200 (active)
2011-02-09T08:42:05.433422+08:00 boston kernel: pnp 00:06: [io  0x0061]
2011-02-09T08:42:05.433425+08:00 boston kernel: pnp 00:06: Plug and Play ACPI device, IDs PNP0800 (active)
2011-02-09T08:42:05.433427+08:00 boston kernel: pnp 00:07: [io  0x00f0]
2011-02-09T08:42:05.433430+08:00 boston kernel: pnp 00:07: [irq 13]
2011-02-09T08:42:05.433433+08:00 boston kernel: pnp 00:07: Plug and Play ACPI device, IDs PNP0c04 (active)
2011-02-09T08:42:05.433435+08:00 boston kernel: pnp 00:08: [io  0x0070-0x0071]
2011-02-09T08:42:05.433437+08:00 boston kernel: pnp 00:08: [irq 8]
2011-02-09T08:42:05.433440+08:00 boston kernel: pnp 00:08: Plug and Play ACPI device, IDs PNP0b00 (active)
2011-02-09T08:42:05.433442+08:00 boston kernel: pnp 00:09: [io  0x0060]
2011-02-09T08:42:05.433444+08:00 boston kernel: pnp 00:09: [io  0x0064]
2011-02-09T08:42:05.433447+08:00 boston kernel: pnp 00:09: [irq 1]
2011-02-09T08:42:05.433449+08:00 boston kernel: pnp 00:09: Plug and Play ACPI device, IDs PNP0303 (active)
2011-02-09T08:42:05.433452+08:00 boston kernel: pnp 00:0a: [irq 12]
2011-02-09T08:42:05.433455+08:00 boston kernel: pnp 00:0a: Plug and Play ACPI device, IDs LEN0018 PNP0f13 (active)
2011-02-09T08:42:05.433457+08:00 boston kernel: pnp 00:0b: [mem 0xfed40000-0xfed44fff]
2011-02-09T08:42:05.433460+08:00 boston kernel: pnp 00:0b: Plug and Play ACPI device, IDs SMO1200 PNP0c31 (active)
2011-02-09T08:42:05.433463+08:00 boston kernel: Switched to NOHz mode on CPU #0
2011-02-09T08:42:05.433465+08:00 boston kernel: Switched to NOHz mode on CPU #2
2011-02-09T08:42:05.433467+08:00 boston kernel: Switched to NOHz mode on CPU #3
2011-02-09T08:42:05.433470+08:00 boston kernel: Switched to NOHz mode on CPU #1
2011-02-09T08:42:05.433472+08:00 boston kernel: pnp: PnP ACPI: found 12 devices
2011-02-09T08:42:05.433628+08:00 boston kernel: ACPI: ACPI bus type pnp unregistered
2011-02-09T08:42:05.433635+08:00 boston kernel: pci 0000:00:1c.0: PCI bridge to [bus 0d-0d]
2011-02-09T08:42:05.433638+08:00 boston kernel: pci 0000:00:1c.0:   bridge window [io  disabled]
2011-02-09T08:42:05.433643+08:00 boston kernel: pci 0000:00:1c.0:   bridge window [mem disabled]
2011-02-09T08:42:05.433646+08:00 boston kernel: pci 0000:00:1c.0:   bridge window [mem pref disabled]
2011-02-09T08:42:05.433648+08:00 boston kernel: pci 0000:00:1c.3: PCI bridge to [bus 05-0c]
2011-02-09T08:42:05.433651+08:00 boston kernel: pci 0000:00:1c.3:   bridge window [io  0x2000-0x2fff]
2011-02-09T08:42:05.433654+08:00 boston kernel: pci 0000:00:1c.3:   bridge window [mem 0xf0000000-0xf1ffffff]
2011-02-09T08:42:05.433657+08:00 boston kernel: pci 0000:00:1c.3:   bridge window [mem 0xf2800000-0xf28fffff 64bit pref]
2011-02-09T08:42:05.433660+08:00 boston kernel: pci 0000:00:1c.4: PCI bridge to [bus 02-02]
2011-02-09T08:42:05.433663+08:00 boston kernel: pci 0000:00:1c.4:   bridge window [io  disabled]
2011-02-09T08:42:05.433666+08:00 boston kernel: pci 0000:00:1c.4:   bridge window [mem 0xf2400000-0xf24fffff]
2011-02-09T08:42:05.433669+08:00 boston kernel: pci 0000:00:1c.4:   bridge window [mem pref disabled]
2011-02-09T08:42:05.433672+08:00 boston kernel: pci 0000:00:1e.0: PCI bridge to [bus 0e-0e]
2011-02-09T08:42:05.433675+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [io  disabled]
2011-02-09T08:42:05.433678+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem disabled]
2011-02-09T08:42:05.433681+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem pref disabled]
2011-02-09T08:42:05.433684+08:00 boston kernel: pci 0000:00:1c.0: PCI INT A -> GSI 20 (level, low) -> IRQ 20
2011-02-09T08:42:05.433686+08:00 boston kernel: pci 0000:00:1c.0: setting latency timer to 64
2011-02-09T08:42:05.433689+08:00 boston kernel: pci 0000:00:1c.3: PCI INT D -> GSI 23 (level, low) -> IRQ 23
2011-02-09T08:42:05.433692+08:00 boston kernel: pci 0000:00:1c.3: setting latency timer to 64
2011-02-09T08:42:05.433695+08:00 boston kernel: pci 0000:00:1c.4: PCI INT A -> GSI 20 (level, low) -> IRQ 20
2011-02-09T08:42:05.433697+08:00 boston kernel: pci 0000:00:1c.4: setting latency timer to 64
2011-02-09T08:42:05.433700+08:00 boston kernel: pci 0000:00:1e.0: setting latency timer to 64
2011-02-09T08:42:05.433703+08:00 boston kernel: pci_bus 0000:00: resource 4 [io  0x0000-0x0cf7]
2011-02-09T08:42:05.433705+08:00 boston kernel: pci_bus 0000:00: resource 5 [io  0x0d00-0xffff]
2011-02-09T08:42:05.433713+08:00 boston kernel: pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff]
2011-02-09T08:42:05.433716+08:00 boston kernel: pci_bus 0000:00: resource 7 [mem 0x000d0000-0x000d3fff]
2011-02-09T08:42:05.433719+08:00 boston kernel: pci_bus 0000:00: resource 8 [mem 0x000d4000-0x000d7fff]
2011-02-09T08:42:05.433722+08:00 boston kernel: pci_bus 0000:00: resource 9 [mem 0x000d8000-0x000dbfff]
2011-02-09T08:42:05.433725+08:00 boston kernel: pci_bus 0000:00: resource 10 [mem 0xc0000000-0xfebfffff]
2011-02-09T08:42:05.433728+08:00 boston kernel: pci_bus 0000:05: resource 0 [io  0x2000-0x2fff]
2011-02-09T08:42:05.433730+08:00 boston kernel: pci_bus 0000:05: resource 1 [mem 0xf0000000-0xf1ffffff]
2011-02-09T08:42:05.433734+08:00 boston kernel: pci_bus 0000:05: resource 2 [mem 0xf2800000-0xf28fffff 64bit pref]
2011-02-09T08:42:05.433736+08:00 boston kernel: pci_bus 0000:02: resource 1 [mem 0xf2400000-0xf24fffff]
2011-02-09T08:42:05.433739+08:00 boston kernel: pci_bus 0000:0e: resource 4 [io  0x0000-0x0cf7]
2011-02-09T08:42:05.433742+08:00 boston kernel: pci_bus 0000:0e: resource 5 [io  0x0d00-0xffff]
2011-02-09T08:42:05.433745+08:00 boston kernel: pci_bus 0000:0e: resource 6 [mem 0x000a0000-0x000bffff]
2011-02-09T08:42:05.433747+08:00 boston kernel: pci_bus 0000:0e: resource 7 [mem 0x000d0000-0x000d3fff]
2011-02-09T08:42:05.433750+08:00 boston kernel: pci_bus 0000:0e: resource 8 [mem 0x000d4000-0x000d7fff]
2011-02-09T08:42:05.433753+08:00 boston kernel: pci_bus 0000:0e: resource 9 [mem 0x000d8000-0x000dbfff]
2011-02-09T08:42:05.433756+08:00 boston kernel: pci_bus 0000:0e: resource 10 [mem 0xc0000000-0xfebfffff]
2011-02-09T08:42:05.433758+08:00 boston kernel: NET: Registered protocol family 2
2011-02-09T08:42:05.433761+08:00 boston kernel: IP route cache hash table entries: 262144 (order: 9, 2097152 bytes)
2011-02-09T08:42:05.433772+08:00 boston kernel: TCP established hash table entries: 524288 (order: 11, 8388608 bytes)
2011-02-09T08:42:05.433776+08:00 boston kernel: TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
2011-02-09T08:42:05.433779+08:00 boston kernel: TCP: Hash tables configured (established 524288 bind 65536)
2011-02-09T08:42:05.433781+08:00 boston kernel: TCP reno registered
2011-02-09T08:42:05.433784+08:00 boston kernel: UDP hash table entries: 4096 (order: 5, 131072 bytes)
2011-02-09T08:42:05.433786+08:00 boston kernel: UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes)
2011-02-09T08:42:05.433789+08:00 boston kernel: NET: Registered protocol family 1
2011-02-09T08:42:05.433791+08:00 boston kernel: pci 0000:00:02.0: Boot video device
2011-02-09T08:42:05.433794+08:00 boston kernel: PCI: CLS 64 bytes, default 64
2011-02-09T08:42:05.433796+08:00 boston kernel: PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
2011-02-09T08:42:05.433800+08:00 boston kernel: Placing 64MB software IO TLB between ffff8800b6e7a000 - ffff8800bae7a000
2011-02-09T08:42:05.433802+08:00 boston kernel: software IO TLB at phys 0xb6e7a000 - 0xbae7a000
2011-02-09T08:42:05.433805+08:00 boston kernel: Simple Boot Flag at 0x35 set to 0x1
2011-02-09T08:42:05.433808+08:00 boston kernel: NTFS driver 2.1.30 [Flags: R/W].
2011-02-09T08:42:05.433810+08:00 boston kernel: fuse init (API version 7.16)
2011-02-09T08:42:05.433812+08:00 boston kernel: Btrfs loaded
2011-02-09T08:42:05.433815+08:00 boston kernel: msgmni has been set to 15604
2011-02-09T08:42:05.433818+08:00 boston kernel: Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)
2011-02-09T08:42:05.433820+08:00 boston kernel: io scheduler noop registered (default)
2011-02-09T08:42:05.433823+08:00 boston kernel: pci_hotplug: PCI Hot Plug PCI Core version: 0.5
2011-02-09T08:42:05.433826+08:00 boston kernel: pciehp: PCI Express Hot Plug Controller Driver version: 0.4
2011-02-09T08:42:05.433828+08:00 boston kernel: acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
2011-02-09T08:42:05.433831+08:00 boston kernel: acpiphp: Slot [1] registered
2011-02-09T08:42:05.433834+08:00 boston kernel: ACPI: Deprecated procfs I/F for AC is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared
2011-02-09T08:42:05.433836+08:00 boston kernel: ACPI: AC Adapter [AC] (off-line)
2011-02-09T08:42:05.433839+08:00 boston kernel: input: Lid Switch as /devices/LNXSYSTM:00/device:00/PNP0C0D:00/input/input0
2011-02-09T08:42:05.433842+08:00 boston kernel: ACPI: Lid Switch [LID]
2011-02-09T08:42:05.433854+08:00 boston kernel: input: Sleep Button as /devices/LNXSYSTM:00/device:00/PNP0C0E:00/input/input1
2011-02-09T08:42:05.433858+08:00 boston kernel: ACPI: Sleep Button [SLPB]
2011-02-09T08:42:05.433861+08:00 boston kernel: input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2
2011-02-09T08:42:05.433863+08:00 boston kernel: ACPI: Power Button [PWRF]
2011-02-09T08:42:05.433866+08:00 boston kernel: ACPI: acpi_idle registered with cpuidle
2011-02-09T08:42:05.434037+08:00 boston kernel: Monitor-Mwait will be used to enter C-1 state
2011-02-09T08:42:05.434043+08:00 boston kernel: Monitor-Mwait will be used to enter C-2 state
2011-02-09T08:42:05.434047+08:00 boston kernel: Monitor-Mwait will be used to enter C-3 state
2011-02-09T08:42:05.434049+08:00 boston kernel: thermal LNXTHERM:00: registered as thermal_zone0
2011-02-09T08:42:05.434052+08:00 boston kernel: ACPI: Thermal Zone [THM0] (53 C)
2011-02-09T08:42:05.434054+08:00 boston kernel: ERST: Table is not found!
2011-02-09T08:42:05.434057+08:00 boston kernel: GHES: HEST is not enabled!
2011-02-09T08:42:05.434060+08:00 boston kernel: ACPI: Deprecated procfs I/F for battery is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared
2011-02-09T08:42:05.434063+08:00 boston kernel: ACPI: Battery Slot [BAT0] (battery present)
2011-02-09T08:42:05.434066+08:00 boston kernel: Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
2011-02-09T08:42:05.434069+08:00 boston kernel: Non-volatile memory driver v1.3
2011-02-09T08:42:05.434072+08:00 boston kernel: Linux agpgart interface v0.103
2011-02-09T08:42:05.434075+08:00 boston kernel: agpgart-intel 0000:00:00.0: Intel HD Graphics Chipset
2011-02-09T08:42:05.434078+08:00 boston kernel: agpgart-intel 0000:00:00.0: detected gtt size: 524288K total, 262144K mappable
2011-02-09T08:42:05.434081+08:00 boston kernel: agpgart-intel 0000:00:00.0: detected 32768K stolen memory
2011-02-09T08:42:05.434083+08:00 boston kernel: agpgart-intel 0000:00:00.0: AGP aperture is 256M @ 0xd0000000
2011-02-09T08:42:05.434086+08:00 boston kernel: brd: module loaded
2011-02-09T08:42:05.434088+08:00 boston kernel: loop: module loaded
2011-02-09T08:42:05.434091+08:00 boston kernel: megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)
2011-02-09T08:42:05.434094+08:00 boston kernel: megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)
2011-02-09T08:42:05.434097+08:00 boston kernel: megasas: 00.00.05.29-rc1 Tue. Dec. 7 17:00:00 PDT 2010
2011-02-09T08:42:05.434099+08:00 boston kernel: mpt2sas version 07.100.00.00 loaded
2011-02-09T08:42:05.434102+08:00 boston kernel: ahci 0000:00:1f.2: version 3.0
2011-02-09T08:42:05.434104+08:00 boston kernel: ahci 0000:00:1f.2: PCI INT B -> GSI 16 (level, low) -> IRQ 16
2011-02-09T08:42:05.434110+08:00 boston kernel: ahci 0000:00:1f.2: irq 40 for MSI/MSI-X
2011-02-09T08:42:05.434114+08:00 boston kernel: ahci: SSS flag set, parallel bus scan disabled
2011-02-09T08:42:05.434117+08:00 boston kernel: ahci 0000:00:1f.2: AHCI 0001.0300 32 slots 6 ports 3 Gbps 0x31 impl SATA mode
2011-02-09T08:42:05.434120+08:00 boston kernel: ahci 0000:00:1f.2: flags: 64bit ncq sntf stag pm led clo pmp pio slum part ems sxs apst 
2011-02-09T08:42:05.434123+08:00 boston kernel: ahci 0000:00:1f.2: setting latency timer to 64
2011-02-09T08:42:05.434125+08:00 boston kernel: scsi0 : ahci
2011-02-09T08:42:05.434128+08:00 boston kernel: scsi1 : ahci
2011-02-09T08:42:05.434130+08:00 boston kernel: scsi2 : ahci
2011-02-09T08:42:05.434132+08:00 boston kernel: scsi3 : ahci
2011-02-09T08:42:05.434135+08:00 boston kernel: scsi4 : ahci
2011-02-09T08:42:05.434137+08:00 boston kernel: scsi5 : ahci
2011-02-09T08:42:05.434140+08:00 boston kernel: ata1: SATA max UDMA/133 abar m2048@0xf2727000 port 0xf2727100 irq 40
2011-02-09T08:42:05.434142+08:00 boston kernel: ata2: DUMMY
2011-02-09T08:42:05.434144+08:00 boston kernel: ata3: DUMMY
2011-02-09T08:42:05.434146+08:00 boston kernel: ata4: DUMMY
2011-02-09T08:42:05.434149+08:00 boston kernel: ata5: SATA max UDMA/133 abar m2048@0xf2727000 port 0xf2727300 irq 40
2011-02-09T08:42:05.434152+08:00 boston kernel: ata6: SATA max UDMA/133 abar m2048@0xf2727000 port 0xf2727380 irq 40
2011-02-09T08:42:05.434154+08:00 boston kernel: Intel(R) Gigabit Ethernet Network Driver - version 2.1.0-k2
2011-02-09T08:42:05.434157+08:00 boston kernel: Copyright (c) 2007-2009 Intel Corporation.
2011-02-09T08:42:05.434160+08:00 boston kernel: ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 3.0.12-k2
2011-02-09T08:42:05.434171+08:00 boston kernel: ixgbe: Copyright (c) 1999-2010 Intel Corporation.
2011-02-09T08:42:05.434175+08:00 boston kernel: pcnet32: pcnet32.c:v1.35 21.Apr.2008 tsbogend@alpha.franken.de
2011-02-09T08:42:05.434177+08:00 boston kernel: PPP generic driver version 2.4.2
2011-02-09T08:42:05.434179+08:00 boston kernel: PPP Deflate Compression module registered
2011-02-09T08:42:05.434182+08:00 boston kernel: PPP BSD Compression module registered
2011-02-09T08:42:05.434185+08:00 boston kernel: tun: Universal TUN/TAP device driver, 1.6
2011-02-09T08:42:05.434187+08:00 boston kernel: tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
2011-02-09T08:42:05.434190+08:00 boston kernel: Fusion MPT base driver 3.04.17
2011-02-09T08:42:05.434192+08:00 boston kernel: Copyright (c) 1999-2008 LSI Corporation
2011-02-09T08:42:05.434195+08:00 boston kernel: Fusion MPT SPI Host driver 3.04.17
2011-02-09T08:42:05.434197+08:00 boston kernel: Fusion MPT SAS Host driver 3.04.17
2011-02-09T08:42:05.434200+08:00 boston kernel: ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
2011-02-09T08:42:05.434203+08:00 boston kernel: ehci_hcd 0000:00:1a.0: power state changed by ACPI to D0
2011-02-09T08:42:05.434206+08:00 boston kernel: ehci_hcd 0000:00:1a.0: power state changed by ACPI to D0
2011-02-09T08:42:05.434209+08:00 boston kernel: ehci_hcd 0000:00:1a.0: PCI INT D -> GSI 23 (level, low) -> IRQ 23
2011-02-09T08:42:05.434211+08:00 boston kernel: ehci_hcd 0000:00:1a.0: setting latency timer to 64
2011-02-09T08:42:05.434214+08:00 boston kernel: ehci_hcd 0000:00:1a.0: EHCI Host Controller
2011-02-09T08:42:05.434217+08:00 boston kernel: ehci_hcd 0000:00:1a.0: new USB bus registered, assigned bus number 1
2011-02-09T08:42:05.434220+08:00 boston kernel: Refined TSC clocksource calibration: 2127.999 MHz.
2011-02-09T08:42:05.434222+08:00 boston kernel: Switching to clocksource tsc
2011-02-09T08:42:05.434225+08:00 boston kernel: ehci_hcd 0000:00:1a.0: debug port 2
2011-02-09T08:42:05.434227+08:00 boston kernel: ehci_hcd 0000:00:1a.0: cache line size of 64 is not supported
2011-02-09T08:42:05.434230+08:00 boston kernel: ehci_hcd 0000:00:1a.0: irq 23, io mem 0xf2728000
2011-02-09T08:42:05.434232+08:00 boston kernel: ehci_hcd 0000:00:1a.0: USB 2.0 started, EHCI 1.00
2011-02-09T08:42:05.434235+08:00 boston kernel: hub 1-0:1.0: USB hub found
2011-02-09T08:42:05.434237+08:00 boston kernel: hub 1-0:1.0: 3 ports detected
2011-02-09T08:42:05.434240+08:00 boston kernel: ehci_hcd 0000:00:1d.0: power state changed by ACPI to D0
2011-02-09T08:42:05.434243+08:00 boston kernel: ehci_hcd 0000:00:1d.0: power state changed by ACPI to D0
2011-02-09T08:42:05.434246+08:00 boston kernel: ehci_hcd 0000:00:1d.0: PCI INT D -> GSI 19 (level, low) -> IRQ 19
2011-02-09T08:42:05.434258+08:00 boston kernel: ehci_hcd 0000:00:1d.0: setting latency timer to 64
2011-02-09T08:42:05.434261+08:00 boston kernel: ehci_hcd 0000:00:1d.0: EHCI Host Controller
2011-02-09T08:42:05.434264+08:00 boston kernel: ehci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 2
2011-02-09T08:42:05.434267+08:00 boston kernel: ehci_hcd 0000:00:1d.0: debug port 2
2011-02-09T08:42:05.434269+08:00 boston kernel: ehci_hcd 0000:00:1d.0: cache line size of 64 is not supported
2011-02-09T08:42:05.434272+08:00 boston kernel: ehci_hcd 0000:00:1d.0: irq 19, io mem 0xf2728400
2011-02-09T08:42:05.434274+08:00 boston kernel: ehci_hcd 0000:00:1d.0: USB 2.0 started, EHCI 1.00
2011-02-09T08:42:05.434277+08:00 boston kernel: hub 2-0:1.0: USB hub found
2011-02-09T08:42:05.434280+08:00 boston kernel: hub 2-0:1.0: 3 ports detected
2011-02-09T08:42:05.434282+08:00 boston kernel: ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
2011-02-09T08:42:05.434285+08:00 boston kernel: uhci_hcd: USB Universal Host Controller Interface driver
2011-02-09T08:42:05.434443+08:00 boston kernel: i8042: PNP: PS/2 Controller [PNP0303:KBD,PNP0f13:MOU] at 0x60,0x64 irq 1,12
2011-02-09T08:42:05.434449+08:00 boston kernel: serio: i8042 KBD port at 0x60,0x64 irq 1
2011-02-09T08:42:05.434452+08:00 boston kernel: serio: i8042 AUX port at 0x60,0x64 irq 12
2011-02-09T08:42:05.434455+08:00 boston kernel: mousedev: PS/2 mouse device common for all mice
2011-02-09T08:42:05.434457+08:00 boston kernel: input: PC Speaker as /devices/platform/pcspkr/input/input3
2011-02-09T08:42:05.434460+08:00 boston kernel: rtc_cmos 00:08: RTC can wake from S4
2011-02-09T08:42:05.434463+08:00 boston kernel: input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input4
2011-02-09T08:42:05.434466+08:00 boston kernel: rtc_cmos 00:08: rtc core: registered rtc_cmos as rtc0
2011-02-09T08:42:05.434469+08:00 boston kernel: rtc0: alarms up to one month, y3k, 114 bytes nvram, hpet irqs
2011-02-09T08:42:05.434471+08:00 boston kernel: lirc_dev: IR Remote Control driver registered, major 251 
2011-02-09T08:42:05.434475+08:00 boston kernel: IR RC5 (streamzap) protocol handler initialized
2011-02-09T08:42:05.434478+08:00 boston kernel: IR LIRC bridge handler initialized
2011-02-09T08:42:05.434480+08:00 boston kernel: Linux video capture interface: v2.00
2011-02-09T08:42:05.434483+08:00 boston kernel: coretemp coretemp.0: TjMax is 105 C.
2011-02-09T08:42:05.434486+08:00 boston kernel: coretemp coretemp.2: TjMax is 105 C.
2011-02-09T08:42:05.434489+08:00 boston kernel: device-mapper: ioctl: 4.19.1-ioctl (2011-01-07) initialised: dm-devel@redhat.com
2011-02-09T08:42:05.434491+08:00 boston kernel: EDAC MC: Ver: 2.1.0 Feb  7 2011
2011-02-09T08:42:05.434494+08:00 boston kernel: cpuidle: using governor ladder
2011-02-09T08:42:05.434496+08:00 boston kernel: cpuidle: using governor menu
2011-02-09T08:42:05.434498+08:00 boston kernel: thinkpad_acpi: ThinkPad ACPI Extras v0.24
2011-02-09T08:42:05.434501+08:00 boston kernel: thinkpad_acpi: http://ibm-acpi.sf.net/
2011-02-09T08:42:05.434504+08:00 boston kernel: thinkpad_acpi: ThinkPad BIOS 6QET62WW (1.32 ), EC 6QHT31WW-1.12
2011-02-09T08:42:05.434506+08:00 boston kernel: thinkpad_acpi: Lenovo ThinkPad X201s, model 5413FGA
2011-02-09T08:42:05.434515+08:00 boston kernel: thinkpad_acpi: detected a 8-level brightness capable ThinkPad
2011-02-09T08:42:05.434519+08:00 boston kernel: thinkpad_acpi: rfkill switch tpacpi_bluetooth_sw: radio is blocked
2011-02-09T08:42:05.434521+08:00 boston kernel: Registered led device: tpacpi::thinklight
2011-02-09T08:42:05.434528+08:00 boston kernel: Registered led device: tpacpi::power
2011-02-09T08:42:05.434531+08:00 boston kernel: Registered led device: tpacpi::standby
2011-02-09T08:42:05.434534+08:00 boston kernel: Registered led device: tpacpi::thinkvantage
2011-02-09T08:42:05.434537+08:00 boston kernel: thinkpad_acpi: volume: disabled as there is no ALSA support in this kernel
2011-02-09T08:42:05.434540+08:00 boston kernel: input: ThinkPad Extra Buttons as /devices/platform/thinkpad_acpi/input/input5
2011-02-09T08:42:05.434543+08:00 boston kernel: HDA Intel 0000:00:1b.0: PCI INT B -> GSI 17 (level, low) -> IRQ 17
2011-02-09T08:42:05.434546+08:00 boston kernel: HDA Intel 0000:00:1b.0: irq 41 for MSI/MSI-X
2011-02-09T08:42:05.434548+08:00 boston kernel: HDA Intel 0000:00:1b.0: setting latency timer to 64
2011-02-09T08:42:05.434551+08:00 boston kernel: ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
2011-02-09T08:42:05.434554+08:00 boston kernel: ata1.00: ACPI cmd ef/02:00:00:00:00:a0 (unknown) succeeded
2011-02-09T08:42:05.434556+08:00 boston kernel: ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (unknown) filtered out
2011-02-09T08:42:05.434559+08:00 boston kernel: ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (unknown) filtered out
2011-02-09T08:42:05.434562+08:00 boston kernel: ata1.00: ATA-7: SAMSUNG SSD PM800 2.5" 256GB, VBM25D1Q, max UDMA/100
2011-02-09T08:42:05.434572+08:00 boston kernel: ata1.00: 500118192 sectors, multi 16: LBA48 NCQ (depth 31/32), AA
2011-02-09T08:42:05.434575+08:00 boston kernel: ata1.00: ACPI cmd ef/02:00:00:00:00:a0 (unknown) succeeded
2011-02-09T08:42:05.434578+08:00 boston kernel: ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (unknown) filtered out
2011-02-09T08:42:05.434581+08:00 boston kernel: ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (unknown) filtered out
2011-02-09T08:42:05.434583+08:00 boston kernel: ata1.00: configured for UDMA/100
2011-02-09T08:42:05.434586+08:00 boston kernel: scsi 0:0:0:0: Direct-Access     ATA      SAMSUNG SSD PM80 VBM2 PQ: 0 ANSI: 5
2011-02-09T08:42:05.434589+08:00 boston kernel: sd 0:0:0:0: [sda] 500118192 512-byte logical blocks: (256 GB/238 GiB)
2011-02-09T08:42:05.434592+08:00 boston kernel: sd 0:0:0:0: [sda] Write Protect is off
2011-02-09T08:42:05.434595+08:00 boston kernel: sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
2011-02-09T08:42:05.434598+08:00 boston kernel: sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
2011-02-09T08:42:05.434601+08:00 boston kernel: sd 0:0:0:0: Attached scsi generic sg0 type 0
2011-02-09T08:42:05.434604+08:00 boston kernel: sda: sda1 sda2 sda3 sda4 < sda5 sda6 sda7 sda8 sda9 sda10 sda11 sda12 sda13 sda14 sda15 >
2011-02-09T08:42:05.434606+08:00 boston kernel: sd 0:0:0:0: [sda] Attached SCSI disk
2011-02-09T08:42:05.434609+08:00 boston kernel: hda-codec: No codec parser is available
2011-02-09T08:42:05.434611+08:00 boston kernel: ALSA device list:
2011-02-09T08:42:05.434613+08:00 boston kernel:  #0: HDA Intel at 0xf2520000 irq 41
2011-02-09T08:42:05.434616+08:00 boston kernel: Netfilter messages via NETLINK v0.30.
2011-02-09T08:42:05.434618+08:00 boston kernel: nf_conntrack version 0.5.0 (16384 buckets, 65536 max)
2011-02-09T08:42:05.434621+08:00 boston kernel: ctnetlink v0.93: registering with nfnetlink.
2011-02-09T08:42:05.434623+08:00 boston kernel: ip_tables: (C) 2000-2006 Netfilter Core Team
2011-02-09T08:42:05.434626+08:00 boston kernel: arp_tables: (C) 2002 David S. Miller
2011-02-09T08:42:05.434636+08:00 boston kernel: TCP bic registered
2011-02-09T08:42:05.434639+08:00 boston kernel: TCP cubic registered
2011-02-09T08:42:05.434642+08:00 boston kernel: TCP highspeed registered
2011-02-09T08:42:05.434645+08:00 boston kernel: NET: Registered protocol family 17
2011-02-09T08:42:05.434647+08:00 boston kernel: lib80211: common routines for IEEE802.11 drivers
2011-02-09T08:42:05.434650+08:00 boston kernel: lib80211_crypt: registered algorithm 'NULL'
2011-02-09T08:42:05.434652+08:00 boston kernel: rtc_cmos 00:08: setting system clock to 2011-02-09 00:42:03 UTC (1297212123)
2011-02-09T08:42:05.434655+08:00 boston kernel: hub 1-1:1.0: USB hub found
2011-02-09T08:42:05.434657+08:00 boston kernel: hub 1-1:1.0: 6 ports detected
2011-02-09T08:42:05.434660+08:00 boston kernel: ata5: SATA link down (SStatus 0 SControl 300)
2011-02-09T08:42:05.434662+08:00 boston kernel: IBM TrackPoint firmware: 0x0e, buttons: 3/3
2011-02-09T08:42:05.434666+08:00 boston kernel: input: TPPS/2 IBM TrackPoint as /devices/platform/i8042/serio1/input/input6
2011-02-09T08:42:05.434668+08:00 boston kernel: hub 2-1:1.0: USB hub found
2011-02-09T08:42:05.434671+08:00 boston kernel: hub 2-1:1.0: 8 ports detected
2011-02-09T08:42:05.434674+08:00 boston kernel: ata6: SATA link down (SStatus 0 SControl 300)
2011-02-09T08:42:05.434677+08:00 boston kernel: VFS: Mounted root (reiserfs filesystem) readonly on device 8:2.
2011-02-09T08:42:05.434679+08:00 boston kernel: Freeing unused kernel memory: 576k freed
2011-02-09T08:42:05.434684+08:00 boston kernel: Adding 8290300k swap on /dev/sda3.  Priority:-1 extents:1 across:8290300k SS
2011-02-09T08:42:05.985075+08:00 boston kernel: [drm] Initialized drm 1.1.0 20060810
2011-02-09T08:42:06.005484+08:00 boston kernel: i915 0000:00:02.0: power state changed by ACPI to D0
2011-02-09T08:42:06.005509+08:00 boston kernel: i915 0000:00:02.0: power state changed by ACPI to D0
2011-02-09T08:42:06.005513+08:00 boston kernel: i915 0000:00:02.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
2011-02-09T08:42:06.005515+08:00 boston kernel: i915 0000:00:02.0: setting latency timer to 64
2011-02-09T08:42:06.095306+08:00 boston kernel: i915 0000:00:02.0: irq 42 for MSI/MSI-X
2011-02-09T08:42:06.095331+08:00 boston kernel: [drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
2011-02-09T08:42:06.095335+08:00 boston kernel: [drm] Driver supports precise vblank timestamp query.
2011-02-09T08:42:06.185060+08:00 boston kernel: vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem
2011-02-09T08:42:06.275147+08:00 boston kernel: Console: switching to colour frame buffer device 180x56
2011-02-09T08:42:06.275173+08:00 boston kernel: fb0: inteldrmfb frame buffer device
2011-02-09T08:42:06.275177+08:00 boston kernel: drm: registered panic notifier
2011-02-09T08:42:06.275179+08:00 boston kernel: No ACPI video bus found
2011-02-09T08:42:06.275183+08:00 boston kernel: [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0
2011-02-09T08:42:16.285163+08:00 boston kernel: [drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0xf40000, result 0
2011-02-09T08:42:16.285194+08:00 boston kernel: [drm:intel_crt_detect], CRT not detected via hotplug
2011-02-09T08:42:16.285203+08:00 boston kernel: [drm:output_poll_execute], [CONNECTOR:12:VGA-1] status updated from 2 to 2
2011-02-09T08:42:16.285210+08:00 boston kernel: [drm:output_poll_execute], [CONNECTOR:15:HDMI-A-1] status updated from 2 to 2
2011-02-09T08:42:16.285216+08:00 boston kernel: [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003e
2011-02-09T08:42:16.285223+08:00 boston kernel: [drm:ironlake_dp_detect], DPCD: 0000
2011-02-09T08:42:16.285230+08:00 boston kernel: [drm:output_poll_execute], [CONNECTOR:17:DP-1] status updated from 2 to 2
2011-02-09T08:42:19.785043+08:00 boston kernel: CPU 1 is now offline
2011-02-09T08:42:19.805040+08:00 boston kernel: coretemp coretemp.3: TjMax is 105 C.
2011-02-09T08:42:19.875044+08:00 boston kernel: CPU 2 is now offline
2011-02-09T08:42:19.885045+08:00 boston kernel: CPU 3 MCA banks CMCI:2 CMCI:3 CMCI:5
2011-02-09T08:42:20.085044+08:00 boston kernel: CPU 3 is now offline
2011-02-09T08:42:20.085067+08:00 boston kernel: SMP alternatives: switching to UP code
2011-02-09T08:42:59.436744+08:00 boston kernel: imklog 5.6.2, log source = /proc/kmsg started.
2011-02-09T08:42:59.437025+08:00 boston kernel: ress 0xfec00000, GSI 0-23
2011-02-09T08:42:59.437030+08:00 boston kernel: ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
2011-02-09T08:42:59.437032+08:00 boston kernel: ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
2011-02-09T08:42:59.437037+08:00 boston kernel: ACPI: IRQ0 used by override.
2011-02-09T08:42:59.437038+08:00 boston kernel: ACPI: IRQ2 used by override.
2011-02-09T08:42:59.437040+08:00 boston kernel: ACPI: IRQ9 used by override.
2011-02-09T08:42:59.437041+08:00 boston kernel: Using ACPI (MADT) for SMP configuration information
2011-02-09T08:42:59.437043+08:00 boston kernel: ACPI: HPET id: 0x8086a701 base: 0xfed00000
2011-02-09T08:42:59.437044+08:00 boston kernel: SMP: Allowing 4 CPUs, 0 hotplug CPUs
2011-02-09T08:42:59.437046+08:00 boston kernel: nr_irqs_gsi: 40
2011-02-09T08:42:59.437049+08:00 boston kernel: PM: Registered nosave memory: 000000000009e000 - 000000000009f000
2011-02-09T08:42:59.437051+08:00 boston kernel: PM: Registered nosave memory: 000000000009f000 - 00000000000a0000
2011-02-09T08:42:59.437052+08:00 boston kernel: PM: Registered nosave memory: 00000000000a0000 - 00000000000dc000
2011-02-09T08:42:59.437054+08:00 boston kernel: PM: Registered nosave memory: 00000000000dc000 - 0000000000100000
2011-02-09T08:42:59.437056+08:00 boston kernel: PM: Registered nosave memory: 00000000bb27c000 - 00000000bb282000
2011-02-09T08:42:59.437057+08:00 boston kernel: PM: Registered nosave memory: 00000000bb35f000 - 00000000bb371000
2011-02-09T08:42:59.437059+08:00 boston kernel: PM: Registered nosave memory: 00000000bb371000 - 00000000bb3f2000
2011-02-09T08:42:59.437060+08:00 boston kernel: PM: Registered nosave memory: 00000000bb3f2000 - 00000000bb40f000
2011-02-09T08:42:59.437064+08:00 boston kernel: PM: Registered nosave memory: 00000000bb46f000 - 00000000bb668000
2011-02-09T08:42:59.437065+08:00 boston kernel: PM: Registered nosave memory: 00000000bb668000 - 00000000bb6e8000
2011-02-09T08:42:59.437067+08:00 boston kernel: PM: Registered nosave memory: 00000000bb6e8000 - 00000000bb70f000
2011-02-09T08:42:59.437069+08:00 boston kernel: PM: Registered nosave memory: 00000000bb717000 - 00000000bb71f000
2011-02-09T08:42:59.437070+08:00 boston kernel: PM: Registered nosave memory: 00000000bb76b000 - 00000000bb777000
2011-02-09T08:42:59.437072+08:00 boston kernel: PM: Registered nosave memory: 00000000bb777000 - 00000000bb77a000
2011-02-09T08:42:59.437073+08:00 boston kernel: PM: Registered nosave memory: 00000000bb77a000 - 00000000bb781000
2011-02-09T08:42:59.437077+08:00 boston kernel: PM: Registered nosave memory: 00000000bb781000 - 00000000bb782000
2011-02-09T08:42:59.437078+08:00 boston kernel: PM: Registered nosave memory: 00000000bb782000 - 00000000bb78b000
2011-02-09T08:42:59.437080+08:00 boston kernel: PM: Registered nosave memory: 00000000bb78b000 - 00000000bb78c000
2011-02-09T08:42:59.437082+08:00 boston kernel: PM: Registered nosave memory: 00000000bb78c000 - 00000000bb79f000
2011-02-09T08:42:59.437083+08:00 boston kernel: PM: Registered nosave memory: 00000000bb79f000 - 00000000bb7ff000
2011-02-09T08:42:59.437085+08:00 boston kernel: PM: Registered nosave memory: 00000000bb800000 - 00000000c0000000
2011-02-09T08:42:59.437086+08:00 boston kernel: PM: Registered nosave memory: 00000000c0000000 - 00000000e0000000
2011-02-09T08:42:59.437088+08:00 boston kernel: PM: Registered nosave memory: 00000000e0000000 - 00000000f0000000
2011-02-09T08:42:59.437091+08:00 boston kernel: PM: Registered nosave memory: 00000000f0000000 - 00000000feaff000
2011-02-09T08:42:59.437093+08:00 boston kernel: PM: Registered nosave memory: 00000000feaff000 - 00000000feb00000
2011-02-09T08:42:59.437094+08:00 boston kernel: PM: Registered nosave memory: 00000000feb00000 - 00000000fec00000
2011-02-09T08:42:59.437096+08:00 boston kernel: PM: Registered nosave memory: 00000000fec00000 - 00000000fec10000
2011-02-09T08:42:59.437097+08:00 boston kernel: PM: Registered nosave memory: 00000000fec10000 - 00000000fed00000
2011-02-09T08:42:59.437099+08:00 boston kernel: PM: Registered nosave memory: 00000000fed00000 - 00000000fed1c000
2011-02-09T08:42:59.437101+08:00 boston kernel: PM: Registered nosave memory: 00000000fed1c000 - 00000000fed90000
2011-02-09T08:42:59.437104+08:00 boston kernel: PM: Registered nosave memory: 00000000fed90000 - 00000000fee00000
2011-02-09T08:42:59.437106+08:00 boston kernel: PM: Registered nosave memory: 00000000fee00000 - 00000000fee01000
2011-02-09T08:42:59.437108+08:00 boston kernel: PM: Registered nosave memory: 00000000fee01000 - 00000000ff000000
2011-02-09T08:42:59.437109+08:00 boston kernel: PM: Registered nosave memory: 00000000ff000000 - 0000000100000000
2011-02-09T08:42:59.437111+08:00 boston kernel: PM: Registered nosave memory: 00000001fc000000 - 0000000200000000
2011-02-09T08:42:59.437113+08:00 boston kernel: Allocating PCI resources starting at c0000000 (gap: c0000000:20000000)
2011-02-09T08:42:59.437114+08:00 boston kernel: Booting paravirtualized kernel on bare hardware
2011-02-09T08:42:59.437118+08:00 boston kernel: setup_percpu: NR_CPUS:16 nr_cpumask_bits:16 nr_cpu_ids:4 nr_node_ids:1
2011-02-09T08:42:59.437120+08:00 boston kernel: PERCPU: Embedded 26 pages/cpu @ffff8800bb000000 s75392 r8192 d22912 u524288
2011-02-09T08:42:59.437122+08:00 boston kernel: pcpu-alloc: s75392 r8192 d22912 u524288 alloc=1*2097152
2011-02-09T08:42:59.437123+08:00 boston kernel: pcpu-alloc: [0] 0 1 2 3 
2011-02-09T08:42:59.437125+08:00 boston kernel: Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 2012790
2011-02-09T08:42:59.437126+08:00 boston kernel: Policy zone: Normal
2011-02-09T08:42:59.437130+08:00 boston kernel: Kernel command line: BOOT_IMAGE=(hd0,14)/linux/bzc1 root=/dev/sda2 ro resume=/dev/sda3 reboot=bios mce x11 snd-hda-intel.model=lenovo-x200 nf_conntrack_sip.sip_direct_signalling=0 nf_conntrack_sip.sip_direct_media=0 testing_only=\"this is got to be good. Now I can send in a very long line just like 2.4 and need not worry about the line being too long. What a great way to start a great year!!! Cool!\"
2011-02-09T08:42:59.437135+08:00 boston kernel: PID hash table entries: 4096 (order: 3, 32768 bytes)
2011-02-09T08:42:59.437138+08:00 boston kernel: Checking aperture...
2011-02-09T08:42:59.437139+08:00 boston kernel: No AGP bridge found
2011-02-09T08:42:59.437141+08:00 boston kernel: Memory: 7989592k/9371648k available (4737k kernel code, 1192336k absent, 189720k reserved, 2573k data, 576k init)
2011-02-09T08:42:59.437143+08:00 boston kernel: SLUB: Genslabs=15, HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
2011-02-09T08:42:59.437144+08:00 boston kernel: Preemptable hierarchical RCU implementation.
2011-02-09T08:42:59.437146+08:00 boston kernel: 	CONFIG_RCU_FANOUT set to non-default value of 32
2011-02-09T08:42:59.437281+08:00 boston kernel: 	RCU-based detection of stalled CPUs is disabled.
2011-02-09T08:42:59.437283+08:00 boston kernel: 	Verbose stalled-CPUs detection is disabled.
2011-02-09T08:42:59.437284+08:00 boston kernel: NR_IRQS:768
2011-02-09T08:42:59.437286+08:00 boston kernel: Extended CMOS year: 2000
2011-02-09T08:42:59.437287+08:00 boston kernel: Console: colour dummy device 80x25
2011-02-09T08:42:59.437289+08:00 boston kernel: console [tty0] enabled
2011-02-09T08:42:59.437290+08:00 boston kernel: hpet clockevent registered
2011-02-09T08:42:59.437293+08:00 boston kernel: Fast TSC calibration using PIT
2011-02-09T08:42:59.437295+08:00 boston kernel: Detected 2127.998 MHz processor.
2011-02-09T08:42:59.437297+08:00 boston kernel: Calibrating delay loop (skipped), value calculated using timer frequency.. 4255.99 BogoMIPS (lpj=21279980)
2011-02-09T08:42:59.437298+08:00 boston kernel: pid_max: default: 32768 minimum: 301
2011-02-09T08:42:59.437300+08:00 boston kernel: Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes)
2011-02-09T08:42:59.437301+08:00 boston kernel: Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes)
2011-02-09T08:42:59.437303+08:00 boston kernel: Mount-cache hash table entries: 256
2011-02-09T08:42:59.437306+08:00 boston kernel: CPU: Physical Processor ID: 0
2011-02-09T08:42:59.437307+08:00 boston kernel: CPU: Processor Core ID: 0
2011-02-09T08:42:59.437309+08:00 boston kernel: mce: CPU supports 9 MCE banks
2011-02-09T08:42:59.437310+08:00 boston kernel: CPU0: Thermal monitoring enabled (TM1)
2011-02-09T08:42:59.437312+08:00 boston kernel: using mwait in idle threads.
2011-02-09T08:42:59.437313+08:00 boston kernel: ACPI: Core revision 20110112
2011-02-09T08:42:59.437314+08:00 boston kernel: Setting APIC routing to flat
2011-02-09T08:42:59.437316+08:00 boston kernel: ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
2011-02-09T08:42:59.437319+08:00 boston kernel: CPU0: Intel(R) Core(TM) i7 CPU       L 640  @ 2.13GHz stepping 02
2011-02-09T08:42:59.437321+08:00 boston kernel: Performance Events: PEBS fmt1+, Westmere events, Intel PMU driver.
2011-02-09T08:42:59.437322+08:00 boston kernel: ... version:                3
2011-02-09T08:42:59.437323+08:00 boston kernel: ... bit width:              48
2011-02-09T08:42:59.437325+08:00 boston kernel: ... generic registers:      4
2011-02-09T08:42:59.437326+08:00 boston kernel: ... value mask:             0000ffffffffffff
2011-02-09T08:42:59.437327+08:00 boston kernel: ... max period:             000000007fffffff
2011-02-09T08:42:59.437330+08:00 boston kernel: ... fixed-purpose events:   3
2011-02-09T08:42:59.437332+08:00 boston kernel: ... event mask:             000000070000000f
2011-02-09T08:42:59.437333+08:00 boston kernel: Booting Node   0, Processors  #1 #2 #3 Ok.
2011-02-09T08:42:59.437335+08:00 boston kernel: Brought up 4 CPUs
2011-02-09T08:42:59.437336+08:00 boston kernel: Total of 4 processors activated (17023.92 BogoMIPS).
2011-02-09T08:42:59.437338+08:00 boston kernel: NET: Registered protocol family 16
2011-02-09T08:42:59.437339+08:00 boston kernel: ACPI FADT declares the system doesn't support PCIe ASPM, so disable it
2011-02-09T08:42:59.437341+08:00 boston kernel: ACPI: bus type pci registered
2011-02-09T08:42:59.437344+08:00 boston kernel: PCI: Using configuration type 1 for base access
2011-02-09T08:42:59.437345+08:00 boston kernel: bio: create slab <bio-0> at 0
2011-02-09T08:42:59.437347+08:00 boston kernel: ACPI: EC: EC description table is found, configuring boot EC
2011-02-09T08:42:59.437349+08:00 boston kernel: [Firmware Bug]: ACPI: BIOS _OSI(Linux) query ignored
2011-02-09T08:42:59.437367+08:00 boston kernel: ACPI: SSDT 00000000bb71a918 003EB (v01  PmRef  Cpu0Ist 00003000 INTL 20050513)
2011-02-09T08:42:59.437370+08:00 boston kernel: ACPI: Dynamic OEM Table Load:
2011-02-09T08:42:59.437372+08:00 boston kernel: ACPI: SSDT           (null) 003EB (v01  PmRef  Cpu0Ist 00003000 INTL 20050513)
2011-02-09T08:42:59.437377+08:00 boston kernel: ACPI: SSDT 00000000bb718718 006B2 (v01  PmRef  Cpu0Cst 00003001 INTL 20050513)
2011-02-09T08:42:59.437378+08:00 boston kernel: ACPI: Dynamic OEM Table Load:
2011-02-09T08:42:59.437380+08:00 boston kernel: ACPI: SSDT           (null) 006B2 (v01  PmRef  Cpu0Cst 00003001 INTL 20050513)
2011-02-09T08:42:59.437382+08:00 boston kernel: ACPI: SSDT 00000000bb719a98 00303 (v01  PmRef    ApIst 00003000 INTL 20050513)
2011-02-09T08:42:59.437383+08:00 boston kernel: ACPI: Dynamic OEM Table Load:
2011-02-09T08:42:59.437385+08:00 boston kernel: ACPI: SSDT           (null) 00303 (v01  PmRef    ApIst 00003000 INTL 20050513)
2011-02-09T08:42:59.437388+08:00 boston kernel: ACPI: SSDT 00000000bb717d98 00119 (v01  PmRef    ApCst 00003000 INTL 20050513)
2011-02-09T08:42:59.437391+08:00 boston kernel: ACPI: Dynamic OEM Table Load:
2011-02-09T08:42:59.437393+08:00 boston kernel: ACPI: SSDT           (null) 00119 (v01  PmRef    ApCst 00003000 INTL 20050513)
2011-02-09T08:42:59.437394+08:00 boston kernel: ACPI: Interpreter enabled
2011-02-09T08:42:59.437395+08:00 boston kernel: ACPI: (supports S0 S3 S4 S5)
2011-02-09T08:42:59.437397+08:00 boston kernel: ACPI: Using IOAPIC for interrupt routing
2011-02-09T08:42:59.437398+08:00 boston kernel: ACPI: Power Resource [PUBS] (on)
2011-02-09T08:42:59.437400+08:00 boston kernel: ACPI: EC: GPE = 0x11, I/O: command/status = 0x66, data = 0x62
2011-02-09T08:42:59.437402+08:00 boston kernel: ACPI: ACPI Dock Station Driver: 3 docks/bays found
2011-02-09T08:42:59.437405+08:00 boston kernel: HEST: Table not found.
2011-02-09T08:42:59.437407+08:00 boston kernel: PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
2011-02-09T08:42:59.437408+08:00 boston kernel: ACPI: PCI Root Bridge [UNCR] (domain 0000 [bus ff])
2011-02-09T08:42:59.437410+08:00 boston kernel: pci 0000:ff:00.0: [8086:2c62] type 0 class 0x000600
2011-02-09T08:42:59.437411+08:00 boston kernel: pci 0000:ff:00.1: [8086:2d01] type 0 class 0x000600
2011-02-09T08:42:59.437413+08:00 boston kernel: pci 0000:ff:02.0: [8086:2d10] type 0 class 0x000600
2011-02-09T08:42:59.437414+08:00 boston kernel: pci 0000:ff:02.1: [8086:2d11] type 0 class 0x000600
2011-02-09T08:42:59.437418+08:00 boston kernel: pci 0000:ff:02.2: [8086:2d12] type 0 class 0x000600
2011-02-09T08:42:59.437419+08:00 boston kernel: pci 0000:ff:02.3: [8086:2d13] type 0 class 0x000600
2011-02-09T08:42:59.437421+08:00 boston kernel: ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-fe])
2011-02-09T08:42:59.437423+08:00 boston kernel: pci_root PNP0A08:00: host bridge window [io  0x0000-0x0cf7]
2011-02-09T08:42:59.437424+08:00 boston kernel: pci_root PNP0A08:00: host bridge window [io  0x0d00-0xffff]
2011-02-09T08:42:59.437426+08:00 boston kernel: pci_root PNP0A08:00: host bridge window [mem 0x000a0000-0x000bffff]
2011-02-09T08:42:59.437427+08:00 boston kernel: pci_root PNP0A08:00: host bridge window [mem 0x000d0000-0x000d3fff]
2011-02-09T08:42:59.437429+08:00 boston kernel: pci_root PNP0A08:00: host bridge window [mem 0x000d4000-0x000d7fff]
2011-02-09T08:42:59.437432+08:00 boston kernel: pci_root PNP0A08:00: host bridge window [mem 0x000d8000-0x000dbfff]
2011-02-09T08:42:59.437434+08:00 boston kernel: pci_root PNP0A08:00: host bridge window [mem 0xc0000000-0xfebfffff]
2011-02-09T08:42:59.437436+08:00 boston kernel: pci 0000:00:00.0: [8086:0044] type 0 class 0x000600
2011-02-09T08:42:59.437438+08:00 boston kernel: pci 0000:00:02.0: [8086:0046] type 0 class 0x000300
2011-02-09T08:42:59.437439+08:00 boston kernel: pci 0000:00:02.0: reg 10: [mem 0xf2000000-0xf23fffff 64bit]
2011-02-09T08:42:59.437573+08:00 boston kernel: pci 0000:00:02.0: reg 18: [mem 0xd0000000-0xdfffffff 64bit pref]
2011-02-09T08:42:59.437574+08:00 boston kernel: pci 0000:00:02.0: reg 20: [io  0x1800-0x1807]
2011-02-09T08:42:59.437577+08:00 boston kernel: pci 0000:00:16.0: [8086:3b64] type 0 class 0x000780
2011-02-09T08:42:59.437579+08:00 boston kernel: pci 0000:00:16.0: reg 10: [mem 0xf2727800-0xf272780f 64bit]
2011-02-09T08:42:59.437581+08:00 boston kernel: pci 0000:00:16.0: PME# supported from D0 D3hot D3cold
2011-02-09T08:42:59.437582+08:00 boston kernel: pci 0000:00:16.0: PME# disabled
2011-02-09T08:42:59.437600+08:00 boston kernel: pci 0000:00:19.0: [8086:10ea] type 0 class 0x000200
2011-02-09T08:42:59.437603+08:00 boston kernel: pci 0000:00:19.0: reg 10: [mem 0xf2500000-0xf251ffff]
2011-02-09T08:42:59.437604+08:00 boston kernel: pci 0000:00:19.0: reg 14: [mem 0xf2525000-0xf2525fff]
2011-02-09T08:42:59.437606+08:00 boston kernel: pci 0000:00:19.0: reg 18: [io  0x1820-0x183f]
2011-02-09T08:42:59.437607+08:00 boston kernel: pci 0000:00:19.0: PME# supported from D0 D3hot D3cold
2011-02-09T08:42:59.437609+08:00 boston kernel: pci 0000:00:19.0: PME# disabled
2011-02-09T08:42:59.437610+08:00 boston kernel: pci 0000:00:1a.0: [8086:3b3c] type 0 class 0x000c03
2011-02-09T08:42:59.437612+08:00 boston kernel: pci 0000:00:1a.0: reg 10: [mem 0xf2728000-0xf27283ff]
2011-02-09T08:42:59.437613+08:00 boston kernel: pci 0000:00:1a.0: PME# supported from D0 D3hot D3cold
2011-02-09T08:42:59.437615+08:00 boston kernel: pci 0000:00:1a.0: PME# disabled
2011-02-09T08:42:59.437616+08:00 boston kernel: pci 0000:00:1b.0: [8086:3b56] type 0 class 0x000403
2011-02-09T08:42:59.437618+08:00 boston kernel: pci 0000:00:1b.0: reg 10: [mem 0xf2520000-0xf2523fff 64bit]
2011-02-09T08:42:59.437619+08:00 boston kernel: pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold
2011-02-09T08:42:59.437621+08:00 boston kernel: pci 0000:00:1b.0: PME# disabled
2011-02-09T08:42:59.437622+08:00 boston kernel: pci 0000:00:1c.0: [8086:3b42] type 1 class 0x000604
2011-02-09T08:42:59.437624+08:00 boston kernel: pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
2011-02-09T08:42:59.437625+08:00 boston kernel: pci 0000:00:1c.0: PME# disabled
2011-02-09T08:42:59.437627+08:00 boston kernel: pci 0000:00:1c.3: [8086:3b48] type 1 class 0x000604
2011-02-09T08:42:59.437628+08:00 boston kernel: pci 0000:00:1c.3: PME# supported from D0 D3hot D3cold
2011-02-09T08:42:59.437630+08:00 boston kernel: pci 0000:00:1c.3: PME# disabled
2011-02-09T08:42:59.437631+08:00 boston kernel: pci 0000:00:1c.4: [8086:3b4a] type 1 class 0x000604
2011-02-09T08:42:59.437633+08:00 boston kernel: pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold
2011-02-09T08:42:59.437634+08:00 boston kernel: pci 0000:00:1c.4: PME# disabled
2011-02-09T08:42:59.437636+08:00 boston kernel: pci 0000:00:1d.0: [8086:3b34] type 0 class 0x000c03
2011-02-09T08:42:59.437637+08:00 boston kernel: pci 0000:00:1d.0: reg 10: [mem 0xf2728400-0xf27287ff]
2011-02-09T08:42:59.437639+08:00 boston kernel: pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold
2011-02-09T08:42:59.437640+08:00 boston kernel: pci 0000:00:1d.0: PME# disabled
2011-02-09T08:42:59.437642+08:00 boston kernel: pci 0000:00:1e.0: [8086:2448] type 1 class 0x000604
2011-02-09T08:42:59.437643+08:00 boston kernel: pci 0000:00:1f.0: [8086:3b07] type 0 class 0x000601
2011-02-09T08:42:59.437645+08:00 boston kernel: pci 0000:00:1f.2: [8086:3b2f] type 0 class 0x000106
2011-02-09T08:42:59.437646+08:00 boston kernel: pci 0000:00:1f.2: reg 10: [io  0x1860-0x1867]
2011-02-09T08:42:59.437647+08:00 boston kernel: pci 0000:00:1f.2: reg 14: [io  0x1814-0x1817]
2011-02-09T08:42:59.437649+08:00 boston kernel: pci 0000:00:1f.2: reg 18: [io  0x1818-0x181f]
2011-02-09T08:42:59.437651+08:00 boston kernel: pci 0000:00:1f.2: reg 1c: [io  0x1810-0x1813]
2011-02-09T08:42:59.437652+08:00 boston kernel: pci 0000:00:1f.2: reg 20: [io  0x1840-0x185f]
2011-02-09T08:42:59.437654+08:00 boston kernel: pci 0000:00:1f.2: reg 24: [mem 0xf2727000-0xf27277ff]
2011-02-09T08:42:59.437658+08:00 boston kernel: pci 0000:00:1f.2: PME# supported from D3hot
2011-02-09T08:42:59.437659+08:00 boston kernel: pci 0000:00:1f.2: PME# disabled
2011-02-09T08:42:59.437661+08:00 boston kernel: pci 0000:00:1f.3: [8086:3b30] type 0 class 0x000c05
2011-02-09T08:42:59.437663+08:00 boston kernel: pci 0000:00:1f.3: reg 10: [mem 0xf2728800-0xf27288ff 64bit]
2011-02-09T08:42:59.437664+08:00 boston kernel: pci 0000:00:1f.3: reg 20: [io  0x1880-0x189f]
2011-02-09T08:42:59.437666+08:00 boston kernel: pci 0000:00:1f.6: [8086:3b32] type 0 class 0x001180
2011-02-09T08:42:59.437667+08:00 boston kernel: pci 0000:00:1f.6: reg 10: [mem 0xf2526000-0xf2526fff 64bit]
2011-02-09T08:42:59.437670+08:00 boston kernel: pci 0000:00:1c.0: PCI bridge to [bus 0d-0d]
2011-02-09T08:42:59.437672+08:00 boston kernel: pci 0000:00:1c.0:   bridge window [io  0xf000-0x0000] (disabled)
2011-02-09T08:42:59.437674+08:00 boston kernel: pci 0000:00:1c.0:   bridge window [mem 0xfff00000-0x000fffff] (disabled)
2011-02-09T08:42:59.437676+08:00 boston kernel: pci 0000:00:1c.0:   bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
2011-02-09T08:42:59.437677+08:00 boston kernel: pci 0000:00:1c.3: PCI bridge to [bus 05-0c]
2011-02-09T08:42:59.437679+08:00 boston kernel: pci 0000:00:1c.3:   bridge window [io  0x2000-0x2fff]
2011-02-09T08:42:59.437680+08:00 boston kernel: pci 0000:00:1c.3:   bridge window [mem 0xf0000000-0xf1ffffff]
2011-02-09T08:42:59.437682+08:00 boston kernel: pci 0000:00:1c.3:   bridge window [mem 0xf2800000-0xf28fffff 64bit pref]
2011-02-09T08:42:59.437685+08:00 boston kernel: pci 0000:02:00.0: [8086:4239] type 0 class 0x000280
2011-02-09T08:42:59.437687+08:00 boston kernel: pci 0000:02:00.0: reg 10: [mem 0xf2400000-0xf2401fff 64bit]
2011-02-09T08:42:59.437688+08:00 boston kernel: pci 0000:02:00.0: PME# supported from D0 D3hot D3cold
2011-02-09T08:42:59.437690+08:00 boston kernel: pci 0000:02:00.0: PME# disabled
2011-02-09T08:42:59.437691+08:00 boston kernel: pci 0000:00:1c.4: PCI bridge to [bus 02-02]
2011-02-09T08:42:59.437693+08:00 boston kernel: pci 0000:00:1c.4:   bridge window [io  0xf000-0x0000] (disabled)
2011-02-09T08:42:59.437694+08:00 boston kernel: pci 0000:00:1c.4:   bridge window [mem 0xf2400000-0xf24fffff]
2011-02-09T08:42:59.437698+08:00 boston kernel: pci 0000:00:1c.4:   bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
2011-02-09T08:42:59.437700+08:00 boston kernel: pci 0000:00:1e.0: PCI bridge to [bus 0e-0e] (subtractive decode)
2011-02-09T08:42:59.437701+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [io  0xf000-0x0000] (disabled)
2011-02-09T08:42:59.437703+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem 0xfff00000-0x000fffff] (disabled)
2011-02-09T08:42:59.437705+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
2011-02-09T08:42:59.437706+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [io  0x0000-0x0cf7] (subtractive decode)
2011-02-09T08:42:59.437708+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [io  0x0d00-0xffff] (subtractive decode)
2011-02-09T08:42:59.437710+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem 0x000a0000-0x000bffff] (subtractive decode)
2011-02-09T08:42:59.437845+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem 0x000d0000-0x000d3fff] (subtractive decode)
2011-02-09T08:42:59.437848+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem 0x000d4000-0x000d7fff] (subtractive decode)
2011-02-09T08:42:59.437851+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem 0x000d8000-0x000dbfff] (subtractive decode)
2011-02-09T08:42:59.437852+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem 0xc0000000-0xfebfffff] (subtractive decode)
2011-02-09T08:42:59.437854+08:00 boston kernel: ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
2011-02-09T08:42:59.437856+08:00 boston kernel: ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.EXP1._PRT]
2011-02-09T08:42:59.437861+08:00 boston kernel: ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.EXP4._PRT]
2011-02-09T08:42:59.437863+08:00 boston kernel: ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.EXP5._PRT]
2011-02-09T08:42:59.437865+08:00 boston kernel: ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 9 10 *11)
2011-02-09T08:42:59.437866+08:00 boston kernel: ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 9 10 *11)
2011-02-09T08:42:59.437868+08:00 boston kernel: ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 9 10 11) *0, disabled.
2011-02-09T08:42:59.437869+08:00 boston kernel: ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 9 10 *11)
2011-02-09T08:42:59.437871+08:00 boston kernel: ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 9 10 *11)
2011-02-09T08:42:59.437873+08:00 boston kernel: ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 9 10 11) *0, disabled.
2011-02-09T08:42:59.437876+08:00 boston kernel: ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 9 10 11) *0, disabled.
2011-02-09T08:42:59.437878+08:00 boston kernel: ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 9 10 *11)
2011-02-09T08:42:59.437880+08:00 boston kernel: vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none
2011-02-09T08:42:59.437881+08:00 boston kernel: vgaarb: loaded
2011-02-09T08:42:59.437882+08:00 boston kernel: SCSI subsystem initialized
2011-02-09T08:42:59.437884+08:00 boston kernel: libata version 3.00 loaded.
2011-02-09T08:42:59.437885+08:00 boston kernel: usbcore: registered new interface driver usbfs
2011-02-09T08:42:59.437888+08:00 boston kernel: usbcore: registered new interface driver hub
2011-02-09T08:42:59.437890+08:00 boston kernel: usbcore: registered new device driver usb
2011-02-09T08:42:59.437891+08:00 boston kernel: Advanced Linux Sound Architecture Driver Version 1.0.23.
2011-02-09T08:42:59.437893+08:00 boston kernel: PCI: Using ACPI for IRQ routing
2011-02-09T08:42:59.437894+08:00 boston kernel: PCI: pci_cache_line_size set to 64 bytes
2011-02-09T08:42:59.437896+08:00 boston kernel: reserve RAM buffer: 000000000009e800 - 000000000009ffff 
2011-02-09T08:42:59.437897+08:00 boston kernel: reserve RAM buffer: 00000000bb27c000 - 00000000bbffffff 
2011-02-09T08:42:59.437899+08:00 boston kernel: reserve RAM buffer: 00000000bb35f000 - 00000000bbffffff 
2011-02-09T08:42:59.437901+08:00 boston kernel: reserve RAM buffer: 00000000bb46f000 - 00000000bbffffff 
2011-02-09T08:42:59.437902+08:00 boston kernel: reserve RAM buffer: 00000000bb717000 - 00000000bbffffff 
2011-02-09T08:42:59.437904+08:00 boston kernel: reserve RAM buffer: 00000000bb76b000 - 00000000bbffffff 
2011-02-09T08:42:59.437905+08:00 boston kernel: reserve RAM buffer: 00000000bb800000 - 00000000bbffffff 
2011-02-09T08:42:59.437907+08:00 boston kernel: Switching to clocksource hpet
2011-02-09T08:42:59.437908+08:00 boston kernel: pnp: PnP ACPI init
2011-02-09T08:42:59.437909+08:00 boston kernel: ACPI: bus type pnp registered
2011-02-09T08:42:59.437911+08:00 boston kernel: pnp 00:00: [mem 0x00000000-0x0009ffff]
2011-02-09T08:42:59.437912+08:00 boston kernel: pnp 00:00: [mem 0x000c0000-0x000c3fff]
2011-02-09T08:42:59.437914+08:00 boston kernel: pnp 00:00: [mem 0x000c4000-0x000c7fff]
2011-02-09T08:42:59.437915+08:00 boston kernel: pnp 00:00: [mem 0x000c8000-0x000cbfff]
2011-02-09T08:42:59.437917+08:00 boston kernel: pnp 00:00: [mem 0x000cc000-0x000cffff]
2011-02-09T08:42:59.437918+08:00 boston kernel: pnp 00:00: [mem 0x000d0000-0x000cffff disabled]
2011-02-09T08:42:59.437920+08:00 boston kernel: pnp 00:00: [mem 0x000d4000-0x000d3fff disabled]
2011-02-09T08:42:59.437921+08:00 boston kernel: pnp 00:00: [mem 0x000d8000-0x000d7fff disabled]
2011-02-09T08:42:59.437923+08:00 boston kernel: pnp 00:00: [mem 0x000dc000-0x000dffff]
2011-02-09T08:42:59.437924+08:00 boston kernel: pnp 00:00: [mem 0x000e0000-0x000e3fff]
2011-02-09T08:42:59.437926+08:00 boston kernel: pnp 00:00: [mem 0x000e4000-0x000e7fff]
2011-02-09T08:42:59.437927+08:00 boston kernel: pnp 00:00: [mem 0x000e8000-0x000ebfff]
2011-02-09T08:42:59.437929+08:00 boston kernel: pnp 00:00: [mem 0x000ec000-0x000effff]
2011-02-09T08:42:59.437931+08:00 boston kernel: pnp 00:00: [mem 0x000f0000-0x000fffff]
2011-02-09T08:42:59.437934+08:00 boston kernel: pnp 00:00: [mem 0x00100000-0xbfffffff]
2011-02-09T08:42:59.437937+08:00 boston kernel: pnp 00:00: [mem 0xfec00000-0xfed3ffff]
2011-02-09T08:42:59.437939+08:00 boston kernel: pnp 00:00: [mem 0xfed4c000-0xffffffff]
2011-02-09T08:42:59.437942+08:00 boston kernel: system 00:00: [mem 0x00000000-0x0009ffff] could not be reserved
2011-02-09T08:42:59.437945+08:00 boston kernel: system 00:00: [mem 0x000c0000-0x000c3fff] has been reserved
2011-02-09T08:42:59.437948+08:00 boston kernel: system 00:00: [mem 0x000c4000-0x000c7fff] has been reserved
2011-02-09T08:42:59.437951+08:00 boston kernel: system 00:00: [mem 0x000c8000-0x000cbfff] has been reserved
2011-02-09T08:42:59.437954+08:00 boston kernel: system 00:00: [mem 0x000cc000-0x000cffff] has been reserved
2011-02-09T08:42:59.437957+08:00 boston kernel: system 00:00: [mem 0x000dc000-0x000dffff] could not be reserved
2011-02-09T08:42:59.437960+08:00 boston kernel: system 00:00: [mem 0x000e0000-0x000e3fff] could not be reserved
2011-02-09T08:42:59.437979+08:00 boston kernel: system 00:00: [mem 0x000e4000-0x000e7fff] could not be reserved
2011-02-09T08:42:59.437984+08:00 boston kernel: system 00:00: [mem 0x000e8000-0x000ebfff] could not be reserved
2011-02-09T08:42:59.437987+08:00 boston kernel: system 00:00: [mem 0x000ec000-0x000effff] could not be reserved
2011-02-09T08:42:59.437990+08:00 boston kernel: system 00:00: [mem 0x000f0000-0x000fffff] could not be reserved
2011-02-09T08:42:59.437993+08:00 boston kernel: system 00:00: [mem 0x00100000-0xbfffffff] could not be reserved
2011-02-09T08:42:59.437995+08:00 boston kernel: system 00:00: [mem 0xfec00000-0xfed3ffff] could not be reserved
2011-02-09T08:42:59.437998+08:00 boston kernel: system 00:00: [mem 0xfed4c000-0xffffffff] could not be reserved
2011-02-09T08:42:59.438001+08:00 boston kernel: system 00:00: Plug and Play ACPI device, IDs PNP0c01 (active)
2011-02-09T08:42:59.438004+08:00 boston kernel: pnp 00:01: [bus ff]
2011-02-09T08:42:59.438006+08:00 boston kernel: pnp 00:01: Plug and Play ACPI device, IDs PNP0a03 (active)
2011-02-09T08:42:59.438009+08:00 boston kernel: pnp 00:02: [bus 00-fe]
2011-02-09T08:42:59.438012+08:00 boston kernel: pnp 00:02: [io  0x0cf8-0x0cff]
2011-02-09T08:42:59.438014+08:00 boston kernel: pnp 00:02: [io  0x0000-0x0cf7 window]
2011-02-09T08:42:59.438017+08:00 boston kernel: pnp 00:02: [io  0x0d00-0xffff window]
2011-02-09T08:42:59.438019+08:00 boston kernel: pnp 00:02: [mem 0x000a0000-0x000bffff window]
2011-02-09T08:42:59.438022+08:00 boston kernel: pnp 00:02: [mem 0x000c0000-0x000c3fff window]
2011-02-09T08:42:59.438025+08:00 boston kernel: pnp 00:02: [mem 0x000c4000-0x000c7fff window]
2011-02-09T08:42:59.438164+08:00 boston kernel: pnp 00:02: [mem 0x000c8000-0x000cbfff window]
2011-02-09T08:42:59.438169+08:00 boston kernel: pnp 00:02: [mem 0x000cc000-0x000cffff window]
2011-02-09T08:42:59.438170+08:00 boston kernel: pnp 00:02: [mem 0x000d0000-0x000d3fff window]
2011-02-09T08:42:59.438172+08:00 boston kernel: pnp 00:02: [mem 0x000d4000-0x000d7fff window]
2011-02-09T08:42:59.438173+08:00 boston kernel: pnp 00:02: [mem 0x000d8000-0x000dbfff window]
2011-02-09T08:42:59.438175+08:00 boston kernel: pnp 00:02: [mem 0x000dc000-0x000dffff window]
2011-02-09T08:42:59.438176+08:00 boston kernel: pnp 00:02: [mem 0x000e0000-0x000e3fff window]
2011-02-09T08:42:59.438178+08:00 boston kernel: pnp 00:02: [mem 0x000e4000-0x000e7fff window]
2011-02-09T08:42:59.438179+08:00 boston kernel: pnp 00:02: [mem 0x000e8000-0x000ebfff window]
2011-02-09T08:42:59.438180+08:00 boston kernel: pnp 00:02: [mem 0x000ec000-0x000effff window]
2011-02-09T08:42:59.438182+08:00 boston kernel: pnp 00:02: [mem 0xc0000000-0xfebfffff window]
2011-02-09T08:42:59.438183+08:00 boston kernel: pnp 00:02: [mem 0xfed40000-0xfed4bfff window]
2011-02-09T08:42:59.438185+08:00 boston kernel: pnp 00:02: Plug and Play ACPI device, IDs PNP0a08 PNP0a03 (active)
2011-02-09T08:42:59.438186+08:00 boston kernel: pnp 00:03: [io  0x0010-0x001f]
2011-02-09T08:42:59.438187+08:00 boston kernel: pnp 00:03: [io  0x0090-0x009f]
2011-02-09T08:42:59.438189+08:00 boston kernel: pnp 00:03: [io  0x0024-0x0025]
2011-02-09T08:42:59.438190+08:00 boston kernel: pnp 00:03: [io  0x0028-0x0029]
2011-02-09T08:42:59.438191+08:00 boston kernel: pnp 00:03: [io  0x002c-0x002d]
2011-02-09T08:42:59.438193+08:00 boston kernel: pnp 00:03: [io  0x0030-0x0031]
2011-02-09T08:42:59.438194+08:00 boston kernel: pnp 00:03: [io  0x0034-0x0035]
2011-02-09T08:42:59.438195+08:00 boston kernel: pnp 00:03: [io  0x0038-0x0039]
2011-02-09T08:42:59.438197+08:00 boston kernel: pnp 00:03: [io  0x003c-0x003d]
2011-02-09T08:42:59.438198+08:00 boston kernel: pnp 00:03: [io  0x00a4-0x00a5]
2011-02-09T08:42:59.438199+08:00 boston kernel: pnp 00:03: [io  0x00a8-0x00a9]
2011-02-09T08:42:59.438201+08:00 boston kernel: pnp 00:03: [io  0x00ac-0x00ad]
2011-02-09T08:42:59.438202+08:00 boston kernel: pnp 00:03: [io  0x00b0-0x00b5]
2011-02-09T08:42:59.438203+08:00 boston kernel: pnp 00:03: [io  0x00b8-0x00b9]
2011-02-09T08:42:59.438204+08:00 boston kernel: pnp 00:03: [io  0x00bc-0x00bd]
2011-02-09T08:42:59.438206+08:00 boston kernel: pnp 00:03: [io  0x0050-0x0053]
2011-02-09T08:42:59.438207+08:00 boston kernel: pnp 00:03: [io  0x0072-0x0077]
2011-02-09T08:42:59.438208+08:00 boston kernel: pnp 00:03: [io  0x164e-0x164f]
2011-02-09T08:42:59.438210+08:00 boston kernel: pnp 00:03: [io  0x002e-0x002f]
2011-02-09T08:42:59.438211+08:00 boston kernel: pnp 00:03: [io  0x1000-0x107f]
2011-02-09T08:42:59.438212+08:00 boston kernel: pnp 00:03: [io  0x1180-0x11ff]
2011-02-09T08:42:59.438214+08:00 boston kernel: pnp 00:03: [io  0x0800-0x080f]
2011-02-09T08:42:59.438215+08:00 boston kernel: pnp 00:03: [io  0x15e0-0x15ef]
2011-02-09T08:42:59.438216+08:00 boston kernel: pnp 00:03: [io  0x1600-0x1641]
2011-02-09T08:42:59.438240+08:00 boston kernel: pnp 00:03: [io  0x1644-0x167f]
2011-02-09T08:42:59.438243+08:00 boston kernel: pnp 00:03: [mem 0xe0000000-0xefffffff]
2011-02-09T08:42:59.438244+08:00 boston kernel: pnp 00:03: [mem 0xfeaff000-0xfeafffff]
2011-02-09T08:42:59.438246+08:00 boston kernel: pnp 00:03: [mem 0xfed1c000-0xfed1ffff]
2011-02-09T08:42:59.438247+08:00 boston kernel: pnp 00:03: [mem 0xfed10000-0xfed13fff]
2011-02-09T08:42:59.438248+08:00 boston kernel: pnp 00:03: [mem 0xfed18000-0xfed18fff]
2011-02-09T08:42:59.438250+08:00 boston kernel: pnp 00:03: [mem 0xfed19000-0xfed19fff]
2011-02-09T08:42:59.438251+08:00 boston kernel: pnp 00:03: [mem 0xfed45000-0xfed4bfff]
2011-02-09T08:42:59.438253+08:00 boston kernel: system 00:03: [io  0x164e-0x164f] has been reserved
2011-02-09T08:42:59.438254+08:00 boston kernel: system 00:03: [io  0x1000-0x107f] has been reserved
2011-02-09T08:42:59.438256+08:00 boston kernel: system 00:03: [io  0x1180-0x11ff] has been reserved
2011-02-09T08:42:59.438258+08:00 boston kernel: system 00:03: [io  0x0800-0x080f] has been reserved
2011-02-09T08:42:59.438259+08:00 boston kernel: system 00:03: [io  0x15e0-0x15ef] has been reserved
2011-02-09T08:42:59.438261+08:00 boston kernel: system 00:03: [io  0x1600-0x1641] has been reserved
2011-02-09T08:42:59.438262+08:00 boston kernel: system 00:03: [io  0x1644-0x167f] could not be reserved
2011-02-09T08:42:59.438264+08:00 boston kernel: system 00:03: [mem 0xe0000000-0xefffffff] has been reserved
2011-02-09T08:42:59.438266+08:00 boston kernel: system 00:03: [mem 0xfeaff000-0xfeafffff] has been reserved
2011-02-09T08:42:59.438267+08:00 boston kernel: system 00:03: [mem 0xfed1c000-0xfed1ffff] has been reserved
2011-02-09T08:42:59.438269+08:00 boston kernel: system 00:03: [mem 0xfed10000-0xfed13fff] has been reserved
2011-02-09T08:42:59.438270+08:00 boston kernel: system 00:03: [mem 0xfed18000-0xfed18fff] has been reserved
2011-02-09T08:42:59.438272+08:00 boston kernel: system 00:03: [mem 0xfed19000-0xfed19fff] has been reserved
2011-02-09T08:42:59.438274+08:00 boston kernel: system 00:03: [mem 0xfed45000-0xfed4bfff] has been reserved
2011-02-09T08:42:59.438275+08:00 boston kernel: system 00:03: Plug and Play ACPI device, IDs PNP0c02 (active)
2011-02-09T08:42:59.438277+08:00 boston kernel: pnp 00:04: [mem 0xfed00000-0xfed003ff]
2011-02-09T08:42:59.438278+08:00 boston kernel: pnp 00:04: Plug and Play ACPI device, IDs PNP0103 (active)
2011-02-09T08:42:59.438279+08:00 boston kernel: pnp 00:05: [io  0x0000-0x000f]
2011-02-09T08:42:59.438281+08:00 boston kernel: pnp 00:05: [io  0x0080-0x008f]
2011-02-09T08:42:59.438282+08:00 boston kernel: pnp 00:05: [io  0x00c0-0x00df]
2011-02-09T08:42:59.438283+08:00 boston kernel: pnp 00:05: [dma 4]
2011-02-09T08:42:59.438285+08:00 boston kernel: pnp 00:05: Plug and Play ACPI device, IDs PNP0200 (active)
2011-02-09T08:42:59.438286+08:00 boston kernel: pnp 00:06: [io  0x0061]
2011-02-09T08:42:59.438288+08:00 boston kernel: pnp 00:06: Plug and Play ACPI device, IDs PNP0800 (active)
2011-02-09T08:42:59.438289+08:00 boston kernel: pnp 00:07: [io  0x00f0]
2011-02-09T08:42:59.438290+08:00 boston kernel: pnp 00:07: [irq 13]
2011-02-09T08:42:59.438292+08:00 boston kernel: pnp 00:07: Plug and Play ACPI device, IDs PNP0c04 (active)
2011-02-09T08:42:59.438293+08:00 boston kernel: pnp 00:08: [io  0x0070-0x0071]
2011-02-09T08:42:59.438295+08:00 boston kernel: pnp 00:08: [irq 8]
2011-02-09T08:42:59.438296+08:00 boston kernel: pnp 00:08: Plug and Play ACPI device, IDs PNP0b00 (active)
2011-02-09T08:42:59.438297+08:00 boston kernel: pnp 00:09: [io  0x0060]
2011-02-09T08:42:59.438299+08:00 boston kernel: pnp 00:09: [io  0x0064]
2011-02-09T08:42:59.438300+08:00 boston kernel: pnp 00:09: [irq 1]
2011-02-09T08:42:59.438301+08:00 boston kernel: pnp 00:09: Plug and Play ACPI device, IDs PNP0303 (active)
2011-02-09T08:42:59.438303+08:00 boston kernel: pnp 00:0a: [irq 12]
2011-02-09T08:42:59.438304+08:00 boston kernel: pnp 00:0a: Plug and Play ACPI device, IDs LEN0018 PNP0f13 (active)
2011-02-09T08:42:59.438306+08:00 boston kernel: Switched to NOHz mode on CPU #0
2011-02-09T08:42:59.438307+08:00 boston kernel: pnp 00:0b: [mem 0xfed40000-0xfed44fff]
2011-02-09T08:42:59.438308+08:00 boston kernel: Switched to NOHz mode on CPU #1
2011-02-09T08:42:59.438321+08:00 boston kernel: pnp 00:0b: Plug and Play ACPI device, IDs SMO1200 PNP0c31 (active)
2011-02-09T08:42:59.438324+08:00 boston kernel: Switched to NOHz mode on CPU #2
2011-02-09T08:42:59.438325+08:00 boston kernel: Switched to NOHz mode on CPU #3
2011-02-09T08:42:59.438327+08:00 boston kernel: pnp: PnP ACPI: found 12 devices
2011-02-09T08:42:59.438328+08:00 boston kernel: ACPI: ACPI bus type pnp unregistered
2011-02-09T08:42:59.438329+08:00 boston kernel: pci 0000:00:1c.0: PCI bridge to [bus 0d-0d]
2011-02-09T08:42:59.438331+08:00 boston kernel: pci 0000:00:1c.0:   bridge window [io  disabled]
2011-02-09T08:42:59.438333+08:00 boston kernel: pci 0000:00:1c.0:   bridge window [mem disabled]
2011-02-09T08:42:59.438334+08:00 boston kernel: pci 0000:00:1c.0:   bridge window [mem pref disabled]
2011-02-09T08:42:59.438470+08:00 boston kernel: pci 0000:00:1c.3: PCI bridge to [bus 05-0c]
2011-02-09T08:42:59.438476+08:00 boston kernel: pci 0000:00:1c.3:   bridge window [io  0x2000-0x2fff]
2011-02-09T08:42:59.438479+08:00 boston kernel: pci 0000:00:1c.3:   bridge window [mem 0xf0000000-0xf1ffffff]
2011-02-09T08:42:59.438480+08:00 boston kernel: pci 0000:00:1c.3:   bridge window [mem 0xf2800000-0xf28fffff 64bit pref]
2011-02-09T08:42:59.438482+08:00 boston kernel: pci 0000:00:1c.4: PCI bridge to [bus 02-02]
2011-02-09T08:42:59.438484+08:00 boston kernel: pci 0000:00:1c.4:   bridge window [io  disabled]
2011-02-09T08:42:59.438486+08:00 boston kernel: pci 0000:00:1c.4:   bridge window [mem 0xf2400000-0xf24fffff]
2011-02-09T08:42:59.438487+08:00 boston kernel: pci 0000:00:1c.4:   bridge window [mem pref disabled]
2011-02-09T08:42:59.438489+08:00 boston kernel: pci 0000:00:1e.0: PCI bridge to [bus 0e-0e]
2011-02-09T08:42:59.438491+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [io  disabled]
2011-02-09T08:42:59.438492+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem disabled]
2011-02-09T08:42:59.438494+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem pref disabled]
2011-02-09T08:42:59.438495+08:00 boston kernel: pci 0000:00:1c.0: PCI INT A -> GSI 20 (level, low) -> IRQ 20
2011-02-09T08:42:59.438497+08:00 boston kernel: pci 0000:00:1c.0: setting latency timer to 64
2011-02-09T08:42:59.438498+08:00 boston kernel: pci 0000:00:1c.3: PCI INT D -> GSI 23 (level, low) -> IRQ 23
2011-02-09T08:42:59.438500+08:00 boston kernel: pci 0000:00:1c.3: setting latency timer to 64
2011-02-09T08:42:59.438501+08:00 boston kernel: pci 0000:00:1c.4: PCI INT A -> GSI 20 (level, low) -> IRQ 20
2011-02-09T08:42:59.438503+08:00 boston kernel: pci 0000:00:1c.4: setting latency timer to 64
2011-02-09T08:42:59.438504+08:00 boston kernel: pci 0000:00:1e.0: setting latency timer to 64
2011-02-09T08:42:59.438506+08:00 boston kernel: pci_bus 0000:00: resource 4 [io  0x0000-0x0cf7]
2011-02-09T08:42:59.438507+08:00 boston kernel: pci_bus 0000:00: resource 5 [io  0x0d00-0xffff]
2011-02-09T08:42:59.438508+08:00 boston kernel: pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff]
2011-02-09T08:42:59.438510+08:00 boston kernel: pci_bus 0000:00: resource 7 [mem 0x000d0000-0x000d3fff]
2011-02-09T08:42:59.438512+08:00 boston kernel: pci_bus 0000:00: resource 8 [mem 0x000d4000-0x000d7fff]
2011-02-09T08:42:59.438513+08:00 boston kernel: pci_bus 0000:00: resource 9 [mem 0x000d8000-0x000dbfff]
2011-02-09T08:42:59.438515+08:00 boston kernel: pci_bus 0000:00: resource 10 [mem 0xc0000000-0xfebfffff]
2011-02-09T08:42:59.438516+08:00 boston kernel: pci_bus 0000:05: resource 0 [io  0x2000-0x2fff]
2011-02-09T08:42:59.438518+08:00 boston kernel: pci_bus 0000:05: resource 1 [mem 0xf0000000-0xf1ffffff]
2011-02-09T08:42:59.438519+08:00 boston kernel: pci_bus 0000:05: resource 2 [mem 0xf2800000-0xf28fffff 64bit pref]
2011-02-09T08:42:59.438521+08:00 boston kernel: pci_bus 0000:02: resource 1 [mem 0xf2400000-0xf24fffff]
2011-02-09T08:42:59.438522+08:00 boston kernel: pci_bus 0000:0e: resource 4 [io  0x0000-0x0cf7]
2011-02-09T08:42:59.438524+08:00 boston kernel: pci_bus 0000:0e: resource 5 [io  0x0d00-0xffff]
2011-02-09T08:42:59.438525+08:00 boston kernel: pci_bus 0000:0e: resource 6 [mem 0x000a0000-0x000bffff]
2011-02-09T08:42:59.438527+08:00 boston kernel: pci_bus 0000:0e: resource 7 [mem 0x000d0000-0x000d3fff]
2011-02-09T08:42:59.438528+08:00 boston kernel: pci_bus 0000:0e: resource 8 [mem 0x000d4000-0x000d7fff]
2011-02-09T08:42:59.438530+08:00 boston kernel: pci_bus 0000:0e: resource 9 [mem 0x000d8000-0x000dbfff]
2011-02-09T08:42:59.438532+08:00 boston kernel: pci_bus 0000:0e: resource 10 [mem 0xc0000000-0xfebfffff]
2011-02-09T08:42:59.438533+08:00 boston kernel: NET: Registered protocol family 2
2011-02-09T08:42:59.438534+08:00 boston kernel: IP route cache hash table entries: 262144 (order: 9, 2097152 bytes)
2011-02-09T08:42:59.438536+08:00 boston kernel: TCP established hash table entries: 524288 (order: 11, 8388608 bytes)
2011-02-09T08:42:59.438538+08:00 boston kernel: TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
2011-02-09T08:42:59.438539+08:00 boston kernel: TCP: Hash tables configured (established 524288 bind 65536)
2011-02-09T08:42:59.438541+08:00 boston kernel: TCP reno registered
2011-02-09T08:42:59.438542+08:00 boston kernel: UDP hash table entries: 4096 (order: 5, 131072 bytes)
2011-02-09T08:42:59.438543+08:00 boston kernel: UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes)
2011-02-09T08:42:59.438545+08:00 boston kernel: NET: Registered protocol family 1
2011-02-09T08:42:59.438546+08:00 boston kernel: pci 0000:00:02.0: Boot video device
2011-02-09T08:42:59.438548+08:00 boston kernel: PCI: CLS 64 bytes, default 64
2011-02-09T08:42:59.438549+08:00 boston kernel: PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
2011-02-09T08:42:59.438551+08:00 boston kernel: Placing 64MB software IO TLB between ffff8800b6e7a000 - ffff8800bae7a000
2011-02-09T08:42:59.438564+08:00 boston kernel: software IO TLB at phys 0xb6e7a000 - 0xbae7a000
2011-02-09T08:42:59.438566+08:00 boston kernel: Simple Boot Flag at 0x35 set to 0x1
2011-02-09T08:42:59.438568+08:00 boston kernel: NTFS driver 2.1.30 [Flags: R/W].
2011-02-09T08:42:59.438569+08:00 boston kernel: fuse init (API version 7.16)
2011-02-09T08:42:59.438571+08:00 boston kernel: Btrfs loaded
2011-02-09T08:42:59.438572+08:00 boston kernel: msgmni has been set to 15604
2011-02-09T08:42:59.438574+08:00 boston kernel: Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)
2011-02-09T08:42:59.438575+08:00 boston kernel: io scheduler noop registered (default)
2011-02-09T08:42:59.438577+08:00 boston kernel: pci_hotplug: PCI Hot Plug PCI Core version: 0.5
2011-02-09T08:42:59.438578+08:00 boston kernel: pciehp: PCI Express Hot Plug Controller Driver version: 0.4
2011-02-09T08:42:59.438580+08:00 boston kernel: acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
2011-02-09T08:42:59.438581+08:00 boston kernel: acpiphp: Slot [1] registered
2011-02-09T08:42:59.438583+08:00 boston kernel: ACPI: Deprecated procfs I/F for AC is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared
2011-02-09T08:42:59.438584+08:00 boston kernel: ACPI: AC Adapter [AC] (off-line)
2011-02-09T08:42:59.438586+08:00 boston kernel: input: Lid Switch as /devices/LNXSYSTM:00/device:00/PNP0C0D:00/input/input0
2011-02-09T08:42:59.438588+08:00 boston kernel: ACPI: Lid Switch [LID]
2011-02-09T08:42:59.438589+08:00 boston kernel: input: Sleep Button as /devices/LNXSYSTM:00/device:00/PNP0C0E:00/input/input1
2011-02-09T08:42:59.438591+08:00 boston kernel: ACPI: Sleep Button [SLPB]
2011-02-09T08:42:59.438592+08:00 boston kernel: input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2
2011-02-09T08:42:59.438594+08:00 boston kernel: ACPI: Power Button [PWRF]
2011-02-09T08:42:59.438595+08:00 boston kernel: ACPI: acpi_idle registered with cpuidle
2011-02-09T08:42:59.438596+08:00 boston kernel: Monitor-Mwait will be used to enter C-1 state
2011-02-09T08:42:59.438598+08:00 boston kernel: Monitor-Mwait will be used to enter C-2 state
2011-02-09T08:42:59.438599+08:00 boston kernel: Monitor-Mwait will be used to enter C-3 state
2011-02-09T08:42:59.438601+08:00 boston kernel: thermal LNXTHERM:00: registered as thermal_zone0
2011-02-09T08:42:59.438602+08:00 boston kernel: ACPI: Thermal Zone [THM0] (48 C)
2011-02-09T08:42:59.438604+08:00 boston kernel: ERST: Table is not found!
2011-02-09T08:42:59.438605+08:00 boston kernel: GHES: HEST is not enabled!
2011-02-09T08:42:59.438739+08:00 boston kernel: ACPI: Deprecated procfs I/F for battery is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared
2011-02-09T08:42:59.438742+08:00 boston kernel: ACPI: Battery Slot [BAT0] (battery present)
2011-02-09T08:42:59.438743+08:00 boston kernel: Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
2011-02-09T08:42:59.438745+08:00 boston kernel: Non-volatile memory driver v1.3
2011-02-09T08:42:59.438746+08:00 boston kernel: Linux agpgart interface v0.103
2011-02-09T08:42:59.438748+08:00 boston kernel: agpgart-intel 0000:00:00.0: Intel HD Graphics Chipset
2011-02-09T08:42:59.438750+08:00 boston kernel: agpgart-intel 0000:00:00.0: detected gtt size: 524288K total, 262144K mappable
2011-02-09T08:42:59.438752+08:00 boston kernel: agpgart-intel 0000:00:00.0: detected 32768K stolen memory
2011-02-09T08:42:59.438753+08:00 boston kernel: agpgart-intel 0000:00:00.0: AGP aperture is 256M @ 0xd0000000
2011-02-09T08:42:59.438755+08:00 boston kernel: brd: module loaded
2011-02-09T08:42:59.438756+08:00 boston kernel: loop: module loaded
2011-02-09T08:42:59.438758+08:00 boston kernel: megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)
2011-02-09T08:42:59.438759+08:00 boston kernel: megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)
2011-02-09T08:42:59.438761+08:00 boston kernel: megasas: 00.00.05.29-rc1 Tue. Dec. 7 17:00:00 PDT 2010
2011-02-09T08:42:59.438762+08:00 boston kernel: mpt2sas version 07.100.00.00 loaded
2011-02-09T08:42:59.438764+08:00 boston kernel: ahci 0000:00:1f.2: version 3.0
2011-02-09T08:42:59.438765+08:00 boston kernel: ahci 0000:00:1f.2: PCI INT B -> GSI 16 (level, low) -> IRQ 16
2011-02-09T08:42:59.438767+08:00 boston kernel: ahci 0000:00:1f.2: irq 40 for MSI/MSI-X
2011-02-09T08:42:59.438769+08:00 boston kernel: ahci: SSS flag set, parallel bus scan disabled
2011-02-09T08:42:59.438770+08:00 boston kernel: ahci 0000:00:1f.2: AHCI 0001.0300 32 slots 6 ports 3 Gbps 0x31 impl SATA mode
2011-02-09T08:42:59.438772+08:00 boston kernel: ahci 0000:00:1f.2: flags: 64bit ncq sntf stag pm led clo pmp pio slum part ems sxs apst 
2011-02-09T08:42:59.438774+08:00 boston kernel: ahci 0000:00:1f.2: setting latency timer to 64
2011-02-09T08:42:59.438775+08:00 boston kernel: scsi0 : ahci
2011-02-09T08:42:59.438777+08:00 boston kernel: scsi1 : ahci
2011-02-09T08:42:59.438778+08:00 boston kernel: scsi2 : ahci
2011-02-09T08:42:59.438779+08:00 boston kernel: scsi3 : ahci
2011-02-09T08:42:59.438781+08:00 boston kernel: scsi4 : ahci
2011-02-09T08:42:59.438792+08:00 boston kernel: scsi5 : ahci
2011-02-09T08:42:59.438795+08:00 boston kernel: ata1: SATA max UDMA/133 abar m2048@0xf2727000 port 0xf2727100 irq 40
2011-02-09T08:42:59.438796+08:00 boston kernel: ata2: DUMMY
2011-02-09T08:42:59.438798+08:00 boston kernel: ata3: DUMMY
2011-02-09T08:42:59.438799+08:00 boston kernel: ata4: DUMMY
2011-02-09T08:42:59.438801+08:00 boston kernel: ata5: SATA max UDMA/133 abar m2048@0xf2727000 port 0xf2727300 irq 40
2011-02-09T08:42:59.438802+08:00 boston kernel: ata6: SATA max UDMA/133 abar m2048@0xf2727000 port 0xf2727380 irq 40
2011-02-09T08:42:59.438804+08:00 boston kernel: Intel(R) Gigabit Ethernet Network Driver - version 2.1.0-k2
2011-02-09T08:42:59.438805+08:00 boston kernel: Copyright (c) 2007-2009 Intel Corporation.
2011-02-09T08:42:59.438807+08:00 boston kernel: ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 3.0.12-k2
2011-02-09T08:42:59.438808+08:00 boston kernel: ixgbe: Copyright (c) 1999-2010 Intel Corporation.
2011-02-09T08:42:59.438810+08:00 boston kernel: pcnet32: pcnet32.c:v1.35 21.Apr.2008 tsbogend@alpha.franken.de
2011-02-09T08:42:59.438811+08:00 boston kernel: PPP generic driver version 2.4.2
2011-02-09T08:42:59.438813+08:00 boston kernel: PPP Deflate Compression module registered
2011-02-09T08:42:59.438814+08:00 boston kernel: PPP BSD Compression module registered
2011-02-09T08:42:59.438815+08:00 boston kernel: tun: Universal TUN/TAP device driver, 1.6
2011-02-09T08:42:59.438817+08:00 boston kernel: tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
2011-02-09T08:42:59.438819+08:00 boston kernel: Fusion MPT base driver 3.04.17
2011-02-09T08:42:59.438820+08:00 boston kernel: Copyright (c) 1999-2008 LSI Corporation
2011-02-09T08:42:59.438821+08:00 boston kernel: Fusion MPT SPI Host driver 3.04.17
2011-02-09T08:42:59.438823+08:00 boston kernel: Fusion MPT SAS Host driver 3.04.17
2011-02-09T08:42:59.438824+08:00 boston kernel: ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
2011-02-09T08:42:59.438826+08:00 boston kernel: ehci_hcd 0000:00:1a.0: power state changed by ACPI to D0
2011-02-09T08:42:59.438827+08:00 boston kernel: ehci_hcd 0000:00:1a.0: power state changed by ACPI to D0
2011-02-09T08:42:59.438829+08:00 boston kernel: ehci_hcd 0000:00:1a.0: PCI INT D -> GSI 23 (level, low) -> IRQ 23
2011-02-09T08:42:59.438830+08:00 boston kernel: ehci_hcd 0000:00:1a.0: setting latency timer to 64
2011-02-09T08:42:59.438832+08:00 boston kernel: ehci_hcd 0000:00:1a.0: EHCI Host Controller
2011-02-09T08:42:59.438833+08:00 boston kernel: ehci_hcd 0000:00:1a.0: new USB bus registered, assigned bus number 1
2011-02-09T08:42:59.438835+08:00 boston kernel: Refined TSC clocksource calibration: 2127.999 MHz.
2011-02-09T08:42:59.438836+08:00 boston kernel: Switching to clocksource tsc
2011-02-09T08:42:59.438837+08:00 boston kernel: ehci_hcd 0000:00:1a.0: debug port 2
2011-02-09T08:42:59.438839+08:00 boston kernel: ehci_hcd 0000:00:1a.0: cache line size of 64 is not supported
2011-02-09T08:42:59.438841+08:00 boston kernel: ehci_hcd 0000:00:1a.0: irq 23, io mem 0xf2728000
2011-02-09T08:42:59.438842+08:00 boston kernel: ehci_hcd 0000:00:1a.0: USB 2.0 started, EHCI 1.00
2011-02-09T08:42:59.438843+08:00 boston kernel: hub 1-0:1.0: USB hub found
2011-02-09T08:42:59.438845+08:00 boston kernel: hub 1-0:1.0: 3 ports detected
2011-02-09T08:42:59.438846+08:00 boston kernel: ehci_hcd 0000:00:1d.0: power state changed by ACPI to D0
2011-02-09T08:42:59.438848+08:00 boston kernel: ehci_hcd 0000:00:1d.0: power state changed by ACPI to D0
2011-02-09T08:42:59.438849+08:00 boston kernel: ehci_hcd 0000:00:1d.0: PCI INT D -> GSI 19 (level, low) -> IRQ 19
2011-02-09T08:42:59.438851+08:00 boston kernel: ehci_hcd 0000:00:1d.0: setting latency timer to 64
2011-02-09T08:42:59.438852+08:00 boston kernel: ehci_hcd 0000:00:1d.0: EHCI Host Controller
2011-02-09T08:42:59.438854+08:00 boston kernel: ehci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 2
2011-02-09T08:42:59.438855+08:00 boston kernel: ehci_hcd 0000:00:1d.0: debug port 2
2011-02-09T08:42:59.438857+08:00 boston kernel: ehci_hcd 0000:00:1d.0: cache line size of 64 is not supported
2011-02-09T08:42:59.438858+08:00 boston kernel: ehci_hcd 0000:00:1d.0: irq 19, io mem 0xf2728400
2011-02-09T08:42:59.438860+08:00 boston kernel: ehci_hcd 0000:00:1d.0: USB 2.0 started, EHCI 1.00
2011-02-09T08:42:59.438861+08:00 boston kernel: hub 2-0:1.0: USB hub found
2011-02-09T08:42:59.438873+08:00 boston kernel: hub 2-0:1.0: 3 ports detected
2011-02-09T08:42:59.438875+08:00 boston kernel: ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
2011-02-09T08:42:59.438878+08:00 boston kernel: uhci_hcd: USB Universal Host Controller Interface driver
2011-02-09T08:42:59.438880+08:00 boston kernel: i8042: PNP: PS/2 Controller [PNP0303:KBD,PNP0f13:MOU] at 0x60,0x64 irq 1,12
2011-02-09T08:42:59.438881+08:00 boston kernel: serio: i8042 KBD port at 0x60,0x64 irq 1
2011-02-09T08:42:59.438883+08:00 boston kernel: serio: i8042 AUX port at 0x60,0x64 irq 12
2011-02-09T08:42:59.438884+08:00 boston kernel: mousedev: PS/2 mouse device common for all mice
2011-02-09T08:42:59.438886+08:00 boston kernel: input: PC Speaker as /devices/platform/pcspkr/input/input3
2011-02-09T08:42:59.439032+08:00 boston kernel: rtc_cmos 00:08: RTC can wake from S4
2011-02-09T08:42:59.439044+08:00 boston kernel: input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input4
2011-02-09T08:42:59.439046+08:00 boston kernel: rtc_cmos 00:08: rtc core: registered rtc_cmos as rtc0
2011-02-09T08:42:59.439048+08:00 boston kernel: rtc0: alarms up to one month, y3k, 114 bytes nvram, hpet irqs
2011-02-09T08:42:59.439050+08:00 boston kernel: lirc_dev: IR Remote Control driver registered, major 251 
2011-02-09T08:42:59.439051+08:00 boston kernel: IR RC5 (streamzap) protocol handler initialized
2011-02-09T08:42:59.439053+08:00 boston kernel: IR LIRC bridge handler initialized
2011-02-09T08:42:59.439054+08:00 boston kernel: Linux video capture interface: v2.00
2011-02-09T08:42:59.439056+08:00 boston kernel: coretemp coretemp.0: TjMax is 105 C.
2011-02-09T08:42:59.439057+08:00 boston kernel: coretemp coretemp.2: TjMax is 105 C.
2011-02-09T08:42:59.439059+08:00 boston kernel: device-mapper: ioctl: 4.19.1-ioctl (2011-01-07) initialised: dm-devel@redhat.com
2011-02-09T08:42:59.439060+08:00 boston kernel: EDAC MC: Ver: 2.1.0 Feb  7 2011
2011-02-09T08:42:59.439061+08:00 boston kernel: cpuidle: using governor ladder
2011-02-09T08:42:59.439063+08:00 boston kernel: cpuidle: using governor menu
2011-02-09T08:42:59.439064+08:00 boston kernel: thinkpad_acpi: ThinkPad ACPI Extras v0.24
2011-02-09T08:42:59.439065+08:00 boston kernel: thinkpad_acpi: http://ibm-acpi.sf.net/
2011-02-09T08:42:59.439067+08:00 boston kernel: thinkpad_acpi: ThinkPad BIOS 6QET62WW (1.32 ), EC 6QHT31WW-1.12
2011-02-09T08:42:59.439068+08:00 boston kernel: thinkpad_acpi: Lenovo ThinkPad X201s, model 5413FGA
2011-02-09T08:42:59.439070+08:00 boston kernel: thinkpad_acpi: detected a 8-level brightness capable ThinkPad
2011-02-09T08:42:59.439071+08:00 boston kernel: thinkpad_acpi: rfkill switch tpacpi_bluetooth_sw: radio is blocked
2011-02-09T08:42:59.439073+08:00 boston kernel: Registered led device: tpacpi::thinklight
2011-02-09T08:42:59.439074+08:00 boston kernel: Registered led device: tpacpi::power
2011-02-09T08:42:59.439081+08:00 boston kernel: Registered led device: tpacpi::standby
2011-02-09T08:42:59.439083+08:00 boston kernel: Registered led device: tpacpi::thinkvantage
2011-02-09T08:42:59.439085+08:00 boston kernel: thinkpad_acpi: volume: disabled as there is no ALSA support in this kernel
2011-02-09T08:42:59.439090+08:00 boston kernel: input: ThinkPad Extra Buttons as /devices/platform/thinkpad_acpi/input/input5
2011-02-09T08:42:59.439092+08:00 boston kernel: HDA Intel 0000:00:1b.0: PCI INT B -> GSI 17 (level, low) -> IRQ 17
2011-02-09T08:42:59.439093+08:00 boston kernel: HDA Intel 0000:00:1b.0: irq 41 for MSI/MSI-X
2011-02-09T08:42:59.439095+08:00 boston kernel: HDA Intel 0000:00:1b.0: setting latency timer to 64
2011-02-09T08:42:59.439096+08:00 boston kernel: ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
2011-02-09T08:42:59.439098+08:00 boston kernel: ata1.00: ACPI cmd ef/02:00:00:00:00:a0 (unknown) succeeded
2011-02-09T08:42:59.439100+08:00 boston kernel: ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (unknown) filtered out
2011-02-09T08:42:59.439101+08:00 boston kernel: ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (unknown) filtered out
2011-02-09T08:42:59.439103+08:00 boston kernel: ata1.00: ATA-7: SAMSUNG SSD PM800 2.5" 256GB, VBM25D1Q, max UDMA/100
2011-02-09T08:42:59.439104+08:00 boston kernel: ata1.00: 500118192 sectors, multi 16: LBA48 NCQ (depth 31/32), AA
2011-02-09T08:42:59.439106+08:00 boston kernel: ata1.00: ACPI cmd ef/02:00:00:00:00:a0 (unknown) succeeded
2011-02-09T08:42:59.439109+08:00 boston kernel: ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (unknown) filtered out
2011-02-09T08:42:59.439111+08:00 boston kernel: ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (unknown) filtered out
2011-02-09T08:42:59.439112+08:00 boston kernel: ata1.00: configured for UDMA/100
2011-02-09T08:42:59.439114+08:00 boston kernel: scsi 0:0:0:0: Direct-Access     ATA      SAMSUNG SSD PM80 VBM2 PQ: 0 ANSI: 5
2011-02-09T08:42:59.439116+08:00 boston kernel: sd 0:0:0:0: [sda] 500118192 512-byte logical blocks: (256 GB/238 GiB)
2011-02-09T08:42:59.439117+08:00 boston kernel: sd 0:0:0:0: [sda] Write Protect is off
2011-02-09T08:42:59.439119+08:00 boston kernel: sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
2011-02-09T08:42:59.439122+08:00 boston kernel: sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
2011-02-09T08:42:59.439124+08:00 boston kernel: sd 0:0:0:0: Attached scsi generic sg0 type 0
2011-02-09T08:42:59.439125+08:00 boston kernel: sda: sda1 sda2 sda3 sda4 < sda5 sda6 sda7 sda8 sda9 sda10 sda11 sda12 sda13 sda14 sda15 >
2011-02-09T08:42:59.439127+08:00 boston kernel: sd 0:0:0:0: [sda] Attached SCSI disk
2011-02-09T08:42:59.439128+08:00 boston kernel: hda-codec: No codec parser is available
2011-02-09T08:42:59.439130+08:00 boston kernel: ALSA device list:
2011-02-09T08:42:59.439131+08:00 boston kernel:  #0: HDA Intel at 0xf2520000 irq 41
2011-02-09T08:42:59.439132+08:00 boston kernel: Netfilter messages via NETLINK v0.30.
2011-02-09T08:42:59.439135+08:00 boston kernel: nf_conntrack version 0.5.0 (16384 buckets, 65536 max)
2011-02-09T08:42:59.439137+08:00 boston kernel: ctnetlink v0.93: registering with nfnetlink.
2011-02-09T08:42:59.439138+08:00 boston kernel: ip_tables: (C) 2000-2006 Netfilter Core Team
2011-02-09T08:42:59.439140+08:00 boston kernel: arp_tables: (C) 2002 David S. Miller
2011-02-09T08:42:59.439141+08:00 boston kernel: TCP bic registered
2011-02-09T08:42:59.439142+08:00 boston kernel: TCP cubic registered
2011-02-09T08:42:59.439144+08:00 boston kernel: TCP highspeed registered
2011-02-09T08:42:59.439147+08:00 boston kernel: NET: Registered protocol family 17
2011-02-09T08:42:59.439159+08:00 boston kernel: lib80211: common routines for IEEE802.11 drivers
2011-02-09T08:42:59.439161+08:00 boston kernel: lib80211_crypt: registered algorithm 'NULL'
2011-02-09T08:42:59.439163+08:00 boston kernel: rtc_cmos 00:08: setting system clock to 2011-02-09 00:42:57 UTC (1297212177)
2011-02-09T08:42:59.439164+08:00 boston kernel: hub 1-1:1.0: USB hub found
2011-02-09T08:42:59.439166+08:00 boston kernel: hub 1-1:1.0: 6 ports detected
2011-02-09T08:42:59.439167+08:00 boston kernel: IBM TrackPoint firmware: 0x0e, buttons: 3/3
2011-02-09T08:42:59.439169+08:00 boston kernel: ata5: SATA link down (SStatus 0 SControl 300)
2011-02-09T08:42:59.439170+08:00 boston kernel: input: TPPS/2 IBM TrackPoint as /devices/platform/i8042/serio1/input/input6
2011-02-09T08:42:59.439172+08:00 boston kernel: hub 2-1:1.0: USB hub found
2011-02-09T08:42:59.439173+08:00 boston kernel: hub 2-1:1.0: 8 ports detected
2011-02-09T08:42:59.439175+08:00 boston kernel: ata6: SATA link down (SStatus 0 SControl 300)
2011-02-09T08:42:59.439176+08:00 boston kernel: VFS: Mounted root (reiserfs filesystem) readonly on device 8:2.
2011-02-09T08:42:59.439178+08:00 boston kernel: Freeing unused kernel memory: 576k freed
2011-02-09T08:42:59.439179+08:00 boston kernel: REISERFS (device sda9): replayed 9 transactions in 0 seconds
2011-02-09T08:42:59.439181+08:00 boston kernel: REISERFS (device sda11): replayed 7 transactions in 0 seconds
2011-02-09T08:42:59.439183+08:00 boston kernel: REISERFS (device sda12): replayed 7 transactions in 0 seconds
2011-02-09T08:42:59.439184+08:00 boston kernel: REISERFS (device dm-0): replayed 7 transactions in 0 seconds
2011-02-09T08:42:59.439187+08:00 boston kernel: Adding 8290300k swap on /dev/sda3.  Priority:-1 extents:1 across:8290300k SS
2011-02-09T08:42:59.998249+08:00 boston kernel: [drm] Initialized drm 1.1.0 20060810
2011-02-09T08:43:00.018253+08:00 boston kernel: i915 0000:00:02.0: power state changed by ACPI to D0
2011-02-09T08:43:00.018283+08:00 boston kernel: i915 0000:00:02.0: power state changed by ACPI to D0
2011-02-09T08:43:00.018288+08:00 boston kernel: i915 0000:00:02.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
2011-02-09T08:43:00.018291+08:00 boston kernel: i915 0000:00:02.0: setting latency timer to 64
2011-02-09T08:43:00.108249+08:00 boston kernel: i915 0000:00:02.0: irq 42 for MSI/MSI-X
2011-02-09T08:43:00.108276+08:00 boston kernel: [drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
2011-02-09T08:43:00.108281+08:00 boston kernel: [drm] Driver supports precise vblank timestamp query.
2011-02-09T08:43:00.198260+08:00 boston kernel: vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem
2011-02-09T08:43:00.298256+08:00 boston kernel: Console: switching to colour frame buffer device 180x56
2011-02-09T08:43:00.298284+08:00 boston kernel: fb0: inteldrmfb frame buffer device
2011-02-09T08:43:00.298288+08:00 boston kernel: drm: registered panic notifier
2011-02-09T08:43:00.298291+08:00 boston kernel: No ACPI video bus found
2011-02-09T08:43:00.298294+08:00 boston kernel: [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0

[-- Attachment #3: Xorg.0.log.old --]
[-- Type: application/octet-stream, Size: 19097 bytes --]

[     4.872] 
This is a pre-release version of the X server from The X.Org Foundation.
It is not supported in any way.
Bugs may be filed in the bugzilla at http://bugs.freedesktop.org/.
Select the "xorg" product for bugs you find in this release.
Before reporting bugs in pre-release versions please check the
latest version in the X.Org Foundation git repository.
See http://wiki.x.org/wiki/GitPage for git access instructions.
[     4.872] 
X.Org X Server 1.9.99.901 (1.10.0 RC 1)
Release Date: 2010-12-06
[     4.872] X Protocol Version 11, Revision 0
[     4.872] Build Operating System: Linux 2.6.38-rc3 x86_64 
[     4.872] Current Operating System: Linux boston 2.6.38-rc4 #2 SMP PREEMPT Tue Feb 8 09:13:37 SGT 2011 x86_64
[     4.872] Kernel command line: BOOT_IMAGE=(hd0,14)/linux/bzc1 root=/dev/sda2 ro resume=/dev/sda3 reboot=bios mce x11 snd-hda-intel.model=lenovo-x200 nf_conntrack_sip.sip_direct_signalling=0 nf_conntrack_sip.sip_direct_media=0 testing_only=\"this is got to be good. Now I can send in a very long line just like 2.4 and need not worry about the line being too long. What a great way to start a great year!!! Cool!\"
[     4.872] Build Date: 04 February 2011  12:23:04AM
[     4.872]  
[     4.872] Current version of pixman: 0.21.5
[     4.872] 	Before reporting problems, check http://wiki.x.org
	to make sure that you have the latest version.
[     4.872] Markers: (--) probed, (**) from config file, (==) default setting,
	(++) from command line, (!!) notice, (II) informational,
	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
[     4.872] (==) Log file: "/usr/X11/var/log/Xorg.0.log", Time: Wed Feb  9 08:42:05 2011
[     4.874] (==) Using config file: "/etc/X11/xorg.conf"
[     4.875] (==) Using system config directory "/usr/X11/share/X11/xorg.conf.d"
[     4.876] (==) ServerLayout "Simple Layout"
[     4.876] (**) |-->Screen "Screen X61" (0)
[     4.876] (**) |   |-->Monitor "Monitor"
[     4.876] (**) |   |-->Device "Device X61"
[     4.876] (**) |-->Input Device "Keyboard1"
[     4.876] (**) |-->Input Device "Mouse1"
[     4.876] (**) Option "DontZap" "off"
[     4.877] (**) Option "Pixmap" "32"
[     4.877] (==) Not automatically adding devices
[     4.877] (==) Not automatically enabling devices
[     4.884] (**) FontPath set to:
	/usr/X11/share/fonts/X11/75dpi,
	/usr/X11/share/fonts/X11/100dpi,
	/usr/X11/share/fonts/X11/Type1,
	/usr/X11/share/fonts/X11/Speedo,
	/usr/X11/share/fonts/X11/cyrillic,
	/usr/X11/share/fonts/X11/encodings,
	/usr/X11/share/fonts/X11/misc,
	/usr/X11/share/fonts/X11/TTF,
	/usr/X11/share/fonts/X11/OTF,
	/usr/share/fonts/utf8,
	/usr/share/fonts/Win2k,
	/usr/X11/share/fonts/X11/misc/,
	/usr/X11/share/fonts/X11/TTF/,
	/usr/X11/share/fonts/X11/OTF/,
	/usr/X11/share/fonts/X11/Type1/,
	/usr/X11/share/fonts/X11/100dpi/,
	/usr/X11/share/fonts/X11/75dpi/
[     4.884] (**) ModulePath set to "/usr/X11/lib/xorg/modules"
[     4.884] (II) Loader magic: 0x7cab80
[     4.884] (II) Module ABI versions:
[     4.884] 	X.Org ANSI C Emulation: 0.4
[     4.884] 	X.Org Video Driver: 9.0
[     4.884] 	X.Org XInput driver : 12.2
[     4.884] 	X.Org Server Extension : 5.0
[     4.885] (--) PCI:*(0:0:2:0) 8086:0046:17aa:215a rev 2, Mem @ 0xf2000000/4194304, 0xd0000000/268435456, I/O @ 0x00001800/8
[     4.885] (II) Open ACPI successful (/var/run/acpid.socket)
[     4.885] (II) "extmod" will be loaded by default.
[     4.885] (II) "dbe" will be loaded by default.
[     4.885] (II) "glx" will be loaded by default.
[     4.885] (II) "record" will be loaded by default.
[     4.885] (II) "dri" will be loaded by default.
[     4.885] (II) "dri2" will be loaded by default.
[     4.885] (II) LoadModule: "vbe"
[     4.887] (II) Loading /usr/X11/lib/xorg/modules/libvbe.so
[     4.889] (II) Module vbe: vendor="X.Org Foundation"
[     4.889] 	compiled for 1.9.99.901, module version = 1.1.0
[     4.889] 	ABI class: X.Org Video Driver, version 9.0
[     4.889] (II) LoadModule: "extmod"
[     4.893] (II) Loading /usr/X11/lib/xorg/modules/extensions/libextmod.so
[     4.898] (II) Module extmod: vendor="X.Org Foundation"
[     4.898] 	compiled for 1.9.99.901, module version = 1.0.0
[     4.898] 	Module class: X.Org Server Extension
[     4.898] 	ABI class: X.Org Server Extension, version 5.0
[     4.898] (II) Loading extension MIT-SCREEN-SAVER
[     4.898] (II) Loading extension XFree86-VidModeExtension
[     4.898] (II) Loading extension XFree86-DGA
[     4.898] (II) Loading extension DPMS
[     4.898] (II) Loading extension XVideo
[     4.898] (II) Loading extension XVideo-MotionCompensation
[     4.898] (II) Loading extension X-Resource
[     4.898] (II) LoadModule: "dbe"
[     4.900] (II) Loading /usr/X11/lib/xorg/modules/extensions/libdbe.so
[     4.901] (II) Module dbe: vendor="X.Org Foundation"
[     4.901] 	compiled for 1.9.99.901, module version = 1.0.0
[     4.901] 	Module class: X.Org Server Extension
[     4.901] 	ABI class: X.Org Server Extension, version 5.0
[     4.901] (II) Loading extension DOUBLE-BUFFER
[     4.901] (II) LoadModule: "glx"
[     4.901] (II) Loading /usr/X11/lib/xorg/modules/extensions/libglx.so
[     4.906] (II) Module glx: vendor="X.Org Foundation"
[     4.906] 	compiled for 1.9.99.901, module version = 1.0.0
[     4.906] 	ABI class: X.Org Server Extension, version 5.0
[     4.906] (==) AIGLX enabled
[     4.906] (II) Loading extension GLX
[     4.907] (II) LoadModule: "record"
[     4.908] (II) Loading /usr/X11/lib/xorg/modules/extensions/librecord.so
[     4.909] (II) Module record: vendor="X.Org Foundation"
[     4.910] 	compiled for 1.9.99.901, module version = 1.13.0
[     4.910] 	Module class: X.Org Server Extension
[     4.910] 	ABI class: X.Org Server Extension, version 5.0
[     4.910] (II) Loading extension RECORD
[     4.910] (II) LoadModule: "dri"
[     4.910] (II) Loading /usr/X11/lib/xorg/modules/extensions/libdri.so
[     4.915] (II) Module dri: vendor="X.Org Foundation"
[     4.915] 	compiled for 1.9.99.901, module version = 1.0.0
[     4.915] 	ABI class: X.Org Server Extension, version 5.0
[     4.915] (II) Loading extension XFree86-DRI
[     4.915] (II) LoadModule: "dri2"
[     4.915] (II) Loading /usr/X11/lib/xorg/modules/extensions/libdri2.so
[     4.917] (II) Module dri2: vendor="X.Org Foundation"
[     4.917] 	compiled for 1.9.99.901, module version = 1.2.0
[     4.917] 	ABI class: X.Org Server Extension, version 5.0
[     4.917] (II) Loading extension DRI2
[     4.917] (II) LoadModule: "intel"
[     4.917] (II) Loading /usr/X11/lib/xorg/modules/drivers/intel_drv.so
[     4.924] (II) Module intel: vendor="X.Org Foundation"
[     4.924] 	compiled for 1.9.99.901, module version = 2.14.0
[     4.924] 	Module class: X.Org Video Driver
[     4.924] 	ABI class: X.Org Video Driver, version 9.0
[     4.924] (II) LoadModule: "kbd"
[     4.924] (II) Loading /usr/X11/lib/xorg/modules/input/kbd_drv.so
[     4.926] (II) Module kbd: vendor="X.Org Foundation"
[     4.926] 	compiled for 1.9.99.901, module version = 1.5.0
[     4.926] 	Module class: X.Org XInput Driver
[     4.926] 	ABI class: X.Org XInput driver, version 12.1
[     4.926] (II) LoadModule: "mouse"
[     4.926] (II) Loading /usr/X11/lib/xorg/modules/input/mouse_drv.so
[     4.927] (II) Module mouse: vendor="X.Org Foundation"
[     4.927] 	compiled for 1.9.99.901, module version = 1.6.99
[     4.927] 	Module class: X.Org XInput Driver
[     4.927] 	ABI class: X.Org XInput driver, version 12.1
[     4.927] (II) intel: Driver for Intel Integrated Graphics Chipsets: i810,
	i810-dc100, i810e, i815, i830M, 845G, 854, 852GM/855GM, 865G, 915G,
	E7221 (i915), 915GM, 945G, 945GM, 945GME, Pineview GM, Pineview G,
	965G, G35, 965Q, 946GZ, 965GM, 965GME/GLE, G33, Q35, Q33, GM45,
	4 Series, G45/G43, Q45/Q43, G41, B43, B43, Clarkdale, Arrandale,
	Sandybridge, Sandybridge, Sandybridge, Sandybridge, Sandybridge,
	Sandybridge, Sandybridge
[     4.927] (--) using VT number 5

[     5.242] (II) Loading /usr/X11/lib/xorg/modules/drivers/intel_drv.so
[     5.242] (WW) VGA arbiter: cannot open kernel arbiter, no multi-card support
[     5.242] drmOpenDevice: node name is /dev/dri/card0
[     5.242] drmOpenDevice: open result is 9, (OK)
[     5.302] drmOpenByBusid: Searching for BusID pci:0000:00:02.0
[     5.302] drmOpenDevice: node name is /dev/dri/card0
[     5.302] drmOpenDevice: open result is 9, (OK)
[     5.302] drmOpenByBusid: drmOpenMinor returns 9
[     5.302] drmOpenByBusid: drmGetBusid reports pci:0000:00:02.0
[     5.302] (**) intel(0): Depth 24, (--) framebuffer bpp 32
[     5.302] (==) intel(0): RGB weight 888
[     5.302] (==) intel(0): Default visual is TrueColor
[     5.302] (**) intel(0): Option "DRI" "true"
[     5.302] (**) intel(0): Option "SwapbuffersWait" "true"
[     5.302] (**) intel(0): Option "XvMC" "true"
[     5.302] (II) intel(0): Integrated Graphics Chipset: Intel(R) Arrandale
[     5.302] (--) intel(0): Chipset: "Arrandale"
[     5.302] (**) intel(0): Tiling enabled
[     5.302] (**) intel(0): SwapBuffers wait enabled
[     5.302] (==) intel(0): video overlay key set to 0x101fe
[     5.302] (II) intel(0): Output LVDS1 using monitor section Monitor
[     5.302] (II) intel(0): found backlight control interface /sys/class/backlight/thinkpad_screen
[     5.302] (II) intel(0): Output VGA1 has no monitor section
[     5.307] (II) intel(0): Output HDMI1 has no monitor section
[     5.308] (II) intel(0): Output DP1 has no monitor section
[     5.308] (II) intel(0): EDID for output LVDS1
[     5.308] (II) intel(0): Manufacturer: LEN  Model: 4014  Serial#: 0
[     5.308] (II) intel(0): Year: 2009  Week: 52
[     5.308] (II) intel(0): EDID Version: 1.3
[     5.308] (II) intel(0): Digital Display Input
[     5.308] (II) intel(0): Max Image Size [cm]: horiz.: 26  vert.: 16
[     5.308] (II) intel(0): Gamma: 2.20
[     5.308] (II) intel(0): DPMS capabilities: StandBy Suspend Off
[     5.308] (II) intel(0): Supported color encodings: RGB 4:4:4 YCrCb 4:4:4 
[     5.308] (II) intel(0): First detailed timing is preferred mode
[     5.308] (II) intel(0): redX: 0.577 redY: 0.338   greenX: 0.310 greenY: 0.563
[     5.308] (II) intel(0): blueX: 0.158 blueY: 0.157   whiteX: 0.313 whiteY: 0.329
[     5.308] (II) intel(0): Manufacturer's mask: 0
[     5.308] (II) intel(0): Supported detailed timing:
[     5.308] (II) intel(0): clock: 74.1 MHz   Image Size:  261 x 163 mm
[     5.308] (II) intel(0): h_active: 1440  h_sync: 1464  h_sync_end 1480 h_blank_end 1600 h_border: 0
[     5.308] (II) intel(0): v_active: 900  v_sync: 903  v_sync_end 909 v_blanking: 926 v_border: 0
[     5.308] (II) intel(0): Supported detailed timing:
[     5.308] (II) intel(0): clock: 74.1 MHz   Image Size:  261 x 163 mm
[     5.308] (II) intel(0): h_active: 1440  h_sync: 1464  h_sync_end 1480 h_blank_end 1600 h_border: 0
[     5.308] (II) intel(0): v_active: 900  v_sync: 903  v_sync_end 909 v_blanking: 926 v_border: 0
[     5.308] (II) intel(0): Unknown vendor-specific block f
[     5.308] (II) intel(0):  LTD121EQ3B
[     5.308] (II) intel(0): EDID (in hex):
[     5.308] (II) intel(0): 	00ffffffffffff0030ae144000000000
[     5.308] (II) intel(0): 	34130103801a1078eae59593564f9028
[     5.308] (II) intel(0): 	28505400000001010101010101010101
[     5.308] (II) intel(0): 	010101010101f01ca0a050841a301810
[     5.308] (II) intel(0): 	360005a310000018f01ca0a050841a30
[     5.308] (II) intel(0): 	1810360005a3100000180000000f0095
[     5.308] (II) intel(0): 	0a32950a3219010030640055000000fe
[     5.308] (II) intel(0): 	004c5444313231455133420a20200088
[     5.308] (II) intel(0): EDID vendor "LEN", prod id 16404
[     5.309] (II) intel(0): Printing DDC gathered Modelines:
[     5.309] (II) intel(0): Modeline "1440x900"x0.0   74.08  1440 1464 1480 1600  900 903 909 926 -hsync -vsync (46.3 kHz)
[     5.309] (II) intel(0): Not using default mode "320x240" (doublescan mode not supported)
[     5.309] (II) intel(0): Not using default mode "400x300" (doublescan mode not supported)
[     5.309] (II) intel(0): Not using default mode "400x300" (doublescan mode not supported)
[     5.309] (II) intel(0): Not using default mode "512x384" (doublescan mode not supported)
[     5.309] (II) intel(0): Not using default mode "640x480" (doublescan mode not supported)
[     5.309] (II) intel(0): Not using default mode "640x512" (doublescan mode not supported)
[     5.309] (II) intel(0): Not using default mode "800x600" (doublescan mode not supported)
[     5.309] (II) intel(0): Not using default mode "896x672" (doublescan mode not supported)
[     5.309] (II) intel(0): Not using default mode "928x696" (doublescan mode not supported)
[     5.309] (II) intel(0): Not using default mode "960x720" (doublescan mode not supported)
[     5.309] (II) intel(0): Not using default mode "700x525" (doublescan mode not supported)
[     5.309] (II) intel(0): Not using default mode "1024x768" (doublescan mode not supported)
[     5.309] (II) intel(0): Printing probed modes for output LVDS1
[     5.309] (II) intel(0): Modeline "1440x900"x50.0   74.08  1440 1464 1480 1600  900 903 909 926 -hsync -vsync (46.3 kHz)
[     5.309] (II) intel(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz)
[     5.309] (II) intel(0): Modeline "800x600"x60.3   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz)
[     5.309] (II) intel(0): Modeline "800x600"x56.2   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz)
[     5.309] (II) intel(0): Modeline "640x480"x59.9   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz)
[     5.309] (II) intel(0): EDID for output VGA1
[     5.313] (II) intel(0): EDID for output HDMI1
[     5.314] (II) intel(0): EDID for output DP1
[     5.315] (II) intel(0): Output LVDS1 connected
[     5.315] (II) intel(0): Output VGA1 disconnected
[     5.315] (II) intel(0): Output HDMI1 disconnected
[     5.315] (II) intel(0): Output DP1 disconnected
[     5.315] (II) intel(0): Using exact sizes for initial modes
[     5.315] (II) intel(0): Output LVDS1 using initial mode 1440x900
[     5.315] (II) intel(0): Using default gamma of (1.0, 1.0, 1.0) unless otherwise stated.
[     5.315] (II) intel(0): Kernel page flipping support detected, enabling
[     5.315] (**) intel(0): Display dimensions: (260, 160) mm
[     5.315] (**) intel(0): DPI set to (140, 142)
[     5.315] (II) Loading sub module "fb"
[     5.315] (II) LoadModule: "fb"
[     5.315] (II) Loading /usr/X11/lib/xorg/modules/libfb.so
[     5.318] (II) Module fb: vendor="X.Org Foundation"
[     5.319] 	compiled for 1.9.99.901, module version = 1.0.0
[     5.319] 	ABI class: X.Org ANSI C Emulation, version 0.4
[     5.319] (II) Loading sub module "dri2"
[     5.319] (II) LoadModule: "dri2"
[     5.319] (II) Loading /usr/X11/lib/xorg/modules/extensions/libdri2.so
[     5.319] (II) Module dri2: vendor="X.Org Foundation"
[     5.319] 	compiled for 1.9.99.901, module version = 1.2.0
[     5.319] 	ABI class: X.Org Server Extension, version 5.0
[     5.319] (**) Depth 24 pixmap format is 32 bpp
[     5.319] (II) intel(0): [DRI2] Setup complete
[     5.319] (II) intel(0): [DRI2]   DRI driver: i965
[     5.319] (II) intel(0): Allocated new frame buffer 1472x900 stride 6144, tiled
[     5.327] (II) UXA(0): Driver registered support for the following operations:
[     5.327] (II)         solid
[     5.327] (II)         copy
[     5.327] (II)         composite (RENDER acceleration)
[     5.327] (II)         put_image
[     5.327] (II)         get_image
[     5.327] (**) intel(0): Option "BackingStore" "on"
[     5.327] (**) intel(0): Backing store enabled
[     5.327] (==) intel(0): Silken mouse enabled
[     5.328] (II) intel(0): Initializing HW Cursor
[     5.400] (II) intel(0): RandR 1.2 enabled, ignore the following RandR disabled message.
[     5.401] (**) intel(0): DPMS enabled
[     5.401] (**) intel(0): Intel XvMC decoder enabled
[     5.401] (II) intel(0): Set up textured video
[     5.401] (II) intel(0): [XvMC] xvmc_vld driver initialized.
[     5.401] (II) intel(0): direct rendering: DRI2 Enabled
[     5.401] (--) RandR disabled
[     5.401] (II) Initializing built-in extension Generic Event Extension
[     5.401] (II) Initializing built-in extension SHAPE
[     5.401] (II) Initializing built-in extension MIT-SHM
[     5.401] (II) Initializing built-in extension XInputExtension
[     5.401] (II) Initializing built-in extension XTEST
[     5.401] (II) Initializing built-in extension BIG-REQUESTS
[     5.401] (II) Initializing built-in extension SYNC
[     5.401] (II) Initializing built-in extension XKEYBOARD
[     5.401] (II) Initializing built-in extension XC-MISC
[     5.401] (II) Initializing built-in extension XINERAMA
[     5.401] (II) Initializing built-in extension XFIXES
[     5.401] (II) Initializing built-in extension RENDER
[     5.401] (II) Initializing built-in extension RANDR
[     5.401] (II) Initializing built-in extension COMPOSITE
[     5.401] (II) Initializing built-in extension DAMAGE
[     5.439] (II) AIGLX: enabled GLX_MESA_copy_sub_buffer
[     5.439] (II) AIGLX: enabled GLX_INTEL_swap_event
[     5.439] (II) AIGLX: enabled GLX_SGI_swap_control and GLX_MESA_swap_control
[     5.439] (II) AIGLX: enabled GLX_SGI_make_current_read
[     5.439] (II) AIGLX: GLX_EXT_texture_from_pixmap backed by buffer objects
[     5.439] (II) AIGLX: Loaded and initialized /usr/X11/lib/dri/i965_dri.so
[     5.439] (II) GLX: Initialized DRI2 GL provider for screen 0
[     5.440] (II) intel(0): Setting screen physical size to 381 x 238
[     5.585] (II) Loading /usr/X11/lib/xorg/modules/input/kbd_drv.so
[     5.585] (**) Option "CoreKeyboard"
[     5.585] (**) Keyboard1: always reports core events
[     5.586] (**) Keyboard1: always reports core events
[     5.586] (**) Option "Protocol" "standard"
[     5.586] (**) Keyboard1: Protocol: standard
[     5.586] (**) Option "XkbRules" "xorg"
[     5.586] (**) Option "XkbModel" "pc101"
[     5.586] (**) Option "XkbLayout" "us"
[     5.586] (**) Option "CustomKeycodes" "off"
[     5.586] (**) Keyboard1: CustomKeycodes disabled
[     5.586] (II) XINPUT: Adding extended input device "Keyboard1" (type: KEYBOARD)
[     5.602] (II) Loading /usr/X11/lib/xorg/modules/input/mouse_drv.so
[     5.602] (**) Option "CorePointer"
[     5.602] (**) Mouse1: always reports core events
[     5.602] (**) Option "Protocol" "PS/2"
[     5.602] (**) Option "Device" "/dev/mouse"
[     5.602] (**) Mouse1: Protocol: "PS/2"
[     5.602] (**) Mouse1: always reports core events
[     5.730] (**) Option "Emulate3Buttons"
[     5.730] (**) Mouse1: Emulate3Buttons, Emulate3Timeout: 50
[     5.730] (**) Mouse1: ZAxisMapping: buttons 4 and 5
[     5.730] (**) Mouse1: Buttons: 9
[     5.730] (II) XINPUT: Adding extended input device "Mouse1" (type: MOUSE)
[     5.730] (**) Mouse1: (accel) keeping acceleration scheme 1
[     5.730] (**) Mouse1: (accel) acceleration profile 0
[     5.730] (**) Mouse1: (accel) acceleration factor: 2.000
[     5.730] (**) Mouse1: (accel) acceleration threshold: 4
[     5.870] (II) Mouse1: ps2EnableDataReporting: succeeded

[-- Attachment #4: .config --]
[-- Type: application/octet-stream, Size: 75626 bytes --]

#
# Automatically generated make config: don't edit
# Linux/x86_64 2.6.38-rc4 Kernel Configuration
# Tue Feb  8 09:13:05 2011
#
CONFIG_64BIT=y
# CONFIG_X86_32 is not set
CONFIG_X86_64=y
CONFIG_X86=y
CONFIG_INSTRUCTION_DECODER=y
CONFIG_OUTPUT_FORMAT="elf64-x86-64"
CONFIG_ARCH_DEFCONFIG="arch/x86/configs/x86_64_defconfig"
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_CLOCKSOURCE_WATCHDOG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_MMU=y
CONFIG_ZONE_DMA=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_GENERIC_ISA_DMA=y
CONFIG_GENERIC_IOMAP=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
# CONFIG_RWSEM_GENERIC_SPINLOCK is not set
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_ARCH_HAS_CPU_RELAX=y
CONFIG_ARCH_HAS_DEFAULT_IDLE=y
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_HAVE_SETUP_PER_CPU_AREA=y
CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
CONFIG_HAVE_CPUMASK_OF_CPU_MAP=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ZONE_DMA32=y
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_AUDIT_ARCH=y
CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_X86_64_SMP=y
CONFIG_X86_HT=y
CONFIG_X86_TRAMPOLINE=y
CONFIG_ARCH_HWEIGHT_CFLAGS="-fcall-saved-rdi -fcall-saved-rsi -fcall-saved-rdx -fcall-saved-rcx -fcall-saved-r8 -fcall-saved-r9 -fcall-saved-r10 -fcall-saved-r11"
# CONFIG_KTIME_SCALAR is not set
CONFIG_ARCH_CPU_PROBE_RELEASE=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_CONSTRUCTORS=y
CONFIG_HAVE_IRQ_WORK=y
CONFIG_IRQ_WORK=y

#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_LOCK_KERNEL=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_CROSS_COMPILE=""
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_BZIP2=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_HAVE_KERNEL_LZO=y
# CONFIG_KERNEL_GZIP is not set
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
CONFIG_KERNEL_XZ=y
# CONFIG_KERNEL_LZO is not set
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_AUDIT is not set
CONFIG_HAVE_GENERIC_HARDIRQS=y

#
# IRQ subsystem
#
CONFIG_GENERIC_HARDIRQS=y
# CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED is not set
CONFIG_HAVE_SPARSE_IRQ=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_PENDING_IRQ=y
# CONFIG_AUTO_IRQ_AFFINITY is not set
# CONFIG_IRQ_PER_CPU is not set
# CONFIG_HARDIRQS_SW_RESEND is not set
# CONFIG_SPARSE_IRQ is not set

#
# RCU Subsystem
#
CONFIG_TREE_PREEMPT_RCU=y
CONFIG_PREEMPT_RCU=y
# CONFIG_RCU_TRACE is not set
CONFIG_RCU_FANOUT=32
# CONFIG_RCU_FANOUT_EXACT is not set
# CONFIG_TREE_RCU_TRACE is not set
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=15
CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y
# CONFIG_CGROUPS is not set
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_IPC_NS is not set
# CONFIG_USER_NS is not set
# CONFIG_PID_NS is not set
# CONFIG_NET_NS is not set
# CONFIG_SCHED_AUTOGROUP is not set
# CONFIG_SYSFS_DEPRECATED is not set
# CONFIG_RELAY is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
# CONFIG_EXPERT is not set
# CONFIG_EMBEDDED is not set
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_PCSPKR_PLATFORM=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_HAVE_PERF_EVENTS=y

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_PERF_COUNTERS is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_PCI_QUIRKS=y
CONFIG_SLUB_DEBUG=y
# CONFIG_COMPAT_BRK is not set
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_PROFILING is not set
CONFIG_HAVE_OPROFILE=y
# CONFIG_KPROBES is not set
# CONFIG_JUMP_LABEL is not set
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_USER_RETURN_NOTIFIER=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_OPTPROBES=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_ATTRS=y
CONFIG_USE_GENERIC_SMP_HELPERS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y
CONFIG_HAVE_USER_RETURN_NOTIFIER=y
CONFIG_HAVE_PERF_EVENTS_NMI=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y

#
# GCOV-based kernel profiling
#
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_STOP_MACHINE=y
CONFIG_BLOCK=y
CONFIG_BLK_DEV_BSG=y
# CONFIG_BLK_DEV_INTEGRITY is not set
CONFIG_BLOCK_COMPAT=y

#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_DEFAULT_NOOP=y
CONFIG_DEFAULT_IOSCHED="noop"
CONFIG_PREEMPT_NOTIFIERS=y
# CONFIG_INLINE_SPIN_TRYLOCK is not set
# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK is not set
# CONFIG_INLINE_SPIN_LOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
# CONFIG_INLINE_SPIN_UNLOCK is not set
# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_READ_TRYLOCK is not set
# CONFIG_INLINE_READ_LOCK is not set
# CONFIG_INLINE_READ_LOCK_BH is not set
# CONFIG_INLINE_READ_LOCK_IRQ is not set
# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
# CONFIG_INLINE_READ_UNLOCK is not set
# CONFIG_INLINE_READ_UNLOCK_BH is not set
# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_WRITE_TRYLOCK is not set
# CONFIG_INLINE_WRITE_LOCK is not set
# CONFIG_INLINE_WRITE_LOCK_BH is not set
# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
# CONFIG_INLINE_WRITE_UNLOCK is not set
# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_FREEZER=y

#
# Processor type and features
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_SMP=y
# CONFIG_X86_MPPARSE is not set
# CONFIG_X86_EXTENDED_PLATFORM is not set
CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y
CONFIG_SCHED_OMIT_FRAME_POINTER=y
CONFIG_PARAVIRT_GUEST=y
# CONFIG_XEN is not set
# CONFIG_XEN_PRIVILEGED_GUEST is not set
CONFIG_KVM_CLOCK=y
CONFIG_KVM_GUEST=y
CONFIG_PARAVIRT=y
# CONFIG_PARAVIRT_SPINLOCKS is not set
CONFIG_PARAVIRT_CLOCK=y
CONFIG_NO_BOOTMEM=y
# CONFIG_MEMTEST is not set
# CONFIG_MK8 is not set
# CONFIG_MPSC is not set
CONFIG_MCORE2=y
# CONFIG_MATOM is not set
# CONFIG_GENERIC_CPU is not set
CONFIG_X86_CPU=y
CONFIG_X86_INTERNODE_CACHE_SHIFT=7
CONFIG_X86_CMPXCHG=y
CONFIG_CMPXCHG_LOCAL=y
CONFIG_X86_L1_CACHE_SHIFT=6
CONFIG_X86_XADD=y
CONFIG_X86_WP_WORKS_OK=y
CONFIG_X86_INTEL_USERCOPY=y
CONFIG_X86_USE_PPRO_CHECKSUM=y
CONFIG_X86_P6_NOP=y
CONFIG_X86_TSC=y
CONFIG_X86_CMPXCHG64=y
CONFIG_X86_CMOV=y
CONFIG_X86_MINIMUM_CPU_FAMILY=64
CONFIG_X86_DEBUGCTLMSR=y
CONFIG_CPU_SUP_INTEL=y
CONFIG_CPU_SUP_AMD=y
CONFIG_CPU_SUP_CENTAUR=y
CONFIG_HPET_TIMER=y
CONFIG_HPET_EMULATE_RTC=y
CONFIG_DMI=y
CONFIG_GART_IOMMU=y
# CONFIG_CALGARY_IOMMU is not set
# CONFIG_AMD_IOMMU is not set
CONFIG_SWIOTLB=y
CONFIG_IOMMU_HELPER=y
# CONFIG_IOMMU_API is not set
CONFIG_NR_CPUS=16
CONFIG_SCHED_SMT=y
CONFIG_SCHED_MC=y
# CONFIG_IRQ_TIME_ACCOUNTING is not set
# CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
CONFIG_X86_LOCAL_APIC=y
CONFIG_X86_IO_APIC=y
# CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS is not set
CONFIG_X86_MCE=y
CONFIG_X86_MCE_INTEL=y
# CONFIG_X86_MCE_AMD is not set
CONFIG_X86_MCE_THRESHOLD=y
# CONFIG_X86_MCE_INJECT is not set
CONFIG_X86_THERMAL_VECTOR=y
# CONFIG_I8K is not set
CONFIG_MICROCODE=m
CONFIG_MICROCODE_INTEL=y
# CONFIG_MICROCODE_AMD is not set
CONFIG_MICROCODE_OLD_INTERFACE=y
CONFIG_X86_MSR=y
CONFIG_X86_CPUID=y
CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_DIRECT_GBPAGES=y
CONFIG_NUMA=y
CONFIG_AMD_NUMA=y
CONFIG_X86_64_ACPI_NUMA=y
CONFIG_NODES_SPAN_OTHER_NODES=y
# CONFIG_NUMA_EMU is not set
CONFIG_NODES_SHIFT=6
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_SPARSEMEM_MANUAL=y
CONFIG_SPARSEMEM=y
CONFIG_NEED_MULTIPLE_NODES=y
CONFIG_HAVE_MEMORY_PRESENT=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSEMEM_ALLOC_MEM_MAP_TOGETHER=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_HAVE_MEMBLOCK=y
# CONFIG_MEMORY_HOTPLUG is not set
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_COMPACTION=y
CONFIG_MIGRATION=y
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_ZONE_DMA_FLAG=1
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
CONFIG_MMU_NOTIFIER=y
CONFIG_KSM=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
# CONFIG_MEMORY_FAILURE is not set
CONFIG_TRANSPARENT_HUGEPAGE=y
CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
# CONFIG_X86_CHECK_BIOS_CORRUPTION is not set
CONFIG_X86_RESERVE_LOW=64
CONFIG_MTRR=y
CONFIG_MTRR_SANITIZER=y
CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=1
CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1
CONFIG_X86_PAT=y
CONFIG_ARCH_USES_PG_UNCACHED=y
# CONFIG_EFI is not set
CONFIG_SECCOMP=y
# CONFIG_CC_STACKPROTECTOR is not set
CONFIG_HZ_100=y
# CONFIG_HZ_250 is not set
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=100
CONFIG_SCHED_HRTICK=y
# CONFIG_KEXEC is not set
# CONFIG_CRASH_DUMP is not set
CONFIG_PHYSICAL_START=0x1000000
# CONFIG_RELOCATABLE is not set
CONFIG_PHYSICAL_ALIGN=0x1000000
CONFIG_HOTPLUG_CPU=y
CONFIG_COMPAT_VDSO=y
# CONFIG_CMDLINE_BOOL is not set
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID=y
CONFIG_USE_PERCPU_NUMA_NODE_ID=y

#
# Power management and ACPI options
#
CONFIG_ARCH_HIBERNATION_HEADER=y
CONFIG_PM=y
# CONFIG_PM_DEBUG is not set
CONFIG_PM_SLEEP_SMP=y
CONFIG_PM_SLEEP=y
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
CONFIG_HIBERNATION=y
CONFIG_PM_STD_PARTITION="/dev/sda3"
CONFIG_PM_RUNTIME=y
CONFIG_PM_OPS=y
CONFIG_ACPI=y
CONFIG_ACPI_SLEEP=y
# CONFIG_ACPI_PROCFS is not set
CONFIG_ACPI_PROCFS_POWER=y
CONFIG_ACPI_POWER_METER=y
# CONFIG_ACPI_EC_DEBUGFS is not set
CONFIG_ACPI_PROC_EVENT=y
CONFIG_ACPI_AC=y
CONFIG_ACPI_BATTERY=y
CONFIG_ACPI_BUTTON=y
CONFIG_ACPI_VIDEO=y
CONFIG_ACPI_FAN=y
CONFIG_ACPI_DOCK=y
CONFIG_ACPI_PROCESSOR=y
CONFIG_ACPI_IPMI=m
CONFIG_ACPI_HOTPLUG_CPU=y
CONFIG_ACPI_PROCESSOR_AGGREGATOR=y
CONFIG_ACPI_THERMAL=y
CONFIG_ACPI_NUMA=y
# CONFIG_ACPI_CUSTOM_DSDT is not set
CONFIG_ACPI_BLACKLIST_YEAR=0
# CONFIG_ACPI_DEBUG is not set
CONFIG_ACPI_PCI_SLOT=y
CONFIG_X86_PM_TIMER=y
CONFIG_ACPI_CONTAINER=y
CONFIG_ACPI_SBS=y
CONFIG_ACPI_HED=y
CONFIG_ACPI_APEI=y
CONFIG_ACPI_APEI_GHES=y
# CONFIG_ACPI_APEI_ERST_DEBUG is not set
# CONFIG_SFI is not set

#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_TABLE=y
# CONFIG_CPU_FREQ_DEBUG is not set
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_STAT_DETAILS=y
CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set

#
# CPUFreq processor drivers
#
# CONFIG_X86_PCC_CPUFREQ is not set
CONFIG_X86_ACPI_CPUFREQ=y
# CONFIG_X86_POWERNOW_K8 is not set
# CONFIG_X86_SPEEDSTEP_CENTRINO is not set
# CONFIG_X86_P4_CLOCKMOD is not set

#
# shared options
#
# CONFIG_X86_SPEEDSTEP_LIB is not set
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
# CONFIG_INTEL_IDLE is not set

#
# Memory power savings
#
# CONFIG_I7300_IDLE is not set

#
# Bus options (PCI etc.)
#
CONFIG_PCI=y
CONFIG_PCI_DIRECT=y
# CONFIG_PCI_MMCONFIG is not set
CONFIG_PCI_DOMAINS=y
# CONFIG_PCI_CNB20LE_QUIRK is not set
# CONFIG_DMAR is not set
# CONFIG_INTR_REMAP is not set
CONFIG_PCIEPORTBUS=y
CONFIG_HOTPLUG_PCI_PCIE=y
CONFIG_PCIEAER=y
CONFIG_PCIE_ECRC=y
# CONFIG_PCIEAER_INJECT is not set
CONFIG_PCIEASPM=y
# CONFIG_PCIEASPM_DEBUG is not set
CONFIG_PCIE_PME=y
CONFIG_ARCH_SUPPORTS_MSI=y
CONFIG_PCI_MSI=y
# CONFIG_PCI_STUB is not set
CONFIG_HT_IRQ=y
# CONFIG_PCI_IOV is not set
CONFIG_PCI_IOAPIC=y
CONFIG_ISA_DMA_API=y
CONFIG_AMD_NB=y
# CONFIG_PCCARD is not set
CONFIG_HOTPLUG_PCI=y
# CONFIG_HOTPLUG_PCI_FAKE is not set
CONFIG_HOTPLUG_PCI_ACPI=y
# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
# CONFIG_HOTPLUG_PCI_CPCI is not set
# CONFIG_HOTPLUG_PCI_SHPC is not set

#
# Executable file formats / Emulations
#
CONFIG_BINFMT_ELF=y
CONFIG_COMPAT_BINFMT_ELF=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
# CONFIG_HAVE_AOUT is not set
CONFIG_BINFMT_MISC=y
CONFIG_IA32_EMULATION=y
# CONFIG_IA32_AOUT is not set
CONFIG_COMPAT=y
CONFIG_COMPAT_FOR_U64_ALIGNMENT=y
CONFIG_SYSVIPC_COMPAT=y
CONFIG_HAVE_TEXT_POKE_SMP=y
CONFIG_NET=y
CONFIG_COMPAT_NETLINK_MESSAGES=y

#
# Networking options
#
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM=y
CONFIG_XFRM_USER=m
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_XFRM_STATISTICS is not set
CONFIG_XFRM_IPCOMP=m
CONFIG_NET_KEY=m
# CONFIG_NET_KEY_MIGRATE is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_ASK_IP_FIB_HASH=y
# CONFIG_IP_FIB_TRIE is not set
CONFIG_IP_FIB_HASH=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
# CONFIG_IP_ROUTE_VERBOSE is not set
# CONFIG_IP_PNP is not set
CONFIG_NET_IPIP=m
# CONFIG_NET_IPGRE_DEMUX is not set
# CONFIG_ARPD is not set
CONFIG_SYN_COOKIES=y
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
CONFIG_INET_IPCOMP=m
CONFIG_INET_XFRM_TUNNEL=m
CONFIG_INET_TUNNEL=m
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
CONFIG_INET_LRO=y
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
CONFIG_TCP_CONG_ADVANCED=y
CONFIG_TCP_CONG_BIC=y
CONFIG_TCP_CONG_CUBIC=y
# CONFIG_TCP_CONG_WESTWOOD is not set
# CONFIG_TCP_CONG_HTCP is not set
CONFIG_TCP_CONG_HSTCP=y
# CONFIG_TCP_CONG_HYBLA is not set
# CONFIG_TCP_CONG_VEGAS is not set
# CONFIG_TCP_CONG_SCALABLE is not set
# CONFIG_TCP_CONG_LP is not set
# CONFIG_TCP_CONG_VENO is not set
# CONFIG_TCP_CONG_YEAH is not set
# CONFIG_TCP_CONG_ILLINOIS is not set
# CONFIG_DEFAULT_BIC is not set
CONFIG_DEFAULT_CUBIC=y
# CONFIG_DEFAULT_RENO is not set
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IPV6 is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_DEBUG is not set
CONFIG_NETFILTER_ADVANCED=y
CONFIG_BRIDGE_NETFILTER=y

#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_NETLINK=y
# CONFIG_NETFILTER_NETLINK_QUEUE is not set
CONFIG_NETFILTER_NETLINK_LOG=y
CONFIG_NF_CONNTRACK=y
CONFIG_NF_CONNTRACK_MARK=y
CONFIG_NF_CONNTRACK_EVENTS=y
# CONFIG_NF_CT_PROTO_DCCP is not set
CONFIG_NF_CT_PROTO_SCTP=y
# CONFIG_NF_CT_PROTO_UDPLITE is not set
# CONFIG_NF_CONNTRACK_AMANDA is not set
CONFIG_NF_CONNTRACK_FTP=y
# CONFIG_NF_CONNTRACK_H323 is not set
# CONFIG_NF_CONNTRACK_IRC is not set
# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
# CONFIG_NF_CONNTRACK_PPTP is not set
# CONFIG_NF_CONNTRACK_SANE is not set
CONFIG_NF_CONNTRACK_SIP=m
CONFIG_NF_CONNTRACK_TFTP=y
CONFIG_NF_CT_NETLINK=y
# CONFIG_NETFILTER_TPROXY is not set
CONFIG_NETFILTER_XTABLES=y

#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=y
CONFIG_NETFILTER_XT_CONNMARK=y

#
# Xtables targets
#
# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
# CONFIG_NETFILTER_XT_TARGET_CT is not set
# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
# CONFIG_NETFILTER_XT_TARGET_HL is not set
# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
# CONFIG_NETFILTER_XT_TARGET_LED is not set
CONFIG_NETFILTER_XT_TARGET_MARK=y
CONFIG_NETFILTER_XT_TARGET_NFLOG=y
# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
# CONFIG_NETFILTER_XT_TARGET_TEE is not set
# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set

#
# Xtables matches
#
# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set
# CONFIG_NETFILTER_XT_MATCH_CPU is not set
# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
# CONFIG_NETFILTER_XT_MATCH_ESP is not set
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
# CONFIG_NETFILTER_XT_MATCH_HL is not set
# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
CONFIG_NETFILTER_XT_MATCH_MAC=y
CONFIG_NETFILTER_XT_MATCH_MARK=y
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
# CONFIG_NETFILTER_XT_MATCH_OSF is not set
# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
CONFIG_NETFILTER_XT_MATCH_POLICY=y
# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
# CONFIG_NETFILTER_XT_MATCH_REALM is not set
# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
CONFIG_NETFILTER_XT_MATCH_SCTP=y
CONFIG_NETFILTER_XT_MATCH_STATE=y
# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
# CONFIG_NETFILTER_XT_MATCH_STRING is not set
CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
# CONFIG_NETFILTER_XT_MATCH_TIME is not set
# CONFIG_NETFILTER_XT_MATCH_U32 is not set
# CONFIG_IP_VS is not set

#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=y
CONFIG_NF_CONNTRACK_IPV4=y
CONFIG_NF_CONNTRACK_PROC_COMPAT=y
CONFIG_IP_NF_QUEUE=y
CONFIG_IP_NF_IPTABLES=y
# CONFIG_IP_NF_MATCH_ADDRTYPE is not set
# CONFIG_IP_NF_MATCH_AH is not set
# CONFIG_IP_NF_MATCH_ECN is not set
# CONFIG_IP_NF_MATCH_TTL is not set
CONFIG_IP_NF_FILTER=y
CONFIG_IP_NF_TARGET_REJECT=y
CONFIG_IP_NF_TARGET_LOG=y
# CONFIG_IP_NF_TARGET_ULOG is not set
CONFIG_NF_NAT=y
CONFIG_NF_NAT_NEEDED=y
CONFIG_IP_NF_TARGET_MASQUERADE=y
CONFIG_IP_NF_TARGET_NETMAP=y
CONFIG_IP_NF_TARGET_REDIRECT=y
# CONFIG_NF_NAT_SNMP_BASIC is not set
CONFIG_NF_NAT_PROTO_SCTP=y
CONFIG_NF_NAT_FTP=y
# CONFIG_NF_NAT_IRC is not set
CONFIG_NF_NAT_TFTP=y
# CONFIG_NF_NAT_AMANDA is not set
# CONFIG_NF_NAT_PPTP is not set
# CONFIG_NF_NAT_H323 is not set
CONFIG_NF_NAT_SIP=m
CONFIG_IP_NF_MANGLE=y
# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
# CONFIG_IP_NF_TARGET_ECN is not set
# CONFIG_IP_NF_TARGET_TTL is not set
CONFIG_IP_NF_RAW=y
CONFIG_IP_NF_ARPTABLES=y
CONFIG_IP_NF_ARPFILTER=y
CONFIG_IP_NF_ARP_MANGLE=y
# CONFIG_BRIDGE_NF_EBTABLES is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_RDS is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_L2TP is not set
CONFIG_STP=m
CONFIG_BRIDGE=m
CONFIG_BRIDGE_IGMP_SNOOPING=y
# CONFIG_NET_DSA is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
CONFIG_LLC=m
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_PHONET is not set
# CONFIG_IEEE802154 is not set
# CONFIG_NET_SCHED is not set
# CONFIG_DCB is not set
# CONFIG_BATMAN_ADV is not set
CONFIG_RPS=y
CONFIG_XPS=y

#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
# CONFIG_IRDA is not set
CONFIG_BT=m
CONFIG_BT_L2CAP=m
CONFIG_BT_SCO=m
CONFIG_BT_RFCOMM=m
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
# CONFIG_BT_CMTP is not set
CONFIG_BT_HIDP=m

#
# Bluetooth device drivers
#
CONFIG_BT_HCIBTUSB=m
# CONFIG_BT_HCIBTSDIO is not set
# CONFIG_BT_HCIUART is not set
# CONFIG_BT_HCIBCM203X is not set
# CONFIG_BT_HCIBPA10X is not set
# CONFIG_BT_HCIBFUSB is not set
# CONFIG_BT_HCIVHCI is not set
# CONFIG_BT_MRVL is not set
# CONFIG_BT_ATH3K is not set
# CONFIG_AF_RXRPC is not set
CONFIG_FIB_RULES=y
CONFIG_WIRELESS=y
CONFIG_WEXT_CORE=y
CONFIG_WEXT_PROC=y
CONFIG_CFG80211=m
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
# CONFIG_CFG80211_REG_DEBUG is not set
# CONFIG_CFG80211_DEFAULT_PS is not set
# CONFIG_CFG80211_INTERNAL_REGDB is not set
CONFIG_CFG80211_WEXT=y
# CONFIG_WIRELESS_EXT_SYSFS is not set
CONFIG_LIB80211=y
# CONFIG_LIB80211_DEBUG is not set
CONFIG_MAC80211=m
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_RC_MINSTREL_HT=y
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
# CONFIG_MAC80211_MESH is not set
CONFIG_MAC80211_LEDS=y
# CONFIG_MAC80211_DEBUG_MENU is not set
# CONFIG_WIMAX is not set
CONFIG_RFKILL=y
CONFIG_RFKILL_LEDS=y
CONFIG_RFKILL_INPUT=y
# CONFIG_NET_9P is not set
# CONFIG_CAIF is not set
# CONFIG_CEPH_LIB is not set

#
# Device Drivers
#

#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_DEVTMPFS is not set
CONFIG_STANDALONE=y
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_FW_LOADER=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_CONNECTOR is not set
# CONFIG_MTD is not set
# CONFIG_PARPORT is not set
CONFIG_PNP=y
# CONFIG_PNP_DEBUG_MESSAGES is not set

#
# Protocols
#
CONFIG_PNPACPI=y
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_CRYPTOLOOP=y

#
# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
#
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_SX8 is not set
# CONFIG_BLK_DEV_UB is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=23000
# CONFIG_BLK_DEV_XIP is not set
CONFIG_CDROM_PKTCDVD=m
CONFIG_CDROM_PKTCDVD_BUFFERS=8
# CONFIG_CDROM_PKTCDVD_WCACHE is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_VIRTIO_BLK=y
# CONFIG_BLK_DEV_HD is not set
# CONFIG_BLK_DEV_RBD is not set
# CONFIG_MISC_DEVICES is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
CONFIG_RAID_ATTRS=y
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
CONFIG_SCSI_PROC_FS=y

#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
CONFIG_BLK_DEV_SR=m
# CONFIG_BLK_DEV_SR_VENDOR is not set
CONFIG_CHR_DEV_SG=y
# CONFIG_CHR_DEV_SCH is not set
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set
CONFIG_SCSI_WAIT_SCAN=m

#
# SCSI Transports
#
CONFIG_SCSI_SPI_ATTRS=y
# CONFIG_SCSI_FC_ATTRS is not set
CONFIG_SCSI_ISCSI_ATTRS=m
CONFIG_SCSI_SAS_ATTRS=y
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
CONFIG_SCSI_LOWLEVEL=y
CONFIG_ISCSI_TCP=m
# CONFIG_ISCSI_BOOT_SYSFS is not set
# CONFIG_SCSI_CXGB3_ISCSI is not set
# CONFIG_SCSI_CXGB4_ISCSI is not set
# CONFIG_SCSI_BNX2_ISCSI is not set
# CONFIG_BE2ISCSI is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_HPSA is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC7XXX_OLD is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_MVSAS is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_ARCMSR is not set
CONFIG_MEGARAID_NEWGEN=y
CONFIG_MEGARAID_MM=y
CONFIG_MEGARAID_MAILBOX=y
# CONFIG_MEGARAID_LEGACY is not set
CONFIG_MEGARAID_SAS=y
CONFIG_SCSI_MPT2SAS=y
CONFIG_SCSI_MPT2SAS_MAX_SGE=128
# CONFIG_SCSI_MPT2SAS_LOGGING is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_VMWARE_PVSCSI is not set
# CONFIG_LIBFC is not set
# CONFIG_LIBFCOE is not set
# CONFIG_FCOE is not set
# CONFIG_FCOE_FNIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_EATA is not set
# CONFIG_SCSI_FUTURE_DOMAIN is not set
# CONFIG_SCSI_GDTH is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_STEX is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_QLA_FC is not set
# CONFIG_SCSI_QLA_ISCSI is not set
# CONFIG_SCSI_LPFC is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_DC390T is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_PMCRAID is not set
# CONFIG_SCSI_PM8001 is not set
# CONFIG_SCSI_SRP is not set
# CONFIG_SCSI_BFA_FC is not set
# CONFIG_SCSI_DH is not set
# CONFIG_SCSI_OSD_INITIATOR is not set
CONFIG_ATA=y
# CONFIG_ATA_NONSTANDARD is not set
# CONFIG_ATA_VERBOSE_ERROR is not set
CONFIG_ATA_ACPI=y
# CONFIG_SATA_PMP is not set

#
# Controllers with non-SFF native interface
#
CONFIG_SATA_AHCI=y
# CONFIG_SATA_AHCI_PLATFORM is not set
# CONFIG_SATA_INIC162X is not set
# CONFIG_SATA_ACARD_AHCI is not set
CONFIG_SATA_SIL24=y
CONFIG_ATA_SFF=y

#
# SFF controllers with custom DMA interface
#
# CONFIG_PDC_ADMA is not set
# CONFIG_SATA_QSTOR is not set
# CONFIG_SATA_SX4 is not set
CONFIG_ATA_BMDMA=y

#
# SATA SFF controllers with BMDMA
#
CONFIG_ATA_PIIX=y
# CONFIG_SATA_MV is not set
# CONFIG_SATA_NV is not set
# CONFIG_SATA_PROMISE is not set
# CONFIG_SATA_SIL is not set
# CONFIG_SATA_SIS is not set
# CONFIG_SATA_SVW is not set
# CONFIG_SATA_ULI is not set
# CONFIG_SATA_VIA is not set
# CONFIG_SATA_VITESSE is not set

#
# PATA SFF controllers with BMDMA
#
# CONFIG_PATA_ALI is not set
# CONFIG_PATA_AMD is not set
# CONFIG_PATA_ARTOP is not set
# CONFIG_PATA_ATIIXP is not set
# CONFIG_PATA_ATP867X is not set
# CONFIG_PATA_CMD64X is not set
# CONFIG_PATA_CS5520 is not set
# CONFIG_PATA_CS5530 is not set
# CONFIG_PATA_CS5536 is not set
# CONFIG_PATA_CYPRESS is not set
# CONFIG_PATA_EFAR is not set
# CONFIG_PATA_HPT366 is not set
# CONFIG_PATA_HPT37X is not set
# CONFIG_PATA_HPT3X2N is not set
# CONFIG_PATA_HPT3X3 is not set
# CONFIG_PATA_IT8213 is not set
# CONFIG_PATA_IT821X is not set
# CONFIG_PATA_JMICRON is not set
# CONFIG_PATA_MARVELL is not set
# CONFIG_PATA_NETCELL is not set
# CONFIG_PATA_NINJA32 is not set
# CONFIG_PATA_NS87415 is not set
# CONFIG_PATA_OLDPIIX is not set
# CONFIG_PATA_OPTIDMA is not set
# CONFIG_PATA_PDC2027X is not set
# CONFIG_PATA_PDC_OLD is not set
# CONFIG_PATA_RADISYS is not set
# CONFIG_PATA_RDC is not set
# CONFIG_PATA_SC1200 is not set
# CONFIG_PATA_SCH is not set
# CONFIG_PATA_SERVERWORKS is not set
# CONFIG_PATA_SIL680 is not set
# CONFIG_PATA_SIS is not set
# CONFIG_PATA_TOSHIBA is not set
# CONFIG_PATA_TRIFLEX is not set
# CONFIG_PATA_VIA is not set
# CONFIG_PATA_WINBOND is not set

#
# PIO-only SFF controllers
#
# CONFIG_PATA_CMD640_PCI is not set
# CONFIG_PATA_MPIIX is not set
# CONFIG_PATA_NS87410 is not set
# CONFIG_PATA_OPTI is not set
# CONFIG_PATA_RZ1000 is not set

#
# Generic fallback / legacy drivers
#
# CONFIG_PATA_ACPI is not set
# CONFIG_ATA_GENERIC is not set
# CONFIG_PATA_LEGACY is not set
CONFIG_MD=y
# CONFIG_BLK_DEV_MD is not set
CONFIG_BLK_DEV_DM=y
# CONFIG_DM_DEBUG is not set
CONFIG_DM_CRYPT=y
# CONFIG_DM_SNAPSHOT is not set
# CONFIG_DM_MIRROR is not set
# CONFIG_DM_RAID is not set
# CONFIG_DM_ZERO is not set
# CONFIG_DM_MULTIPATH is not set
# CONFIG_DM_DELAY is not set
# CONFIG_DM_UEVENT is not set
# CONFIG_TARGET_CORE is not set
CONFIG_FUSION=y
CONFIG_FUSION_SPI=y
# CONFIG_FUSION_FC is not set
CONFIG_FUSION_SAS=y
CONFIG_FUSION_MAX_SGE=128
# CONFIG_FUSION_CTL is not set
# CONFIG_FUSION_LOGGING is not set

#
# IEEE 1394 (FireWire) support
#
CONFIG_FIREWIRE=m
CONFIG_FIREWIRE_OHCI=m
CONFIG_FIREWIRE_OHCI_DEBUG=y
CONFIG_FIREWIRE_SBP2=m
# CONFIG_FIREWIRE_NET is not set
# CONFIG_FIREWIRE_NOSY is not set
# CONFIG_I2O is not set
# CONFIG_MACINTOSH_DRIVERS is not set
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_BONDING=m
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
CONFIG_TUN=y
# CONFIG_VETH is not set
# CONFIG_NET_SB1000 is not set
# CONFIG_ARCNET is not set
CONFIG_MII=y
CONFIG_PHYLIB=y

#
# MII PHY device drivers
#
# CONFIG_MARVELL_PHY is not set
# CONFIG_DAVICOM_PHY is not set
# CONFIG_QSEMI_PHY is not set
# CONFIG_LXT_PHY is not set
# CONFIG_CICADA_PHY is not set
# CONFIG_VITESSE_PHY is not set
# CONFIG_SMSC_PHY is not set
# CONFIG_BROADCOM_PHY is not set
# CONFIG_BCM63XX_PHY is not set
# CONFIG_ICPLUS_PHY is not set
# CONFIG_REALTEK_PHY is not set
# CONFIG_NATIONAL_PHY is not set
# CONFIG_STE10XP is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_MICREL_PHY is not set
# CONFIG_FIXED_PHY is not set
# CONFIG_MDIO_BITBANG is not set
CONFIG_NET_ETHERNET=y
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNGEM is not set
# CONFIG_CASSINI is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_ETHOC is not set
# CONFIG_DNET is not set
# CONFIG_NET_TULIP is not set
# CONFIG_HP100 is not set
# CONFIG_IBM_NEW_EMAC_ZMII is not set
# CONFIG_IBM_NEW_EMAC_RGMII is not set
# CONFIG_IBM_NEW_EMAC_TAH is not set
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
CONFIG_NET_PCI=y
CONFIG_PCNET32=y
# CONFIG_AMD8111_ETH is not set
# CONFIG_ADAPTEC_STARFIRE is not set
# CONFIG_KSZ884X_PCI is not set
# CONFIG_B44 is not set
# CONFIG_FORCEDETH is not set
# CONFIG_E100 is not set
# CONFIG_FEALNX is not set
# CONFIG_NATSEMI is not set
# CONFIG_NE2K_PCI is not set
CONFIG_8139CP=m
# CONFIG_8139TOO is not set
# CONFIG_R6040 is not set
# CONFIG_SIS900 is not set
# CONFIG_EPIC100 is not set
# CONFIG_SMSC9420 is not set
# CONFIG_SUNDANCE is not set
# CONFIG_TLAN is not set
# CONFIG_KS8851_MLL is not set
# CONFIG_VIA_RHINE is not set
# CONFIG_SC92031 is not set
# CONFIG_ATL2 is not set
CONFIG_NETDEV_1000=y
# CONFIG_ACENIC is not set
# CONFIG_DL2K is not set
CONFIG_E1000=m
CONFIG_E1000E=m
# CONFIG_IP1000 is not set
CONFIG_IGB=y
# CONFIG_IGBVF is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_R8169 is not set
# CONFIG_SIS190 is not set
# CONFIG_SKGE is not set
# CONFIG_SKY2 is not set
# CONFIG_VIA_VELOCITY is not set
CONFIG_TIGON3=y
CONFIG_BNX2=y
# CONFIG_CNIC is not set
# CONFIG_QLA3XXX is not set
# CONFIG_ATL1 is not set
# CONFIG_ATL1E is not set
# CONFIG_ATL1C is not set
# CONFIG_JME is not set
# CONFIG_STMMAC_ETH is not set
# CONFIG_PCH_GBE is not set
CONFIG_NETDEV_10000=y
CONFIG_MDIO=y
# CONFIG_CHELSIO_T1 is not set
CONFIG_CHELSIO_T3_DEPENDS=y
# CONFIG_CHELSIO_T3 is not set
CONFIG_CHELSIO_T4_DEPENDS=y
# CONFIG_CHELSIO_T4 is not set
CONFIG_CHELSIO_T4VF_DEPENDS=y
# CONFIG_CHELSIO_T4VF is not set
# CONFIG_ENIC is not set
CONFIG_IXGBE=y
# CONFIG_IXGBEVF is not set
# CONFIG_IXGB is not set
# CONFIG_S2IO is not set
# CONFIG_VXGE is not set
# CONFIG_MYRI10GE is not set
# CONFIG_NETXEN_NIC is not set
# CONFIG_NIU is not set
# CONFIG_MLX4_EN is not set
# CONFIG_MLX4_CORE is not set
# CONFIG_TEHUTI is not set
# CONFIG_BNX2X is not set
# CONFIG_QLCNIC is not set
# CONFIG_QLGE is not set
# CONFIG_BNA is not set
# CONFIG_SFC is not set
# CONFIG_BE2NET is not set
# CONFIG_TR is not set
CONFIG_WLAN=y
# CONFIG_LIBERTAS_THINFIRM is not set
# CONFIG_AIRO is not set
# CONFIG_ATMEL is not set
# CONFIG_AT76C50X_USB is not set
# CONFIG_PRISM54 is not set
# CONFIG_USB_ZD1201 is not set
# CONFIG_USB_NET_RNDIS_WLAN is not set
# CONFIG_RTL8180 is not set
# CONFIG_RTL8187 is not set
# CONFIG_ADM8211 is not set
# CONFIG_MAC80211_HWSIM is not set
# CONFIG_MWL8K is not set
# CONFIG_ATH_COMMON is not set
# CONFIG_B43 is not set
# CONFIG_B43LEGACY is not set
# CONFIG_HOSTAP is not set
# CONFIG_IPW2100 is not set
# CONFIG_IPW2200 is not set
CONFIG_IWLWIFI=m

#
# Debugging Options
#
# CONFIG_IWLWIFI_DEBUG is not set
CONFIG_IWLAGN=m
CONFIG_IWL4965=y
CONFIG_IWL5000=y
CONFIG_IWL3945=m
# CONFIG_IWM is not set
# CONFIG_LIBERTAS is not set
# CONFIG_HERMES is not set
# CONFIG_P54_COMMON is not set
# CONFIG_RT2X00 is not set
# CONFIG_RTL8192CE is not set
# CONFIG_WL1251 is not set
# CONFIG_WL12XX_MENU is not set
# CONFIG_ZD1211RW is not set

#
# Enable WiMAX (Networking options) to see the WiMAX drivers
#

#
# USB Network Adapters
#
# CONFIG_USB_CATC is not set
# CONFIG_USB_KAWETH is not set
CONFIG_USB_PEGASUS=m
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_USBNET is not set
# CONFIG_USB_HSO is not set
# CONFIG_USB_IPHETH is not set
# CONFIG_WAN is not set

#
# CAIF transport drivers
#
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
CONFIG_PPP=y
CONFIG_PPP_MULTILINK=y
CONFIG_PPP_FILTER=y
CONFIG_PPP_ASYNC=y
# CONFIG_PPP_SYNC_TTY is not set
CONFIG_PPP_DEFLATE=y
CONFIG_PPP_BSDCOMP=y
# CONFIG_PPP_MPPE is not set
# CONFIG_PPPOE is not set
# CONFIG_SLIP is not set
CONFIG_SLHC=y
# CONFIG_NET_FC is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
CONFIG_VIRTIO_NET=y
# CONFIG_VMXNET3 is not set
CONFIG_ISDN=y
# CONFIG_ISDN_I4L is not set
CONFIG_ISDN_CAPI=m
CONFIG_ISDN_DRV_AVMB1_VERBOSE_REASON=y
CONFIG_CAPI_TRACE=y
# CONFIG_ISDN_CAPI_MIDDLEWARE is not set
CONFIG_ISDN_CAPI_CAPI20=m

#
# CAPI hardware drivers
#
# CONFIG_CAPI_AVM is not set

#
# Active Dialogic DIVA Server cards
#
CONFIG_CAPI_EICON=y
CONFIG_ISDN_DIVAS=m
CONFIG_ISDN_DIVAS_BRIPCI=y
CONFIG_ISDN_DIVAS_PRIPCI=y
CONFIG_ISDN_DIVAS_ANALOG=y
CONFIG_ISDN_DIVAS_DIVACAPI=m
CONFIG_ISDN_DIVAS_USERIDI=m
CONFIG_ISDN_DIVAS_MAINT=m
# CONFIG_ISDN_DRV_GIGASET is not set
# CONFIG_HYSDN is not set
# CONFIG_MISDN is not set
# CONFIG_PHONE is not set

#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
CONFIG_INPUT_POLLDEV=y
# CONFIG_INPUT_SPARSEKMAP is not set

#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADP5588 is not set
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_LM8323 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_LIFEBOOK=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_PS2_ELANTECH is not set
# CONFIG_MOUSE_PS2_SENTELIC is not set
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_APPLETOUCH is not set
# CONFIG_MOUSE_BCM5974 is not set
# CONFIG_MOUSE_VSXXXAA is not set
# CONFIG_MOUSE_SYNAPTICS_I2C is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_AD714X is not set
CONFIG_INPUT_PCSPKR=y
# CONFIG_INPUT_APANEL is not set
# CONFIG_INPUT_ATLAS_BTNS is not set
# CONFIG_INPUT_ATI_REMOTE is not set
# CONFIG_INPUT_ATI_REMOTE2 is not set
# CONFIG_INPUT_KEYSPAN_REMOTE is not set
# CONFIG_INPUT_POWERMATE is not set
# CONFIG_INPUT_YEALINK is not set
# CONFIG_INPUT_CM109 is not set
CONFIG_INPUT_UINPUT=y
# CONFIG_INPUT_PCF8574 is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_CMA3000 is not set

#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_I8042=y
# CONFIG_SERIO_SERPORT is not set
# CONFIG_SERIO_CT82C710 is not set
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_SERIO_PS2MULT is not set
# CONFIG_GAMEPORT is not set

#
# Character devices
#
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
# CONFIG_DEVKMEM is not set
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_N_GSM is not set
# CONFIG_NOZOMI is not set

#
# Serial drivers
#
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_CONSOLE is not set
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_SERIAL_8250_PCI=y
CONFIG_SERIAL_8250_PNP=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
# CONFIG_SERIAL_8250_EXTENDED is not set

#
# Non-8250 serial port support
#
# CONFIG_SERIAL_MFD_HSU is not set
CONFIG_SERIAL_CORE=y
# CONFIG_SERIAL_JSM is not set
# CONFIG_SERIAL_TIMBERDALE is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_VIRTIO_CONSOLE is not set
CONFIG_IPMI_HANDLER=m
CONFIG_IPMI_PANIC_EVENT=y
CONFIG_IPMI_PANIC_STRING=y
CONFIG_IPMI_DEVICE_INTERFACE=m
CONFIG_IPMI_SI=m
CONFIG_IPMI_WATCHDOG=m
CONFIG_IPMI_POWEROFF=m
# CONFIG_HW_RANDOM is not set
CONFIG_NVRAM=y
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
# CONFIG_MWAVE is not set
CONFIG_RAW_DRIVER=y
CONFIG_MAX_RAW_DEVS=256
# CONFIG_HPET is not set
# CONFIG_HANGCHECK_TIMER is not set
# CONFIG_TCG_TPM is not set
# CONFIG_TELCLOCK is not set
CONFIG_DEVPORT=y
# CONFIG_RAMOOPS is not set
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
# CONFIG_I2C_COMPAT is not set
# CONFIG_I2C_CHARDEV is not set
# CONFIG_I2C_MUX is not set
# CONFIG_I2C_HELPER_AUTO is not set
# CONFIG_I2C_SMBUS is not set

#
# I2C Algorithms
#
CONFIG_I2C_ALGOBIT=y
# CONFIG_I2C_ALGOPCF is not set
# CONFIG_I2C_ALGOPCA is not set

#
# I2C Hardware Bus support
#

#
# PC SMBus host controller drivers
#
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_ISCH is not set
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set

#
# ACPI drivers
#
# CONFIG_I2C_SCMI is not set

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_INTEL_MID is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_XILINX is not set
# CONFIG_I2C_EG20T is not set

#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_TINY_USB is not set

#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_SPI is not set

#
# PPS support
#
# CONFIG_PPS is not set

#
# PPS generators support
#
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
# CONFIG_GPIOLIB is not set
# CONFIG_W1 is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
# CONFIG_PDA_POWER is not set
# CONFIG_TEST_POWER is not set
# CONFIG_BATTERY_DS2782 is not set
# CONFIG_BATTERY_BQ20Z75 is not set
# CONFIG_BATTERY_BQ27x00 is not set
# CONFIG_BATTERY_MAX17040 is not set
# CONFIG_BATTERY_MAX17042 is not set
CONFIG_HWMON=y
# CONFIG_HWMON_VID is not set
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_ABITUGURU is not set
# CONFIG_SENSORS_ABITUGURU3 is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_ASC7621 is not set
# CONFIG_SENSORS_K8TEMP is not set
# CONFIG_SENSORS_K10TEMP is not set
# CONFIG_SENSORS_ASB100 is not set
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_DS620 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_I5K_AMB is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_FSCHMD is not set
# CONFIG_SENSORS_G760A is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
CONFIG_SENSORS_CORETEMP=y
# CONFIG_SENSORS_PKGTEMP is not set
# CONFIG_SENSORS_IBMAEM is not set
# CONFIG_SENSORS_IBMPEX is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_JC42 is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM73 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_LTC4215 is not set
# CONFIG_SENSORS_LTC4245 is not set
# CONFIG_SENSORS_LTC4261 is not set
# CONFIG_SENSORS_LM95241 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_SENSORS_SHT21 is not set
# CONFIG_SENSORS_SIS5595 is not set
# CONFIG_SENSORS_SMM665 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_VIA_CPUTEMP is not set
# CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_VT8231 is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_SENSORS_APPLESMC is not set

#
# ACPI drivers
#
# CONFIG_SENSORS_ATK0110 is not set
# CONFIG_SENSORS_LIS3LV02D is not set
CONFIG_THERMAL=y
CONFIG_THERMAL_HWMON=y
# CONFIG_WATCHDOG is not set
CONFIG_SSB_POSSIBLE=y

#
# Sonics Silicon Backplane
#
# CONFIG_SSB is not set
# CONFIG_MFD_SUPPORT is not set
# CONFIG_REGULATOR is not set
CONFIG_MEDIA_SUPPORT=y

#
# Multimedia core support
#
CONFIG_VIDEO_DEV=y
CONFIG_VIDEO_V4L2_COMMON=y
# CONFIG_DVB_CORE is not set
CONFIG_VIDEO_MEDIA=y

#
# Multimedia drivers
#
CONFIG_RC_CORE=y
CONFIG_LIRC=y
# CONFIG_RC_MAP is not set
# CONFIG_IR_NEC_DECODER is not set
# CONFIG_IR_RC5_DECODER is not set
# CONFIG_IR_RC6_DECODER is not set
# CONFIG_IR_JVC_DECODER is not set
# CONFIG_IR_SONY_DECODER is not set
CONFIG_IR_RC5_SZ_DECODER=y
CONFIG_IR_LIRC_CODEC=y
# CONFIG_IR_ENE is not set
# CONFIG_IR_IMON is not set
# CONFIG_IR_MCEUSB is not set
# CONFIG_IR_NUVOTON is not set
# CONFIG_IR_STREAMZAP is not set
# CONFIG_IR_WINBOND_CIR is not set
# CONFIG_RC_LOOPBACK is not set
# CONFIG_MEDIA_ATTACH is not set
CONFIG_MEDIA_TUNER=y
# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
CONFIG_MEDIA_TUNER_SIMPLE=y
CONFIG_MEDIA_TUNER_TDA8290=y
CONFIG_MEDIA_TUNER_TDA827X=y
CONFIG_MEDIA_TUNER_TDA18271=y
CONFIG_MEDIA_TUNER_TDA9887=y
CONFIG_MEDIA_TUNER_TEA5761=y
CONFIG_MEDIA_TUNER_TEA5767=y
CONFIG_MEDIA_TUNER_MT20XX=y
CONFIG_MEDIA_TUNER_XC2028=y
CONFIG_MEDIA_TUNER_XC5000=y
CONFIG_MEDIA_TUNER_MC44S803=y
CONFIG_VIDEO_V4L2=y
CONFIG_VIDEO_CAPTURE_DRIVERS=y
# CONFIG_VIDEO_ADV_DEBUG is not set
# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
CONFIG_VIDEO_IR_I2C=y

#
# Audio decoders
#

#
# RDS decoders
#

#
# Video decoders
#

#
# Video and audio decoders
#

#
# MPEG video encoders
#

#
# Video encoders
#

#
# Video improvement chips
#
# CONFIG_VIDEO_VIVI is not set
# CONFIG_VIDEO_BT848 is not set
# CONFIG_VIDEO_CPIA2 is not set
# CONFIG_VIDEO_ZORAN is not set
# CONFIG_VIDEO_SAA7134 is not set
# CONFIG_VIDEO_MXB is not set
# CONFIG_VIDEO_HEXIUM_ORION is not set
# CONFIG_VIDEO_HEXIUM_GEMINI is not set
# CONFIG_VIDEO_TIMBERDALE is not set
# CONFIG_VIDEO_CX88 is not set
# CONFIG_VIDEO_IVTV is not set
# CONFIG_VIDEO_CAFE_CCIC is not set
# CONFIG_VIDEO_SR030PC30 is not set
# CONFIG_SOC_CAMERA is not set
CONFIG_V4L_USB_DRIVERS=y
CONFIG_USB_VIDEO_CLASS=m
CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
# CONFIG_USB_GSPCA is not set
# CONFIG_VIDEO_PVRUSB2 is not set
# CONFIG_VIDEO_HDPVR is not set
# CONFIG_VIDEO_EM28XX is not set
# CONFIG_VIDEO_CX231XX is not set
# CONFIG_VIDEO_USBVISION is not set
# CONFIG_USB_ET61X251 is not set
# CONFIG_USB_SN9C102 is not set
# CONFIG_USB_PWC is not set
# CONFIG_USB_ZR364XX is not set
# CONFIG_USB_STKWEBCAM is not set
# CONFIG_USB_S2255 is not set
# CONFIG_V4L_MEM2MEM_DRIVERS is not set
# CONFIG_RADIO_ADAPTERS is not set

#
# Graphics support
#
CONFIG_AGP=y
# CONFIG_AGP_AMD64 is not set
CONFIG_AGP_INTEL=y
# CONFIG_AGP_SIS is not set
# CONFIG_AGP_VIA is not set
CONFIG_VGA_ARB=y
CONFIG_VGA_ARB_MAX_GPUS=16
# CONFIG_VGA_SWITCHEROO is not set
CONFIG_DRM=m
CONFIG_DRM_KMS_HELPER=m
CONFIG_DRM_TTM=m
# CONFIG_DRM_TDFX is not set
# CONFIG_DRM_R128 is not set
# CONFIG_DRM_RADEON is not set
# CONFIG_DRM_I810 is not set
# CONFIG_DRM_I830 is not set
CONFIG_DRM_I915=m
CONFIG_DRM_I915_KMS=y
# CONFIG_DRM_MGA is not set
# CONFIG_DRM_SIS is not set
# CONFIG_DRM_VIA is not set
# CONFIG_DRM_SAVAGE is not set
# CONFIG_STUB_POULSBO is not set
# CONFIG_VGASTATE is not set
CONFIG_VIDEO_OUTPUT_CONTROL=y
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
# CONFIG_FB_DDC is not set
CONFIG_FB_BOOT_VESA_SUPPORT=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
# CONFIG_FB_SYS_FILLRECT is not set
# CONFIG_FB_SYS_COPYAREA is not set
# CONFIG_FB_SYS_IMAGEBLIT is not set
# CONFIG_FB_FOREIGN_ENDIAN is not set
# CONFIG_FB_SYS_FOPS is not set
# CONFIG_FB_WMT_GE_ROPS is not set
CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FB_TILEBLITTING is not set

#
# Frame buffer hardware drivers
#
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_ARC is not set
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_VGA16 is not set
CONFIG_FB_VESA=y
# CONFIG_FB_N411 is not set
# CONFIG_FB_HGA is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_LE80578 is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_S3 is not set
# CONFIG_FB_SAVAGE is not set
# CONFIG_FB_SIS is not set
# CONFIG_FB_VIA is not set
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_VT8623 is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set
# CONFIG_FB_CARMINE is not set
# CONFIG_FB_GEODE is not set
# CONFIG_FB_UDL is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
# CONFIG_FB_BROADSHEET is not set
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_PLATFORM=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_GENERIC is not set
# CONFIG_BACKLIGHT_PROGEAR is not set
# CONFIG_BACKLIGHT_MBP_NVIDIA is not set
# CONFIG_BACKLIGHT_SAHARA is not set
# CONFIG_BACKLIGHT_ADP8860 is not set

#
# Display device support
#
CONFIG_DISPLAY_SUPPORT=y

#
# Display hardware drivers
#

#
# Console display driver support
#
CONFIG_VGA_CONSOLE=y
# CONFIG_VGACON_SOFT_SCROLLBACK is not set
CONFIG_DUMMY_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
CONFIG_FONTS=y
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
# CONFIG_FONT_6x11 is not set
CONFIG_FONT_7x14=y
# CONFIG_FONT_PEARL_8x8 is not set
# CONFIG_FONT_ACORN_8x8 is not set
# CONFIG_FONT_MINI_4x6 is not set
# CONFIG_FONT_SUN8x16 is not set
# CONFIG_FONT_SUN12x22 is not set
# CONFIG_FONT_10x18 is not set
# CONFIG_LOGO is not set
CONFIG_SOUND=y
CONFIG_SOUND_OSS_CORE=y
# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_HWDEP=m
CONFIG_SND_RAWMIDI=y
CONFIG_SND_JACK=y
CONFIG_SND_SEQUENCER=y
# CONFIG_SND_SEQ_DUMMY is not set
CONFIG_SND_OSSEMUL=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
CONFIG_SND_PCM_OSS_PLUGINS=y
CONFIG_SND_SEQUENCER_OSS=y
CONFIG_SND_HRTIMER=y
CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
# CONFIG_SND_DYNAMIC_MINORS is not set
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_VERBOSE_PROCFS is not set
CONFIG_SND_VERBOSE_PRINTK=y
# CONFIG_SND_DEBUG is not set
CONFIG_SND_VMASTER=y
CONFIG_SND_DMA_SGBUF=y
CONFIG_SND_RAWMIDI_SEQ=y
# CONFIG_SND_OPL3_LIB_SEQ is not set
# CONFIG_SND_OPL4_LIB_SEQ is not set
# CONFIG_SND_SBAWE_SEQ is not set
# CONFIG_SND_EMU10K1_SEQ is not set
CONFIG_SND_AC97_CODEC=y
# CONFIG_SND_DRIVERS is not set
CONFIG_SND_PCI=y
# CONFIG_SND_AD1889 is not set
# CONFIG_SND_ALS300 is not set
# CONFIG_SND_ALS4000 is not set
# CONFIG_SND_ALI5451 is not set
# CONFIG_SND_ASIHPI is not set
# CONFIG_SND_ATIIXP is not set
# CONFIG_SND_ATIIXP_MODEM is not set
# CONFIG_SND_AU8810 is not set
# CONFIG_SND_AU8820 is not set
# CONFIG_SND_AU8830 is not set
# CONFIG_SND_AW2 is not set
# CONFIG_SND_AZT3328 is not set
# CONFIG_SND_BT87X is not set
# CONFIG_SND_CA0106 is not set
# CONFIG_SND_CMIPCI is not set
# CONFIG_SND_OXYGEN is not set
# CONFIG_SND_CS4281 is not set
# CONFIG_SND_CS46XX is not set
# CONFIG_SND_CS5530 is not set
# CONFIG_SND_CS5535AUDIO is not set
# CONFIG_SND_CTXFI is not set
# CONFIG_SND_DARLA20 is not set
# CONFIG_SND_GINA20 is not set
# CONFIG_SND_LAYLA20 is not set
# CONFIG_SND_DARLA24 is not set
# CONFIG_SND_GINA24 is not set
# CONFIG_SND_LAYLA24 is not set
# CONFIG_SND_MONA is not set
# CONFIG_SND_MIA is not set
# CONFIG_SND_ECHO3G is not set
# CONFIG_SND_INDIGO is not set
# CONFIG_SND_INDIGOIO is not set
# CONFIG_SND_INDIGODJ is not set
# CONFIG_SND_INDIGOIOX is not set
# CONFIG_SND_INDIGODJX is not set
# CONFIG_SND_EMU10K1 is not set
# CONFIG_SND_EMU10K1X is not set
CONFIG_SND_ENS1370=y
CONFIG_SND_ENS1371=y
# CONFIG_SND_ES1938 is not set
# CONFIG_SND_ES1968 is not set
# CONFIG_SND_FM801 is not set
CONFIG_SND_HDA_INTEL=y
# CONFIG_SND_HDA_HWDEP is not set
# CONFIG_SND_HDA_INPUT_BEEP is not set
CONFIG_SND_HDA_INPUT_JACK=y
# CONFIG_SND_HDA_PATCH_LOADER is not set
# CONFIG_SND_HDA_CODEC_REALTEK is not set
CONFIG_SND_HDA_CODEC_ANALOG=y
CONFIG_SND_HDA_CODEC_SIGMATEL=y
# CONFIG_SND_HDA_CODEC_VIA is not set
# CONFIG_SND_HDA_CODEC_HDMI is not set
# CONFIG_SND_HDA_CODEC_CIRRUS is not set
CONFIG_SND_HDA_CODEC_CONEXANT=y
# CONFIG_SND_HDA_CODEC_CA0110 is not set
# CONFIG_SND_HDA_CODEC_CMEDIA is not set
# CONFIG_SND_HDA_CODEC_SI3054 is not set
# CONFIG_SND_HDA_GENERIC is not set
# CONFIG_SND_HDA_POWER_SAVE is not set
# CONFIG_SND_HDSP is not set
# CONFIG_SND_HDSPM is not set
# CONFIG_SND_ICE1712 is not set
# CONFIG_SND_ICE1724 is not set
# CONFIG_SND_INTEL8X0 is not set
# CONFIG_SND_INTEL8X0M is not set
# CONFIG_SND_KORG1212 is not set
# CONFIG_SND_LX6464ES is not set
# CONFIG_SND_MAESTRO3 is not set
# CONFIG_SND_MIXART is not set
# CONFIG_SND_NM256 is not set
# CONFIG_SND_PCXHR is not set
# CONFIG_SND_RIPTIDE is not set
# CONFIG_SND_RME32 is not set
# CONFIG_SND_RME96 is not set
# CONFIG_SND_RME9652 is not set
# CONFIG_SND_SONICVIBES is not set
# CONFIG_SND_TRIDENT is not set
# CONFIG_SND_VIA82XX is not set
# CONFIG_SND_VIA82XX_MODEM is not set
# CONFIG_SND_VIRTUOSO is not set
# CONFIG_SND_VX222 is not set
# CONFIG_SND_YMFPCI is not set
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=m
# CONFIG_SND_USB_UA101 is not set
# CONFIG_SND_USB_USX2Y is not set
# CONFIG_SND_USB_CAIAQ is not set
# CONFIG_SND_USB_US122L is not set
# CONFIG_SND_SOC is not set
# CONFIG_SOUND_PRIME is not set
CONFIG_AC97_BUS=y
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
# CONFIG_HIDRAW is not set

#
# USB Input Devices
#
CONFIG_USB_HID=m
# CONFIG_HID_PID is not set
CONFIG_USB_HIDDEV=y

#
# Special HID drivers
#
# CONFIG_HID_3M_PCT is not set
CONFIG_HID_A4TECH=m
# CONFIG_HID_ACRUX_FF is not set
CONFIG_HID_APPLE=m
CONFIG_HID_BELKIN=m
# CONFIG_HID_CANDO is not set
CONFIG_HID_CHERRY=m
CONFIG_HID_CHICONY=m
# CONFIG_HID_PRODIKEYS is not set
CONFIG_HID_CYPRESS=m
# CONFIG_HID_DRAGONRISE is not set
# CONFIG_HID_EMS_FF is not set
# CONFIG_HID_EGALAX is not set
# CONFIG_HID_ELECOM is not set
CONFIG_HID_EZKEY=m
CONFIG_HID_KYE=m
# CONFIG_HID_UCLOGIC is not set
# CONFIG_HID_WALTOP is not set
# CONFIG_HID_GYRATION is not set
# CONFIG_HID_TWINHAN is not set
CONFIG_HID_KENSINGTON=m
CONFIG_HID_LOGITECH=m
# CONFIG_LOGITECH_FF is not set
# CONFIG_LOGIRUMBLEPAD2_FF is not set
# CONFIG_LOGIG940_FF is not set
# CONFIG_LOGIWII_FF is not set
# CONFIG_HID_MAGICMOUSE is not set
CONFIG_HID_MICROSOFT=m
# CONFIG_HID_MOSART is not set
CONFIG_HID_MONTEREY=m
# CONFIG_HID_MULTITOUCH is not set
# CONFIG_HID_NTRIG is not set
# CONFIG_HID_ORTEK is not set
# CONFIG_HID_PANTHERLORD is not set
# CONFIG_HID_PETALYNX is not set
# CONFIG_HID_PICOLCD is not set
# CONFIG_HID_QUANTA is not set
# CONFIG_HID_ROCCAT is not set
# CONFIG_HID_ROCCAT_KONE is not set
# CONFIG_HID_ROCCAT_KONEPLUS is not set
# CONFIG_HID_ROCCAT_PYRA is not set
# CONFIG_HID_SAMSUNG is not set
# CONFIG_HID_SONY is not set
# CONFIG_HID_STANTUM is not set
# CONFIG_HID_SUNPLUS is not set
# CONFIG_HID_GREENASIA is not set
# CONFIG_HID_SMARTJOYPLUS is not set
# CONFIG_HID_TOPSEED is not set
# CONFIG_HID_THRUSTMASTER is not set
# CONFIG_HID_WACOM is not set
# CONFIG_HID_ZEROPLUS is not set
# CONFIG_HID_ZYDACRON is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
CONFIG_USB_ARCH_HAS_EHCI=y
CONFIG_USB=y
# CONFIG_USB_DEBUG is not set
# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set

#
# Miscellaneous USB options
#
CONFIG_USB_DEVICEFS=y
CONFIG_USB_DEVICE_CLASS=y
CONFIG_USB_DYNAMIC_MINORS=y
CONFIG_USB_SUSPEND=y
# CONFIG_USB_OTG is not set
# CONFIG_USB_MON is not set
# CONFIG_USB_WUSB is not set
# CONFIG_USB_WUSB_CBAF is not set

#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
CONFIG_USB_XHCI_HCD=y
# CONFIG_USB_XHCI_HCD_DEBUGGING is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_TT_NEWSCHED=y
# CONFIG_USB_OXU210HP_HCD is not set
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_ISP1760_HCD is not set
# CONFIG_USB_ISP1362_HCD is not set
CONFIG_USB_OHCI_HCD=y
# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_UHCI_HCD=y
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_WHCI_HCD is not set
# CONFIG_USB_HWA_HCD is not set

#
# USB Device Class drivers
#
CONFIG_USB_ACM=m
# CONFIG_USB_PRINTER is not set
# CONFIG_USB_WDM is not set
# CONFIG_USB_TMC is not set

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=m
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_ISD200 is not set
# CONFIG_USB_STORAGE_USBAT is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_STORAGE_SDDR55 is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_ALAUDA is not set
# CONFIG_USB_STORAGE_ONETOUCH is not set
# CONFIG_USB_STORAGE_KARMA is not set
# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
# CONFIG_USB_UAS is not set
# CONFIG_USB_LIBUSUAL is not set

#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set

#
# USB port drivers
#
CONFIG_USB_SERIAL=m
# CONFIG_USB_EZUSB is not set
# CONFIG_USB_SERIAL_GENERIC is not set
# CONFIG_USB_SERIAL_AIRCABLE is not set
# CONFIG_USB_SERIAL_ARK3116 is not set
# CONFIG_USB_SERIAL_BELKIN is not set
# CONFIG_USB_SERIAL_CH341 is not set
# CONFIG_USB_SERIAL_WHITEHEAT is not set
# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
# CONFIG_USB_SERIAL_CP210X is not set
# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
# CONFIG_USB_SERIAL_EMPEG is not set
# CONFIG_USB_SERIAL_FTDI_SIO is not set
# CONFIG_USB_SERIAL_FUNSOFT is not set
# CONFIG_USB_SERIAL_VISOR is not set
# CONFIG_USB_SERIAL_IPAQ is not set
# CONFIG_USB_SERIAL_IR is not set
# CONFIG_USB_SERIAL_EDGEPORT is not set
# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
# CONFIG_USB_SERIAL_GARMIN is not set
# CONFIG_USB_SERIAL_IPW is not set
# CONFIG_USB_SERIAL_IUU is not set
# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
# CONFIG_USB_SERIAL_KEYSPAN is not set
# CONFIG_USB_SERIAL_KLSI is not set
# CONFIG_USB_SERIAL_KOBIL_SCT is not set
# CONFIG_USB_SERIAL_MCT_U232 is not set
# CONFIG_USB_SERIAL_MOS7720 is not set
# CONFIG_USB_SERIAL_MOS7840 is not set
# CONFIG_USB_SERIAL_MOTOROLA is not set
# CONFIG_USB_SERIAL_NAVMAN is not set
# CONFIG_USB_SERIAL_PL2303 is not set
# CONFIG_USB_SERIAL_OTI6858 is not set
# CONFIG_USB_SERIAL_QCAUX is not set
# CONFIG_USB_SERIAL_QUALCOMM is not set
# CONFIG_USB_SERIAL_SPCP8X5 is not set
# CONFIG_USB_SERIAL_HP4X is not set
# CONFIG_USB_SERIAL_SAFE is not set
# CONFIG_USB_SERIAL_SAMBA is not set
# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
CONFIG_USB_SERIAL_SIERRAWIRELESS=m
# CONFIG_USB_SERIAL_SYMBOL is not set
# CONFIG_USB_SERIAL_TI is not set
# CONFIG_USB_SERIAL_CYBERJACK is not set
# CONFIG_USB_SERIAL_XIRCOM is not set
CONFIG_USB_SERIAL_WWAN=m
CONFIG_USB_SERIAL_OPTION=m
# CONFIG_USB_SERIAL_OMNINET is not set
# CONFIG_USB_SERIAL_OPTICON is not set
# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
# CONFIG_USB_SERIAL_ZIO is not set
# CONFIG_USB_SERIAL_SSU100 is not set
# CONFIG_USB_SERIAL_DEBUG is not set

#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_SEVSEG is not set
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_LED is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_FTDI_ELAN is not set
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_SISUSBVGA is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_YUREX is not set
# CONFIG_USB_GADGET is not set

#
# OTG and related infrastructure
#
# CONFIG_NOP_USB_XCEIV is not set
# CONFIG_UWB is not set
CONFIG_MMC=m
# CONFIG_MMC_DEBUG is not set
# CONFIG_MMC_UNSAFE_RESUME is not set
# CONFIG_MMC_CLKGATE is not set

#
# MMC/SD/SDIO Card Drivers
#
CONFIG_MMC_BLOCK=m
CONFIG_MMC_BLOCK_MINORS=8
CONFIG_MMC_BLOCK_BOUNCE=y
# CONFIG_SDIO_UART is not set
# CONFIG_MMC_TEST is not set

#
# MMC/SD/SDIO Host Controller Drivers
#
CONFIG_MMC_SDHCI=m
CONFIG_MMC_SDHCI_PCI=m
CONFIG_MMC_RICOH_MMC=y
CONFIG_MMC_SDHCI_PLTFM=m
# CONFIG_MMC_WBSD is not set
# CONFIG_MMC_TIFM_SD is not set
# CONFIG_MMC_CB710 is not set
# CONFIG_MMC_VIA_SDMMC is not set
# CONFIG_MMC_USHC is not set
# CONFIG_MEMSTICK is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y

#
# LED drivers
#
# CONFIG_LEDS_ALIX2 is not set
# CONFIG_LEDS_PCA9532 is not set
# CONFIG_LEDS_LP3944 is not set
# CONFIG_LEDS_LP5521 is not set
# CONFIG_LEDS_LP5523 is not set
# CONFIG_LEDS_CLEVO_MAIL is not set
# CONFIG_LEDS_PCA955X is not set
# CONFIG_LEDS_BD2802 is not set
# CONFIG_LEDS_INTEL_SS4200 is not set
CONFIG_LEDS_TRIGGERS=y

#
# LED Triggers
#
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y

#
# iptables trigger is under Netfilter config (LED target)
#
# CONFIG_NFC_DEVICES is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
CONFIG_EDAC=y

#
# Reporting subsystems
#
# CONFIG_EDAC_DEBUG is not set
CONFIG_EDAC_DECODE_MCE=y
# CONFIG_EDAC_MCE_INJ is not set
CONFIG_EDAC_MM_EDAC=y
CONFIG_EDAC_MCE=y
# CONFIG_EDAC_AMD64 is not set
# CONFIG_EDAC_E752X is not set
# CONFIG_EDAC_I82975X is not set
# CONFIG_EDAC_I3000 is not set
# CONFIG_EDAC_I3200 is not set
# CONFIG_EDAC_X38 is not set
# CONFIG_EDAC_I5400 is not set
CONFIG_EDAC_I7CORE=y
# CONFIG_EDAC_I5000 is not set
# CONFIG_EDAC_I5100 is not set
# CONFIG_EDAC_I7300 is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set

#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_DRV_TEST is not set

#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
# CONFIG_RTC_DRV_DS3232 is not set
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_ISL12022 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8581 is not set
# CONFIG_RTC_DRV_RX8025 is not set

#
# SPI RTC drivers
#

#
# Platform RTC drivers
#
CONFIG_RTC_DRV_CMOS=y
# CONFIG_RTC_DRV_DS1286 is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set

#
# on-CPU RTC drivers
#
# CONFIG_DMADEVICES is not set
# CONFIG_AUXDISPLAY is not set
# CONFIG_UIO is not set
CONFIG_STAGING=y
# CONFIG_STAGING_EXCLUDE_BUILD is not set
# CONFIG_ET131X is not set
# CONFIG_SLICOSS is not set
# CONFIG_VIDEO_GO7007 is not set
# CONFIG_VIDEO_TM6000 is not set
# CONFIG_USB_DABUSB is not set
# CONFIG_USB_SE401 is not set
# CONFIG_USB_VICAM is not set
# CONFIG_USB_IP_COMMON is not set
# CONFIG_W35UND is not set
# CONFIG_PRISM2_USB is not set
# CONFIG_ECHO is not set
# CONFIG_BRCM80211 is not set
# CONFIG_RT2860 is not set
# CONFIG_RT2870 is not set
# CONFIG_COMEDI is not set
# CONFIG_ASUS_OLED is not set
# CONFIG_R8187SE is not set
# CONFIG_RTL8192U is not set
# CONFIG_RTL8192E is not set
# CONFIG_R8712U is not set
# CONFIG_TRANZPORT is not set
# CONFIG_POHMELFS is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_IDE_PHISON is not set
# CONFIG_LINE6_USB is not set
CONFIG_DRM_VMWGFX=m
# CONFIG_DRM_NOUVEAU is not set

#
# I2C encoder or helper chips
#
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_SIL164 is not set
# CONFIG_USB_SERIAL_QUATECH2 is not set
# CONFIG_USB_SERIAL_QUATECH_USB2 is not set
# CONFIG_VT6655 is not set
# CONFIG_VT6656 is not set
# CONFIG_HYPERV is not set
# CONFIG_VME_BUS is not set
# CONFIG_DX_SEP is not set
# CONFIG_IIO is not set
# CONFIG_ZRAM is not set
# CONFIG_SAMSUNG_LAPTOP is not set
# CONFIG_FB_SM7XX is not set
# CONFIG_VIDEO_DT3155 is not set
# CONFIG_CRYSTALHD is not set

#
# Texas Instruments shared transport line discipline
#
# CONFIG_ST_BT is not set
# CONFIG_FB_XGI is not set
# CONFIG_LIRC_STAGING is not set
# CONFIG_SMB_FS is not set
# CONFIG_EASYCAP is not set
# CONFIG_SOLO6X10 is not set
# CONFIG_ACPI_QUICKSTART is not set
CONFIG_MACH_NO_WESTBRIDGE=y
# CONFIG_ATH6K_LEGACY is not set
# CONFIG_USB_ENESTORAGE is not set
# CONFIG_BCM_WIMAX is not set
# CONFIG_FT1000 is not set

#
# Speakup console speech
#
# CONFIG_SPEAKUP is not set
# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
CONFIG_X86_PLATFORM_DEVICES=y
# CONFIG_ACERHDF is not set
# CONFIG_ASUS_LAPTOP is not set
# CONFIG_DELL_LAPTOP is not set
# CONFIG_FUJITSU_LAPTOP is not set
# CONFIG_MSI_LAPTOP is not set
# CONFIG_PANASONIC_LAPTOP is not set
# CONFIG_COMPAL_LAPTOP is not set
# CONFIG_SONY_LAPTOP is not set
# CONFIG_IDEAPAD_LAPTOP is not set
CONFIG_THINKPAD_ACPI=y
# CONFIG_THINKPAD_ACPI_ALSA_SUPPORT is not set
# CONFIG_THINKPAD_ACPI_DEBUGFACILITIES is not set
# CONFIG_THINKPAD_ACPI_DEBUG is not set
# CONFIG_THINKPAD_ACPI_UNSAFE_LEDS is not set
# CONFIG_THINKPAD_ACPI_VIDEO is not set
# CONFIG_THINKPAD_ACPI_HOTKEY_POLL is not set
# CONFIG_SENSORS_HDAPS is not set
# CONFIG_INTEL_MENLOW is not set
# CONFIG_EEEPC_LAPTOP is not set
# CONFIG_ACPI_WMI is not set
# CONFIG_ACPI_ASUS is not set
# CONFIG_TOPSTAR_LAPTOP is not set
# CONFIG_ACPI_TOSHIBA is not set
# CONFIG_TOSHIBA_BT_RFKILL is not set
# CONFIG_ACPI_CMPC is not set
# CONFIG_INTEL_IPS is not set
# CONFIG_IBM_RTL is not set

#
# Firmware Drivers
#
# CONFIG_EDD is not set
CONFIG_FIRMWARE_MEMMAP=y
CONFIG_DELL_RBU=m
CONFIG_DCDBAS=m
# CONFIG_DMIID is not set
# CONFIG_ISCSI_IBFT_FIND is not set

#
# File systems
#
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
# CONFIG_EXT2_FS_POSIX_ACL is not set
# CONFIG_EXT2_FS_SECURITY is not set
# CONFIG_EXT2_FS_XIP is not set
# CONFIG_EXT3_FS is not set
CONFIG_EXT4_FS=m
CONFIG_EXT4_USE_FOR_EXT23=y
CONFIG_EXT4_FS_XATTR=y
# CONFIG_EXT4_FS_POSIX_ACL is not set
# CONFIG_EXT4_FS_SECURITY is not set
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD2=m
CONFIG_FS_MBCACHE=y
CONFIG_REISERFS_FS=y
# CONFIG_REISERFS_CHECK is not set
# CONFIG_REISERFS_PROC_INFO is not set
# CONFIG_REISERFS_FS_XATTR is not set
# CONFIG_JFS_FS is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
CONFIG_BTRFS_FS=y
# CONFIG_BTRFS_FS_POSIX_ACL is not set
# CONFIG_NILFS2_FS is not set
# CONFIG_FS_POSIX_ACL is not set
CONFIG_FILE_LOCKING=y
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_FANOTIFY is not set
# CONFIG_QUOTA is not set
# CONFIG_QUOTACTL is not set
# CONFIG_AUTOFS4_FS is not set
CONFIG_FUSE_FS=y
CONFIG_CUSE=y

#
# Caches
#
# CONFIG_FSCACHE is not set

#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=y
CONFIG_JOLIET=y
# CONFIG_ZISOFS is not set
CONFIG_UDF_FS=y
CONFIG_UDF_NLS=y

#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
CONFIG_NTFS_FS=y
# CONFIG_NTFS_DEBUG is not set
CONFIG_NTFS_RW=y

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_PROC_KCORE is not set
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLBFS is not set
# CONFIG_HUGETLB_PAGE is not set
# CONFIG_CONFIGFS_FS is not set
# CONFIG_MISC_FILESYSTEMS is not set
# CONFIG_NETWORK_FILESYSTEMS is not set

#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_KARMA_PARTITION is not set
CONFIG_EFI_PARTITION=y
# CONFIG_SYSV68_PARTITION is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ASCII is not set
CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set

#
# Kernel hacking
#
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
# CONFIG_PRINTK_TIME is not set
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_FRAME_WARN=1024
# CONFIG_MAGIC_SYSRQ is not set
CONFIG_STRIP_ASM_SYMS=y
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_HARDLOCKUP_DETECTOR is not set
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_SLUB_STATS is not set
CONFIG_BKL=y
# CONFIG_SPARSE_RCU_POINTER is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_ARCH_WANT_FRAME_POINTERS=y
# CONFIG_FRAME_POINTER is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
CONFIG_USER_STACKTRACE_SUPPORT=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_FP_TEST=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set
# CONFIG_FIREWIRE_OHCI_REMOTE_DMA is not set
# CONFIG_DMA_API_DEBUG is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_ARCH_KMEMCHECK=y
# CONFIG_STRICT_DEVMEM is not set
# CONFIG_X86_VERBOSE_BOOTUP is not set
CONFIG_EARLY_PRINTK=y
# CONFIG_EARLY_PRINTK_DBGP is not set
# CONFIG_DEBUG_SET_MODULE_RONX is not set
# CONFIG_IOMMU_STRESS is not set
CONFIG_HAVE_MMIOTRACE_SUPPORT=y
CONFIG_IO_DELAY_TYPE_0X80=0
CONFIG_IO_DELAY_TYPE_0XED=1
CONFIG_IO_DELAY_TYPE_UDELAY=2
CONFIG_IO_DELAY_TYPE_NONE=3
# CONFIG_IO_DELAY_0X80 is not set
CONFIG_IO_DELAY_0XED=y
# CONFIG_IO_DELAY_UDELAY is not set
# CONFIG_IO_DELAY_NONE is not set
CONFIG_DEFAULT_IO_DELAY_TYPE=1
# CONFIG_OPTIMIZE_INLINING is not set

#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY_DMESG_RESTRICT is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITYFS is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=m
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_BLKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_PCOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
# CONFIG_CRYPTO_GF128MUL is not set
CONFIG_CRYPTO_NULL=m
# CONFIG_CRYPTO_PCRYPT is not set
CONFIG_CRYPTO_WORKQUEUE=y
# CONFIG_CRYPTO_CRYPTD is not set
CONFIG_CRYPTO_AUTHENC=m
# CONFIG_CRYPTO_TEST is not set

#
# Authenticated Encryption with Associated Data
#
# CONFIG_CRYPTO_CCM is not set
# CONFIG_CRYPTO_GCM is not set
# CONFIG_CRYPTO_SEQIV is not set

#
# Block modes
#
CONFIG_CRYPTO_CBC=y
# CONFIG_CRYPTO_CTR is not set
# CONFIG_CRYPTO_CTS is not set
CONFIG_CRYPTO_ECB=y
# CONFIG_CRYPTO_LRW is not set
CONFIG_CRYPTO_PCBC=m
# CONFIG_CRYPTO_XTS is not set

#
# Hash modes
#
CONFIG_CRYPTO_HMAC=y
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_VMAC is not set

#
# Digest
#
CONFIG_CRYPTO_CRC32C=y
# CONFIG_CRYPTO_CRC32C_INTEL is not set
# CONFIG_CRYPTO_GHASH is not set
# CONFIG_CRYPTO_MD4 is not set
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=m
# CONFIG_CRYPTO_RMD128 is not set
# CONFIG_CRYPTO_RMD160 is not set
# CONFIG_CRYPTO_RMD256 is not set
# CONFIG_CRYPTO_RMD320 is not set
CONFIG_CRYPTO_SHA1=m
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_WP512 is not set
# CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set

#
# Ciphers
#
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_AES_X86_64=y
# CONFIG_CRYPTO_AES_NI_INTEL is not set
# CONFIG_CRYPTO_ANUBIS is not set
CONFIG_CRYPTO_ARC4=y
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
CONFIG_CRYPTO_DES=m
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_SALSA20 is not set
# CONFIG_CRYPTO_SALSA20_X86_64 is not set
# CONFIG_CRYPTO_SEED is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_TEA is not set
# CONFIG_CRYPTO_TWOFISH is not set
# CONFIG_CRYPTO_TWOFISH_X86_64 is not set

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
# CONFIG_CRYPTO_ZLIB is not set
CONFIG_CRYPTO_LZO=y

#
# Random Number Generation
#
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_USER_API_HASH is not set
# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
# CONFIG_CRYPTO_HW is not set
CONFIG_HAVE_KVM=y
CONFIG_HAVE_KVM_IRQCHIP=y
CONFIG_HAVE_KVM_EVENTFD=y
CONFIG_KVM_APIC_ARCHITECTURE=y
CONFIG_KVM_MMIO=y
CONFIG_KVM_ASYNC_PF=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=m
CONFIG_KVM_INTEL=m
# CONFIG_KVM_AMD is not set
# CONFIG_VHOST_NET is not set
CONFIG_VIRTIO=y
CONFIG_VIRTIO_RING=y
CONFIG_VIRTIO_PCI=y
# CONFIG_VIRTIO_BALLOON is not set
# CONFIG_BINARY_PRINTF is not set

#
# Library routines
#
CONFIG_BITREVERSE=y
CONFIG_GENERIC_FIND_FIRST_BIT=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_FIND_LAST_BIT=y
CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
CONFIG_LIBCRC32C=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_XZ_DEC=y
CONFIG_XZ_DEC_X86=y
CONFIG_XZ_DEC_POWERPC=y
CONFIG_XZ_DEC_IA64=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
CONFIG_XZ_DEC_SPARC=y
CONFIG_XZ_DEC_BCJ=y
# CONFIG_XZ_DEC_TEST is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
CONFIG_NLATTR=y
CONFIG_AVERAGE=y

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Jeff Chua]

[-- Attachment #1: Type: text/plain, Size: 438 bytes --]

On Wed, Feb 9, 2011 at 8:55 AM, Jeff Chua <jeff.chua.linux@gmail.com> wrote:

> And the console hangs even without starting X.

I went back to retry suspending without starting X and realized that
it's only the "screen" that's hang .. and that's without drm and i915
loaded. On the console, I could still reboot the machine normally, but
not when in X (everything hangs including keybard).

Here's the kernel log without X.

Thanks.
Jeff

[-- Attachment #2: k1 --]
[-- Type: application/octet-stream, Size: 70804 bytes --]

2011-02-09T08:58:36.630368+08:00 boston kernel: [drm] Initialized drm 1.1.0 20060810
2011-02-09T08:59:03.710383+08:00 boston kernel: CPU 1 is now offline
2011-02-09T08:59:03.740369+08:00 boston kernel: coretemp coretemp.3: TjMax is 105 C.
2011-02-09T08:59:03.920373+08:00 boston kernel: CPU 2 is now offline
2011-02-09T08:59:03.930444+08:00 boston kernel: CPU 3 MCA banks CMCI:2 CMCI:3 CMCI:5
2011-02-09T08:59:04.110372+08:00 boston kernel: CPU 3 is now offline
2011-02-09T08:59:04.110395+08:00 boston kernel: SMP alternatives: switching to UP code
2011-02-09T08:59:04.152729+08:00 boston kernel: PM: Syncing filesystems ... done.
2011-02-09T08:59:08.559749+08:00 boston kernel: Freezing user space processes ... (elapsed 0.01 seconds) done.
2011-02-09T08:59:08.559775+08:00 boston kernel: Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done.
2011-02-09T08:59:08.559778+08:00 boston kernel: Suspending console(s) (use no_console_suspend to debug)
2011-02-09T08:59:08.559779+08:00 boston kernel: sd 0:0:0:0: [sda] Synchronizing SCSI cache
2011-02-09T08:59:08.559781+08:00 boston kernel: sd 0:0:0:0: [sda] Stopping disk
2011-02-09T08:59:08.559783+08:00 boston kernel: ehci_hcd 0000:00:1d.0: PCI INT D disabled
2011-02-09T08:59:08.559785+08:00 boston kernel: ehci_hcd 0000:00:1a.0: PCI INT D disabled
2011-02-09T08:59:08.559787+08:00 boston kernel: HDA Intel 0000:00:1b.0: PCI INT B disabled
2011-02-09T08:59:08.559788+08:00 boston kernel: PM: suspend of devices complete after 549.467 msecs
2011-02-09T08:59:08.559790+08:00 boston kernel: ehci_hcd 0000:00:1d.0: power state changed by ACPI to D3
2011-02-09T08:59:08.559791+08:00 boston kernel: ehci_hcd 0000:00:1a.0: power state changed by ACPI to D3
2011-02-09T08:59:08.559793+08:00 boston kernel: PM: late suspend of devices complete after 90.110 msecs
2011-02-09T08:59:08.559794+08:00 boston kernel: ACPI: Preparing to enter system sleep state S3
2011-02-09T08:59:08.559795+08:00 boston kernel: PM: Saving platform NVS memory
2011-02-09T08:59:08.559797+08:00 boston kernel: Disabling non-boot CPUs ...
2011-02-09T08:59:08.559798+08:00 boston kernel: Extended CMOS year: 2000
2011-02-09T08:59:08.559799+08:00 boston kernel: Back to C!
2011-02-09T08:59:08.559800+08:00 boston kernel: PM: Restoring platform NVS memory
2011-02-09T08:59:08.559802+08:00 boston kernel: Extended CMOS year: 2000
2011-02-09T08:59:08.559803+08:00 boston kernel: ACPI: Waking up from system sleep state S3
2011-02-09T08:59:08.559805+08:00 boston kernel: agpgart-intel 0000:00:00.0: restoring config space at offset 0x1 (was 0x900006, writing 0x20900006)
2011-02-09T08:59:08.559807+08:00 boston kernel: ehci_hcd 0000:00:1a.0: restoring config space at offset 0xf (was 0x400, writing 0x40b)
2011-02-09T08:59:08.559808+08:00 boston kernel: ehci_hcd 0000:00:1a.0: restoring config space at offset 0x4 (was 0x0, writing 0xf2728000)
2011-02-09T08:59:08.559810+08:00 boston kernel: ehci_hcd 0000:00:1a.0: restoring config space at offset 0x1 (was 0x2900000, writing 0x2900102)
2011-02-09T08:59:08.559812+08:00 boston kernel: ehci_hcd 0000:00:1a.0: power state changed by ACPI to D0
2011-02-09T08:59:08.559813+08:00 boston kernel: ehci_hcd 0000:00:1a.0: power state changed by ACPI to D0
2011-02-09T08:59:08.559815+08:00 boston kernel: pcieport 0000:00:1c.0: restoring config space at offset 0x7 (was 0xf0, writing 0x200000f0)
2011-02-09T08:59:08.559816+08:00 boston kernel: pcieport 0000:00:1c.4: restoring config space at offset 0xf (was 0x100, writing 0x4010b)
2011-02-09T08:59:08.559818+08:00 boston kernel: pcieport 0000:00:1c.4: restoring config space at offset 0x9 (was 0x10001, writing 0x1fff1)
2011-02-09T08:59:08.559820+08:00 boston kernel: pcieport 0000:00:1c.4: restoring config space at offset 0x8 (was 0x0, writing 0xf240f240)
2011-02-09T08:59:08.559821+08:00 boston kernel: pcieport 0000:00:1c.4: restoring config space at offset 0x7 (was 0x0, writing 0x200000f0)
2011-02-09T08:59:08.559823+08:00 boston kernel: pcieport 0000:00:1c.4: restoring config space at offset 0x3 (was 0x810000, writing 0x810010)
2011-02-09T08:59:08.559825+08:00 boston kernel: pcieport 0000:00:1c.4: restoring config space at offset 0x1 (was 0x100000, writing 0x100107)
2011-02-09T08:59:08.559827+08:00 boston kernel: ehci_hcd 0000:00:1d.0: restoring config space at offset 0xf (was 0x400, writing 0x40b)
2011-02-09T08:59:08.559828+08:00 boston kernel: ehci_hcd 0000:00:1d.0: restoring config space at offset 0x4 (was 0x0, writing 0xf2728400)
2011-02-09T08:59:08.559830+08:00 boston kernel: ehci_hcd 0000:00:1d.0: restoring config space at offset 0x1 (was 0x2900000, writing 0x2900102)
2011-02-09T08:59:08.559832+08:00 boston kernel: ehci_hcd 0000:00:1d.0: power state changed by ACPI to D0
2011-02-09T08:59:08.559833+08:00 boston kernel: ehci_hcd 0000:00:1d.0: power state changed by ACPI to D0
2011-02-09T08:59:08.559835+08:00 boston kernel: ahci 0000:00:1f.2: restoring config space at offset 0x1 (was 0x2b00007, writing 0x2b00407)
2011-02-09T08:59:08.559837+08:00 boston kernel: pci 0000:00:1f.6: restoring config space at offset 0xf (was 0x400, writing 0x40b)
2011-02-09T08:59:08.559838+08:00 boston kernel: pci 0000:00:1f.6: restoring config space at offset 0x1 (was 0x100000, writing 0x100002)
2011-02-09T08:59:08.559840+08:00 boston kernel: PM: early resume of devices complete after 50.681 msecs
2011-02-09T08:59:08.559841+08:00 boston kernel: ehci_hcd 0000:00:1a.0: power state changed by ACPI to D0
2011-02-09T08:59:08.559843+08:00 boston kernel: ehci_hcd 0000:00:1a.0: power state changed by ACPI to D0
2011-02-09T08:59:08.559844+08:00 boston kernel: ehci_hcd 0000:00:1a.0: PCI INT D -> GSI 23 (level, low) -> IRQ 23
2011-02-09T08:59:08.559846+08:00 boston kernel: ehci_hcd 0000:00:1a.0: setting latency timer to 64
2011-02-09T08:59:08.559847+08:00 boston kernel: HDA Intel 0000:00:1b.0: PCI INT B -> GSI 17 (level, low) -> IRQ 17
2011-02-09T08:59:08.559849+08:00 boston kernel: HDA Intel 0000:00:1b.0: setting latency timer to 64
2011-02-09T08:59:08.559850+08:00 boston kernel: HDA Intel 0000:00:1b.0: irq 41 for MSI/MSI-X
2011-02-09T08:59:08.559851+08:00 boston kernel: ehci_hcd 0000:00:1d.0: power state changed by ACPI to D0
2011-02-09T08:59:08.559853+08:00 boston kernel: ehci_hcd 0000:00:1d.0: power state changed by ACPI to D0
2011-02-09T08:59:08.559854+08:00 boston kernel: ehci_hcd 0000:00:1d.0: PCI INT D -> GSI 19 (level, low) -> IRQ 19
2011-02-09T08:59:08.559856+08:00 boston kernel: ehci_hcd 0000:00:1d.0: setting latency timer to 64
2011-02-09T08:59:08.559857+08:00 boston kernel: pci 0000:00:1e.0: setting latency timer to 64
2011-02-09T08:59:08.559858+08:00 boston kernel: ahci 0000:00:1f.2: setting latency timer to 64
2011-02-09T08:59:08.559860+08:00 boston kernel: sd 0:0:0:0: [sda] Starting disk
2011-02-09T08:59:08.559861+08:00 boston kernel: ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
2011-02-09T08:59:08.559863+08:00 boston kernel: ata1.00: ACPI cmd ef/02:00:00:00:00:a0 (unknown) succeeded
2011-02-09T08:59:08.559864+08:00 boston kernel: ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (unknown) filtered out
2011-02-09T08:59:08.559866+08:00 boston kernel: ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (unknown) filtered out
2011-02-09T08:59:08.559867+08:00 boston kernel: ata1.00: ACPI cmd ef/02:00:00:00:00:a0 (unknown) succeeded
2011-02-09T08:59:08.559869+08:00 boston kernel: ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (unknown) filtered out
2011-02-09T08:59:08.559870+08:00 boston kernel: ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (unknown) filtered out
2011-02-09T08:59:08.559872+08:00 boston kernel: ata1.00: configured for UDMA/100
2011-02-09T08:59:08.559873+08:00 boston kernel: ata5: SATA link down (SStatus 0 SControl 300)
2011-02-09T08:59:08.559878+08:00 boston kernel: ata6: SATA link down (SStatus 0 SControl 300)
2011-02-09T08:59:08.559879+08:00 boston kernel: PM: resume of devices complete after 406.945 msecs
2011-02-09T08:59:08.568986+08:00 boston kernel: Restarting tasks ... done.
2011-02-09T08:59:08.598994+08:00 boston kernel: SMP alternatives: switching to SMP code
2011-02-09T08:59:08.599004+08:00 boston kernel: Booting Node 0 Processor 1 APIC 0x1
2011-02-09T08:59:08.789074+08:00 boston kernel: Switched to NOHz mode on CPU #1
2011-02-09T08:59:08.938997+08:00 boston kernel: Booting Node 0 Processor 2 APIC 0x4
2011-02-09T08:59:09.129093+08:00 boston kernel: Switched to NOHz mode on CPU #2
2011-02-09T08:59:09.279000+08:00 boston kernel: coretemp coretemp.2: TjMax is 105 C.
2011-02-09T08:59:09.299030+08:00 boston kernel: Booting Node 0 Processor 3 APIC 0x5
2011-02-09T08:59:09.489080+08:00 boston kernel: Switched to NOHz mode on CPU #3
2011-02-09T08:59:16.713584+08:00 boston kernel: Kernel logging (proc) stopped.





2011-02-09T08:59:37.422763+08:00 boston kernel: imklog 5.6.2, log source = /proc/kmsg started.
2011-02-09T08:59:37.423041+08:00 boston kernel: I: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
2011-02-09T08:59:37.423047+08:00 boston kernel: ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1])
2011-02-09T08:59:37.423049+08:00 boston kernel: ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1])
2011-02-09T08:59:37.423053+08:00 boston kernel: ACPI: IOAPIC (id[0x01] address[0xfec00000] gsi_base[0])
2011-02-09T08:59:37.423055+08:00 boston kernel: IOAPIC[0]: apic_id 1, version 32, address 0xfec00000, GSI 0-23
2011-02-09T08:59:37.423057+08:00 boston kernel: ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
2011-02-09T08:59:37.423058+08:00 boston kernel: ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
2011-02-09T08:59:37.423060+08:00 boston kernel: ACPI: IRQ0 used by override.
2011-02-09T08:59:37.423061+08:00 boston kernel: ACPI: IRQ2 used by override.
2011-02-09T08:59:37.423062+08:00 boston kernel: ACPI: IRQ9 used by override.
2011-02-09T08:59:37.423065+08:00 boston kernel: Using ACPI (MADT) for SMP configuration information
2011-02-09T08:59:37.423079+08:00 boston kernel: ACPI: HPET id: 0x8086a701 base: 0xfed00000
2011-02-09T08:59:37.423081+08:00 boston kernel: SMP: Allowing 4 CPUs, 0 hotplug CPUs
2011-02-09T08:59:37.423082+08:00 boston kernel: nr_irqs_gsi: 40
2011-02-09T08:59:37.423084+08:00 boston kernel: PM: Registered nosave memory: 000000000009e000 - 000000000009f000
2011-02-09T08:59:37.423085+08:00 boston kernel: PM: Registered nosave memory: 000000000009f000 - 00000000000a0000
2011-02-09T08:59:37.423087+08:00 boston kernel: PM: Registered nosave memory: 00000000000a0000 - 00000000000dc000
2011-02-09T08:59:37.423088+08:00 boston kernel: PM: Registered nosave memory: 00000000000dc000 - 0000000000100000
2011-02-09T08:59:37.423092+08:00 boston kernel: PM: Registered nosave memory: 00000000bb27c000 - 00000000bb282000
2011-02-09T08:59:37.423093+08:00 boston kernel: PM: Registered nosave memory: 00000000bb35f000 - 00000000bb371000
2011-02-09T08:59:37.423095+08:00 boston kernel: PM: Registered nosave memory: 00000000bb371000 - 00000000bb3f2000
2011-02-09T08:59:37.423096+08:00 boston kernel: PM: Registered nosave memory: 00000000bb3f2000 - 00000000bb40f000
2011-02-09T08:59:37.423098+08:00 boston kernel: PM: Registered nosave memory: 00000000bb46f000 - 00000000bb668000
2011-02-09T08:59:37.423099+08:00 boston kernel: PM: Registered nosave memory: 00000000bb668000 - 00000000bb6e8000
2011-02-09T08:59:37.423101+08:00 boston kernel: PM: Registered nosave memory: 00000000bb6e8000 - 00000000bb70f000
2011-02-09T08:59:37.423104+08:00 boston kernel: PM: Registered nosave memory: 00000000bb717000 - 00000000bb71f000
2011-02-09T08:59:37.423105+08:00 boston kernel: PM: Registered nosave memory: 00000000bb76b000 - 00000000bb777000
2011-02-09T08:59:37.423107+08:00 boston kernel: PM: Registered nosave memory: 00000000bb777000 - 00000000bb77a000
2011-02-09T08:59:37.423108+08:00 boston kernel: PM: Registered nosave memory: 00000000bb77a000 - 00000000bb781000
2011-02-09T08:59:37.423110+08:00 boston kernel: PM: Registered nosave memory: 00000000bb781000 - 00000000bb782000
2011-02-09T08:59:37.423111+08:00 boston kernel: PM: Registered nosave memory: 00000000bb782000 - 00000000bb78b000
2011-02-09T08:59:37.423113+08:00 boston kernel: PM: Registered nosave memory: 00000000bb78b000 - 00000000bb78c000
2011-02-09T08:59:37.423114+08:00 boston kernel: PM: Registered nosave memory: 00000000bb78c000 - 00000000bb79f000
2011-02-09T08:59:37.423117+08:00 boston kernel: PM: Registered nosave memory: 00000000bb79f000 - 00000000bb7ff000
2011-02-09T08:59:37.423119+08:00 boston kernel: PM: Registered nosave memory: 00000000bb800000 - 00000000c0000000
2011-02-09T08:59:37.423120+08:00 boston kernel: PM: Registered nosave memory: 00000000c0000000 - 00000000e0000000
2011-02-09T08:59:37.423122+08:00 boston kernel: PM: Registered nosave memory: 00000000e0000000 - 00000000f0000000
2011-02-09T08:59:37.423123+08:00 boston kernel: PM: Registered nosave memory: 00000000f0000000 - 00000000feaff000
2011-02-09T08:59:37.423126+08:00 boston kernel: PM: Registered nosave memory: 00000000feaff000 - 00000000feb00000
2011-02-09T08:59:37.423128+08:00 boston kernel: PM: Registered nosave memory: 00000000feb00000 - 00000000fec00000
2011-02-09T08:59:37.423143+08:00 boston kernel: PM: Registered nosave memory: 00000000fec00000 - 00000000fec10000
2011-02-09T08:59:37.423148+08:00 boston kernel: PM: Registered nosave memory: 00000000fec10000 - 00000000fed00000
2011-02-09T08:59:37.423151+08:00 boston kernel: PM: Registered nosave memory: 00000000fed00000 - 00000000fed1c000
2011-02-09T08:59:37.423156+08:00 boston kernel: PM: Registered nosave memory: 00000000fed1c000 - 00000000fed90000
2011-02-09T08:59:37.423159+08:00 boston kernel: PM: Registered nosave memory: 00000000fed90000 - 00000000fee00000
2011-02-09T08:59:37.423162+08:00 boston kernel: PM: Registered nosave memory: 00000000fee00000 - 00000000fee01000
2011-02-09T08:59:37.423165+08:00 boston kernel: PM: Registered nosave memory: 00000000fee01000 - 00000000ff000000
2011-02-09T08:59:37.423167+08:00 boston kernel: PM: Registered nosave memory: 00000000ff000000 - 0000000100000000
2011-02-09T08:59:37.423170+08:00 boston kernel: PM: Registered nosave memory: 00000001fc000000 - 0000000200000000
2011-02-09T08:59:37.423173+08:00 boston kernel: Allocating PCI resources starting at c0000000 (gap: c0000000:20000000)
2011-02-09T08:59:37.423178+08:00 boston kernel: Booting paravirtualized kernel on bare hardware
2011-02-09T08:59:37.423181+08:00 boston kernel: setup_percpu: NR_CPUS:16 nr_cpumask_bits:16 nr_cpu_ids:4 nr_node_ids:1
2011-02-09T08:59:37.423183+08:00 boston kernel: PERCPU: Embedded 26 pages/cpu @ffff8800bb000000 s75392 r8192 d22912 u524288
2011-02-09T08:59:37.423186+08:00 boston kernel: pcpu-alloc: s75392 r8192 d22912 u524288 alloc=1*2097152
2011-02-09T08:59:37.423189+08:00 boston kernel: pcpu-alloc: [0] 0 1 2 3 
2011-02-09T08:59:37.423194+08:00 boston kernel: Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 2012790
2011-02-09T08:59:37.423197+08:00 boston kernel: Policy zone: Normal
2011-02-09T08:59:37.423203+08:00 boston kernel: Kernel command line: BOOT_IMAGE=(hd0,14)/linux/bzc1 root=/dev/sda2 ro resume=/dev/sda3 reboot=bios mce x11 snd-hda-intel.model=lenovo-x200 nf_conntrack_sip.sip_direct_signalling=0 nf_conntrack_sip.sip_direct_media=0 testing_only=\"this is got to be good. Now I can send in a very long line just like 2.4 and need not worry about the line being too long. What a great way to start a great year!!! Cool!\"
2011-02-09T08:59:37.423208+08:00 boston kernel: PID hash table entries: 4096 (order: 3, 32768 bytes)
2011-02-09T08:59:37.423211+08:00 boston kernel: Checking aperture...
2011-02-09T08:59:37.423213+08:00 boston kernel: No AGP bridge found
2011-02-09T08:59:37.423363+08:00 boston kernel: Memory: 7989592k/9371648k available (4737k kernel code, 1192336k absent, 189720k reserved, 2573k data, 576k init)
2011-02-09T08:59:37.423368+08:00 boston kernel: SLUB: Genslabs=15, HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
2011-02-09T08:59:37.423370+08:00 boston kernel: Preemptable hierarchical RCU implementation.
2011-02-09T08:59:37.423371+08:00 boston kernel: 	CONFIG_RCU_FANOUT set to non-default value of 32
2011-02-09T08:59:37.423376+08:00 boston kernel: 	RCU-based detection of stalled CPUs is disabled.
2011-02-09T08:59:37.423377+08:00 boston kernel: 	Verbose stalled-CPUs detection is disabled.
2011-02-09T08:59:37.423379+08:00 boston kernel: NR_IRQS:768
2011-02-09T08:59:37.423380+08:00 boston kernel: Extended CMOS year: 2000
2011-02-09T08:59:37.423382+08:00 boston kernel: Console: colour dummy device 80x25
2011-02-09T08:59:37.423383+08:00 boston kernel: console [tty0] enabled
2011-02-09T08:59:37.423384+08:00 boston kernel: hpet clockevent registered
2011-02-09T08:59:37.423387+08:00 boston kernel: Fast TSC calibration using PIT
2011-02-09T08:59:37.423389+08:00 boston kernel: Detected 2127.639 MHz processor.
2011-02-09T08:59:37.423391+08:00 boston kernel: Calibrating delay loop (skipped), value calculated using timer frequency.. 4255.27 BogoMIPS (lpj=21276390)
2011-02-09T08:59:37.423392+08:00 boston kernel: pid_max: default: 32768 minimum: 301
2011-02-09T08:59:37.423394+08:00 boston kernel: Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes)
2011-02-09T08:59:37.423395+08:00 boston kernel: Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes)
2011-02-09T08:59:37.423397+08:00 boston kernel: Mount-cache hash table entries: 256
2011-02-09T08:59:37.423400+08:00 boston kernel: CPU: Physical Processor ID: 0
2011-02-09T08:59:37.423401+08:00 boston kernel: CPU: Processor Core ID: 0
2011-02-09T08:59:37.423403+08:00 boston kernel: mce: CPU supports 9 MCE banks
2011-02-09T08:59:37.423404+08:00 boston kernel: CPU0: Thermal monitoring enabled (TM1)
2011-02-09T08:59:37.423405+08:00 boston kernel: using mwait in idle threads.
2011-02-09T08:59:37.423407+08:00 boston kernel: ACPI: Core revision 20110112
2011-02-09T08:59:37.423408+08:00 boston kernel: Setting APIC routing to flat
2011-02-09T08:59:37.423409+08:00 boston kernel: ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
2011-02-09T08:59:37.423413+08:00 boston kernel: CPU0: Intel(R) Core(TM) i7 CPU       L 640  @ 2.13GHz stepping 02
2011-02-09T08:59:37.423414+08:00 boston kernel: Performance Events: PEBS fmt1+, Westmere events, Intel PMU driver.
2011-02-09T08:59:37.423416+08:00 boston kernel: ... version:                3
2011-02-09T08:59:37.423417+08:00 boston kernel: ... bit width:              48
2011-02-09T08:59:37.423418+08:00 boston kernel: ... generic registers:      4
2011-02-09T08:59:37.423420+08:00 boston kernel: ... value mask:             0000ffffffffffff
2011-02-09T08:59:37.423421+08:00 boston kernel: ... max period:             000000007fffffff
2011-02-09T08:59:37.423424+08:00 boston kernel: ... fixed-purpose events:   3
2011-02-09T08:59:37.423425+08:00 boston kernel: ... event mask:             000000070000000f
2011-02-09T08:59:37.423427+08:00 boston kernel: Booting Node   0, Processors  #1 #2 #3 Ok.
2011-02-09T08:59:37.423428+08:00 boston kernel: Brought up 4 CPUs
2011-02-09T08:59:37.423429+08:00 boston kernel: Total of 4 processors activated (17023.19 BogoMIPS).
2011-02-09T08:59:37.423431+08:00 boston kernel: NET: Registered protocol family 16
2011-02-09T08:59:37.423433+08:00 boston kernel: ACPI FADT declares the system doesn't support PCIe ASPM, so disable it
2011-02-09T08:59:37.423434+08:00 boston kernel: ACPI: bus type pci registered
2011-02-09T08:59:37.423437+08:00 boston kernel: PCI: Using configuration type 1 for base access
2011-02-09T08:59:37.423451+08:00 boston kernel: bio: create slab <bio-0> at 0
2011-02-09T08:59:37.423454+08:00 boston kernel: ACPI: EC: EC description table is found, configuring boot EC
2011-02-09T08:59:37.423456+08:00 boston kernel: [Firmware Bug]: ACPI: BIOS _OSI(Linux) query ignored
2011-02-09T08:59:37.423457+08:00 boston kernel: ACPI: SSDT 00000000bb71a918 003EB (v01  PmRef  Cpu0Ist 00003000 INTL 20050513)
2011-02-09T08:59:37.423459+08:00 boston kernel: ACPI: Dynamic OEM Table Load:
2011-02-09T08:59:37.423460+08:00 boston kernel: ACPI: SSDT           (null) 003EB (v01  PmRef  Cpu0Ist 00003000 INTL 20050513)
2011-02-09T08:59:37.423464+08:00 boston kernel: ACPI: SSDT 00000000bb718718 006B2 (v01  PmRef  Cpu0Cst 00003001 INTL 20050513)
2011-02-09T08:59:37.423465+08:00 boston kernel: ACPI: Dynamic OEM Table Load:
2011-02-09T08:59:37.423467+08:00 boston kernel: ACPI: SSDT           (null) 006B2 (v01  PmRef  Cpu0Cst 00003001 INTL 20050513)
2011-02-09T08:59:37.423468+08:00 boston kernel: ACPI: SSDT 00000000bb719a98 00303 (v01  PmRef    ApIst 00003000 INTL 20050513)
2011-02-09T08:59:37.423470+08:00 boston kernel: ACPI: Dynamic OEM Table Load:
2011-02-09T08:59:37.423471+08:00 boston kernel: ACPI: SSDT           (null) 00303 (v01  PmRef    ApIst 00003000 INTL 20050513)
2011-02-09T08:59:37.423473+08:00 boston kernel: ACPI: SSDT 00000000bb717d98 00119 (v01  PmRef    ApCst 00003000 INTL 20050513)
2011-02-09T08:59:37.423474+08:00 boston kernel: ACPI: Dynamic OEM Table Load:
2011-02-09T08:59:37.423477+08:00 boston kernel: ACPI: SSDT           (null) 00119 (v01  PmRef    ApCst 00003000 INTL 20050513)
2011-02-09T08:59:37.423479+08:00 boston kernel: ACPI: Interpreter enabled
2011-02-09T08:59:37.423480+08:00 boston kernel: ACPI: (supports S0 S3 S4 S5)
2011-02-09T08:59:37.423482+08:00 boston kernel: ACPI: Using IOAPIC for interrupt routing
2011-02-09T08:59:37.423483+08:00 boston kernel: ACPI: Power Resource [PUBS] (on)
2011-02-09T08:59:37.423485+08:00 boston kernel: ACPI: EC: GPE = 0x11, I/O: command/status = 0x66, data = 0x62
2011-02-09T08:59:37.423486+08:00 boston kernel: ACPI: ACPI Dock Station Driver: 3 docks/bays found
2011-02-09T08:59:37.423488+08:00 boston kernel: HEST: Table not found.
2011-02-09T08:59:37.423492+08:00 boston kernel: PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
2011-02-09T08:59:37.423494+08:00 boston kernel: ACPI: PCI Root Bridge [UNCR] (domain 0000 [bus ff])
2011-02-09T08:59:37.423496+08:00 boston kernel: pci 0000:ff:00.0: [8086:2c62] type 0 class 0x000600
2011-02-09T08:59:37.423497+08:00 boston kernel: pci 0000:ff:00.1: [8086:2d01] type 0 class 0x000600
2011-02-09T08:59:37.423499+08:00 boston kernel: pci 0000:ff:02.0: [8086:2d10] type 0 class 0x000600
2011-02-09T08:59:37.423500+08:00 boston kernel: pci 0000:ff:02.1: [8086:2d11] type 0 class 0x000600
2011-02-09T08:59:37.423501+08:00 boston kernel: pci 0000:ff:02.2: [8086:2d12] type 0 class 0x000600
2011-02-09T08:59:37.423505+08:00 boston kernel: pci 0000:ff:02.3: [8086:2d13] type 0 class 0x000600
2011-02-09T08:59:37.423506+08:00 boston kernel: ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-fe])
2011-02-09T08:59:37.423508+08:00 boston kernel: pci_root PNP0A08:00: host bridge window [io  0x0000-0x0cf7]
2011-02-09T08:59:37.423510+08:00 boston kernel: pci_root PNP0A08:00: host bridge window [io  0x0d00-0xffff]
2011-02-09T08:59:37.423511+08:00 boston kernel: pci_root PNP0A08:00: host bridge window [mem 0x000a0000-0x000bffff]
2011-02-09T08:59:37.423513+08:00 boston kernel: pci_root PNP0A08:00: host bridge window [mem 0x000d0000-0x000d3fff]
2011-02-09T08:59:37.423515+08:00 boston kernel: pci_root PNP0A08:00: host bridge window [mem 0x000d4000-0x000d7fff]
2011-02-09T08:59:37.423516+08:00 boston kernel: pci_root PNP0A08:00: host bridge window [mem 0x000d8000-0x000dbfff]
2011-02-09T08:59:37.423652+08:00 boston kernel: pci_root PNP0A08:00: host bridge window [mem 0xc0000000-0xfebfffff]
2011-02-09T08:59:37.423654+08:00 boston kernel: pci 0000:00:00.0: [8086:0044] type 0 class 0x000600
2011-02-09T08:59:37.423655+08:00 boston kernel: pci 0000:00:02.0: [8086:0046] type 0 class 0x000300
2011-02-09T08:59:37.423657+08:00 boston kernel: pci 0000:00:02.0: reg 10: [mem 0xf2000000-0xf23fffff 64bit]
2011-02-09T08:59:37.423658+08:00 boston kernel: pci 0000:00:02.0: reg 18: [mem 0xd0000000-0xdfffffff 64bit pref]
2011-02-09T08:59:37.423659+08:00 boston kernel: pci 0000:00:02.0: reg 20: [io  0x1800-0x1807]
2011-02-09T08:59:37.423661+08:00 boston kernel: pci 0000:00:16.0: [8086:3b64] type 0 class 0x000780
2011-02-09T08:59:37.423664+08:00 boston kernel: pci 0000:00:16.0: reg 10: [mem 0xf2727800-0xf272780f 64bit]
2011-02-09T08:59:37.423666+08:00 boston kernel: pci 0000:00:16.0: PME# supported from D0 D3hot D3cold
2011-02-09T08:59:37.423667+08:00 boston kernel: pci 0000:00:16.0: PME# disabled
2011-02-09T08:59:37.423668+08:00 boston kernel: pci 0000:00:19.0: [8086:10ea] type 0 class 0x000200
2011-02-09T08:59:37.423670+08:00 boston kernel: pci 0000:00:19.0: reg 10: [mem 0xf2500000-0xf251ffff]
2011-02-09T08:59:37.423671+08:00 boston kernel: pci 0000:00:19.0: reg 14: [mem 0xf2525000-0xf2525fff]
2011-02-09T08:59:37.423673+08:00 boston kernel: pci 0000:00:19.0: reg 18: [io  0x1820-0x183f]
2011-02-09T08:59:37.423674+08:00 boston kernel: pci 0000:00:19.0: PME# supported from D0 D3hot D3cold
2011-02-09T08:59:37.423677+08:00 boston kernel: pci 0000:00:19.0: PME# disabled
2011-02-09T08:59:37.423679+08:00 boston kernel: pci 0000:00:1a.0: [8086:3b3c] type 0 class 0x000c03
2011-02-09T08:59:37.423680+08:00 boston kernel: pci 0000:00:1a.0: reg 10: [mem 0xf2728000-0xf27283ff]
2011-02-09T08:59:37.423681+08:00 boston kernel: pci 0000:00:1a.0: PME# supported from D0 D3hot D3cold
2011-02-09T08:59:37.423683+08:00 boston kernel: pci 0000:00:1a.0: PME# disabled
2011-02-09T08:59:37.423684+08:00 boston kernel: pci 0000:00:1b.0: [8086:3b56] type 0 class 0x000403
2011-02-09T08:59:37.423686+08:00 boston kernel: pci 0000:00:1b.0: reg 10: [mem 0xf2520000-0xf2523fff 64bit]
2011-02-09T08:59:37.423689+08:00 boston kernel: pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold
2011-02-09T08:59:37.423705+08:00 boston kernel: pci 0000:00:1b.0: PME# disabled
2011-02-09T08:59:37.423707+08:00 boston kernel: pci 0000:00:1c.0: [8086:3b42] type 1 class 0x000604
2011-02-09T08:59:37.423709+08:00 boston kernel: pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
2011-02-09T08:59:37.423710+08:00 boston kernel: pci 0000:00:1c.0: PME# disabled
2011-02-09T08:59:37.423712+08:00 boston kernel: pci 0000:00:1c.3: [8086:3b48] type 1 class 0x000604
2011-02-09T08:59:37.423713+08:00 boston kernel: pci 0000:00:1c.3: PME# supported from D0 D3hot D3cold
2011-02-09T08:59:37.423715+08:00 boston kernel: pci 0000:00:1c.3: PME# disabled
2011-02-09T08:59:37.423716+08:00 boston kernel: pci 0000:00:1c.4: [8086:3b4a] type 1 class 0x000604
2011-02-09T08:59:37.423718+08:00 boston kernel: pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold
2011-02-09T08:59:37.423719+08:00 boston kernel: pci 0000:00:1c.4: PME# disabled
2011-02-09T08:59:37.423720+08:00 boston kernel: pci 0000:00:1d.0: [8086:3b34] type 0 class 0x000c03
2011-02-09T08:59:37.423722+08:00 boston kernel: pci 0000:00:1d.0: reg 10: [mem 0xf2728400-0xf27287ff]
2011-02-09T08:59:37.423723+08:00 boston kernel: pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold
2011-02-09T08:59:37.423725+08:00 boston kernel: pci 0000:00:1d.0: PME# disabled
2011-02-09T08:59:37.423726+08:00 boston kernel: pci 0000:00:1e.0: [8086:2448] type 1 class 0x000604
2011-02-09T08:59:37.423728+08:00 boston kernel: pci 0000:00:1f.0: [8086:3b07] type 0 class 0x000601
2011-02-09T08:59:37.423729+08:00 boston kernel: pci 0000:00:1f.2: [8086:3b2f] type 0 class 0x000106
2011-02-09T08:59:37.423730+08:00 boston kernel: pci 0000:00:1f.2: reg 10: [io  0x1860-0x1867]
2011-02-09T08:59:37.423732+08:00 boston kernel: pci 0000:00:1f.2: reg 14: [io  0x1814-0x1817]
2011-02-09T08:59:37.423733+08:00 boston kernel: pci 0000:00:1f.2: reg 18: [io  0x1818-0x181f]
2011-02-09T08:59:37.423735+08:00 boston kernel: pci 0000:00:1f.2: reg 1c: [io  0x1810-0x1813]
2011-02-09T08:59:37.423736+08:00 boston kernel: pci 0000:00:1f.2: reg 20: [io  0x1840-0x185f]
2011-02-09T08:59:37.423737+08:00 boston kernel: pci 0000:00:1f.2: reg 24: [mem 0xf2727000-0xf27277ff]
2011-02-09T08:59:37.423739+08:00 boston kernel: pci 0000:00:1f.2: PME# supported from D3hot
2011-02-09T08:59:37.423740+08:00 boston kernel: pci 0000:00:1f.2: PME# disabled
2011-02-09T08:59:37.423742+08:00 boston kernel: pci 0000:00:1f.3: [8086:3b30] type 0 class 0x000c05
2011-02-09T08:59:37.423743+08:00 boston kernel: pci 0000:00:1f.3: reg 10: [mem 0xf2728800-0xf27288ff 64bit]
2011-02-09T08:59:37.423745+08:00 boston kernel: pci 0000:00:1f.3: reg 20: [io  0x1880-0x189f]
2011-02-09T08:59:37.423746+08:00 boston kernel: pci 0000:00:1f.6: [8086:3b32] type 0 class 0x001180
2011-02-09T08:59:37.423747+08:00 boston kernel: pci 0000:00:1f.6: reg 10: [mem 0xf2526000-0xf2526fff 64bit]
2011-02-09T08:59:37.423749+08:00 boston kernel: pci 0000:00:1c.0: PCI bridge to [bus 0d-0d]
2011-02-09T08:59:37.423753+08:00 boston kernel: pci 0000:00:1c.0:   bridge window [io  0xf000-0x0000] (disabled)
2011-02-09T08:59:37.423755+08:00 boston kernel: pci 0000:00:1c.0:   bridge window [mem 0xfff00000-0x000fffff] (disabled)
2011-02-09T08:59:37.423756+08:00 boston kernel: pci 0000:00:1c.0:   bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
2011-02-09T08:59:37.423758+08:00 boston kernel: pci 0000:00:1c.3: PCI bridge to [bus 05-0c]
2011-02-09T08:59:37.423759+08:00 boston kernel: pci 0000:00:1c.3:   bridge window [io  0x2000-0x2fff]
2011-02-09T08:59:37.423761+08:00 boston kernel: pci 0000:00:1c.3:   bridge window [mem 0xf0000000-0xf1ffffff]
2011-02-09T08:59:37.423762+08:00 boston kernel: pci 0000:00:1c.3:   bridge window [mem 0xf2800000-0xf28fffff 64bit pref]
2011-02-09T08:59:37.423766+08:00 boston kernel: pci 0000:02:00.0: [8086:4239] type 0 class 0x000280
2011-02-09T08:59:37.423767+08:00 boston kernel: pci 0000:02:00.0: reg 10: [mem 0xf2400000-0xf2401fff 64bit]
2011-02-09T08:59:37.423769+08:00 boston kernel: pci 0000:02:00.0: PME# supported from D0 D3hot D3cold
2011-02-09T08:59:37.423770+08:00 boston kernel: pci 0000:02:00.0: PME# disabled
2011-02-09T08:59:37.423772+08:00 boston kernel: pci 0000:00:1c.4: PCI bridge to [bus 02-02]
2011-02-09T08:59:37.423773+08:00 boston kernel: pci 0000:00:1c.4:   bridge window [io  0xf000-0x0000] (disabled)
2011-02-09T08:59:37.423775+08:00 boston kernel: pci 0000:00:1c.4:   bridge window [mem 0xf2400000-0xf24fffff]
2011-02-09T08:59:37.423776+08:00 boston kernel: pci 0000:00:1c.4:   bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
2011-02-09T08:59:37.423780+08:00 boston kernel: pci 0000:00:1e.0: PCI bridge to [bus 0e-0e] (subtractive decode)
2011-02-09T08:59:37.423782+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [io  0xf000-0x0000] (disabled)
2011-02-09T08:59:37.423783+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem 0xfff00000-0x000fffff] (disabled)
2011-02-09T08:59:37.423785+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
2011-02-09T08:59:37.423919+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [io  0x0000-0x0cf7] (subtractive decode)
2011-02-09T08:59:37.423921+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [io  0x0d00-0xffff] (subtractive decode)
2011-02-09T08:59:37.423923+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem 0x000a0000-0x000bffff] (subtractive decode)
2011-02-09T08:59:37.423924+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem 0x000d0000-0x000d3fff] (subtractive decode)
2011-02-09T08:59:37.423926+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem 0x000d4000-0x000d7fff] (subtractive decode)
2011-02-09T08:59:37.423928+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem 0x000d8000-0x000dbfff] (subtractive decode)
2011-02-09T08:59:37.423930+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem 0xc0000000-0xfebfffff] (subtractive decode)
2011-02-09T08:59:37.423931+08:00 boston kernel: ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
2011-02-09T08:59:37.423932+08:00 boston kernel: ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.EXP1._PRT]
2011-02-09T08:59:37.423934+08:00 boston kernel: ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.EXP4._PRT]
2011-02-09T08:59:37.423951+08:00 boston kernel: ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.EXP5._PRT]
2011-02-09T08:59:37.423953+08:00 boston kernel: ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 9 10 *11)
2011-02-09T08:59:37.423955+08:00 boston kernel: ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 9 10 *11)
2011-02-09T08:59:37.423956+08:00 boston kernel: ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 9 10 11) *0, disabled.
2011-02-09T08:59:37.423958+08:00 boston kernel: ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 9 10 *11)
2011-02-09T08:59:37.423959+08:00 boston kernel: ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 9 10 *11)
2011-02-09T08:59:37.423961+08:00 boston kernel: ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 9 10 11) *0, disabled.
2011-02-09T08:59:37.423963+08:00 boston kernel: ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 9 10 11) *0, disabled.
2011-02-09T08:59:37.423964+08:00 boston kernel: ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 9 10 *11)
2011-02-09T08:59:37.423966+08:00 boston kernel: vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none
2011-02-09T08:59:37.423967+08:00 boston kernel: vgaarb: loaded
2011-02-09T08:59:37.423969+08:00 boston kernel: SCSI subsystem initialized
2011-02-09T08:59:37.423970+08:00 boston kernel: libata version 3.00 loaded.
2011-02-09T08:59:37.423971+08:00 boston kernel: usbcore: registered new interface driver usbfs
2011-02-09T08:59:37.423973+08:00 boston kernel: usbcore: registered new interface driver hub
2011-02-09T08:59:37.423974+08:00 boston kernel: usbcore: registered new device driver usb
2011-02-09T08:59:37.423976+08:00 boston kernel: Advanced Linux Sound Architecture Driver Version 1.0.23.
2011-02-09T08:59:37.423978+08:00 boston kernel: PCI: Using ACPI for IRQ routing
2011-02-09T08:59:37.423981+08:00 boston kernel: PCI: pci_cache_line_size set to 64 bytes
2011-02-09T08:59:37.423983+08:00 boston kernel: reserve RAM buffer: 000000000009e800 - 000000000009ffff 
2011-02-09T08:59:37.423986+08:00 boston kernel: reserve RAM buffer: 00000000bb27c000 - 00000000bbffffff 
2011-02-09T08:59:37.423989+08:00 boston kernel: reserve RAM buffer: 00000000bb35f000 - 00000000bbffffff 
2011-02-09T08:59:37.423992+08:00 boston kernel: reserve RAM buffer: 00000000bb46f000 - 00000000bbffffff 
2011-02-09T08:59:37.423994+08:00 boston kernel: reserve RAM buffer: 00000000bb717000 - 00000000bbffffff 
2011-02-09T08:59:37.423997+08:00 boston kernel: reserve RAM buffer: 00000000bb76b000 - 00000000bbffffff 
2011-02-09T08:59:37.424000+08:00 boston kernel: reserve RAM buffer: 00000000bb800000 - 00000000bbffffff 
2011-02-09T08:59:37.424002+08:00 boston kernel: Switching to clocksource hpet
2011-02-09T08:59:37.424004+08:00 boston kernel: pnp: PnP ACPI init
2011-02-09T08:59:37.424006+08:00 boston kernel: ACPI: bus type pnp registered
2011-02-09T08:59:37.424009+08:00 boston kernel: pnp 00:00: [mem 0x00000000-0x0009ffff]
2011-02-09T08:59:37.424012+08:00 boston kernel: pnp 00:00: [mem 0x000c0000-0x000c3fff]
2011-02-09T08:59:37.424014+08:00 boston kernel: pnp 00:00: [mem 0x000c4000-0x000c7fff]
2011-02-09T08:59:37.424017+08:00 boston kernel: pnp 00:00: [mem 0x000c8000-0x000cbfff]
2011-02-09T08:59:37.424019+08:00 boston kernel: pnp 00:00: [mem 0x000cc000-0x000cffff]
2011-02-09T08:59:37.424022+08:00 boston kernel: pnp 00:00: [mem 0x000d0000-0x000cffff disabled]
2011-02-09T08:59:37.424025+08:00 boston kernel: pnp 00:00: [mem 0x000d4000-0x000d3fff disabled]
2011-02-09T08:59:37.424028+08:00 boston kernel: pnp 00:00: [mem 0x000d8000-0x000d7fff disabled]
2011-02-09T08:59:37.424030+08:00 boston kernel: pnp 00:00: [mem 0x000dc000-0x000dffff]
2011-02-09T08:59:37.424033+08:00 boston kernel: pnp 00:00: [mem 0x000e0000-0x000e3fff]
2011-02-09T08:59:37.424035+08:00 boston kernel: pnp 00:00: [mem 0x000e4000-0x000e7fff]
2011-02-09T08:59:37.424038+08:00 boston kernel: pnp 00:00: [mem 0x000e8000-0x000ebfff]
2011-02-09T08:59:37.424040+08:00 boston kernel: pnp 00:00: [mem 0x000ec000-0x000effff]
2011-02-09T08:59:37.424043+08:00 boston kernel: pnp 00:00: [mem 0x000f0000-0x000fffff]
2011-02-09T08:59:37.424046+08:00 boston kernel: pnp 00:00: [mem 0x00100000-0xbfffffff]
2011-02-09T08:59:37.424048+08:00 boston kernel: pnp 00:00: [mem 0xfec00000-0xfed3ffff]
2011-02-09T08:59:37.424051+08:00 boston kernel: pnp 00:00: [mem 0xfed4c000-0xffffffff]
2011-02-09T08:59:37.424054+08:00 boston kernel: system 00:00: [mem 0x00000000-0x0009ffff] could not be reserved
2011-02-09T08:59:37.424068+08:00 boston kernel: system 00:00: [mem 0x000c0000-0x000c3fff] has been reserved
2011-02-09T08:59:37.424072+08:00 boston kernel: system 00:00: [mem 0x000c4000-0x000c7fff] has been reserved
2011-02-09T08:59:37.424075+08:00 boston kernel: system 00:00: [mem 0x000c8000-0x000cbfff] has been reserved
2011-02-09T08:59:37.424078+08:00 boston kernel: system 00:00: [mem 0x000cc000-0x000cffff] has been reserved
2011-02-09T08:59:37.424081+08:00 boston kernel: system 00:00: [mem 0x000dc000-0x000dffff] could not be reserved
2011-02-09T08:59:37.424084+08:00 boston kernel: system 00:00: [mem 0x000e0000-0x000e3fff] could not be reserved
2011-02-09T08:59:37.424087+08:00 boston kernel: system 00:00: [mem 0x000e4000-0x000e7fff] could not be reserved
2011-02-09T08:59:37.424090+08:00 boston kernel: system 00:00: [mem 0x000e8000-0x000ebfff] could not be reserved
2011-02-09T08:59:37.424092+08:00 boston kernel: system 00:00: [mem 0x000ec000-0x000effff] could not be reserved
2011-02-09T08:59:37.424095+08:00 boston kernel: system 00:00: [mem 0x000f0000-0x000fffff] could not be reserved
2011-02-09T08:59:37.424098+08:00 boston kernel: system 00:00: [mem 0x00100000-0xbfffffff] could not be reserved
2011-02-09T08:59:37.424101+08:00 boston kernel: system 00:00: [mem 0xfec00000-0xfed3ffff] could not be reserved
2011-02-09T08:59:37.424103+08:00 boston kernel: system 00:00: [mem 0xfed4c000-0xffffffff] could not be reserved
2011-02-09T08:59:37.424106+08:00 boston kernel: system 00:00: Plug and Play ACPI device, IDs PNP0c01 (active)
2011-02-09T08:59:37.424108+08:00 boston kernel: pnp 00:01: [bus ff]
2011-02-09T08:59:37.424111+08:00 boston kernel: pnp 00:01: Plug and Play ACPI device, IDs PNP0a03 (active)
2011-02-09T08:59:37.424113+08:00 boston kernel: pnp 00:02: [bus 00-fe]
2011-02-09T08:59:37.424249+08:00 boston kernel: pnp 00:02: [io  0x0cf8-0x0cff]
2011-02-09T08:59:37.424252+08:00 boston kernel: pnp 00:02: [io  0x0000-0x0cf7 window]
2011-02-09T08:59:37.424253+08:00 boston kernel: pnp 00:02: [io  0x0d00-0xffff window]
2011-02-09T08:59:37.424254+08:00 boston kernel: pnp 00:02: [mem 0x000a0000-0x000bffff window]
2011-02-09T08:59:37.424256+08:00 boston kernel: pnp 00:02: [mem 0x000c0000-0x000c3fff window]
2011-02-09T08:59:37.424257+08:00 boston kernel: pnp 00:02: [mem 0x000c4000-0x000c7fff window]
2011-02-09T08:59:37.424258+08:00 boston kernel: pnp 00:02: [mem 0x000c8000-0x000cbfff window]
2011-02-09T08:59:37.424260+08:00 boston kernel: pnp 00:02: [mem 0x000cc000-0x000cffff window]
2011-02-09T08:59:37.424261+08:00 boston kernel: pnp 00:02: [mem 0x000d0000-0x000d3fff window]
2011-02-09T08:59:37.424262+08:00 boston kernel: pnp 00:02: [mem 0x000d4000-0x000d7fff window]
2011-02-09T08:59:37.424264+08:00 boston kernel: pnp 00:02: [mem 0x000d8000-0x000dbfff window]
2011-02-09T08:59:37.424265+08:00 boston kernel: pnp 00:02: [mem 0x000dc000-0x000dffff window]
2011-02-09T08:59:37.424266+08:00 boston kernel: pnp 00:02: [mem 0x000e0000-0x000e3fff window]
2011-02-09T08:59:37.424268+08:00 boston kernel: pnp 00:02: [mem 0x000e4000-0x000e7fff window]
2011-02-09T08:59:37.424269+08:00 boston kernel: pnp 00:02: [mem 0x000e8000-0x000ebfff window]
2011-02-09T08:59:37.424270+08:00 boston kernel: pnp 00:02: [mem 0x000ec000-0x000effff window]
2011-02-09T08:59:37.424272+08:00 boston kernel: pnp 00:02: [mem 0xc0000000-0xfebfffff window]
2011-02-09T08:59:37.424273+08:00 boston kernel: pnp 00:02: [mem 0xfed40000-0xfed4bfff window]
2011-02-09T08:59:37.424274+08:00 boston kernel: pnp 00:02: Plug and Play ACPI device, IDs PNP0a08 PNP0a03 (active)
2011-02-09T08:59:37.424276+08:00 boston kernel: pnp 00:03: [io  0x0010-0x001f]
2011-02-09T08:59:37.424277+08:00 boston kernel: pnp 00:03: [io  0x0090-0x009f]
2011-02-09T08:59:37.424278+08:00 boston kernel: pnp 00:03: [io  0x0024-0x0025]
2011-02-09T08:59:37.424279+08:00 boston kernel: pnp 00:03: [io  0x0028-0x0029]
2011-02-09T08:59:37.424281+08:00 boston kernel: pnp 00:03: [io  0x002c-0x002d]
2011-02-09T08:59:37.424282+08:00 boston kernel: pnp 00:03: [io  0x0030-0x0031]
2011-02-09T08:59:37.424283+08:00 boston kernel: pnp 00:03: [io  0x0034-0x0035]
2011-02-09T08:59:37.424284+08:00 boston kernel: pnp 00:03: [io  0x0038-0x0039]
2011-02-09T08:59:37.424286+08:00 boston kernel: pnp 00:03: [io  0x003c-0x003d]
2011-02-09T08:59:37.424287+08:00 boston kernel: pnp 00:03: [io  0x00a4-0x00a5]
2011-02-09T08:59:37.424288+08:00 boston kernel: pnp 00:03: [io  0x00a8-0x00a9]
2011-02-09T08:59:37.424289+08:00 boston kernel: pnp 00:03: [io  0x00ac-0x00ad]
2011-02-09T08:59:37.424301+08:00 boston kernel: pnp 00:03: [io  0x00b0-0x00b5]
2011-02-09T08:59:37.424303+08:00 boston kernel: pnp 00:03: [io  0x00b8-0x00b9]
2011-02-09T08:59:37.424305+08:00 boston kernel: pnp 00:03: [io  0x00bc-0x00bd]
2011-02-09T08:59:37.424306+08:00 boston kernel: pnp 00:03: [io  0x0050-0x0053]
2011-02-09T08:59:37.424307+08:00 boston kernel: pnp 00:03: [io  0x0072-0x0077]
2011-02-09T08:59:37.424308+08:00 boston kernel: pnp 00:03: [io  0x164e-0x164f]
2011-02-09T08:59:37.424310+08:00 boston kernel: pnp 00:03: [io  0x002e-0x002f]
2011-02-09T08:59:37.424311+08:00 boston kernel: pnp 00:03: [io  0x1000-0x107f]
2011-02-09T08:59:37.424312+08:00 boston kernel: pnp 00:03: [io  0x1180-0x11ff]
2011-02-09T08:59:37.424313+08:00 boston kernel: pnp 00:03: [io  0x0800-0x080f]
2011-02-09T08:59:37.424315+08:00 boston kernel: pnp 00:03: [io  0x15e0-0x15ef]
2011-02-09T08:59:37.424316+08:00 boston kernel: pnp 00:03: [io  0x1600-0x1641]
2011-02-09T08:59:37.424317+08:00 boston kernel: pnp 00:03: [io  0x1644-0x167f]
2011-02-09T08:59:37.424319+08:00 boston kernel: pnp 00:03: [mem 0xe0000000-0xefffffff]
2011-02-09T08:59:37.424320+08:00 boston kernel: pnp 00:03: [mem 0xfeaff000-0xfeafffff]
2011-02-09T08:59:37.424321+08:00 boston kernel: pnp 00:03: [mem 0xfed1c000-0xfed1ffff]
2011-02-09T08:59:37.424323+08:00 boston kernel: pnp 00:03: [mem 0xfed10000-0xfed13fff]
2011-02-09T08:59:37.424324+08:00 boston kernel: pnp 00:03: [mem 0xfed18000-0xfed18fff]
2011-02-09T08:59:37.424325+08:00 boston kernel: pnp 00:03: [mem 0xfed19000-0xfed19fff]
2011-02-09T08:59:37.424327+08:00 boston kernel: pnp 00:03: [mem 0xfed45000-0xfed4bfff]
2011-02-09T08:59:37.424328+08:00 boston kernel: system 00:03: [io  0x164e-0x164f] has been reserved
2011-02-09T08:59:37.424330+08:00 boston kernel: system 00:03: [io  0x1000-0x107f] has been reserved
2011-02-09T08:59:37.424331+08:00 boston kernel: system 00:03: [io  0x1180-0x11ff] has been reserved
2011-02-09T08:59:37.424333+08:00 boston kernel: system 00:03: [io  0x0800-0x080f] has been reserved
2011-02-09T08:59:37.424334+08:00 boston kernel: system 00:03: [io  0x15e0-0x15ef] has been reserved
2011-02-09T08:59:37.424336+08:00 boston kernel: system 00:03: [io  0x1600-0x1641] has been reserved
2011-02-09T08:59:37.424337+08:00 boston kernel: system 00:03: [io  0x1644-0x167f] could not be reserved
2011-02-09T08:59:37.424339+08:00 boston kernel: system 00:03: [mem 0xe0000000-0xefffffff] has been reserved
2011-02-09T08:59:37.424340+08:00 boston kernel: system 00:03: [mem 0xfeaff000-0xfeafffff] has been reserved
2011-02-09T08:59:37.424342+08:00 boston kernel: system 00:03: [mem 0xfed1c000-0xfed1ffff] has been reserved
2011-02-09T08:59:37.424344+08:00 boston kernel: system 00:03: [mem 0xfed10000-0xfed13fff] has been reserved
2011-02-09T08:59:37.424345+08:00 boston kernel: system 00:03: [mem 0xfed18000-0xfed18fff] has been reserved
2011-02-09T08:59:37.424347+08:00 boston kernel: system 00:03: [mem 0xfed19000-0xfed19fff] has been reserved
2011-02-09T08:59:37.424348+08:00 boston kernel: system 00:03: [mem 0xfed45000-0xfed4bfff] has been reserved
2011-02-09T08:59:37.424350+08:00 boston kernel: system 00:03: Plug and Play ACPI device, IDs PNP0c02 (active)
2011-02-09T08:59:37.424351+08:00 boston kernel: pnp 00:04: [mem 0xfed00000-0xfed003ff]
2011-02-09T08:59:37.424353+08:00 boston kernel: pnp 00:04: Plug and Play ACPI device, IDs PNP0103 (active)
2011-02-09T08:59:37.424354+08:00 boston kernel: pnp 00:05: [io  0x0000-0x000f]
2011-02-09T08:59:37.424356+08:00 boston kernel: pnp 00:05: [io  0x0080-0x008f]
2011-02-09T08:59:37.424357+08:00 boston kernel: pnp 00:05: [io  0x00c0-0x00df]
2011-02-09T08:59:37.424358+08:00 boston kernel: pnp 00:05: [dma 4]
2011-02-09T08:59:37.424360+08:00 boston kernel: pnp 00:05: Plug and Play ACPI device, IDs PNP0200 (active)
2011-02-09T08:59:37.424361+08:00 boston kernel: pnp 00:06: [io  0x0061]
2011-02-09T08:59:37.424362+08:00 boston kernel: pnp 00:06: Plug and Play ACPI device, IDs PNP0800 (active)
2011-02-09T08:59:37.424364+08:00 boston kernel: pnp 00:07: [io  0x00f0]
2011-02-09T08:59:37.424365+08:00 boston kernel: pnp 00:07: [irq 13]
2011-02-09T08:59:37.424366+08:00 boston kernel: pnp 00:07: Plug and Play ACPI device, IDs PNP0c04 (active)
2011-02-09T08:59:37.424368+08:00 boston kernel: pnp 00:08: [io  0x0070-0x0071]
2011-02-09T08:59:37.424369+08:00 boston kernel: pnp 00:08: [irq 8]
2011-02-09T08:59:37.424381+08:00 boston kernel: pnp 00:08: Plug and Play ACPI device, IDs PNP0b00 (active)
2011-02-09T08:59:37.424383+08:00 boston kernel: pnp 00:09: [io  0x0060]
2011-02-09T08:59:37.424384+08:00 boston kernel: pnp 00:09: [io  0x0064]
2011-02-09T08:59:37.424385+08:00 boston kernel: pnp 00:09: [irq 1]
2011-02-09T08:59:37.424387+08:00 boston kernel: pnp 00:09: Plug and Play ACPI device, IDs PNP0303 (active)
2011-02-09T08:59:37.424388+08:00 boston kernel: pnp 00:0a: [irq 12]
2011-02-09T08:59:37.424390+08:00 boston kernel: pnp 00:0a: Plug and Play ACPI device, IDs LEN0018 PNP0f13 (active)
2011-02-09T08:59:37.424391+08:00 boston kernel: Switched to NOHz mode on CPU #0
2011-02-09T08:59:37.424392+08:00 boston kernel: pnp 00:0b: [mem 0xfed40000-0xfed44fff]
2011-02-09T08:59:37.424394+08:00 boston kernel: Switched to NOHz mode on CPU #2
2011-02-09T08:59:37.424395+08:00 boston kernel: Switched to NOHz mode on CPU #3
2011-02-09T08:59:37.424397+08:00 boston kernel: pnp 00:0b: Plug and Play ACPI device, IDs SMO1200 PNP0c31 (active)
2011-02-09T08:59:37.424398+08:00 boston kernel: Switched to NOHz mode on CPU #1
2011-02-09T08:59:37.424399+08:00 boston kernel: pnp: PnP ACPI: found 12 devices
2011-02-09T08:59:37.424547+08:00 boston kernel: ACPI: ACPI bus type pnp unregistered
2011-02-09T08:59:37.424551+08:00 boston kernel: pci 0000:00:1c.0: PCI bridge to [bus 0d-0d]
2011-02-09T08:59:37.424553+08:00 boston kernel: pci 0000:00:1c.0:   bridge window [io  disabled]
2011-02-09T08:59:37.424555+08:00 boston kernel: pci 0000:00:1c.0:   bridge window [mem disabled]
2011-02-09T08:59:37.424556+08:00 boston kernel: pci 0000:00:1c.0:   bridge window [mem pref disabled]
2011-02-09T08:59:37.424558+08:00 boston kernel: pci 0000:00:1c.3: PCI bridge to [bus 05-0c]
2011-02-09T08:59:37.424559+08:00 boston kernel: pci 0000:00:1c.3:   bridge window [io  0x2000-0x2fff]
2011-02-09T08:59:37.424561+08:00 boston kernel: pci 0000:00:1c.3:   bridge window [mem 0xf0000000-0xf1ffffff]
2011-02-09T08:59:37.424562+08:00 boston kernel: pci 0000:00:1c.3:   bridge window [mem 0xf2800000-0xf28fffff 64bit pref]
2011-02-09T08:59:37.424564+08:00 boston kernel: pci 0000:00:1c.4: PCI bridge to [bus 02-02]
2011-02-09T08:59:37.424565+08:00 boston kernel: pci 0000:00:1c.4:   bridge window [io  disabled]
2011-02-09T08:59:37.424566+08:00 boston kernel: pci 0000:00:1c.4:   bridge window [mem 0xf2400000-0xf24fffff]
2011-02-09T08:59:37.424568+08:00 boston kernel: pci 0000:00:1c.4:   bridge window [mem pref disabled]
2011-02-09T08:59:37.424569+08:00 boston kernel: pci 0000:00:1e.0: PCI bridge to [bus 0e-0e]
2011-02-09T08:59:37.424571+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [io  disabled]
2011-02-09T08:59:37.424572+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem disabled]
2011-02-09T08:59:37.424574+08:00 boston kernel: pci 0000:00:1e.0:   bridge window [mem pref disabled]
2011-02-09T08:59:37.424575+08:00 boston kernel: pci 0000:00:1c.0: PCI INT A -> GSI 20 (level, low) -> IRQ 20
2011-02-09T08:59:37.424577+08:00 boston kernel: pci 0000:00:1c.0: setting latency timer to 64
2011-02-09T08:59:37.424578+08:00 boston kernel: pci 0000:00:1c.3: PCI INT D -> GSI 23 (level, low) -> IRQ 23
2011-02-09T08:59:37.424579+08:00 boston kernel: pci 0000:00:1c.3: setting latency timer to 64
2011-02-09T08:59:37.424581+08:00 boston kernel: pci 0000:00:1c.4: PCI INT A -> GSI 20 (level, low) -> IRQ 20
2011-02-09T08:59:37.424582+08:00 boston kernel: pci 0000:00:1c.4: setting latency timer to 64
2011-02-09T08:59:37.424583+08:00 boston kernel: pci 0000:00:1e.0: setting latency timer to 64
2011-02-09T08:59:37.424585+08:00 boston kernel: pci_bus 0000:00: resource 4 [io  0x0000-0x0cf7]
2011-02-09T08:59:37.424586+08:00 boston kernel: pci_bus 0000:00: resource 5 [io  0x0d00-0xffff]
2011-02-09T08:59:37.424588+08:00 boston kernel: pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff]
2011-02-09T08:59:37.424589+08:00 boston kernel: pci_bus 0000:00: resource 7 [mem 0x000d0000-0x000d3fff]
2011-02-09T08:59:37.424591+08:00 boston kernel: pci_bus 0000:00: resource 8 [mem 0x000d4000-0x000d7fff]
2011-02-09T08:59:37.424592+08:00 boston kernel: pci_bus 0000:00: resource 9 [mem 0x000d8000-0x000dbfff]
2011-02-09T08:59:37.424594+08:00 boston kernel: pci_bus 0000:00: resource 10 [mem 0xc0000000-0xfebfffff]
2011-02-09T08:59:37.424595+08:00 boston kernel: pci_bus 0000:05: resource 0 [io  0x2000-0x2fff]
2011-02-09T08:59:37.424596+08:00 boston kernel: pci_bus 0000:05: resource 1 [mem 0xf0000000-0xf1ffffff]
2011-02-09T08:59:37.424598+08:00 boston kernel: pci_bus 0000:05: resource 2 [mem 0xf2800000-0xf28fffff 64bit pref]
2011-02-09T08:59:37.424610+08:00 boston kernel: pci_bus 0000:02: resource 1 [mem 0xf2400000-0xf24fffff]
2011-02-09T08:59:37.424612+08:00 boston kernel: pci_bus 0000:0e: resource 4 [io  0x0000-0x0cf7]
2011-02-09T08:59:37.424614+08:00 boston kernel: pci_bus 0000:0e: resource 5 [io  0x0d00-0xffff]
2011-02-09T08:59:37.424615+08:00 boston kernel: pci_bus 0000:0e: resource 6 [mem 0x000a0000-0x000bffff]
2011-02-09T08:59:37.424617+08:00 boston kernel: pci_bus 0000:0e: resource 7 [mem 0x000d0000-0x000d3fff]
2011-02-09T08:59:37.424619+08:00 boston kernel: pci_bus 0000:0e: resource 8 [mem 0x000d4000-0x000d7fff]
2011-02-09T08:59:37.424620+08:00 boston kernel: pci_bus 0000:0e: resource 9 [mem 0x000d8000-0x000dbfff]
2011-02-09T08:59:37.424621+08:00 boston kernel: pci_bus 0000:0e: resource 10 [mem 0xc0000000-0xfebfffff]
2011-02-09T08:59:37.424623+08:00 boston kernel: NET: Registered protocol family 2
2011-02-09T08:59:37.424624+08:00 boston kernel: IP route cache hash table entries: 262144 (order: 9, 2097152 bytes)
2011-02-09T08:59:37.424626+08:00 boston kernel: TCP established hash table entries: 524288 (order: 11, 8388608 bytes)
2011-02-09T08:59:37.424627+08:00 boston kernel: TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
2011-02-09T08:59:37.424629+08:00 boston kernel: TCP: Hash tables configured (established 524288 bind 65536)
2011-02-09T08:59:37.424630+08:00 boston kernel: TCP reno registered
2011-02-09T08:59:37.424632+08:00 boston kernel: UDP hash table entries: 4096 (order: 5, 131072 bytes)
2011-02-09T08:59:37.424633+08:00 boston kernel: UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes)
2011-02-09T08:59:37.424634+08:00 boston kernel: NET: Registered protocol family 1
2011-02-09T08:59:37.424636+08:00 boston kernel: pci 0000:00:02.0: Boot video device
2011-02-09T08:59:37.424637+08:00 boston kernel: PCI: CLS 64 bytes, default 64
2011-02-09T08:59:37.424638+08:00 boston kernel: PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
2011-02-09T08:59:37.424640+08:00 boston kernel: Placing 64MB software IO TLB between ffff8800b6e7a000 - ffff8800bae7a000
2011-02-09T08:59:37.424641+08:00 boston kernel: software IO TLB at phys 0xb6e7a000 - 0xbae7a000
2011-02-09T08:59:37.424643+08:00 boston kernel: Simple Boot Flag at 0x35 set to 0x1
2011-02-09T08:59:37.424644+08:00 boston kernel: NTFS driver 2.1.30 [Flags: R/W].
2011-02-09T08:59:37.424645+08:00 boston kernel: fuse init (API version 7.16)
2011-02-09T08:59:37.424646+08:00 boston kernel: Btrfs loaded
2011-02-09T08:59:37.424648+08:00 boston kernel: msgmni has been set to 15604
2011-02-09T08:59:37.424649+08:00 boston kernel: Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)
2011-02-09T08:59:37.424651+08:00 boston kernel: io scheduler noop registered (default)
2011-02-09T08:59:37.424652+08:00 boston kernel: pci_hotplug: PCI Hot Plug PCI Core version: 0.5
2011-02-09T08:59:37.424654+08:00 boston kernel: pciehp: PCI Express Hot Plug Controller Driver version: 0.4
2011-02-09T08:59:37.424655+08:00 boston kernel: acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
2011-02-09T08:59:37.424656+08:00 boston kernel: acpiphp: Slot [1] registered
2011-02-09T08:59:37.424658+08:00 boston kernel: ACPI: Deprecated procfs I/F for AC is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared
2011-02-09T08:59:37.424660+08:00 boston kernel: ACPI: AC Adapter [AC] (off-line)
2011-02-09T08:59:37.424661+08:00 boston kernel: input: Lid Switch as /devices/LNXSYSTM:00/device:00/PNP0C0D:00/input/input0
2011-02-09T08:59:37.424663+08:00 boston kernel: ACPI: Lid Switch [LID]
2011-02-09T08:59:37.424664+08:00 boston kernel: input: Sleep Button as /devices/LNXSYSTM:00/device:00/PNP0C0E:00/input/input1
2011-02-09T08:59:37.424666+08:00 boston kernel: ACPI: Sleep Button [SLPB]
2011-02-09T08:59:37.424667+08:00 boston kernel: input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2
2011-02-09T08:59:37.424668+08:00 boston kernel: ACPI: Power Button [PWRF]
2011-02-09T08:59:37.424670+08:00 boston kernel: ACPI: acpi_idle registered with cpuidle
2011-02-09T08:59:37.424803+08:00 boston kernel: Monitor-Mwait will be used to enter C-1 state
2011-02-09T08:59:37.424807+08:00 boston kernel: Monitor-Mwait will be used to enter C-2 state
2011-02-09T08:59:37.424808+08:00 boston kernel: Monitor-Mwait will be used to enter C-3 state
2011-02-09T08:59:37.424810+08:00 boston kernel: thermal LNXTHERM:00: registered as thermal_zone0
2011-02-09T08:59:37.424811+08:00 boston kernel: ACPI: Thermal Zone [THM0] (58 C)
2011-02-09T08:59:37.424813+08:00 boston kernel: ERST: Table is not found!
2011-02-09T08:59:37.424814+08:00 boston kernel: GHES: HEST is not enabled!
2011-02-09T08:59:37.424816+08:00 boston kernel: ACPI: Deprecated procfs I/F for battery is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared
2011-02-09T08:59:37.424818+08:00 boston kernel: ACPI: Battery Slot [BAT0] (battery present)
2011-02-09T08:59:37.424820+08:00 boston kernel: Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
2011-02-09T08:59:37.424821+08:00 boston kernel: Non-volatile memory driver v1.3
2011-02-09T08:59:37.424822+08:00 boston kernel: Linux agpgart interface v0.103
2011-02-09T08:59:37.424824+08:00 boston kernel: agpgart-intel 0000:00:00.0: Intel HD Graphics Chipset
2011-02-09T08:59:37.424825+08:00 boston kernel: agpgart-intel 0000:00:00.0: detected gtt size: 524288K total, 262144K mappable
2011-02-09T08:59:37.424827+08:00 boston kernel: agpgart-intel 0000:00:00.0: detected 32768K stolen memory
2011-02-09T08:59:37.424828+08:00 boston kernel: agpgart-intel 0000:00:00.0: AGP aperture is 256M @ 0xd0000000
2011-02-09T08:59:37.424829+08:00 boston kernel: brd: module loaded
2011-02-09T08:59:37.424831+08:00 boston kernel: loop: module loaded
2011-02-09T08:59:37.424832+08:00 boston kernel: megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)
2011-02-09T08:59:37.424834+08:00 boston kernel: megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)
2011-02-09T08:59:37.424835+08:00 boston kernel: megasas: 00.00.05.29-rc1 Tue. Dec. 7 17:00:00 PDT 2010
2011-02-09T08:59:37.424836+08:00 boston kernel: mpt2sas version 07.100.00.00 loaded
2011-02-09T08:59:37.424838+08:00 boston kernel: ahci 0000:00:1f.2: version 3.0
2011-02-09T08:59:37.424844+08:00 boston kernel: ahci 0000:00:1f.2: PCI INT B -> GSI 16 (level, low) -> IRQ 16
2011-02-09T08:59:37.424846+08:00 boston kernel: ahci 0000:00:1f.2: irq 40 for MSI/MSI-X
2011-02-09T08:59:37.424847+08:00 boston kernel: ahci: SSS flag set, parallel bus scan disabled
2011-02-09T08:59:37.424849+08:00 boston kernel: ahci 0000:00:1f.2: AHCI 0001.0300 32 slots 6 ports 3 Gbps 0x31 impl SATA mode
2011-02-09T08:59:37.424851+08:00 boston kernel: ahci 0000:00:1f.2: flags: 64bit ncq sntf stag pm led clo pmp pio slum part ems sxs apst 
2011-02-09T08:59:37.424852+08:00 boston kernel: ahci 0000:00:1f.2: setting latency timer to 64
2011-02-09T08:59:37.424854+08:00 boston kernel: scsi0 : ahci
2011-02-09T08:59:37.424855+08:00 boston kernel: scsi1 : ahci
2011-02-09T08:59:37.424856+08:00 boston kernel: scsi2 : ahci
2011-02-09T08:59:37.424857+08:00 boston kernel: scsi3 : ahci
2011-02-09T08:59:37.424858+08:00 boston kernel: scsi4 : ahci
2011-02-09T08:59:37.424860+08:00 boston kernel: scsi5 : ahci
2011-02-09T08:59:37.424861+08:00 boston kernel: ata1: SATA max UDMA/133 abar m2048@0xf2727000 port 0xf2727100 irq 40
2011-02-09T08:59:37.424862+08:00 boston kernel: ata2: DUMMY
2011-02-09T08:59:37.424863+08:00 boston kernel: ata3: DUMMY
2011-02-09T08:59:37.424864+08:00 boston kernel: ata4: DUMMY
2011-02-09T08:59:37.424866+08:00 boston kernel: ata5: SATA max UDMA/133 abar m2048@0xf2727000 port 0xf2727300 irq 40
2011-02-09T08:59:37.424867+08:00 boston kernel: ata6: SATA max UDMA/133 abar m2048@0xf2727000 port 0xf2727380 irq 40
2011-02-09T08:59:37.424869+08:00 boston kernel: Intel(R) Gigabit Ethernet Network Driver - version 2.1.0-k2
2011-02-09T08:59:37.424870+08:00 boston kernel: Copyright (c) 2007-2009 Intel Corporation.
2011-02-09T08:59:37.424872+08:00 boston kernel: ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 3.0.12-k2
2011-02-09T08:59:37.424873+08:00 boston kernel: ixgbe: Copyright (c) 1999-2010 Intel Corporation.
2011-02-09T08:59:37.424875+08:00 boston kernel: pcnet32: pcnet32.c:v1.35 21.Apr.2008 tsbogend@alpha.franken.de
2011-02-09T08:59:37.424876+08:00 boston kernel: PPP generic driver version 2.4.2
2011-02-09T08:59:37.424877+08:00 boston kernel: PPP Deflate Compression module registered
2011-02-09T08:59:37.424879+08:00 boston kernel: PPP BSD Compression module registered
2011-02-09T08:59:37.424880+08:00 boston kernel: tun: Universal TUN/TAP device driver, 1.6
2011-02-09T08:59:37.424888+08:00 boston kernel: tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
2011-02-09T08:59:37.424890+08:00 boston kernel: Fusion MPT base driver 3.04.17
2011-02-09T08:59:37.424892+08:00 boston kernel: Copyright (c) 1999-2008 LSI Corporation
2011-02-09T08:59:37.424893+08:00 boston kernel: Fusion MPT SPI Host driver 3.04.17
2011-02-09T08:59:37.424895+08:00 boston kernel: Fusion MPT SAS Host driver 3.04.17
2011-02-09T08:59:37.424896+08:00 boston kernel: ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
2011-02-09T08:59:37.424898+08:00 boston kernel: ehci_hcd 0000:00:1a.0: power state changed by ACPI to D0
2011-02-09T08:59:37.424899+08:00 boston kernel: ehci_hcd 0000:00:1a.0: power state changed by ACPI to D0
2011-02-09T08:59:37.424901+08:00 boston kernel: ehci_hcd 0000:00:1a.0: PCI INT D -> GSI 23 (level, low) -> IRQ 23
2011-02-09T08:59:37.424902+08:00 boston kernel: ehci_hcd 0000:00:1a.0: setting latency timer to 64
2011-02-09T08:59:37.424903+08:00 boston kernel: ehci_hcd 0000:00:1a.0: EHCI Host Controller
2011-02-09T08:59:37.424905+08:00 boston kernel: ehci_hcd 0000:00:1a.0: new USB bus registered, assigned bus number 1
2011-02-09T08:59:37.424907+08:00 boston kernel: Refined TSC clocksource calibration: 2127.999 MHz.
2011-02-09T08:59:37.424908+08:00 boston kernel: Switching to clocksource tsc
2011-02-09T08:59:37.424909+08:00 boston kernel: ehci_hcd 0000:00:1a.0: debug port 2
2011-02-09T08:59:37.424911+08:00 boston kernel: ehci_hcd 0000:00:1a.0: cache line size of 64 is not supported
2011-02-09T08:59:37.424912+08:00 boston kernel: ehci_hcd 0000:00:1a.0: irq 23, io mem 0xf2728000
2011-02-09T08:59:37.424914+08:00 boston kernel: ehci_hcd 0000:00:1a.0: USB 2.0 started, EHCI 1.00
2011-02-09T08:59:37.424915+08:00 boston kernel: hub 1-0:1.0: USB hub found
2011-02-09T08:59:37.424916+08:00 boston kernel: hub 1-0:1.0: 3 ports detected
2011-02-09T08:59:37.424918+08:00 boston kernel: ehci_hcd 0000:00:1d.0: power state changed by ACPI to D0
2011-02-09T08:59:37.424919+08:00 boston kernel: ehci_hcd 0000:00:1d.0: power state changed by ACPI to D0
2011-02-09T08:59:37.424921+08:00 boston kernel: ehci_hcd 0000:00:1d.0: PCI INT D -> GSI 19 (level, low) -> IRQ 19
2011-02-09T08:59:37.424922+08:00 boston kernel: ehci_hcd 0000:00:1d.0: setting latency timer to 64
2011-02-09T08:59:37.424923+08:00 boston kernel: ehci_hcd 0000:00:1d.0: EHCI Host Controller
2011-02-09T08:59:37.424925+08:00 boston kernel: ehci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 2
2011-02-09T08:59:37.424926+08:00 boston kernel: ehci_hcd 0000:00:1d.0: debug port 2
2011-02-09T08:59:37.424928+08:00 boston kernel: ehci_hcd 0000:00:1d.0: cache line size of 64 is not supported
2011-02-09T08:59:37.424929+08:00 boston kernel: ehci_hcd 0000:00:1d.0: irq 19, io mem 0xf2728400
2011-02-09T08:59:37.424931+08:00 boston kernel: ehci_hcd 0000:00:1d.0: USB 2.0 started, EHCI 1.00
2011-02-09T08:59:37.424932+08:00 boston kernel: hub 2-0:1.0: USB hub found
2011-02-09T08:59:37.424933+08:00 boston kernel: hub 2-0:1.0: 3 ports detected
2011-02-09T08:59:37.424935+08:00 boston kernel: ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
2011-02-09T08:59:37.424936+08:00 boston kernel: uhci_hcd: USB Universal Host Controller Interface driver
2011-02-09T08:59:37.425071+08:00 boston kernel: i8042: PNP: PS/2 Controller [PNP0303:KBD,PNP0f13:MOU] at 0x60,0x64 irq 1,12
2011-02-09T08:59:37.425077+08:00 boston kernel: serio: i8042 KBD port at 0x60,0x64 irq 1
2011-02-09T08:59:37.425080+08:00 boston kernel: serio: i8042 AUX port at 0x60,0x64 irq 12
2011-02-09T08:59:37.425083+08:00 boston kernel: mousedev: PS/2 mouse device common for all mice
2011-02-09T08:59:37.425086+08:00 boston kernel: input: PC Speaker as /devices/platform/pcspkr/input/input3
2011-02-09T08:59:37.425089+08:00 boston kernel: rtc_cmos 00:08: RTC can wake from S4
2011-02-09T08:59:37.425092+08:00 boston kernel: input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input4
2011-02-09T08:59:37.425095+08:00 boston kernel: rtc_cmos 00:08: rtc core: registered rtc_cmos as rtc0
2011-02-09T08:59:37.425102+08:00 boston kernel: rtc0: alarms up to one month, y3k, 114 bytes nvram, hpet irqs
2011-02-09T08:59:37.425105+08:00 boston kernel: lirc_dev: IR Remote Control driver registered, major 251 
2011-02-09T08:59:37.425108+08:00 boston kernel: IR RC5 (streamzap) protocol handler initialized
2011-02-09T08:59:37.425110+08:00 boston kernel: IR LIRC bridge handler initialized
2011-02-09T08:59:37.425113+08:00 boston kernel: Linux video capture interface: v2.00
2011-02-09T08:59:37.425115+08:00 boston kernel: coretemp coretemp.0: TjMax is 105 C.
2011-02-09T08:59:37.425123+08:00 boston kernel: coretemp coretemp.2: TjMax is 105 C.
2011-02-09T08:59:37.425127+08:00 boston kernel: device-mapper: ioctl: 4.19.1-ioctl (2011-01-07) initialised: dm-devel@redhat.com
2011-02-09T08:59:37.425129+08:00 boston kernel: EDAC MC: Ver: 2.1.0 Feb  7 2011
2011-02-09T08:59:37.425131+08:00 boston kernel: cpuidle: using governor ladder
2011-02-09T08:59:37.425134+08:00 boston kernel: cpuidle: using governor menu
2011-02-09T08:59:37.425136+08:00 boston kernel: thinkpad_acpi: ThinkPad ACPI Extras v0.24
2011-02-09T08:59:37.425143+08:00 boston kernel: thinkpad_acpi: http://ibm-acpi.sf.net/
2011-02-09T08:59:37.425147+08:00 boston kernel: thinkpad_acpi: ThinkPad BIOS 6QET62WW (1.32 ), EC 6QHT31WW-1.12
2011-02-09T08:59:37.425150+08:00 boston kernel: thinkpad_acpi: Lenovo ThinkPad X201s, model 5413FGA
2011-02-09T08:59:37.425153+08:00 boston kernel: thinkpad_acpi: detected a 8-level brightness capable ThinkPad
2011-02-09T08:59:37.425156+08:00 boston kernel: thinkpad_acpi: rfkill switch tpacpi_bluetooth_sw: radio is blocked
2011-02-09T08:59:37.425159+08:00 boston kernel: Registered led device: tpacpi::thinklight
2011-02-09T08:59:37.425168+08:00 boston kernel: Registered led device: tpacpi::power
2011-02-09T08:59:37.425172+08:00 boston kernel: Registered led device: tpacpi::standby
2011-02-09T08:59:37.425175+08:00 boston kernel: Registered led device: tpacpi::thinkvantage
2011-02-09T08:59:37.425178+08:00 boston kernel: thinkpad_acpi: volume: disabled as there is no ALSA support in this kernel
2011-02-09T08:59:37.425181+08:00 boston kernel: input: ThinkPad Extra Buttons as /devices/platform/thinkpad_acpi/input/input5
2011-02-09T08:59:37.425185+08:00 boston kernel: HDA Intel 0000:00:1b.0: PCI INT B -> GSI 17 (level, low) -> IRQ 17
2011-02-09T08:59:37.425187+08:00 boston kernel: HDA Intel 0000:00:1b.0: irq 41 for MSI/MSI-X
2011-02-09T08:59:37.425190+08:00 boston kernel: HDA Intel 0000:00:1b.0: setting latency timer to 64
2011-02-09T08:59:37.425193+08:00 boston kernel: ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
2011-02-09T08:59:37.425196+08:00 boston kernel: ata1.00: ACPI cmd ef/02:00:00:00:00:a0 (unknown) succeeded
2011-02-09T08:59:37.425199+08:00 boston kernel: ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (unknown) filtered out
2011-02-09T08:59:37.425205+08:00 boston kernel: ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (unknown) filtered out
2011-02-09T08:59:37.425209+08:00 boston kernel: ata1.00: ATA-7: SAMSUNG SSD PM800 2.5" 256GB, VBM25D1Q, max UDMA/100
2011-02-09T08:59:37.425212+08:00 boston kernel: ata1.00: 500118192 sectors, multi 16: LBA48 NCQ (depth 31/32), AA
2011-02-09T08:59:37.425214+08:00 boston kernel: ata1.00: ACPI cmd ef/02:00:00:00:00:a0 (unknown) succeeded
2011-02-09T08:59:37.425216+08:00 boston kernel: ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (unknown) filtered out
2011-02-09T08:59:37.425218+08:00 boston kernel: ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (unknown) filtered out
2011-02-09T08:59:37.425219+08:00 boston kernel: ata1.00: configured for UDMA/100
2011-02-09T08:59:37.425221+08:00 boston kernel: scsi 0:0:0:0: Direct-Access     ATA      SAMSUNG SSD PM80 VBM2 PQ: 0 ANSI: 5
2011-02-09T08:59:37.425227+08:00 boston kernel: sd 0:0:0:0: [sda] 500118192 512-byte logical blocks: (256 GB/238 GiB)
2011-02-09T08:59:37.425229+08:00 boston kernel: sd 0:0:0:0: [sda] Write Protect is off
2011-02-09T08:59:37.425230+08:00 boston kernel: sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
2011-02-09T08:59:37.425232+08:00 boston kernel: sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
2011-02-09T08:59:37.425234+08:00 boston kernel: sd 0:0:0:0: Attached scsi generic sg0 type 0
2011-02-09T08:59:37.425236+08:00 boston kernel: sda: sda1 sda2 sda3 sda4 < sda5 sda6 sda7 sda8 sda9 sda10 sda11 sda12 sda13 sda14 sda15 >
2011-02-09T08:59:37.425237+08:00 boston kernel: sd 0:0:0:0: [sda] Attached SCSI disk
2011-02-09T08:59:37.425239+08:00 boston kernel: hda-codec: No codec parser is available
2011-02-09T08:59:37.425240+08:00 boston kernel: ALSA device list:
2011-02-09T08:59:37.425241+08:00 boston kernel:  #0: HDA Intel at 0xf2520000 irq 41
2011-02-09T08:59:37.425243+08:00 boston kernel: Netfilter messages via NETLINK v0.30.
2011-02-09T08:59:37.425244+08:00 boston kernel: nf_conntrack version 0.5.0 (16384 buckets, 65536 max)
2011-02-09T08:59:37.425246+08:00 boston kernel: ctnetlink v0.93: registering with nfnetlink.
2011-02-09T08:59:37.425247+08:00 boston kernel: ip_tables: (C) 2000-2006 Netfilter Core Team
2011-02-09T08:59:37.425248+08:00 boston kernel: arp_tables: (C) 2002 David S. Miller
2011-02-09T08:59:37.425249+08:00 boston kernel: TCP bic registered
2011-02-09T08:59:37.425251+08:00 boston kernel: TCP cubic registered
2011-02-09T08:59:37.425252+08:00 boston kernel: TCP highspeed registered
2011-02-09T08:59:37.425253+08:00 boston kernel: NET: Registered protocol family 17
2011-02-09T08:59:37.425260+08:00 boston kernel: lib80211: common routines for IEEE802.11 drivers
2011-02-09T08:59:37.425262+08:00 boston kernel: lib80211_crypt: registered algorithm 'NULL'
2011-02-09T08:59:37.425264+08:00 boston kernel: rtc_cmos 00:08: setting system clock to 2011-02-09 00:59:35 UTC (1297213175)
2011-02-09T08:59:37.425265+08:00 boston kernel: hub 1-1:1.0: USB hub found
2011-02-09T08:59:37.425266+08:00 boston kernel: hub 1-1:1.0: 6 ports detected
2011-02-09T08:59:37.425268+08:00 boston kernel: ata5: SATA link down (SStatus 0 SControl 300)
2011-02-09T08:59:37.425269+08:00 boston kernel: IBM TrackPoint firmware: 0x0e, buttons: 3/3
2011-02-09T08:59:37.425271+08:00 boston kernel: input: TPPS/2 IBM TrackPoint as /devices/platform/i8042/serio1/input/input6
2011-02-09T08:59:37.425273+08:00 boston kernel: hub 2-1:1.0: USB hub found
2011-02-09T08:59:37.425274+08:00 boston kernel: hub 2-1:1.0: 8 ports detected
2011-02-09T08:59:37.425275+08:00 boston kernel: ata6: SATA link down (SStatus 0 SControl 300)
2011-02-09T08:59:37.425277+08:00 boston kernel: VFS: Mounted root (reiserfs filesystem) readonly on device 8:2.
2011-02-09T08:59:37.425278+08:00 boston kernel: Freeing unused kernel memory: 576k freed
2011-02-09T08:59:37.425281+08:00 boston kernel: Adding 8290300k swap on /dev/sda3.  Priority:-1 extents:1 across:8290300k SS
2011-02-09T08:59:37.983094+08:00 boston kernel: [drm] Initialized drm 1.1.0 20060810
2011-02-09T08:59:38.003102+08:00 boston kernel: i915 0000:00:02.0: power state changed by ACPI to D0
2011-02-09T08:59:38.003129+08:00 boston kernel: i915 0000:00:02.0: power state changed by ACPI to D0
2011-02-09T08:59:38.003135+08:00 boston kernel: i915 0000:00:02.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
2011-02-09T08:59:38.003139+08:00 boston kernel: i915 0000:00:02.0: setting latency timer to 64
2011-02-09T08:59:38.093096+08:00 boston kernel: i915 0000:00:02.0: irq 42 for MSI/MSI-X
2011-02-09T08:59:38.093124+08:00 boston kernel: [drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
2011-02-09T08:59:38.093128+08:00 boston kernel: [drm] Driver supports precise vblank timestamp query.
2011-02-09T08:59:38.183735+08:00 boston kernel: vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem
2011-02-09T08:59:38.273096+08:00 boston kernel: Console: switching to colour frame buffer device 180x56
2011-02-09T08:59:38.273125+08:00 boston kernel: fb0: inteldrmfb frame buffer device
2011-02-09T08:59:38.273129+08:00 boston kernel: drm: registered panic notifier
2011-02-09T08:59:38.273132+08:00 boston kernel: No ACPI video bus found
2011-02-09T08:59:38.273136+08:00 boston kernel: [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Indan Zupancic]

On Wed, February 9, 2011 02:05, Jeff Chua wrote:
> On Wed, Feb 9, 2011 at 8:55 AM, Jeff Chua <jeff.chua.linux@gmail.com> wrote:
>
>> And the console hangs even without starting X.
>
> I went back to retry suspending without starting X and realized that
> it's only the "screen" that's hang .. and that's without drm and i915
> loaded.

According to the dmesg you sent, you do have drm (and probably i915 too) loaded.
It seems the hang is the first bit, and then you rebooted into X to capture the
log.

Perhaps relevant message (probably not):

"No ACPI video bus found"

> On the console, I could still reboot the machine normally, but
> not when in X (everything hangs including keybard).
>
> Here's the kernel log without X.
>
> Thanks.
> Jeff
>

Looking at the commit, all it does is changing the timing.

It used to set active to true when intel_crtc_init() was called, but now
it does it always when the drm reset() callback is called.

intel_crtc->active = true; /* force the pipe off on setup_init_config */

I can't find a setup_init_config anywhere, but looking at the other code
it assumes that *_crtc_disable() will be called just after the forced true.

All in all it seems quite wrong, no matter if it happens to work, because
it depends on the calling order done by the drm layer. If *_crtc_enable()
is called instead it won't do anything because of that active = true thing.
This seems to be happening in your case.

So I'd get rid of that dodgy active = true assignment altogether. Isn't
the introduction of the reset() callback done to avoid exactly this kind
of subtle state fiddling? And removing it might solve the original problem
that the move tried to fix as well.

I can't check the rest of the code as I'm still on patched 37 (won't move
till the fix for bug 23472 is upstream), but my gut feeling is that removing
that weird active = true will solve most problems.

Greetings,

Indan

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Jeff Chua]

On Wed, Feb 9, 2011 at 10:56 AM, Indan Zupancic <indan@nul.nu> wrote:
> On Wed, February 9, 2011 02:05, Jeff Chua wrote:
>> On Wed, Feb 9, 2011 at 8:55 AM, Jeff Chua <jeff.chua.linux@gmail.com> wrote:
>>
>>> And the console hangs even without starting X.
>>
>> I went back to retry suspending without starting X and realized that
>> it's only the "screen" that's hang .. and that's without drm and i915
>> loaded.
>
> According to the dmesg you sent, you do have drm (and probably i915 too) loaded.
> It seems the hang is the first bit, and then you rebooted into X to capture the
> log.
>
> Perhaps relevant message (probably not):
>
> "No ACPI video bus found"
>
>> On the console, I could still reboot the machine normally, but
>> not when in X (everything hangs including keybard).
>>
>> Here's the kernel log without X.
>>
>> Thanks.
>> Jeff
>>
>
> Looking at the commit, all it does is changing the timing.
>
> It used to set active to true when intel_crtc_init() was called, but now
> it does it always when the drm reset() callback is called.
>
> intel_crtc->active = true; /* force the pipe off on setup_init_config */
>
> I can't find a setup_init_config anywhere, but looking at the other code
> it assumes that *_crtc_disable() will be called just after the forced true.
>
> All in all it seems quite wrong, no matter if it happens to work, because
> it depends on the calling order done by the drm layer. If *_crtc_enable()
> is called instead it won't do anything because of that active = true thing.
> This seems to be happening in your case.
>
> So I'd get rid of that dodgy active = true assignment altogether. Isn't
> the introduction of the reset() callback done to avoid exactly this kind
> of subtle state fiddling? And removing it might solve the original problem
> that the move tried to fix as well.
>
> I can't check the rest of the code as I'm still on patched 37 (won't move
> till the fix for bug 23472 is upstream), but my gut feeling is that removing
> that weird active = true will solve most problems.

This may help a little. I added printk("intel_crtc 2") inside
intel_crtc_reset() and added printk("intel_crtc 1") before calling
intel_crtc_reset().

Looking at  dmesg, it looks like something else is calling
intel_crtc_reset() and not from intel_crtc_init() during resume.

intel_crtc 2 ffff880239cdf000
intel_crtc 2 ffff880239cdf800


Jeff.

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Chris Wilson]

On Wed, 9 Feb 2011 03:56:36 +0100 (CET), "Indan Zupancic" <indan@nul.nu> wrote:
> All in all it seems quite wrong, no matter if it happens to work, because
> it depends on the calling order done by the drm layer. If *_crtc_enable()
> is called instead it won't do anything because of that active = true thing.
> This seems to be happening in your case.

The order is very well defined.

modesetting (upon resume we set the previous mode):
  for each enabled crtc:
    crtc_helper->prepare -> intel_crtc_disable()
    crtc->mode_set -> intel_crtc_mode_set() 
    crtc_helper->commit -> intel_crtc_enable()
  for each !enabled crtc:
    crtc->disable -> intel_crtc_disable()
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Indan Zupancic]

On Wed, February 9, 2011 06:45, Jeff Chua wrote:
>
> This may help a little. I added printk("intel_crtc 2") inside
> intel_crtc_reset() and added printk("intel_crtc 1") before calling
> intel_crtc_reset().
>
> Looking at  dmesg, it looks like something else is calling
> intel_crtc_reset() and not from intel_crtc_init() during resume.

That something else is the drm layer.

(I must say it's very unclear what the the ordering of driver function
calls will be from just looking at drm the code. I hope the drm
abstraction is working out well for others, to me it all seems a bit
awkward. If state needs to be tracked, fine, but do it either in the
drm layer or let the driver handle it.)

> intel_crtc 2 ffff880239cdf000
> intel_crtc 2 ffff880239cdf800

This doesn't really help, all it probably means is that you've got
multiple crtc outputs, or something like that. It might help if you
get two calls with the offending commit, but only one without it.

I'd add printk's to the *_crtc_disable()/*_crtc_enable() calls with
info whether it actually enables or disables something and compare
the result between a working suspend and a broken one.

Greetings,

Indan

Re: Commit 500f7147cf5bafd139056d521536b10c2bc2e154 breaks _resume_

[Indan Zupancic]

On Wed, February 9, 2011 10:32, Chris Wilson wrote:
> On Wed, 9 Feb 2011 03:56:36 +0100 (CET), "Indan Zupancic" <indan@nul.nu> wrote:
>> All in all it seems quite wrong, no matter if it happens to work, because
>> it depends on the calling order done by the drm layer. If *_crtc_enable()
>> is called instead it won't do anything because of that active = true thing.
>> This seems to be happening in your case.
>
> The order is very well defined.
>
> modesetting (upon resume we set the previous mode):
>   for each enabled crtc:
>     crtc_helper->prepare -> intel_crtc_disable()
>     crtc->mode_set -> intel_crtc_mode_set()
>     crtc_helper->commit -> intel_crtc_enable()
>   for each !enabled crtc:
>     crtc->disable -> intel_crtc_disable()

Prepare for what? That could mean anything. Is it only used to
prepare changing a mode, or suspend, or what? Same for commit.
Should it have been named modes_set_prepare and mode_set_commit?

It's clear if you've worked a lot on the code, but if you're just
debugging it's had to tell when anything will be called, the
function pointer chasing isn't fun. And that doesn't guarantee
a driver function won't be called in a different way in the
future anyway.

I'd go as far as saying that if that's always the order, then
just get rid of prepare and commit and do what's needed in the
mode_set function. If prepare and commit don't have any other
purpose or reason for existence.

And back to the original thing, where does that reset() callback
fit in? It's absent from the very well defined order. And judging
by its name, it should be okay to call at any moment, but it seems
that isn't the case.

But the real wrong thing is fiddling with "active" outside of those
state changing functions to force a certain behaviour later on if a
specific function is called just after this (fingers crossed).

My advise is to just remove that active = true line and fix any
breakage that results in some other way. It acts as an out-of-band
message to *crtc_disable() to re-disable already disabled crtcs,
which doesn't always work (either now or in the future). If the state
wasn't already messed up, it is after doing the active = true thing.

Greetings,

Indan