* [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-01 2:26 Masayuki Ohtak
2010-09-01 2:43 ` Joe Perches
2010-09-01 19:44 ` Linus Walleij
0 siblings, 2 replies; 47+ messages in thread
From: Masayuki Ohtak @ 2010-09-01 2:26 UTC (permalink / raw)
To: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c, linux-kernel
Cc: Wang Yong Y", Wang Qi", Andrew",
arjan, Tomoya MORINAGA, Arnd Bergmann
I2C driver of Topcliff PCH
Topcliff PCH is the platform controller hub that is going to be used in
Intel's upcoming general embedded platform. All IO peripherals in
Topcliff PCH are actually devices sitting on AMBA bus.
Topcliff PCH has I2C I/F. Using this I/F, it is able to access system
devices connected to I2C.
Signed-off-by: Masayuki Ohtake <masa-korg@dsn.okisemi.com>
---
drivers/i2c/busses/Kconfig | 18 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-pch.c | 966 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 985 insertions(+), 0 deletions(-)
create mode 100644 drivers/i2c/busses/i2c-pch.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index bceafbf..c5db1e7 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -613,6 +613,24 @@ config I2C_XILINX
This driver can also be built as a module. If so, the module
will be called xilinx_i2c.
+config PCH_I2C
+ tristate "PCH I2C of Intel Topcliff"
+ depends on PCI
+ help
+ This driver is for PCH(Platform controller Hub) I2C of Topcliff which
+ is an IOH(Input/Output Hub) for x86 embedded processor.
+ This driver can access PCH I2C bus device.
+
+config PCH_I2C_CH_COUNT
+ int "PCH I2C the number of channel count"
+ range 1 2
+ depends on PCH_I2C
+ help
+ This driver is for PCH(Platform controller Hub) I2C of Topcliff which
+ is an IOH(Input/Output Hub) for x86 embedded processor.
+ The number of I2C buses/channels supported by the PCH I2C controller.
+ PCH I2C of Topcliff supports only one channel.
+
comment "External I2C/SMBus adapter drivers"
config I2C_PARPORT
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 936880b..aa04135 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
+obj-$(CONFIG_PCH_I2C) += i2c-pch.o
# External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o
diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c
new file mode 100644
index 0000000..fc1b6a0
--- /dev/null
+++ b/drivers/i2c/busses/i2c-pch.c
@@ -0,0 +1,966 @@
+/*
+ * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/pci.h>
+#include <linux/mutex.h>
+#include <linux/ktime.h>
+
+#define PCH_MAX_CHN CONFIG_PCH_I2C_CH_COUNT /* Maximum I2C channels
+ available */
+#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
+#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
+#define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
+#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
+#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
+
+#define PCH_I2CSADR 0x00 /* I2C slave address register */
+#define PCH_I2CCTL 0x04 /* I2C control register */
+#define PCH_I2CSR 0x08 /* I2C status register */
+#define PCH_I2CDR 0x0C /* I2C data register */
+#define PCH_I2CMON 0x10 /* I2C bus monitor register */
+#define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
+#define PCH_I2CMOD 0x18 /* I2C mode register */
+#define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
+#define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
+#define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
+#define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
+#define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
+#define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
+#define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
+#define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
+#define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
+#define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
+#define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
+#define PCH_I2CTMR 0x48 /* I2C timer register */
+#define PCH_I2CSRST 0xFC /* I2C reset register */
+#define PCH_I2CNF 0xF8 /* I2C noise filter register */
+
+#define BUS_IDLE_TIMEOUT 20
+#define PCH_I2CCTL_I2CMEN 0x0080
+#define TEN_BIT_ADDR_DEFAULT 0xF000
+#define TEN_BIT_ADDR_MASK 0xF0
+#define PCH_START 0x0020
+#define PCH_ESR_START 0x0001
+#define PCH_BUFF_START 0x1
+#define PCH_REPSTART 0x0004
+#define PCH_ACK 0x0008
+#define PCH_GETACK 0x0001
+#define CLR_REG 0x0
+#define I2C_RD 0x1
+#define I2CMCF_BIT 0x0080
+#define I2CMIF_BIT 0x0002
+#define I2CMAL_BIT 0x0010
+#define I2CBMFI_BIT 0x0001
+#define I2CBMAL_BIT 0x0002
+#define I2CBMNA_BIT 0x0004
+#define I2CBMTO_BIT 0x0008
+#define I2CBMIS_BIT 0x0010
+#define I2CESRFI_BIT 0X0001
+#define I2CESRTO_BIT 0x0002
+#define I2CESRFIIE_BIT 0x1
+#define I2CESRTOIE_BIT 0x2
+#define I2CBMDZ_BIT 0x0040
+#define I2CBMAG_BIT 0x0020
+#define I2CMBB_BIT 0x0020
+#define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
+ I2CBMTO_BIT | I2CBMIS_BIT)
+#define I2C_ADDR_MSK 0xFF
+#define I2C_MSB_2B_MSK 0x300
+#define FAST_MODE_CLK 400
+#define FAST_MODE_EN 0x0001
+#define SUB_ADDR_LEN_MAX 4
+#define BUF_LEN_MAX 32
+#define PCH_BUFFER_MODE 0x1
+#define EEPROM_SW_RST_MODE 0x0002
+#define NORMAL_INTR_ENBL 0x0300
+#define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
+#define EEPROM_RST_INTR_DISBL 0x0
+#define BUFFER_MODE_INTR_ENBL 0x001F
+#define BUFFER_MODE_INTR_DISBL 0x0
+#define NORMAL_MODE 0x0
+#define BUFFER_MODE 0x1
+#define EEPROM_SR_MODE 0x2
+#define I2C_TX_MODE 0x0010
+#define PCH_BUF_TX 0xFFF7
+#define PCH_BUF_RD 0x0008
+#define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
+ I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
+#define I2CMAL_EVENT 0x0001
+#define I2CMCF_EVENT 0x0002
+#define I2CBMFI_EVENT 0x0004
+#define I2CBMAL_EVENT 0x0008
+#define I2CBMNA_EVENT 0x0010
+#define I2CBMTO_EVENT 0x0020
+#define I2CBMIS_EVENT 0x0040
+#define I2CESRFI_EVENT 0x0080
+#define I2CESRTO_EVENT 0x0100
+
+#define MODULE_NAME "pch_i2c"
+#define PCI_DEVICE_ID_PCH_I2C 0x8817
+
+/**
+ * struct i2c_algo_pch_data - for I2C driver functionalities
+ * @p_adapter_info: stores the reference to adapter_info structure
+ * @pch_adapter: stores the reference to i2c_adapter structure
+ * @pch_base_address: specifies the remapped base address
+ * @pch_buff_mode_en: specifies if buffer mode is enabled
+ * @pch_event_flag: specifies occurrence of interrupt events
+ * @pch_xfer_in_progress: specifies whether the transfer is completed
+ */
+struct i2c_algo_pch_data {
+ struct adapter_info *p_adapter_info;
+ struct i2c_adapter pch_adapter;
+ void __iomem *pch_base_address;
+ int pch_buff_mode_en;
+ u32 pch_event_flag;
+ bool pch_xfer_in_progress;
+};
+
+/**
+ * struct adapter_info - This structure holds the adapter information for the
+ PCH i2c controller
+ * @pch_data: stores a list of i2c_algo_pch_data
+ * @pch_suspended: specifies whether the system is suspended or not
+ * perhaps with more lines and words.
+ *
+ * pch_data has as many elements as maximum I2C channels
+ */
+struct adapter_info {
+ struct i2c_algo_pch_data pch_data[PCH_MAX_CHN];
+ bool pch_suspended;
+};
+
+
+static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
+static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
+static wait_queue_head_t pch_event;
+static DEFINE_MUTEX(pch_mutex);
+
+static struct pci_device_id __devinitdata pch_pcidev_id[] = {
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_I2C)},
+ {0,}
+};
+
+static irqreturn_t pch_handler_ch0(int irq, void *pData);
+static irqreturn_t(*pch_handler_list[PCH_MAX_CHN]) (int irq, void *pData) = {
+ pch_handler_ch0,
+};
+
+static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ u32 val;
+ val = ioread32(addr + offset);
+ val |= bitmask;
+ iowrite32(val, addr + offset);
+}
+
+static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ u32 val;
+ val = ioread32(addr + offset);
+ val &= (~bitmask);
+ iowrite32(val, addr + offset);
+}
+
+/**
+ * pch_init() - hardware initialization of I2C module
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_init(struct i2c_algo_pch_data *adap)
+{
+ u32 pch_i2cbc;
+ u32 pch_i2ctmr;
+ u32 reg_value;
+ void __iomem *p = adap->pch_base_address;
+
+ /* reset I2C controller */
+ iowrite32(0x01, p + PCH_I2CSRST);
+ iowrite32(0x0, p + PCH_I2CSRST);
+ /* Initialize I2C registers */
+ iowrite32(CLR_REG, p + PCH_I2CCTL);
+ iowrite32(CLR_REG, p + PCH_I2CMOD);
+ iowrite32(CLR_REG, p + PCH_I2CBUFFOR);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSLV);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSUB);
+ iowrite32(CLR_REG, p + PCH_I2CBUFMSK);
+ iowrite32(CLR_REG, p + PCH_I2CESRFOR);
+ iowrite32(CLR_REG, p + PCH_I2CESRMSK);
+ iowrite32(0x21, p + PCH_I2CNF);
+
+ reg_value = PCH_I2CCTL_I2CMEN;
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL,
+ PCH_I2CCTL_I2CMEN);
+
+ if (pch_i2c_speed != 400)
+ pch_i2c_speed = 100;
+
+ if (pch_i2c_speed == FAST_MODE_CLK) {
+ reg_value |= FAST_MODE_EN;
+ dev_dbg(adap->pch_adapter.dev.parent, "Fast mode enabled\n");
+ }
+
+ if (pch_clk <= 0 || pch_clk > PCH_MAX_CLK)
+ pch_clk = 62500;
+
+ pch_i2cbc = ((pch_clk) + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
+ /* Set transfer speed in I2CBC */
+ iowrite32(pch_i2cbc, p + PCH_I2CBC);
+
+ pch_i2ctmr = (pch_clk) / 8;
+ iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
+
+ reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
+ iowrite32(reg_value, p + PCH_I2CCTL);
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s: I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
+ __func__, ioread32(p + PCH_I2CCTL),
+ pch_i2cbc, pch_i2ctmr);
+
+ init_waitqueue_head(&pch_event);
+}
+
+static inline int ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
+{
+ return cmp1.tv64 < cmp2.tv64;
+}
+
+/**
+ * pch_wait_for_bus_idle() - check the status of bus.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ * @timeout: waiting time counter (us).
+ */
+static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
+ s32 timeout)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ /* MAX timeout value is timeout*1000*1000nsec */
+ ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
+ do {
+ if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
+ break;
+ msleep(1);
+ } while (ktime_lt(ktime_get(), ns_val));
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s : I2CSR = %x\n", __func__, ioread32(p + PCH_I2CSR));
+
+ if (timeout == 0) {
+ dev_err(adap->pch_adapter.dev.parent,
+ "%s :return%d\n", __func__, -ETIME);
+ } else {
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s : return %d\n", __func__, 0);
+ }
+
+ return ((timeout <= 0) ? (-ETIME) : (0));
+}
+
+/**
+ * pch_start() - Generate I2C start condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ *
+ * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
+ */
+static void pch_start(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ dev_dbg(adap->pch_adapter.dev.parent, "In %s : I2CCTL = %x\n",
+ __func__, ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+}
+
+/**
+ * pch_wait_for_xfer_complete() - initiates a wait for the tx complete event
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
+{
+ s32 ret;
+ ret = wait_event_interruptible_timeout(pch_event,
+ (adap->pch_event_flag != 0), msecs_to_jiffies(50));
+ if (ret < 0)
+ goto out;
+
+ if (ret == 0) {
+ ret = -ETIMEDOUT;
+ goto out;
+ }
+
+ if (adap->pch_event_flag & I2C_ERROR_MASK) {
+ ret = -EIO;
+ dev_err(adap->pch_adapter.dev.parent,
+ "error bits set: %x\n", adap->pch_event_flag);
+ goto out;
+ }
+
+ adap->pch_event_flag = 0;
+ ret = 0;
+out:
+ return ret;
+}
+
+/**
+ * pch_getack() - to confirm ACK/NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_getack(struct i2c_algo_pch_data *adap)
+{
+ u32 reg_val;
+ void __iomem *p = adap->pch_base_address;
+ reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
+
+ if (reg_val == 0)
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : return 0\n",
+ __func__);
+ else
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : return%d\n",
+ __func__, -EPROTO);
+
+ return (((reg_val) == 0) ? (0) : (-EPROTO));
+}
+
+/**
+ * pch_stop() - generate stop condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_stop(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : I2CCTL = %x\n", __func__,
+ ioread32(p + PCH_I2CCTL));
+ /* clear the start bit */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+}
+
+/**
+ * pch_repstart() - generate repeated start condition in normal mode
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_repstart(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ dev_dbg(adap->pch_adapter.dev.parent, "In %s : I2CCTL = %x\n",
+ __func__, ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_REPSTART);
+}
+
+/**
+ * pch_writebytes() - write data to I2C bus in normal mode
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @last: specifies whether last message or not.
+ * In the case of compound mode it will be 1 for last message,
+ * otherwise 0.
+ * @first: specifies whether first message or not.
+ * 1 for first message otherwise 0.
+ */
+static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+ u8 *buf;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ u32 addr_8_lsb;
+ s32 wrcount;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+ /* enable master tx */
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s : I2CCTL = %x msgs->len = %d\n", __func__,
+ ioread32(p + PCH_I2CCTL), length);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ addr_8_lsb = (addr & I2C_ADDR_MSK);
+ iowrite32(addr_8_lsb, p + PCH_I2CDR);
+ } else {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } else {
+ /* set 7 bit slave address and R/W bit as 0 */
+ iowrite32(addr << 1, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ }
+
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ for (wrcount = 0; wrcount < length; ++wrcount) {
+ /* write buffer value to I2C data register */
+ iowrite32(buf[wrcount], p + PCH_I2CDR);
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s : writing %x to Data register\n",
+ __func__, buf[wrcount]);
+
+ if (pch_wait_for_xfer_complete(adap) != 0) {
+ wrcount = -ETIME;
+ break;
+ }
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s return %d", __func__, 0);
+
+ if (pch_getack(adap)) {
+ wrcount = -ETIME;
+ break;
+ }
+ }
+
+ /* check if this is the last message */
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+ } else {
+ pch_stop(adap);
+ }
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s return=%d\n", __func__, wrcount);
+
+ return wrcount;
+}
+
+/**
+ * pch_sendack() - send ACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : I2CCTL = %x\n", __func__,
+ ioread32(p + PCH_I2CCTL));
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+}
+
+/**
+ * pch_sendnack() - send NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendnack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : I2CCTL = %x\n", __func__,
+ ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+}
+
+/**
+ * pch_readbytes() - read data from I2C bus in normal mode.
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @last: specifies whether last message or not.
+ * @first: specifies whether first message or not.
+ */
+s32 pch_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ u8 *buf;
+ u32 count;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+
+ /* enable master reception */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+
+ } else {
+ /* 7 address bits + R/W bit */
+ addr = (((addr) << 1) | (I2C_RD));
+ iowrite32(addr, p + PCH_I2CDR);
+ }
+
+ /* check if it is the first message */
+ if (first)
+ pch_start(adap);
+
+ if ((pch_wait_for_xfer_complete(adap) == 0)
+ && (pch_getack(adap) == 0)) {
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s return %d", __func__, 0);
+
+ if (length == 0) {
+ pch_stop(adap);
+ ioread32(p + PCH_I2CDR); /* Dummy read needs */
+
+ count = length;
+ } else {
+ int read_index;
+ int loop;
+ pch_sendack(adap);
+
+ /* Dummy read */
+ for (loop = 1, read_index = 0; loop < length; loop++) {
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (loop != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) != 0) {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } /* end for */
+
+ pch_sendnack(adap);
+
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (length != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) == 0) {
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+
+ buf[read_index++] = ioread32(p + PCH_I2CDR);
+ count = read_index;
+ } else {
+ count = -ETIME;
+ }
+
+ }
+ } else {
+ count = -ETIME;
+ pch_stop(adap);
+ }
+
+ return count;
+}
+
+/**
+ * pch_cb_ch0() - Interrupt handler Call back function
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_cb_ch0(struct i2c_algo_pch_data *adap)
+{
+ u32 sts;
+ void __iomem *p = adap->pch_base_address;
+
+ sts = ioread32(p + PCH_I2CSR);
+ sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
+ if (I2CMAL_BIT & sts)
+ adap->pch_event_flag |= I2CMAL_EVENT;
+
+ if (I2CMCF_BIT & sts)
+ adap->pch_event_flag |= I2CMCF_EVENT;
+
+ /* clear the applicable bits */
+ pch_clrbit((adap->pch_base_address), PCH_I2CSR, sts);
+
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : PCH_I2CSR = %x\n",
+ __func__, ioread32(p + PCH_I2CSR));
+
+ wake_up_interruptible(&pch_event);
+}
+
+/**
+ * pch_handler_ch0() - interrupt handler for the PCH I2C controller
+ * @irq: irq number.
+ * @pData: cookie passed back to the handler function.
+ */
+static irqreturn_t pch_handler_ch0(int irq, void *pData)
+{
+ s32 reg_val;
+
+ struct i2c_algo_pch_data *adap_data = (struct i2c_algo_pch_data *)pData;
+ void __iomem *p = adap_data->pch_base_address;
+ u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE);
+
+ if (mode == NORMAL_MODE) {
+ reg_val = ioread32(p + PCH_I2CSR);
+ if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
+ pch_cb_ch0(adap_data);
+ else
+ goto err_out;
+ } else {
+ dev_err(adap_data->pch_adapter.dev.parent,
+ "%s I2C mode is not supported\n", __func__);
+ goto err_out;
+ }
+ return IRQ_HANDLED;
+
+err_out:
+ return IRQ_NONE;
+}
+
+/**
+ * pch_xfer() - Reading adnd writing data through I2C bus
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @num: number of messages.
+ */
+static s32 pch_xfer(struct i2c_adapter *i2c_adap,
+ struct i2c_msg *msgs, s32 num)
+{
+ struct i2c_msg *pmsg;
+ u32 i;
+ u32 status;
+ u32 msglen;
+ u32 subaddrlen;
+ s32 ret;
+
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ ret = mutex_lock_interruptible(&pch_mutex);
+ if (ret) {
+ ret = -ERESTARTSYS;
+ goto return_err_nomutex;
+ }
+ if (adap->p_adapter_info->pch_suspended == false) {
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s adap->p_adapter_info->pch_suspended is %d\n",
+ __func__, adap->p_adapter_info->pch_suspended);
+ /* transfer not completed */
+ adap->pch_xfer_in_progress = true;
+
+ ret = -EBUSY;
+ for (i = 0; i < num; i++) {
+ pmsg = &msgs[i];
+ pmsg->flags |= adap->pch_buff_mode_en;
+ status = pmsg->flags;
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "After invoking I2C_MODE_SEL :flag= 0x%x\n",
+ status);
+ /* calculate sub address length and message length */
+ /* these are applicable only for buffer mode */
+ subaddrlen = pmsg->buf[0];
+ /* calculate actual message length excluding
+ * the sub address fields */
+ msglen = (pmsg->len) - (subaddrlen + 1);
+ if (status & (I2C_M_RD)) {
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s invoking pch_readbytes\n",
+ __func__);
+ ret = pch_readbytes(i2c_adap, pmsg,
+ (i + 1 == num),
+ (i == 0));
+ } else {
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s invoking pch_writebytes\n",
+ __func__);
+ ret = pch_writebytes(i2c_adap, pmsg,
+ (i + 1 == num),
+ (i == 0));
+ }
+
+ }
+
+ adap->pch_xfer_in_progress = false; /* transfer completed */
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "adap->pch_xfer_in_progress is %d\n",
+ adap->pch_xfer_in_progress);
+ } else {
+ ret = -EBUSY;
+ }
+
+ mutex_unlock(&pch_mutex);
+return_err_nomutex:
+ dev_dbg(adap->pch_adapter.dev.parent, "%s return:%d\n\n\n\n",
+ __func__, ret);
+ return ret;
+}
+
+/**
+ * pch_func() - return the functionality of the I2C driver
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static u32 pch_func(struct i2c_adapter *adap)
+{
+ u32 ret;
+ ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
+ return ret;
+}
+
+static struct i2c_algorithm pch_algorithm = {
+ .master_xfer = pch_xfer,
+ .functionality = pch_func
+};
+
+/**
+ * pch_disbl_int() - Disable PCH I2C interrupts
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_disbl_int(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL,
+ NORMAL_INTR_ENBL);
+
+ iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
+
+ iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
+}
+
+static int __devinit pch_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ int i;
+ void __iomem *base_addr;
+ s32 ret;
+ struct adapter_info *adap_info =
+ kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
+
+ dev_dbg(&pdev->dev, "Enterred in %s\n", __func__);
+
+ if (adap_info == NULL) {
+ dev_err(&pdev->dev, "Memory allocation failed FAILED");
+ ret = -ENOMEM;
+ goto return_err;
+ }
+
+ ret = pci_enable_device(pdev);
+ if (ret) {
+ dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__);
+ goto err_pci_enable;
+ }
+
+ ret = pci_request_regions(pdev, MODULE_NAME);
+ if (ret) {
+ dev_err(&pdev->dev, "pci_request_regions FAILED");
+ goto err_pci_req;
+ }
+
+ base_addr = pci_iomap(pdev, 1, 0);
+
+ if (base_addr == 0) {
+ dev_err(&pdev->dev, "pci_iomap FAILED");
+ ret = -ENOMEM;
+ goto err_pci_iomap;
+ }
+
+ adap_info->pch_suspended = false;
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ adap_info->pch_data[i].p_adapter_info = adap_info;
+
+ adap_info->pch_data[i].pch_adapter.owner = THIS_MODULE;
+ adap_info->pch_data[i].pch_adapter.class = I2C_CLASS_HWMON;
+ strcpy(adap_info->pch_data[i].pch_adapter.name, "pch_i2c");
+ adap_info->pch_data[i].pch_adapter.algo = &pch_algorithm;
+ adap_info->pch_data[i].pch_adapter.algo_data =
+ &adap_info->pch_data[i];
+
+ /* (i * 0x80) + base_addr; */
+ adap_info->pch_data[i].pch_base_address = base_addr;
+
+ adap_info->pch_data[i].pch_adapter.dev.parent = &pdev->dev;
+
+ ret = i2c_add_adapter(&(adap_info->pch_data[i].pch_adapter));
+
+ if (ret) {
+ dev_err(&pdev->dev, "i2c_add_adapter FAILED");
+ goto err_i2c_add_adapter;
+ }
+
+ pch_init(&adap_info->pch_data[i]);
+ ret = request_irq(pdev->irq, pch_handler_list[i], IRQF_SHARED,
+ MODULE_NAME, &adap_info->pch_data[i]);
+ if (ret) {
+ dev_err(&pdev->dev, "request_irq Failed\n");
+ goto err_request_irq;
+ }
+ }
+
+ dev_dbg(&pdev->dev, "request_irq returns %d pch_probe returns.\n", ret);
+ pci_set_drvdata(pdev, adap_info);
+ return 0;
+
+err_request_irq:
+ for (i = 0; i < PCH_MAX_CHN; i++)
+ i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
+err_i2c_add_adapter:
+ pci_iounmap(pdev, base_addr);
+err_pci_iomap:
+ pci_release_regions(pdev);
+err_pci_req:
+ pci_disable_device(pdev);
+err_pci_enable:
+ kfree(adap_info);
+return_err:
+ return ret;
+}
+
+static void __devexit pch_remove(struct pci_dev *pdev)
+{
+ int i;
+
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ pch_disbl_int(&adap_info->pch_data[i]);
+ free_irq(pdev->irq, &adap_info->pch_data[i]);
+ i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
+ }
+
+ if (adap_info->pch_data[0].pch_base_address) {
+ pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
+ adap_info->pch_data[0].pch_base_address = 0;
+ }
+
+ pci_set_drvdata(pdev, NULL);
+
+ pci_release_regions(pdev);
+
+ pci_disable_device(pdev);
+ kfree(adap_info);
+}
+
+#ifdef CONFIG_PM
+static int pch_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ int i;
+ int ret;
+
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+ void __iomem *p = adap_info->pch_data[0].pch_base_address;
+
+ adap_info->pch_suspended = true;
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
+ /* It is assumed that any pending transfer will
+ * be completed after the delay
+ */
+ msleep(1);
+ }
+ /* Disable the i2c interrupts */
+ pch_disbl_int(&adap_info->pch_data[i]);
+ }
+
+ dev_dbg(&pdev->dev,
+ "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
+ "invoked function pch_disbl_int successfully\n",
+ ioread32(p + 0x08),
+ ioread32(p + 0x30),
+ ioread32(p + 0x44));
+
+ ret = pci_save_state(pdev);
+
+ if (ret) {
+ dev_err(&pdev->dev, "pci_save_state failed\n");
+ return ret;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+ pci_disable_device(pdev);
+ pci_set_power_state(pdev, pci_choose_state(pdev, state));
+
+ return 0;
+}
+
+static int pch_resume(struct pci_dev *pdev)
+{
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+ int i;
+
+ pci_set_power_state(pdev, PCI_D0);
+ pci_restore_state(pdev);
+
+ if (pci_enable_device(pdev) < 0) {
+ dev_err(&pdev->dev, "pci_enable_device failed in pch_resume\n");
+ return -EIO;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+
+ for (i = 0; i < PCH_MAX_CHN; i++)
+ pch_init(&adap_info->pch_data[i]);
+
+ adap_info->pch_suspended = false;
+
+ return 0;
+}
+#else
+#define pch_suspend NULL
+#define pch_resume NULL
+#endif
+
+static struct pci_driver pch_pcidriver = {
+ .name = "pch_i2c",
+ .id_table = pch_pcidev_id,
+ .probe = pch_probe,
+ .remove = __devexit_p(pch_remove),
+ .suspend = pch_suspend,
+ .resume = pch_resume
+};
+
+static int __init pch_pci_init(void)
+{
+ return pci_register_driver(&pch_pcidriver);
+}
+
+static void __exit pch_pci_exit(void)
+{
+ pci_unregister_driver(&pch_pcidriver);
+}
+
+MODULE_DESCRIPTION("PCH I2C PCI Driver");
+MODULE_LICENSE("GPL");
+module_init(pch_pci_init);
+module_exit(pch_pci_exit);
+module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
+module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
--
1.6.0.6
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-01 2:43 ` Joe Perches
0 siblings, 0 replies; 47+ messages in thread
From: Joe Perches @ 2010-09-01 2:43 UTC (permalink / raw)
To: Masayuki Ohtak
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c, linux-kernel, Wang Yong Y",
Wang Qi", Andrew",
arjan, Tomoya MORINAGA, Arnd Bergmann
On Wed, 2010-09-01 at 11:26 +0900, Masayuki Ohtak wrote:
> I2C driver of Topcliff PCH
> +++ b/drivers/i2c/busses/i2c-pch.c
[]
> +static void pch_init(struct i2c_algo_pch_data *adap)
[]
> + if (pch_i2c_speed == FAST_MODE_CLK) {
> + reg_value |= FAST_MODE_EN;
> + dev_dbg(adap->pch_adapter.dev.parent, "Fast mode enabled\n");
> + }
Just a suggestion below, ignore it at your pleasure...
These dev_<level> calls might be easier to read if you had
some #defines like:
#define pch_dbg(adap, fmt, arg...) \
dev_dbg(adap->pch_adapter.dev.parent, fmt, ##arg)
#define pch_err(adap, fmt, arg...) \
dev_err(adap->pch_adapter.dev.parent, fmt, ##arg)
#define pch_info(adap, fmt, arg...) \
dev_info(adap->pch_adapter.dev.parent, fmt, ##arg)
then the last dev_dbg becomes:
pch_dbg(adap, "Fast mode enabled\n");
Many modules use similar wrapper #defines.
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "%s: I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
> + __func__, ioread32(p + PCH_I2CCTL),
> + pch_i2cbc, pch_i2ctmr);
pch_dbg(adap, etc...)
etc.
cheers, Joe
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-01 2:43 ` Joe Perches
0 siblings, 0 replies; 47+ messages in thread
From: Joe Perches @ 2010-09-01 2:43 UTC (permalink / raw)
To: Masayuki Ohtak
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Wang Yong Y",
Wang Qi", Andrew",
arjan-VuQAYsv1563Yd54FQh9/CA, Tomoya MORINAGA, Arnd Bergmann
On Wed, 2010-09-01 at 11:26 +0900, Masayuki Ohtak wrote:
> I2C driver of Topcliff PCH
> +++ b/drivers/i2c/busses/i2c-pch.c
[]
> +static void pch_init(struct i2c_algo_pch_data *adap)
[]
> + if (pch_i2c_speed == FAST_MODE_CLK) {
> + reg_value |= FAST_MODE_EN;
> + dev_dbg(adap->pch_adapter.dev.parent, "Fast mode enabled\n");
> + }
Just a suggestion below, ignore it at your pleasure...
These dev_<level> calls might be easier to read if you had
some #defines like:
#define pch_dbg(adap, fmt, arg...) \
dev_dbg(adap->pch_adapter.dev.parent, fmt, ##arg)
#define pch_err(adap, fmt, arg...) \
dev_err(adap->pch_adapter.dev.parent, fmt, ##arg)
#define pch_info(adap, fmt, arg...) \
dev_info(adap->pch_adapter.dev.parent, fmt, ##arg)
then the last dev_dbg becomes:
pch_dbg(adap, "Fast mode enabled\n");
Many modules use similar wrapper #defines.
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "%s: I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
> + __func__, ioread32(p + PCH_I2CCTL),
> + pch_i2cbc, pch_i2ctmr);
pch_dbg(adap, etc...)
etc.
cheers, Joe
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
2010-09-01 2:43 ` Joe Perches
@ 2010-09-01 4:16 ` Masayuki Ohtake
-1 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtake @ 2010-09-01 4:16 UTC (permalink / raw)
To: Joe Perches
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c, linux-kernel, Wang Yong Y",
Wang Qi", Andrew",
arjan, Tomoya MORINAGA, Arnd Bergmann
Hi Joe,
Thank you for your comments.
We will update.
Thanks, Ohtake(OKISemi)
----- Original Message -----
From: "Joe Perches" <joe@perches.com>
To: "Masayuki Ohtak" <masa-korg@dsn.okisemi.com>
Cc: "Jean Delvare (PC drivers, core)" <khali@linux-fr.org>; "Ben Dooks (embedded platforms)" <ben-linux@fluff.org>;
"Crane Cai" <crane.cai@amd.com>; "Samuel Ortiz" <sameo@linux.intel.com>; "Linus Walleij" <linus.walleij@stericsson.com>;
"Ralf Baechle" <ralf@linux-mips.org>; "srinidhi kasagar" <srinidhi.kasagar@stericsson.com>; <linux-i2c@vger.kernel.org>;
<linux-kernel@vger.kernel.org>; "Wang Yong Y"" <yong.y.wang@intel.com>; "Wang Qi"" <qi.wang@intel.com>; "Andrew""
<andrew.chih.howe.khor@intel.com>; <arjan@linux.intel.com>; "Tomoya MORINAGA" <morinaga526@dsn.okisemi.com>; "Arnd
Bergmann" <arnd@arndb.de>
Sent: Wednesday, September 01, 2010 11:43 AM
Subject: Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
> On Wed, 2010-09-01 at 11:26 +0900, Masayuki Ohtak wrote:
> > I2C driver of Topcliff PCH
> > +++ b/drivers/i2c/busses/i2c-pch.c
> []
> > +static void pch_init(struct i2c_algo_pch_data *adap)
> []
> > + if (pch_i2c_speed == FAST_MODE_CLK) {
> > + reg_value |= FAST_MODE_EN;
> > + dev_dbg(adap->pch_adapter.dev.parent, "Fast mode enabled\n");
> > + }
>
> Just a suggestion below, ignore it at your pleasure...
>
> These dev_<level> calls might be easier to read if you had
> some #defines like:
>
> #define pch_dbg(adap, fmt, arg...) \
> dev_dbg(adap->pch_adapter.dev.parent, fmt, ##arg)
> #define pch_err(adap, fmt, arg...) \
> dev_err(adap->pch_adapter.dev.parent, fmt, ##arg)
> #define pch_info(adap, fmt, arg...) \
> dev_info(adap->pch_adapter.dev.parent, fmt, ##arg)
>
> then the last dev_dbg becomes:
>
> pch_dbg(adap, "Fast mode enabled\n");
>
> Many modules use similar wrapper #defines.
>
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "%s: I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
> > + __func__, ioread32(p + PCH_I2CCTL),
> > + pch_i2cbc, pch_i2ctmr);
>
> pch_dbg(adap, etc...)
>
> etc.
>
> cheers, Joe
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-01 4:16 ` Masayuki Ohtake
0 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtake @ 2010-09-01 4:16 UTC (permalink / raw)
To: Joe Perches
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Wang Yong Y",
Wang Qi", Andrew",
arjan-VuQAYsv1563Yd54FQh9/CA, Tomoya MORINAGA, Arnd Bergmann
Hi Joe,
Thank you for your comments.
We will update.
Thanks, Ohtake(OKISemi)
----- Original Message -----
From: "Joe Perches" <joe-6d6DIl74uiNBDgjK7y7TUQ@public.gmane.org>
To: "Masayuki Ohtak" <masa-korg-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>
Cc: "Jean Delvare (PC drivers, core)" <khali-PUYAD+kWke1g9hUCZPvPmw@public.gmane.org>; "Ben Dooks (embedded platforms)" <ben-linux-elnMNo+KYs3YtjvyW6yDsg@public.gmane.org>;
"Crane Cai" <crane.cai-5C7GfCeVMHo@public.gmane.org>; "Samuel Ortiz" <sameo-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>; "Linus Walleij" <linus.walleij-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>;
"Ralf Baechle" <ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>; "srinidhi kasagar" <srinidhi.kasagar-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>; <linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>;
<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>; "Wang Yong Y"" <yong.y.wang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>; "Wang Qi"" <qi.wang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>; "Andrew""
<andrew.chih.howe.khor-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>; <arjan-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>; "Tomoya MORINAGA" <morinaga526-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>; "Arnd
Bergmann" <arnd-r2nGTMty4D4@public.gmane.org>
Sent: Wednesday, September 01, 2010 11:43 AM
Subject: Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
> On Wed, 2010-09-01 at 11:26 +0900, Masayuki Ohtak wrote:
> > I2C driver of Topcliff PCH
> > +++ b/drivers/i2c/busses/i2c-pch.c
> []
> > +static void pch_init(struct i2c_algo_pch_data *adap)
> []
> > + if (pch_i2c_speed == FAST_MODE_CLK) {
> > + reg_value |= FAST_MODE_EN;
> > + dev_dbg(adap->pch_adapter.dev.parent, "Fast mode enabled\n");
> > + }
>
> Just a suggestion below, ignore it at your pleasure...
>
> These dev_<level> calls might be easier to read if you had
> some #defines like:
>
> #define pch_dbg(adap, fmt, arg...) \
> dev_dbg(adap->pch_adapter.dev.parent, fmt, ##arg)
> #define pch_err(adap, fmt, arg...) \
> dev_err(adap->pch_adapter.dev.parent, fmt, ##arg)
> #define pch_info(adap, fmt, arg...) \
> dev_info(adap->pch_adapter.dev.parent, fmt, ##arg)
>
> then the last dev_dbg becomes:
>
> pch_dbg(adap, "Fast mode enabled\n");
>
> Many modules use similar wrapper #defines.
>
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "%s: I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
> > + __func__, ioread32(p + PCH_I2CCTL),
> > + pch_i2cbc, pch_i2ctmr);
>
> pch_dbg(adap, etc...)
>
> etc.
>
> cheers, Joe
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
2010-09-01 2:43 ` Joe Perches
@ 2010-09-01 5:08 ` Masayuki Ohtake
-1 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtake @ 2010-09-01 5:08 UTC (permalink / raw)
To: Joe Perches
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c, linux-kernel, Wang Yong Y",
Wang Qi", Andrew",
arjan, Tomoya MORINAGA, Arnd Bergmann
Hi Joe,
I have a question.
Current our I2C driver has the following 2 patterns dev_err().
(1) dev_err(adap->pch_adapter.dev.parent, "...");
(2) dev_err(&pdev->dev, "...");
> #define pch_err(adap, fmt, arg...) \
> dev_err(adap->pch_adapter.dev.parent, fmt, ##arg)
In case of using the above code, pattern (1) can apply, but (2) can't.
As to (2),
Should we use as dev_err or define another macro?
Thanks, Ohtake(OKISemi)
----- Original Message -----
From: "Joe Perches" <joe@perches.com>
To: "Masayuki Ohtak" <masa-korg@dsn.okisemi.com>
Cc: "Jean Delvare (PC drivers, core)" <khali@linux-fr.org>; "Ben Dooks (embedded platforms)" <ben-linux@fluff.org>;
"Crane Cai" <crane.cai@amd.com>; "Samuel Ortiz" <sameo@linux.intel.com>; "Linus Walleij" <linus.walleij@stericsson.com>;
"Ralf Baechle" <ralf@linux-mips.org>; "srinidhi kasagar" <srinidhi.kasagar@stericsson.com>; <linux-i2c@vger.kernel.org>;
<linux-kernel@vger.kernel.org>; "Wang Yong Y"" <yong.y.wang@intel.com>; "Wang Qi"" <qi.wang@intel.com>; "Andrew""
<andrew.chih.howe.khor@intel.com>; <arjan@linux.intel.com>; "Tomoya MORINAGA" <morinaga526@dsn.okisemi.com>; "Arnd
Bergmann" <arnd@arndb.de>
Sent: Wednesday, September 01, 2010 11:43 AM
Subject: Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
> On Wed, 2010-09-01 at 11:26 +0900, Masayuki Ohtak wrote:
> > I2C driver of Topcliff PCH
> > +++ b/drivers/i2c/busses/i2c-pch.c
> []
> > +static void pch_init(struct i2c_algo_pch_data *adap)
> []
> > + if (pch_i2c_speed == FAST_MODE_CLK) {
> > + reg_value |= FAST_MODE_EN;
> > + dev_dbg(adap->pch_adapter.dev.parent, "Fast mode enabled\n");
> > + }
>
> Just a suggestion below, ignore it at your pleasure...
>
> These dev_<level> calls might be easier to read if you had
> some #defines like:
>
> #define pch_dbg(adap, fmt, arg...) \
> dev_dbg(adap->pch_adapter.dev.parent, fmt, ##arg)
> #define pch_err(adap, fmt, arg...) \
> dev_err(adap->pch_adapter.dev.parent, fmt, ##arg)
> #define pch_info(adap, fmt, arg...) \
> dev_info(adap->pch_adapter.dev.parent, fmt, ##arg)
>
> then the last dev_dbg becomes:
>
> pch_dbg(adap, "Fast mode enabled\n");
>
> Many modules use similar wrapper #defines.
>
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "%s: I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
> > + __func__, ioread32(p + PCH_I2CCTL),
> > + pch_i2cbc, pch_i2ctmr);
>
> pch_dbg(adap, etc...)
>
> etc.
>
> cheers, Joe
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-01 5:08 ` Masayuki Ohtake
0 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtake @ 2010-09-01 5:08 UTC (permalink / raw)
To: Joe Perches
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Wang Yong Y",
Wang Qi", Andrew",
arjan-VuQAYsv1563Yd54FQh9/CA, Tomoya MORINAGA, Arnd Bergmann
Hi Joe,
I have a question.
Current our I2C driver has the following 2 patterns dev_err().
(1) dev_err(adap->pch_adapter.dev.parent, "...");
(2) dev_err(&pdev->dev, "...");
> #define pch_err(adap, fmt, arg...) \
> dev_err(adap->pch_adapter.dev.parent, fmt, ##arg)
In case of using the above code, pattern (1) can apply, but (2) can't.
As to (2),
Should we use as dev_err or define another macro?
Thanks, Ohtake(OKISemi)
----- Original Message -----
From: "Joe Perches" <joe-6d6DIl74uiNBDgjK7y7TUQ@public.gmane.org>
To: "Masayuki Ohtak" <masa-korg-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>
Cc: "Jean Delvare (PC drivers, core)" <khali-PUYAD+kWke1g9hUCZPvPmw@public.gmane.org>; "Ben Dooks (embedded platforms)" <ben-linux-elnMNo+KYs3YtjvyW6yDsg@public.gmane.org>;
"Crane Cai" <crane.cai-5C7GfCeVMHo@public.gmane.org>; "Samuel Ortiz" <sameo-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>; "Linus Walleij" <linus.walleij-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>;
"Ralf Baechle" <ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>; "srinidhi kasagar" <srinidhi.kasagar-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>; <linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>;
<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>; "Wang Yong Y"" <yong.y.wang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>; "Wang Qi"" <qi.wang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>; "Andrew""
<andrew.chih.howe.khor-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>; <arjan-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>; "Tomoya MORINAGA" <morinaga526-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>; "Arnd
Bergmann" <arnd-r2nGTMty4D4@public.gmane.org>
Sent: Wednesday, September 01, 2010 11:43 AM
Subject: Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
> On Wed, 2010-09-01 at 11:26 +0900, Masayuki Ohtak wrote:
> > I2C driver of Topcliff PCH
> > +++ b/drivers/i2c/busses/i2c-pch.c
> []
> > +static void pch_init(struct i2c_algo_pch_data *adap)
> []
> > + if (pch_i2c_speed == FAST_MODE_CLK) {
> > + reg_value |= FAST_MODE_EN;
> > + dev_dbg(adap->pch_adapter.dev.parent, "Fast mode enabled\n");
> > + }
>
> Just a suggestion below, ignore it at your pleasure...
>
> These dev_<level> calls might be easier to read if you had
> some #defines like:
>
> #define pch_dbg(adap, fmt, arg...) \
> dev_dbg(adap->pch_adapter.dev.parent, fmt, ##arg)
> #define pch_err(adap, fmt, arg...) \
> dev_err(adap->pch_adapter.dev.parent, fmt, ##arg)
> #define pch_info(adap, fmt, arg...) \
> dev_info(adap->pch_adapter.dev.parent, fmt, ##arg)
>
> then the last dev_dbg becomes:
>
> pch_dbg(adap, "Fast mode enabled\n");
>
> Many modules use similar wrapper #defines.
>
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "%s: I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
> > + __func__, ioread32(p + PCH_I2CCTL),
> > + pch_i2cbc, pch_i2ctmr);
>
> pch_dbg(adap, etc...)
>
> etc.
>
> cheers, Joe
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
2010-09-01 5:08 ` Masayuki Ohtake
(?)
@ 2010-09-01 5:24 ` Joe Perches
2010-09-01 5:44 ` Masayuki Ohtake
-1 siblings, 1 reply; 47+ messages in thread
From: Joe Perches @ 2010-09-01 5:24 UTC (permalink / raw)
To: Masayuki Ohtake
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c, linux-kernel, Wang Yong Y",
Wang Qi", Andrew",
arjan, Tomoya MORINAGA, Arnd Bergmann
On Wed, 2010-09-01 at 14:08 +0900, Masayuki Ohtake wrote:
> I have a question.
> Current our I2C driver has the following 2 patterns dev_err().
> (1) dev_err(adap->pch_adapter.dev.parent, "...");
> (2) dev_err(&pdev->dev, "...");
> > #define pch_err(adap, fmt, arg...) \
> > dev_err(adap->pch_adapter.dev.parent, fmt, ##arg)
> In case of using the above code, pattern (1) can apply, but (2) can't.
> As to (2),
> Should we use as dev_err or define another macro?
Hello Ohtake.
To me, it's a visual complexity vs std pattern trade-off.
A 2 level dereference like dev_info(&dev->dev, ...)
isn't overly difficult to read.
3 or more dereferences can be harder and a bit error prone.
So I would only use pch_<level> for (1) and dev_err for (2).
There are also times when there are additional standard
arguments that you want to prefix to dev_<level> calls
and that can be simplified with a custom XXX_<level>
define for dev_<level>
Look at the current uses in the tree and see what you like.
$ grep -rP --include=*.[ch] "#define\s*.+\s+dev_[a-z]{3,7}\s*\(" *
These aren't requirements, do what you think best.
cheers, Joe
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
2010-09-01 5:24 ` Joe Perches
@ 2010-09-01 5:44 ` Masayuki Ohtake
0 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtake @ 2010-09-01 5:44 UTC (permalink / raw)
To: Joe Perches
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c, linux-kernel, Wang Yong Y",
Wang Qi", Andrew",
arjan, Tomoya MORINAGA, Arnd Bergmann
Hi Joe,
Thank you for your comments.
Best Regards,
Ohtake(OKISemi)
----- Original Message -----
From: "Joe Perches" <joe@perches.com>
To: "Masayuki Ohtake" <masa-korg@dsn.okisemi.com>
Cc: "Jean Delvare (PC drivers, core)" <khali@linux-fr.org>; "Ben Dooks (embedded platforms)" <ben-linux@fluff.org>;
"Crane Cai" <crane.cai@amd.com>; "Samuel Ortiz" <sameo@linux.intel.com>; "Linus Walleij" <linus.walleij@stericsson.com>;
"Ralf Baechle" <ralf@linux-mips.org>; "srinidhi kasagar" <srinidhi.kasagar@stericsson.com>; <linux-i2c@vger.kernel.org>;
<linux-kernel@vger.kernel.org>; "Wang Yong Y"" <yong.y.wang@intel.com>; "Wang Qi"" <qi.wang@intel.com>; "Andrew""
<andrew.chih.howe.khor@intel.com>; <arjan@linux.intel.com>; "Tomoya MORINAGA" <morinaga526@dsn.okisemi.com>; "Arnd
Bergmann" <arnd@arndb.de>
Sent: Wednesday, September 01, 2010 2:24 PM
Subject: Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
> On Wed, 2010-09-01 at 14:08 +0900, Masayuki Ohtake wrote:
> > I have a question.
> > Current our I2C driver has the following 2 patterns dev_err().
> > (1) dev_err(adap->pch_adapter.dev.parent, "...");
> > (2) dev_err(&pdev->dev, "...");
> > > #define pch_err(adap, fmt, arg...) \
> > > dev_err(adap->pch_adapter.dev.parent, fmt, ##arg)
> > In case of using the above code, pattern (1) can apply, but (2) can't.
> > As to (2),
> > Should we use as dev_err or define another macro?
>
> Hello Ohtake.
>
> To me, it's a visual complexity vs std pattern trade-off.
>
> A 2 level dereference like dev_info(&dev->dev, ...)
> isn't overly difficult to read.
> 3 or more dereferences can be harder and a bit error prone.
> So I would only use pch_<level> for (1) and dev_err for (2).
>
> There are also times when there are additional standard
> arguments that you want to prefix to dev_<level> calls
> and that can be simplified with a custom XXX_<level>
> define for dev_<level>
>
> Look at the current uses in the tree and see what you like.
>
> $ grep -rP --include=*.[ch] "#define\s*.+\s+dev_[a-z]{3,7}\s*\(" *
>
> These aren't requirements, do what you think best.
>
> cheers, Joe
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-01 5:44 ` Masayuki Ohtake
0 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtake @ 2010-09-01 5:44 UTC (permalink / raw)
To: Joe Perches
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Wang Yong Y",
Wang Qi", Andrew",
arjan-VuQAYsv1563Yd54FQh9/CA, Tomoya MORINAGA, Arnd Bergmann
Hi Joe,
Thank you for your comments.
Best Regards,
Ohtake(OKISemi)
----- Original Message -----
From: "Joe Perches" <joe-6d6DIl74uiNBDgjK7y7TUQ@public.gmane.org>
To: "Masayuki Ohtake" <masa-korg-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>
Cc: "Jean Delvare (PC drivers, core)" <khali-PUYAD+kWke1g9hUCZPvPmw@public.gmane.org>; "Ben Dooks (embedded platforms)" <ben-linux-elnMNo+KYs3YtjvyW6yDsg@public.gmane.org>;
"Crane Cai" <crane.cai-5C7GfCeVMHo@public.gmane.org>; "Samuel Ortiz" <sameo-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>; "Linus Walleij" <linus.walleij-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>;
"Ralf Baechle" <ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>; "srinidhi kasagar" <srinidhi.kasagar-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>; <linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>;
<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>; "Wang Yong Y"" <yong.y.wang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>; "Wang Qi"" <qi.wang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>; "Andrew""
<andrew.chih.howe.khor-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>; <arjan-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>; "Tomoya MORINAGA" <morinaga526-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>; "Arnd
Bergmann" <arnd-r2nGTMty4D4@public.gmane.org>
Sent: Wednesday, September 01, 2010 2:24 PM
Subject: Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
> On Wed, 2010-09-01 at 14:08 +0900, Masayuki Ohtake wrote:
> > I have a question.
> > Current our I2C driver has the following 2 patterns dev_err().
> > (1) dev_err(adap->pch_adapter.dev.parent, "...");
> > (2) dev_err(&pdev->dev, "...");
> > > #define pch_err(adap, fmt, arg...) \
> > > dev_err(adap->pch_adapter.dev.parent, fmt, ##arg)
> > In case of using the above code, pattern (1) can apply, but (2) can't.
> > As to (2),
> > Should we use as dev_err or define another macro?
>
> Hello Ohtake.
>
> To me, it's a visual complexity vs std pattern trade-off.
>
> A 2 level dereference like dev_info(&dev->dev, ...)
> isn't overly difficult to read.
> 3 or more dereferences can be harder and a bit error prone.
> So I would only use pch_<level> for (1) and dev_err for (2).
>
> There are also times when there are additional standard
> arguments that you want to prefix to dev_<level> calls
> and that can be simplified with a custom XXX_<level>
> define for dev_<level>
>
> Look at the current uses in the tree and see what you like.
>
> $ grep -rP --include=*.[ch] "#define\s*.+\s+dev_[a-z]{3,7}\s*\(" *
>
> These aren't requirements, do what you think best.
>
> cheers, Joe
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-01 19:44 ` Linus Walleij
0 siblings, 0 replies; 47+ messages in thread
From: Linus Walleij @ 2010-09-01 19:44 UTC (permalink / raw)
To: Masayuki Ohtak
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Ralf Baechle, srinidhi kasagar,
linux-i2c, linux-kernel, Wang Yong Y", Wang Qi",
Andrew",
arjan, Tomoya MORINAGA, Arnd Bergmann
2010/9/1 Masayuki Ohtak <masa-korg@dsn.okisemi.com>:
> I2C driver of Topcliff PCH
> (...)
> +++ b/drivers/i2c/busses/i2c-pch.c
> (...)
> +/**
> + * pch_wait_for_bus_idle() - check the status of bus.
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + * @timeout: waiting time counter (us).
> + */
> +static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
> + s32 timeout)
> +{
> + void __iomem *p = adap->pch_base_address;
> +
> + /* MAX timeout value is timeout*1000*1000nsec */
> + ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
> + do {
> + if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
> + break;
> + msleep(1);
> + } while (ktime_lt(ktime_get(), ns_val));
> +
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "%s : I2CSR = %x\n", __func__, ioread32(p + PCH_I2CSR));
> +
> + if (timeout == 0) {
> + dev_err(adap->pch_adapter.dev.parent,
> + "%s :return%d\n", __func__, -ETIME);
Why not just return -ETIME; here?
> + } else {
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "%s : return %d\n", __func__, 0);
> + }
Delete this else clause, who is interested in return 0???
> + return ((timeout <= 0) ? (-ETIME) : (0));
return 0;
> (...)
> +/**
> + * pch_wait_for_xfer_complete() - initiates a wait for the tx complete event
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + */
> +static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
> +{
> + s32 ret;
> + ret = wait_event_interruptible_timeout(pch_event,
> + (adap->pch_event_flag != 0), msecs_to_jiffies(50));
> + if (ret < 0)
> + goto out;
The goto construction is unnecessary, just
return ret;
> +
> + if (ret == 0) {
> + ret = -ETIMEDOUT;
> + goto out;
return -ETIMEDOUT;
> + }
> +
> + if (adap->pch_event_flag & I2C_ERROR_MASK) {
> + ret = -EIO;
> + dev_err(adap->pch_adapter.dev.parent,
> + "error bits set: %x\n", adap->pch_event_flag);
> + goto out;
Skip ret assignment
return -EIO;
> + }
> +
> + adap->pch_event_flag = 0;
> + ret = 0;
Skip this
> +out:
> + return ret;
return 0;
> +}
> (...)
> +/**
> + * pch_getack() - to confirm ACK/NACK
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + */
> +static s32 pch_getack(struct i2c_algo_pch_data *adap)
> +{
> + u32 reg_val;
> + void __iomem *p = adap->pch_base_address;
> + reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
> +
> + if (reg_val == 0)
> + dev_dbg(adap->pch_adapter.dev.parent, "%s : return 0\n",
> + __func__);
> + else
> + dev_dbg(adap->pch_adapter.dev.parent, "%s : return%d\n",
> + __func__, -EPROTO);
> +
> + return (((reg_val) == 0) ? (0) : (-EPROTO));
Refactor this like the other function, no weirdo debug prints
return 0;
> +}
> (...)
> +/**
> + * pch_writebytes() - write data to I2C bus in normal mode
> + * @i2c_adap: Pointer to the struct i2c_adapter.
> + * @last: specifies whether last message or not.
> + * In the case of compound mode it will be 1 for last message,
> + * otherwise 0.
> + * @first: specifies whether first message or not.
> + * 1 for first message otherwise 0.
> + */
> +static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
> + u32 last, u32 first)
> +{
> + struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
> + u8 *buf;
> + u32 length;
> + u32 addr;
> + u32 addr_2_msb;
> + u32 addr_8_lsb;
> + s32 wrcount;
You don't assign anything to wrcount...
> + void __iomem *p = adap->pch_base_address;
> + length = msgs->len;
> + buf = msgs->buf;
> + addr = msgs->addr;
> + /* enable master tx */
> + pch_setbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
> +
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "%s : I2CCTL = %x msgs->len = %d\n", __func__,
> + ioread32(p + PCH_I2CCTL), length);
> +
> + if (first) {
> + if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
> + return -ETIME;
> + }
> +
> + if (msgs->flags & I2C_M_TEN) {
> + addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
> + iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
> + if (first)
> + pch_start(adap);
> + if ((pch_wait_for_xfer_complete(adap) == 0) &&
> + (pch_getack(adap) == 0)) {
> + addr_8_lsb = (addr & I2C_ADDR_MSK);
> + iowrite32(addr_8_lsb, p + PCH_I2CDR);
> + } else {
> + pch_stop(adap);
> + return -ETIME;
> + }
> + } else {
> + /* set 7 bit slave address and R/W bit as 0 */
> + iowrite32(addr << 1, p + PCH_I2CDR);
> + if (first)
> + pch_start(adap);
> + }
> +
> + if ((pch_wait_for_xfer_complete(adap) == 0) &&
> + (pch_getack(adap) == 0)) {
> + for (wrcount = 0; wrcount < length; ++wrcount) {
...but it is only conditionally used here...
> + /* write buffer value to I2C data register */
> + iowrite32(buf[wrcount], p + PCH_I2CDR);
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "%s : writing %x to Data register\n",
> + __func__, buf[wrcount]);
> +
> + if (pch_wait_for_xfer_complete(adap) != 0) {
> + wrcount = -ETIME;
> + break;
> + }
> +
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "%s return %d", __func__, 0);
> +
> + if (pch_getack(adap)) {
> + wrcount = -ETIME;
> + break;
> + }
> + }
> +
> + /* check if this is the last message */
> + if (last)
> + pch_stop(adap);
> + else
> + pch_repstart(adap);
> + } else {
> + pch_stop(adap);
> + }
> +
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "%s return=%d\n", __func__, wrcount);
> +
> + return wrcount;
...and then you return it, leading to a possibly unassigned state.
> +}
> (...)
> +/**
> + * pch_readbytes() - read data from I2C bus in normal mode.
> + * @i2c_adap: Pointer to the struct i2c_adapter.
> + * @msgs: Pointer to i2c_msg structure.
> + * @last: specifies whether last message or not.
> + * @first: specifies whether first message or not.
> + */
> +s32 pch_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
> + u32 last, u32 first)
> +{
> + struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
> +
> + u8 *buf;
> + u32 count;
Same problem here. Initialize to 0.
> + u32 length;
> + u32 addr;
> + u32 addr_2_msb;
> + void __iomem *p = adap->pch_base_address;
> + length = msgs->len;
> + buf = msgs->buf;
> + addr = msgs->addr;
> +
> + /* enable master reception */
> + pch_clrbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
> +
> + if (first) {
> + if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
> + return -ETIME;
> + }
> +
> + if (msgs->flags & I2C_M_TEN) {
> + addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
> + iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
> +
> + } else {
> + /* 7 address bits + R/W bit */
> + addr = (((addr) << 1) | (I2C_RD));
> + iowrite32(addr, p + PCH_I2CDR);
> + }
> +
> + /* check if it is the first message */
> + if (first)
> + pch_start(adap);
> +
> + if ((pch_wait_for_xfer_complete(adap) == 0)
> + && (pch_getack(adap) == 0)) {
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "%s return %d", __func__, 0);
> +
> + if (length == 0) {
> + pch_stop(adap);
> + ioread32(p + PCH_I2CDR); /* Dummy read needs */
> +
> + count = length;
> + } else {
> + int read_index;
> + int loop;
> + pch_sendack(adap);
> +
> + /* Dummy read */
> + for (loop = 1, read_index = 0; loop < length; loop++) {
> + buf[read_index] = ioread32(p + PCH_I2CDR);
> +
> + if (loop != 1)
> + read_index++;
> +
> + if (pch_wait_for_xfer_complete(adap) != 0) {
> + pch_stop(adap);
> + return -ETIME;
> + }
> + } /* end for */
> +
> + pch_sendnack(adap);
> +
> + buf[read_index] = ioread32(p + PCH_I2CDR);
> +
> + if (length != 1)
> + read_index++;
> +
> + if (pch_wait_for_xfer_complete(adap) == 0) {
> + if (last)
> + pch_stop(adap);
> + else
> + pch_repstart(adap);
> +
> + buf[read_index++] = ioread32(p + PCH_I2CDR);
> + count = read_index;
> + } else {
> + count = -ETIME;
> + }
> +
> + }
> + } else {
> + count = -ETIME;
> + pch_stop(adap);
> + }
> +
> + return count;
> +}
> (...)
> +/**
> + * pch_handler_ch0() - interrupt handler for the PCH I2C controller
> + * @irq: irq number.
> + * @pData: cookie passed back to the handler function.
> + */
> +static irqreturn_t pch_handler_ch0(int irq, void *pData)
> +{
> + s32 reg_val;
> +
> + struct i2c_algo_pch_data *adap_data = (struct i2c_algo_pch_data *)pData;
> + void __iomem *p = adap_data->pch_base_address;
> + u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE);
> +
> + if (mode == NORMAL_MODE) {
No.
if (mode != NORMAL_MODE) {
dev_err(...)
return IRQ_NONE;
}
Then de-indent the rest and remove the else clause.
> + reg_val = ioread32(p + PCH_I2CSR);
> + if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
> + pch_cb_ch0(adap_data);
> + else
> + goto err_out;
> + } else {
> + dev_err(adap_data->pch_adapter.dev.parent,
> + "%s I2C mode is not supported\n", __func__);
> + goto err_out;
> + }
> + return IRQ_HANDLED;
> +
> +err_out:
> + return IRQ_NONE;
> +}
> (...)
> +/**
> + * pch_xfer() - Reading adnd writing data through I2C bus
> + * @i2c_adap: Pointer to the struct i2c_adapter.
> + * @msgs: Pointer to i2c_msg structure.
> + * @num: number of messages.
> + */
> +static s32 pch_xfer(struct i2c_adapter *i2c_adap,
> + struct i2c_msg *msgs, s32 num)
> +{
> + struct i2c_msg *pmsg;
> + u32 i;
> + u32 status;
> + u32 msglen;
> + u32 subaddrlen;
> + s32 ret;
> +
> + struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
> +
> + ret = mutex_lock_interruptible(&pch_mutex);
> + if (ret) {
> + ret = -ERESTARTSYS;
> + goto return_err_nomutex;
> + }
> + if (adap->p_adapter_info->pch_suspended == false) {
No.
if (adap->p_adapter_info->pch_suspended) {
mutex_unlock(&pch_nomutex);
return -EBUSY;
}
De-indent the rest and remove the else clause.
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "%s adap->p_adapter_info->pch_suspended is %d\n",
> + __func__, adap->p_adapter_info->pch_suspended);
> + /* transfer not completed */
> + adap->pch_xfer_in_progress = true;
> +
> + ret = -EBUSY;
> + for (i = 0; i < num; i++) {
> + pmsg = &msgs[i];
> + pmsg->flags |= adap->pch_buff_mode_en;
> + status = pmsg->flags;
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "After invoking I2C_MODE_SEL :flag= 0x%x\n",
> + status);
> + /* calculate sub address length and message length */
> + /* these are applicable only for buffer mode */
> + subaddrlen = pmsg->buf[0];
> + /* calculate actual message length excluding
> + * the sub address fields */
> + msglen = (pmsg->len) - (subaddrlen + 1);
> + if (status & (I2C_M_RD)) {
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "%s invoking pch_readbytes\n",
> + __func__);
> + ret = pch_readbytes(i2c_adap, pmsg,
> + (i + 1 == num),
> + (i == 0));
> + } else {
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "%s invoking pch_writebytes\n",
> + __func__);
> + ret = pch_writebytes(i2c_adap, pmsg,
> + (i + 1 == num),
> + (i == 0));
> + }
> +
> + }
> +
> + adap->pch_xfer_in_progress = false; /* transfer completed */
> +
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "adap->pch_xfer_in_progress is %d\n",
> + adap->pch_xfer_in_progress);
> + } else {
> + ret = -EBUSY;
> + }
> +
> + mutex_unlock(&pch_mutex);
> +return_err_nomutex:
> + dev_dbg(adap->pch_adapter.dev.parent, "%s return:%d\n\n\n\n",
> + __func__, ret);
> + return ret;
> +}
> (...)
> +static int __devinit pch_probe(struct pci_dev *pdev,
> + const struct pci_device_id *id)
> +{
> + int i;
> + void __iomem *base_addr;
> + s32 ret;
> + struct adapter_info *adap_info =
> + kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
> +
> + dev_dbg(&pdev->dev, "Enterred in %s\n", __func__);
> +
> + if (adap_info == NULL) {
> + dev_err(&pdev->dev, "Memory allocation failed FAILED");
> + ret = -ENOMEM;
> + goto return_err;
Just
return -ENOMEM;
Goto construction unnecessary here.
> (...)
> +#ifdef CONFIG_PM
> +static int pch_suspend(struct pci_dev *pdev, pm_message_t state)
> +{
> + int i;
> + int ret;
> +
> + struct adapter_info *adap_info = pci_get_drvdata(pdev);
> + void __iomem *p = adap_info->pch_data[0].pch_base_address;
> +
> + adap_info->pch_suspended = true;
> +
> + for (i = 0; i < PCH_MAX_CHN; i++) {
> + while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
> + /* It is assumed that any pending transfer will
> + * be completed after the delay
> + */
> + msleep(1);
> + }
The comment seems to be a lie. It is not assumed that it will
be completed at all, because you're sleeping repeatedly until all
transfers are completed.
What you are doing is you are waiting for channel zero to
complete transfers, then channel 1 etc up to channel PCH_MAX_CHN.
> + /* Disable the i2c interrupts */
> + pch_disbl_int(&adap_info->pch_data[i]);
> + }
> +
> + dev_dbg(&pdev->dev,
> + "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
> + "invoked function pch_disbl_int successfully\n",
> + ioread32(p + 0x08),
> + ioread32(p + 0x30),
> + ioread32(p + 0x44));
> +
> + ret = pci_save_state(pdev);
> +
> + if (ret) {
> + dev_err(&pdev->dev, "pci_save_state failed\n");
> + return ret;
> + }
> +
> + pci_enable_wake(pdev, PCI_D3hot, 0);
> + pci_disable_device(pdev);
> + pci_set_power_state(pdev, pci_choose_state(pdev, state));
> +
> + return 0;
> +}
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-01 19:44 ` Linus Walleij
0 siblings, 0 replies; 47+ messages in thread
From: Linus Walleij @ 2010-09-01 19:44 UTC (permalink / raw)
To: Masayuki Ohtak
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Ralf Baechle, srinidhi kasagar,
linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Wang Yong Y",
Wang Qi", Andrew",
arjan-VuQAYsv1563Yd54FQh9/CA, Tomoya MORINAGA, Arnd Bergmann
2010/9/1 Masayuki Ohtak <masa-korg-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>:
> I2C driver of Topcliff PCH
> (...)
> +++ b/drivers/i2c/busses/i2c-pch.c
> (...)
> +/**
> + * pch_wait_for_bus_idle() - check the status of bus.
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + * @timeout: waiting time counter (us).
> + */
> +static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
> + s32 timeout)
> +{
> + void __iomem *p = adap->pch_base_address;
> +
> + /* MAX timeout value is timeout*1000*1000nsec */
> + ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
> + do {
> + if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
> + break;
> + msleep(1);
> + } while (ktime_lt(ktime_get(), ns_val));
> +
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "%s : I2CSR = %x\n", __func__, ioread32(p + PCH_I2CSR));
> +
> + if (timeout == 0) {
> + dev_err(adap->pch_adapter.dev.parent,
> + "%s :return%d\n", __func__, -ETIME);
Why not just return -ETIME; here?
> + } else {
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "%s : return %d\n", __func__, 0);
> + }
Delete this else clause, who is interested in return 0???
> + return ((timeout <= 0) ? (-ETIME) : (0));
return 0;
> (...)
> +/**
> + * pch_wait_for_xfer_complete() - initiates a wait for the tx complete event
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + */
> +static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
> +{
> + s32 ret;
> + ret = wait_event_interruptible_timeout(pch_event,
> + (adap->pch_event_flag != 0), msecs_to_jiffies(50));
> + if (ret < 0)
> + goto out;
The goto construction is unnecessary, just
return ret;
> +
> + if (ret == 0) {
> + ret = -ETIMEDOUT;
> + goto out;
return -ETIMEDOUT;
> + }
> +
> + if (adap->pch_event_flag & I2C_ERROR_MASK) {
> + ret = -EIO;
> + dev_err(adap->pch_adapter.dev.parent,
> + "error bits set: %x\n", adap->pch_event_flag);
> + goto out;
Skip ret assignment
return -EIO;
> + }
> +
> + adap->pch_event_flag = 0;
> + ret = 0;
Skip this
> +out:
> + return ret;
return 0;
> +}
> (...)
> +/**
> + * pch_getack() - to confirm ACK/NACK
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + */
> +static s32 pch_getack(struct i2c_algo_pch_data *adap)
> +{
> + u32 reg_val;
> + void __iomem *p = adap->pch_base_address;
> + reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
> +
> + if (reg_val == 0)
> + dev_dbg(adap->pch_adapter.dev.parent, "%s : return 0\n",
> + __func__);
> + else
> + dev_dbg(adap->pch_adapter.dev.parent, "%s : return%d\n",
> + __func__, -EPROTO);
> +
> + return (((reg_val) == 0) ? (0) : (-EPROTO));
Refactor this like the other function, no weirdo debug prints
return 0;
> +}
> (...)
> +/**
> + * pch_writebytes() - write data to I2C bus in normal mode
> + * @i2c_adap: Pointer to the struct i2c_adapter.
> + * @last: specifies whether last message or not.
> + * In the case of compound mode it will be 1 for last message,
> + * otherwise 0.
> + * @first: specifies whether first message or not.
> + * 1 for first message otherwise 0.
> + */
> +static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
> + u32 last, u32 first)
> +{
> + struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
> + u8 *buf;
> + u32 length;
> + u32 addr;
> + u32 addr_2_msb;
> + u32 addr_8_lsb;
> + s32 wrcount;
You don't assign anything to wrcount...
> + void __iomem *p = adap->pch_base_address;
> + length = msgs->len;
> + buf = msgs->buf;
> + addr = msgs->addr;
> + /* enable master tx */
> + pch_setbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
> +
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "%s : I2CCTL = %x msgs->len = %d\n", __func__,
> + ioread32(p + PCH_I2CCTL), length);
> +
> + if (first) {
> + if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
> + return -ETIME;
> + }
> +
> + if (msgs->flags & I2C_M_TEN) {
> + addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
> + iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
> + if (first)
> + pch_start(adap);
> + if ((pch_wait_for_xfer_complete(adap) == 0) &&
> + (pch_getack(adap) == 0)) {
> + addr_8_lsb = (addr & I2C_ADDR_MSK);
> + iowrite32(addr_8_lsb, p + PCH_I2CDR);
> + } else {
> + pch_stop(adap);
> + return -ETIME;
> + }
> + } else {
> + /* set 7 bit slave address and R/W bit as 0 */
> + iowrite32(addr << 1, p + PCH_I2CDR);
> + if (first)
> + pch_start(adap);
> + }
> +
> + if ((pch_wait_for_xfer_complete(adap) == 0) &&
> + (pch_getack(adap) == 0)) {
> + for (wrcount = 0; wrcount < length; ++wrcount) {
...but it is only conditionally used here...
> + /* write buffer value to I2C data register */
> + iowrite32(buf[wrcount], p + PCH_I2CDR);
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "%s : writing %x to Data register\n",
> + __func__, buf[wrcount]);
> +
> + if (pch_wait_for_xfer_complete(adap) != 0) {
> + wrcount = -ETIME;
> + break;
> + }
> +
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "%s return %d", __func__, 0);
> +
> + if (pch_getack(adap)) {
> + wrcount = -ETIME;
> + break;
> + }
> + }
> +
> + /* check if this is the last message */
> + if (last)
> + pch_stop(adap);
> + else
> + pch_repstart(adap);
> + } else {
> + pch_stop(adap);
> + }
> +
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "%s return=%d\n", __func__, wrcount);
> +
> + return wrcount;
...and then you return it, leading to a possibly unassigned state.
> +}
> (...)
> +/**
> + * pch_readbytes() - read data from I2C bus in normal mode.
> + * @i2c_adap: Pointer to the struct i2c_adapter.
> + * @msgs: Pointer to i2c_msg structure.
> + * @last: specifies whether last message or not.
> + * @first: specifies whether first message or not.
> + */
> +s32 pch_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
> + u32 last, u32 first)
> +{
> + struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
> +
> + u8 *buf;
> + u32 count;
Same problem here. Initialize to 0.
> + u32 length;
> + u32 addr;
> + u32 addr_2_msb;
> + void __iomem *p = adap->pch_base_address;
> + length = msgs->len;
> + buf = msgs->buf;
> + addr = msgs->addr;
> +
> + /* enable master reception */
> + pch_clrbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
> +
> + if (first) {
> + if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
> + return -ETIME;
> + }
> +
> + if (msgs->flags & I2C_M_TEN) {
> + addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
> + iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
> +
> + } else {
> + /* 7 address bits + R/W bit */
> + addr = (((addr) << 1) | (I2C_RD));
> + iowrite32(addr, p + PCH_I2CDR);
> + }
> +
> + /* check if it is the first message */
> + if (first)
> + pch_start(adap);
> +
> + if ((pch_wait_for_xfer_complete(adap) == 0)
> + && (pch_getack(adap) == 0)) {
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "%s return %d", __func__, 0);
> +
> + if (length == 0) {
> + pch_stop(adap);
> + ioread32(p + PCH_I2CDR); /* Dummy read needs */
> +
> + count = length;
> + } else {
> + int read_index;
> + int loop;
> + pch_sendack(adap);
> +
> + /* Dummy read */
> + for (loop = 1, read_index = 0; loop < length; loop++) {
> + buf[read_index] = ioread32(p + PCH_I2CDR);
> +
> + if (loop != 1)
> + read_index++;
> +
> + if (pch_wait_for_xfer_complete(adap) != 0) {
> + pch_stop(adap);
> + return -ETIME;
> + }
> + } /* end for */
> +
> + pch_sendnack(adap);
> +
> + buf[read_index] = ioread32(p + PCH_I2CDR);
> +
> + if (length != 1)
> + read_index++;
> +
> + if (pch_wait_for_xfer_complete(adap) == 0) {
> + if (last)
> + pch_stop(adap);
> + else
> + pch_repstart(adap);
> +
> + buf[read_index++] = ioread32(p + PCH_I2CDR);
> + count = read_index;
> + } else {
> + count = -ETIME;
> + }
> +
> + }
> + } else {
> + count = -ETIME;
> + pch_stop(adap);
> + }
> +
> + return count;
> +}
> (...)
> +/**
> + * pch_handler_ch0() - interrupt handler for the PCH I2C controller
> + * @irq: irq number.
> + * @pData: cookie passed back to the handler function.
> + */
> +static irqreturn_t pch_handler_ch0(int irq, void *pData)
> +{
> + s32 reg_val;
> +
> + struct i2c_algo_pch_data *adap_data = (struct i2c_algo_pch_data *)pData;
> + void __iomem *p = adap_data->pch_base_address;
> + u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE);
> +
> + if (mode == NORMAL_MODE) {
No.
if (mode != NORMAL_MODE) {
dev_err(...)
return IRQ_NONE;
}
Then de-indent the rest and remove the else clause.
> + reg_val = ioread32(p + PCH_I2CSR);
> + if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
> + pch_cb_ch0(adap_data);
> + else
> + goto err_out;
> + } else {
> + dev_err(adap_data->pch_adapter.dev.parent,
> + "%s I2C mode is not supported\n", __func__);
> + goto err_out;
> + }
> + return IRQ_HANDLED;
> +
> +err_out:
> + return IRQ_NONE;
> +}
> (...)
> +/**
> + * pch_xfer() - Reading adnd writing data through I2C bus
> + * @i2c_adap: Pointer to the struct i2c_adapter.
> + * @msgs: Pointer to i2c_msg structure.
> + * @num: number of messages.
> + */
> +static s32 pch_xfer(struct i2c_adapter *i2c_adap,
> + struct i2c_msg *msgs, s32 num)
> +{
> + struct i2c_msg *pmsg;
> + u32 i;
> + u32 status;
> + u32 msglen;
> + u32 subaddrlen;
> + s32 ret;
> +
> + struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
> +
> + ret = mutex_lock_interruptible(&pch_mutex);
> + if (ret) {
> + ret = -ERESTARTSYS;
> + goto return_err_nomutex;
> + }
> + if (adap->p_adapter_info->pch_suspended == false) {
No.
if (adap->p_adapter_info->pch_suspended) {
mutex_unlock(&pch_nomutex);
return -EBUSY;
}
De-indent the rest and remove the else clause.
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "%s adap->p_adapter_info->pch_suspended is %d\n",
> + __func__, adap->p_adapter_info->pch_suspended);
> + /* transfer not completed */
> + adap->pch_xfer_in_progress = true;
> +
> + ret = -EBUSY;
> + for (i = 0; i < num; i++) {
> + pmsg = &msgs[i];
> + pmsg->flags |= adap->pch_buff_mode_en;
> + status = pmsg->flags;
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "After invoking I2C_MODE_SEL :flag= 0x%x\n",
> + status);
> + /* calculate sub address length and message length */
> + /* these are applicable only for buffer mode */
> + subaddrlen = pmsg->buf[0];
> + /* calculate actual message length excluding
> + * the sub address fields */
> + msglen = (pmsg->len) - (subaddrlen + 1);
> + if (status & (I2C_M_RD)) {
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "%s invoking pch_readbytes\n",
> + __func__);
> + ret = pch_readbytes(i2c_adap, pmsg,
> + (i + 1 == num),
> + (i == 0));
> + } else {
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "%s invoking pch_writebytes\n",
> + __func__);
> + ret = pch_writebytes(i2c_adap, pmsg,
> + (i + 1 == num),
> + (i == 0));
> + }
> +
> + }
> +
> + adap->pch_xfer_in_progress = false; /* transfer completed */
> +
> + dev_dbg(adap->pch_adapter.dev.parent,
> + "adap->pch_xfer_in_progress is %d\n",
> + adap->pch_xfer_in_progress);
> + } else {
> + ret = -EBUSY;
> + }
> +
> + mutex_unlock(&pch_mutex);
> +return_err_nomutex:
> + dev_dbg(adap->pch_adapter.dev.parent, "%s return:%d\n\n\n\n",
> + __func__, ret);
> + return ret;
> +}
> (...)
> +static int __devinit pch_probe(struct pci_dev *pdev,
> + const struct pci_device_id *id)
> +{
> + int i;
> + void __iomem *base_addr;
> + s32 ret;
> + struct adapter_info *adap_info =
> + kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
> +
> + dev_dbg(&pdev->dev, "Enterred in %s\n", __func__);
> +
> + if (adap_info == NULL) {
> + dev_err(&pdev->dev, "Memory allocation failed FAILED");
> + ret = -ENOMEM;
> + goto return_err;
Just
return -ENOMEM;
Goto construction unnecessary here.
> (...)
> +#ifdef CONFIG_PM
> +static int pch_suspend(struct pci_dev *pdev, pm_message_t state)
> +{
> + int i;
> + int ret;
> +
> + struct adapter_info *adap_info = pci_get_drvdata(pdev);
> + void __iomem *p = adap_info->pch_data[0].pch_base_address;
> +
> + adap_info->pch_suspended = true;
> +
> + for (i = 0; i < PCH_MAX_CHN; i++) {
> + while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
> + /* It is assumed that any pending transfer will
> + * be completed after the delay
> + */
> + msleep(1);
> + }
The comment seems to be a lie. It is not assumed that it will
be completed at all, because you're sleeping repeatedly until all
transfers are completed.
What you are doing is you are waiting for channel zero to
complete transfers, then channel 1 etc up to channel PCH_MAX_CHN.
> + /* Disable the i2c interrupts */
> + pch_disbl_int(&adap_info->pch_data[i]);
> + }
> +
> + dev_dbg(&pdev->dev,
> + "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
> + "invoked function pch_disbl_int successfully\n",
> + ioread32(p + 0x08),
> + ioread32(p + 0x30),
> + ioread32(p + 0x44));
> +
> + ret = pci_save_state(pdev);
> +
> + if (ret) {
> + dev_err(&pdev->dev, "pci_save_state failed\n");
> + return ret;
> + }
> +
> + pci_enable_wake(pdev, PCI_D3hot, 0);
> + pci_disable_device(pdev);
> + pci_set_power_state(pdev, pci_choose_state(pdev, state));
> +
> + return 0;
> +}
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
2010-09-01 19:44 ` Linus Walleij
@ 2010-09-03 3:12 ` Masayuki Ohtake
-1 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtake @ 2010-09-03 3:12 UTC (permalink / raw)
To: Linus Walleij
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Ralf Baechle, srinidhi kasagar,
linux-i2c, ML linux-kernel, Wang Yong Y", Wang Qi",
Andrew",
arjan, Tomoya MORINAGA, Arnd Bergmann
> ----- Original Message -----
> From: "Linus Walleij" <linus.ml.walleij@gmail.com>
> To: "Masayuki Ohtak" <masa-korg@dsn.okisemi.com>
> Cc: "Jean Delvare (PC drivers, core)" <khali@linux-fr.org>; "Ben Dooks (embedded platforms)" <ben-linux@fluff.org>;
"Crane Cai" <crane.cai@amd.com>; "Samuel Ortiz" <sameo@linux.intel.com>; "Ralf Baechle" <ralf@linux-mips.org>; "srinidhi
kasagar" <srinidhi.kasagar@stericsson.com>; <linux-i2c@vger.kernel.org>; <linux-kernel@vger.kernel.org>; "Wang Yong Y""
<yong.y.wang@intel.com>; "Wang Qi"" <qi.wang@intel.com>; "Andrew"" <andrew.chih.howe.khor@intel.com>;
<arjan@linux.intel.com>; "Tomoya MORINAGA" <morinaga526@dsn.okisemi.com>; "Arnd Bergmann" <arnd@arndb.de>
> Sent: Thursday, September 02, 2010 4:44 AM
> Subject: Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
>
>
> 2010/9/1 Masayuki Ohtak <masa-korg@dsn.okisemi.com>:
>
> > I2C driver of Topcliff PCH
> > (...)
> > +++ b/drivers/i2c/busses/i2c-pch.c
> > (...)
> > +/**
> > + * pch_wait_for_bus_idle() - check the status of bus.
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + * @timeout: waiting time counter (us).
> > + */
> > +static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
> > + s32 timeout)
> > +{
> > + void __iomem *p = adap->pch_base_address;
> > +
> > + /* MAX timeout value is timeout*1000*1000nsec */
> > + ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
> > + do {
> > + if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
> > + break;
> > + msleep(1);
> > + } while (ktime_lt(ktime_get(), ns_val));
> > +
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "%s : I2CSR = %x\n", __func__, ioread32(p + PCH_I2CSR));
> > +
> > + if (timeout == 0) {
> > + dev_err(adap->pch_adapter.dev.parent,
> > + "%s :return%d\n", __func__, -ETIME);
>
> Why not just return -ETIME; here?
>
> > + } else {
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "%s : return %d\n", __func__, 0);
> > + }
>
> Delete this else clause, who is interested in return 0???
>
> > + return ((timeout <= 0) ? (-ETIME) : (0));
>
> return 0;
>
> > (...)
> > +/**
> > + * pch_wait_for_xfer_complete() - initiates a wait for the tx complete event
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + */
> > +static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
> > +{
> > + s32 ret;
> > + ret = wait_event_interruptible_timeout(pch_event,
> > + (adap->pch_event_flag != 0), msecs_to_jiffies(50));
> > + if (ret < 0)
> > + goto out;
>
> The goto construction is unnecessary, just
>
> return ret;
>
> > +
> > + if (ret == 0) {
> > + ret = -ETIMEDOUT;
> > + goto out;
>
> return -ETIMEDOUT;
>
> > + }
> > +
> > + if (adap->pch_event_flag & I2C_ERROR_MASK) {
> > + ret = -EIO;
> > + dev_err(adap->pch_adapter.dev.parent,
> > + "error bits set: %x\n", adap->pch_event_flag);
> > + goto out;
>
> Skip ret assignment
> return -EIO;
>
> > + }
> > +
> > + adap->pch_event_flag = 0;
> > + ret = 0;
>
> Skip this
>
> > +out:
> > + return ret;
>
> return 0;
>
> > +}
> > (...)
> > +/**
> > + * pch_getack() - to confirm ACK/NACK
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + */
> > +static s32 pch_getack(struct i2c_algo_pch_data *adap)
> > +{
> > + u32 reg_val;
> > + void __iomem *p = adap->pch_base_address;
> > + reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
> > +
> > + if (reg_val == 0)
> > + dev_dbg(adap->pch_adapter.dev.parent, "%s : return 0\n",
> > + __func__);
> > + else
> > + dev_dbg(adap->pch_adapter.dev.parent, "%s : return%d\n",
> > + __func__, -EPROTO);
> > +
> > + return (((reg_val) == 0) ? (0) : (-EPROTO));
>
> Refactor this like the other function, no weirdo debug prints
> return 0;
>
> > +}
> > (...)
> > +/**
> > + * pch_writebytes() - write data to I2C bus in normal mode
> > + * @i2c_adap: Pointer to the struct i2c_adapter.
> > + * @last: specifies whether last message or not.
> > + * In the case of compound mode it will be 1 for last message,
> > + * otherwise 0.
> > + * @first: specifies whether first message or not.
> > + * 1 for first message otherwise 0.
> > + */
> > +static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
> > + u32 last, u32 first)
> > +{
> > + struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
> > + u8 *buf;
> > + u32 length;
> > + u32 addr;
> > + u32 addr_2_msb;
> > + u32 addr_8_lsb;
> > + s32 wrcount;
>
> You don't assign anything to wrcount...
>
> > + void __iomem *p = adap->pch_base_address;
> > + length = msgs->len;
> > + buf = msgs->buf;
> > + addr = msgs->addr;
> > + /* enable master tx */
> > + pch_setbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
> > +
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "%s : I2CCTL = %x msgs->len = %d\n", __func__,
> > + ioread32(p + PCH_I2CCTL), length);
> > +
> > + if (first) {
> > + if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
> > + return -ETIME;
> > + }
> > +
> > + if (msgs->flags & I2C_M_TEN) {
> > + addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
> > + iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
> > + if (first)
> > + pch_start(adap);
> > + if ((pch_wait_for_xfer_complete(adap) == 0) &&
> > + (pch_getack(adap) == 0)) {
> > + addr_8_lsb = (addr & I2C_ADDR_MSK);
> > + iowrite32(addr_8_lsb, p + PCH_I2CDR);
> > + } else {
> > + pch_stop(adap);
> > + return -ETIME;
> > + }
> > + } else {
> > + /* set 7 bit slave address and R/W bit as 0 */
> > + iowrite32(addr << 1, p + PCH_I2CDR);
> > + if (first)
> > + pch_start(adap);
> > + }
> > +
> > + if ((pch_wait_for_xfer_complete(adap) == 0) &&
> > + (pch_getack(adap) == 0)) {
> > + for (wrcount = 0; wrcount < length; ++wrcount) {
>
> ...but it is only conditionally used here...
>
> > + /* write buffer value to I2C data register */
> > + iowrite32(buf[wrcount], p + PCH_I2CDR);
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "%s : writing %x to Data register\n",
> > + __func__, buf[wrcount]);
> > +
> > + if (pch_wait_for_xfer_complete(adap) != 0) {
> > + wrcount = -ETIME;
> > + break;
> > + }
> > +
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "%s return %d", __func__, 0);
> > +
> > + if (pch_getack(adap)) {
> > + wrcount = -ETIME;
> > + break;
> > + }
> > + }
> > +
> > + /* check if this is the last message */
> > + if (last)
> > + pch_stop(adap);
> > + else
> > + pch_repstart(adap);
> > + } else {
> > + pch_stop(adap);
> > + }
> > +
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "%s return=%d\n", __func__, wrcount);
> > +
> > + return wrcount;
>
> ...and then you return it, leading to a possibly unassigned state.
>
> > +}
> > (...)
> > +/**
> > + * pch_readbytes() - read data from I2C bus in normal mode.
> > + * @i2c_adap: Pointer to the struct i2c_adapter.
> > + * @msgs: Pointer to i2c_msg structure.
> > + * @last: specifies whether last message or not.
> > + * @first: specifies whether first message or not.
> > + */
> > +s32 pch_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
> > + u32 last, u32 first)
> > +{
> > + struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
> > +
> > + u8 *buf;
> > + u32 count;
>
> Same problem here. Initialize to 0.
When I submit other patch to upstream,
a maintainer said "variable shouldn't initialize to 0".
Thus, we don't do.
Can you admit above?
>
> > + u32 length;
> > + u32 addr;
> > + u32 addr_2_msb;
> > + void __iomem *p = adap->pch_base_address;
> > + length = msgs->len;
> > + buf = msgs->buf;
> > + addr = msgs->addr;
> > +
> > + /* enable master reception */
> > + pch_clrbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
> > +
> > + if (first) {
> > + if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
> > + return -ETIME;
> > + }
> > +
> > + if (msgs->flags & I2C_M_TEN) {
> > + addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
> > + iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
> > +
> > + } else {
> > + /* 7 address bits + R/W bit */
> > + addr = (((addr) << 1) | (I2C_RD));
> > + iowrite32(addr, p + PCH_I2CDR);
> > + }
> > +
> > + /* check if it is the first message */
> > + if (first)
> > + pch_start(adap);
> > +
> > + if ((pch_wait_for_xfer_complete(adap) == 0)
> > + && (pch_getack(adap) == 0)) {
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "%s return %d", __func__, 0);
> > +
> > + if (length == 0) {
> > + pch_stop(adap);
> > + ioread32(p + PCH_I2CDR); /* Dummy read needs */
> > +
> > + count = length;
> > + } else {
> > + int read_index;
> > + int loop;
> > + pch_sendack(adap);
> > +
> > + /* Dummy read */
> > + for (loop = 1, read_index = 0; loop < length; loop++) {
> > + buf[read_index] = ioread32(p + PCH_I2CDR);
> > +
> > + if (loop != 1)
> > + read_index++;
> > +
> > + if (pch_wait_for_xfer_complete(adap) != 0) {
> > + pch_stop(adap);
> > + return -ETIME;
> > + }
> > + } /* end for */
> > +
> > + pch_sendnack(adap);
> > +
> > + buf[read_index] = ioread32(p + PCH_I2CDR);
> > +
> > + if (length != 1)
> > + read_index++;
> > +
> > + if (pch_wait_for_xfer_complete(adap) == 0) {
> > + if (last)
> > + pch_stop(adap);
> > + else
> > + pch_repstart(adap);
> > +
> > + buf[read_index++] = ioread32(p + PCH_I2CDR);
> > + count = read_index;
> > + } else {
> > + count = -ETIME;
> > + }
> > +
> > + }
> > + } else {
> > + count = -ETIME;
> > + pch_stop(adap);
> > + }
> > +
> > + return count;
> > +}
>
> > (...)
> > +/**
> > + * pch_handler_ch0() - interrupt handler for the PCH I2C controller
> > + * @irq: irq number.
> > + * @pData: cookie passed back to the handler function.
> > + */
> > +static irqreturn_t pch_handler_ch0(int irq, void *pData)
> > +{
> > + s32 reg_val;
> > +
> > + struct i2c_algo_pch_data *adap_data = (struct i2c_algo_pch_data *)pData;
> > + void __iomem *p = adap_data->pch_base_address;
> > + u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE);
> > +
> > + if (mode == NORMAL_MODE) {
>
> No.
>
> if (mode != NORMAL_MODE) {
> dev_err(...)
> return IRQ_NONE;
> }
>
> Then de-indent the rest and remove the else clause.
>
> > + reg_val = ioread32(p + PCH_I2CSR);
> > + if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
> > + pch_cb_ch0(adap_data);
> > + else
> > + goto err_out;
> > + } else {
> > + dev_err(adap_data->pch_adapter.dev.parent,
> > + "%s I2C mode is not supported\n", __func__);
> > + goto err_out;
> > + }
> > + return IRQ_HANDLED;
> > +
> > +err_out:
> > + return IRQ_NONE;
> > +}
>
> > (...)
> > +/**
> > + * pch_xfer() - Reading adnd writing data through I2C bus
> > + * @i2c_adap: Pointer to the struct i2c_adapter.
> > + * @msgs: Pointer to i2c_msg structure.
> > + * @num: number of messages.
> > + */
> > +static s32 pch_xfer(struct i2c_adapter *i2c_adap,
> > + struct i2c_msg *msgs, s32 num)
> > +{
> > + struct i2c_msg *pmsg;
> > + u32 i;
> > + u32 status;
> > + u32 msglen;
> > + u32 subaddrlen;
> > + s32 ret;
> > +
> > + struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
> > +
> > + ret = mutex_lock_interruptible(&pch_mutex);
> > + if (ret) {
> > + ret = -ERESTARTSYS;
> > + goto return_err_nomutex;
> > + }
> > + if (adap->p_adapter_info->pch_suspended == false) {
>
> No.
>
> if (adap->p_adapter_info->pch_suspended) {
> mutex_unlock(&pch_nomutex);
> return -EBUSY;
> }
>
> De-indent the rest and remove the else clause.
>
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "%s adap->p_adapter_info->pch_suspended is %d\n",
> > + __func__, adap->p_adapter_info->pch_suspended);
> > + /* transfer not completed */
> > + adap->pch_xfer_in_progress = true;
> > +
> > + ret = -EBUSY;
> > + for (i = 0; i < num; i++) {
> > + pmsg = &msgs[i];
> > + pmsg->flags |= adap->pch_buff_mode_en;
> > + status = pmsg->flags;
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "After invoking I2C_MODE_SEL :flag= 0x%x\n",
> > + status);
> > + /* calculate sub address length and message length */
> > + /* these are applicable only for buffer mode */
> > + subaddrlen = pmsg->buf[0];
> > + /* calculate actual message length excluding
> > + * the sub address fields */
> > + msglen = (pmsg->len) - (subaddrlen + 1);
> > + if (status & (I2C_M_RD)) {
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "%s invoking pch_readbytes\n",
> > + __func__);
> > + ret = pch_readbytes(i2c_adap, pmsg,
> > + (i + 1 == num),
> > + (i == 0));
> > + } else {
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "%s invoking pch_writebytes\n",
> > + __func__);
> > + ret = pch_writebytes(i2c_adap, pmsg,
> > + (i + 1 == num),
> > + (i == 0));
> > + }
> > +
> > + }
> > +
> > + adap->pch_xfer_in_progress = false; /* transfer completed */
> > +
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "adap->pch_xfer_in_progress is %d\n",
> > + adap->pch_xfer_in_progress);
> > + } else {
> > + ret = -EBUSY;
> > + }
> > +
> > + mutex_unlock(&pch_mutex);
> > +return_err_nomutex:
> > + dev_dbg(adap->pch_adapter.dev.parent, "%s return:%d\n\n\n\n",
> > + __func__, ret);
> > + return ret;
> > +}
>
> > (...)
> > +static int __devinit pch_probe(struct pci_dev *pdev,
> > + const struct pci_device_id *id)
> > +{
> > + int i;
> > + void __iomem *base_addr;
> > + s32 ret;
> > + struct adapter_info *adap_info =
> > + kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
> > +
> > + dev_dbg(&pdev->dev, "Enterred in %s\n", __func__);
> > +
> > + if (adap_info == NULL) {
> > + dev_err(&pdev->dev, "Memory allocation failed FAILED");
> > + ret = -ENOMEM;
> > + goto return_err;
>
> Just
> return -ENOMEM;
>
> Goto construction unnecessary here.
>
> > (...)
> > +#ifdef CONFIG_PM
> > +static int pch_suspend(struct pci_dev *pdev, pm_message_t state)
> > +{
> > + int i;
> > + int ret;
> > +
> > + struct adapter_info *adap_info = pci_get_drvdata(pdev);
> > + void __iomem *p = adap_info->pch_data[0].pch_base_address;
> > +
> > + adap_info->pch_suspended = true;
> > +
> > + for (i = 0; i < PCH_MAX_CHN; i++) {
> > + while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
> > + /* It is assumed that any pending transfer will
> > + * be completed after the delay
> > + */
> > + msleep(1);
> > + }
>
> The comment seems to be a lie. It is not assumed that it will
> be completed at all, because you're sleeping repeatedly until all
> transfers are completed.
>
> What you are doing is you are waiting for channel zero to
> complete transfers, then channel 1 etc up to channel PCH_MAX_CHN.
>
> > + /* Disable the i2c interrupts */
> > + pch_disbl_int(&adap_info->pch_data[i]);
> > + }
> > +
> > + dev_dbg(&pdev->dev,
> > + "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
> > + "invoked function pch_disbl_int successfully\n",
> > + ioread32(p + 0x08),
> > + ioread32(p + 0x30),
> > + ioread32(p + 0x44));
> > +
> > + ret = pci_save_state(pdev);
> > +
> > + if (ret) {
> > + dev_err(&pdev->dev, "pci_save_state failed\n");
> > + return ret;
> > + }
> > +
> > + pci_enable_wake(pdev, PCI_D3hot, 0);
> > + pci_disable_device(pdev);
> > + pci_set_power_state(pdev, pci_choose_state(pdev, state));
> > +
> > + return 0;
> > +}
>
>
> Yours,
> Linus Walleij
Thanks, Ohtake(OKISemi)
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-03 3:12 ` Masayuki Ohtake
0 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtake @ 2010-09-03 3:12 UTC (permalink / raw)
To: Linus Walleij
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Ralf Baechle, srinidhi kasagar,
linux-i2c-u79uwXL29TY76Z2rM5mHXA, ML linux-kernel,
Wang Yong Y", Wang Qi", Andrew",
arjan-VuQAYsv1563Yd54FQh9/CA, Tomoya MORINAGA, Arnd Bergmann
> ----- Original Message -----
> From: "Linus Walleij" <linus.ml.walleij-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> To: "Masayuki Ohtak" <masa-korg-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>
> Cc: "Jean Delvare (PC drivers, core)" <khali-PUYAD+kWke1g9hUCZPvPmw@public.gmane.org>; "Ben Dooks (embedded platforms)" <ben-linux-elnMNo+KYs3YtjvyW6yDsg@public.gmane.org>;
"Crane Cai" <crane.cai-5C7GfCeVMHo@public.gmane.org>; "Samuel Ortiz" <sameo-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>; "Ralf Baechle" <ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>; "srinidhi
kasagar" <srinidhi.kasagar-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>; <linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>; <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>; "Wang Yong Y""
<yong.y.wang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>; "Wang Qi"" <qi.wang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>; "Andrew"" <andrew.chih.howe.khor-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>;
<arjan-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>; "Tomoya MORINAGA" <morinaga526-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>; "Arnd Bergmann" <arnd-r2nGTMty4D4@public.gmane.org>
> Sent: Thursday, September 02, 2010 4:44 AM
> Subject: Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
>
>
> 2010/9/1 Masayuki Ohtak <masa-korg-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>:
>
> > I2C driver of Topcliff PCH
> > (...)
> > +++ b/drivers/i2c/busses/i2c-pch.c
> > (...)
> > +/**
> > + * pch_wait_for_bus_idle() - check the status of bus.
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + * @timeout: waiting time counter (us).
> > + */
> > +static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
> > + s32 timeout)
> > +{
> > + void __iomem *p = adap->pch_base_address;
> > +
> > + /* MAX timeout value is timeout*1000*1000nsec */
> > + ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
> > + do {
> > + if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
> > + break;
> > + msleep(1);
> > + } while (ktime_lt(ktime_get(), ns_val));
> > +
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "%s : I2CSR = %x\n", __func__, ioread32(p + PCH_I2CSR));
> > +
> > + if (timeout == 0) {
> > + dev_err(adap->pch_adapter.dev.parent,
> > + "%s :return%d\n", __func__, -ETIME);
>
> Why not just return -ETIME; here?
>
> > + } else {
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "%s : return %d\n", __func__, 0);
> > + }
>
> Delete this else clause, who is interested in return 0???
>
> > + return ((timeout <= 0) ? (-ETIME) : (0));
>
> return 0;
>
> > (...)
> > +/**
> > + * pch_wait_for_xfer_complete() - initiates a wait for the tx complete event
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + */
> > +static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
> > +{
> > + s32 ret;
> > + ret = wait_event_interruptible_timeout(pch_event,
> > + (adap->pch_event_flag != 0), msecs_to_jiffies(50));
> > + if (ret < 0)
> > + goto out;
>
> The goto construction is unnecessary, just
>
> return ret;
>
> > +
> > + if (ret == 0) {
> > + ret = -ETIMEDOUT;
> > + goto out;
>
> return -ETIMEDOUT;
>
> > + }
> > +
> > + if (adap->pch_event_flag & I2C_ERROR_MASK) {
> > + ret = -EIO;
> > + dev_err(adap->pch_adapter.dev.parent,
> > + "error bits set: %x\n", adap->pch_event_flag);
> > + goto out;
>
> Skip ret assignment
> return -EIO;
>
> > + }
> > +
> > + adap->pch_event_flag = 0;
> > + ret = 0;
>
> Skip this
>
> > +out:
> > + return ret;
>
> return 0;
>
> > +}
> > (...)
> > +/**
> > + * pch_getack() - to confirm ACK/NACK
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + */
> > +static s32 pch_getack(struct i2c_algo_pch_data *adap)
> > +{
> > + u32 reg_val;
> > + void __iomem *p = adap->pch_base_address;
> > + reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
> > +
> > + if (reg_val == 0)
> > + dev_dbg(adap->pch_adapter.dev.parent, "%s : return 0\n",
> > + __func__);
> > + else
> > + dev_dbg(adap->pch_adapter.dev.parent, "%s : return%d\n",
> > + __func__, -EPROTO);
> > +
> > + return (((reg_val) == 0) ? (0) : (-EPROTO));
>
> Refactor this like the other function, no weirdo debug prints
> return 0;
>
> > +}
> > (...)
> > +/**
> > + * pch_writebytes() - write data to I2C bus in normal mode
> > + * @i2c_adap: Pointer to the struct i2c_adapter.
> > + * @last: specifies whether last message or not.
> > + * In the case of compound mode it will be 1 for last message,
> > + * otherwise 0.
> > + * @first: specifies whether first message or not.
> > + * 1 for first message otherwise 0.
> > + */
> > +static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
> > + u32 last, u32 first)
> > +{
> > + struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
> > + u8 *buf;
> > + u32 length;
> > + u32 addr;
> > + u32 addr_2_msb;
> > + u32 addr_8_lsb;
> > + s32 wrcount;
>
> You don't assign anything to wrcount...
>
> > + void __iomem *p = adap->pch_base_address;
> > + length = msgs->len;
> > + buf = msgs->buf;
> > + addr = msgs->addr;
> > + /* enable master tx */
> > + pch_setbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
> > +
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "%s : I2CCTL = %x msgs->len = %d\n", __func__,
> > + ioread32(p + PCH_I2CCTL), length);
> > +
> > + if (first) {
> > + if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
> > + return -ETIME;
> > + }
> > +
> > + if (msgs->flags & I2C_M_TEN) {
> > + addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
> > + iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
> > + if (first)
> > + pch_start(adap);
> > + if ((pch_wait_for_xfer_complete(adap) == 0) &&
> > + (pch_getack(adap) == 0)) {
> > + addr_8_lsb = (addr & I2C_ADDR_MSK);
> > + iowrite32(addr_8_lsb, p + PCH_I2CDR);
> > + } else {
> > + pch_stop(adap);
> > + return -ETIME;
> > + }
> > + } else {
> > + /* set 7 bit slave address and R/W bit as 0 */
> > + iowrite32(addr << 1, p + PCH_I2CDR);
> > + if (first)
> > + pch_start(adap);
> > + }
> > +
> > + if ((pch_wait_for_xfer_complete(adap) == 0) &&
> > + (pch_getack(adap) == 0)) {
> > + for (wrcount = 0; wrcount < length; ++wrcount) {
>
> ...but it is only conditionally used here...
>
> > + /* write buffer value to I2C data register */
> > + iowrite32(buf[wrcount], p + PCH_I2CDR);
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "%s : writing %x to Data register\n",
> > + __func__, buf[wrcount]);
> > +
> > + if (pch_wait_for_xfer_complete(adap) != 0) {
> > + wrcount = -ETIME;
> > + break;
> > + }
> > +
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "%s return %d", __func__, 0);
> > +
> > + if (pch_getack(adap)) {
> > + wrcount = -ETIME;
> > + break;
> > + }
> > + }
> > +
> > + /* check if this is the last message */
> > + if (last)
> > + pch_stop(adap);
> > + else
> > + pch_repstart(adap);
> > + } else {
> > + pch_stop(adap);
> > + }
> > +
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "%s return=%d\n", __func__, wrcount);
> > +
> > + return wrcount;
>
> ...and then you return it, leading to a possibly unassigned state.
>
> > +}
> > (...)
> > +/**
> > + * pch_readbytes() - read data from I2C bus in normal mode.
> > + * @i2c_adap: Pointer to the struct i2c_adapter.
> > + * @msgs: Pointer to i2c_msg structure.
> > + * @last: specifies whether last message or not.
> > + * @first: specifies whether first message or not.
> > + */
> > +s32 pch_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
> > + u32 last, u32 first)
> > +{
> > + struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
> > +
> > + u8 *buf;
> > + u32 count;
>
> Same problem here. Initialize to 0.
When I submit other patch to upstream,
a maintainer said "variable shouldn't initialize to 0".
Thus, we don't do.
Can you admit above?
>
> > + u32 length;
> > + u32 addr;
> > + u32 addr_2_msb;
> > + void __iomem *p = adap->pch_base_address;
> > + length = msgs->len;
> > + buf = msgs->buf;
> > + addr = msgs->addr;
> > +
> > + /* enable master reception */
> > + pch_clrbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
> > +
> > + if (first) {
> > + if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
> > + return -ETIME;
> > + }
> > +
> > + if (msgs->flags & I2C_M_TEN) {
> > + addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
> > + iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
> > +
> > + } else {
> > + /* 7 address bits + R/W bit */
> > + addr = (((addr) << 1) | (I2C_RD));
> > + iowrite32(addr, p + PCH_I2CDR);
> > + }
> > +
> > + /* check if it is the first message */
> > + if (first)
> > + pch_start(adap);
> > +
> > + if ((pch_wait_for_xfer_complete(adap) == 0)
> > + && (pch_getack(adap) == 0)) {
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "%s return %d", __func__, 0);
> > +
> > + if (length == 0) {
> > + pch_stop(adap);
> > + ioread32(p + PCH_I2CDR); /* Dummy read needs */
> > +
> > + count = length;
> > + } else {
> > + int read_index;
> > + int loop;
> > + pch_sendack(adap);
> > +
> > + /* Dummy read */
> > + for (loop = 1, read_index = 0; loop < length; loop++) {
> > + buf[read_index] = ioread32(p + PCH_I2CDR);
> > +
> > + if (loop != 1)
> > + read_index++;
> > +
> > + if (pch_wait_for_xfer_complete(adap) != 0) {
> > + pch_stop(adap);
> > + return -ETIME;
> > + }
> > + } /* end for */
> > +
> > + pch_sendnack(adap);
> > +
> > + buf[read_index] = ioread32(p + PCH_I2CDR);
> > +
> > + if (length != 1)
> > + read_index++;
> > +
> > + if (pch_wait_for_xfer_complete(adap) == 0) {
> > + if (last)
> > + pch_stop(adap);
> > + else
> > + pch_repstart(adap);
> > +
> > + buf[read_index++] = ioread32(p + PCH_I2CDR);
> > + count = read_index;
> > + } else {
> > + count = -ETIME;
> > + }
> > +
> > + }
> > + } else {
> > + count = -ETIME;
> > + pch_stop(adap);
> > + }
> > +
> > + return count;
> > +}
>
> > (...)
> > +/**
> > + * pch_handler_ch0() - interrupt handler for the PCH I2C controller
> > + * @irq: irq number.
> > + * @pData: cookie passed back to the handler function.
> > + */
> > +static irqreturn_t pch_handler_ch0(int irq, void *pData)
> > +{
> > + s32 reg_val;
> > +
> > + struct i2c_algo_pch_data *adap_data = (struct i2c_algo_pch_data *)pData;
> > + void __iomem *p = adap_data->pch_base_address;
> > + u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE);
> > +
> > + if (mode == NORMAL_MODE) {
>
> No.
>
> if (mode != NORMAL_MODE) {
> dev_err(...)
> return IRQ_NONE;
> }
>
> Then de-indent the rest and remove the else clause.
>
> > + reg_val = ioread32(p + PCH_I2CSR);
> > + if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
> > + pch_cb_ch0(adap_data);
> > + else
> > + goto err_out;
> > + } else {
> > + dev_err(adap_data->pch_adapter.dev.parent,
> > + "%s I2C mode is not supported\n", __func__);
> > + goto err_out;
> > + }
> > + return IRQ_HANDLED;
> > +
> > +err_out:
> > + return IRQ_NONE;
> > +}
>
> > (...)
> > +/**
> > + * pch_xfer() - Reading adnd writing data through I2C bus
> > + * @i2c_adap: Pointer to the struct i2c_adapter.
> > + * @msgs: Pointer to i2c_msg structure.
> > + * @num: number of messages.
> > + */
> > +static s32 pch_xfer(struct i2c_adapter *i2c_adap,
> > + struct i2c_msg *msgs, s32 num)
> > +{
> > + struct i2c_msg *pmsg;
> > + u32 i;
> > + u32 status;
> > + u32 msglen;
> > + u32 subaddrlen;
> > + s32 ret;
> > +
> > + struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
> > +
> > + ret = mutex_lock_interruptible(&pch_mutex);
> > + if (ret) {
> > + ret = -ERESTARTSYS;
> > + goto return_err_nomutex;
> > + }
> > + if (adap->p_adapter_info->pch_suspended == false) {
>
> No.
>
> if (adap->p_adapter_info->pch_suspended) {
> mutex_unlock(&pch_nomutex);
> return -EBUSY;
> }
>
> De-indent the rest and remove the else clause.
>
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "%s adap->p_adapter_info->pch_suspended is %d\n",
> > + __func__, adap->p_adapter_info->pch_suspended);
> > + /* transfer not completed */
> > + adap->pch_xfer_in_progress = true;
> > +
> > + ret = -EBUSY;
> > + for (i = 0; i < num; i++) {
> > + pmsg = &msgs[i];
> > + pmsg->flags |= adap->pch_buff_mode_en;
> > + status = pmsg->flags;
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "After invoking I2C_MODE_SEL :flag= 0x%x\n",
> > + status);
> > + /* calculate sub address length and message length */
> > + /* these are applicable only for buffer mode */
> > + subaddrlen = pmsg->buf[0];
> > + /* calculate actual message length excluding
> > + * the sub address fields */
> > + msglen = (pmsg->len) - (subaddrlen + 1);
> > + if (status & (I2C_M_RD)) {
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "%s invoking pch_readbytes\n",
> > + __func__);
> > + ret = pch_readbytes(i2c_adap, pmsg,
> > + (i + 1 == num),
> > + (i == 0));
> > + } else {
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "%s invoking pch_writebytes\n",
> > + __func__);
> > + ret = pch_writebytes(i2c_adap, pmsg,
> > + (i + 1 == num),
> > + (i == 0));
> > + }
> > +
> > + }
> > +
> > + adap->pch_xfer_in_progress = false; /* transfer completed */
> > +
> > + dev_dbg(adap->pch_adapter.dev.parent,
> > + "adap->pch_xfer_in_progress is %d\n",
> > + adap->pch_xfer_in_progress);
> > + } else {
> > + ret = -EBUSY;
> > + }
> > +
> > + mutex_unlock(&pch_mutex);
> > +return_err_nomutex:
> > + dev_dbg(adap->pch_adapter.dev.parent, "%s return:%d\n\n\n\n",
> > + __func__, ret);
> > + return ret;
> > +}
>
> > (...)
> > +static int __devinit pch_probe(struct pci_dev *pdev,
> > + const struct pci_device_id *id)
> > +{
> > + int i;
> > + void __iomem *base_addr;
> > + s32 ret;
> > + struct adapter_info *adap_info =
> > + kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
> > +
> > + dev_dbg(&pdev->dev, "Enterred in %s\n", __func__);
> > +
> > + if (adap_info == NULL) {
> > + dev_err(&pdev->dev, "Memory allocation failed FAILED");
> > + ret = -ENOMEM;
> > + goto return_err;
>
> Just
> return -ENOMEM;
>
> Goto construction unnecessary here.
>
> > (...)
> > +#ifdef CONFIG_PM
> > +static int pch_suspend(struct pci_dev *pdev, pm_message_t state)
> > +{
> > + int i;
> > + int ret;
> > +
> > + struct adapter_info *adap_info = pci_get_drvdata(pdev);
> > + void __iomem *p = adap_info->pch_data[0].pch_base_address;
> > +
> > + adap_info->pch_suspended = true;
> > +
> > + for (i = 0; i < PCH_MAX_CHN; i++) {
> > + while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
> > + /* It is assumed that any pending transfer will
> > + * be completed after the delay
> > + */
> > + msleep(1);
> > + }
>
> The comment seems to be a lie. It is not assumed that it will
> be completed at all, because you're sleeping repeatedly until all
> transfers are completed.
>
> What you are doing is you are waiting for channel zero to
> complete transfers, then channel 1 etc up to channel PCH_MAX_CHN.
>
> > + /* Disable the i2c interrupts */
> > + pch_disbl_int(&adap_info->pch_data[i]);
> > + }
> > +
> > + dev_dbg(&pdev->dev,
> > + "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
> > + "invoked function pch_disbl_int successfully\n",
> > + ioread32(p + 0x08),
> > + ioread32(p + 0x30),
> > + ioread32(p + 0x44));
> > +
> > + ret = pci_save_state(pdev);
> > +
> > + if (ret) {
> > + dev_err(&pdev->dev, "pci_save_state failed\n");
> > + return ret;
> > + }
> > +
> > + pci_enable_wake(pdev, PCI_D3hot, 0);
> > + pci_disable_device(pdev);
> > + pci_set_power_state(pdev, pci_choose_state(pdev, state));
> > +
> > + return 0;
> > +}
>
>
> Yours,
> Linus Walleij
Thanks, Ohtake(OKISemi)
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
2010-09-07 23:55 ` Ben Dooks
@ 2010-09-08 12:06 ` Masayuki Ohtake
-1 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtake @ 2010-09-08 12:06 UTC (permalink / raw)
To: Ben Dooks
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c, linux-kernel, joe, yong.y.wang,
qi.wang, andrew.chih.howe.khor, arjan, Tomoya MORINAGA,
Arnd Bergmann
----- Original Message -----
From: "Ben Dooks" <ben-i2c@fluff.org>
To: "Masayuki Ohtak" <masa-korg@dsn.okisemi.com>
Cc: "Jean Delvare (PC drivers, core)" <khali@linux-fr.org>; "Ben Dooks (embedded platforms)" <ben-linux@fluff.org>;
"Crane Cai" <crane.cai@amd.com>; "Samuel Ortiz" <sameo@linux.intel.com>; "Linus Walleij" <linus.walleij@stericsson.com>;
"Ralf Baechle" <ralf@linux-mips.org>; "srinidhi kasagar" <srinidhi.kasagar@stericsson.com>; <linux-i2c@vger.kernel.org>;
<linux-kernel@vger.kernel.org>; <joe@perches.com>; <yong.y.wang@intel.com>; <qi.wang@intel.com>;
<andrew.chih.howe.khor@intel.com>; <arjan@linux.intel.com>; "Tomoya MORINAGA" <morinaga526@dsn.okisemi.com>; "Arnd
Bergmann" <arnd@arndb.de>
Sent: Wednesday, September 08, 2010 8:55 AM
Subject: Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
> On Fri, Sep 03, 2010 at 07:19:44PM +0900, Masayuki Ohtak wrote:
> > I2C driver of Topcliff PCH
> >
> > Topcliff PCH is the platform controller hub that is going to be used in
> > Intel's upcoming general embedded platform. All IO peripherals in
> > Topcliff PCH are actually devices sitting on AMBA bus.
> > Topcliff PCH has I2C I/F. Using this I/F, it is able to access system
> > devices connected to I2C.
> >
> > Signed-off-by: Masayuki Ohtake <masa-korg@dsn.okisemi.com>
> > Reviewed-by: Linus Walleij <linus.walleij@stericsson.com>
> > ---
> > drivers/i2c/busses/Kconfig | 18 +
> > drivers/i2c/busses/Makefile | 1 +
> > drivers/i2c/busses/i2c-pch.c | 944 ++++++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 963 insertions(+), 0 deletions(-)
> > create mode 100644 drivers/i2c/busses/i2c-pch.c
> >
> > diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> > index bceafbf..c5db1e7 100644
> > --- a/drivers/i2c/busses/Kconfig
> > +++ b/drivers/i2c/busses/Kconfig
> > @@ -613,6 +613,24 @@ config I2C_XILINX
> > This driver can also be built as a module. If so, the module
> > will be called xilinx_i2c.
> >
> > +config PCH_I2C
> > + tristate "PCH I2C of Intel Topcliff"
> > + depends on PCI
> > + help
> > + This driver is for PCH(Platform controller Hub) I2C of Topcliff which
> > + is an IOH(Input/Output Hub) for x86 embedded processor.
> > + This driver can access PCH I2C bus device.
> > +
> > +config PCH_I2C_CH_COUNT
> > + int "PCH I2C the number of channel count"
> > + range 1 2
> > + depends on PCH_I2C
> > + help
> > + This driver is for PCH(Platform controller Hub) I2C of Topcliff which
> > + is an IOH(Input/Output Hub) for x86 embedded processor.
> > + The number of I2C buses/channels supported by the PCH I2C controller.
> > + PCH I2C of Topcliff supports only one channel.
> > +
> > comment "External I2C/SMBus adapter drivers"
> >
> > config I2C_PARPORT
> > diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
> > index 936880b..aa04135 100644
> > --- a/drivers/i2c/busses/Makefile
> > +++ b/drivers/i2c/busses/Makefile
> > @@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
> > obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
> > obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
> > obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
> > +obj-$(CONFIG_PCH_I2C) += i2c-pch.o
> >
> > # External I2C/SMBus adapter drivers
> > obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o
> > diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c
> > new file mode 100644
> > index 0000000..ae55a83
> > --- /dev/null
> > +++ b/drivers/i2c/busses/i2c-pch.c
> > @@ -0,0 +1,944 @@
> > +/*
> > + * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; version 2 of the License.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
> > + */
> > +
> > +#include <linux/module.h>
> > +#include <linux/kernel.h>
> > +#include <linux/delay.h>
> > +#include <linux/init.h>
> > +#include <linux/errno.h>
> > +#include <linux/i2c.h>
> > +#include <linux/fs.h>
> > +#include <linux/io.h>
> > +#include <linux/types.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/jiffies.h>
> > +#include <linux/pci.h>
> > +#include <linux/mutex.h>
> > +#include <linux/ktime.h>
> > +
> > +#define PCH_MAX_CHN CONFIG_PCH_I2C_CH_COUNT /* Maximum I2C channels
> > + available */
> > +#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
> > +#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
> > +#define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
> > +#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
> > +#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
> > +
> > +#define PCH_I2CSADR 0x00 /* I2C slave address register */
> > +#define PCH_I2CCTL 0x04 /* I2C control register */
> > +#define PCH_I2CSR 0x08 /* I2C status register */
> > +#define PCH_I2CDR 0x0C /* I2C data register */
> > +#define PCH_I2CMON 0x10 /* I2C bus monitor register */
> > +#define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
> > +#define PCH_I2CMOD 0x18 /* I2C mode register */
> > +#define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
> > +#define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
> > +#define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
> > +#define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
> > +#define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
> > +#define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
> > +#define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
> > +#define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
> > +#define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
> > +#define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
> > +#define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
> > +#define PCH_I2CTMR 0x48 /* I2C timer register */
> > +#define PCH_I2CSRST 0xFC /* I2C reset register */
> > +#define PCH_I2CNF 0xF8 /* I2C noise filter register */
> > +
> > +#define BUS_IDLE_TIMEOUT 20
> > +#define PCH_I2CCTL_I2CMEN 0x0080
> > +#define TEN_BIT_ADDR_DEFAULT 0xF000
> > +#define TEN_BIT_ADDR_MASK 0xF0
> > +#define PCH_START 0x0020
> > +#define PCH_ESR_START 0x0001
> > +#define PCH_BUFF_START 0x1
> > +#define PCH_REPSTART 0x0004
> > +#define PCH_ACK 0x0008
> > +#define PCH_GETACK 0x0001
> > +#define CLR_REG 0x0
> > +#define I2C_RD 0x1
> > +#define I2CMCF_BIT 0x0080
> > +#define I2CMIF_BIT 0x0002
> > +#define I2CMAL_BIT 0x0010
> > +#define I2CBMFI_BIT 0x0001
> > +#define I2CBMAL_BIT 0x0002
> > +#define I2CBMNA_BIT 0x0004
> > +#define I2CBMTO_BIT 0x0008
> > +#define I2CBMIS_BIT 0x0010
> > +#define I2CESRFI_BIT 0X0001
> > +#define I2CESRTO_BIT 0x0002
> > +#define I2CESRFIIE_BIT 0x1
> > +#define I2CESRTOIE_BIT 0x2
> > +#define I2CBMDZ_BIT 0x0040
> > +#define I2CBMAG_BIT 0x0020
> > +#define I2CMBB_BIT 0x0020
> > +#define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
> > + I2CBMTO_BIT | I2CBMIS_BIT)
> > +#define I2C_ADDR_MSK 0xFF
> > +#define I2C_MSB_2B_MSK 0x300
> > +#define FAST_MODE_CLK 400
> > +#define FAST_MODE_EN 0x0001
> > +#define SUB_ADDR_LEN_MAX 4
> > +#define BUF_LEN_MAX 32
> > +#define PCH_BUFFER_MODE 0x1
> > +#define EEPROM_SW_RST_MODE 0x0002
> > +#define NORMAL_INTR_ENBL 0x0300
> > +#define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
> > +#define EEPROM_RST_INTR_DISBL 0x0
> > +#define BUFFER_MODE_INTR_ENBL 0x001F
> > +#define BUFFER_MODE_INTR_DISBL 0x0
> > +#define NORMAL_MODE 0x0
> > +#define BUFFER_MODE 0x1
> > +#define EEPROM_SR_MODE 0x2
> > +#define I2C_TX_MODE 0x0010
> > +#define PCH_BUF_TX 0xFFF7
> > +#define PCH_BUF_RD 0x0008
> > +#define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
> > + I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
> > +#define I2CMAL_EVENT 0x0001
> > +#define I2CMCF_EVENT 0x0002
> > +#define I2CBMFI_EVENT 0x0004
> > +#define I2CBMAL_EVENT 0x0008
> > +#define I2CBMNA_EVENT 0x0010
> > +#define I2CBMTO_EVENT 0x0020
> > +#define I2CBMIS_EVENT 0x0040
> > +#define I2CESRFI_EVENT 0x0080
> > +#define I2CESRTO_EVENT 0x0100
> > +#define PCI_DEVICE_ID_PCH_I2C 0x8817
> > +
> > +#define pch_dbg(adap, fmt, arg...) \
> > + dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
> > +
> > +#define pch_err(adap, fmt, arg...) \
> > + dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
> > +
> > +#define pch_pci_err(pdev, fmt, arg...) \
> > + dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
> > +
> > +#define pch_pci_dbg(pdev, fmt, arg...) \
> > + dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
> > +
> > +/**
> > + * struct i2c_algo_pch_data - for I2C driver functionalities
> > + * @p_adapter_info: stores the reference to adapter_info structure
> > + * @pch_adapter: stores the reference to i2c_adapter structure
> > + * @pch_base_address: specifies the remapped base address
> > + * @pch_buff_mode_en: specifies if buffer mode is enabled
> > + * @pch_event_flag: specifies occurrence of interrupt events
> > + * @pch_xfer_in_progress: specifies whether the transfer is completed
> > + */
> > +struct i2c_algo_pch_data {
> > + struct adapter_info *p_adapter_info;
> > + struct i2c_adapter pch_adapter;
> > + void __iomem *pch_base_address;
> > + int pch_buff_mode_en;
> > + u32 pch_event_flag;
> > + bool pch_xfer_in_progress;
> > +};
> > +
> > +/**
> > + * struct adapter_info - This structure holds the adapter information for the
> > + PCH i2c controller
> > + * @pch_data: stores a list of i2c_algo_pch_data
> > + * @pch_suspended: specifies whether the system is suspended or not
> > + * perhaps with more lines and words.
> > + *
> > + * pch_data has as many elements as maximum I2C channels
> > + */
> > +struct adapter_info {
> > + struct i2c_algo_pch_data pch_data[PCH_MAX_CHN];
> > + bool pch_suspended;
> > +};
> > +
> > +
> > +static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
> > +static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
> > +static wait_queue_head_t pch_event;
> > +static DEFINE_MUTEX(pch_mutex);
> > +
> > +static struct pci_device_id __devinitdata pch_pcidev_id[] = {
> > + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_I2C)},
> > + {0,}
> > +};
> > +
> > +static irqreturn_t pch_handler_ch0(int irq, void *pData);
> > +static irqreturn_t(*pch_handler_list[PCH_MAX_CHN]) (int irq, void *pData) = {
> > + pch_handler_ch0,
> > +};
> > +
> > +static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
> > +{
> > + u32 val;
> > + val = ioread32(addr + offset);
> > + val |= bitmask;
> > + iowrite32(val, addr + offset);
> > +}
> > +
> > +static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
> > +{
> > + u32 val;
> > + val = ioread32(addr + offset);
> > + val &= (~bitmask);
> > + iowrite32(val, addr + offset);
> > +}
> > +
> > +/**
> > + * pch_init() - hardware initialization of I2C module
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + */
> > +static void pch_init(struct i2c_algo_pch_data *adap)
> > +{
> > + u32 pch_i2cbc;
> > + u32 pch_i2ctmr;
> > + u32 reg_value;
> > + void __iomem *p = adap->pch_base_address;
>
> my personal preference is to put the larger items at the top of the list.
>
> > + /* reset I2C controller */
> > + iowrite32(0x01, p + PCH_I2CSRST);
> > + iowrite32(0x0, p + PCH_I2CSRST);
> > + /* Initialize I2C registers */
> > + iowrite32(CLR_REG, p + PCH_I2CCTL);
> > + iowrite32(CLR_REG, p + PCH_I2CMOD);
> > + iowrite32(CLR_REG, p + PCH_I2CBUFFOR);
> > + iowrite32(CLR_REG, p + PCH_I2CBUFSLV);
> > + iowrite32(CLR_REG, p + PCH_I2CBUFSUB);
> > + iowrite32(CLR_REG, p + PCH_I2CBUFMSK);
> > + iowrite32(CLR_REG, p + PCH_I2CESRFOR);
> > + iowrite32(CLR_REG, p + PCH_I2CESRMSK);
> > + iowrite32(0x21, p + PCH_I2CNF);
> > +
> > + reg_value = PCH_I2CCTL_I2CMEN;
> > + pch_setbit((adap->pch_base_address), PCH_I2CCTL,
> > + PCH_I2CCTL_I2CMEN);
> > +
> > + if (pch_i2c_speed != 400)
> > + pch_i2c_speed = 100;
> > +
> > + if (pch_i2c_speed == FAST_MODE_CLK) {
> > + reg_value |= FAST_MODE_EN;
> > + pch_dbg(adap, "Fast mode enabled\n");
> > + }
> > +
> > + if (pch_clk <= 0 || pch_clk > PCH_MAX_CLK)
> > + pch_clk = 62500;
> > +
> > + pch_i2cbc = ((pch_clk) + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
>
> do you really need the () around pch_clk? there seems to be quite a few
> of these around. you also don't need them around pch_i2c_speed * 4. I would
> like to see these gone.
>
> > + /* Set transfer speed in I2CBC */
> > + iowrite32(pch_i2cbc, p + PCH_I2CBC);
> > +
> > + pch_i2ctmr = (pch_clk) / 8;
> > + iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
> > +
> > + reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
> > + iowrite32(reg_value, p + PCH_I2CCTL);
> > +
> > + pch_dbg(adap,
> > + "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
> > + ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
> > +
> > + init_waitqueue_head(&pch_event);
> > +}
> > +
> > +static inline int ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
> > +{
> > + return cmp1.tv64 < cmp2.tv64;
> > +}
>
> surely this should be with the ktime headers?
You mean should we use keime_sub_ns instead of our ktime_lt ?
>
> > +/**
> > + * pch_wait_for_bus_idle() - check the status of bus.
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + * @timeout: waiting time counter (us).
> > + */
> > +static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
> > + s32 timeout)
> > +{
> > + void __iomem *p = adap->pch_base_address;
> > +
> > + /* MAX timeout value is timeout*1000*1000nsec */
> > + ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
> > + do {
> > + if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
> > + break;
> > + msleep(1);
> > + } while (ktime_lt(ktime_get(), ns_val));
> > +
> > + pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
> > +
> > + if (timeout == 0) {
> > + pch_err(adap, "return%d\n", -ETIME);
>
> how about just printing timedout? would be easier to work out what
> happened.
>
> > + return -ETIME;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * pch_start() - Generate I2C start condition in normal mode.
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + *
> > + * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
> > + */
> > +static void pch_start(struct i2c_algo_pch_data *adap)
> > +{
> > + void __iomem *p = adap->pch_base_address;
> > + pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
> > + pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
>
> again with the ()s.
>
> > +static s32 pch_getack(struct i2c_algo_pch_data *adap)
> > +{
> > + u32 reg_val;
> > + void __iomem *p = adap->pch_base_address;
> > + reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
> > +
> > + if (reg_val != 0) {
> > + pch_err(adap, "return%d\n", -EPROTO);
> > + return -EPROTO;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * pch_stop() - generate stop condition in normal mode.
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + */
> > +static void pch_stop(struct i2c_algo_pch_data *adap)
> > +{
> > + void __iomem *p = adap->pch_base_address;
> > + pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
> > + /* clear the start bit */
> > + pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
> > +}
> > +
> > +/**
> > + * pch_repstart() - generate repeated start condition in normal mode
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + */
> > +static void pch_repstart(struct i2c_algo_pch_data *adap)
> > +{
> > + void __iomem *p = adap->pch_base_address;
> > + pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
> > + pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_REPSTART);
> > +}
> > +
> > +/**
> > + * pch_writebytes() - write data to I2C bus in normal mode
> > + * @i2c_adap: Pointer to the struct i2c_adapter.
> > + * @last: specifies whether last message or not.
> > + * In the case of compound mode it will be 1 for last message,
> > + * otherwise 0.
> > + * @first: specifies whether first message or not.
> > + * 1 for first message otherwise 0.
> > + */
> > +static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
> > + u32 last, u32 first)
> > +{
> > + struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
> > + u8 *buf;
> > + u32 length;
> > + u32 addr;
> > + u32 addr_2_msb;
> > + u32 addr_8_lsb;
> > + s32 wrcount;
> > + void __iomem *p = adap->pch_base_address;
> > + length = msgs->len;
> > + buf = msgs->buf;
> > + addr = msgs->addr;
>
> blank line between decls and code please.
>
> > + /* enable master tx */
> > + pch_setbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
>
> this is the last warning on ()s...
>
> > + pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
> > + length);
> > +
> > + if (first) {
> > + if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
> > + return -ETIME;
> > + }
>
> hmm, -ETIME versus -ETIMEDOUT elsewhere?
>
> > + if (msgs->flags & I2C_M_TEN) {
> > + addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
> > + iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
> > + if (first)
> > + pch_start(adap);
> > + if ((pch_wait_for_xfer_complete(adap) == 0) &&
> > + (pch_getack(adap) == 0)) {
>
> and no need for most of the ()s here...
>
> > + addr_8_lsb = (addr & I2C_ADDR_MSK);
> > + iowrite32(addr_8_lsb, p + PCH_I2CDR);
> > + } else {
> > + pch_stop(adap);
> > + return -ETIME;
> > + }
> > + } else {
> > + /* set 7 bit slave address and R/W bit as 0 */
> > + iowrite32(addr << 1, p + PCH_I2CDR);
> > + if (first)
> > + pch_start(adap);
> > + }
> > +
> > + if ((pch_wait_for_xfer_complete(adap) == 0) &&
> > + (pch_getack(adap) == 0)) {
> > + for (wrcount = 0; wrcount < length; ++wrcount) {
> > + /* write buffer value to I2C data register */
> > + iowrite32(buf[wrcount], p + PCH_I2CDR);
> > + pch_dbg(adap, "writing %x to Data register\n",
> > + buf[wrcount]);
> > +
> > + if (pch_wait_for_xfer_complete(adap) != 0)
> > + return -ETIME;
> > +
> > + if (pch_getack(adap))
> > + return -ETIME;
>
> you sure it isn't -EIO here if ack problem?
>
> > + }
> > +
> > + /* check if this is the last message */
> > + if (last)
> > + pch_stop(adap);
> > + else
> > + pch_repstart(adap);
> > + } else {
> > + pch_stop(adap);
> > + return -EIO;
> > + }
> > +
> > + pch_dbg(adap, "return=%d\n", wrcount);
> > +
> > + return wrcount;
> > +}
> > +
> > +/**
> > + * pch_sendack() - send ACK
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + */
> > +static void pch_sendack(struct i2c_algo_pch_data *adap)
> > +{
> > + void __iomem *p = adap->pch_base_address;
> > + pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
> > + pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
> > +}
> > +
> > +/**
> > + * pch_sendnack() - send NACK
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + */
> > +static void pch_sendnack(struct i2c_algo_pch_data *adap)
> > +{
> > + void __iomem *p = adap->pch_base_address;
> > + pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
> > + pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
> > +}
> > +
> > +/**
> > + * pch_readbytes() - read data from I2C bus in normal mode.
> > + * @i2c_adap: Pointer to the struct i2c_adapter.
> > + * @msgs: Pointer to i2c_msg structure.
> > + * @last: specifies whether last message or not.
> > + * @first: specifies whether first message or not.
> > + */
> > +s32 pch_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
> > + u32 last, u32 first)
> > +{
> > + struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
> > +
> > + u8 *buf;
> > + u32 count;
> > + u32 length;
> > + u32 addr;
> > + u32 addr_2_msb;
> > + void __iomem *p = adap->pch_base_address;
> > + length = msgs->len;
> > + buf = msgs->buf;
> > + addr = msgs->addr;
> > +
> > + /* enable master reception */
> > + pch_clrbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
> > +
> > + if (first) {
> > + if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
> > + return -ETIME;
> > + }
> > +
> > + if (msgs->flags & I2C_M_TEN) {
> > + addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
> > + iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
> > +
> > + } else {
> > + /* 7 address bits + R/W bit */
> > + addr = (((addr) << 1) | (I2C_RD));
> > + iowrite32(addr, p + PCH_I2CDR);
> > + }
> > +
> > + /* check if it is the first message */
> > + if (first)
> > + pch_start(adap);
> > +
> > + if ((pch_wait_for_xfer_complete(adap) == 0) &&
> > + (pch_getack(adap) == 0)) {
> > + pch_dbg(adap, "return %d\n", 0);
> > +
> > + if (length == 0) {
> > + pch_stop(adap);
> > + ioread32(p + PCH_I2CDR); /* Dummy read needs */
> > +
> > + count = length;
> > + } else {
> > + int read_index;
> > + int loop;
> > + pch_sendack(adap);
> > +
> > + /* Dummy read */
> > + for (loop = 1, read_index = 0; loop < length; loop++) {
> > + buf[read_index] = ioread32(p + PCH_I2CDR);
> > +
> > + if (loop != 1)
> > + read_index++;
> > +
> > + if (pch_wait_for_xfer_complete(adap) != 0) {
> > + pch_stop(adap);
> > + return -ETIME;
> > + }
> > + } /* end for */
> > +
> > + pch_sendnack(adap);
> > +
> > + buf[read_index] = ioread32(p + PCH_I2CDR);
> > +
> > + if (length != 1)
> > + read_index++;
> > +
> > + if (pch_wait_for_xfer_complete(adap) == 0) {
> > + if (last)
> > + pch_stop(adap);
> > + else
> > + pch_repstart(adap);
> > +
> > + buf[read_index++] = ioread32(p + PCH_I2CDR);
> > + count = read_index;
> > + } else {
> > + count = -ETIME;
> > + }
> > +
> > + }
> > + } else {
> > + count = -ETIME;
> > + pch_stop(adap);
> > + }
> > +
> > + return count;
> > +}
> > +
> > +/**
> > + * pch_cb_ch0() - Interrupt handler Call back function
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + */
> > +static void pch_cb_ch0(struct i2c_algo_pch_data *adap)
> > +{
> > + u32 sts;
> > + void __iomem *p = adap->pch_base_address;
> > +
> > + sts = ioread32(p + PCH_I2CSR);
> > + sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
> > + if (I2CMAL_BIT & sts)
> > + adap->pch_event_flag |= I2CMAL_EVENT;
> > +
> > + if (I2CMCF_BIT & sts)
> > + adap->pch_event_flag |= I2CMCF_EVENT;
> > +
> > + /* clear the applicable bits */
> > + pch_clrbit((adap->pch_base_address), PCH_I2CSR, sts);
> > +
> > + pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
> > +
> > + wake_up_interruptible(&pch_event);
> > +}
> > +
> > +/**
> > + * pch_handler_ch0() - interrupt handler for the PCH I2C controller
> > + * @irq: irq number.
> > + * @pData: cookie passed back to the handler function.
> > + */
> > +static irqreturn_t pch_handler_ch0(int irq, void *pData)
> > +{
> > + s32 reg_val;
> > +
> > + struct i2c_algo_pch_data *adap_data = (struct i2c_algo_pch_data *)pData;
> > + void __iomem *p = adap_data->pch_base_address;
> > + u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE);
> > +
> > + if (mode != NORMAL_MODE) {
> > + pch_err(adap_data, "I2C mode is not supported\n");
> > + return IRQ_NONE;
> > + }
> > +
> > + reg_val = ioread32(p + PCH_I2CSR);
> > + if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
> > + pch_cb_ch0(adap_data);
> > + else
> > + return IRQ_NONE;
> > +
> > + return IRQ_HANDLED;
> > +}
> > +#if 0
> > + if (mode == NORMAL_MODE) {
> > + reg_val = ioread32(p + PCH_I2CSR);
> > + if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
> > + pch_cb_ch0(adap_data);
> > + else
> > + goto err_out;
> > + } else {
> > + pch_err(adap_data, "I2C mode is not supported\n");
> > + goto err_out;
> > + }
> > + return IRQ_HANDLED;
> > +
> > +err_out:
> > + return IRQ_NONE;
> > +}
> > +#endif
>
> please, no #if 0. either remove completely or do something with it.
>
> > +/**
> > + * pch_xfer() - Reading adnd writing data through I2C bus
> > + * @i2c_adap: Pointer to the struct i2c_adapter.
> > + * @msgs: Pointer to i2c_msg structure.
> > + * @num: number of messages.
> > + */
> > +static s32 pch_xfer(struct i2c_adapter *i2c_adap,
> > + struct i2c_msg *msgs, s32 num)
> > +{
> > + struct i2c_msg *pmsg;
> > + u32 i;
> > + u32 status;
> > + u32 msglen;
> > + u32 subaddrlen;
> > + s32 ret;
> > +
> > + struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
> > +
> > + ret = mutex_lock_interruptible(&pch_mutex);
> > + if (ret)
> > + return -ERESTARTSYS;
> > +
> > + if (adap->p_adapter_info->pch_suspended) {
> > + mutex_unlock(&pch_mutex);
> > + return -EBUSY;
> > + }
> > +
> > + pch_dbg(adap, "adap->p_adapter_info->pch_suspended is %d\n",
> > + adap->p_adapter_info->pch_suspended);
> > + /* transfer not completed */
> > + adap->pch_xfer_in_progress = true;
> > +
> > + for (i = 0; i < num; i++) {
> > + pmsg = &msgs[i];
> > + pmsg->flags |= adap->pch_buff_mode_en;
> > + status = pmsg->flags;
> > + pch_dbg(adap,
> > + "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
> > + /* calculate sub address length and message length */
> > + /* these are applicable only for buffer mode */
> > + subaddrlen = pmsg->buf[0];
> > + /* calculate actual message length excluding
> > + * the sub address fields */
> > + msglen = (pmsg->len) - (subaddrlen + 1);
> > + if (status & (I2C_M_RD)) {
> > + pch_dbg(adap, "invoking pch_readbytes\n");
> > + ret = pch_readbytes(i2c_adap, pmsg, (i + 1 == num),
> > + (i == 0));
> > + } else {
> > + pch_dbg(adap, "invoking pch_writebytes\n");
> > + ret = pch_writebytes(i2c_adap, pmsg, (i + 1 == num),
> > + (i == 0));
> > + }
> > +
> > + }
> > +
> > + adap->pch_xfer_in_progress = false; /* transfer completed */
> > +
> > + mutex_unlock(&pch_mutex);
> > +
> > + return ret;
> > +}
> > +
> > +/**
> > + * pch_func() - return the functionality of the I2C driver
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + */
> > +static u32 pch_func(struct i2c_adapter *adap)
> > +{
> > + u32 ret;
> > + ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
> > + return ret;
> > +}
>
> how about just return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
>
> > +static struct i2c_algorithm pch_algorithm = {
> > + .master_xfer = pch_xfer,
> > + .functionality = pch_func
> > +};
> > +
> > +/**
> > + * pch_disbl_int() - Disable PCH I2C interrupts
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + */
> > +static void pch_disbl_int(struct i2c_algo_pch_data *adap)
> > +{
> > + void __iomem *p = adap->pch_base_address;
> > +
> > + pch_clrbit((adap->pch_base_address), PCH_I2CCTL,
> > + NORMAL_INTR_ENBL);
> > +
> > + iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
> > +
> > + iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
> > +}
> > +
> > +static int __devinit pch_probe(struct pci_dev *pdev,
> > + const struct pci_device_id *id)
> > +{
> > + int i;
> > + void __iomem *base_addr;
> > + s32 ret;
> > + struct adapter_info *adap_info =
> > + kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
>
> this would be a good case to putting the kzalloc() on a different line
> from the decleration.
>
> > + pch_pci_dbg(pdev, "Entered.\n");
> > +
> > + if (adap_info == NULL) {
> > + pch_pci_err(pdev, "Memory allocation FAILED\n");
> > + return -ENOMEM;
> > + }
> > +
> > + ret = pci_enable_device(pdev);
> > + if (ret) {
> > + pch_pci_err(pdev, "pci_enable_device FAILED\n");
> > + goto err_pci_enable;
> > + }
>
> do you really need to put FAILED in capitals here?
You mean should we use "failed" not "FAILED" ?
>
> > + ret = pci_request_regions(pdev, KBUILD_MODNAME);
> > + if (ret) {
> > + pch_pci_err(pdev, "pci_request_regions FAILED\n");
> > + goto err_pci_req;
> > + }
> > +
> > + base_addr = pci_iomap(pdev, 1, 0);
> > +
> > + if (base_addr == 0) {
>
> surley that would be == NULL?
>
> > + pch_pci_err(pdev, "pci_iomap FAILED\n");
> > + ret = -ENOMEM;
> > + goto err_pci_iomap;
> > + }
> > +
> > + adap_info->pch_suspended = false;
> > +
> > + for (i = 0; i < PCH_MAX_CHN; i++) {
> > + adap_info->pch_data[i].p_adapter_info = adap_info;
>
> looks like a pointer to adap_info->pch_data[i] would make the source
> smaller and a bit easier to read.
This code have already modified.(PCH_MAX_CHN is deleted.)
Please refer the latest our i2c patch.
>
> > + adap_info->pch_data[i].pch_adapter.owner = THIS_MODULE;
> > + adap_info->pch_data[i].pch_adapter.class = I2C_CLASS_HWMON;
> > + strcpy(adap_info->pch_data[i].pch_adapter.name, KBUILD_MODNAME);
> > + adap_info->pch_data[i].pch_adapter.algo = &pch_algorithm;
> > + adap_info->pch_data[i].pch_adapter.algo_data =
> > + &adap_info->pch_data[i];
> > +
> > + /* (i * 0x80) + base_addr; */
> > + adap_info->pch_data[i].pch_base_address = base_addr;
> > +
> > + adap_info->pch_data[i].pch_adapter.dev.parent = &pdev->dev;
> > +
> > + ret = i2c_add_adapter(&(adap_info->pch_data[i].pch_adapter));
> > +
> > + if (ret) {
> > + pch_pci_err(pdev, "i2c_add_adapter FAILED\n");
> > + goto err_i2c_add_adapter;
> > + }
> > +
> > + pch_init(&adap_info->pch_data[i]);
> > + ret = request_irq(pdev->irq, pch_handler_list[i], IRQF_SHARED,
> > + KBUILD_MODNAME, &adap_info->pch_data[i]);
> > + if (ret) {
> > + pch_pci_err(pdev, "request_irq FAILED\n");
> > + goto err_request_irq;
> > + }
> > + }
> > +
> > + pci_set_drvdata(pdev, adap_info);
> > + pch_pci_dbg(pdev, "returns %d.\n", ret);
> > + return 0;
> > +
> > +err_request_irq:
> > + for (i = 0; i < PCH_MAX_CHN; i++)
> > + i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
> > +err_i2c_add_adapter:
> > + pci_iounmap(pdev, base_addr);
> > +err_pci_iomap:
> > + pci_release_regions(pdev);
> > +err_pci_req:
> > + pci_disable_device(pdev);
> > +err_pci_enable:
> > + kfree(adap_info);
> > + return ret;
> > +}
> > +
> > +static void __devexit pch_remove(struct pci_dev *pdev)
> > +{
> > + int i;
> > +
> > + struct adapter_info *adap_info = pci_get_drvdata(pdev);
>
> no need for the blank line.
>
> > +
> > +
> > + for (i = 0; i < PCH_MAX_CHN; i++) {
> > + pch_disbl_int(&adap_info->pch_data[i]);
> > + free_irq(pdev->irq, &adap_info->pch_data[i]);
> > + i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
> > + }
> > +
> > + if (adap_info->pch_data[0].pch_base_address) {
> > + pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
> > + adap_info->pch_data[0].pch_base_address = 0;
> > + }
> > +
> > + pci_set_drvdata(pdev, NULL);
> > +
> > + pci_release_regions(pdev);
> > +
> > + pci_disable_device(pdev);
> > + kfree(adap_info);
> > +}
> > +
> > +#ifdef CONFIG_PM
> > +static int pch_suspend(struct pci_dev *pdev, pm_message_t state)
> > +{
> > + int i;
> > + int ret;
> > +
> > + struct adapter_info *adap_info = pci_get_drvdata(pdev);
> > + void __iomem *p = adap_info->pch_data[0].pch_base_address;
> >
> again, blank line, also see notes on ordering.
>
> > + adap_info->pch_suspended = true;
> > +
> > + for (i = 0; i < PCH_MAX_CHN; i++) {
> > + while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
> > + /* Wait until all channel transfers are completed */
> > + msleep(1);
> > + }
> > + /* Disable the i2c interrupts */
> > + pch_disbl_int(&adap_info->pch_data[i]);
> > + }
> > +
> > + pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
> > + "invoked function pch_disbl_int successfully\n",
> > + ioread32(p + 0x08), ioread32(p + 0x30), ioread32(p + 0x44));
>
> magic numbers being used to ioread32?
>
> > + ret = pci_save_state(pdev);
> > +
> > + if (ret) {
> > + pch_pci_err(pdev, "pci_save_state\n");
> > + return ret;
> > + }
> > +
> > + pci_enable_wake(pdev, PCI_D3hot, 0);
> > + pci_disable_device(pdev);
> > + pci_set_power_state(pdev, pci_choose_state(pdev, state));
> > +
> > + return 0;
> > +}
> > +
> > +static int pch_resume(struct pci_dev *pdev)
> > +{
> > + struct adapter_info *adap_info = pci_get_drvdata(pdev);
> > + int i;
> > +
> > + pci_set_power_state(pdev, PCI_D0);
> > + pci_restore_state(pdev);
> > +
> > + if (pci_enable_device(pdev) < 0) {
> > + pch_pci_err(pdev, "pci_enable_device FAILED in pch_resume\n");
> > + return -EIO;
> > + }
> > +
> > + pci_enable_wake(pdev, PCI_D3hot, 0);
> > +
> > + for (i = 0; i < PCH_MAX_CHN; i++)
> > + pch_init(&adap_info->pch_data[i]);
> > +
> > + adap_info->pch_suspended = false;
> > +
> > + return 0;
> > +}
> > +#else
> > +#define pch_suspend NULL
> > +#define pch_resume NULL
> > +#endif
> > +
> > +static struct pci_driver pch_pcidriver = {
> > + .name = KBUILD_MODNAME,
> > + .id_table = pch_pcidev_id,
> > + .probe = pch_probe,
> > + .remove = __devexit_p(pch_remove),
> > + .suspend = pch_suspend,
> > + .resume = pch_resume
> > +};
> > +
> > +static int __init pch_pci_init(void)
> > +{
> > + return pci_register_driver(&pch_pcidriver);
> > +}
> > +
> > +static void __exit pch_pci_exit(void)
> > +{
> > + pci_unregister_driver(&pch_pcidriver);
> > +}
> > +
> > +MODULE_DESCRIPTION("PCH I2C PCI Driver");
> > +MODULE_LICENSE("GPL");
>
> no MODULE_AUTHOR?
>
> > +module_init(pch_pci_init);
> > +module_exit(pch_pci_exit);
> > +module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
> > +module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
>
Thanks, Ohtake(OKISemi)
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-08 12:06 ` Masayuki Ohtake
0 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtake @ 2010-09-08 12:06 UTC (permalink / raw)
To: Ben Dooks
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c, linux-kernel, joe, yong.y.wang,
qi.wang, andrew.chih.howe.khor, arjan, Tomoya MORINAGA,
Arnd Bergmann
----- Original Message -----
From: "Ben Dooks" <ben-i2c@fluff.org>
To: "Masayuki Ohtak" <masa-korg@dsn.okisemi.com>
Cc: "Jean Delvare (PC drivers, core)" <khali@linux-fr.org>; "Ben Dooks (embedded platforms)" <ben-linux@fluff.org>;
"Crane Cai" <crane.cai@amd.com>; "Samuel Ortiz" <sameo@linux.intel.com>; "Linus Walleij" <linus.walleij@stericsson.com>;
"Ralf Baechle" <ralf@linux-mips.org>; "srinidhi kasagar" <srinidhi.kasagar@stericsson.com>; <linux-i2c@vger.kernel.org>;
<linux-kernel@vger.kernel.org>; <joe@perches.com>; <yong.y.wang@intel.com>; <qi.wang@intel.com>;
<andrew.chih.howe.khor@intel.com>; <arjan@linux.intel.com>; "Tomoya MORINAGA" <morinaga526@dsn.okisemi.com>; "Arnd
Bergmann" <arnd@arndb.de>
Sent: Wednesday, September 08, 2010 8:55 AM
Subject: Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
> On Fri, Sep 03, 2010 at 07:19:44PM +0900, Masayuki Ohtak wrote:
> > I2C driver of Topcliff PCH
> >
> > Topcliff PCH is the platform controller hub that is going to be used in
> > Intel's upcoming general embedded platform. All IO peripherals in
> > Topcliff PCH are actually devices sitting on AMBA bus.
> > Topcliff PCH has I2C I/F. Using this I/F, it is able to access system
> > devices connected to I2C.
> >
> > Signed-off-by: Masayuki Ohtake <masa-korg@dsn.okisemi.com>
> > Reviewed-by: Linus Walleij <linus.walleij@stericsson.com>
> > ---
> > drivers/i2c/busses/Kconfig | 18 +
> > drivers/i2c/busses/Makefile | 1 +
> > drivers/i2c/busses/i2c-pch.c | 944 ++++++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 963 insertions(+), 0 deletions(-)
> > create mode 100644 drivers/i2c/busses/i2c-pch.c
> >
> > diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> > index bceafbf..c5db1e7 100644
> > --- a/drivers/i2c/busses/Kconfig
> > +++ b/drivers/i2c/busses/Kconfig
> > @@ -613,6 +613,24 @@ config I2C_XILINX
> > This driver can also be built as a module. If so, the module
> > will be called xilinx_i2c.
> >
> > +config PCH_I2C
> > + tristate "PCH I2C of Intel Topcliff"
> > + depends on PCI
> > + help
> > + This driver is for PCH(Platform controller Hub) I2C of Topcliff which
> > + is an IOH(Input/Output Hub) for x86 embedded processor.
> > + This driver can access PCH I2C bus device.
> > +
> > +config PCH_I2C_CH_COUNT
> > + int "PCH I2C the number of channel count"
> > + range 1 2
> > + depends on PCH_I2C
> > + help
> > + This driver is for PCH(Platform controller Hub) I2C of Topcliff which
> > + is an IOH(Input/Output Hub) for x86 embedded processor.
> > + The number of I2C buses/channels supported by the PCH I2C controller.
> > + PCH I2C of Topcliff supports only one channel.
> > +
> > comment "External I2C/SMBus adapter drivers"
> >
> > config I2C_PARPORT
> > diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
> > index 936880b..aa04135 100644
> > --- a/drivers/i2c/busses/Makefile
> > +++ b/drivers/i2c/busses/Makefile
> > @@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
> > obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
> > obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
> > obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
> > +obj-$(CONFIG_PCH_I2C) += i2c-pch.o
> >
> > # External I2C/SMBus adapter drivers
> > obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o
> > diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c
> > new file mode 100644
> > index 0000000..ae55a83
> > --- /dev/null
> > +++ b/drivers/i2c/busses/i2c-pch.c
> > @@ -0,0 +1,944 @@
> > +/*
> > + * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; version 2 of the License.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
> > + */
> > +
> > +#include <linux/module.h>
> > +#include <linux/kernel.h>
> > +#include <linux/delay.h>
> > +#include <linux/init.h>
> > +#include <linux/errno.h>
> > +#include <linux/i2c.h>
> > +#include <linux/fs.h>
> > +#include <linux/io.h>
> > +#include <linux/types.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/jiffies.h>
> > +#include <linux/pci.h>
> > +#include <linux/mutex.h>
> > +#include <linux/ktime.h>
> > +
> > +#define PCH_MAX_CHN CONFIG_PCH_I2C_CH_COUNT /* Maximum I2C channels
> > + available */
> > +#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
> > +#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
> > +#define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
> > +#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
> > +#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
> > +
> > +#define PCH_I2CSADR 0x00 /* I2C slave address register */
> > +#define PCH_I2CCTL 0x04 /* I2C control register */
> > +#define PCH_I2CSR 0x08 /* I2C status register */
> > +#define PCH_I2CDR 0x0C /* I2C data register */
> > +#define PCH_I2CMON 0x10 /* I2C bus monitor register */
> > +#define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
> > +#define PCH_I2CMOD 0x18 /* I2C mode register */
> > +#define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
> > +#define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
> > +#define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
> > +#define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
> > +#define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
> > +#define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
> > +#define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
> > +#define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
> > +#define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
> > +#define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
> > +#define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
> > +#define PCH_I2CTMR 0x48 /* I2C timer register */
> > +#define PCH_I2CSRST 0xFC /* I2C reset register */
> > +#define PCH_I2CNF 0xF8 /* I2C noise filter register */
> > +
> > +#define BUS_IDLE_TIMEOUT 20
> > +#define PCH_I2CCTL_I2CMEN 0x0080
> > +#define TEN_BIT_ADDR_DEFAULT 0xF000
> > +#define TEN_BIT_ADDR_MASK 0xF0
> > +#define PCH_START 0x0020
> > +#define PCH_ESR_START 0x0001
> > +#define PCH_BUFF_START 0x1
> > +#define PCH_REPSTART 0x0004
> > +#define PCH_ACK 0x0008
> > +#define PCH_GETACK 0x0001
> > +#define CLR_REG 0x0
> > +#define I2C_RD 0x1
> > +#define I2CMCF_BIT 0x0080
> > +#define I2CMIF_BIT 0x0002
> > +#define I2CMAL_BIT 0x0010
> > +#define I2CBMFI_BIT 0x0001
> > +#define I2CBMAL_BIT 0x0002
> > +#define I2CBMNA_BIT 0x0004
> > +#define I2CBMTO_BIT 0x0008
> > +#define I2CBMIS_BIT 0x0010
> > +#define I2CESRFI_BIT 0X0001
> > +#define I2CESRTO_BIT 0x0002
> > +#define I2CESRFIIE_BIT 0x1
> > +#define I2CESRTOIE_BIT 0x2
> > +#define I2CBMDZ_BIT 0x0040
> > +#define I2CBMAG_BIT 0x0020
> > +#define I2CMBB_BIT 0x0020
> > +#define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
> > + I2CBMTO_BIT | I2CBMIS_BIT)
> > +#define I2C_ADDR_MSK 0xFF
> > +#define I2C_MSB_2B_MSK 0x300
> > +#define FAST_MODE_CLK 400
> > +#define FAST_MODE_EN 0x0001
> > +#define SUB_ADDR_LEN_MAX 4
> > +#define BUF_LEN_MAX 32
> > +#define PCH_BUFFER_MODE 0x1
> > +#define EEPROM_SW_RST_MODE 0x0002
> > +#define NORMAL_INTR_ENBL 0x0300
> > +#define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
> > +#define EEPROM_RST_INTR_DISBL 0x0
> > +#define BUFFER_MODE_INTR_ENBL 0x001F
> > +#define BUFFER_MODE_INTR_DISBL 0x0
> > +#define NORMAL_MODE 0x0
> > +#define BUFFER_MODE 0x1
> > +#define EEPROM_SR_MODE 0x2
> > +#define I2C_TX_MODE 0x0010
> > +#define PCH_BUF_TX 0xFFF7
> > +#define PCH_BUF_RD 0x0008
> > +#define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
> > + I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
> > +#define I2CMAL_EVENT 0x0001
> > +#define I2CMCF_EVENT 0x0002
> > +#define I2CBMFI_EVENT 0x0004
> > +#define I2CBMAL_EVENT 0x0008
> > +#define I2CBMNA_EVENT 0x0010
> > +#define I2CBMTO_EVENT 0x0020
> > +#define I2CBMIS_EVENT 0x0040
> > +#define I2CESRFI_EVENT 0x0080
> > +#define I2CESRTO_EVENT 0x0100
> > +#define PCI_DEVICE_ID_PCH_I2C 0x8817
> > +
> > +#define pch_dbg(adap, fmt, arg...) \
> > + dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
> > +
> > +#define pch_err(adap, fmt, arg...) \
> > + dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
> > +
> > +#define pch_pci_err(pdev, fmt, arg...) \
> > + dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
> > +
> > +#define pch_pci_dbg(pdev, fmt, arg...) \
> > + dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
> > +
> > +/**
> > + * struct i2c_algo_pch_data - for I2C driver functionalities
> > + * @p_adapter_info: stores the reference to adapter_info structure
> > + * @pch_adapter: stores the reference to i2c_adapter structure
> > + * @pch_base_address: specifies the remapped base address
> > + * @pch_buff_mode_en: specifies if buffer mode is enabled
> > + * @pch_event_flag: specifies occurrence of interrupt events
> > + * @pch_xfer_in_progress: specifies whether the transfer is completed
> > + */
> > +struct i2c_algo_pch_data {
> > + struct adapter_info *p_adapter_info;
> > + struct i2c_adapter pch_adapter;
> > + void __iomem *pch_base_address;
> > + int pch_buff_mode_en;
> > + u32 pch_event_flag;
> > + bool pch_xfer_in_progress;
> > +};
> > +
> > +/**
> > + * struct adapter_info - This structure holds the adapter information for the
> > + PCH i2c controller
> > + * @pch_data: stores a list of i2c_algo_pch_data
> > + * @pch_suspended: specifies whether the system is suspended or not
> > + * perhaps with more lines and words.
> > + *
> > + * pch_data has as many elements as maximum I2C channels
> > + */
> > +struct adapter_info {
> > + struct i2c_algo_pch_data pch_data[PCH_MAX_CHN];
> > + bool pch_suspended;
> > +};
> > +
> > +
> > +static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
> > +static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
> > +static wait_queue_head_t pch_event;
> > +static DEFINE_MUTEX(pch_mutex);
> > +
> > +static struct pci_device_id __devinitdata pch_pcidev_id[] = {
> > + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_I2C)},
> > + {0,}
> > +};
> > +
> > +static irqreturn_t pch_handler_ch0(int irq, void *pData);
> > +static irqreturn_t(*pch_handler_list[PCH_MAX_CHN]) (int irq, void *pData) = {
> > + pch_handler_ch0,
> > +};
> > +
> > +static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
> > +{
> > + u32 val;
> > + val = ioread32(addr + offset);
> > + val |= bitmask;
> > + iowrite32(val, addr + offset);
> > +}
> > +
> > +static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
> > +{
> > + u32 val;
> > + val = ioread32(addr + offset);
> > + val &= (~bitmask);
> > + iowrite32(val, addr + offset);
> > +}
> > +
> > +/**
> > + * pch_init() - hardware initialization of I2C module
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + */
> > +static void pch_init(struct i2c_algo_pch_data *adap)
> > +{
> > + u32 pch_i2cbc;
> > + u32 pch_i2ctmr;
> > + u32 reg_value;
> > + void __iomem *p = adap->pch_base_address;
>
> my personal preference is to put the larger items at the top of the list.
>
> > + /* reset I2C controller */
> > + iowrite32(0x01, p + PCH_I2CSRST);
> > + iowrite32(0x0, p + PCH_I2CSRST);
> > + /* Initialize I2C registers */
> > + iowrite32(CLR_REG, p + PCH_I2CCTL);
> > + iowrite32(CLR_REG, p + PCH_I2CMOD);
> > + iowrite32(CLR_REG, p + PCH_I2CBUFFOR);
> > + iowrite32(CLR_REG, p + PCH_I2CBUFSLV);
> > + iowrite32(CLR_REG, p + PCH_I2CBUFSUB);
> > + iowrite32(CLR_REG, p + PCH_I2CBUFMSK);
> > + iowrite32(CLR_REG, p + PCH_I2CESRFOR);
> > + iowrite32(CLR_REG, p + PCH_I2CESRMSK);
> > + iowrite32(0x21, p + PCH_I2CNF);
> > +
> > + reg_value = PCH_I2CCTL_I2CMEN;
> > + pch_setbit((adap->pch_base_address), PCH_I2CCTL,
> > + PCH_I2CCTL_I2CMEN);
> > +
> > + if (pch_i2c_speed != 400)
> > + pch_i2c_speed = 100;
> > +
> > + if (pch_i2c_speed == FAST_MODE_CLK) {
> > + reg_value |= FAST_MODE_EN;
> > + pch_dbg(adap, "Fast mode enabled\n");
> > + }
> > +
> > + if (pch_clk <= 0 || pch_clk > PCH_MAX_CLK)
> > + pch_clk = 62500;
> > +
> > + pch_i2cbc = ((pch_clk) + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
>
> do you really need the () around pch_clk? there seems to be quite a few
> of these around. you also don't need them around pch_i2c_speed * 4. I would
> like to see these gone.
>
> > + /* Set transfer speed in I2CBC */
> > + iowrite32(pch_i2cbc, p + PCH_I2CBC);
> > +
> > + pch_i2ctmr = (pch_clk) / 8;
> > + iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
> > +
> > + reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
> > + iowrite32(reg_value, p + PCH_I2CCTL);
> > +
> > + pch_dbg(adap,
> > + "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
> > + ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
> > +
> > + init_waitqueue_head(&pch_event);
> > +}
> > +
> > +static inline int ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
> > +{
> > + return cmp1.tv64 < cmp2.tv64;
> > +}
>
> surely this should be with the ktime headers?
You mean should we use keime_sub_ns instead of our ktime_lt ?
>
> > +/**
> > + * pch_wait_for_bus_idle() - check the status of bus.
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + * @timeout: waiting time counter (us).
> > + */
> > +static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
> > + s32 timeout)
> > +{
> > + void __iomem *p = adap->pch_base_address;
> > +
> > + /* MAX timeout value is timeout*1000*1000nsec */
> > + ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
> > + do {
> > + if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
> > + break;
> > + msleep(1);
> > + } while (ktime_lt(ktime_get(), ns_val));
> > +
> > + pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
> > +
> > + if (timeout == 0) {
> > + pch_err(adap, "return%d\n", -ETIME);
>
> how about just printing timedout? would be easier to work out what
> happened.
>
> > + return -ETIME;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * pch_start() - Generate I2C start condition in normal mode.
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + *
> > + * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
> > + */
> > +static void pch_start(struct i2c_algo_pch_data *adap)
> > +{
> > + void __iomem *p = adap->pch_base_address;
> > + pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
> > + pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
>
> again with the ()s.
>
> > +static s32 pch_getack(struct i2c_algo_pch_data *adap)
> > +{
> > + u32 reg_val;
> > + void __iomem *p = adap->pch_base_address;
> > + reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
> > +
> > + if (reg_val != 0) {
> > + pch_err(adap, "return%d\n", -EPROTO);
> > + return -EPROTO;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * pch_stop() - generate stop condition in normal mode.
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + */
> > +static void pch_stop(struct i2c_algo_pch_data *adap)
> > +{
> > + void __iomem *p = adap->pch_base_address;
> > + pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
> > + /* clear the start bit */
> > + pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
> > +}
> > +
> > +/**
> > + * pch_repstart() - generate repeated start condition in normal mode
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + */
> > +static void pch_repstart(struct i2c_algo_pch_data *adap)
> > +{
> > + void __iomem *p = adap->pch_base_address;
> > + pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
> > + pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_REPSTART);
> > +}
> > +
> > +/**
> > + * pch_writebytes() - write data to I2C bus in normal mode
> > + * @i2c_adap: Pointer to the struct i2c_adapter.
> > + * @last: specifies whether last message or not.
> > + * In the case of compound mode it will be 1 for last message,
> > + * otherwise 0.
> > + * @first: specifies whether first message or not.
> > + * 1 for first message otherwise 0.
> > + */
> > +static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
> > + u32 last, u32 first)
> > +{
> > + struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
> > + u8 *buf;
> > + u32 length;
> > + u32 addr;
> > + u32 addr_2_msb;
> > + u32 addr_8_lsb;
> > + s32 wrcount;
> > + void __iomem *p = adap->pch_base_address;
> > + length = msgs->len;
> > + buf = msgs->buf;
> > + addr = msgs->addr;
>
> blank line between decls and code please.
>
> > + /* enable master tx */
> > + pch_setbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
>
> this is the last warning on ()s...
>
> > + pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
> > + length);
> > +
> > + if (first) {
> > + if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
> > + return -ETIME;
> > + }
>
> hmm, -ETIME versus -ETIMEDOUT elsewhere?
>
> > + if (msgs->flags & I2C_M_TEN) {
> > + addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
> > + iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
> > + if (first)
> > + pch_start(adap);
> > + if ((pch_wait_for_xfer_complete(adap) == 0) &&
> > + (pch_getack(adap) == 0)) {
>
> and no need for most of the ()s here...
>
> > + addr_8_lsb = (addr & I2C_ADDR_MSK);
> > + iowrite32(addr_8_lsb, p + PCH_I2CDR);
> > + } else {
> > + pch_stop(adap);
> > + return -ETIME;
> > + }
> > + } else {
> > + /* set 7 bit slave address and R/W bit as 0 */
> > + iowrite32(addr << 1, p + PCH_I2CDR);
> > + if (first)
> > + pch_start(adap);
> > + }
> > +
> > + if ((pch_wait_for_xfer_complete(adap) == 0) &&
> > + (pch_getack(adap) == 0)) {
> > + for (wrcount = 0; wrcount < length; ++wrcount) {
> > + /* write buffer value to I2C data register */
> > + iowrite32(buf[wrcount], p + PCH_I2CDR);
> > + pch_dbg(adap, "writing %x to Data register\n",
> > + buf[wrcount]);
> > +
> > + if (pch_wait_for_xfer_complete(adap) != 0)
> > + return -ETIME;
> > +
> > + if (pch_getack(adap))
> > + return -ETIME;
>
> you sure it isn't -EIO here if ack problem?
>
> > + }
> > +
> > + /* check if this is the last message */
> > + if (last)
> > + pch_stop(adap);
> > + else
> > + pch_repstart(adap);
> > + } else {
> > + pch_stop(adap);
> > + return -EIO;
> > + }
> > +
> > + pch_dbg(adap, "return=%d\n", wrcount);
> > +
> > + return wrcount;
> > +}
> > +
> > +/**
> > + * pch_sendack() - send ACK
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + */
> > +static void pch_sendack(struct i2c_algo_pch_data *adap)
> > +{
> > + void __iomem *p = adap->pch_base_address;
> > + pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
> > + pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
> > +}
> > +
> > +/**
> > + * pch_sendnack() - send NACK
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + */
> > +static void pch_sendnack(struct i2c_algo_pch_data *adap)
> > +{
> > + void __iomem *p = adap->pch_base_address;
> > + pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
> > + pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
> > +}
> > +
> > +/**
> > + * pch_readbytes() - read data from I2C bus in normal mode.
> > + * @i2c_adap: Pointer to the struct i2c_adapter.
> > + * @msgs: Pointer to i2c_msg structure.
> > + * @last: specifies whether last message or not.
> > + * @first: specifies whether first message or not.
> > + */
> > +s32 pch_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
> > + u32 last, u32 first)
> > +{
> > + struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
> > +
> > + u8 *buf;
> > + u32 count;
> > + u32 length;
> > + u32 addr;
> > + u32 addr_2_msb;
> > + void __iomem *p = adap->pch_base_address;
> > + length = msgs->len;
> > + buf = msgs->buf;
> > + addr = msgs->addr;
> > +
> > + /* enable master reception */
> > + pch_clrbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
> > +
> > + if (first) {
> > + if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
> > + return -ETIME;
> > + }
> > +
> > + if (msgs->flags & I2C_M_TEN) {
> > + addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
> > + iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
> > +
> > + } else {
> > + /* 7 address bits + R/W bit */
> > + addr = (((addr) << 1) | (I2C_RD));
> > + iowrite32(addr, p + PCH_I2CDR);
> > + }
> > +
> > + /* check if it is the first message */
> > + if (first)
> > + pch_start(adap);
> > +
> > + if ((pch_wait_for_xfer_complete(adap) == 0) &&
> > + (pch_getack(adap) == 0)) {
> > + pch_dbg(adap, "return %d\n", 0);
> > +
> > + if (length == 0) {
> > + pch_stop(adap);
> > + ioread32(p + PCH_I2CDR); /* Dummy read needs */
> > +
> > + count = length;
> > + } else {
> > + int read_index;
> > + int loop;
> > + pch_sendack(adap);
> > +
> > + /* Dummy read */
> > + for (loop = 1, read_index = 0; loop < length; loop++) {
> > + buf[read_index] = ioread32(p + PCH_I2CDR);
> > +
> > + if (loop != 1)
> > + read_index++;
> > +
> > + if (pch_wait_for_xfer_complete(adap) != 0) {
> > + pch_stop(adap);
> > + return -ETIME;
> > + }
> > + } /* end for */
> > +
> > + pch_sendnack(adap);
> > +
> > + buf[read_index] = ioread32(p + PCH_I2CDR);
> > +
> > + if (length != 1)
> > + read_index++;
> > +
> > + if (pch_wait_for_xfer_complete(adap) == 0) {
> > + if (last)
> > + pch_stop(adap);
> > + else
> > + pch_repstart(adap);
> > +
> > + buf[read_index++] = ioread32(p + PCH_I2CDR);
> > + count = read_index;
> > + } else {
> > + count = -ETIME;
> > + }
> > +
> > + }
> > + } else {
> > + count = -ETIME;
> > + pch_stop(adap);
> > + }
> > +
> > + return count;
> > +}
> > +
> > +/**
> > + * pch_cb_ch0() - Interrupt handler Call back function
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + */
> > +static void pch_cb_ch0(struct i2c_algo_pch_data *adap)
> > +{
> > + u32 sts;
> > + void __iomem *p = adap->pch_base_address;
> > +
> > + sts = ioread32(p + PCH_I2CSR);
> > + sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
> > + if (I2CMAL_BIT & sts)
> > + adap->pch_event_flag |= I2CMAL_EVENT;
> > +
> > + if (I2CMCF_BIT & sts)
> > + adap->pch_event_flag |= I2CMCF_EVENT;
> > +
> > + /* clear the applicable bits */
> > + pch_clrbit((adap->pch_base_address), PCH_I2CSR, sts);
> > +
> > + pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
> > +
> > + wake_up_interruptible(&pch_event);
> > +}
> > +
> > +/**
> > + * pch_handler_ch0() - interrupt handler for the PCH I2C controller
> > + * @irq: irq number.
> > + * @pData: cookie passed back to the handler function.
> > + */
> > +static irqreturn_t pch_handler_ch0(int irq, void *pData)
> > +{
> > + s32 reg_val;
> > +
> > + struct i2c_algo_pch_data *adap_data = (struct i2c_algo_pch_data *)pData;
> > + void __iomem *p = adap_data->pch_base_address;
> > + u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE);
> > +
> > + if (mode != NORMAL_MODE) {
> > + pch_err(adap_data, "I2C mode is not supported\n");
> > + return IRQ_NONE;
> > + }
> > +
> > + reg_val = ioread32(p + PCH_I2CSR);
> > + if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
> > + pch_cb_ch0(adap_data);
> > + else
> > + return IRQ_NONE;
> > +
> > + return IRQ_HANDLED;
> > +}
> > +#if 0
> > + if (mode == NORMAL_MODE) {
> > + reg_val = ioread32(p + PCH_I2CSR);
> > + if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
> > + pch_cb_ch0(adap_data);
> > + else
> > + goto err_out;
> > + } else {
> > + pch_err(adap_data, "I2C mode is not supported\n");
> > + goto err_out;
> > + }
> > + return IRQ_HANDLED;
> > +
> > +err_out:
> > + return IRQ_NONE;
> > +}
> > +#endif
>
> please, no #if 0. either remove completely or do something with it.
>
> > +/**
> > + * pch_xfer() - Reading adnd writing data through I2C bus
> > + * @i2c_adap: Pointer to the struct i2c_adapter.
> > + * @msgs: Pointer to i2c_msg structure.
> > + * @num: number of messages.
> > + */
> > +static s32 pch_xfer(struct i2c_adapter *i2c_adap,
> > + struct i2c_msg *msgs, s32 num)
> > +{
> > + struct i2c_msg *pmsg;
> > + u32 i;
> > + u32 status;
> > + u32 msglen;
> > + u32 subaddrlen;
> > + s32 ret;
> > +
> > + struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
> > +
> > + ret = mutex_lock_interruptible(&pch_mutex);
> > + if (ret)
> > + return -ERESTARTSYS;
> > +
> > + if (adap->p_adapter_info->pch_suspended) {
> > + mutex_unlock(&pch_mutex);
> > + return -EBUSY;
> > + }
> > +
> > + pch_dbg(adap, "adap->p_adapter_info->pch_suspended is %d\n",
> > + adap->p_adapter_info->pch_suspended);
> > + /* transfer not completed */
> > + adap->pch_xfer_in_progress = true;
> > +
> > + for (i = 0; i < num; i++) {
> > + pmsg = &msgs[i];
> > + pmsg->flags |= adap->pch_buff_mode_en;
> > + status = pmsg->flags;
> > + pch_dbg(adap,
> > + "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
> > + /* calculate sub address length and message length */
> > + /* these are applicable only for buffer mode */
> > + subaddrlen = pmsg->buf[0];
> > + /* calculate actual message length excluding
> > + * the sub address fields */
> > + msglen = (pmsg->len) - (subaddrlen + 1);
> > + if (status & (I2C_M_RD)) {
> > + pch_dbg(adap, "invoking pch_readbytes\n");
> > + ret = pch_readbytes(i2c_adap, pmsg, (i + 1 == num),
> > + (i == 0));
> > + } else {
> > + pch_dbg(adap, "invoking pch_writebytes\n");
> > + ret = pch_writebytes(i2c_adap, pmsg, (i + 1 == num),
> > + (i == 0));
> > + }
> > +
> > + }
> > +
> > + adap->pch_xfer_in_progress = false; /* transfer completed */
> > +
> > + mutex_unlock(&pch_mutex);
> > +
> > + return ret;
> > +}
> > +
> > +/**
> > + * pch_func() - return the functionality of the I2C driver
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + */
> > +static u32 pch_func(struct i2c_adapter *adap)
> > +{
> > + u32 ret;
> > + ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
> > + return ret;
> > +}
>
> how about just return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
>
> > +static struct i2c_algorithm pch_algorithm = {
> > + .master_xfer = pch_xfer,
> > + .functionality = pch_func
> > +};
> > +
> > +/**
> > + * pch_disbl_int() - Disable PCH I2C interrupts
> > + * @adap: Pointer to struct i2c_algo_pch_data.
> > + */
> > +static void pch_disbl_int(struct i2c_algo_pch_data *adap)
> > +{
> > + void __iomem *p = adap->pch_base_address;
> > +
> > + pch_clrbit((adap->pch_base_address), PCH_I2CCTL,
> > + NORMAL_INTR_ENBL);
> > +
> > + iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
> > +
> > + iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
> > +}
> > +
> > +static int __devinit pch_probe(struct pci_dev *pdev,
> > + const struct pci_device_id *id)
> > +{
> > + int i;
> > + void __iomem *base_addr;
> > + s32 ret;
> > + struct adapter_info *adap_info =
> > + kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
>
> this would be a good case to putting the kzalloc() on a different line
> from the decleration.
>
> > + pch_pci_dbg(pdev, "Entered.\n");
> > +
> > + if (adap_info == NULL) {
> > + pch_pci_err(pdev, "Memory allocation FAILED\n");
> > + return -ENOMEM;
> > + }
> > +
> > + ret = pci_enable_device(pdev);
> > + if (ret) {
> > + pch_pci_err(pdev, "pci_enable_device FAILED\n");
> > + goto err_pci_enable;
> > + }
>
> do you really need to put FAILED in capitals here?
You mean should we use "failed" not "FAILED" ?
>
> > + ret = pci_request_regions(pdev, KBUILD_MODNAME);
> > + if (ret) {
> > + pch_pci_err(pdev, "pci_request_regions FAILED\n");
> > + goto err_pci_req;
> > + }
> > +
> > + base_addr = pci_iomap(pdev, 1, 0);
> > +
> > + if (base_addr == 0) {
>
> surley that would be == NULL?
>
> > + pch_pci_err(pdev, "pci_iomap FAILED\n");
> > + ret = -ENOMEM;
> > + goto err_pci_iomap;
> > + }
> > +
> > + adap_info->pch_suspended = false;
> > +
> > + for (i = 0; i < PCH_MAX_CHN; i++) {
> > + adap_info->pch_data[i].p_adapter_info = adap_info;
>
> looks like a pointer to adap_info->pch_data[i] would make the source
> smaller and a bit easier to read.
This code have already modified.(PCH_MAX_CHN is deleted.)
Please refer the latest our i2c patch.
>
> > + adap_info->pch_data[i].pch_adapter.owner = THIS_MODULE;
> > + adap_info->pch_data[i].pch_adapter.class = I2C_CLASS_HWMON;
> > + strcpy(adap_info->pch_data[i].pch_adapter.name, KBUILD_MODNAME);
> > + adap_info->pch_data[i].pch_adapter.algo = &pch_algorithm;
> > + adap_info->pch_data[i].pch_adapter.algo_data =
> > + &adap_info->pch_data[i];
> > +
> > + /* (i * 0x80) + base_addr; */
> > + adap_info->pch_data[i].pch_base_address = base_addr;
> > +
> > + adap_info->pch_data[i].pch_adapter.dev.parent = &pdev->dev;
> > +
> > + ret = i2c_add_adapter(&(adap_info->pch_data[i].pch_adapter));
> > +
> > + if (ret) {
> > + pch_pci_err(pdev, "i2c_add_adapter FAILED\n");
> > + goto err_i2c_add_adapter;
> > + }
> > +
> > + pch_init(&adap_info->pch_data[i]);
> > + ret = request_irq(pdev->irq, pch_handler_list[i], IRQF_SHARED,
> > + KBUILD_MODNAME, &adap_info->pch_data[i]);
> > + if (ret) {
> > + pch_pci_err(pdev, "request_irq FAILED\n");
> > + goto err_request_irq;
> > + }
> > + }
> > +
> > + pci_set_drvdata(pdev, adap_info);
> > + pch_pci_dbg(pdev, "returns %d.\n", ret);
> > + return 0;
> > +
> > +err_request_irq:
> > + for (i = 0; i < PCH_MAX_CHN; i++)
> > + i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
> > +err_i2c_add_adapter:
> > + pci_iounmap(pdev, base_addr);
> > +err_pci_iomap:
> > + pci_release_regions(pdev);
> > +err_pci_req:
> > + pci_disable_device(pdev);
> > +err_pci_enable:
> > + kfree(adap_info);
> > + return ret;
> > +}
> > +
> > +static void __devexit pch_remove(struct pci_dev *pdev)
> > +{
> > + int i;
> > +
> > + struct adapter_info *adap_info = pci_get_drvdata(pdev);
>
> no need for the blank line.
>
> > +
> > +
> > + for (i = 0; i < PCH_MAX_CHN; i++) {
> > + pch_disbl_int(&adap_info->pch_data[i]);
> > + free_irq(pdev->irq, &adap_info->pch_data[i]);
> > + i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
> > + }
> > +
> > + if (adap_info->pch_data[0].pch_base_address) {
> > + pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
> > + adap_info->pch_data[0].pch_base_address = 0;
> > + }
> > +
> > + pci_set_drvdata(pdev, NULL);
> > +
> > + pci_release_regions(pdev);
> > +
> > + pci_disable_device(pdev);
> > + kfree(adap_info);
> > +}
> > +
> > +#ifdef CONFIG_PM
> > +static int pch_suspend(struct pci_dev *pdev, pm_message_t state)
> > +{
> > + int i;
> > + int ret;
> > +
> > + struct adapter_info *adap_info = pci_get_drvdata(pdev);
> > + void __iomem *p = adap_info->pch_data[0].pch_base_address;
> >
> again, blank line, also see notes on ordering.
>
> > + adap_info->pch_suspended = true;
> > +
> > + for (i = 0; i < PCH_MAX_CHN; i++) {
> > + while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
> > + /* Wait until all channel transfers are completed */
> > + msleep(1);
> > + }
> > + /* Disable the i2c interrupts */
> > + pch_disbl_int(&adap_info->pch_data[i]);
> > + }
> > +
> > + pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
> > + "invoked function pch_disbl_int successfully\n",
> > + ioread32(p + 0x08), ioread32(p + 0x30), ioread32(p + 0x44));
>
> magic numbers being used to ioread32?
>
> > + ret = pci_save_state(pdev);
> > +
> > + if (ret) {
> > + pch_pci_err(pdev, "pci_save_state\n");
> > + return ret;
> > + }
> > +
> > + pci_enable_wake(pdev, PCI_D3hot, 0);
> > + pci_disable_device(pdev);
> > + pci_set_power_state(pdev, pci_choose_state(pdev, state));
> > +
> > + return 0;
> > +}
> > +
> > +static int pch_resume(struct pci_dev *pdev)
> > +{
> > + struct adapter_info *adap_info = pci_get_drvdata(pdev);
> > + int i;
> > +
> > + pci_set_power_state(pdev, PCI_D0);
> > + pci_restore_state(pdev);
> > +
> > + if (pci_enable_device(pdev) < 0) {
> > + pch_pci_err(pdev, "pci_enable_device FAILED in pch_resume\n");
> > + return -EIO;
> > + }
> > +
> > + pci_enable_wake(pdev, PCI_D3hot, 0);
> > +
> > + for (i = 0; i < PCH_MAX_CHN; i++)
> > + pch_init(&adap_info->pch_data[i]);
> > +
> > + adap_info->pch_suspended = false;
> > +
> > + return 0;
> > +}
> > +#else
> > +#define pch_suspend NULL
> > +#define pch_resume NULL
> > +#endif
> > +
> > +static struct pci_driver pch_pcidriver = {
> > + .name = KBUILD_MODNAME,
> > + .id_table = pch_pcidev_id,
> > + .probe = pch_probe,
> > + .remove = __devexit_p(pch_remove),
> > + .suspend = pch_suspend,
> > + .resume = pch_resume
> > +};
> > +
> > +static int __init pch_pci_init(void)
> > +{
> > + return pci_register_driver(&pch_pcidriver);
> > +}
> > +
> > +static void __exit pch_pci_exit(void)
> > +{
> > + pci_unregister_driver(&pch_pcidriver);
> > +}
> > +
> > +MODULE_DESCRIPTION("PCH I2C PCI Driver");
> > +MODULE_LICENSE("GPL");
>
> no MODULE_AUTHOR?
>
> > +module_init(pch_pci_init);
> > +module_exit(pch_pci_exit);
> > +module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
> > +module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
>
Thanks, Ohtake(OKISemi)
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-07 23:55 ` Ben Dooks
0 siblings, 0 replies; 47+ messages in thread
From: Ben Dooks @ 2010-09-07 23:55 UTC (permalink / raw)
To: Masayuki Ohtak
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c, linux-kernel, joe, yong.y.wang,
qi.wang, andrew.chih.howe.khor, arjan, Tomoya MORINAGA,
Arnd Bergmann
On Fri, Sep 03, 2010 at 07:19:44PM +0900, Masayuki Ohtak wrote:
> I2C driver of Topcliff PCH
>
> Topcliff PCH is the platform controller hub that is going to be used in
> Intel's upcoming general embedded platform. All IO peripherals in
> Topcliff PCH are actually devices sitting on AMBA bus.
> Topcliff PCH has I2C I/F. Using this I/F, it is able to access system
> devices connected to I2C.
>
> Signed-off-by: Masayuki Ohtake <masa-korg@dsn.okisemi.com>
> Reviewed-by: Linus Walleij <linus.walleij@stericsson.com>
> ---
> drivers/i2c/busses/Kconfig | 18 +
> drivers/i2c/busses/Makefile | 1 +
> drivers/i2c/busses/i2c-pch.c | 944 ++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 963 insertions(+), 0 deletions(-)
> create mode 100644 drivers/i2c/busses/i2c-pch.c
>
> diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> index bceafbf..c5db1e7 100644
> --- a/drivers/i2c/busses/Kconfig
> +++ b/drivers/i2c/busses/Kconfig
> @@ -613,6 +613,24 @@ config I2C_XILINX
> This driver can also be built as a module. If so, the module
> will be called xilinx_i2c.
>
> +config PCH_I2C
> + tristate "PCH I2C of Intel Topcliff"
> + depends on PCI
> + help
> + This driver is for PCH(Platform controller Hub) I2C of Topcliff which
> + is an IOH(Input/Output Hub) for x86 embedded processor.
> + This driver can access PCH I2C bus device.
> +
> +config PCH_I2C_CH_COUNT
> + int "PCH I2C the number of channel count"
> + range 1 2
> + depends on PCH_I2C
> + help
> + This driver is for PCH(Platform controller Hub) I2C of Topcliff which
> + is an IOH(Input/Output Hub) for x86 embedded processor.
> + The number of I2C buses/channels supported by the PCH I2C controller.
> + PCH I2C of Topcliff supports only one channel.
> +
> comment "External I2C/SMBus adapter drivers"
>
> config I2C_PARPORT
> diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
> index 936880b..aa04135 100644
> --- a/drivers/i2c/busses/Makefile
> +++ b/drivers/i2c/busses/Makefile
> @@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
> obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
> obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
> obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
> +obj-$(CONFIG_PCH_I2C) += i2c-pch.o
>
> # External I2C/SMBus adapter drivers
> obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o
> diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c
> new file mode 100644
> index 0000000..ae55a83
> --- /dev/null
> +++ b/drivers/i2c/busses/i2c-pch.c
> @@ -0,0 +1,944 @@
> +/*
> + * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; version 2 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/kernel.h>
> +#include <linux/delay.h>
> +#include <linux/init.h>
> +#include <linux/errno.h>
> +#include <linux/i2c.h>
> +#include <linux/fs.h>
> +#include <linux/io.h>
> +#include <linux/types.h>
> +#include <linux/interrupt.h>
> +#include <linux/jiffies.h>
> +#include <linux/pci.h>
> +#include <linux/mutex.h>
> +#include <linux/ktime.h>
> +
> +#define PCH_MAX_CHN CONFIG_PCH_I2C_CH_COUNT /* Maximum I2C channels
> + available */
> +#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
> +#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
> +#define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
> +#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
> +#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
> +
> +#define PCH_I2CSADR 0x00 /* I2C slave address register */
> +#define PCH_I2CCTL 0x04 /* I2C control register */
> +#define PCH_I2CSR 0x08 /* I2C status register */
> +#define PCH_I2CDR 0x0C /* I2C data register */
> +#define PCH_I2CMON 0x10 /* I2C bus monitor register */
> +#define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
> +#define PCH_I2CMOD 0x18 /* I2C mode register */
> +#define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
> +#define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
> +#define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
> +#define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
> +#define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
> +#define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
> +#define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
> +#define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
> +#define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
> +#define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
> +#define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
> +#define PCH_I2CTMR 0x48 /* I2C timer register */
> +#define PCH_I2CSRST 0xFC /* I2C reset register */
> +#define PCH_I2CNF 0xF8 /* I2C noise filter register */
> +
> +#define BUS_IDLE_TIMEOUT 20
> +#define PCH_I2CCTL_I2CMEN 0x0080
> +#define TEN_BIT_ADDR_DEFAULT 0xF000
> +#define TEN_BIT_ADDR_MASK 0xF0
> +#define PCH_START 0x0020
> +#define PCH_ESR_START 0x0001
> +#define PCH_BUFF_START 0x1
> +#define PCH_REPSTART 0x0004
> +#define PCH_ACK 0x0008
> +#define PCH_GETACK 0x0001
> +#define CLR_REG 0x0
> +#define I2C_RD 0x1
> +#define I2CMCF_BIT 0x0080
> +#define I2CMIF_BIT 0x0002
> +#define I2CMAL_BIT 0x0010
> +#define I2CBMFI_BIT 0x0001
> +#define I2CBMAL_BIT 0x0002
> +#define I2CBMNA_BIT 0x0004
> +#define I2CBMTO_BIT 0x0008
> +#define I2CBMIS_BIT 0x0010
> +#define I2CESRFI_BIT 0X0001
> +#define I2CESRTO_BIT 0x0002
> +#define I2CESRFIIE_BIT 0x1
> +#define I2CESRTOIE_BIT 0x2
> +#define I2CBMDZ_BIT 0x0040
> +#define I2CBMAG_BIT 0x0020
> +#define I2CMBB_BIT 0x0020
> +#define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
> + I2CBMTO_BIT | I2CBMIS_BIT)
> +#define I2C_ADDR_MSK 0xFF
> +#define I2C_MSB_2B_MSK 0x300
> +#define FAST_MODE_CLK 400
> +#define FAST_MODE_EN 0x0001
> +#define SUB_ADDR_LEN_MAX 4
> +#define BUF_LEN_MAX 32
> +#define PCH_BUFFER_MODE 0x1
> +#define EEPROM_SW_RST_MODE 0x0002
> +#define NORMAL_INTR_ENBL 0x0300
> +#define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
> +#define EEPROM_RST_INTR_DISBL 0x0
> +#define BUFFER_MODE_INTR_ENBL 0x001F
> +#define BUFFER_MODE_INTR_DISBL 0x0
> +#define NORMAL_MODE 0x0
> +#define BUFFER_MODE 0x1
> +#define EEPROM_SR_MODE 0x2
> +#define I2C_TX_MODE 0x0010
> +#define PCH_BUF_TX 0xFFF7
> +#define PCH_BUF_RD 0x0008
> +#define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
> + I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
> +#define I2CMAL_EVENT 0x0001
> +#define I2CMCF_EVENT 0x0002
> +#define I2CBMFI_EVENT 0x0004
> +#define I2CBMAL_EVENT 0x0008
> +#define I2CBMNA_EVENT 0x0010
> +#define I2CBMTO_EVENT 0x0020
> +#define I2CBMIS_EVENT 0x0040
> +#define I2CESRFI_EVENT 0x0080
> +#define I2CESRTO_EVENT 0x0100
> +#define PCI_DEVICE_ID_PCH_I2C 0x8817
> +
> +#define pch_dbg(adap, fmt, arg...) \
> + dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
> +
> +#define pch_err(adap, fmt, arg...) \
> + dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
> +
> +#define pch_pci_err(pdev, fmt, arg...) \
> + dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
> +
> +#define pch_pci_dbg(pdev, fmt, arg...) \
> + dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
> +
> +/**
> + * struct i2c_algo_pch_data - for I2C driver functionalities
> + * @p_adapter_info: stores the reference to adapter_info structure
> + * @pch_adapter: stores the reference to i2c_adapter structure
> + * @pch_base_address: specifies the remapped base address
> + * @pch_buff_mode_en: specifies if buffer mode is enabled
> + * @pch_event_flag: specifies occurrence of interrupt events
> + * @pch_xfer_in_progress: specifies whether the transfer is completed
> + */
> +struct i2c_algo_pch_data {
> + struct adapter_info *p_adapter_info;
> + struct i2c_adapter pch_adapter;
> + void __iomem *pch_base_address;
> + int pch_buff_mode_en;
> + u32 pch_event_flag;
> + bool pch_xfer_in_progress;
> +};
> +
> +/**
> + * struct adapter_info - This structure holds the adapter information for the
> + PCH i2c controller
> + * @pch_data: stores a list of i2c_algo_pch_data
> + * @pch_suspended: specifies whether the system is suspended or not
> + * perhaps with more lines and words.
> + *
> + * pch_data has as many elements as maximum I2C channels
> + */
> +struct adapter_info {
> + struct i2c_algo_pch_data pch_data[PCH_MAX_CHN];
> + bool pch_suspended;
> +};
> +
> +
> +static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
> +static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
> +static wait_queue_head_t pch_event;
> +static DEFINE_MUTEX(pch_mutex);
> +
> +static struct pci_device_id __devinitdata pch_pcidev_id[] = {
> + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_I2C)},
> + {0,}
> +};
> +
> +static irqreturn_t pch_handler_ch0(int irq, void *pData);
> +static irqreturn_t(*pch_handler_list[PCH_MAX_CHN]) (int irq, void *pData) = {
> + pch_handler_ch0,
> +};
> +
> +static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
> +{
> + u32 val;
> + val = ioread32(addr + offset);
> + val |= bitmask;
> + iowrite32(val, addr + offset);
> +}
> +
> +static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
> +{
> + u32 val;
> + val = ioread32(addr + offset);
> + val &= (~bitmask);
> + iowrite32(val, addr + offset);
> +}
> +
> +/**
> + * pch_init() - hardware initialization of I2C module
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + */
> +static void pch_init(struct i2c_algo_pch_data *adap)
> +{
> + u32 pch_i2cbc;
> + u32 pch_i2ctmr;
> + u32 reg_value;
> + void __iomem *p = adap->pch_base_address;
my personal preference is to put the larger items at the top of the list.
> + /* reset I2C controller */
> + iowrite32(0x01, p + PCH_I2CSRST);
> + iowrite32(0x0, p + PCH_I2CSRST);
> + /* Initialize I2C registers */
> + iowrite32(CLR_REG, p + PCH_I2CCTL);
> + iowrite32(CLR_REG, p + PCH_I2CMOD);
> + iowrite32(CLR_REG, p + PCH_I2CBUFFOR);
> + iowrite32(CLR_REG, p + PCH_I2CBUFSLV);
> + iowrite32(CLR_REG, p + PCH_I2CBUFSUB);
> + iowrite32(CLR_REG, p + PCH_I2CBUFMSK);
> + iowrite32(CLR_REG, p + PCH_I2CESRFOR);
> + iowrite32(CLR_REG, p + PCH_I2CESRMSK);
> + iowrite32(0x21, p + PCH_I2CNF);
> +
> + reg_value = PCH_I2CCTL_I2CMEN;
> + pch_setbit((adap->pch_base_address), PCH_I2CCTL,
> + PCH_I2CCTL_I2CMEN);
> +
> + if (pch_i2c_speed != 400)
> + pch_i2c_speed = 100;
> +
> + if (pch_i2c_speed == FAST_MODE_CLK) {
> + reg_value |= FAST_MODE_EN;
> + pch_dbg(adap, "Fast mode enabled\n");
> + }
> +
> + if (pch_clk <= 0 || pch_clk > PCH_MAX_CLK)
> + pch_clk = 62500;
> +
> + pch_i2cbc = ((pch_clk) + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
do you really need the () around pch_clk? there seems to be quite a few
of these around. you also don't need them around pch_i2c_speed * 4. I would
like to see these gone.
> + /* Set transfer speed in I2CBC */
> + iowrite32(pch_i2cbc, p + PCH_I2CBC);
> +
> + pch_i2ctmr = (pch_clk) / 8;
> + iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
> +
> + reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
> + iowrite32(reg_value, p + PCH_I2CCTL);
> +
> + pch_dbg(adap,
> + "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
> + ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
> +
> + init_waitqueue_head(&pch_event);
> +}
> +
> +static inline int ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
> +{
> + return cmp1.tv64 < cmp2.tv64;
> +}
surely this should be with the ktime headers?
> +/**
> + * pch_wait_for_bus_idle() - check the status of bus.
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + * @timeout: waiting time counter (us).
> + */
> +static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
> + s32 timeout)
> +{
> + void __iomem *p = adap->pch_base_address;
> +
> + /* MAX timeout value is timeout*1000*1000nsec */
> + ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
> + do {
> + if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
> + break;
> + msleep(1);
> + } while (ktime_lt(ktime_get(), ns_val));
> +
> + pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
> +
> + if (timeout == 0) {
> + pch_err(adap, "return%d\n", -ETIME);
how about just printing timedout? would be easier to work out what
happened.
> + return -ETIME;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * pch_start() - Generate I2C start condition in normal mode.
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + *
> + * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
> + */
> +static void pch_start(struct i2c_algo_pch_data *adap)
> +{
> + void __iomem *p = adap->pch_base_address;
> + pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
> + pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
again with the ()s.
> +static s32 pch_getack(struct i2c_algo_pch_data *adap)
> +{
> + u32 reg_val;
> + void __iomem *p = adap->pch_base_address;
> + reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
> +
> + if (reg_val != 0) {
> + pch_err(adap, "return%d\n", -EPROTO);
> + return -EPROTO;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * pch_stop() - generate stop condition in normal mode.
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + */
> +static void pch_stop(struct i2c_algo_pch_data *adap)
> +{
> + void __iomem *p = adap->pch_base_address;
> + pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
> + /* clear the start bit */
> + pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
> +}
> +
> +/**
> + * pch_repstart() - generate repeated start condition in normal mode
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + */
> +static void pch_repstart(struct i2c_algo_pch_data *adap)
> +{
> + void __iomem *p = adap->pch_base_address;
> + pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
> + pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_REPSTART);
> +}
> +
> +/**
> + * pch_writebytes() - write data to I2C bus in normal mode
> + * @i2c_adap: Pointer to the struct i2c_adapter.
> + * @last: specifies whether last message or not.
> + * In the case of compound mode it will be 1 for last message,
> + * otherwise 0.
> + * @first: specifies whether first message or not.
> + * 1 for first message otherwise 0.
> + */
> +static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
> + u32 last, u32 first)
> +{
> + struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
> + u8 *buf;
> + u32 length;
> + u32 addr;
> + u32 addr_2_msb;
> + u32 addr_8_lsb;
> + s32 wrcount;
> + void __iomem *p = adap->pch_base_address;
> + length = msgs->len;
> + buf = msgs->buf;
> + addr = msgs->addr;
blank line between decls and code please.
> + /* enable master tx */
> + pch_setbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
this is the last warning on ()s...
> + pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
> + length);
> +
> + if (first) {
> + if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
> + return -ETIME;
> + }
hmm, -ETIME versus -ETIMEDOUT elsewhere?
> + if (msgs->flags & I2C_M_TEN) {
> + addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
> + iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
> + if (first)
> + pch_start(adap);
> + if ((pch_wait_for_xfer_complete(adap) == 0) &&
> + (pch_getack(adap) == 0)) {
and no need for most of the ()s here...
> + addr_8_lsb = (addr & I2C_ADDR_MSK);
> + iowrite32(addr_8_lsb, p + PCH_I2CDR);
> + } else {
> + pch_stop(adap);
> + return -ETIME;
> + }
> + } else {
> + /* set 7 bit slave address and R/W bit as 0 */
> + iowrite32(addr << 1, p + PCH_I2CDR);
> + if (first)
> + pch_start(adap);
> + }
> +
> + if ((pch_wait_for_xfer_complete(adap) == 0) &&
> + (pch_getack(adap) == 0)) {
> + for (wrcount = 0; wrcount < length; ++wrcount) {
> + /* write buffer value to I2C data register */
> + iowrite32(buf[wrcount], p + PCH_I2CDR);
> + pch_dbg(adap, "writing %x to Data register\n",
> + buf[wrcount]);
> +
> + if (pch_wait_for_xfer_complete(adap) != 0)
> + return -ETIME;
> +
> + if (pch_getack(adap))
> + return -ETIME;
you sure it isn't -EIO here if ack problem?
> + }
> +
> + /* check if this is the last message */
> + if (last)
> + pch_stop(adap);
> + else
> + pch_repstart(adap);
> + } else {
> + pch_stop(adap);
> + return -EIO;
> + }
> +
> + pch_dbg(adap, "return=%d\n", wrcount);
> +
> + return wrcount;
> +}
> +
> +/**
> + * pch_sendack() - send ACK
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + */
> +static void pch_sendack(struct i2c_algo_pch_data *adap)
> +{
> + void __iomem *p = adap->pch_base_address;
> + pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
> + pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
> +}
> +
> +/**
> + * pch_sendnack() - send NACK
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + */
> +static void pch_sendnack(struct i2c_algo_pch_data *adap)
> +{
> + void __iomem *p = adap->pch_base_address;
> + pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
> + pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
> +}
> +
> +/**
> + * pch_readbytes() - read data from I2C bus in normal mode.
> + * @i2c_adap: Pointer to the struct i2c_adapter.
> + * @msgs: Pointer to i2c_msg structure.
> + * @last: specifies whether last message or not.
> + * @first: specifies whether first message or not.
> + */
> +s32 pch_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
> + u32 last, u32 first)
> +{
> + struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
> +
> + u8 *buf;
> + u32 count;
> + u32 length;
> + u32 addr;
> + u32 addr_2_msb;
> + void __iomem *p = adap->pch_base_address;
> + length = msgs->len;
> + buf = msgs->buf;
> + addr = msgs->addr;
> +
> + /* enable master reception */
> + pch_clrbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
> +
> + if (first) {
> + if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
> + return -ETIME;
> + }
> +
> + if (msgs->flags & I2C_M_TEN) {
> + addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
> + iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
> +
> + } else {
> + /* 7 address bits + R/W bit */
> + addr = (((addr) << 1) | (I2C_RD));
> + iowrite32(addr, p + PCH_I2CDR);
> + }
> +
> + /* check if it is the first message */
> + if (first)
> + pch_start(adap);
> +
> + if ((pch_wait_for_xfer_complete(adap) == 0) &&
> + (pch_getack(adap) == 0)) {
> + pch_dbg(adap, "return %d\n", 0);
> +
> + if (length == 0) {
> + pch_stop(adap);
> + ioread32(p + PCH_I2CDR); /* Dummy read needs */
> +
> + count = length;
> + } else {
> + int read_index;
> + int loop;
> + pch_sendack(adap);
> +
> + /* Dummy read */
> + for (loop = 1, read_index = 0; loop < length; loop++) {
> + buf[read_index] = ioread32(p + PCH_I2CDR);
> +
> + if (loop != 1)
> + read_index++;
> +
> + if (pch_wait_for_xfer_complete(adap) != 0) {
> + pch_stop(adap);
> + return -ETIME;
> + }
> + } /* end for */
> +
> + pch_sendnack(adap);
> +
> + buf[read_index] = ioread32(p + PCH_I2CDR);
> +
> + if (length != 1)
> + read_index++;
> +
> + if (pch_wait_for_xfer_complete(adap) == 0) {
> + if (last)
> + pch_stop(adap);
> + else
> + pch_repstart(adap);
> +
> + buf[read_index++] = ioread32(p + PCH_I2CDR);
> + count = read_index;
> + } else {
> + count = -ETIME;
> + }
> +
> + }
> + } else {
> + count = -ETIME;
> + pch_stop(adap);
> + }
> +
> + return count;
> +}
> +
> +/**
> + * pch_cb_ch0() - Interrupt handler Call back function
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + */
> +static void pch_cb_ch0(struct i2c_algo_pch_data *adap)
> +{
> + u32 sts;
> + void __iomem *p = adap->pch_base_address;
> +
> + sts = ioread32(p + PCH_I2CSR);
> + sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
> + if (I2CMAL_BIT & sts)
> + adap->pch_event_flag |= I2CMAL_EVENT;
> +
> + if (I2CMCF_BIT & sts)
> + adap->pch_event_flag |= I2CMCF_EVENT;
> +
> + /* clear the applicable bits */
> + pch_clrbit((adap->pch_base_address), PCH_I2CSR, sts);
> +
> + pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
> +
> + wake_up_interruptible(&pch_event);
> +}
> +
> +/**
> + * pch_handler_ch0() - interrupt handler for the PCH I2C controller
> + * @irq: irq number.
> + * @pData: cookie passed back to the handler function.
> + */
> +static irqreturn_t pch_handler_ch0(int irq, void *pData)
> +{
> + s32 reg_val;
> +
> + struct i2c_algo_pch_data *adap_data = (struct i2c_algo_pch_data *)pData;
> + void __iomem *p = adap_data->pch_base_address;
> + u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE);
> +
> + if (mode != NORMAL_MODE) {
> + pch_err(adap_data, "I2C mode is not supported\n");
> + return IRQ_NONE;
> + }
> +
> + reg_val = ioread32(p + PCH_I2CSR);
> + if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
> + pch_cb_ch0(adap_data);
> + else
> + return IRQ_NONE;
> +
> + return IRQ_HANDLED;
> +}
> +#if 0
> + if (mode == NORMAL_MODE) {
> + reg_val = ioread32(p + PCH_I2CSR);
> + if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
> + pch_cb_ch0(adap_data);
> + else
> + goto err_out;
> + } else {
> + pch_err(adap_data, "I2C mode is not supported\n");
> + goto err_out;
> + }
> + return IRQ_HANDLED;
> +
> +err_out:
> + return IRQ_NONE;
> +}
> +#endif
please, no #if 0. either remove completely or do something with it.
> +/**
> + * pch_xfer() - Reading adnd writing data through I2C bus
> + * @i2c_adap: Pointer to the struct i2c_adapter.
> + * @msgs: Pointer to i2c_msg structure.
> + * @num: number of messages.
> + */
> +static s32 pch_xfer(struct i2c_adapter *i2c_adap,
> + struct i2c_msg *msgs, s32 num)
> +{
> + struct i2c_msg *pmsg;
> + u32 i;
> + u32 status;
> + u32 msglen;
> + u32 subaddrlen;
> + s32 ret;
> +
> + struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
> +
> + ret = mutex_lock_interruptible(&pch_mutex);
> + if (ret)
> + return -ERESTARTSYS;
> +
> + if (adap->p_adapter_info->pch_suspended) {
> + mutex_unlock(&pch_mutex);
> + return -EBUSY;
> + }
> +
> + pch_dbg(adap, "adap->p_adapter_info->pch_suspended is %d\n",
> + adap->p_adapter_info->pch_suspended);
> + /* transfer not completed */
> + adap->pch_xfer_in_progress = true;
> +
> + for (i = 0; i < num; i++) {
> + pmsg = &msgs[i];
> + pmsg->flags |= adap->pch_buff_mode_en;
> + status = pmsg->flags;
> + pch_dbg(adap,
> + "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
> + /* calculate sub address length and message length */
> + /* these are applicable only for buffer mode */
> + subaddrlen = pmsg->buf[0];
> + /* calculate actual message length excluding
> + * the sub address fields */
> + msglen = (pmsg->len) - (subaddrlen + 1);
> + if (status & (I2C_M_RD)) {
> + pch_dbg(adap, "invoking pch_readbytes\n");
> + ret = pch_readbytes(i2c_adap, pmsg, (i + 1 == num),
> + (i == 0));
> + } else {
> + pch_dbg(adap, "invoking pch_writebytes\n");
> + ret = pch_writebytes(i2c_adap, pmsg, (i + 1 == num),
> + (i == 0));
> + }
> +
> + }
> +
> + adap->pch_xfer_in_progress = false; /* transfer completed */
> +
> + mutex_unlock(&pch_mutex);
> +
> + return ret;
> +}
> +
> +/**
> + * pch_func() - return the functionality of the I2C driver
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + */
> +static u32 pch_func(struct i2c_adapter *adap)
> +{
> + u32 ret;
> + ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
> + return ret;
> +}
how about just return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
> +static struct i2c_algorithm pch_algorithm = {
> + .master_xfer = pch_xfer,
> + .functionality = pch_func
> +};
> +
> +/**
> + * pch_disbl_int() - Disable PCH I2C interrupts
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + */
> +static void pch_disbl_int(struct i2c_algo_pch_data *adap)
> +{
> + void __iomem *p = adap->pch_base_address;
> +
> + pch_clrbit((adap->pch_base_address), PCH_I2CCTL,
> + NORMAL_INTR_ENBL);
> +
> + iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
> +
> + iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
> +}
> +
> +static int __devinit pch_probe(struct pci_dev *pdev,
> + const struct pci_device_id *id)
> +{
> + int i;
> + void __iomem *base_addr;
> + s32 ret;
> + struct adapter_info *adap_info =
> + kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
this would be a good case to putting the kzalloc() on a different line
from the decleration.
> + pch_pci_dbg(pdev, "Entered.\n");
> +
> + if (adap_info == NULL) {
> + pch_pci_err(pdev, "Memory allocation FAILED\n");
> + return -ENOMEM;
> + }
> +
> + ret = pci_enable_device(pdev);
> + if (ret) {
> + pch_pci_err(pdev, "pci_enable_device FAILED\n");
> + goto err_pci_enable;
> + }
do you really need to put FAILED in capitals here?
> + ret = pci_request_regions(pdev, KBUILD_MODNAME);
> + if (ret) {
> + pch_pci_err(pdev, "pci_request_regions FAILED\n");
> + goto err_pci_req;
> + }
> +
> + base_addr = pci_iomap(pdev, 1, 0);
> +
> + if (base_addr == 0) {
surley that would be == NULL?
> + pch_pci_err(pdev, "pci_iomap FAILED\n");
> + ret = -ENOMEM;
> + goto err_pci_iomap;
> + }
> +
> + adap_info->pch_suspended = false;
> +
> + for (i = 0; i < PCH_MAX_CHN; i++) {
> + adap_info->pch_data[i].p_adapter_info = adap_info;
looks like a pointer to adap_info->pch_data[i] would make the source
smaller and a bit easier to read.
> + adap_info->pch_data[i].pch_adapter.owner = THIS_MODULE;
> + adap_info->pch_data[i].pch_adapter.class = I2C_CLASS_HWMON;
> + strcpy(adap_info->pch_data[i].pch_adapter.name, KBUILD_MODNAME);
> + adap_info->pch_data[i].pch_adapter.algo = &pch_algorithm;
> + adap_info->pch_data[i].pch_adapter.algo_data =
> + &adap_info->pch_data[i];
> +
> + /* (i * 0x80) + base_addr; */
> + adap_info->pch_data[i].pch_base_address = base_addr;
> +
> + adap_info->pch_data[i].pch_adapter.dev.parent = &pdev->dev;
> +
> + ret = i2c_add_adapter(&(adap_info->pch_data[i].pch_adapter));
> +
> + if (ret) {
> + pch_pci_err(pdev, "i2c_add_adapter FAILED\n");
> + goto err_i2c_add_adapter;
> + }
> +
> + pch_init(&adap_info->pch_data[i]);
> + ret = request_irq(pdev->irq, pch_handler_list[i], IRQF_SHARED,
> + KBUILD_MODNAME, &adap_info->pch_data[i]);
> + if (ret) {
> + pch_pci_err(pdev, "request_irq FAILED\n");
> + goto err_request_irq;
> + }
> + }
> +
> + pci_set_drvdata(pdev, adap_info);
> + pch_pci_dbg(pdev, "returns %d.\n", ret);
> + return 0;
> +
> +err_request_irq:
> + for (i = 0; i < PCH_MAX_CHN; i++)
> + i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
> +err_i2c_add_adapter:
> + pci_iounmap(pdev, base_addr);
> +err_pci_iomap:
> + pci_release_regions(pdev);
> +err_pci_req:
> + pci_disable_device(pdev);
> +err_pci_enable:
> + kfree(adap_info);
> + return ret;
> +}
> +
> +static void __devexit pch_remove(struct pci_dev *pdev)
> +{
> + int i;
> +
> + struct adapter_info *adap_info = pci_get_drvdata(pdev);
no need for the blank line.
> +
> +
> + for (i = 0; i < PCH_MAX_CHN; i++) {
> + pch_disbl_int(&adap_info->pch_data[i]);
> + free_irq(pdev->irq, &adap_info->pch_data[i]);
> + i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
> + }
> +
> + if (adap_info->pch_data[0].pch_base_address) {
> + pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
> + adap_info->pch_data[0].pch_base_address = 0;
> + }
> +
> + pci_set_drvdata(pdev, NULL);
> +
> + pci_release_regions(pdev);
> +
> + pci_disable_device(pdev);
> + kfree(adap_info);
> +}
> +
> +#ifdef CONFIG_PM
> +static int pch_suspend(struct pci_dev *pdev, pm_message_t state)
> +{
> + int i;
> + int ret;
> +
> + struct adapter_info *adap_info = pci_get_drvdata(pdev);
> + void __iomem *p = adap_info->pch_data[0].pch_base_address;
>
again, blank line, also see notes on ordering.
> + adap_info->pch_suspended = true;
> +
> + for (i = 0; i < PCH_MAX_CHN; i++) {
> + while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
> + /* Wait until all channel transfers are completed */
> + msleep(1);
> + }
> + /* Disable the i2c interrupts */
> + pch_disbl_int(&adap_info->pch_data[i]);
> + }
> +
> + pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
> + "invoked function pch_disbl_int successfully\n",
> + ioread32(p + 0x08), ioread32(p + 0x30), ioread32(p + 0x44));
magic numbers being used to ioread32?
> + ret = pci_save_state(pdev);
> +
> + if (ret) {
> + pch_pci_err(pdev, "pci_save_state\n");
> + return ret;
> + }
> +
> + pci_enable_wake(pdev, PCI_D3hot, 0);
> + pci_disable_device(pdev);
> + pci_set_power_state(pdev, pci_choose_state(pdev, state));
> +
> + return 0;
> +}
> +
> +static int pch_resume(struct pci_dev *pdev)
> +{
> + struct adapter_info *adap_info = pci_get_drvdata(pdev);
> + int i;
> +
> + pci_set_power_state(pdev, PCI_D0);
> + pci_restore_state(pdev);
> +
> + if (pci_enable_device(pdev) < 0) {
> + pch_pci_err(pdev, "pci_enable_device FAILED in pch_resume\n");
> + return -EIO;
> + }
> +
> + pci_enable_wake(pdev, PCI_D3hot, 0);
> +
> + for (i = 0; i < PCH_MAX_CHN; i++)
> + pch_init(&adap_info->pch_data[i]);
> +
> + adap_info->pch_suspended = false;
> +
> + return 0;
> +}
> +#else
> +#define pch_suspend NULL
> +#define pch_resume NULL
> +#endif
> +
> +static struct pci_driver pch_pcidriver = {
> + .name = KBUILD_MODNAME,
> + .id_table = pch_pcidev_id,
> + .probe = pch_probe,
> + .remove = __devexit_p(pch_remove),
> + .suspend = pch_suspend,
> + .resume = pch_resume
> +};
> +
> +static int __init pch_pci_init(void)
> +{
> + return pci_register_driver(&pch_pcidriver);
> +}
> +
> +static void __exit pch_pci_exit(void)
> +{
> + pci_unregister_driver(&pch_pcidriver);
> +}
> +
> +MODULE_DESCRIPTION("PCH I2C PCI Driver");
> +MODULE_LICENSE("GPL");
no MODULE_AUTHOR?
> +module_init(pch_pci_init);
> +module_exit(pch_pci_exit);
> +module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
> +module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-07 23:55 ` Ben Dooks
0 siblings, 0 replies; 47+ messages in thread
From: Ben Dooks @ 2010-09-07 23:55 UTC (permalink / raw)
To: Masayuki Ohtak
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, joe-6d6DIl74uiNBDgjK7y7TUQ,
yong.y.wang-ral2JQCrhuEAvxtiuMwx3w,
qi.wang-ral2JQCrhuEAvxtiuMwx3w,
andrew.chih.howe.khor-ral2JQCrhuEAvxtiuMwx3w,
arjan-VuQAYsv1563Yd54FQh9/CA, Tomoya MORINAGA, Arnd Bergmann
On Fri, Sep 03, 2010 at 07:19:44PM +0900, Masayuki Ohtak wrote:
> I2C driver of Topcliff PCH
>
> Topcliff PCH is the platform controller hub that is going to be used in
> Intel's upcoming general embedded platform. All IO peripherals in
> Topcliff PCH are actually devices sitting on AMBA bus.
> Topcliff PCH has I2C I/F. Using this I/F, it is able to access system
> devices connected to I2C.
>
> Signed-off-by: Masayuki Ohtake <masa-korg-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>
> Reviewed-by: Linus Walleij <linus.walleij-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>
> ---
> drivers/i2c/busses/Kconfig | 18 +
> drivers/i2c/busses/Makefile | 1 +
> drivers/i2c/busses/i2c-pch.c | 944 ++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 963 insertions(+), 0 deletions(-)
> create mode 100644 drivers/i2c/busses/i2c-pch.c
>
> diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> index bceafbf..c5db1e7 100644
> --- a/drivers/i2c/busses/Kconfig
> +++ b/drivers/i2c/busses/Kconfig
> @@ -613,6 +613,24 @@ config I2C_XILINX
> This driver can also be built as a module. If so, the module
> will be called xilinx_i2c.
>
> +config PCH_I2C
> + tristate "PCH I2C of Intel Topcliff"
> + depends on PCI
> + help
> + This driver is for PCH(Platform controller Hub) I2C of Topcliff which
> + is an IOH(Input/Output Hub) for x86 embedded processor.
> + This driver can access PCH I2C bus device.
> +
> +config PCH_I2C_CH_COUNT
> + int "PCH I2C the number of channel count"
> + range 1 2
> + depends on PCH_I2C
> + help
> + This driver is for PCH(Platform controller Hub) I2C of Topcliff which
> + is an IOH(Input/Output Hub) for x86 embedded processor.
> + The number of I2C buses/channels supported by the PCH I2C controller.
> + PCH I2C of Topcliff supports only one channel.
> +
> comment "External I2C/SMBus adapter drivers"
>
> config I2C_PARPORT
> diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
> index 936880b..aa04135 100644
> --- a/drivers/i2c/busses/Makefile
> +++ b/drivers/i2c/busses/Makefile
> @@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
> obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
> obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
> obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
> +obj-$(CONFIG_PCH_I2C) += i2c-pch.o
>
> # External I2C/SMBus adapter drivers
> obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o
> diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c
> new file mode 100644
> index 0000000..ae55a83
> --- /dev/null
> +++ b/drivers/i2c/busses/i2c-pch.c
> @@ -0,0 +1,944 @@
> +/*
> + * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; version 2 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/kernel.h>
> +#include <linux/delay.h>
> +#include <linux/init.h>
> +#include <linux/errno.h>
> +#include <linux/i2c.h>
> +#include <linux/fs.h>
> +#include <linux/io.h>
> +#include <linux/types.h>
> +#include <linux/interrupt.h>
> +#include <linux/jiffies.h>
> +#include <linux/pci.h>
> +#include <linux/mutex.h>
> +#include <linux/ktime.h>
> +
> +#define PCH_MAX_CHN CONFIG_PCH_I2C_CH_COUNT /* Maximum I2C channels
> + available */
> +#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
> +#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
> +#define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
> +#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
> +#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
> +
> +#define PCH_I2CSADR 0x00 /* I2C slave address register */
> +#define PCH_I2CCTL 0x04 /* I2C control register */
> +#define PCH_I2CSR 0x08 /* I2C status register */
> +#define PCH_I2CDR 0x0C /* I2C data register */
> +#define PCH_I2CMON 0x10 /* I2C bus monitor register */
> +#define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
> +#define PCH_I2CMOD 0x18 /* I2C mode register */
> +#define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
> +#define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
> +#define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
> +#define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
> +#define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
> +#define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
> +#define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
> +#define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
> +#define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
> +#define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
> +#define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
> +#define PCH_I2CTMR 0x48 /* I2C timer register */
> +#define PCH_I2CSRST 0xFC /* I2C reset register */
> +#define PCH_I2CNF 0xF8 /* I2C noise filter register */
> +
> +#define BUS_IDLE_TIMEOUT 20
> +#define PCH_I2CCTL_I2CMEN 0x0080
> +#define TEN_BIT_ADDR_DEFAULT 0xF000
> +#define TEN_BIT_ADDR_MASK 0xF0
> +#define PCH_START 0x0020
> +#define PCH_ESR_START 0x0001
> +#define PCH_BUFF_START 0x1
> +#define PCH_REPSTART 0x0004
> +#define PCH_ACK 0x0008
> +#define PCH_GETACK 0x0001
> +#define CLR_REG 0x0
> +#define I2C_RD 0x1
> +#define I2CMCF_BIT 0x0080
> +#define I2CMIF_BIT 0x0002
> +#define I2CMAL_BIT 0x0010
> +#define I2CBMFI_BIT 0x0001
> +#define I2CBMAL_BIT 0x0002
> +#define I2CBMNA_BIT 0x0004
> +#define I2CBMTO_BIT 0x0008
> +#define I2CBMIS_BIT 0x0010
> +#define I2CESRFI_BIT 0X0001
> +#define I2CESRTO_BIT 0x0002
> +#define I2CESRFIIE_BIT 0x1
> +#define I2CESRTOIE_BIT 0x2
> +#define I2CBMDZ_BIT 0x0040
> +#define I2CBMAG_BIT 0x0020
> +#define I2CMBB_BIT 0x0020
> +#define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
> + I2CBMTO_BIT | I2CBMIS_BIT)
> +#define I2C_ADDR_MSK 0xFF
> +#define I2C_MSB_2B_MSK 0x300
> +#define FAST_MODE_CLK 400
> +#define FAST_MODE_EN 0x0001
> +#define SUB_ADDR_LEN_MAX 4
> +#define BUF_LEN_MAX 32
> +#define PCH_BUFFER_MODE 0x1
> +#define EEPROM_SW_RST_MODE 0x0002
> +#define NORMAL_INTR_ENBL 0x0300
> +#define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
> +#define EEPROM_RST_INTR_DISBL 0x0
> +#define BUFFER_MODE_INTR_ENBL 0x001F
> +#define BUFFER_MODE_INTR_DISBL 0x0
> +#define NORMAL_MODE 0x0
> +#define BUFFER_MODE 0x1
> +#define EEPROM_SR_MODE 0x2
> +#define I2C_TX_MODE 0x0010
> +#define PCH_BUF_TX 0xFFF7
> +#define PCH_BUF_RD 0x0008
> +#define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
> + I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
> +#define I2CMAL_EVENT 0x0001
> +#define I2CMCF_EVENT 0x0002
> +#define I2CBMFI_EVENT 0x0004
> +#define I2CBMAL_EVENT 0x0008
> +#define I2CBMNA_EVENT 0x0010
> +#define I2CBMTO_EVENT 0x0020
> +#define I2CBMIS_EVENT 0x0040
> +#define I2CESRFI_EVENT 0x0080
> +#define I2CESRTO_EVENT 0x0100
> +#define PCI_DEVICE_ID_PCH_I2C 0x8817
> +
> +#define pch_dbg(adap, fmt, arg...) \
> + dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
> +
> +#define pch_err(adap, fmt, arg...) \
> + dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
> +
> +#define pch_pci_err(pdev, fmt, arg...) \
> + dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
> +
> +#define pch_pci_dbg(pdev, fmt, arg...) \
> + dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
> +
> +/**
> + * struct i2c_algo_pch_data - for I2C driver functionalities
> + * @p_adapter_info: stores the reference to adapter_info structure
> + * @pch_adapter: stores the reference to i2c_adapter structure
> + * @pch_base_address: specifies the remapped base address
> + * @pch_buff_mode_en: specifies if buffer mode is enabled
> + * @pch_event_flag: specifies occurrence of interrupt events
> + * @pch_xfer_in_progress: specifies whether the transfer is completed
> + */
> +struct i2c_algo_pch_data {
> + struct adapter_info *p_adapter_info;
> + struct i2c_adapter pch_adapter;
> + void __iomem *pch_base_address;
> + int pch_buff_mode_en;
> + u32 pch_event_flag;
> + bool pch_xfer_in_progress;
> +};
> +
> +/**
> + * struct adapter_info - This structure holds the adapter information for the
> + PCH i2c controller
> + * @pch_data: stores a list of i2c_algo_pch_data
> + * @pch_suspended: specifies whether the system is suspended or not
> + * perhaps with more lines and words.
> + *
> + * pch_data has as many elements as maximum I2C channels
> + */
> +struct adapter_info {
> + struct i2c_algo_pch_data pch_data[PCH_MAX_CHN];
> + bool pch_suspended;
> +};
> +
> +
> +static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
> +static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
> +static wait_queue_head_t pch_event;
> +static DEFINE_MUTEX(pch_mutex);
> +
> +static struct pci_device_id __devinitdata pch_pcidev_id[] = {
> + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_I2C)},
> + {0,}
> +};
> +
> +static irqreturn_t pch_handler_ch0(int irq, void *pData);
> +static irqreturn_t(*pch_handler_list[PCH_MAX_CHN]) (int irq, void *pData) = {
> + pch_handler_ch0,
> +};
> +
> +static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
> +{
> + u32 val;
> + val = ioread32(addr + offset);
> + val |= bitmask;
> + iowrite32(val, addr + offset);
> +}
> +
> +static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
> +{
> + u32 val;
> + val = ioread32(addr + offset);
> + val &= (~bitmask);
> + iowrite32(val, addr + offset);
> +}
> +
> +/**
> + * pch_init() - hardware initialization of I2C module
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + */
> +static void pch_init(struct i2c_algo_pch_data *adap)
> +{
> + u32 pch_i2cbc;
> + u32 pch_i2ctmr;
> + u32 reg_value;
> + void __iomem *p = adap->pch_base_address;
my personal preference is to put the larger items at the top of the list.
> + /* reset I2C controller */
> + iowrite32(0x01, p + PCH_I2CSRST);
> + iowrite32(0x0, p + PCH_I2CSRST);
> + /* Initialize I2C registers */
> + iowrite32(CLR_REG, p + PCH_I2CCTL);
> + iowrite32(CLR_REG, p + PCH_I2CMOD);
> + iowrite32(CLR_REG, p + PCH_I2CBUFFOR);
> + iowrite32(CLR_REG, p + PCH_I2CBUFSLV);
> + iowrite32(CLR_REG, p + PCH_I2CBUFSUB);
> + iowrite32(CLR_REG, p + PCH_I2CBUFMSK);
> + iowrite32(CLR_REG, p + PCH_I2CESRFOR);
> + iowrite32(CLR_REG, p + PCH_I2CESRMSK);
> + iowrite32(0x21, p + PCH_I2CNF);
> +
> + reg_value = PCH_I2CCTL_I2CMEN;
> + pch_setbit((adap->pch_base_address), PCH_I2CCTL,
> + PCH_I2CCTL_I2CMEN);
> +
> + if (pch_i2c_speed != 400)
> + pch_i2c_speed = 100;
> +
> + if (pch_i2c_speed == FAST_MODE_CLK) {
> + reg_value |= FAST_MODE_EN;
> + pch_dbg(adap, "Fast mode enabled\n");
> + }
> +
> + if (pch_clk <= 0 || pch_clk > PCH_MAX_CLK)
> + pch_clk = 62500;
> +
> + pch_i2cbc = ((pch_clk) + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
do you really need the () around pch_clk? there seems to be quite a few
of these around. you also don't need them around pch_i2c_speed * 4. I would
like to see these gone.
> + /* Set transfer speed in I2CBC */
> + iowrite32(pch_i2cbc, p + PCH_I2CBC);
> +
> + pch_i2ctmr = (pch_clk) / 8;
> + iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
> +
> + reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
> + iowrite32(reg_value, p + PCH_I2CCTL);
> +
> + pch_dbg(adap,
> + "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
> + ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
> +
> + init_waitqueue_head(&pch_event);
> +}
> +
> +static inline int ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
> +{
> + return cmp1.tv64 < cmp2.tv64;
> +}
surely this should be with the ktime headers?
> +/**
> + * pch_wait_for_bus_idle() - check the status of bus.
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + * @timeout: waiting time counter (us).
> + */
> +static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
> + s32 timeout)
> +{
> + void __iomem *p = adap->pch_base_address;
> +
> + /* MAX timeout value is timeout*1000*1000nsec */
> + ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
> + do {
> + if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
> + break;
> + msleep(1);
> + } while (ktime_lt(ktime_get(), ns_val));
> +
> + pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
> +
> + if (timeout == 0) {
> + pch_err(adap, "return%d\n", -ETIME);
how about just printing timedout? would be easier to work out what
happened.
> + return -ETIME;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * pch_start() - Generate I2C start condition in normal mode.
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + *
> + * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
> + */
> +static void pch_start(struct i2c_algo_pch_data *adap)
> +{
> + void __iomem *p = adap->pch_base_address;
> + pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
> + pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
again with the ()s.
> +static s32 pch_getack(struct i2c_algo_pch_data *adap)
> +{
> + u32 reg_val;
> + void __iomem *p = adap->pch_base_address;
> + reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
> +
> + if (reg_val != 0) {
> + pch_err(adap, "return%d\n", -EPROTO);
> + return -EPROTO;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * pch_stop() - generate stop condition in normal mode.
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + */
> +static void pch_stop(struct i2c_algo_pch_data *adap)
> +{
> + void __iomem *p = adap->pch_base_address;
> + pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
> + /* clear the start bit */
> + pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
> +}
> +
> +/**
> + * pch_repstart() - generate repeated start condition in normal mode
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + */
> +static void pch_repstart(struct i2c_algo_pch_data *adap)
> +{
> + void __iomem *p = adap->pch_base_address;
> + pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
> + pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_REPSTART);
> +}
> +
> +/**
> + * pch_writebytes() - write data to I2C bus in normal mode
> + * @i2c_adap: Pointer to the struct i2c_adapter.
> + * @last: specifies whether last message or not.
> + * In the case of compound mode it will be 1 for last message,
> + * otherwise 0.
> + * @first: specifies whether first message or not.
> + * 1 for first message otherwise 0.
> + */
> +static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
> + u32 last, u32 first)
> +{
> + struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
> + u8 *buf;
> + u32 length;
> + u32 addr;
> + u32 addr_2_msb;
> + u32 addr_8_lsb;
> + s32 wrcount;
> + void __iomem *p = adap->pch_base_address;
> + length = msgs->len;
> + buf = msgs->buf;
> + addr = msgs->addr;
blank line between decls and code please.
> + /* enable master tx */
> + pch_setbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
this is the last warning on ()s...
> + pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
> + length);
> +
> + if (first) {
> + if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
> + return -ETIME;
> + }
hmm, -ETIME versus -ETIMEDOUT elsewhere?
> + if (msgs->flags & I2C_M_TEN) {
> + addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
> + iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
> + if (first)
> + pch_start(adap);
> + if ((pch_wait_for_xfer_complete(adap) == 0) &&
> + (pch_getack(adap) == 0)) {
and no need for most of the ()s here...
> + addr_8_lsb = (addr & I2C_ADDR_MSK);
> + iowrite32(addr_8_lsb, p + PCH_I2CDR);
> + } else {
> + pch_stop(adap);
> + return -ETIME;
> + }
> + } else {
> + /* set 7 bit slave address and R/W bit as 0 */
> + iowrite32(addr << 1, p + PCH_I2CDR);
> + if (first)
> + pch_start(adap);
> + }
> +
> + if ((pch_wait_for_xfer_complete(adap) == 0) &&
> + (pch_getack(adap) == 0)) {
> + for (wrcount = 0; wrcount < length; ++wrcount) {
> + /* write buffer value to I2C data register */
> + iowrite32(buf[wrcount], p + PCH_I2CDR);
> + pch_dbg(adap, "writing %x to Data register\n",
> + buf[wrcount]);
> +
> + if (pch_wait_for_xfer_complete(adap) != 0)
> + return -ETIME;
> +
> + if (pch_getack(adap))
> + return -ETIME;
you sure it isn't -EIO here if ack problem?
> + }
> +
> + /* check if this is the last message */
> + if (last)
> + pch_stop(adap);
> + else
> + pch_repstart(adap);
> + } else {
> + pch_stop(adap);
> + return -EIO;
> + }
> +
> + pch_dbg(adap, "return=%d\n", wrcount);
> +
> + return wrcount;
> +}
> +
> +/**
> + * pch_sendack() - send ACK
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + */
> +static void pch_sendack(struct i2c_algo_pch_data *adap)
> +{
> + void __iomem *p = adap->pch_base_address;
> + pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
> + pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
> +}
> +
> +/**
> + * pch_sendnack() - send NACK
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + */
> +static void pch_sendnack(struct i2c_algo_pch_data *adap)
> +{
> + void __iomem *p = adap->pch_base_address;
> + pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
> + pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
> +}
> +
> +/**
> + * pch_readbytes() - read data from I2C bus in normal mode.
> + * @i2c_adap: Pointer to the struct i2c_adapter.
> + * @msgs: Pointer to i2c_msg structure.
> + * @last: specifies whether last message or not.
> + * @first: specifies whether first message or not.
> + */
> +s32 pch_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
> + u32 last, u32 first)
> +{
> + struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
> +
> + u8 *buf;
> + u32 count;
> + u32 length;
> + u32 addr;
> + u32 addr_2_msb;
> + void __iomem *p = adap->pch_base_address;
> + length = msgs->len;
> + buf = msgs->buf;
> + addr = msgs->addr;
> +
> + /* enable master reception */
> + pch_clrbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
> +
> + if (first) {
> + if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
> + return -ETIME;
> + }
> +
> + if (msgs->flags & I2C_M_TEN) {
> + addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
> + iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
> +
> + } else {
> + /* 7 address bits + R/W bit */
> + addr = (((addr) << 1) | (I2C_RD));
> + iowrite32(addr, p + PCH_I2CDR);
> + }
> +
> + /* check if it is the first message */
> + if (first)
> + pch_start(adap);
> +
> + if ((pch_wait_for_xfer_complete(adap) == 0) &&
> + (pch_getack(adap) == 0)) {
> + pch_dbg(adap, "return %d\n", 0);
> +
> + if (length == 0) {
> + pch_stop(adap);
> + ioread32(p + PCH_I2CDR); /* Dummy read needs */
> +
> + count = length;
> + } else {
> + int read_index;
> + int loop;
> + pch_sendack(adap);
> +
> + /* Dummy read */
> + for (loop = 1, read_index = 0; loop < length; loop++) {
> + buf[read_index] = ioread32(p + PCH_I2CDR);
> +
> + if (loop != 1)
> + read_index++;
> +
> + if (pch_wait_for_xfer_complete(adap) != 0) {
> + pch_stop(adap);
> + return -ETIME;
> + }
> + } /* end for */
> +
> + pch_sendnack(adap);
> +
> + buf[read_index] = ioread32(p + PCH_I2CDR);
> +
> + if (length != 1)
> + read_index++;
> +
> + if (pch_wait_for_xfer_complete(adap) == 0) {
> + if (last)
> + pch_stop(adap);
> + else
> + pch_repstart(adap);
> +
> + buf[read_index++] = ioread32(p + PCH_I2CDR);
> + count = read_index;
> + } else {
> + count = -ETIME;
> + }
> +
> + }
> + } else {
> + count = -ETIME;
> + pch_stop(adap);
> + }
> +
> + return count;
> +}
> +
> +/**
> + * pch_cb_ch0() - Interrupt handler Call back function
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + */
> +static void pch_cb_ch0(struct i2c_algo_pch_data *adap)
> +{
> + u32 sts;
> + void __iomem *p = adap->pch_base_address;
> +
> + sts = ioread32(p + PCH_I2CSR);
> + sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
> + if (I2CMAL_BIT & sts)
> + adap->pch_event_flag |= I2CMAL_EVENT;
> +
> + if (I2CMCF_BIT & sts)
> + adap->pch_event_flag |= I2CMCF_EVENT;
> +
> + /* clear the applicable bits */
> + pch_clrbit((adap->pch_base_address), PCH_I2CSR, sts);
> +
> + pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
> +
> + wake_up_interruptible(&pch_event);
> +}
> +
> +/**
> + * pch_handler_ch0() - interrupt handler for the PCH I2C controller
> + * @irq: irq number.
> + * @pData: cookie passed back to the handler function.
> + */
> +static irqreturn_t pch_handler_ch0(int irq, void *pData)
> +{
> + s32 reg_val;
> +
> + struct i2c_algo_pch_data *adap_data = (struct i2c_algo_pch_data *)pData;
> + void __iomem *p = adap_data->pch_base_address;
> + u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE);
> +
> + if (mode != NORMAL_MODE) {
> + pch_err(adap_data, "I2C mode is not supported\n");
> + return IRQ_NONE;
> + }
> +
> + reg_val = ioread32(p + PCH_I2CSR);
> + if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
> + pch_cb_ch0(adap_data);
> + else
> + return IRQ_NONE;
> +
> + return IRQ_HANDLED;
> +}
> +#if 0
> + if (mode == NORMAL_MODE) {
> + reg_val = ioread32(p + PCH_I2CSR);
> + if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
> + pch_cb_ch0(adap_data);
> + else
> + goto err_out;
> + } else {
> + pch_err(adap_data, "I2C mode is not supported\n");
> + goto err_out;
> + }
> + return IRQ_HANDLED;
> +
> +err_out:
> + return IRQ_NONE;
> +}
> +#endif
please, no #if 0. either remove completely or do something with it.
> +/**
> + * pch_xfer() - Reading adnd writing data through I2C bus
> + * @i2c_adap: Pointer to the struct i2c_adapter.
> + * @msgs: Pointer to i2c_msg structure.
> + * @num: number of messages.
> + */
> +static s32 pch_xfer(struct i2c_adapter *i2c_adap,
> + struct i2c_msg *msgs, s32 num)
> +{
> + struct i2c_msg *pmsg;
> + u32 i;
> + u32 status;
> + u32 msglen;
> + u32 subaddrlen;
> + s32 ret;
> +
> + struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
> +
> + ret = mutex_lock_interruptible(&pch_mutex);
> + if (ret)
> + return -ERESTARTSYS;
> +
> + if (adap->p_adapter_info->pch_suspended) {
> + mutex_unlock(&pch_mutex);
> + return -EBUSY;
> + }
> +
> + pch_dbg(adap, "adap->p_adapter_info->pch_suspended is %d\n",
> + adap->p_adapter_info->pch_suspended);
> + /* transfer not completed */
> + adap->pch_xfer_in_progress = true;
> +
> + for (i = 0; i < num; i++) {
> + pmsg = &msgs[i];
> + pmsg->flags |= adap->pch_buff_mode_en;
> + status = pmsg->flags;
> + pch_dbg(adap,
> + "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
> + /* calculate sub address length and message length */
> + /* these are applicable only for buffer mode */
> + subaddrlen = pmsg->buf[0];
> + /* calculate actual message length excluding
> + * the sub address fields */
> + msglen = (pmsg->len) - (subaddrlen + 1);
> + if (status & (I2C_M_RD)) {
> + pch_dbg(adap, "invoking pch_readbytes\n");
> + ret = pch_readbytes(i2c_adap, pmsg, (i + 1 == num),
> + (i == 0));
> + } else {
> + pch_dbg(adap, "invoking pch_writebytes\n");
> + ret = pch_writebytes(i2c_adap, pmsg, (i + 1 == num),
> + (i == 0));
> + }
> +
> + }
> +
> + adap->pch_xfer_in_progress = false; /* transfer completed */
> +
> + mutex_unlock(&pch_mutex);
> +
> + return ret;
> +}
> +
> +/**
> + * pch_func() - return the functionality of the I2C driver
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + */
> +static u32 pch_func(struct i2c_adapter *adap)
> +{
> + u32 ret;
> + ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
> + return ret;
> +}
how about just return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
> +static struct i2c_algorithm pch_algorithm = {
> + .master_xfer = pch_xfer,
> + .functionality = pch_func
> +};
> +
> +/**
> + * pch_disbl_int() - Disable PCH I2C interrupts
> + * @adap: Pointer to struct i2c_algo_pch_data.
> + */
> +static void pch_disbl_int(struct i2c_algo_pch_data *adap)
> +{
> + void __iomem *p = adap->pch_base_address;
> +
> + pch_clrbit((adap->pch_base_address), PCH_I2CCTL,
> + NORMAL_INTR_ENBL);
> +
> + iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
> +
> + iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
> +}
> +
> +static int __devinit pch_probe(struct pci_dev *pdev,
> + const struct pci_device_id *id)
> +{
> + int i;
> + void __iomem *base_addr;
> + s32 ret;
> + struct adapter_info *adap_info =
> + kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
this would be a good case to putting the kzalloc() on a different line
from the decleration.
> + pch_pci_dbg(pdev, "Entered.\n");
> +
> + if (adap_info == NULL) {
> + pch_pci_err(pdev, "Memory allocation FAILED\n");
> + return -ENOMEM;
> + }
> +
> + ret = pci_enable_device(pdev);
> + if (ret) {
> + pch_pci_err(pdev, "pci_enable_device FAILED\n");
> + goto err_pci_enable;
> + }
do you really need to put FAILED in capitals here?
> + ret = pci_request_regions(pdev, KBUILD_MODNAME);
> + if (ret) {
> + pch_pci_err(pdev, "pci_request_regions FAILED\n");
> + goto err_pci_req;
> + }
> +
> + base_addr = pci_iomap(pdev, 1, 0);
> +
> + if (base_addr == 0) {
surley that would be == NULL?
> + pch_pci_err(pdev, "pci_iomap FAILED\n");
> + ret = -ENOMEM;
> + goto err_pci_iomap;
> + }
> +
> + adap_info->pch_suspended = false;
> +
> + for (i = 0; i < PCH_MAX_CHN; i++) {
> + adap_info->pch_data[i].p_adapter_info = adap_info;
looks like a pointer to adap_info->pch_data[i] would make the source
smaller and a bit easier to read.
> + adap_info->pch_data[i].pch_adapter.owner = THIS_MODULE;
> + adap_info->pch_data[i].pch_adapter.class = I2C_CLASS_HWMON;
> + strcpy(adap_info->pch_data[i].pch_adapter.name, KBUILD_MODNAME);
> + adap_info->pch_data[i].pch_adapter.algo = &pch_algorithm;
> + adap_info->pch_data[i].pch_adapter.algo_data =
> + &adap_info->pch_data[i];
> +
> + /* (i * 0x80) + base_addr; */
> + adap_info->pch_data[i].pch_base_address = base_addr;
> +
> + adap_info->pch_data[i].pch_adapter.dev.parent = &pdev->dev;
> +
> + ret = i2c_add_adapter(&(adap_info->pch_data[i].pch_adapter));
> +
> + if (ret) {
> + pch_pci_err(pdev, "i2c_add_adapter FAILED\n");
> + goto err_i2c_add_adapter;
> + }
> +
> + pch_init(&adap_info->pch_data[i]);
> + ret = request_irq(pdev->irq, pch_handler_list[i], IRQF_SHARED,
> + KBUILD_MODNAME, &adap_info->pch_data[i]);
> + if (ret) {
> + pch_pci_err(pdev, "request_irq FAILED\n");
> + goto err_request_irq;
> + }
> + }
> +
> + pci_set_drvdata(pdev, adap_info);
> + pch_pci_dbg(pdev, "returns %d.\n", ret);
> + return 0;
> +
> +err_request_irq:
> + for (i = 0; i < PCH_MAX_CHN; i++)
> + i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
> +err_i2c_add_adapter:
> + pci_iounmap(pdev, base_addr);
> +err_pci_iomap:
> + pci_release_regions(pdev);
> +err_pci_req:
> + pci_disable_device(pdev);
> +err_pci_enable:
> + kfree(adap_info);
> + return ret;
> +}
> +
> +static void __devexit pch_remove(struct pci_dev *pdev)
> +{
> + int i;
> +
> + struct adapter_info *adap_info = pci_get_drvdata(pdev);
no need for the blank line.
> +
> +
> + for (i = 0; i < PCH_MAX_CHN; i++) {
> + pch_disbl_int(&adap_info->pch_data[i]);
> + free_irq(pdev->irq, &adap_info->pch_data[i]);
> + i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
> + }
> +
> + if (adap_info->pch_data[0].pch_base_address) {
> + pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
> + adap_info->pch_data[0].pch_base_address = 0;
> + }
> +
> + pci_set_drvdata(pdev, NULL);
> +
> + pci_release_regions(pdev);
> +
> + pci_disable_device(pdev);
> + kfree(adap_info);
> +}
> +
> +#ifdef CONFIG_PM
> +static int pch_suspend(struct pci_dev *pdev, pm_message_t state)
> +{
> + int i;
> + int ret;
> +
> + struct adapter_info *adap_info = pci_get_drvdata(pdev);
> + void __iomem *p = adap_info->pch_data[0].pch_base_address;
>
again, blank line, also see notes on ordering.
> + adap_info->pch_suspended = true;
> +
> + for (i = 0; i < PCH_MAX_CHN; i++) {
> + while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
> + /* Wait until all channel transfers are completed */
> + msleep(1);
> + }
> + /* Disable the i2c interrupts */
> + pch_disbl_int(&adap_info->pch_data[i]);
> + }
> +
> + pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
> + "invoked function pch_disbl_int successfully\n",
> + ioread32(p + 0x08), ioread32(p + 0x30), ioread32(p + 0x44));
magic numbers being used to ioread32?
> + ret = pci_save_state(pdev);
> +
> + if (ret) {
> + pch_pci_err(pdev, "pci_save_state\n");
> + return ret;
> + }
> +
> + pci_enable_wake(pdev, PCI_D3hot, 0);
> + pci_disable_device(pdev);
> + pci_set_power_state(pdev, pci_choose_state(pdev, state));
> +
> + return 0;
> +}
> +
> +static int pch_resume(struct pci_dev *pdev)
> +{
> + struct adapter_info *adap_info = pci_get_drvdata(pdev);
> + int i;
> +
> + pci_set_power_state(pdev, PCI_D0);
> + pci_restore_state(pdev);
> +
> + if (pci_enable_device(pdev) < 0) {
> + pch_pci_err(pdev, "pci_enable_device FAILED in pch_resume\n");
> + return -EIO;
> + }
> +
> + pci_enable_wake(pdev, PCI_D3hot, 0);
> +
> + for (i = 0; i < PCH_MAX_CHN; i++)
> + pch_init(&adap_info->pch_data[i]);
> +
> + adap_info->pch_suspended = false;
> +
> + return 0;
> +}
> +#else
> +#define pch_suspend NULL
> +#define pch_resume NULL
> +#endif
> +
> +static struct pci_driver pch_pcidriver = {
> + .name = KBUILD_MODNAME,
> + .id_table = pch_pcidev_id,
> + .probe = pch_probe,
> + .remove = __devexit_p(pch_remove),
> + .suspend = pch_suspend,
> + .resume = pch_resume
> +};
> +
> +static int __init pch_pci_init(void)
> +{
> + return pci_register_driver(&pch_pcidriver);
> +}
> +
> +static void __exit pch_pci_exit(void)
> +{
> + pci_unregister_driver(&pch_pcidriver);
> +}
> +
> +MODULE_DESCRIPTION("PCH I2C PCI Driver");
> +MODULE_LICENSE("GPL");
no MODULE_AUTHOR?
> +module_init(pch_pci_init);
> +module_exit(pch_pci_exit);
> +module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
> +module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
^ permalink raw reply [flat|nested] 47+ messages in thread
* [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-06 1:31 ` Masayuki Ohtak
0 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtak @ 2010-09-06 1:31 UTC (permalink / raw)
To: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c, linux-kernel, joe, Linus Walleij,
Wolfram Sang <w.sang@pengutronix.de>; Alan Cox
Cc: yong.y.wang, qi.wang, andrew.chih.howe.khor, arjan,
Tomoya MORINAGA, Arnd Bergmann, Masayuki Ohtake
Hi Alan and Wolfram Sang
Sorry, previous patch is invalid patch.
Please refer this patch.
Thanks, Ohtake (OKISemi)
---
I2C driver of Topcliff PCH
Topcliff PCH is the platform controller hub that is going to be used in
Intel's upcoming general embedded platform. All IO peripherals in
Topcliff PCH are actually devices sitting on AMBA bus.
Topcliff PCH has I2C I/F. Using this I/F, it is able to access system
devices connected to I2C.
Signed-off-by: Masayuki Ohtake <masa-korg@dsn.okisemi.com>
Reviewed-by: Linus Walleij <linus.walleij@stericsson.com>
---
drivers/i2c/busses/Kconfig | 8 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-pch.c | 923 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 932 insertions(+), 0 deletions(-)
create mode 100644 drivers/i2c/busses/i2c-pch.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index bceafbf..b7b132d 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -613,6 +613,14 @@ config I2C_XILINX
This driver can also be built as a module. If so, the module
will be called xilinx_i2c.
+config PCH_I2C
+ tristate "PCH I2C of Intel Topcliff"
+ depends on PCI
+ help
+ This driver is for PCH(Platform controller Hub) I2C of Topcliff which
+ is an IOH(Input/Output Hub) for x86 embedded processor.
+ This driver can access PCH I2C bus device.
+
comment "External I2C/SMBus adapter drivers"
config I2C_PARPORT
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 936880b..aa04135 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
+obj-$(CONFIG_PCH_I2C) += i2c-pch.o
# External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o
diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c
new file mode 100644
index 0000000..abaef96
--- /dev/null
+++ b/drivers/i2c/busses/i2c-pch.c
@@ -0,0 +1,923 @@
+/*
+ * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/pci.h>
+#include <linux/mutex.h>
+#include <linux/ktime.h>
+
+#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
+#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
+#define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
+#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
+#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
+
+#define PCH_I2CSADR 0x00 /* I2C slave address register */
+#define PCH_I2CCTL 0x04 /* I2C control register */
+#define PCH_I2CSR 0x08 /* I2C status register */
+#define PCH_I2CDR 0x0C /* I2C data register */
+#define PCH_I2CMON 0x10 /* I2C bus monitor register */
+#define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
+#define PCH_I2CMOD 0x18 /* I2C mode register */
+#define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
+#define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
+#define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
+#define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
+#define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
+#define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
+#define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
+#define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
+#define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
+#define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
+#define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
+#define PCH_I2CTMR 0x48 /* I2C timer register */
+#define PCH_I2CSRST 0xFC /* I2C reset register */
+#define PCH_I2CNF 0xF8 /* I2C noise filter register */
+
+#define BUS_IDLE_TIMEOUT 20
+#define PCH_I2CCTL_I2CMEN 0x0080
+#define TEN_BIT_ADDR_DEFAULT 0xF000
+#define TEN_BIT_ADDR_MASK 0xF0
+#define PCH_START 0x0020
+#define PCH_ESR_START 0x0001
+#define PCH_BUFF_START 0x1
+#define PCH_REPSTART 0x0004
+#define PCH_ACK 0x0008
+#define PCH_GETACK 0x0001
+#define CLR_REG 0x0
+#define I2C_RD 0x1
+#define I2CMCF_BIT 0x0080
+#define I2CMIF_BIT 0x0002
+#define I2CMAL_BIT 0x0010
+#define I2CBMFI_BIT 0x0001
+#define I2CBMAL_BIT 0x0002
+#define I2CBMNA_BIT 0x0004
+#define I2CBMTO_BIT 0x0008
+#define I2CBMIS_BIT 0x0010
+#define I2CESRFI_BIT 0X0001
+#define I2CESRTO_BIT 0x0002
+#define I2CESRFIIE_BIT 0x1
+#define I2CESRTOIE_BIT 0x2
+#define I2CBMDZ_BIT 0x0040
+#define I2CBMAG_BIT 0x0020
+#define I2CMBB_BIT 0x0020
+#define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
+ I2CBMTO_BIT | I2CBMIS_BIT)
+#define I2C_ADDR_MSK 0xFF
+#define I2C_MSB_2B_MSK 0x300
+#define FAST_MODE_CLK 400
+#define FAST_MODE_EN 0x0001
+#define SUB_ADDR_LEN_MAX 4
+#define BUF_LEN_MAX 32
+#define PCH_BUFFER_MODE 0x1
+#define EEPROM_SW_RST_MODE 0x0002
+#define NORMAL_INTR_ENBL 0x0300
+#define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
+#define EEPROM_RST_INTR_DISBL 0x0
+#define BUFFER_MODE_INTR_ENBL 0x001F
+#define BUFFER_MODE_INTR_DISBL 0x0
+#define NORMAL_MODE 0x0
+#define BUFFER_MODE 0x1
+#define EEPROM_SR_MODE 0x2
+#define I2C_TX_MODE 0x0010
+#define PCH_BUF_TX 0xFFF7
+#define PCH_BUF_RD 0x0008
+#define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
+ I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
+#define I2CMAL_EVENT 0x0001
+#define I2CMCF_EVENT 0x0002
+#define I2CBMFI_EVENT 0x0004
+#define I2CBMAL_EVENT 0x0008
+#define I2CBMNA_EVENT 0x0010
+#define I2CBMTO_EVENT 0x0020
+#define I2CBMIS_EVENT 0x0040
+#define I2CESRFI_EVENT 0x0080
+#define I2CESRTO_EVENT 0x0100
+#define PCI_DEVICE_ID_PCH_I2C 0x8817
+
+#define pch_dbg(adap, fmt, arg...) \
+ dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
+
+#define pch_err(adap, fmt, arg...) \
+ dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
+
+#define pch_pci_err(pdev, fmt, arg...) \
+ dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
+
+#define pch_pci_dbg(pdev, fmt, arg...) \
+ dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
+
+/**
+ * struct i2c_algo_pch_data - for I2C driver functionalities
+ * @p_adapter_info: stores the reference to adapter_info structure
+ * @pch_adapter: stores the reference to i2c_adapter structure
+ * @pch_base_address: specifies the remapped base address
+ * @pch_buff_mode_en: specifies if buffer mode is enabled
+ * @pch_event_flag: specifies occurrence of interrupt events
+ * @pch_xfer_in_progress: specifies whether the transfer is completed
+ */
+struct i2c_algo_pch_data {
+ struct adapter_info *p_adapter_info;
+ struct i2c_adapter pch_adapter;
+ void __iomem *pch_base_address;
+ int pch_buff_mode_en;
+ u32 pch_event_flag;
+ bool pch_xfer_in_progress;
+};
+
+/**
+ * struct adapter_info - This structure holds the adapter information for the
+ PCH i2c controller
+ * @pch_data: stores a list of i2c_algo_pch_data
+ * @pch_suspended: specifies whether the system is suspended or not
+ * perhaps with more lines and words.
+ *
+ * pch_data has as many elements as maximum I2C channels
+ */
+struct adapter_info {
+ struct i2c_algo_pch_data pch_data;
+ bool pch_suspended;
+};
+
+
+static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
+static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
+static wait_queue_head_t pch_event;
+static DEFINE_MUTEX(pch_mutex);
+
+static struct pci_device_id __devinitdata pch_pcidev_id[] = {
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_I2C)},
+ {0,}
+};
+
+static irqreturn_t pch_handler(int irq, void *pData);
+
+static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ u32 val;
+ val = ioread32(addr + offset);
+ val |= bitmask;
+ iowrite32(val, addr + offset);
+}
+
+static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ u32 val;
+ val = ioread32(addr + offset);
+ val &= (~bitmask);
+ iowrite32(val, addr + offset);
+}
+
+/**
+ * pch_init() - hardware initialization of I2C module
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_init(struct i2c_algo_pch_data *adap)
+{
+ u32 pch_i2cbc;
+ u32 pch_i2ctmr;
+ u32 reg_value;
+ void __iomem *p = adap->pch_base_address;
+
+ /* reset I2C controller */
+ iowrite32(0x01, p + PCH_I2CSRST);
+ iowrite32(0x0, p + PCH_I2CSRST);
+ /* Initialize I2C registers */
+ iowrite32(CLR_REG, p + PCH_I2CCTL);
+ iowrite32(CLR_REG, p + PCH_I2CMOD);
+ iowrite32(CLR_REG, p + PCH_I2CBUFFOR);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSLV);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSUB);
+ iowrite32(CLR_REG, p + PCH_I2CBUFMSK);
+ iowrite32(CLR_REG, p + PCH_I2CESRFOR);
+ iowrite32(CLR_REG, p + PCH_I2CESRMSK);
+ iowrite32(0x21, p + PCH_I2CNF);
+
+ reg_value = PCH_I2CCTL_I2CMEN;
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL,
+ PCH_I2CCTL_I2CMEN);
+
+ if (pch_i2c_speed != 400)
+ pch_i2c_speed = 100;
+
+ if (pch_i2c_speed == FAST_MODE_CLK) {
+ reg_value |= FAST_MODE_EN;
+ pch_dbg(adap, "Fast mode enabled\n");
+ }
+
+ if (pch_clk <= 0 || pch_clk > PCH_MAX_CLK)
+ pch_clk = 62500;
+
+ pch_i2cbc = ((pch_clk) + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
+ /* Set transfer speed in I2CBC */
+ iowrite32(pch_i2cbc, p + PCH_I2CBC);
+
+ pch_i2ctmr = (pch_clk) / 8;
+ iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
+
+ reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
+ iowrite32(reg_value, p + PCH_I2CCTL);
+
+ pch_dbg(adap,
+ "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
+ ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
+
+ init_waitqueue_head(&pch_event);
+}
+
+static inline int ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
+{
+ return cmp1.tv64 < cmp2.tv64;
+}
+
+/**
+ * pch_wait_for_bus_idle() - check the status of bus.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ * @timeout: waiting time counter (us).
+ */
+static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
+ s32 timeout)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ /* MAX timeout value is timeout*1000*1000nsec */
+ ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
+ do {
+ if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
+ break;
+ msleep(1);
+ } while (ktime_lt(ktime_get(), ns_val));
+
+ pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
+
+ if (timeout == 0) {
+ pch_err(adap, "return%d\n", -ETIME);
+ return -ETIME;
+ }
+
+ return 0;
+}
+
+/**
+ * pch_start() - Generate I2C start condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ *
+ * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
+ */
+static void pch_start(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+}
+
+/**
+ * pch_wait_for_xfer_complete() - initiates a wait for the tx complete event
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
+{
+ s32 ret;
+ ret = wait_event_timeout(pch_event,
+ (adap->pch_event_flag != 0), msecs_to_jiffies(50));
+ if (ret < 0) {
+ pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
+ return ret;
+ }
+
+ if (ret == 0) {
+ pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
+ return -ETIMEDOUT;
+ }
+
+ if (adap->pch_event_flag & I2C_ERROR_MASK) {
+ pch_err(adap, "error bits set: %x\n", adap->pch_event_flag);
+ return -EIO;
+ }
+
+ adap->pch_event_flag = 0;
+ ret = 0;
+
+ return ret;
+}
+
+/**
+ * pch_getack() - to confirm ACK/NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_getack(struct i2c_algo_pch_data *adap)
+{
+ u32 reg_val;
+ void __iomem *p = adap->pch_base_address;
+ reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
+
+ if (reg_val != 0) {
+ pch_err(adap, "return%d\n", -EPROTO);
+ return -EPROTO;
+ }
+
+ return 0;
+}
+
+/**
+ * pch_stop() - generate stop condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_stop(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ /* clear the start bit */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+}
+
+/**
+ * pch_repstart() - generate repeated start condition in normal mode
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_repstart(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_REPSTART);
+}
+
+/**
+ * pch_writebytes() - write data to I2C bus in normal mode
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @last: specifies whether last message or not.
+ * In the case of compound mode it will be 1 for last message,
+ * otherwise 0.
+ * @first: specifies whether first message or not.
+ * 1 for first message otherwise 0.
+ */
+static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+ u8 *buf;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ u32 addr_8_lsb;
+ s32 wrcount;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+ /* enable master tx */
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
+ length);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ addr_8_lsb = (addr & I2C_ADDR_MSK);
+ iowrite32(addr_8_lsb, p + PCH_I2CDR);
+ } else {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } else {
+ /* set 7 bit slave address and R/W bit as 0 */
+ iowrite32(addr << 1, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ }
+
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ for (wrcount = 0; wrcount < length; ++wrcount) {
+ /* write buffer value to I2C data register */
+ iowrite32(buf[wrcount], p + PCH_I2CDR);
+ pch_dbg(adap, "writing %x to Data register\n",
+ buf[wrcount]);
+
+ if (pch_wait_for_xfer_complete(adap) != 0)
+ return -ETIME;
+
+ if (pch_getack(adap))
+ return -ETIME;
+ }
+
+ /* check if this is the last message */
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+ } else {
+ pch_stop(adap);
+ return -EIO;
+ }
+
+ pch_dbg(adap, "return=%d\n", wrcount);
+
+ return wrcount;
+}
+
+/**
+ * pch_sendack() - send ACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+}
+
+/**
+ * pch_sendnack() - send NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendnack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+}
+
+/**
+ * pch_readbytes() - read data from I2C bus in normal mode.
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @last: specifies whether last message or not.
+ * @first: specifies whether first message or not.
+ */
+s32 pch_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ u8 *buf;
+ u32 count;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+
+ /* enable master reception */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+
+ } else {
+ /* 7 address bits + R/W bit */
+ addr = (((addr) << 1) | (I2C_RD));
+ iowrite32(addr, p + PCH_I2CDR);
+ }
+
+ /* check if it is the first message */
+ if (first)
+ pch_start(adap);
+
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ pch_dbg(adap, "return %d\n", 0);
+
+ if (length == 0) {
+ pch_stop(adap);
+ ioread32(p + PCH_I2CDR); /* Dummy read needs */
+
+ count = length;
+ } else {
+ int read_index;
+ int loop;
+ pch_sendack(adap);
+
+ /* Dummy read */
+ for (loop = 1, read_index = 0; loop < length; loop++) {
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (loop != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) != 0) {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } /* end for */
+
+ pch_sendnack(adap);
+
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (length != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) == 0) {
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+
+ buf[read_index++] = ioread32(p + PCH_I2CDR);
+ count = read_index;
+ } else {
+ count = -ETIME;
+ }
+
+ }
+ } else {
+ count = -ETIME;
+ pch_stop(adap);
+ }
+
+ return count;
+}
+
+/**
+ * pch_cb_ch0() - Interrupt handler Call back function
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_cb_ch0(struct i2c_algo_pch_data *adap)
+{
+ u32 sts;
+ void __iomem *p = adap->pch_base_address;
+
+ sts = ioread32(p + PCH_I2CSR);
+ sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
+ if (I2CMAL_BIT & sts)
+ adap->pch_event_flag |= I2CMAL_EVENT;
+
+ if (I2CMCF_BIT & sts)
+ adap->pch_event_flag |= I2CMCF_EVENT;
+
+ /* clear the applicable bits */
+ pch_clrbit((adap->pch_base_address), PCH_I2CSR, sts);
+
+ pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
+
+ wake_up(&pch_event);
+}
+
+/**
+ * pch_handler() - interrupt handler for the PCH I2C controller
+ * @irq: irq number.
+ * @pData: cookie passed back to the handler function.
+ */
+static irqreturn_t pch_handler(int irq, void *pData)
+{
+ s32 reg_val;
+
+ struct i2c_algo_pch_data *adap_data = (struct i2c_algo_pch_data *)pData;
+ void __iomem *p = adap_data->pch_base_address;
+ u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE);
+
+ if (mode != NORMAL_MODE) {
+ pch_err(adap_data, "I2C mode is not supported\n");
+ return IRQ_NONE;
+ }
+
+ reg_val = ioread32(p + PCH_I2CSR);
+ if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
+ pch_cb_ch0(adap_data);
+ else
+ return IRQ_NONE;
+
+ return IRQ_HANDLED;
+}
+#if 0
+ if (mode == NORMAL_MODE) {
+ reg_val = ioread32(p + PCH_I2CSR);
+ if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
+ pch_cb_ch0(adap_data);
+ else
+ goto err_out;
+ } else {
+ pch_err(adap_data, "I2C mode is not supported\n");
+ goto err_out;
+ }
+ return IRQ_HANDLED;
+
+err_out:
+ return IRQ_NONE;
+}
+#endif
+/**
+ * pch_xfer() - Reading adnd writing data through I2C bus
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @num: number of messages.
+ */
+static s32 pch_xfer(struct i2c_adapter *i2c_adap,
+ struct i2c_msg *msgs, s32 num)
+{
+ struct i2c_msg *pmsg;
+ u32 i;
+ u32 status;
+ u32 msglen;
+ u32 subaddrlen;
+ s32 ret;
+
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ ret = mutex_lock_interruptible(&pch_mutex);
+ if (ret)
+ return -ERESTARTSYS;
+
+ if (adap->p_adapter_info->pch_suspended) {
+ mutex_unlock(&pch_mutex);
+ return -EBUSY;
+ }
+
+ pch_dbg(adap, "adap->p_adapter_info->pch_suspended is %d\n",
+ adap->p_adapter_info->pch_suspended);
+ /* transfer not completed */
+ adap->pch_xfer_in_progress = true;
+
+ pmsg = &msgs[0];
+ pmsg->flags |= adap->pch_buff_mode_en;
+ status = pmsg->flags;
+ pch_dbg(adap,
+ "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
+ /* calculate sub address length and message length */
+ /* these are applicable only for buffer mode */
+ subaddrlen = pmsg->buf[0];
+ /* calculate actual message length excluding
+ * the sub address fields */
+ msglen = (pmsg->len) - (subaddrlen + 1);
+ i = 0;
+ if (status & (I2C_M_RD)) {
+ pch_dbg(adap, "invoking pch_readbytes\n");
+ ret = pch_readbytes(i2c_adap, pmsg, (i + 1 == num),
+ (i == 0));
+ } else {
+ pch_dbg(adap, "invoking pch_writebytes\n");
+ ret = pch_writebytes(i2c_adap, pmsg, (i + 1 == num),
+ (i == 0));
+ }
+
+ adap->pch_xfer_in_progress = false; /* transfer completed */
+
+ mutex_unlock(&pch_mutex);
+
+ return ret;
+}
+
+/**
+ * pch_func() - return the functionality of the I2C driver
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static u32 pch_func(struct i2c_adapter *adap)
+{
+ u32 ret;
+ ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
+ return ret;
+}
+
+static struct i2c_algorithm pch_algorithm = {
+ .master_xfer = pch_xfer,
+ .functionality = pch_func
+};
+
+/**
+ * pch_disbl_int() - Disable PCH I2C interrupts
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_disbl_int(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL,
+ NORMAL_INTR_ENBL);
+
+ iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
+
+ iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
+}
+
+static int __devinit pch_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ void __iomem *base_addr;
+ s32 ret;
+ struct adapter_info *adap_info =
+ kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
+
+ pch_pci_dbg(pdev, "Entered.\n");
+
+ if (adap_info == NULL) {
+ pch_pci_err(pdev, "Memory allocation FAILED\n");
+ return -ENOMEM;
+ }
+
+ ret = pci_enable_device(pdev);
+ if (ret) {
+ pch_pci_err(pdev, "pci_enable_device FAILED\n");
+ goto err_pci_enable;
+ }
+
+ ret = pci_request_regions(pdev, KBUILD_MODNAME);
+ if (ret) {
+ pch_pci_err(pdev, "pci_request_regions FAILED\n");
+ goto err_pci_req;
+ }
+
+ base_addr = pci_iomap(pdev, 1, 0);
+
+ if (base_addr == 0) {
+ pch_pci_err(pdev, "pci_iomap FAILED\n");
+ ret = -ENOMEM;
+ goto err_pci_iomap;
+ }
+
+ adap_info->pch_suspended = false;
+
+ adap_info->pch_data.p_adapter_info = adap_info;
+
+ adap_info->pch_data.pch_adapter.owner = THIS_MODULE;
+ adap_info->pch_data.pch_adapter.class = I2C_CLASS_HWMON;
+ strcpy(adap_info->pch_data.pch_adapter.name, KBUILD_MODNAME);
+ adap_info->pch_data.pch_adapter.algo = &pch_algorithm;
+ adap_info->pch_data.pch_adapter.algo_data =
+ &adap_info->pch_data;
+
+ /* (i * 0x80) + base_addr; */
+ adap_info->pch_data.pch_base_address = base_addr;
+
+ adap_info->pch_data.pch_adapter.dev.parent = &pdev->dev;
+
+ ret = i2c_add_adapter(&(adap_info->pch_data.pch_adapter));
+
+ if (ret) {
+ pch_pci_err(pdev, "i2c_add_adapter FAILED\n");
+ goto err_i2c_add_adapter;
+ }
+
+ pch_init(&adap_info->pch_data);
+ ret = request_irq(pdev->irq, pch_handler, IRQF_SHARED,
+ KBUILD_MODNAME, &adap_info->pch_data);
+ if (ret) {
+ pch_pci_err(pdev, "request_irq FAILED\n");
+ goto err_request_irq;
+ }
+
+ pci_set_drvdata(pdev, adap_info);
+ pch_pci_dbg(pdev, "returns %d.\n", ret);
+ return 0;
+
+err_request_irq:
+ i2c_del_adapter(&(adap_info->pch_data.pch_adapter));
+err_i2c_add_adapter:
+ pci_iounmap(pdev, base_addr);
+err_pci_iomap:
+ pci_release_regions(pdev);
+err_pci_req:
+ pci_disable_device(pdev);
+err_pci_enable:
+ kfree(adap_info);
+ return ret;
+}
+
+static void __devexit pch_remove(struct pci_dev *pdev)
+{
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+
+
+ pch_disbl_int(&adap_info->pch_data);
+ free_irq(pdev->irq, &adap_info->pch_data);
+ i2c_del_adapter(&(adap_info->pch_data.pch_adapter));
+
+ if (adap_info->pch_data.pch_base_address) {
+ pci_iounmap(pdev, adap_info->pch_data.pch_base_address);
+ adap_info->pch_data.pch_base_address = 0;
+ }
+
+ pci_set_drvdata(pdev, NULL);
+
+ pci_release_regions(pdev);
+
+ pci_disable_device(pdev);
+ kfree(adap_info);
+}
+
+#ifdef CONFIG_PM
+static int pch_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ int ret;
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+ void __iomem *p = adap_info->pch_data.pch_base_address;
+
+ adap_info->pch_suspended = true;
+
+ while ((adap_info->pch_data.pch_xfer_in_progress)) {
+ /* Wait until all channel transfers are completed */
+ msleep(1);
+ }
+ /* Disable the i2c interrupts */
+ pch_disbl_int(&adap_info->pch_data);
+
+ pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
+ "invoked function pch_disbl_int successfully\n",
+ ioread32(p + 0x08), ioread32(p + 0x30), ioread32(p + 0x44));
+
+ ret = pci_save_state(pdev);
+
+ if (ret) {
+ pch_pci_err(pdev, "pci_save_state\n");
+ return ret;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+ pci_disable_device(pdev);
+ pci_set_power_state(pdev, pci_choose_state(pdev, state));
+
+ return 0;
+}
+
+static int pch_resume(struct pci_dev *pdev)
+{
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+
+ pci_set_power_state(pdev, PCI_D0);
+ pci_restore_state(pdev);
+
+ if (pci_enable_device(pdev) < 0) {
+ pch_pci_err(pdev, "pci_enable_device FAILED in pch_resume\n");
+ return -EIO;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+
+ pch_init(&adap_info->pch_data);
+
+ adap_info->pch_suspended = false;
+
+ return 0;
+}
+#else
+#define pch_suspend NULL
+#define pch_resume NULL
+#endif
+
+static struct pci_driver pch_pcidriver = {
+ .name = KBUILD_MODNAME,
+ .id_table = pch_pcidev_id,
+ .probe = pch_probe,
+ .remove = __devexit_p(pch_remove),
+ .suspend = pch_suspend,
+ .resume = pch_resume
+};
+
+static int __init pch_pci_init(void)
+{
+ return pci_register_driver(&pch_pcidriver);
+}
+
+static void __exit pch_pci_exit(void)
+{
+ pci_unregister_driver(&pch_pcidriver);
+}
+
+MODULE_DESCRIPTION("PCH I2C PCI Driver");
+MODULE_LICENSE("GPL");
+module_init(pch_pci_init);
+module_exit(pch_pci_exit);
+module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
+module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
--
1.6.0.6
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-06 1:31 ` Masayuki Ohtak
0 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtak @ 2010-09-06 1:31 UTC (permalink / raw)
To: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz
Cc: yong.y.wang-ral2JQCrhuEAvxtiuMwx3w,
qi.wang-ral2JQCrhuEAvxtiuMwx3w,
andrew.chih.howe.khor-ral2JQCrhuEAvxtiuMwx3w,
arjan-VuQAYsv1563Yd54FQh9/CA, Tomoya MORINAGA, Arnd Bergmann,
Masayuki Ohtake
Hi Alan and Wolfram Sang
Sorry, previous patch is invalid patch.
Please refer this patch.
Thanks, Ohtake (OKISemi)
---
I2C driver of Topcliff PCH
Topcliff PCH is the platform controller hub that is going to be used in
Intel's upcoming general embedded platform. All IO peripherals in
Topcliff PCH are actually devices sitting on AMBA bus.
Topcliff PCH has I2C I/F. Using this I/F, it is able to access system
devices connected to I2C.
Signed-off-by: Masayuki Ohtake <masa-korg-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>
Reviewed-by: Linus Walleij <linus.walleij-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>
---
drivers/i2c/busses/Kconfig | 8 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-pch.c | 923 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 932 insertions(+), 0 deletions(-)
create mode 100644 drivers/i2c/busses/i2c-pch.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index bceafbf..b7b132d 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -613,6 +613,14 @@ config I2C_XILINX
This driver can also be built as a module. If so, the module
will be called xilinx_i2c.
+config PCH_I2C
+ tristate "PCH I2C of Intel Topcliff"
+ depends on PCI
+ help
+ This driver is for PCH(Platform controller Hub) I2C of Topcliff which
+ is an IOH(Input/Output Hub) for x86 embedded processor.
+ This driver can access PCH I2C bus device.
+
comment "External I2C/SMBus adapter drivers"
config I2C_PARPORT
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 936880b..aa04135 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
+obj-$(CONFIG_PCH_I2C) += i2c-pch.o
# External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o
diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c
new file mode 100644
index 0000000..abaef96
--- /dev/null
+++ b/drivers/i2c/busses/i2c-pch.c
@@ -0,0 +1,923 @@
+/*
+ * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/pci.h>
+#include <linux/mutex.h>
+#include <linux/ktime.h>
+
+#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
+#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
+#define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
+#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
+#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
+
+#define PCH_I2CSADR 0x00 /* I2C slave address register */
+#define PCH_I2CCTL 0x04 /* I2C control register */
+#define PCH_I2CSR 0x08 /* I2C status register */
+#define PCH_I2CDR 0x0C /* I2C data register */
+#define PCH_I2CMON 0x10 /* I2C bus monitor register */
+#define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
+#define PCH_I2CMOD 0x18 /* I2C mode register */
+#define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
+#define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
+#define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
+#define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
+#define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
+#define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
+#define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
+#define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
+#define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
+#define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
+#define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
+#define PCH_I2CTMR 0x48 /* I2C timer register */
+#define PCH_I2CSRST 0xFC /* I2C reset register */
+#define PCH_I2CNF 0xF8 /* I2C noise filter register */
+
+#define BUS_IDLE_TIMEOUT 20
+#define PCH_I2CCTL_I2CMEN 0x0080
+#define TEN_BIT_ADDR_DEFAULT 0xF000
+#define TEN_BIT_ADDR_MASK 0xF0
+#define PCH_START 0x0020
+#define PCH_ESR_START 0x0001
+#define PCH_BUFF_START 0x1
+#define PCH_REPSTART 0x0004
+#define PCH_ACK 0x0008
+#define PCH_GETACK 0x0001
+#define CLR_REG 0x0
+#define I2C_RD 0x1
+#define I2CMCF_BIT 0x0080
+#define I2CMIF_BIT 0x0002
+#define I2CMAL_BIT 0x0010
+#define I2CBMFI_BIT 0x0001
+#define I2CBMAL_BIT 0x0002
+#define I2CBMNA_BIT 0x0004
+#define I2CBMTO_BIT 0x0008
+#define I2CBMIS_BIT 0x0010
+#define I2CESRFI_BIT 0X0001
+#define I2CESRTO_BIT 0x0002
+#define I2CESRFIIE_BIT 0x1
+#define I2CESRTOIE_BIT 0x2
+#define I2CBMDZ_BIT 0x0040
+#define I2CBMAG_BIT 0x0020
+#define I2CMBB_BIT 0x0020
+#define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
+ I2CBMTO_BIT | I2CBMIS_BIT)
+#define I2C_ADDR_MSK 0xFF
+#define I2C_MSB_2B_MSK 0x300
+#define FAST_MODE_CLK 400
+#define FAST_MODE_EN 0x0001
+#define SUB_ADDR_LEN_MAX 4
+#define BUF_LEN_MAX 32
+#define PCH_BUFFER_MODE 0x1
+#define EEPROM_SW_RST_MODE 0x0002
+#define NORMAL_INTR_ENBL 0x0300
+#define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
+#define EEPROM_RST_INTR_DISBL 0x0
+#define BUFFER_MODE_INTR_ENBL 0x001F
+#define BUFFER_MODE_INTR_DISBL 0x0
+#define NORMAL_MODE 0x0
+#define BUFFER_MODE 0x1
+#define EEPROM_SR_MODE 0x2
+#define I2C_TX_MODE 0x0010
+#define PCH_BUF_TX 0xFFF7
+#define PCH_BUF_RD 0x0008
+#define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
+ I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
+#define I2CMAL_EVENT 0x0001
+#define I2CMCF_EVENT 0x0002
+#define I2CBMFI_EVENT 0x0004
+#define I2CBMAL_EVENT 0x0008
+#define I2CBMNA_EVENT 0x0010
+#define I2CBMTO_EVENT 0x0020
+#define I2CBMIS_EVENT 0x0040
+#define I2CESRFI_EVENT 0x0080
+#define I2CESRTO_EVENT 0x0100
+#define PCI_DEVICE_ID_PCH_I2C 0x8817
+
+#define pch_dbg(adap, fmt, arg...) \
+ dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
+
+#define pch_err(adap, fmt, arg...) \
+ dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
+
+#define pch_pci_err(pdev, fmt, arg...) \
+ dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
+
+#define pch_pci_dbg(pdev, fmt, arg...) \
+ dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
+
+/**
+ * struct i2c_algo_pch_data - for I2C driver functionalities
+ * @p_adapter_info: stores the reference to adapter_info structure
+ * @pch_adapter: stores the reference to i2c_adapter structure
+ * @pch_base_address: specifies the remapped base address
+ * @pch_buff_mode_en: specifies if buffer mode is enabled
+ * @pch_event_flag: specifies occurrence of interrupt events
+ * @pch_xfer_in_progress: specifies whether the transfer is completed
+ */
+struct i2c_algo_pch_data {
+ struct adapter_info *p_adapter_info;
+ struct i2c_adapter pch_adapter;
+ void __iomem *pch_base_address;
+ int pch_buff_mode_en;
+ u32 pch_event_flag;
+ bool pch_xfer_in_progress;
+};
+
+/**
+ * struct adapter_info - This structure holds the adapter information for the
+ PCH i2c controller
+ * @pch_data: stores a list of i2c_algo_pch_data
+ * @pch_suspended: specifies whether the system is suspended or not
+ * perhaps with more lines and words.
+ *
+ * pch_data has as many elements as maximum I2C channels
+ */
+struct adapter_info {
+ struct i2c_algo_pch_data pch_data;
+ bool pch_suspended;
+};
+
+
+static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
+static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
+static wait_queue_head_t pch_event;
+static DEFINE_MUTEX(pch_mutex);
+
+static struct pci_device_id __devinitdata pch_pcidev_id[] = {
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_I2C)},
+ {0,}
+};
+
+static irqreturn_t pch_handler(int irq, void *pData);
+
+static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ u32 val;
+ val = ioread32(addr + offset);
+ val |= bitmask;
+ iowrite32(val, addr + offset);
+}
+
+static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ u32 val;
+ val = ioread32(addr + offset);
+ val &= (~bitmask);
+ iowrite32(val, addr + offset);
+}
+
+/**
+ * pch_init() - hardware initialization of I2C module
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_init(struct i2c_algo_pch_data *adap)
+{
+ u32 pch_i2cbc;
+ u32 pch_i2ctmr;
+ u32 reg_value;
+ void __iomem *p = adap->pch_base_address;
+
+ /* reset I2C controller */
+ iowrite32(0x01, p + PCH_I2CSRST);
+ iowrite32(0x0, p + PCH_I2CSRST);
+ /* Initialize I2C registers */
+ iowrite32(CLR_REG, p + PCH_I2CCTL);
+ iowrite32(CLR_REG, p + PCH_I2CMOD);
+ iowrite32(CLR_REG, p + PCH_I2CBUFFOR);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSLV);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSUB);
+ iowrite32(CLR_REG, p + PCH_I2CBUFMSK);
+ iowrite32(CLR_REG, p + PCH_I2CESRFOR);
+ iowrite32(CLR_REG, p + PCH_I2CESRMSK);
+ iowrite32(0x21, p + PCH_I2CNF);
+
+ reg_value = PCH_I2CCTL_I2CMEN;
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL,
+ PCH_I2CCTL_I2CMEN);
+
+ if (pch_i2c_speed != 400)
+ pch_i2c_speed = 100;
+
+ if (pch_i2c_speed == FAST_MODE_CLK) {
+ reg_value |= FAST_MODE_EN;
+ pch_dbg(adap, "Fast mode enabled\n");
+ }
+
+ if (pch_clk <= 0 || pch_clk > PCH_MAX_CLK)
+ pch_clk = 62500;
+
+ pch_i2cbc = ((pch_clk) + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
+ /* Set transfer speed in I2CBC */
+ iowrite32(pch_i2cbc, p + PCH_I2CBC);
+
+ pch_i2ctmr = (pch_clk) / 8;
+ iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
+
+ reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
+ iowrite32(reg_value, p + PCH_I2CCTL);
+
+ pch_dbg(adap,
+ "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
+ ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
+
+ init_waitqueue_head(&pch_event);
+}
+
+static inline int ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
+{
+ return cmp1.tv64 < cmp2.tv64;
+}
+
+/**
+ * pch_wait_for_bus_idle() - check the status of bus.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ * @timeout: waiting time counter (us).
+ */
+static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
+ s32 timeout)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ /* MAX timeout value is timeout*1000*1000nsec */
+ ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
+ do {
+ if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
+ break;
+ msleep(1);
+ } while (ktime_lt(ktime_get(), ns_val));
+
+ pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
+
+ if (timeout == 0) {
+ pch_err(adap, "return%d\n", -ETIME);
+ return -ETIME;
+ }
+
+ return 0;
+}
+
+/**
+ * pch_start() - Generate I2C start condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ *
+ * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
+ */
+static void pch_start(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+}
+
+/**
+ * pch_wait_for_xfer_complete() - initiates a wait for the tx complete event
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
+{
+ s32 ret;
+ ret = wait_event_timeout(pch_event,
+ (adap->pch_event_flag != 0), msecs_to_jiffies(50));
+ if (ret < 0) {
+ pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
+ return ret;
+ }
+
+ if (ret == 0) {
+ pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
+ return -ETIMEDOUT;
+ }
+
+ if (adap->pch_event_flag & I2C_ERROR_MASK) {
+ pch_err(adap, "error bits set: %x\n", adap->pch_event_flag);
+ return -EIO;
+ }
+
+ adap->pch_event_flag = 0;
+ ret = 0;
+
+ return ret;
+}
+
+/**
+ * pch_getack() - to confirm ACK/NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_getack(struct i2c_algo_pch_data *adap)
+{
+ u32 reg_val;
+ void __iomem *p = adap->pch_base_address;
+ reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
+
+ if (reg_val != 0) {
+ pch_err(adap, "return%d\n", -EPROTO);
+ return -EPROTO;
+ }
+
+ return 0;
+}
+
+/**
+ * pch_stop() - generate stop condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_stop(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ /* clear the start bit */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+}
+
+/**
+ * pch_repstart() - generate repeated start condition in normal mode
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_repstart(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_REPSTART);
+}
+
+/**
+ * pch_writebytes() - write data to I2C bus in normal mode
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @last: specifies whether last message or not.
+ * In the case of compound mode it will be 1 for last message,
+ * otherwise 0.
+ * @first: specifies whether first message or not.
+ * 1 for first message otherwise 0.
+ */
+static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+ u8 *buf;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ u32 addr_8_lsb;
+ s32 wrcount;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+ /* enable master tx */
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
+ length);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ addr_8_lsb = (addr & I2C_ADDR_MSK);
+ iowrite32(addr_8_lsb, p + PCH_I2CDR);
+ } else {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } else {
+ /* set 7 bit slave address and R/W bit as 0 */
+ iowrite32(addr << 1, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ }
+
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ for (wrcount = 0; wrcount < length; ++wrcount) {
+ /* write buffer value to I2C data register */
+ iowrite32(buf[wrcount], p + PCH_I2CDR);
+ pch_dbg(adap, "writing %x to Data register\n",
+ buf[wrcount]);
+
+ if (pch_wait_for_xfer_complete(adap) != 0)
+ return -ETIME;
+
+ if (pch_getack(adap))
+ return -ETIME;
+ }
+
+ /* check if this is the last message */
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+ } else {
+ pch_stop(adap);
+ return -EIO;
+ }
+
+ pch_dbg(adap, "return=%d\n", wrcount);
+
+ return wrcount;
+}
+
+/**
+ * pch_sendack() - send ACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+}
+
+/**
+ * pch_sendnack() - send NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendnack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+}
+
+/**
+ * pch_readbytes() - read data from I2C bus in normal mode.
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @last: specifies whether last message or not.
+ * @first: specifies whether first message or not.
+ */
+s32 pch_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ u8 *buf;
+ u32 count;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+
+ /* enable master reception */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+
+ } else {
+ /* 7 address bits + R/W bit */
+ addr = (((addr) << 1) | (I2C_RD));
+ iowrite32(addr, p + PCH_I2CDR);
+ }
+
+ /* check if it is the first message */
+ if (first)
+ pch_start(adap);
+
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ pch_dbg(adap, "return %d\n", 0);
+
+ if (length == 0) {
+ pch_stop(adap);
+ ioread32(p + PCH_I2CDR); /* Dummy read needs */
+
+ count = length;
+ } else {
+ int read_index;
+ int loop;
+ pch_sendack(adap);
+
+ /* Dummy read */
+ for (loop = 1, read_index = 0; loop < length; loop++) {
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (loop != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) != 0) {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } /* end for */
+
+ pch_sendnack(adap);
+
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (length != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) == 0) {
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+
+ buf[read_index++] = ioread32(p + PCH_I2CDR);
+ count = read_index;
+ } else {
+ count = -ETIME;
+ }
+
+ }
+ } else {
+ count = -ETIME;
+ pch_stop(adap);
+ }
+
+ return count;
+}
+
+/**
+ * pch_cb_ch0() - Interrupt handler Call back function
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_cb_ch0(struct i2c_algo_pch_data *adap)
+{
+ u32 sts;
+ void __iomem *p = adap->pch_base_address;
+
+ sts = ioread32(p + PCH_I2CSR);
+ sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
+ if (I2CMAL_BIT & sts)
+ adap->pch_event_flag |= I2CMAL_EVENT;
+
+ if (I2CMCF_BIT & sts)
+ adap->pch_event_flag |= I2CMCF_EVENT;
+
+ /* clear the applicable bits */
+ pch_clrbit((adap->pch_base_address), PCH_I2CSR, sts);
+
+ pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
+
+ wake_up(&pch_event);
+}
+
+/**
+ * pch_handler() - interrupt handler for the PCH I2C controller
+ * @irq: irq number.
+ * @pData: cookie passed back to the handler function.
+ */
+static irqreturn_t pch_handler(int irq, void *pData)
+{
+ s32 reg_val;
+
+ struct i2c_algo_pch_data *adap_data = (struct i2c_algo_pch_data *)pData;
+ void __iomem *p = adap_data->pch_base_address;
+ u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE);
+
+ if (mode != NORMAL_MODE) {
+ pch_err(adap_data, "I2C mode is not supported\n");
+ return IRQ_NONE;
+ }
+
+ reg_val = ioread32(p + PCH_I2CSR);
+ if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
+ pch_cb_ch0(adap_data);
+ else
+ return IRQ_NONE;
+
+ return IRQ_HANDLED;
+}
+#if 0
+ if (mode == NORMAL_MODE) {
+ reg_val = ioread32(p + PCH_I2CSR);
+ if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
+ pch_cb_ch0(adap_data);
+ else
+ goto err_out;
+ } else {
+ pch_err(adap_data, "I2C mode is not supported\n");
+ goto err_out;
+ }
+ return IRQ_HANDLED;
+
+err_out:
+ return IRQ_NONE;
+}
+#endif
+/**
+ * pch_xfer() - Reading adnd writing data through I2C bus
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @num: number of messages.
+ */
+static s32 pch_xfer(struct i2c_adapter *i2c_adap,
+ struct i2c_msg *msgs, s32 num)
+{
+ struct i2c_msg *pmsg;
+ u32 i;
+ u32 status;
+ u32 msglen;
+ u32 subaddrlen;
+ s32 ret;
+
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ ret = mutex_lock_interruptible(&pch_mutex);
+ if (ret)
+ return -ERESTARTSYS;
+
+ if (adap->p_adapter_info->pch_suspended) {
+ mutex_unlock(&pch_mutex);
+ return -EBUSY;
+ }
+
+ pch_dbg(adap, "adap->p_adapter_info->pch_suspended is %d\n",
+ adap->p_adapter_info->pch_suspended);
+ /* transfer not completed */
+ adap->pch_xfer_in_progress = true;
+
+ pmsg = &msgs[0];
+ pmsg->flags |= adap->pch_buff_mode_en;
+ status = pmsg->flags;
+ pch_dbg(adap,
+ "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
+ /* calculate sub address length and message length */
+ /* these are applicable only for buffer mode */
+ subaddrlen = pmsg->buf[0];
+ /* calculate actual message length excluding
+ * the sub address fields */
+ msglen = (pmsg->len) - (subaddrlen + 1);
+ i = 0;
+ if (status & (I2C_M_RD)) {
+ pch_dbg(adap, "invoking pch_readbytes\n");
+ ret = pch_readbytes(i2c_adap, pmsg, (i + 1 == num),
+ (i == 0));
+ } else {
+ pch_dbg(adap, "invoking pch_writebytes\n");
+ ret = pch_writebytes(i2c_adap, pmsg, (i + 1 == num),
+ (i == 0));
+ }
+
+ adap->pch_xfer_in_progress = false; /* transfer completed */
+
+ mutex_unlock(&pch_mutex);
+
+ return ret;
+}
+
+/**
+ * pch_func() - return the functionality of the I2C driver
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static u32 pch_func(struct i2c_adapter *adap)
+{
+ u32 ret;
+ ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
+ return ret;
+}
+
+static struct i2c_algorithm pch_algorithm = {
+ .master_xfer = pch_xfer,
+ .functionality = pch_func
+};
+
+/**
+ * pch_disbl_int() - Disable PCH I2C interrupts
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_disbl_int(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL,
+ NORMAL_INTR_ENBL);
+
+ iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
+
+ iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
+}
+
+static int __devinit pch_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ void __iomem *base_addr;
+ s32 ret;
+ struct adapter_info *adap_info =
+ kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
+
+ pch_pci_dbg(pdev, "Entered.\n");
+
+ if (adap_info == NULL) {
+ pch_pci_err(pdev, "Memory allocation FAILED\n");
+ return -ENOMEM;
+ }
+
+ ret = pci_enable_device(pdev);
+ if (ret) {
+ pch_pci_err(pdev, "pci_enable_device FAILED\n");
+ goto err_pci_enable;
+ }
+
+ ret = pci_request_regions(pdev, KBUILD_MODNAME);
+ if (ret) {
+ pch_pci_err(pdev, "pci_request_regions FAILED\n");
+ goto err_pci_req;
+ }
+
+ base_addr = pci_iomap(pdev, 1, 0);
+
+ if (base_addr == 0) {
+ pch_pci_err(pdev, "pci_iomap FAILED\n");
+ ret = -ENOMEM;
+ goto err_pci_iomap;
+ }
+
+ adap_info->pch_suspended = false;
+
+ adap_info->pch_data.p_adapter_info = adap_info;
+
+ adap_info->pch_data.pch_adapter.owner = THIS_MODULE;
+ adap_info->pch_data.pch_adapter.class = I2C_CLASS_HWMON;
+ strcpy(adap_info->pch_data.pch_adapter.name, KBUILD_MODNAME);
+ adap_info->pch_data.pch_adapter.algo = &pch_algorithm;
+ adap_info->pch_data.pch_adapter.algo_data =
+ &adap_info->pch_data;
+
+ /* (i * 0x80) + base_addr; */
+ adap_info->pch_data.pch_base_address = base_addr;
+
+ adap_info->pch_data.pch_adapter.dev.parent = &pdev->dev;
+
+ ret = i2c_add_adapter(&(adap_info->pch_data.pch_adapter));
+
+ if (ret) {
+ pch_pci_err(pdev, "i2c_add_adapter FAILED\n");
+ goto err_i2c_add_adapter;
+ }
+
+ pch_init(&adap_info->pch_data);
+ ret = request_irq(pdev->irq, pch_handler, IRQF_SHARED,
+ KBUILD_MODNAME, &adap_info->pch_data);
+ if (ret) {
+ pch_pci_err(pdev, "request_irq FAILED\n");
+ goto err_request_irq;
+ }
+
+ pci_set_drvdata(pdev, adap_info);
+ pch_pci_dbg(pdev, "returns %d.\n", ret);
+ return 0;
+
+err_request_irq:
+ i2c_del_adapter(&(adap_info->pch_data.pch_adapter));
+err_i2c_add_adapter:
+ pci_iounmap(pdev, base_addr);
+err_pci_iomap:
+ pci_release_regions(pdev);
+err_pci_req:
+ pci_disable_device(pdev);
+err_pci_enable:
+ kfree(adap_info);
+ return ret;
+}
+
+static void __devexit pch_remove(struct pci_dev *pdev)
+{
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+
+
+ pch_disbl_int(&adap_info->pch_data);
+ free_irq(pdev->irq, &adap_info->pch_data);
+ i2c_del_adapter(&(adap_info->pch_data.pch_adapter));
+
+ if (adap_info->pch_data.pch_base_address) {
+ pci_iounmap(pdev, adap_info->pch_data.pch_base_address);
+ adap_info->pch_data.pch_base_address = 0;
+ }
+
+ pci_set_drvdata(pdev, NULL);
+
+ pci_release_regions(pdev);
+
+ pci_disable_device(pdev);
+ kfree(adap_info);
+}
+
+#ifdef CONFIG_PM
+static int pch_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ int ret;
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+ void __iomem *p = adap_info->pch_data.pch_base_address;
+
+ adap_info->pch_suspended = true;
+
+ while ((adap_info->pch_data.pch_xfer_in_progress)) {
+ /* Wait until all channel transfers are completed */
+ msleep(1);
+ }
+ /* Disable the i2c interrupts */
+ pch_disbl_int(&adap_info->pch_data);
+
+ pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
+ "invoked function pch_disbl_int successfully\n",
+ ioread32(p + 0x08), ioread32(p + 0x30), ioread32(p + 0x44));
+
+ ret = pci_save_state(pdev);
+
+ if (ret) {
+ pch_pci_err(pdev, "pci_save_state\n");
+ return ret;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+ pci_disable_device(pdev);
+ pci_set_power_state(pdev, pci_choose_state(pdev, state));
+
+ return 0;
+}
+
+static int pch_resume(struct pci_dev *pdev)
+{
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+
+ pci_set_power_state(pdev, PCI_D0);
+ pci_restore_state(pdev);
+
+ if (pci_enable_device(pdev) < 0) {
+ pch_pci_err(pdev, "pci_enable_device FAILED in pch_resume\n");
+ return -EIO;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+
+ pch_init(&adap_info->pch_data);
+
+ adap_info->pch_suspended = false;
+
+ return 0;
+}
+#else
+#define pch_suspend NULL
+#define pch_resume NULL
+#endif
+
+static struct pci_driver pch_pcidriver = {
+ .name = KBUILD_MODNAME,
+ .id_table = pch_pcidev_id,
+ .probe = pch_probe,
+ .remove = __devexit_p(pch_remove),
+ .suspend = pch_suspend,
+ .resume = pch_resume
+};
+
+static int __init pch_pci_init(void)
+{
+ return pci_register_driver(&pch_pcidriver);
+}
+
+static void __exit pch_pci_exit(void)
+{
+ pci_unregister_driver(&pch_pcidriver);
+}
+
+MODULE_DESCRIPTION("PCH I2C PCI Driver");
+MODULE_LICENSE("GPL");
+module_init(pch_pci_init);
+module_exit(pch_pci_exit);
+module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
+module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
--
1.6.0.6
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-06 1:10 ` Masayuki Ohtak
0 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtak @ 2010-09-06 1:10 UTC (permalink / raw)
To: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c, linux-kernel, joe, Linus Walleij,
Wolfram Sang <w.sang@pengutronix.de>; Alan Cox
Cc: yong.y.wang, qi.wang, andrew.chih.howe.khor, arjan,
Tomoya MORINAGA, Arnd Bergmann, Masayuki Ohtake
Hi Alan and Wolfram Sang
We have updated for your indications.
Please confirm below.
Thanks, Ohtake (OKISemi)
---
I2C driver of Topcliff PCH
Topcliff PCH is the platform controller hub that is going to be used in
Intel's upcoming general embedded platform. All IO peripherals in
Topcliff PCH are actually devices sitting on AMBA bus.
Topcliff PCH has I2C I/F. Using this I/F, it is able to access system
devices connected to I2C.
Signed-off-by: Masayuki Ohtake <masa-korg@dsn.okisemi.com>
Reviewed-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Masayuki Ohtake <masa-korg@dsn.okisemi.com>
---
drivers/i2c/busses/Kconfig | 8 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-pch.c | 929 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 938 insertions(+), 0 deletions(-)
create mode 100644 drivers/i2c/busses/i2c-pch.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index bceafbf..b7b132d 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -613,6 +613,14 @@ config I2C_XILINX
This driver can also be built as a module. If so, the module
will be called xilinx_i2c.
+config PCH_I2C
+ tristate "PCH I2C of Intel Topcliff"
+ depends on PCI
+ help
+ This driver is for PCH(Platform controller Hub) I2C of Topcliff which
+ is an IOH(Input/Output Hub) for x86 embedded processor.
+ This driver can access PCH I2C bus device.
+
comment "External I2C/SMBus adapter drivers"
config I2C_PARPORT
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 936880b..aa04135 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
+obj-$(CONFIG_PCH_I2C) += i2c-pch.o
# External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o
diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c
new file mode 100644
index 0000000..749fcd2
--- /dev/null
+++ b/drivers/i2c/busses/i2c-pch.c
@@ -0,0 +1,929 @@
+/*
+ * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/pci.h>
+#include <linux/mutex.h>
+#include <linux/ktime.h>
+
+#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
+#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
+#define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
+#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
+#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
+
+#define PCH_I2CSADR 0x00 /* I2C slave address register */
+#define PCH_I2CCTL 0x04 /* I2C control register */
+#define PCH_I2CSR 0x08 /* I2C status register */
+#define PCH_I2CDR 0x0C /* I2C data register */
+#define PCH_I2CMON 0x10 /* I2C bus monitor register */
+#define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
+#define PCH_I2CMOD 0x18 /* I2C mode register */
+#define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
+#define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
+#define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
+#define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
+#define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
+#define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
+#define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
+#define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
+#define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
+#define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
+#define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
+#define PCH_I2CTMR 0x48 /* I2C timer register */
+#define PCH_I2CSRST 0xFC /* I2C reset register */
+#define PCH_I2CNF 0xF8 /* I2C noise filter register */
+
+#define BUS_IDLE_TIMEOUT 20
+#define PCH_I2CCTL_I2CMEN 0x0080
+#define TEN_BIT_ADDR_DEFAULT 0xF000
+#define TEN_BIT_ADDR_MASK 0xF0
+#define PCH_START 0x0020
+#define PCH_ESR_START 0x0001
+#define PCH_BUFF_START 0x1
+#define PCH_REPSTART 0x0004
+#define PCH_ACK 0x0008
+#define PCH_GETACK 0x0001
+#define CLR_REG 0x0
+#define I2C_RD 0x1
+#define I2CMCF_BIT 0x0080
+#define I2CMIF_BIT 0x0002
+#define I2CMAL_BIT 0x0010
+#define I2CBMFI_BIT 0x0001
+#define I2CBMAL_BIT 0x0002
+#define I2CBMNA_BIT 0x0004
+#define I2CBMTO_BIT 0x0008
+#define I2CBMIS_BIT 0x0010
+#define I2CESRFI_BIT 0X0001
+#define I2CESRTO_BIT 0x0002
+#define I2CESRFIIE_BIT 0x1
+#define I2CESRTOIE_BIT 0x2
+#define I2CBMDZ_BIT 0x0040
+#define I2CBMAG_BIT 0x0020
+#define I2CMBB_BIT 0x0020
+#define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
+ I2CBMTO_BIT | I2CBMIS_BIT)
+#define I2C_ADDR_MSK 0xFF
+#define I2C_MSB_2B_MSK 0x300
+#define FAST_MODE_CLK 400
+#define FAST_MODE_EN 0x0001
+#define SUB_ADDR_LEN_MAX 4
+#define BUF_LEN_MAX 32
+#define PCH_BUFFER_MODE 0x1
+#define EEPROM_SW_RST_MODE 0x0002
+#define NORMAL_INTR_ENBL 0x0300
+#define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
+#define EEPROM_RST_INTR_DISBL 0x0
+#define BUFFER_MODE_INTR_ENBL 0x001F
+#define BUFFER_MODE_INTR_DISBL 0x0
+#define NORMAL_MODE 0x0
+#define BUFFER_MODE 0x1
+#define EEPROM_SR_MODE 0x2
+#define I2C_TX_MODE 0x0010
+#define PCH_BUF_TX 0xFFF7
+#define PCH_BUF_RD 0x0008
+#define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
+ I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
+#define I2CMAL_EVENT 0x0001
+#define I2CMCF_EVENT 0x0002
+#define I2CBMFI_EVENT 0x0004
+#define I2CBMAL_EVENT 0x0008
+#define I2CBMNA_EVENT 0x0010
+#define I2CBMTO_EVENT 0x0020
+#define I2CBMIS_EVENT 0x0040
+#define I2CESRFI_EVENT 0x0080
+#define I2CESRTO_EVENT 0x0100
+#define PCI_DEVICE_ID_PCH_I2C 0x8817
+
+#define pch_dbg(adap, fmt, arg...) \
+ dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
+
+#define pch_err(adap, fmt, arg...) \
+ dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
+
+#define pch_pci_err(pdev, fmt, arg...) \
+ dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
+
+#define pch_pci_dbg(pdev, fmt, arg...) \
+ dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
+
+/**
+ * struct i2c_algo_pch_data - for I2C driver functionalities
+ * @p_adapter_info: stores the reference to adapter_info structure
+ * @pch_adapter: stores the reference to i2c_adapter structure
+ * @pch_base_address: specifies the remapped base address
+ * @pch_buff_mode_en: specifies if buffer mode is enabled
+ * @pch_event_flag: specifies occurrence of interrupt events
+ * @pch_xfer_in_progress: specifies whether the transfer is completed
+ */
+struct i2c_algo_pch_data {
+ struct adapter_info *p_adapter_info;
+ struct i2c_adapter pch_adapter;
+ void __iomem *pch_base_address;
+ int pch_buff_mode_en;
+ u32 pch_event_flag;
+ bool pch_xfer_in_progress;
+};
+
+/**
+ * struct adapter_info - This structure holds the adapter information for the
+ PCH i2c controller
+ * @pch_data: stores a list of i2c_algo_pch_data
+ * @pch_suspended: specifies whether the system is suspended or not
+ * perhaps with more lines and words.
+ *
+ * pch_data has as many elements as maximum I2C channels
+ */
+struct adapter_info {
+ struct i2c_algo_pch_data pch_data;
+ bool pch_suspended;
+};
+
+
+static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
+static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
+static wait_queue_head_t pch_event;
+static DEFINE_MUTEX(pch_mutex);
+
+static struct pci_device_id __devinitdata pch_pcidev_id[] = {
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_I2C)},
+ {0,}
+};
+
+static irqreturn_t pch_handler(int irq, void *pData);
+
+static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ u32 val;
+ val = ioread32(addr + offset);
+ val |= bitmask;
+ iowrite32(val, addr + offset);
+}
+
+static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ u32 val;
+ val = ioread32(addr + offset);
+ val &= (~bitmask);
+ iowrite32(val, addr + offset);
+}
+
+/**
+ * pch_init() - hardware initialization of I2C module
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_init(struct i2c_algo_pch_data *adap)
+{
+ u32 pch_i2cbc;
+ u32 pch_i2ctmr;
+ u32 reg_value;
+ void __iomem *p = adap->pch_base_address;
+
+ /* reset I2C controller */
+ iowrite32(0x01, p + PCH_I2CSRST);
+ iowrite32(0x0, p + PCH_I2CSRST);
+ /* Initialize I2C registers */
+ iowrite32(CLR_REG, p + PCH_I2CCTL);
+ iowrite32(CLR_REG, p + PCH_I2CMOD);
+ iowrite32(CLR_REG, p + PCH_I2CBUFFOR);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSLV);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSUB);
+ iowrite32(CLR_REG, p + PCH_I2CBUFMSK);
+ iowrite32(CLR_REG, p + PCH_I2CESRFOR);
+ iowrite32(CLR_REG, p + PCH_I2CESRMSK);
+ iowrite32(0x21, p + PCH_I2CNF);
+
+ reg_value = PCH_I2CCTL_I2CMEN;
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL,
+ PCH_I2CCTL_I2CMEN);
+
+ if (pch_i2c_speed != 400)
+ pch_i2c_speed = 100;
+
+ if (pch_i2c_speed == FAST_MODE_CLK) {
+ reg_value |= FAST_MODE_EN;
+ pch_dbg(adap, "Fast mode enabled\n");
+ }
+
+ if (pch_clk <= 0 || pch_clk > PCH_MAX_CLK)
+ pch_clk = 62500;
+
+ pch_i2cbc = ((pch_clk) + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
+ /* Set transfer speed in I2CBC */
+ iowrite32(pch_i2cbc, p + PCH_I2CBC);
+
+ pch_i2ctmr = (pch_clk) / 8;
+ iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
+
+ reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
+ iowrite32(reg_value, p + PCH_I2CCTL);
+
+ pch_dbg(adap,
+ "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
+ ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
+
+ init_waitqueue_head(&pch_event);
+}
+
+static inline int ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
+{
+ return cmp1.tv64 < cmp2.tv64;
+}
+
+/**
+ * pch_wait_for_bus_idle() - check the status of bus.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ * @timeout: waiting time counter (us).
+ */
+static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
+ s32 timeout)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ /* MAX timeout value is timeout*1000*1000nsec */
+ ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
+ do {
+ if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
+ break;
+ msleep(1);
+ } while (ktime_lt(ktime_get(), ns_val));
+
+ pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
+
+ if (timeout == 0) {
+ pch_err(adap, "return%d\n", -ETIME);
+ return -ETIME;
+ }
+
+ return 0;
+}
+
+/**
+ * pch_start() - Generate I2C start condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ *
+ * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
+ */
+static void pch_start(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+}
+
+/**
+ * pch_wait_for_xfer_complete() - initiates a wait for the tx complete event
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
+{
+ s32 ret;
+ ret = wait_event_timeout(pch_event,
+ (adap->pch_event_flag != 0), msecs_to_jiffies(50));
+ if (ret < 0) {
+ pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
+ return ret;
+ }
+
+ if (ret == 0) {
+ pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
+ return -ETIMEDOUT;
+ }
+
+ if (adap->pch_event_flag & I2C_ERROR_MASK) {
+ pch_err(adap, "error bits set: %x\n", adap->pch_event_flag);
+ return -EIO;
+ }
+
+ adap->pch_event_flag = 0;
+ ret = 0;
+
+ return ret;
+}
+
+/**
+ * pch_getack() - to confirm ACK/NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_getack(struct i2c_algo_pch_data *adap)
+{
+ u32 reg_val;
+ void __iomem *p = adap->pch_base_address;
+ reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
+
+ if (reg_val != 0) {
+ pch_err(adap, "return%d\n", -EPROTO);
+ return -EPROTO;
+ }
+
+ return 0;
+}
+
+/**
+ * pch_stop() - generate stop condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_stop(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ /* clear the start bit */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+}
+
+/**
+ * pch_repstart() - generate repeated start condition in normal mode
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_repstart(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_REPSTART);
+}
+
+/**
+ * pch_writebytes() - write data to I2C bus in normal mode
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @last: specifies whether last message or not.
+ * In the case of compound mode it will be 1 for last message,
+ * otherwise 0.
+ * @first: specifies whether first message or not.
+ * 1 for first message otherwise 0.
+ */
+static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+ u8 *buf;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ u32 addr_8_lsb;
+ s32 wrcount;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+ /* enable master tx */
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
+ length);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ addr_8_lsb = (addr & I2C_ADDR_MSK);
+ iowrite32(addr_8_lsb, p + PCH_I2CDR);
+ } else {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } else {
+ /* set 7 bit slave address and R/W bit as 0 */
+ iowrite32(addr << 1, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ }
+
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ for (wrcount = 0; wrcount < length; ++wrcount) {
+ /* write buffer value to I2C data register */
+ iowrite32(buf[wrcount], p + PCH_I2CDR);
+ pch_dbg(adap, "writing %x to Data register\n",
+ buf[wrcount]);
+
+ if (pch_wait_for_xfer_complete(adap) != 0)
+ return -ETIME;
+
+ if (pch_getack(adap))
+ return -ETIME;
+ }
+
+ /* check if this is the last message */
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+ } else {
+ pch_stop(adap);
+ return -EIO;
+ }
+
+ pch_dbg(adap, "return=%d\n", wrcount);
+
+ return wrcount;
+}
+
+/**
+ * pch_sendack() - send ACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+}
+
+/**
+ * pch_sendnack() - send NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendnack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+}
+
+/**
+ * pch_readbytes() - read data from I2C bus in normal mode.
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @last: specifies whether last message or not.
+ * @first: specifies whether first message or not.
+ */
+s32 pch_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ u8 *buf;
+ u32 count;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+
+ /* enable master reception */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+
+ } else {
+ /* 7 address bits + R/W bit */
+ addr = (((addr) << 1) | (I2C_RD));
+ iowrite32(addr, p + PCH_I2CDR);
+ }
+
+ /* check if it is the first message */
+ if (first)
+ pch_start(adap);
+
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ pch_dbg(adap, "return %d\n", 0);
+
+ if (length == 0) {
+ pch_stop(adap);
+ ioread32(p + PCH_I2CDR); /* Dummy read needs */
+
+ count = length;
+ } else {
+ int read_index;
+ int loop;
+ pch_sendack(adap);
+
+ /* Dummy read */
+ for (loop = 1, read_index = 0; loop < length; loop++) {
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (loop != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) != 0) {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } /* end for */
+
+ pch_sendnack(adap);
+
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (length != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) == 0) {
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+
+ buf[read_index++] = ioread32(p + PCH_I2CDR);
+ count = read_index;
+ } else {
+ count = -ETIME;
+ }
+
+ }
+ } else {
+ count = -ETIME;
+ pch_stop(adap);
+ }
+
+ return count;
+}
+
+/**
+ * pch_cb_ch0() - Interrupt handler Call back function
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_cb_ch0(struct i2c_algo_pch_data *adap)
+{
+ u32 sts;
+ void __iomem *p = adap->pch_base_address;
+
+ sts = ioread32(p + PCH_I2CSR);
+ sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
+ if (I2CMAL_BIT & sts)
+ adap->pch_event_flag |= I2CMAL_EVENT;
+
+ if (I2CMCF_BIT & sts)
+ adap->pch_event_flag |= I2CMCF_EVENT;
+
+ /* clear the applicable bits */
+ pch_clrbit((adap->pch_base_address), PCH_I2CSR, sts);
+
+ pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
+
+ wake_up(&pch_event);
+}
+
+/**
+ * pch_handler() - interrupt handler for the PCH I2C controller
+ * @irq: irq number.
+ * @pData: cookie passed back to the handler function.
+ */
+static irqreturn_t pch_handler(int irq, void *pData)
+{
+ s32 reg_val;
+
+ struct i2c_algo_pch_data *adap_data = (struct i2c_algo_pch_data *)pData;
+ void __iomem *p = adap_data->pch_base_address;
+ u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE);
+
+ if (mode != NORMAL_MODE) {
+ pch_err(adap_data, "I2C mode is not supported\n");
+ return IRQ_NONE;
+ }
+
+ reg_val = ioread32(p + PCH_I2CSR);
+ if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
+ pch_cb_ch0(adap_data);
+ else
+ return IRQ_NONE;
+
+ return IRQ_HANDLED;
+}
+#if 0
+ if (mode == NORMAL_MODE) {
+ reg_val = ioread32(p + PCH_I2CSR);
+ if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
+ pch_cb_ch0(adap_data);
+ else
+ goto err_out;
+ } else {
+ pch_err(adap_data, "I2C mode is not supported\n");
+ goto err_out;
+ }
+ return IRQ_HANDLED;
+
+err_out:
+ return IRQ_NONE;
+}
+#endif
+/**
+ * pch_xfer() - Reading adnd writing data through I2C bus
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @num: number of messages.
+ */
+static s32 pch_xfer(struct i2c_adapter *i2c_adap,
+ struct i2c_msg *msgs, s32 num)
+{
+ struct i2c_msg *pmsg;
+ u32 i;
+ u32 status;
+ u32 msglen;
+ u32 subaddrlen;
+ s32 ret;
+
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ ret = mutex_lock_interruptible(&pch_mutex);
+ if (ret)
+ return -ERESTARTSYS;
+
+ if (adap->p_adapter_info->pch_suspended) {
+ mutex_unlock(&pch_mutex);
+ return -EBUSY;
+ }
+
+ pch_dbg(adap, "adap->p_adapter_info->pch_suspended is %d\n",
+ adap->p_adapter_info->pch_suspended);
+ /* transfer not completed */
+ adap->pch_xfer_in_progress = true;
+
+ pmsg = &msgs[0];
+ pmsg->flags |= adap->pch_buff_mode_en;
+ status = pmsg->flags;
+ pch_dbg(adap,
+ "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
+ /* calculate sub address length and message length */
+ /* these are applicable only for buffer mode */
+ subaddrlen = pmsg->buf[0];
+ /* calculate actual message length excluding
+ * the sub address fields */
+ msglen = (pmsg->len) - (subaddrlen + 1);
+ i = 0;
+ if (status & (I2C_M_RD)) {
+ pch_dbg(adap, "invoking pch_readbytes\n");
+ ret = pch_readbytes(i2c_adap, pmsg, (i + 1 == num),
+ (i == 0));
+ } else {
+ pch_dbg(adap, "invoking pch_writebytes\n");
+ ret = pch_writebytes(i2c_adap, pmsg, (i + 1 == num),
+ (i == 0));
+ }
+
+ adap->pch_xfer_in_progress = false; /* transfer completed */
+
+ mutex_unlock(&pch_mutex);
+
+ return ret;
+}
+
+/**
+ * pch_func() - return the functionality of the I2C driver
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static u32 pch_func(struct i2c_adapter *adap)
+{
+ u32 ret;
+ ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
+ return ret;
+}
+
+static struct i2c_algorithm pch_algorithm = {
+ .master_xfer = pch_xfer,
+ .functionality = pch_func
+};
+
+/**
+ * pch_disbl_int() - Disable PCH I2C interrupts
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_disbl_int(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL,
+ NORMAL_INTR_ENBL);
+
+ iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
+
+ iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
+}
+
+static int __devinit pch_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ int i;
+ void __iomem *base_addr;
+ s32 ret;
+ struct adapter_info *adap_info =
+ kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
+
+ pch_pci_dbg(pdev, "Entered.\n");
+
+ if (adap_info == NULL) {
+ pch_pci_err(pdev, "Memory allocation FAILED\n");
+ return -ENOMEM;
+ }
+
+ ret = pci_enable_device(pdev);
+ if (ret) {
+ pch_pci_err(pdev, "pci_enable_device FAILED\n");
+ goto err_pci_enable;
+ }
+
+ ret = pci_request_regions(pdev, KBUILD_MODNAME);
+ if (ret) {
+ pch_pci_err(pdev, "pci_request_regions FAILED\n");
+ goto err_pci_req;
+ }
+
+ base_addr = pci_iomap(pdev, 1, 0);
+
+ if (base_addr == 0) {
+ pch_pci_err(pdev, "pci_iomap FAILED\n");
+ ret = -ENOMEM;
+ goto err_pci_iomap;
+ }
+
+ adap_info->pch_suspended = false;
+
+ adap_info->pch_data.p_adapter_info = adap_info;
+
+ adap_info->pch_data.pch_adapter.owner = THIS_MODULE;
+ adap_info->pch_data.pch_adapter.class = I2C_CLASS_HWMON;
+ strcpy(adap_info->pch_data.pch_adapter.name, KBUILD_MODNAME);
+ adap_info->pch_data.pch_adapter.algo = &pch_algorithm;
+ adap_info->pch_data.pch_adapter.algo_data =
+ &adap_info->pch_data;
+
+ /* (i * 0x80) + base_addr; */
+ adap_info->pch_data.pch_base_address = base_addr;
+
+ adap_info->pch_data.pch_adapter.dev.parent = &pdev->dev;
+
+ ret = i2c_add_adapter(&(adap_info->pch_data.pch_adapter));
+
+ if (ret) {
+ pch_pci_err(pdev, "i2c_add_adapter FAILED\n");
+ goto err_i2c_add_adapter;
+ }
+
+ pch_init(&adap_info->pch_data);
+ ret = request_irq(pdev->irq, pch_handler, IRQF_SHARED,
+ KBUILD_MODNAME, &adap_info->pch_data);
+ if (ret) {
+ pch_pci_err(pdev, "request_irq FAILED\n");
+ goto err_request_irq;
+ }
+
+ pci_set_drvdata(pdev, adap_info);
+ pch_pci_dbg(pdev, "returns %d.\n", ret);
+ return 0;
+
+err_request_irq:
+ i2c_del_adapter(&(adap_info->pch_data.pch_adapter));
+err_i2c_add_adapter:
+ pci_iounmap(pdev, base_addr);
+err_pci_iomap:
+ pci_release_regions(pdev);
+err_pci_req:
+ pci_disable_device(pdev);
+err_pci_enable:
+ kfree(adap_info);
+ return ret;
+}
+
+static void __devexit pch_remove(struct pci_dev *pdev)
+{
+ int i;
+
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+
+
+ pch_disbl_int(&adap_info->pch_data);
+ free_irq(pdev->irq, &adap_info->pch_data);
+ i2c_del_adapter(&(adap_info->pch_data.pch_adapter));
+
+ if (adap_info->pch_data.pch_base_address) {
+ pci_iounmap(pdev, adap_info->pch_data.pch_base_address);
+ adap_info->pch_data.pch_base_address = 0;
+ }
+
+ pci_set_drvdata(pdev, NULL);
+
+ pci_release_regions(pdev);
+
+ pci_disable_device(pdev);
+ kfree(adap_info);
+}
+
+#ifdef CONFIG_PM
+static int pch_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ int i;
+ int ret;
+
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+ void __iomem *p = adap_info->pch_data.pch_base_address;
+
+ adap_info->pch_suspended = true;
+
+ while ((adap_info->pch_data.pch_xfer_in_progress)) {
+ /* Wait until all channel transfers are completed */
+ msleep(1);
+ }
+ /* Disable the i2c interrupts */
+ pch_disbl_int(&adap_info->pch_data);
+
+ pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
+ "invoked function pch_disbl_int successfully\n",
+ ioread32(p + 0x08), ioread32(p + 0x30), ioread32(p + 0x44));
+
+ ret = pci_save_state(pdev);
+
+ if (ret) {
+ pch_pci_err(pdev, "pci_save_state\n");
+ return ret;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+ pci_disable_device(pdev);
+ pci_set_power_state(pdev, pci_choose_state(pdev, state));
+
+ return 0;
+}
+
+static int pch_resume(struct pci_dev *pdev)
+{
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+ int i;
+
+ pci_set_power_state(pdev, PCI_D0);
+ pci_restore_state(pdev);
+
+ if (pci_enable_device(pdev) < 0) {
+ pch_pci_err(pdev, "pci_enable_device FAILED in pch_resume\n");
+ return -EIO;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+
+ pch_init(&adap_info->pch_data);
+
+ adap_info->pch_suspended = false;
+
+ return 0;
+}
+#else
+#define pch_suspend NULL
+#define pch_resume NULL
+#endif
+
+static struct pci_driver pch_pcidriver = {
+ .name = KBUILD_MODNAME,
+ .id_table = pch_pcidev_id,
+ .probe = pch_probe,
+ .remove = __devexit_p(pch_remove),
+ .suspend = pch_suspend,
+ .resume = pch_resume
+};
+
+static int __init pch_pci_init(void)
+{
+ return pci_register_driver(&pch_pcidriver);
+}
+
+static void __exit pch_pci_exit(void)
+{
+ pci_unregister_driver(&pch_pcidriver);
+}
+
+MODULE_DESCRIPTION("PCH I2C PCI Driver");
+MODULE_LICENSE("GPL");
+module_init(pch_pci_init);
+module_exit(pch_pci_exit);
+module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
+module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
--
1.6.0.6
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-06 1:10 ` Masayuki Ohtak
0 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtak @ 2010-09-06 1:10 UTC (permalink / raw)
To: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz
Cc: yong.y.wang-ral2JQCrhuEAvxtiuMwx3w,
qi.wang-ral2JQCrhuEAvxtiuMwx3w,
andrew.chih.howe.khor-ral2JQCrhuEAvxtiuMwx3w,
arjan-VuQAYsv1563Yd54FQh9/CA, Tomoya MORINAGA, Arnd Bergmann,
Masayuki Ohtake
Hi Alan and Wolfram Sang
We have updated for your indications.
Please confirm below.
Thanks, Ohtake (OKISemi)
---
I2C driver of Topcliff PCH
Topcliff PCH is the platform controller hub that is going to be used in
Intel's upcoming general embedded platform. All IO peripherals in
Topcliff PCH are actually devices sitting on AMBA bus.
Topcliff PCH has I2C I/F. Using this I/F, it is able to access system
devices connected to I2C.
Signed-off-by: Masayuki Ohtake <masa-korg-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>
Reviewed-by: Linus Walleij <linus.walleij-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>
Signed-off-by: Masayuki Ohtake <masa-korg-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>
---
drivers/i2c/busses/Kconfig | 8 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-pch.c | 929 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 938 insertions(+), 0 deletions(-)
create mode 100644 drivers/i2c/busses/i2c-pch.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index bceafbf..b7b132d 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -613,6 +613,14 @@ config I2C_XILINX
This driver can also be built as a module. If so, the module
will be called xilinx_i2c.
+config PCH_I2C
+ tristate "PCH I2C of Intel Topcliff"
+ depends on PCI
+ help
+ This driver is for PCH(Platform controller Hub) I2C of Topcliff which
+ is an IOH(Input/Output Hub) for x86 embedded processor.
+ This driver can access PCH I2C bus device.
+
comment "External I2C/SMBus adapter drivers"
config I2C_PARPORT
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 936880b..aa04135 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
+obj-$(CONFIG_PCH_I2C) += i2c-pch.o
# External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o
diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c
new file mode 100644
index 0000000..749fcd2
--- /dev/null
+++ b/drivers/i2c/busses/i2c-pch.c
@@ -0,0 +1,929 @@
+/*
+ * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/pci.h>
+#include <linux/mutex.h>
+#include <linux/ktime.h>
+
+#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
+#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
+#define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
+#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
+#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
+
+#define PCH_I2CSADR 0x00 /* I2C slave address register */
+#define PCH_I2CCTL 0x04 /* I2C control register */
+#define PCH_I2CSR 0x08 /* I2C status register */
+#define PCH_I2CDR 0x0C /* I2C data register */
+#define PCH_I2CMON 0x10 /* I2C bus monitor register */
+#define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
+#define PCH_I2CMOD 0x18 /* I2C mode register */
+#define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
+#define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
+#define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
+#define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
+#define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
+#define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
+#define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
+#define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
+#define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
+#define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
+#define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
+#define PCH_I2CTMR 0x48 /* I2C timer register */
+#define PCH_I2CSRST 0xFC /* I2C reset register */
+#define PCH_I2CNF 0xF8 /* I2C noise filter register */
+
+#define BUS_IDLE_TIMEOUT 20
+#define PCH_I2CCTL_I2CMEN 0x0080
+#define TEN_BIT_ADDR_DEFAULT 0xF000
+#define TEN_BIT_ADDR_MASK 0xF0
+#define PCH_START 0x0020
+#define PCH_ESR_START 0x0001
+#define PCH_BUFF_START 0x1
+#define PCH_REPSTART 0x0004
+#define PCH_ACK 0x0008
+#define PCH_GETACK 0x0001
+#define CLR_REG 0x0
+#define I2C_RD 0x1
+#define I2CMCF_BIT 0x0080
+#define I2CMIF_BIT 0x0002
+#define I2CMAL_BIT 0x0010
+#define I2CBMFI_BIT 0x0001
+#define I2CBMAL_BIT 0x0002
+#define I2CBMNA_BIT 0x0004
+#define I2CBMTO_BIT 0x0008
+#define I2CBMIS_BIT 0x0010
+#define I2CESRFI_BIT 0X0001
+#define I2CESRTO_BIT 0x0002
+#define I2CESRFIIE_BIT 0x1
+#define I2CESRTOIE_BIT 0x2
+#define I2CBMDZ_BIT 0x0040
+#define I2CBMAG_BIT 0x0020
+#define I2CMBB_BIT 0x0020
+#define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
+ I2CBMTO_BIT | I2CBMIS_BIT)
+#define I2C_ADDR_MSK 0xFF
+#define I2C_MSB_2B_MSK 0x300
+#define FAST_MODE_CLK 400
+#define FAST_MODE_EN 0x0001
+#define SUB_ADDR_LEN_MAX 4
+#define BUF_LEN_MAX 32
+#define PCH_BUFFER_MODE 0x1
+#define EEPROM_SW_RST_MODE 0x0002
+#define NORMAL_INTR_ENBL 0x0300
+#define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
+#define EEPROM_RST_INTR_DISBL 0x0
+#define BUFFER_MODE_INTR_ENBL 0x001F
+#define BUFFER_MODE_INTR_DISBL 0x0
+#define NORMAL_MODE 0x0
+#define BUFFER_MODE 0x1
+#define EEPROM_SR_MODE 0x2
+#define I2C_TX_MODE 0x0010
+#define PCH_BUF_TX 0xFFF7
+#define PCH_BUF_RD 0x0008
+#define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
+ I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
+#define I2CMAL_EVENT 0x0001
+#define I2CMCF_EVENT 0x0002
+#define I2CBMFI_EVENT 0x0004
+#define I2CBMAL_EVENT 0x0008
+#define I2CBMNA_EVENT 0x0010
+#define I2CBMTO_EVENT 0x0020
+#define I2CBMIS_EVENT 0x0040
+#define I2CESRFI_EVENT 0x0080
+#define I2CESRTO_EVENT 0x0100
+#define PCI_DEVICE_ID_PCH_I2C 0x8817
+
+#define pch_dbg(adap, fmt, arg...) \
+ dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
+
+#define pch_err(adap, fmt, arg...) \
+ dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
+
+#define pch_pci_err(pdev, fmt, arg...) \
+ dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
+
+#define pch_pci_dbg(pdev, fmt, arg...) \
+ dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
+
+/**
+ * struct i2c_algo_pch_data - for I2C driver functionalities
+ * @p_adapter_info: stores the reference to adapter_info structure
+ * @pch_adapter: stores the reference to i2c_adapter structure
+ * @pch_base_address: specifies the remapped base address
+ * @pch_buff_mode_en: specifies if buffer mode is enabled
+ * @pch_event_flag: specifies occurrence of interrupt events
+ * @pch_xfer_in_progress: specifies whether the transfer is completed
+ */
+struct i2c_algo_pch_data {
+ struct adapter_info *p_adapter_info;
+ struct i2c_adapter pch_adapter;
+ void __iomem *pch_base_address;
+ int pch_buff_mode_en;
+ u32 pch_event_flag;
+ bool pch_xfer_in_progress;
+};
+
+/**
+ * struct adapter_info - This structure holds the adapter information for the
+ PCH i2c controller
+ * @pch_data: stores a list of i2c_algo_pch_data
+ * @pch_suspended: specifies whether the system is suspended or not
+ * perhaps with more lines and words.
+ *
+ * pch_data has as many elements as maximum I2C channels
+ */
+struct adapter_info {
+ struct i2c_algo_pch_data pch_data;
+ bool pch_suspended;
+};
+
+
+static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
+static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
+static wait_queue_head_t pch_event;
+static DEFINE_MUTEX(pch_mutex);
+
+static struct pci_device_id __devinitdata pch_pcidev_id[] = {
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_I2C)},
+ {0,}
+};
+
+static irqreturn_t pch_handler(int irq, void *pData);
+
+static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ u32 val;
+ val = ioread32(addr + offset);
+ val |= bitmask;
+ iowrite32(val, addr + offset);
+}
+
+static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ u32 val;
+ val = ioread32(addr + offset);
+ val &= (~bitmask);
+ iowrite32(val, addr + offset);
+}
+
+/**
+ * pch_init() - hardware initialization of I2C module
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_init(struct i2c_algo_pch_data *adap)
+{
+ u32 pch_i2cbc;
+ u32 pch_i2ctmr;
+ u32 reg_value;
+ void __iomem *p = adap->pch_base_address;
+
+ /* reset I2C controller */
+ iowrite32(0x01, p + PCH_I2CSRST);
+ iowrite32(0x0, p + PCH_I2CSRST);
+ /* Initialize I2C registers */
+ iowrite32(CLR_REG, p + PCH_I2CCTL);
+ iowrite32(CLR_REG, p + PCH_I2CMOD);
+ iowrite32(CLR_REG, p + PCH_I2CBUFFOR);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSLV);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSUB);
+ iowrite32(CLR_REG, p + PCH_I2CBUFMSK);
+ iowrite32(CLR_REG, p + PCH_I2CESRFOR);
+ iowrite32(CLR_REG, p + PCH_I2CESRMSK);
+ iowrite32(0x21, p + PCH_I2CNF);
+
+ reg_value = PCH_I2CCTL_I2CMEN;
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL,
+ PCH_I2CCTL_I2CMEN);
+
+ if (pch_i2c_speed != 400)
+ pch_i2c_speed = 100;
+
+ if (pch_i2c_speed == FAST_MODE_CLK) {
+ reg_value |= FAST_MODE_EN;
+ pch_dbg(adap, "Fast mode enabled\n");
+ }
+
+ if (pch_clk <= 0 || pch_clk > PCH_MAX_CLK)
+ pch_clk = 62500;
+
+ pch_i2cbc = ((pch_clk) + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
+ /* Set transfer speed in I2CBC */
+ iowrite32(pch_i2cbc, p + PCH_I2CBC);
+
+ pch_i2ctmr = (pch_clk) / 8;
+ iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
+
+ reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
+ iowrite32(reg_value, p + PCH_I2CCTL);
+
+ pch_dbg(adap,
+ "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
+ ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
+
+ init_waitqueue_head(&pch_event);
+}
+
+static inline int ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
+{
+ return cmp1.tv64 < cmp2.tv64;
+}
+
+/**
+ * pch_wait_for_bus_idle() - check the status of bus.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ * @timeout: waiting time counter (us).
+ */
+static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
+ s32 timeout)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ /* MAX timeout value is timeout*1000*1000nsec */
+ ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
+ do {
+ if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
+ break;
+ msleep(1);
+ } while (ktime_lt(ktime_get(), ns_val));
+
+ pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
+
+ if (timeout == 0) {
+ pch_err(adap, "return%d\n", -ETIME);
+ return -ETIME;
+ }
+
+ return 0;
+}
+
+/**
+ * pch_start() - Generate I2C start condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ *
+ * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
+ */
+static void pch_start(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+}
+
+/**
+ * pch_wait_for_xfer_complete() - initiates a wait for the tx complete event
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
+{
+ s32 ret;
+ ret = wait_event_timeout(pch_event,
+ (adap->pch_event_flag != 0), msecs_to_jiffies(50));
+ if (ret < 0) {
+ pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
+ return ret;
+ }
+
+ if (ret == 0) {
+ pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
+ return -ETIMEDOUT;
+ }
+
+ if (adap->pch_event_flag & I2C_ERROR_MASK) {
+ pch_err(adap, "error bits set: %x\n", adap->pch_event_flag);
+ return -EIO;
+ }
+
+ adap->pch_event_flag = 0;
+ ret = 0;
+
+ return ret;
+}
+
+/**
+ * pch_getack() - to confirm ACK/NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_getack(struct i2c_algo_pch_data *adap)
+{
+ u32 reg_val;
+ void __iomem *p = adap->pch_base_address;
+ reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
+
+ if (reg_val != 0) {
+ pch_err(adap, "return%d\n", -EPROTO);
+ return -EPROTO;
+ }
+
+ return 0;
+}
+
+/**
+ * pch_stop() - generate stop condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_stop(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ /* clear the start bit */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+}
+
+/**
+ * pch_repstart() - generate repeated start condition in normal mode
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_repstart(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_REPSTART);
+}
+
+/**
+ * pch_writebytes() - write data to I2C bus in normal mode
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @last: specifies whether last message or not.
+ * In the case of compound mode it will be 1 for last message,
+ * otherwise 0.
+ * @first: specifies whether first message or not.
+ * 1 for first message otherwise 0.
+ */
+static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+ u8 *buf;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ u32 addr_8_lsb;
+ s32 wrcount;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+ /* enable master tx */
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
+ length);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ addr_8_lsb = (addr & I2C_ADDR_MSK);
+ iowrite32(addr_8_lsb, p + PCH_I2CDR);
+ } else {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } else {
+ /* set 7 bit slave address and R/W bit as 0 */
+ iowrite32(addr << 1, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ }
+
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ for (wrcount = 0; wrcount < length; ++wrcount) {
+ /* write buffer value to I2C data register */
+ iowrite32(buf[wrcount], p + PCH_I2CDR);
+ pch_dbg(adap, "writing %x to Data register\n",
+ buf[wrcount]);
+
+ if (pch_wait_for_xfer_complete(adap) != 0)
+ return -ETIME;
+
+ if (pch_getack(adap))
+ return -ETIME;
+ }
+
+ /* check if this is the last message */
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+ } else {
+ pch_stop(adap);
+ return -EIO;
+ }
+
+ pch_dbg(adap, "return=%d\n", wrcount);
+
+ return wrcount;
+}
+
+/**
+ * pch_sendack() - send ACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+}
+
+/**
+ * pch_sendnack() - send NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendnack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+}
+
+/**
+ * pch_readbytes() - read data from I2C bus in normal mode.
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @last: specifies whether last message or not.
+ * @first: specifies whether first message or not.
+ */
+s32 pch_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ u8 *buf;
+ u32 count;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+
+ /* enable master reception */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+
+ } else {
+ /* 7 address bits + R/W bit */
+ addr = (((addr) << 1) | (I2C_RD));
+ iowrite32(addr, p + PCH_I2CDR);
+ }
+
+ /* check if it is the first message */
+ if (first)
+ pch_start(adap);
+
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ pch_dbg(adap, "return %d\n", 0);
+
+ if (length == 0) {
+ pch_stop(adap);
+ ioread32(p + PCH_I2CDR); /* Dummy read needs */
+
+ count = length;
+ } else {
+ int read_index;
+ int loop;
+ pch_sendack(adap);
+
+ /* Dummy read */
+ for (loop = 1, read_index = 0; loop < length; loop++) {
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (loop != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) != 0) {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } /* end for */
+
+ pch_sendnack(adap);
+
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (length != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) == 0) {
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+
+ buf[read_index++] = ioread32(p + PCH_I2CDR);
+ count = read_index;
+ } else {
+ count = -ETIME;
+ }
+
+ }
+ } else {
+ count = -ETIME;
+ pch_stop(adap);
+ }
+
+ return count;
+}
+
+/**
+ * pch_cb_ch0() - Interrupt handler Call back function
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_cb_ch0(struct i2c_algo_pch_data *adap)
+{
+ u32 sts;
+ void __iomem *p = adap->pch_base_address;
+
+ sts = ioread32(p + PCH_I2CSR);
+ sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
+ if (I2CMAL_BIT & sts)
+ adap->pch_event_flag |= I2CMAL_EVENT;
+
+ if (I2CMCF_BIT & sts)
+ adap->pch_event_flag |= I2CMCF_EVENT;
+
+ /* clear the applicable bits */
+ pch_clrbit((adap->pch_base_address), PCH_I2CSR, sts);
+
+ pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
+
+ wake_up(&pch_event);
+}
+
+/**
+ * pch_handler() - interrupt handler for the PCH I2C controller
+ * @irq: irq number.
+ * @pData: cookie passed back to the handler function.
+ */
+static irqreturn_t pch_handler(int irq, void *pData)
+{
+ s32 reg_val;
+
+ struct i2c_algo_pch_data *adap_data = (struct i2c_algo_pch_data *)pData;
+ void __iomem *p = adap_data->pch_base_address;
+ u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE);
+
+ if (mode != NORMAL_MODE) {
+ pch_err(adap_data, "I2C mode is not supported\n");
+ return IRQ_NONE;
+ }
+
+ reg_val = ioread32(p + PCH_I2CSR);
+ if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
+ pch_cb_ch0(adap_data);
+ else
+ return IRQ_NONE;
+
+ return IRQ_HANDLED;
+}
+#if 0
+ if (mode == NORMAL_MODE) {
+ reg_val = ioread32(p + PCH_I2CSR);
+ if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
+ pch_cb_ch0(adap_data);
+ else
+ goto err_out;
+ } else {
+ pch_err(adap_data, "I2C mode is not supported\n");
+ goto err_out;
+ }
+ return IRQ_HANDLED;
+
+err_out:
+ return IRQ_NONE;
+}
+#endif
+/**
+ * pch_xfer() - Reading adnd writing data through I2C bus
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @num: number of messages.
+ */
+static s32 pch_xfer(struct i2c_adapter *i2c_adap,
+ struct i2c_msg *msgs, s32 num)
+{
+ struct i2c_msg *pmsg;
+ u32 i;
+ u32 status;
+ u32 msglen;
+ u32 subaddrlen;
+ s32 ret;
+
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ ret = mutex_lock_interruptible(&pch_mutex);
+ if (ret)
+ return -ERESTARTSYS;
+
+ if (adap->p_adapter_info->pch_suspended) {
+ mutex_unlock(&pch_mutex);
+ return -EBUSY;
+ }
+
+ pch_dbg(adap, "adap->p_adapter_info->pch_suspended is %d\n",
+ adap->p_adapter_info->pch_suspended);
+ /* transfer not completed */
+ adap->pch_xfer_in_progress = true;
+
+ pmsg = &msgs[0];
+ pmsg->flags |= adap->pch_buff_mode_en;
+ status = pmsg->flags;
+ pch_dbg(adap,
+ "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
+ /* calculate sub address length and message length */
+ /* these are applicable only for buffer mode */
+ subaddrlen = pmsg->buf[0];
+ /* calculate actual message length excluding
+ * the sub address fields */
+ msglen = (pmsg->len) - (subaddrlen + 1);
+ i = 0;
+ if (status & (I2C_M_RD)) {
+ pch_dbg(adap, "invoking pch_readbytes\n");
+ ret = pch_readbytes(i2c_adap, pmsg, (i + 1 == num),
+ (i == 0));
+ } else {
+ pch_dbg(adap, "invoking pch_writebytes\n");
+ ret = pch_writebytes(i2c_adap, pmsg, (i + 1 == num),
+ (i == 0));
+ }
+
+ adap->pch_xfer_in_progress = false; /* transfer completed */
+
+ mutex_unlock(&pch_mutex);
+
+ return ret;
+}
+
+/**
+ * pch_func() - return the functionality of the I2C driver
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static u32 pch_func(struct i2c_adapter *adap)
+{
+ u32 ret;
+ ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
+ return ret;
+}
+
+static struct i2c_algorithm pch_algorithm = {
+ .master_xfer = pch_xfer,
+ .functionality = pch_func
+};
+
+/**
+ * pch_disbl_int() - Disable PCH I2C interrupts
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_disbl_int(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL,
+ NORMAL_INTR_ENBL);
+
+ iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
+
+ iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
+}
+
+static int __devinit pch_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ int i;
+ void __iomem *base_addr;
+ s32 ret;
+ struct adapter_info *adap_info =
+ kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
+
+ pch_pci_dbg(pdev, "Entered.\n");
+
+ if (adap_info == NULL) {
+ pch_pci_err(pdev, "Memory allocation FAILED\n");
+ return -ENOMEM;
+ }
+
+ ret = pci_enable_device(pdev);
+ if (ret) {
+ pch_pci_err(pdev, "pci_enable_device FAILED\n");
+ goto err_pci_enable;
+ }
+
+ ret = pci_request_regions(pdev, KBUILD_MODNAME);
+ if (ret) {
+ pch_pci_err(pdev, "pci_request_regions FAILED\n");
+ goto err_pci_req;
+ }
+
+ base_addr = pci_iomap(pdev, 1, 0);
+
+ if (base_addr == 0) {
+ pch_pci_err(pdev, "pci_iomap FAILED\n");
+ ret = -ENOMEM;
+ goto err_pci_iomap;
+ }
+
+ adap_info->pch_suspended = false;
+
+ adap_info->pch_data.p_adapter_info = adap_info;
+
+ adap_info->pch_data.pch_adapter.owner = THIS_MODULE;
+ adap_info->pch_data.pch_adapter.class = I2C_CLASS_HWMON;
+ strcpy(adap_info->pch_data.pch_adapter.name, KBUILD_MODNAME);
+ adap_info->pch_data.pch_adapter.algo = &pch_algorithm;
+ adap_info->pch_data.pch_adapter.algo_data =
+ &adap_info->pch_data;
+
+ /* (i * 0x80) + base_addr; */
+ adap_info->pch_data.pch_base_address = base_addr;
+
+ adap_info->pch_data.pch_adapter.dev.parent = &pdev->dev;
+
+ ret = i2c_add_adapter(&(adap_info->pch_data.pch_adapter));
+
+ if (ret) {
+ pch_pci_err(pdev, "i2c_add_adapter FAILED\n");
+ goto err_i2c_add_adapter;
+ }
+
+ pch_init(&adap_info->pch_data);
+ ret = request_irq(pdev->irq, pch_handler, IRQF_SHARED,
+ KBUILD_MODNAME, &adap_info->pch_data);
+ if (ret) {
+ pch_pci_err(pdev, "request_irq FAILED\n");
+ goto err_request_irq;
+ }
+
+ pci_set_drvdata(pdev, adap_info);
+ pch_pci_dbg(pdev, "returns %d.\n", ret);
+ return 0;
+
+err_request_irq:
+ i2c_del_adapter(&(adap_info->pch_data.pch_adapter));
+err_i2c_add_adapter:
+ pci_iounmap(pdev, base_addr);
+err_pci_iomap:
+ pci_release_regions(pdev);
+err_pci_req:
+ pci_disable_device(pdev);
+err_pci_enable:
+ kfree(adap_info);
+ return ret;
+}
+
+static void __devexit pch_remove(struct pci_dev *pdev)
+{
+ int i;
+
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+
+
+ pch_disbl_int(&adap_info->pch_data);
+ free_irq(pdev->irq, &adap_info->pch_data);
+ i2c_del_adapter(&(adap_info->pch_data.pch_adapter));
+
+ if (adap_info->pch_data.pch_base_address) {
+ pci_iounmap(pdev, adap_info->pch_data.pch_base_address);
+ adap_info->pch_data.pch_base_address = 0;
+ }
+
+ pci_set_drvdata(pdev, NULL);
+
+ pci_release_regions(pdev);
+
+ pci_disable_device(pdev);
+ kfree(adap_info);
+}
+
+#ifdef CONFIG_PM
+static int pch_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ int i;
+ int ret;
+
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+ void __iomem *p = adap_info->pch_data.pch_base_address;
+
+ adap_info->pch_suspended = true;
+
+ while ((adap_info->pch_data.pch_xfer_in_progress)) {
+ /* Wait until all channel transfers are completed */
+ msleep(1);
+ }
+ /* Disable the i2c interrupts */
+ pch_disbl_int(&adap_info->pch_data);
+
+ pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
+ "invoked function pch_disbl_int successfully\n",
+ ioread32(p + 0x08), ioread32(p + 0x30), ioread32(p + 0x44));
+
+ ret = pci_save_state(pdev);
+
+ if (ret) {
+ pch_pci_err(pdev, "pci_save_state\n");
+ return ret;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+ pci_disable_device(pdev);
+ pci_set_power_state(pdev, pci_choose_state(pdev, state));
+
+ return 0;
+}
+
+static int pch_resume(struct pci_dev *pdev)
+{
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+ int i;
+
+ pci_set_power_state(pdev, PCI_D0);
+ pci_restore_state(pdev);
+
+ if (pci_enable_device(pdev) < 0) {
+ pch_pci_err(pdev, "pci_enable_device FAILED in pch_resume\n");
+ return -EIO;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+
+ pch_init(&adap_info->pch_data);
+
+ adap_info->pch_suspended = false;
+
+ return 0;
+}
+#else
+#define pch_suspend NULL
+#define pch_resume NULL
+#endif
+
+static struct pci_driver pch_pcidriver = {
+ .name = KBUILD_MODNAME,
+ .id_table = pch_pcidev_id,
+ .probe = pch_probe,
+ .remove = __devexit_p(pch_remove),
+ .suspend = pch_suspend,
+ .resume = pch_resume
+};
+
+static int __init pch_pci_init(void)
+{
+ return pci_register_driver(&pch_pcidriver);
+}
+
+static void __exit pch_pci_exit(void)
+{
+ pci_unregister_driver(&pch_pcidriver);
+}
+
+MODULE_DESCRIPTION("PCH I2C PCI Driver");
+MODULE_LICENSE("GPL");
+module_init(pch_pci_init);
+module_exit(pch_pci_exit);
+module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
+module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
--
1.6.0.6
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
2010-09-03 12:26 ` Wolfram Sang
@ 2010-09-06 0:44 ` Masayuki Ohtake
-1 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtake @ 2010-09-06 0:44 UTC (permalink / raw)
To: Wolfram Sang, Alan Cox
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c, linux-kernel, joe, yong.y.wang,
qi.wang, andrew.chih.howe.khor, arjan, Tomoya MORINAGA,
Arnd Bergmann
Hi Wolfram Sang,
Thank you for your comments.
We will update and resubmit soon.
Thanks, Ohtake(OKISemi)
----- Original Message -----
From: "Wolfram Sang" <w.sang@pengutronix.de>
To: "Alan Cox" <alan@lxorguk.ukuu.org.uk>
Cc: "Masayuki Ohtak" <masa-korg@dsn.okisemi.com>; "Jean Delvare (PC drivers, core)" <khali@linux-fr.org>; "Ben Dooks
(embedded platforms)" <ben-linux@fluff.org>; "Crane Cai" <crane.cai@amd.com>; "Samuel Ortiz" <sameo@linux.intel.com>;
"Linus Walleij" <linus.walleij@stericsson.com>; "Ralf Baechle" <ralf@linux-mips.org>; "srinidhi kasagar"
<srinidhi.kasagar@stericsson.com>; <linux-i2c@vger.kernel.org>; <linux-kernel@vger.kernel.org>; <joe@perches.com>;
<yong.y.wang@intel.com>; <qi.wang@intel.com>; <andrew.chih.howe.khor@intel.com>; <arjan@linux.intel.com>; "Tomoya
MORINAGA" <morinaga526@dsn.okisemi.com>; "Arnd Bergmann" <arnd@arndb.de>
Sent: Friday, September 03, 2010 9:26 PM
Subject: Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-06 0:44 ` Masayuki Ohtake
0 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtake @ 2010-09-06 0:44 UTC (permalink / raw)
To: Wolfram Sang, Alan Cox
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, joe-6d6DIl74uiNBDgjK7y7TUQ,
yong.y.wang-ral2JQCrhuEAvxtiuMwx3w,
qi.wang-ral2JQCrhuEAvxtiuMwx3w,
andrew.chih.howe.khor-ral2JQCrhuEAvxtiuMwx3w,
arjan-VuQAYsv1563Yd54FQh9/CA, Tomoya MORINAGA, Arnd Bergmann
Hi Wolfram Sang,
Thank you for your comments.
We will update and resubmit soon.
Thanks, Ohtake(OKISemi)
----- Original Message -----
From: "Wolfram Sang" <w.sang-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
To: "Alan Cox" <alan-qBU/x9rampVanCEyBjwyrvXRex20P6io@public.gmane.org>
Cc: "Masayuki Ohtak" <masa-korg-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>; "Jean Delvare (PC drivers, core)" <khali-PUYAD+kWke1g9hUCZPvPmw@public.gmane.org>; "Ben Dooks
(embedded platforms)" <ben-linux-elnMNo+KYs3YtjvyW6yDsg@public.gmane.org>; "Crane Cai" <crane.cai-5C7GfCeVMHo@public.gmane.org>; "Samuel Ortiz" <sameo-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>;
"Linus Walleij" <linus.walleij-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>; "Ralf Baechle" <ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>; "srinidhi kasagar"
<srinidhi.kasagar-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>; <linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>; <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>; <joe-6d6DIl74uiNBDgjK7y7TUQ@public.gmane.org>;
<yong.y.wang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>; <qi.wang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>; <andrew.chih.howe.khor-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>; <arjan-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>; "Tomoya
MORINAGA" <morinaga526-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>; "Arnd Bergmann" <arnd-r2nGTMty4D4@public.gmane.org>
Sent: Friday, September 03, 2010 9:26 PM
Subject: Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
2010-09-03 12:36 ` Alan Cox
@ 2010-09-06 0:43 ` Masayuki Ohtake
-1 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtake @ 2010-09-06 0:43 UTC (permalink / raw)
To: Alan Cox
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c, linux-kernel, joe, yong.y.wang,
qi.wang, andrew.chih.howe.khor, arjan, Tomoya MORINAGA,
Arnd Bergmann
Hi Alan,
Thank you for your comments.
We will update and resubmit soon.
Thanks, Ohtake(OKISemi)
----- Original Message -----
From: "Alan Cox" <alan@lxorguk.ukuu.org.uk>
To: "Masayuki Ohtak" <masa-korg@dsn.okisemi.com>
Cc: "Jean Delvare (PC drivers, core)" <khali@linux-fr.org>; "Ben Dooks (embedded platforms)" <ben-linux@fluff.org>;
"Crane Cai" <crane.cai@amd.com>; "Samuel Ortiz" <sameo@linux.intel.com>; "Linus Walleij" <linus.walleij@stericsson.com>;
"Ralf Baechle" <ralf@linux-mips.org>; "srinidhi kasagar" <srinidhi.kasagar@stericsson.com>; <linux-i2c@vger.kernel.org>;
<linux-kernel@vger.kernel.org>; <joe@perches.com>; <yong.y.wang@intel.com>; <qi.wang@intel.com>;
<andrew.chih.howe.khor@intel.com>; <arjan@linux.intel.com>; "Tomoya MORINAGA" <morinaga526@dsn.okisemi.com>; "Arnd
Bergmann" <arnd@arndb.de>
Sent: Friday, September 03, 2010 9:36 PM
Subject: Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
> > +config PCH_I2C_CH_COUNT
> > + int "PCH I2C the number of channel count"
> > + range 1 2
> > + depends on PCH_I2C
> > + help
> > + This driver is for PCH(Platform controller Hub) I2C of Topcliff which
> > + is an IOH(Input/Output Hub) for x86 embedded processor.
> > + The number of I2C buses/channels supported by the PCH I2C controller.
> > + PCH I2C of Topcliff supports only one channel.
>
> These sort of settings need to be runtime so one kernel can be built for
> many platform variants. In this case if I understand correctly the
> current device only has one channel so the define could just be moved
> into the driver for now and made a variable later as/when/if new hardware
> with more channels appears.
>
>
>
> > +static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
> > +{
> > + s32 ret;
> > + ret = wait_event_interruptible_timeout(pch_event,
> > + (adap->pch_event_flag != 0), msecs_to_jiffies(50));
> > + if (ret < 0) {
> > + pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
> > + return ret;
> > + }
>
> You are reporting a timeout when _interruptible can also be woken by a
> signal to the process (eg the user hitting ^C)
>
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-06 0:43 ` Masayuki Ohtake
0 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtake @ 2010-09-06 0:43 UTC (permalink / raw)
To: Alan Cox
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, joe-6d6DIl74uiNBDgjK7y7TUQ,
yong.y.wang-ral2JQCrhuEAvxtiuMwx3w,
qi.wang-ral2JQCrhuEAvxtiuMwx3w,
andrew.chih.howe.khor-ral2JQCrhuEAvxtiuMwx3w,
arjan-VuQAYsv1563Yd54FQh9/CA, Tomoya MORINAGA, Arnd Bergmann
Hi Alan,
Thank you for your comments.
We will update and resubmit soon.
Thanks, Ohtake(OKISemi)
----- Original Message -----
From: "Alan Cox" <alan-qBU/x9rampVanCEyBjwyrvXRex20P6io@public.gmane.org>
To: "Masayuki Ohtak" <masa-korg-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>
Cc: "Jean Delvare (PC drivers, core)" <khali-PUYAD+kWke1g9hUCZPvPmw@public.gmane.org>; "Ben Dooks (embedded platforms)" <ben-linux-elnMNo+KYs3YtjvyW6yDsg@public.gmane.org>;
"Crane Cai" <crane.cai-5C7GfCeVMHo@public.gmane.org>; "Samuel Ortiz" <sameo-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>; "Linus Walleij" <linus.walleij-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>;
"Ralf Baechle" <ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>; "srinidhi kasagar" <srinidhi.kasagar-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>; <linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>;
<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>; <joe-6d6DIl74uiNBDgjK7y7TUQ@public.gmane.org>; <yong.y.wang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>; <qi.wang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>;
<andrew.chih.howe.khor-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>; <arjan-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>; "Tomoya MORINAGA" <morinaga526-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>; "Arnd
Bergmann" <arnd-r2nGTMty4D4@public.gmane.org>
Sent: Friday, September 03, 2010 9:36 PM
Subject: Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
> > +config PCH_I2C_CH_COUNT
> > + int "PCH I2C the number of channel count"
> > + range 1 2
> > + depends on PCH_I2C
> > + help
> > + This driver is for PCH(Platform controller Hub) I2C of Topcliff which
> > + is an IOH(Input/Output Hub) for x86 embedded processor.
> > + The number of I2C buses/channels supported by the PCH I2C controller.
> > + PCH I2C of Topcliff supports only one channel.
>
> These sort of settings need to be runtime so one kernel can be built for
> many platform variants. In this case if I understand correctly the
> current device only has one channel so the define could just be moved
> into the driver for now and made a variable later as/when/if new hardware
> with more channels appears.
>
>
>
> > +static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
> > +{
> > + s32 ret;
> > + ret = wait_event_interruptible_timeout(pch_event,
> > + (adap->pch_event_flag != 0), msecs_to_jiffies(50));
> > + if (ret < 0) {
> > + pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
> > + return ret;
> > + }
>
> You are reporting a timeout when _interruptible can also be woken by a
> signal to the process (eg the user hitting ^C)
>
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-03 12:36 ` Alan Cox
0 siblings, 0 replies; 47+ messages in thread
From: Alan Cox @ 2010-09-03 12:36 UTC (permalink / raw)
To: Masayuki Ohtak
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c, linux-kernel, joe, yong.y.wang,
qi.wang, andrew.chih.howe.khor, arjan, Tomoya MORINAGA,
Arnd Bergmann
> +config PCH_I2C_CH_COUNT
> + int "PCH I2C the number of channel count"
> + range 1 2
> + depends on PCH_I2C
> + help
> + This driver is for PCH(Platform controller Hub) I2C of Topcliff which
> + is an IOH(Input/Output Hub) for x86 embedded processor.
> + The number of I2C buses/channels supported by the PCH I2C controller.
> + PCH I2C of Topcliff supports only one channel.
These sort of settings need to be runtime so one kernel can be built for
many platform variants. In this case if I understand correctly the
current device only has one channel so the define could just be moved
into the driver for now and made a variable later as/when/if new hardware
with more channels appears.
> +static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
> +{
> + s32 ret;
> + ret = wait_event_interruptible_timeout(pch_event,
> + (adap->pch_event_flag != 0), msecs_to_jiffies(50));
> + if (ret < 0) {
> + pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
> + return ret;
> + }
You are reporting a timeout when _interruptible can also be woken by a
signal to the process (eg the user hitting ^C)
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-03 12:36 ` Alan Cox
0 siblings, 0 replies; 47+ messages in thread
From: Alan Cox @ 2010-09-03 12:36 UTC (permalink / raw)
To: Masayuki Ohtak
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, joe-6d6DIl74uiNBDgjK7y7TUQ,
yong.y.wang-ral2JQCrhuEAvxtiuMwx3w,
qi.wang-ral2JQCrhuEAvxtiuMwx3w,
andrew.chih.howe.khor-ral2JQCrhuEAvxtiuMwx3w,
arjan-VuQAYsv1563Yd54FQh9/CA, Tomoya MORINAGA, Arnd Bergmann
> +config PCH_I2C_CH_COUNT
> + int "PCH I2C the number of channel count"
> + range 1 2
> + depends on PCH_I2C
> + help
> + This driver is for PCH(Platform controller Hub) I2C of Topcliff which
> + is an IOH(Input/Output Hub) for x86 embedded processor.
> + The number of I2C buses/channels supported by the PCH I2C controller.
> + PCH I2C of Topcliff supports only one channel.
These sort of settings need to be runtime so one kernel can be built for
many platform variants. In this case if I understand correctly the
current device only has one channel so the define could just be moved
into the driver for now and made a variable later as/when/if new hardware
with more channels appears.
> +static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
> +{
> + s32 ret;
> + ret = wait_event_interruptible_timeout(pch_event,
> + (adap->pch_event_flag != 0), msecs_to_jiffies(50));
> + if (ret < 0) {
> + pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
> + return ret;
> + }
You are reporting a timeout when _interruptible can also be woken by a
signal to the process (eg the user hitting ^C)
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-03 12:26 ` Wolfram Sang
0 siblings, 0 replies; 47+ messages in thread
From: Wolfram Sang @ 2010-09-03 12:26 UTC (permalink / raw)
To: Alan Cox
Cc: Masayuki Ohtak, Jean Delvare (PC drivers, core),
Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c, linux-kernel, joe, yong.y.wang,
qi.wang, andrew.chih.howe.khor, arjan, Tomoya MORINAGA,
Arnd Bergmann
[-- Attachment #1: Type: text/plain, Size: 1733 bytes --]
On Fri, Sep 03, 2010 at 01:36:13PM +0100, Alan Cox wrote:
> > +config PCH_I2C_CH_COUNT
> > + int "PCH I2C the number of channel count"
> > + range 1 2
> > + depends on PCH_I2C
> > + help
> > + This driver is for PCH(Platform controller Hub) I2C of Topcliff which
> > + is an IOH(Input/Output Hub) for x86 embedded processor.
> > + The number of I2C buses/channels supported by the PCH I2C controller.
> > + PCH I2C of Topcliff supports only one channel.
>
> These sort of settings need to be runtime so one kernel can be built for
> many platform variants. In this case if I understand correctly the
> current device only has one channel so the define could just be moved
> into the driver for now and made a variable later as/when/if new hardware
> with more channels appears.
>
>
>
> > +static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
> > +{
> > + s32 ret;
> > + ret = wait_event_interruptible_timeout(pch_event,
> > + (adap->pch_event_flag != 0), msecs_to_jiffies(50));
> > + if (ret < 0) {
> > + pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
> > + return ret;
> > + }
>
> You are reporting a timeout when _interruptible can also be woken by a
> signal to the process (eg the user hitting ^C)
Sidenote: a number of embedded drivers decided to switch to
wait_event_timeout() recently because reacting to a signal may have
subtle issues and must be carefully implemented and tested. Stalled
busses were often the consequence. I don't know if this applies here but
better keep it in mind.
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 198 bytes --]
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-03 12:26 ` Wolfram Sang
0 siblings, 0 replies; 47+ messages in thread
From: Wolfram Sang @ 2010-09-03 12:26 UTC (permalink / raw)
To: Alan Cox
Cc: Masayuki Ohtak, Jean Delvare (PC drivers, core),
Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, joe-6d6DIl74uiNBDgjK7y7TUQ,
yong.y.wang-ral2JQCrhuEAvxtiuMwx3w,
qi.wang-ral2JQCrhuEAvxtiuMwx3w,
andrew.chih.howe.khor-ral2JQCrhuEAvxtiuMwx3w,
arjan-VuQAYsv1563Yd54FQh9/CA, Tomoya MORINAGA, Arnd Bergmann
[-- Attachment #1: Type: text/plain, Size: 1733 bytes --]
On Fri, Sep 03, 2010 at 01:36:13PM +0100, Alan Cox wrote:
> > +config PCH_I2C_CH_COUNT
> > + int "PCH I2C the number of channel count"
> > + range 1 2
> > + depends on PCH_I2C
> > + help
> > + This driver is for PCH(Platform controller Hub) I2C of Topcliff which
> > + is an IOH(Input/Output Hub) for x86 embedded processor.
> > + The number of I2C buses/channels supported by the PCH I2C controller.
> > + PCH I2C of Topcliff supports only one channel.
>
> These sort of settings need to be runtime so one kernel can be built for
> many platform variants. In this case if I understand correctly the
> current device only has one channel so the define could just be moved
> into the driver for now and made a variable later as/when/if new hardware
> with more channels appears.
>
>
>
> > +static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
> > +{
> > + s32 ret;
> > + ret = wait_event_interruptible_timeout(pch_event,
> > + (adap->pch_event_flag != 0), msecs_to_jiffies(50));
> > + if (ret < 0) {
> > + pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
> > + return ret;
> > + }
>
> You are reporting a timeout when _interruptible can also be woken by a
> signal to the process (eg the user hitting ^C)
Sidenote: a number of embedded drivers decided to switch to
wait_event_timeout() recently because reacting to a signal may have
subtle issues and must be carefully implemented and tested. Stalled
busses were often the consequence. I don't know if this applies here but
better keep it in mind.
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 198 bytes --]
^ permalink raw reply [flat|nested] 47+ messages in thread
* [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-03 10:19 ` Masayuki Ohtak
0 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtak @ 2010-09-03 10:19 UTC (permalink / raw)
To: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c, linux-kernel, joe, Linus Walleij
Cc: yong.y.wang, qi.wang, andrew.chih.howe.khor, arjan,
Tomoya MORINAGA, Arnd Bergmann, Masayuki Ohtake
I2C driver of Topcliff PCH
Topcliff PCH is the platform controller hub that is going to be used in
Intel's upcoming general embedded platform. All IO peripherals in
Topcliff PCH are actually devices sitting on AMBA bus.
Topcliff PCH has I2C I/F. Using this I/F, it is able to access system
devices connected to I2C.
Signed-off-by: Masayuki Ohtake <masa-korg@dsn.okisemi.com>
Reviewed-by: Linus Walleij <linus.walleij@stericsson.com>
---
drivers/i2c/busses/Kconfig | 18 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-pch.c | 944 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 963 insertions(+), 0 deletions(-)
create mode 100644 drivers/i2c/busses/i2c-pch.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index bceafbf..c5db1e7 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -613,6 +613,24 @@ config I2C_XILINX
This driver can also be built as a module. If so, the module
will be called xilinx_i2c.
+config PCH_I2C
+ tristate "PCH I2C of Intel Topcliff"
+ depends on PCI
+ help
+ This driver is for PCH(Platform controller Hub) I2C of Topcliff which
+ is an IOH(Input/Output Hub) for x86 embedded processor.
+ This driver can access PCH I2C bus device.
+
+config PCH_I2C_CH_COUNT
+ int "PCH I2C the number of channel count"
+ range 1 2
+ depends on PCH_I2C
+ help
+ This driver is for PCH(Platform controller Hub) I2C of Topcliff which
+ is an IOH(Input/Output Hub) for x86 embedded processor.
+ The number of I2C buses/channels supported by the PCH I2C controller.
+ PCH I2C of Topcliff supports only one channel.
+
comment "External I2C/SMBus adapter drivers"
config I2C_PARPORT
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 936880b..aa04135 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
+obj-$(CONFIG_PCH_I2C) += i2c-pch.o
# External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o
diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c
new file mode 100644
index 0000000..ae55a83
--- /dev/null
+++ b/drivers/i2c/busses/i2c-pch.c
@@ -0,0 +1,944 @@
+/*
+ * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/pci.h>
+#include <linux/mutex.h>
+#include <linux/ktime.h>
+
+#define PCH_MAX_CHN CONFIG_PCH_I2C_CH_COUNT /* Maximum I2C channels
+ available */
+#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
+#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
+#define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
+#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
+#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
+
+#define PCH_I2CSADR 0x00 /* I2C slave address register */
+#define PCH_I2CCTL 0x04 /* I2C control register */
+#define PCH_I2CSR 0x08 /* I2C status register */
+#define PCH_I2CDR 0x0C /* I2C data register */
+#define PCH_I2CMON 0x10 /* I2C bus monitor register */
+#define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
+#define PCH_I2CMOD 0x18 /* I2C mode register */
+#define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
+#define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
+#define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
+#define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
+#define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
+#define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
+#define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
+#define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
+#define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
+#define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
+#define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
+#define PCH_I2CTMR 0x48 /* I2C timer register */
+#define PCH_I2CSRST 0xFC /* I2C reset register */
+#define PCH_I2CNF 0xF8 /* I2C noise filter register */
+
+#define BUS_IDLE_TIMEOUT 20
+#define PCH_I2CCTL_I2CMEN 0x0080
+#define TEN_BIT_ADDR_DEFAULT 0xF000
+#define TEN_BIT_ADDR_MASK 0xF0
+#define PCH_START 0x0020
+#define PCH_ESR_START 0x0001
+#define PCH_BUFF_START 0x1
+#define PCH_REPSTART 0x0004
+#define PCH_ACK 0x0008
+#define PCH_GETACK 0x0001
+#define CLR_REG 0x0
+#define I2C_RD 0x1
+#define I2CMCF_BIT 0x0080
+#define I2CMIF_BIT 0x0002
+#define I2CMAL_BIT 0x0010
+#define I2CBMFI_BIT 0x0001
+#define I2CBMAL_BIT 0x0002
+#define I2CBMNA_BIT 0x0004
+#define I2CBMTO_BIT 0x0008
+#define I2CBMIS_BIT 0x0010
+#define I2CESRFI_BIT 0X0001
+#define I2CESRTO_BIT 0x0002
+#define I2CESRFIIE_BIT 0x1
+#define I2CESRTOIE_BIT 0x2
+#define I2CBMDZ_BIT 0x0040
+#define I2CBMAG_BIT 0x0020
+#define I2CMBB_BIT 0x0020
+#define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
+ I2CBMTO_BIT | I2CBMIS_BIT)
+#define I2C_ADDR_MSK 0xFF
+#define I2C_MSB_2B_MSK 0x300
+#define FAST_MODE_CLK 400
+#define FAST_MODE_EN 0x0001
+#define SUB_ADDR_LEN_MAX 4
+#define BUF_LEN_MAX 32
+#define PCH_BUFFER_MODE 0x1
+#define EEPROM_SW_RST_MODE 0x0002
+#define NORMAL_INTR_ENBL 0x0300
+#define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
+#define EEPROM_RST_INTR_DISBL 0x0
+#define BUFFER_MODE_INTR_ENBL 0x001F
+#define BUFFER_MODE_INTR_DISBL 0x0
+#define NORMAL_MODE 0x0
+#define BUFFER_MODE 0x1
+#define EEPROM_SR_MODE 0x2
+#define I2C_TX_MODE 0x0010
+#define PCH_BUF_TX 0xFFF7
+#define PCH_BUF_RD 0x0008
+#define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
+ I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
+#define I2CMAL_EVENT 0x0001
+#define I2CMCF_EVENT 0x0002
+#define I2CBMFI_EVENT 0x0004
+#define I2CBMAL_EVENT 0x0008
+#define I2CBMNA_EVENT 0x0010
+#define I2CBMTO_EVENT 0x0020
+#define I2CBMIS_EVENT 0x0040
+#define I2CESRFI_EVENT 0x0080
+#define I2CESRTO_EVENT 0x0100
+#define PCI_DEVICE_ID_PCH_I2C 0x8817
+
+#define pch_dbg(adap, fmt, arg...) \
+ dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
+
+#define pch_err(adap, fmt, arg...) \
+ dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
+
+#define pch_pci_err(pdev, fmt, arg...) \
+ dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
+
+#define pch_pci_dbg(pdev, fmt, arg...) \
+ dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
+
+/**
+ * struct i2c_algo_pch_data - for I2C driver functionalities
+ * @p_adapter_info: stores the reference to adapter_info structure
+ * @pch_adapter: stores the reference to i2c_adapter structure
+ * @pch_base_address: specifies the remapped base address
+ * @pch_buff_mode_en: specifies if buffer mode is enabled
+ * @pch_event_flag: specifies occurrence of interrupt events
+ * @pch_xfer_in_progress: specifies whether the transfer is completed
+ */
+struct i2c_algo_pch_data {
+ struct adapter_info *p_adapter_info;
+ struct i2c_adapter pch_adapter;
+ void __iomem *pch_base_address;
+ int pch_buff_mode_en;
+ u32 pch_event_flag;
+ bool pch_xfer_in_progress;
+};
+
+/**
+ * struct adapter_info - This structure holds the adapter information for the
+ PCH i2c controller
+ * @pch_data: stores a list of i2c_algo_pch_data
+ * @pch_suspended: specifies whether the system is suspended or not
+ * perhaps with more lines and words.
+ *
+ * pch_data has as many elements as maximum I2C channels
+ */
+struct adapter_info {
+ struct i2c_algo_pch_data pch_data[PCH_MAX_CHN];
+ bool pch_suspended;
+};
+
+
+static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
+static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
+static wait_queue_head_t pch_event;
+static DEFINE_MUTEX(pch_mutex);
+
+static struct pci_device_id __devinitdata pch_pcidev_id[] = {
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_I2C)},
+ {0,}
+};
+
+static irqreturn_t pch_handler_ch0(int irq, void *pData);
+static irqreturn_t(*pch_handler_list[PCH_MAX_CHN]) (int irq, void *pData) = {
+ pch_handler_ch0,
+};
+
+static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ u32 val;
+ val = ioread32(addr + offset);
+ val |= bitmask;
+ iowrite32(val, addr + offset);
+}
+
+static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ u32 val;
+ val = ioread32(addr + offset);
+ val &= (~bitmask);
+ iowrite32(val, addr + offset);
+}
+
+/**
+ * pch_init() - hardware initialization of I2C module
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_init(struct i2c_algo_pch_data *adap)
+{
+ u32 pch_i2cbc;
+ u32 pch_i2ctmr;
+ u32 reg_value;
+ void __iomem *p = adap->pch_base_address;
+
+ /* reset I2C controller */
+ iowrite32(0x01, p + PCH_I2CSRST);
+ iowrite32(0x0, p + PCH_I2CSRST);
+ /* Initialize I2C registers */
+ iowrite32(CLR_REG, p + PCH_I2CCTL);
+ iowrite32(CLR_REG, p + PCH_I2CMOD);
+ iowrite32(CLR_REG, p + PCH_I2CBUFFOR);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSLV);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSUB);
+ iowrite32(CLR_REG, p + PCH_I2CBUFMSK);
+ iowrite32(CLR_REG, p + PCH_I2CESRFOR);
+ iowrite32(CLR_REG, p + PCH_I2CESRMSK);
+ iowrite32(0x21, p + PCH_I2CNF);
+
+ reg_value = PCH_I2CCTL_I2CMEN;
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL,
+ PCH_I2CCTL_I2CMEN);
+
+ if (pch_i2c_speed != 400)
+ pch_i2c_speed = 100;
+
+ if (pch_i2c_speed == FAST_MODE_CLK) {
+ reg_value |= FAST_MODE_EN;
+ pch_dbg(adap, "Fast mode enabled\n");
+ }
+
+ if (pch_clk <= 0 || pch_clk > PCH_MAX_CLK)
+ pch_clk = 62500;
+
+ pch_i2cbc = ((pch_clk) + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
+ /* Set transfer speed in I2CBC */
+ iowrite32(pch_i2cbc, p + PCH_I2CBC);
+
+ pch_i2ctmr = (pch_clk) / 8;
+ iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
+
+ reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
+ iowrite32(reg_value, p + PCH_I2CCTL);
+
+ pch_dbg(adap,
+ "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
+ ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
+
+ init_waitqueue_head(&pch_event);
+}
+
+static inline int ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
+{
+ return cmp1.tv64 < cmp2.tv64;
+}
+
+/**
+ * pch_wait_for_bus_idle() - check the status of bus.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ * @timeout: waiting time counter (us).
+ */
+static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
+ s32 timeout)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ /* MAX timeout value is timeout*1000*1000nsec */
+ ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
+ do {
+ if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
+ break;
+ msleep(1);
+ } while (ktime_lt(ktime_get(), ns_val));
+
+ pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
+
+ if (timeout == 0) {
+ pch_err(adap, "return%d\n", -ETIME);
+ return -ETIME;
+ }
+
+ return 0;
+}
+
+/**
+ * pch_start() - Generate I2C start condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ *
+ * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
+ */
+static void pch_start(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+}
+
+/**
+ * pch_wait_for_xfer_complete() - initiates a wait for the tx complete event
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
+{
+ s32 ret;
+ ret = wait_event_interruptible_timeout(pch_event,
+ (adap->pch_event_flag != 0), msecs_to_jiffies(50));
+ if (ret < 0) {
+ pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
+ return ret;
+ }
+
+ if (ret == 0) {
+ pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
+ return -ETIMEDOUT;
+ }
+
+ if (adap->pch_event_flag & I2C_ERROR_MASK) {
+ pch_err(adap, "error bits set: %x\n", adap->pch_event_flag);
+ return -EIO;
+ }
+
+ adap->pch_event_flag = 0;
+ ret = 0;
+
+ return ret;
+}
+
+/**
+ * pch_getack() - to confirm ACK/NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_getack(struct i2c_algo_pch_data *adap)
+{
+ u32 reg_val;
+ void __iomem *p = adap->pch_base_address;
+ reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
+
+ if (reg_val != 0) {
+ pch_err(adap, "return%d\n", -EPROTO);
+ return -EPROTO;
+ }
+
+ return 0;
+}
+
+/**
+ * pch_stop() - generate stop condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_stop(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ /* clear the start bit */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+}
+
+/**
+ * pch_repstart() - generate repeated start condition in normal mode
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_repstart(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_REPSTART);
+}
+
+/**
+ * pch_writebytes() - write data to I2C bus in normal mode
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @last: specifies whether last message or not.
+ * In the case of compound mode it will be 1 for last message,
+ * otherwise 0.
+ * @first: specifies whether first message or not.
+ * 1 for first message otherwise 0.
+ */
+static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+ u8 *buf;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ u32 addr_8_lsb;
+ s32 wrcount;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+ /* enable master tx */
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
+ length);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ addr_8_lsb = (addr & I2C_ADDR_MSK);
+ iowrite32(addr_8_lsb, p + PCH_I2CDR);
+ } else {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } else {
+ /* set 7 bit slave address and R/W bit as 0 */
+ iowrite32(addr << 1, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ }
+
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ for (wrcount = 0; wrcount < length; ++wrcount) {
+ /* write buffer value to I2C data register */
+ iowrite32(buf[wrcount], p + PCH_I2CDR);
+ pch_dbg(adap, "writing %x to Data register\n",
+ buf[wrcount]);
+
+ if (pch_wait_for_xfer_complete(adap) != 0)
+ return -ETIME;
+
+ if (pch_getack(adap))
+ return -ETIME;
+ }
+
+ /* check if this is the last message */
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+ } else {
+ pch_stop(adap);
+ return -EIO;
+ }
+
+ pch_dbg(adap, "return=%d\n", wrcount);
+
+ return wrcount;
+}
+
+/**
+ * pch_sendack() - send ACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+}
+
+/**
+ * pch_sendnack() - send NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendnack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+}
+
+/**
+ * pch_readbytes() - read data from I2C bus in normal mode.
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @last: specifies whether last message or not.
+ * @first: specifies whether first message or not.
+ */
+s32 pch_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ u8 *buf;
+ u32 count;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+
+ /* enable master reception */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+
+ } else {
+ /* 7 address bits + R/W bit */
+ addr = (((addr) << 1) | (I2C_RD));
+ iowrite32(addr, p + PCH_I2CDR);
+ }
+
+ /* check if it is the first message */
+ if (first)
+ pch_start(adap);
+
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ pch_dbg(adap, "return %d\n", 0);
+
+ if (length == 0) {
+ pch_stop(adap);
+ ioread32(p + PCH_I2CDR); /* Dummy read needs */
+
+ count = length;
+ } else {
+ int read_index;
+ int loop;
+ pch_sendack(adap);
+
+ /* Dummy read */
+ for (loop = 1, read_index = 0; loop < length; loop++) {
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (loop != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) != 0) {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } /* end for */
+
+ pch_sendnack(adap);
+
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (length != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) == 0) {
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+
+ buf[read_index++] = ioread32(p + PCH_I2CDR);
+ count = read_index;
+ } else {
+ count = -ETIME;
+ }
+
+ }
+ } else {
+ count = -ETIME;
+ pch_stop(adap);
+ }
+
+ return count;
+}
+
+/**
+ * pch_cb_ch0() - Interrupt handler Call back function
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_cb_ch0(struct i2c_algo_pch_data *adap)
+{
+ u32 sts;
+ void __iomem *p = adap->pch_base_address;
+
+ sts = ioread32(p + PCH_I2CSR);
+ sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
+ if (I2CMAL_BIT & sts)
+ adap->pch_event_flag |= I2CMAL_EVENT;
+
+ if (I2CMCF_BIT & sts)
+ adap->pch_event_flag |= I2CMCF_EVENT;
+
+ /* clear the applicable bits */
+ pch_clrbit((adap->pch_base_address), PCH_I2CSR, sts);
+
+ pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
+
+ wake_up_interruptible(&pch_event);
+}
+
+/**
+ * pch_handler_ch0() - interrupt handler for the PCH I2C controller
+ * @irq: irq number.
+ * @pData: cookie passed back to the handler function.
+ */
+static irqreturn_t pch_handler_ch0(int irq, void *pData)
+{
+ s32 reg_val;
+
+ struct i2c_algo_pch_data *adap_data = (struct i2c_algo_pch_data *)pData;
+ void __iomem *p = adap_data->pch_base_address;
+ u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE);
+
+ if (mode != NORMAL_MODE) {
+ pch_err(adap_data, "I2C mode is not supported\n");
+ return IRQ_NONE;
+ }
+
+ reg_val = ioread32(p + PCH_I2CSR);
+ if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
+ pch_cb_ch0(adap_data);
+ else
+ return IRQ_NONE;
+
+ return IRQ_HANDLED;
+}
+#if 0
+ if (mode == NORMAL_MODE) {
+ reg_val = ioread32(p + PCH_I2CSR);
+ if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
+ pch_cb_ch0(adap_data);
+ else
+ goto err_out;
+ } else {
+ pch_err(adap_data, "I2C mode is not supported\n");
+ goto err_out;
+ }
+ return IRQ_HANDLED;
+
+err_out:
+ return IRQ_NONE;
+}
+#endif
+/**
+ * pch_xfer() - Reading adnd writing data through I2C bus
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @num: number of messages.
+ */
+static s32 pch_xfer(struct i2c_adapter *i2c_adap,
+ struct i2c_msg *msgs, s32 num)
+{
+ struct i2c_msg *pmsg;
+ u32 i;
+ u32 status;
+ u32 msglen;
+ u32 subaddrlen;
+ s32 ret;
+
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ ret = mutex_lock_interruptible(&pch_mutex);
+ if (ret)
+ return -ERESTARTSYS;
+
+ if (adap->p_adapter_info->pch_suspended) {
+ mutex_unlock(&pch_mutex);
+ return -EBUSY;
+ }
+
+ pch_dbg(adap, "adap->p_adapter_info->pch_suspended is %d\n",
+ adap->p_adapter_info->pch_suspended);
+ /* transfer not completed */
+ adap->pch_xfer_in_progress = true;
+
+ for (i = 0; i < num; i++) {
+ pmsg = &msgs[i];
+ pmsg->flags |= adap->pch_buff_mode_en;
+ status = pmsg->flags;
+ pch_dbg(adap,
+ "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
+ /* calculate sub address length and message length */
+ /* these are applicable only for buffer mode */
+ subaddrlen = pmsg->buf[0];
+ /* calculate actual message length excluding
+ * the sub address fields */
+ msglen = (pmsg->len) - (subaddrlen + 1);
+ if (status & (I2C_M_RD)) {
+ pch_dbg(adap, "invoking pch_readbytes\n");
+ ret = pch_readbytes(i2c_adap, pmsg, (i + 1 == num),
+ (i == 0));
+ } else {
+ pch_dbg(adap, "invoking pch_writebytes\n");
+ ret = pch_writebytes(i2c_adap, pmsg, (i + 1 == num),
+ (i == 0));
+ }
+
+ }
+
+ adap->pch_xfer_in_progress = false; /* transfer completed */
+
+ mutex_unlock(&pch_mutex);
+
+ return ret;
+}
+
+/**
+ * pch_func() - return the functionality of the I2C driver
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static u32 pch_func(struct i2c_adapter *adap)
+{
+ u32 ret;
+ ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
+ return ret;
+}
+
+static struct i2c_algorithm pch_algorithm = {
+ .master_xfer = pch_xfer,
+ .functionality = pch_func
+};
+
+/**
+ * pch_disbl_int() - Disable PCH I2C interrupts
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_disbl_int(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL,
+ NORMAL_INTR_ENBL);
+
+ iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
+
+ iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
+}
+
+static int __devinit pch_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ int i;
+ void __iomem *base_addr;
+ s32 ret;
+ struct adapter_info *adap_info =
+ kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
+
+ pch_pci_dbg(pdev, "Entered.\n");
+
+ if (adap_info == NULL) {
+ pch_pci_err(pdev, "Memory allocation FAILED\n");
+ return -ENOMEM;
+ }
+
+ ret = pci_enable_device(pdev);
+ if (ret) {
+ pch_pci_err(pdev, "pci_enable_device FAILED\n");
+ goto err_pci_enable;
+ }
+
+ ret = pci_request_regions(pdev, KBUILD_MODNAME);
+ if (ret) {
+ pch_pci_err(pdev, "pci_request_regions FAILED\n");
+ goto err_pci_req;
+ }
+
+ base_addr = pci_iomap(pdev, 1, 0);
+
+ if (base_addr == 0) {
+ pch_pci_err(pdev, "pci_iomap FAILED\n");
+ ret = -ENOMEM;
+ goto err_pci_iomap;
+ }
+
+ adap_info->pch_suspended = false;
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ adap_info->pch_data[i].p_adapter_info = adap_info;
+
+ adap_info->pch_data[i].pch_adapter.owner = THIS_MODULE;
+ adap_info->pch_data[i].pch_adapter.class = I2C_CLASS_HWMON;
+ strcpy(adap_info->pch_data[i].pch_adapter.name, KBUILD_MODNAME);
+ adap_info->pch_data[i].pch_adapter.algo = &pch_algorithm;
+ adap_info->pch_data[i].pch_adapter.algo_data =
+ &adap_info->pch_data[i];
+
+ /* (i * 0x80) + base_addr; */
+ adap_info->pch_data[i].pch_base_address = base_addr;
+
+ adap_info->pch_data[i].pch_adapter.dev.parent = &pdev->dev;
+
+ ret = i2c_add_adapter(&(adap_info->pch_data[i].pch_adapter));
+
+ if (ret) {
+ pch_pci_err(pdev, "i2c_add_adapter FAILED\n");
+ goto err_i2c_add_adapter;
+ }
+
+ pch_init(&adap_info->pch_data[i]);
+ ret = request_irq(pdev->irq, pch_handler_list[i], IRQF_SHARED,
+ KBUILD_MODNAME, &adap_info->pch_data[i]);
+ if (ret) {
+ pch_pci_err(pdev, "request_irq FAILED\n");
+ goto err_request_irq;
+ }
+ }
+
+ pci_set_drvdata(pdev, adap_info);
+ pch_pci_dbg(pdev, "returns %d.\n", ret);
+ return 0;
+
+err_request_irq:
+ for (i = 0; i < PCH_MAX_CHN; i++)
+ i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
+err_i2c_add_adapter:
+ pci_iounmap(pdev, base_addr);
+err_pci_iomap:
+ pci_release_regions(pdev);
+err_pci_req:
+ pci_disable_device(pdev);
+err_pci_enable:
+ kfree(adap_info);
+ return ret;
+}
+
+static void __devexit pch_remove(struct pci_dev *pdev)
+{
+ int i;
+
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ pch_disbl_int(&adap_info->pch_data[i]);
+ free_irq(pdev->irq, &adap_info->pch_data[i]);
+ i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
+ }
+
+ if (adap_info->pch_data[0].pch_base_address) {
+ pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
+ adap_info->pch_data[0].pch_base_address = 0;
+ }
+
+ pci_set_drvdata(pdev, NULL);
+
+ pci_release_regions(pdev);
+
+ pci_disable_device(pdev);
+ kfree(adap_info);
+}
+
+#ifdef CONFIG_PM
+static int pch_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ int i;
+ int ret;
+
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+ void __iomem *p = adap_info->pch_data[0].pch_base_address;
+
+ adap_info->pch_suspended = true;
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
+ /* Wait until all channel transfers are completed */
+ msleep(1);
+ }
+ /* Disable the i2c interrupts */
+ pch_disbl_int(&adap_info->pch_data[i]);
+ }
+
+ pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
+ "invoked function pch_disbl_int successfully\n",
+ ioread32(p + 0x08), ioread32(p + 0x30), ioread32(p + 0x44));
+
+ ret = pci_save_state(pdev);
+
+ if (ret) {
+ pch_pci_err(pdev, "pci_save_state\n");
+ return ret;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+ pci_disable_device(pdev);
+ pci_set_power_state(pdev, pci_choose_state(pdev, state));
+
+ return 0;
+}
+
+static int pch_resume(struct pci_dev *pdev)
+{
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+ int i;
+
+ pci_set_power_state(pdev, PCI_D0);
+ pci_restore_state(pdev);
+
+ if (pci_enable_device(pdev) < 0) {
+ pch_pci_err(pdev, "pci_enable_device FAILED in pch_resume\n");
+ return -EIO;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+
+ for (i = 0; i < PCH_MAX_CHN; i++)
+ pch_init(&adap_info->pch_data[i]);
+
+ adap_info->pch_suspended = false;
+
+ return 0;
+}
+#else
+#define pch_suspend NULL
+#define pch_resume NULL
+#endif
+
+static struct pci_driver pch_pcidriver = {
+ .name = KBUILD_MODNAME,
+ .id_table = pch_pcidev_id,
+ .probe = pch_probe,
+ .remove = __devexit_p(pch_remove),
+ .suspend = pch_suspend,
+ .resume = pch_resume
+};
+
+static int __init pch_pci_init(void)
+{
+ return pci_register_driver(&pch_pcidriver);
+}
+
+static void __exit pch_pci_exit(void)
+{
+ pci_unregister_driver(&pch_pcidriver);
+}
+
+MODULE_DESCRIPTION("PCH I2C PCI Driver");
+MODULE_LICENSE("GPL");
+module_init(pch_pci_init);
+module_exit(pch_pci_exit);
+module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
+module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
--
1.6.0.6
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-03 10:19 ` Masayuki Ohtak
0 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtak @ 2010-09-03 10:19 UTC (permalink / raw)
To: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz
Cc: yong.y.wang-ral2JQCrhuEAvxtiuMwx3w,
qi.wang-ral2JQCrhuEAvxtiuMwx3w,
andrew.chih.howe.khor-ral2JQCrhuEAvxtiuMwx3w,
arjan-VuQAYsv1563Yd54FQh9/CA, Tomoya MORINAGA, Arnd Bergmann,
Masayuki Ohtake
I2C driver of Topcliff PCH
Topcliff PCH is the platform controller hub that is going to be used in
Intel's upcoming general embedded platform. All IO peripherals in
Topcliff PCH are actually devices sitting on AMBA bus.
Topcliff PCH has I2C I/F. Using this I/F, it is able to access system
devices connected to I2C.
Signed-off-by: Masayuki Ohtake <masa-korg-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>
Reviewed-by: Linus Walleij <linus.walleij-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>
---
drivers/i2c/busses/Kconfig | 18 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-pch.c | 944 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 963 insertions(+), 0 deletions(-)
create mode 100644 drivers/i2c/busses/i2c-pch.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index bceafbf..c5db1e7 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -613,6 +613,24 @@ config I2C_XILINX
This driver can also be built as a module. If so, the module
will be called xilinx_i2c.
+config PCH_I2C
+ tristate "PCH I2C of Intel Topcliff"
+ depends on PCI
+ help
+ This driver is for PCH(Platform controller Hub) I2C of Topcliff which
+ is an IOH(Input/Output Hub) for x86 embedded processor.
+ This driver can access PCH I2C bus device.
+
+config PCH_I2C_CH_COUNT
+ int "PCH I2C the number of channel count"
+ range 1 2
+ depends on PCH_I2C
+ help
+ This driver is for PCH(Platform controller Hub) I2C of Topcliff which
+ is an IOH(Input/Output Hub) for x86 embedded processor.
+ The number of I2C buses/channels supported by the PCH I2C controller.
+ PCH I2C of Topcliff supports only one channel.
+
comment "External I2C/SMBus adapter drivers"
config I2C_PARPORT
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 936880b..aa04135 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
+obj-$(CONFIG_PCH_I2C) += i2c-pch.o
# External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o
diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c
new file mode 100644
index 0000000..ae55a83
--- /dev/null
+++ b/drivers/i2c/busses/i2c-pch.c
@@ -0,0 +1,944 @@
+/*
+ * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/pci.h>
+#include <linux/mutex.h>
+#include <linux/ktime.h>
+
+#define PCH_MAX_CHN CONFIG_PCH_I2C_CH_COUNT /* Maximum I2C channels
+ available */
+#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
+#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
+#define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
+#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
+#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
+
+#define PCH_I2CSADR 0x00 /* I2C slave address register */
+#define PCH_I2CCTL 0x04 /* I2C control register */
+#define PCH_I2CSR 0x08 /* I2C status register */
+#define PCH_I2CDR 0x0C /* I2C data register */
+#define PCH_I2CMON 0x10 /* I2C bus monitor register */
+#define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
+#define PCH_I2CMOD 0x18 /* I2C mode register */
+#define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
+#define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
+#define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
+#define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
+#define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
+#define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
+#define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
+#define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
+#define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
+#define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
+#define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
+#define PCH_I2CTMR 0x48 /* I2C timer register */
+#define PCH_I2CSRST 0xFC /* I2C reset register */
+#define PCH_I2CNF 0xF8 /* I2C noise filter register */
+
+#define BUS_IDLE_TIMEOUT 20
+#define PCH_I2CCTL_I2CMEN 0x0080
+#define TEN_BIT_ADDR_DEFAULT 0xF000
+#define TEN_BIT_ADDR_MASK 0xF0
+#define PCH_START 0x0020
+#define PCH_ESR_START 0x0001
+#define PCH_BUFF_START 0x1
+#define PCH_REPSTART 0x0004
+#define PCH_ACK 0x0008
+#define PCH_GETACK 0x0001
+#define CLR_REG 0x0
+#define I2C_RD 0x1
+#define I2CMCF_BIT 0x0080
+#define I2CMIF_BIT 0x0002
+#define I2CMAL_BIT 0x0010
+#define I2CBMFI_BIT 0x0001
+#define I2CBMAL_BIT 0x0002
+#define I2CBMNA_BIT 0x0004
+#define I2CBMTO_BIT 0x0008
+#define I2CBMIS_BIT 0x0010
+#define I2CESRFI_BIT 0X0001
+#define I2CESRTO_BIT 0x0002
+#define I2CESRFIIE_BIT 0x1
+#define I2CESRTOIE_BIT 0x2
+#define I2CBMDZ_BIT 0x0040
+#define I2CBMAG_BIT 0x0020
+#define I2CMBB_BIT 0x0020
+#define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
+ I2CBMTO_BIT | I2CBMIS_BIT)
+#define I2C_ADDR_MSK 0xFF
+#define I2C_MSB_2B_MSK 0x300
+#define FAST_MODE_CLK 400
+#define FAST_MODE_EN 0x0001
+#define SUB_ADDR_LEN_MAX 4
+#define BUF_LEN_MAX 32
+#define PCH_BUFFER_MODE 0x1
+#define EEPROM_SW_RST_MODE 0x0002
+#define NORMAL_INTR_ENBL 0x0300
+#define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
+#define EEPROM_RST_INTR_DISBL 0x0
+#define BUFFER_MODE_INTR_ENBL 0x001F
+#define BUFFER_MODE_INTR_DISBL 0x0
+#define NORMAL_MODE 0x0
+#define BUFFER_MODE 0x1
+#define EEPROM_SR_MODE 0x2
+#define I2C_TX_MODE 0x0010
+#define PCH_BUF_TX 0xFFF7
+#define PCH_BUF_RD 0x0008
+#define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
+ I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
+#define I2CMAL_EVENT 0x0001
+#define I2CMCF_EVENT 0x0002
+#define I2CBMFI_EVENT 0x0004
+#define I2CBMAL_EVENT 0x0008
+#define I2CBMNA_EVENT 0x0010
+#define I2CBMTO_EVENT 0x0020
+#define I2CBMIS_EVENT 0x0040
+#define I2CESRFI_EVENT 0x0080
+#define I2CESRTO_EVENT 0x0100
+#define PCI_DEVICE_ID_PCH_I2C 0x8817
+
+#define pch_dbg(adap, fmt, arg...) \
+ dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
+
+#define pch_err(adap, fmt, arg...) \
+ dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
+
+#define pch_pci_err(pdev, fmt, arg...) \
+ dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
+
+#define pch_pci_dbg(pdev, fmt, arg...) \
+ dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
+
+/**
+ * struct i2c_algo_pch_data - for I2C driver functionalities
+ * @p_adapter_info: stores the reference to adapter_info structure
+ * @pch_adapter: stores the reference to i2c_adapter structure
+ * @pch_base_address: specifies the remapped base address
+ * @pch_buff_mode_en: specifies if buffer mode is enabled
+ * @pch_event_flag: specifies occurrence of interrupt events
+ * @pch_xfer_in_progress: specifies whether the transfer is completed
+ */
+struct i2c_algo_pch_data {
+ struct adapter_info *p_adapter_info;
+ struct i2c_adapter pch_adapter;
+ void __iomem *pch_base_address;
+ int pch_buff_mode_en;
+ u32 pch_event_flag;
+ bool pch_xfer_in_progress;
+};
+
+/**
+ * struct adapter_info - This structure holds the adapter information for the
+ PCH i2c controller
+ * @pch_data: stores a list of i2c_algo_pch_data
+ * @pch_suspended: specifies whether the system is suspended or not
+ * perhaps with more lines and words.
+ *
+ * pch_data has as many elements as maximum I2C channels
+ */
+struct adapter_info {
+ struct i2c_algo_pch_data pch_data[PCH_MAX_CHN];
+ bool pch_suspended;
+};
+
+
+static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
+static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
+static wait_queue_head_t pch_event;
+static DEFINE_MUTEX(pch_mutex);
+
+static struct pci_device_id __devinitdata pch_pcidev_id[] = {
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_I2C)},
+ {0,}
+};
+
+static irqreturn_t pch_handler_ch0(int irq, void *pData);
+static irqreturn_t(*pch_handler_list[PCH_MAX_CHN]) (int irq, void *pData) = {
+ pch_handler_ch0,
+};
+
+static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ u32 val;
+ val = ioread32(addr + offset);
+ val |= bitmask;
+ iowrite32(val, addr + offset);
+}
+
+static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ u32 val;
+ val = ioread32(addr + offset);
+ val &= (~bitmask);
+ iowrite32(val, addr + offset);
+}
+
+/**
+ * pch_init() - hardware initialization of I2C module
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_init(struct i2c_algo_pch_data *adap)
+{
+ u32 pch_i2cbc;
+ u32 pch_i2ctmr;
+ u32 reg_value;
+ void __iomem *p = adap->pch_base_address;
+
+ /* reset I2C controller */
+ iowrite32(0x01, p + PCH_I2CSRST);
+ iowrite32(0x0, p + PCH_I2CSRST);
+ /* Initialize I2C registers */
+ iowrite32(CLR_REG, p + PCH_I2CCTL);
+ iowrite32(CLR_REG, p + PCH_I2CMOD);
+ iowrite32(CLR_REG, p + PCH_I2CBUFFOR);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSLV);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSUB);
+ iowrite32(CLR_REG, p + PCH_I2CBUFMSK);
+ iowrite32(CLR_REG, p + PCH_I2CESRFOR);
+ iowrite32(CLR_REG, p + PCH_I2CESRMSK);
+ iowrite32(0x21, p + PCH_I2CNF);
+
+ reg_value = PCH_I2CCTL_I2CMEN;
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL,
+ PCH_I2CCTL_I2CMEN);
+
+ if (pch_i2c_speed != 400)
+ pch_i2c_speed = 100;
+
+ if (pch_i2c_speed == FAST_MODE_CLK) {
+ reg_value |= FAST_MODE_EN;
+ pch_dbg(adap, "Fast mode enabled\n");
+ }
+
+ if (pch_clk <= 0 || pch_clk > PCH_MAX_CLK)
+ pch_clk = 62500;
+
+ pch_i2cbc = ((pch_clk) + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
+ /* Set transfer speed in I2CBC */
+ iowrite32(pch_i2cbc, p + PCH_I2CBC);
+
+ pch_i2ctmr = (pch_clk) / 8;
+ iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
+
+ reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
+ iowrite32(reg_value, p + PCH_I2CCTL);
+
+ pch_dbg(adap,
+ "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
+ ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
+
+ init_waitqueue_head(&pch_event);
+}
+
+static inline int ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
+{
+ return cmp1.tv64 < cmp2.tv64;
+}
+
+/**
+ * pch_wait_for_bus_idle() - check the status of bus.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ * @timeout: waiting time counter (us).
+ */
+static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
+ s32 timeout)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ /* MAX timeout value is timeout*1000*1000nsec */
+ ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
+ do {
+ if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
+ break;
+ msleep(1);
+ } while (ktime_lt(ktime_get(), ns_val));
+
+ pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
+
+ if (timeout == 0) {
+ pch_err(adap, "return%d\n", -ETIME);
+ return -ETIME;
+ }
+
+ return 0;
+}
+
+/**
+ * pch_start() - Generate I2C start condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ *
+ * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
+ */
+static void pch_start(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+}
+
+/**
+ * pch_wait_for_xfer_complete() - initiates a wait for the tx complete event
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
+{
+ s32 ret;
+ ret = wait_event_interruptible_timeout(pch_event,
+ (adap->pch_event_flag != 0), msecs_to_jiffies(50));
+ if (ret < 0) {
+ pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
+ return ret;
+ }
+
+ if (ret == 0) {
+ pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
+ return -ETIMEDOUT;
+ }
+
+ if (adap->pch_event_flag & I2C_ERROR_MASK) {
+ pch_err(adap, "error bits set: %x\n", adap->pch_event_flag);
+ return -EIO;
+ }
+
+ adap->pch_event_flag = 0;
+ ret = 0;
+
+ return ret;
+}
+
+/**
+ * pch_getack() - to confirm ACK/NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_getack(struct i2c_algo_pch_data *adap)
+{
+ u32 reg_val;
+ void __iomem *p = adap->pch_base_address;
+ reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
+
+ if (reg_val != 0) {
+ pch_err(adap, "return%d\n", -EPROTO);
+ return -EPROTO;
+ }
+
+ return 0;
+}
+
+/**
+ * pch_stop() - generate stop condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_stop(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ /* clear the start bit */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+}
+
+/**
+ * pch_repstart() - generate repeated start condition in normal mode
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_repstart(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_REPSTART);
+}
+
+/**
+ * pch_writebytes() - write data to I2C bus in normal mode
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @last: specifies whether last message or not.
+ * In the case of compound mode it will be 1 for last message,
+ * otherwise 0.
+ * @first: specifies whether first message or not.
+ * 1 for first message otherwise 0.
+ */
+static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+ u8 *buf;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ u32 addr_8_lsb;
+ s32 wrcount;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+ /* enable master tx */
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
+ length);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ addr_8_lsb = (addr & I2C_ADDR_MSK);
+ iowrite32(addr_8_lsb, p + PCH_I2CDR);
+ } else {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } else {
+ /* set 7 bit slave address and R/W bit as 0 */
+ iowrite32(addr << 1, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ }
+
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ for (wrcount = 0; wrcount < length; ++wrcount) {
+ /* write buffer value to I2C data register */
+ iowrite32(buf[wrcount], p + PCH_I2CDR);
+ pch_dbg(adap, "writing %x to Data register\n",
+ buf[wrcount]);
+
+ if (pch_wait_for_xfer_complete(adap) != 0)
+ return -ETIME;
+
+ if (pch_getack(adap))
+ return -ETIME;
+ }
+
+ /* check if this is the last message */
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+ } else {
+ pch_stop(adap);
+ return -EIO;
+ }
+
+ pch_dbg(adap, "return=%d\n", wrcount);
+
+ return wrcount;
+}
+
+/**
+ * pch_sendack() - send ACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+}
+
+/**
+ * pch_sendnack() - send NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendnack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+}
+
+/**
+ * pch_readbytes() - read data from I2C bus in normal mode.
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @last: specifies whether last message or not.
+ * @first: specifies whether first message or not.
+ */
+s32 pch_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ u8 *buf;
+ u32 count;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+
+ /* enable master reception */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+
+ } else {
+ /* 7 address bits + R/W bit */
+ addr = (((addr) << 1) | (I2C_RD));
+ iowrite32(addr, p + PCH_I2CDR);
+ }
+
+ /* check if it is the first message */
+ if (first)
+ pch_start(adap);
+
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ pch_dbg(adap, "return %d\n", 0);
+
+ if (length == 0) {
+ pch_stop(adap);
+ ioread32(p + PCH_I2CDR); /* Dummy read needs */
+
+ count = length;
+ } else {
+ int read_index;
+ int loop;
+ pch_sendack(adap);
+
+ /* Dummy read */
+ for (loop = 1, read_index = 0; loop < length; loop++) {
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (loop != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) != 0) {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } /* end for */
+
+ pch_sendnack(adap);
+
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (length != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) == 0) {
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+
+ buf[read_index++] = ioread32(p + PCH_I2CDR);
+ count = read_index;
+ } else {
+ count = -ETIME;
+ }
+
+ }
+ } else {
+ count = -ETIME;
+ pch_stop(adap);
+ }
+
+ return count;
+}
+
+/**
+ * pch_cb_ch0() - Interrupt handler Call back function
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_cb_ch0(struct i2c_algo_pch_data *adap)
+{
+ u32 sts;
+ void __iomem *p = adap->pch_base_address;
+
+ sts = ioread32(p + PCH_I2CSR);
+ sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
+ if (I2CMAL_BIT & sts)
+ adap->pch_event_flag |= I2CMAL_EVENT;
+
+ if (I2CMCF_BIT & sts)
+ adap->pch_event_flag |= I2CMCF_EVENT;
+
+ /* clear the applicable bits */
+ pch_clrbit((adap->pch_base_address), PCH_I2CSR, sts);
+
+ pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
+
+ wake_up_interruptible(&pch_event);
+}
+
+/**
+ * pch_handler_ch0() - interrupt handler for the PCH I2C controller
+ * @irq: irq number.
+ * @pData: cookie passed back to the handler function.
+ */
+static irqreturn_t pch_handler_ch0(int irq, void *pData)
+{
+ s32 reg_val;
+
+ struct i2c_algo_pch_data *adap_data = (struct i2c_algo_pch_data *)pData;
+ void __iomem *p = adap_data->pch_base_address;
+ u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE);
+
+ if (mode != NORMAL_MODE) {
+ pch_err(adap_data, "I2C mode is not supported\n");
+ return IRQ_NONE;
+ }
+
+ reg_val = ioread32(p + PCH_I2CSR);
+ if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
+ pch_cb_ch0(adap_data);
+ else
+ return IRQ_NONE;
+
+ return IRQ_HANDLED;
+}
+#if 0
+ if (mode == NORMAL_MODE) {
+ reg_val = ioread32(p + PCH_I2CSR);
+ if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
+ pch_cb_ch0(adap_data);
+ else
+ goto err_out;
+ } else {
+ pch_err(adap_data, "I2C mode is not supported\n");
+ goto err_out;
+ }
+ return IRQ_HANDLED;
+
+err_out:
+ return IRQ_NONE;
+}
+#endif
+/**
+ * pch_xfer() - Reading adnd writing data through I2C bus
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @num: number of messages.
+ */
+static s32 pch_xfer(struct i2c_adapter *i2c_adap,
+ struct i2c_msg *msgs, s32 num)
+{
+ struct i2c_msg *pmsg;
+ u32 i;
+ u32 status;
+ u32 msglen;
+ u32 subaddrlen;
+ s32 ret;
+
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ ret = mutex_lock_interruptible(&pch_mutex);
+ if (ret)
+ return -ERESTARTSYS;
+
+ if (adap->p_adapter_info->pch_suspended) {
+ mutex_unlock(&pch_mutex);
+ return -EBUSY;
+ }
+
+ pch_dbg(adap, "adap->p_adapter_info->pch_suspended is %d\n",
+ adap->p_adapter_info->pch_suspended);
+ /* transfer not completed */
+ adap->pch_xfer_in_progress = true;
+
+ for (i = 0; i < num; i++) {
+ pmsg = &msgs[i];
+ pmsg->flags |= adap->pch_buff_mode_en;
+ status = pmsg->flags;
+ pch_dbg(adap,
+ "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
+ /* calculate sub address length and message length */
+ /* these are applicable only for buffer mode */
+ subaddrlen = pmsg->buf[0];
+ /* calculate actual message length excluding
+ * the sub address fields */
+ msglen = (pmsg->len) - (subaddrlen + 1);
+ if (status & (I2C_M_RD)) {
+ pch_dbg(adap, "invoking pch_readbytes\n");
+ ret = pch_readbytes(i2c_adap, pmsg, (i + 1 == num),
+ (i == 0));
+ } else {
+ pch_dbg(adap, "invoking pch_writebytes\n");
+ ret = pch_writebytes(i2c_adap, pmsg, (i + 1 == num),
+ (i == 0));
+ }
+
+ }
+
+ adap->pch_xfer_in_progress = false; /* transfer completed */
+
+ mutex_unlock(&pch_mutex);
+
+ return ret;
+}
+
+/**
+ * pch_func() - return the functionality of the I2C driver
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static u32 pch_func(struct i2c_adapter *adap)
+{
+ u32 ret;
+ ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
+ return ret;
+}
+
+static struct i2c_algorithm pch_algorithm = {
+ .master_xfer = pch_xfer,
+ .functionality = pch_func
+};
+
+/**
+ * pch_disbl_int() - Disable PCH I2C interrupts
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_disbl_int(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL,
+ NORMAL_INTR_ENBL);
+
+ iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
+
+ iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
+}
+
+static int __devinit pch_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ int i;
+ void __iomem *base_addr;
+ s32 ret;
+ struct adapter_info *adap_info =
+ kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
+
+ pch_pci_dbg(pdev, "Entered.\n");
+
+ if (adap_info == NULL) {
+ pch_pci_err(pdev, "Memory allocation FAILED\n");
+ return -ENOMEM;
+ }
+
+ ret = pci_enable_device(pdev);
+ if (ret) {
+ pch_pci_err(pdev, "pci_enable_device FAILED\n");
+ goto err_pci_enable;
+ }
+
+ ret = pci_request_regions(pdev, KBUILD_MODNAME);
+ if (ret) {
+ pch_pci_err(pdev, "pci_request_regions FAILED\n");
+ goto err_pci_req;
+ }
+
+ base_addr = pci_iomap(pdev, 1, 0);
+
+ if (base_addr == 0) {
+ pch_pci_err(pdev, "pci_iomap FAILED\n");
+ ret = -ENOMEM;
+ goto err_pci_iomap;
+ }
+
+ adap_info->pch_suspended = false;
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ adap_info->pch_data[i].p_adapter_info = adap_info;
+
+ adap_info->pch_data[i].pch_adapter.owner = THIS_MODULE;
+ adap_info->pch_data[i].pch_adapter.class = I2C_CLASS_HWMON;
+ strcpy(adap_info->pch_data[i].pch_adapter.name, KBUILD_MODNAME);
+ adap_info->pch_data[i].pch_adapter.algo = &pch_algorithm;
+ adap_info->pch_data[i].pch_adapter.algo_data =
+ &adap_info->pch_data[i];
+
+ /* (i * 0x80) + base_addr; */
+ adap_info->pch_data[i].pch_base_address = base_addr;
+
+ adap_info->pch_data[i].pch_adapter.dev.parent = &pdev->dev;
+
+ ret = i2c_add_adapter(&(adap_info->pch_data[i].pch_adapter));
+
+ if (ret) {
+ pch_pci_err(pdev, "i2c_add_adapter FAILED\n");
+ goto err_i2c_add_adapter;
+ }
+
+ pch_init(&adap_info->pch_data[i]);
+ ret = request_irq(pdev->irq, pch_handler_list[i], IRQF_SHARED,
+ KBUILD_MODNAME, &adap_info->pch_data[i]);
+ if (ret) {
+ pch_pci_err(pdev, "request_irq FAILED\n");
+ goto err_request_irq;
+ }
+ }
+
+ pci_set_drvdata(pdev, adap_info);
+ pch_pci_dbg(pdev, "returns %d.\n", ret);
+ return 0;
+
+err_request_irq:
+ for (i = 0; i < PCH_MAX_CHN; i++)
+ i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
+err_i2c_add_adapter:
+ pci_iounmap(pdev, base_addr);
+err_pci_iomap:
+ pci_release_regions(pdev);
+err_pci_req:
+ pci_disable_device(pdev);
+err_pci_enable:
+ kfree(adap_info);
+ return ret;
+}
+
+static void __devexit pch_remove(struct pci_dev *pdev)
+{
+ int i;
+
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ pch_disbl_int(&adap_info->pch_data[i]);
+ free_irq(pdev->irq, &adap_info->pch_data[i]);
+ i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
+ }
+
+ if (adap_info->pch_data[0].pch_base_address) {
+ pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
+ adap_info->pch_data[0].pch_base_address = 0;
+ }
+
+ pci_set_drvdata(pdev, NULL);
+
+ pci_release_regions(pdev);
+
+ pci_disable_device(pdev);
+ kfree(adap_info);
+}
+
+#ifdef CONFIG_PM
+static int pch_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ int i;
+ int ret;
+
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+ void __iomem *p = adap_info->pch_data[0].pch_base_address;
+
+ adap_info->pch_suspended = true;
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
+ /* Wait until all channel transfers are completed */
+ msleep(1);
+ }
+ /* Disable the i2c interrupts */
+ pch_disbl_int(&adap_info->pch_data[i]);
+ }
+
+ pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
+ "invoked function pch_disbl_int successfully\n",
+ ioread32(p + 0x08), ioread32(p + 0x30), ioread32(p + 0x44));
+
+ ret = pci_save_state(pdev);
+
+ if (ret) {
+ pch_pci_err(pdev, "pci_save_state\n");
+ return ret;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+ pci_disable_device(pdev);
+ pci_set_power_state(pdev, pci_choose_state(pdev, state));
+
+ return 0;
+}
+
+static int pch_resume(struct pci_dev *pdev)
+{
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+ int i;
+
+ pci_set_power_state(pdev, PCI_D0);
+ pci_restore_state(pdev);
+
+ if (pci_enable_device(pdev) < 0) {
+ pch_pci_err(pdev, "pci_enable_device FAILED in pch_resume\n");
+ return -EIO;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+
+ for (i = 0; i < PCH_MAX_CHN; i++)
+ pch_init(&adap_info->pch_data[i]);
+
+ adap_info->pch_suspended = false;
+
+ return 0;
+}
+#else
+#define pch_suspend NULL
+#define pch_resume NULL
+#endif
+
+static struct pci_driver pch_pcidriver = {
+ .name = KBUILD_MODNAME,
+ .id_table = pch_pcidev_id,
+ .probe = pch_probe,
+ .remove = __devexit_p(pch_remove),
+ .suspend = pch_suspend,
+ .resume = pch_resume
+};
+
+static int __init pch_pci_init(void)
+{
+ return pci_register_driver(&pch_pcidriver);
+}
+
+static void __exit pch_pci_exit(void)
+{
+ pci_unregister_driver(&pch_pcidriver);
+}
+
+MODULE_DESCRIPTION("PCH I2C PCI Driver");
+MODULE_LICENSE("GPL");
+module_init(pch_pci_init);
+module_exit(pch_pci_exit);
+module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
+module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
--
1.6.0.6
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
2010-09-03 8:10 ` Joe Perches
@ 2010-09-03 10:01 ` Masayuki Ohtake
-1 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtake @ 2010-09-03 10:01 UTC (permalink / raw)
To: Joe Perches
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c, linux-kernel, yong.y.wang, qi.wang,
andrew.chih.howe.khor, arjan, Tomoya MORINAGA, Arnd Bergmann
----- Original Message -----
From: "Joe Perches" <joe@perches.com>
To: "Masayuki Ohtak" <masa-korg@dsn.okisemi.com>
Cc: "Jean Delvare (PC drivers, core)" <khali@linux-fr.org>; "Ben Dooks (embedded platforms)" <ben-linux@fluff.org>;
"Crane Cai" <crane.cai@amd.com>; "Samuel Ortiz" <sameo@linux.intel.com>; "Linus Walleij" <linus.walleij@stericsson.com>;
"Ralf Baechle" <ralf@linux-mips.org>; "srinidhi kasagar" <srinidhi.kasagar@stericsson.com>; <linux-i2c@vger.kernel.org>;
<linux-kernel@vger.kernel.org>; <yong.y.wang@intel.com>; <qi.wang@intel.com>; <andrew.chih.howe.khor@intel.com>;
<arjan@linux.intel.com>; "Tomoya MORINAGA" <morinaga526@dsn.okisemi.com>; "Arnd Bergmann" <arnd@arndb.de>
Sent: Friday, September 03, 2010 5:10 PM
Subject: Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
> On Fri, 2010-09-03 at 16:15 +0900, Masayuki Ohtak wrote:
> []
> > +#define pch_dbg(adap, fmt, arg...) \
> > + dev_dbg(adap->pch_adapter.dev.parent, "%s :"fmt, __func__, ##arg)
> > +
> > +#define pch_err(adap, fmt, arg...) \
> > + dev_err(adap->pch_adapter.dev.parent, "%s :"fmt, __func__, ##arg)
> > +
> > +#define pch_pci_err(pdev, fmt, arg...) \
> > + dev_err(&pdev->dev, "%s :"fmt, __func__, ##arg)
> > +#define pch_pci_dbg(pdev, fmt, arg...) \
> > + dev_dbg(&pdev->dev, "%s :"fmt, __func__, ##arg)
>
> OK, but it seems careless because the two types
> are not uniformly indented, there's a blank line
> between pch_dbg and pch_err, and the two pch_pci_<level>
> defines are in the reverse order without a blank line
> between them.
>
> I think it's better to use separate multiple strings
> that are concatentated by the preprocessor like:
> "%s :" fmt
> not
> "%s :"fmt
>
> Almost all code in kernel uses "%s: " to format __func__.
> Some use "%s(): ". I think "%s :" is unique.
>
> The rest of the logging messages look good.
>
> Some other comments:
>
> > + if ((pch_wait_for_xfer_complete(adap) == 0) &&
> > + (pch_getack(adap) == 0)) {
>
> This would look better as:
>
> if ((pch_wait_for_xfer_complete(adap) == 0) &&
> (pch_getack(adap) == 0)) {
>
> > + if ((pch_wait_for_xfer_complete(adap) == 0)
> > + && (pch_getack(adap) == 0)) {
>
> Here too.
>
> > + for (i = 0; i < PCH_MAX_CHN; i++) {
> > + while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
> > + /* Wait until all channel transfers are completed */
> > + msleep(1);
> > + }
> > + /* Disable the i2c interrupts */
> > + pch_disbl_int(&adap_info->pch_data[i]);
> > + }
>
> Would it be better to disable all possible interrupts first
> or do you need to disable them in order?
* Your proposal
If pch_disbl_int is executed firstly,
queued data is destroyed.
* Current spec
If checking status firstly,
all data can be sent.
Thus, I think current spec is better than yours.
>
> Something like:
>
> bool *disabled = kzalloc(PCH_MAX_CHN * sizeof(bool), GFP_KERNEL);
> /*
> * or a static with a memset, or check something
> * like pch_is_int_enabled(&adap_info->pch_data[i])
> * then remove the else because the kzalloc couldn't fail.
> */
> if (disabled) {
> bool alldone;
> do {
> alldone = true;
> for (i = 0; i < PCH_MAX_CHN; i++) {
> if (!adap_info->pch_data[i].pch_xfer_in_progress &&
> !disabled[i])) {
> pch_disbl_int(&adap_info->pch_data[i]);
> disabled[i] = true;
> } else
> alldone = false;
> }
> if (!alldone) {
> /* Wait until all channel transfers are completed */
> msleep(1);
> }
> } while (!alldone);
> kfree(disabled);
>
> /* remove the else if there's a static etc */
>
> } else {
> for (i = 0; i < PCH_MAX_CHN; i++) {
> while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
> /* Wait until all channel transfers are completed */
> msleep(1);
> }
> /* Disable the i2c interrupts */
> pch_disbl_int(&adap_info->pch_data[i]);
> }
> }
>
> cheers, Joe
>
I will resubmit modified patch soon.
Thanks, Ohtake(OKISemi)
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-03 10:01 ` Masayuki Ohtake
0 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtake @ 2010-09-03 10:01 UTC (permalink / raw)
To: Joe Perches
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
yong.y.wang-ral2JQCrhuEAvxtiuMwx3w,
qi.wang-ral2JQCrhuEAvxtiuMwx3w,
andrew.chih.howe.khor-ral2JQCrhuEAvxtiuMwx3w,
arjan-VuQAYsv1563Yd54FQh9/CA, Tomoya MORINAGA, Arnd Bergmann
----- Original Message -----
From: "Joe Perches" <joe-6d6DIl74uiNBDgjK7y7TUQ@public.gmane.org>
To: "Masayuki Ohtak" <masa-korg-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>
Cc: "Jean Delvare (PC drivers, core)" <khali-PUYAD+kWke1g9hUCZPvPmw@public.gmane.org>; "Ben Dooks (embedded platforms)" <ben-linux-elnMNo+KYs3YtjvyW6yDsg@public.gmane.org>;
"Crane Cai" <crane.cai-5C7GfCeVMHo@public.gmane.org>; "Samuel Ortiz" <sameo-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>; "Linus Walleij" <linus.walleij-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>;
"Ralf Baechle" <ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>; "srinidhi kasagar" <srinidhi.kasagar-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>; <linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>;
<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>; <yong.y.wang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>; <qi.wang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>; <andrew.chih.howe.khor-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>;
<arjan-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>; "Tomoya MORINAGA" <morinaga526-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>; "Arnd Bergmann" <arnd-r2nGTMty4D4@public.gmane.org>
Sent: Friday, September 03, 2010 5:10 PM
Subject: Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
> On Fri, 2010-09-03 at 16:15 +0900, Masayuki Ohtak wrote:
> []
> > +#define pch_dbg(adap, fmt, arg...) \
> > + dev_dbg(adap->pch_adapter.dev.parent, "%s :"fmt, __func__, ##arg)
> > +
> > +#define pch_err(adap, fmt, arg...) \
> > + dev_err(adap->pch_adapter.dev.parent, "%s :"fmt, __func__, ##arg)
> > +
> > +#define pch_pci_err(pdev, fmt, arg...) \
> > + dev_err(&pdev->dev, "%s :"fmt, __func__, ##arg)
> > +#define pch_pci_dbg(pdev, fmt, arg...) \
> > + dev_dbg(&pdev->dev, "%s :"fmt, __func__, ##arg)
>
> OK, but it seems careless because the two types
> are not uniformly indented, there's a blank line
> between pch_dbg and pch_err, and the two pch_pci_<level>
> defines are in the reverse order without a blank line
> between them.
>
> I think it's better to use separate multiple strings
> that are concatentated by the preprocessor like:
> "%s :" fmt
> not
> "%s :"fmt
>
> Almost all code in kernel uses "%s: " to format __func__.
> Some use "%s(): ". I think "%s :" is unique.
>
> The rest of the logging messages look good.
>
> Some other comments:
>
> > + if ((pch_wait_for_xfer_complete(adap) == 0) &&
> > + (pch_getack(adap) == 0)) {
>
> This would look better as:
>
> if ((pch_wait_for_xfer_complete(adap) == 0) &&
> (pch_getack(adap) == 0)) {
>
> > + if ((pch_wait_for_xfer_complete(adap) == 0)
> > + && (pch_getack(adap) == 0)) {
>
> Here too.
>
> > + for (i = 0; i < PCH_MAX_CHN; i++) {
> > + while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
> > + /* Wait until all channel transfers are completed */
> > + msleep(1);
> > + }
> > + /* Disable the i2c interrupts */
> > + pch_disbl_int(&adap_info->pch_data[i]);
> > + }
>
> Would it be better to disable all possible interrupts first
> or do you need to disable them in order?
* Your proposal
If pch_disbl_int is executed firstly,
queued data is destroyed.
* Current spec
If checking status firstly,
all data can be sent.
Thus, I think current spec is better than yours.
>
> Something like:
>
> bool *disabled = kzalloc(PCH_MAX_CHN * sizeof(bool), GFP_KERNEL);
> /*
> * or a static with a memset, or check something
> * like pch_is_int_enabled(&adap_info->pch_data[i])
> * then remove the else because the kzalloc couldn't fail.
> */
> if (disabled) {
> bool alldone;
> do {
> alldone = true;
> for (i = 0; i < PCH_MAX_CHN; i++) {
> if (!adap_info->pch_data[i].pch_xfer_in_progress &&
> !disabled[i])) {
> pch_disbl_int(&adap_info->pch_data[i]);
> disabled[i] = true;
> } else
> alldone = false;
> }
> if (!alldone) {
> /* Wait until all channel transfers are completed */
> msleep(1);
> }
> } while (!alldone);
> kfree(disabled);
>
> /* remove the else if there's a static etc */
>
> } else {
> for (i = 0; i < PCH_MAX_CHN; i++) {
> while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
> /* Wait until all channel transfers are completed */
> msleep(1);
> }
> /* Disable the i2c interrupts */
> pch_disbl_int(&adap_info->pch_data[i]);
> }
> }
>
> cheers, Joe
>
I will resubmit modified patch soon.
Thanks, Ohtake(OKISemi)
^ permalink raw reply [flat|nested] 47+ messages in thread
* RE: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
2010-09-03 3:19 ` Masayuki Ohtak
(?)
(?)
@ 2010-09-03 8:39 ` Linus WALLEIJ
-1 siblings, 0 replies; 47+ messages in thread
From: Linus WALLEIJ @ 2010-09-03 8:39 UTC (permalink / raw)
To: Masayuki Ohtak, Jean Delvare (PC drivers, core),
Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Ralf Baechle, Srinidhi KASAGAR,
linux-i2c, linux-kernel
Cc: yong.y.wang, qi.wang, andrew.chih.howe.khor, arjan,
Tomoya MORINAGA, Arnd Bergmann
[Masayuki]
> We have updated for your comments.
> Please confirm below.
It's really looking good now! :-)
Reviewed-by: Linus Walleij <linus.walleij@stericsson.com>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 47+ messages in thread
* RE: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
[not found] ` <4C80692E.80004-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>
@ 2010-09-03 8:39 ` Linus WALLEIJ
0 siblings, 0 replies; 47+ messages in thread
From: Linus WALLEIJ @ 2010-09-03 8:39 UTC (permalink / raw)
To: Masayuki Ohtak, Jean Delvare (PC drivers, core),
Ben Dooks (embedded platforms),
Crane Cai
Cc: yong.y.wang-ral2JQCrhuEAvxtiuMwx3w,
qi.wang-ral2JQCrhuEAvxtiuMwx3w,
andrew.chih.howe.khor-ral2JQCrhuEAvxtiuMwx3w,
arjan-VuQAYsv1563Yd54FQh9/CA, Tomoya MORINAGA, Arnd Bergmann
[Masayuki]
> We have updated for your comments.
> Please confirm below.
It's really looking good now! :-)
Reviewed-by: Linus Walleij <linus.walleij-0IS4wlFg1OjSUeElwK9/Pw@public.gmane.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-03 8:10 ` Joe Perches
0 siblings, 0 replies; 47+ messages in thread
From: Joe Perches @ 2010-09-03 8:10 UTC (permalink / raw)
To: Masayuki Ohtak
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c, linux-kernel, yong.y.wang, qi.wang,
andrew.chih.howe.khor, arjan, Tomoya MORINAGA, Arnd Bergmann
On Fri, 2010-09-03 at 16:15 +0900, Masayuki Ohtak wrote:
[]
> +#define pch_dbg(adap, fmt, arg...) \
> + dev_dbg(adap->pch_adapter.dev.parent, "%s :"fmt, __func__, ##arg)
> +
> +#define pch_err(adap, fmt, arg...) \
> + dev_err(adap->pch_adapter.dev.parent, "%s :"fmt, __func__, ##arg)
> +
> +#define pch_pci_err(pdev, fmt, arg...) \
> + dev_err(&pdev->dev, "%s :"fmt, __func__, ##arg)
> +#define pch_pci_dbg(pdev, fmt, arg...) \
> + dev_dbg(&pdev->dev, "%s :"fmt, __func__, ##arg)
OK, but it seems careless because the two types
are not uniformly indented, there's a blank line
between pch_dbg and pch_err, and the two pch_pci_<level>
defines are in the reverse order without a blank line
between them.
I think it's better to use separate multiple strings
that are concatentated by the preprocessor like:
"%s :" fmt
not
"%s :"fmt
Almost all code in kernel uses "%s: " to format __func__.
Some use "%s(): ". I think "%s :" is unique.
The rest of the logging messages look good.
Some other comments:
> + if ((pch_wait_for_xfer_complete(adap) == 0) &&
> + (pch_getack(adap) == 0)) {
This would look better as:
if ((pch_wait_for_xfer_complete(adap) == 0) &&
(pch_getack(adap) == 0)) {
> + if ((pch_wait_for_xfer_complete(adap) == 0)
> + && (pch_getack(adap) == 0)) {
Here too.
> + for (i = 0; i < PCH_MAX_CHN; i++) {
> + while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
> + /* Wait until all channel transfers are completed */
> + msleep(1);
> + }
> + /* Disable the i2c interrupts */
> + pch_disbl_int(&adap_info->pch_data[i]);
> + }
Would it be better to disable all possible interrupts first
or do you need to disable them in order?
Something like:
bool *disabled = kzalloc(PCH_MAX_CHN * sizeof(bool), GFP_KERNEL);
/*
* or a static with a memset, or check something
* like pch_is_int_enabled(&adap_info->pch_data[i])
* then remove the else because the kzalloc couldn't fail.
*/
if (disabled) {
bool alldone;
do {
alldone = true;
for (i = 0; i < PCH_MAX_CHN; i++) {
if (!adap_info->pch_data[i].pch_xfer_in_progress &&
!disabled[i])) {
pch_disbl_int(&adap_info->pch_data[i]);
disabled[i] = true;
} else
alldone = false;
}
if (!alldone) {
/* Wait until all channel transfers are completed */
msleep(1);
}
} while (!alldone);
kfree(disabled);
/* remove the else if there's a static etc */
} else {
for (i = 0; i < PCH_MAX_CHN; i++) {
while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
/* Wait until all channel transfers are completed */
msleep(1);
}
/* Disable the i2c interrupts */
pch_disbl_int(&adap_info->pch_data[i]);
}
}
cheers, Joe
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-03 8:10 ` Joe Perches
0 siblings, 0 replies; 47+ messages in thread
From: Joe Perches @ 2010-09-03 8:10 UTC (permalink / raw)
To: Masayuki Ohtak
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
yong.y.wang-ral2JQCrhuEAvxtiuMwx3w,
qi.wang-ral2JQCrhuEAvxtiuMwx3w,
andrew.chih.howe.khor-ral2JQCrhuEAvxtiuMwx3w,
arjan-VuQAYsv1563Yd54FQh9/CA, Tomoya MORINAGA, Arnd Bergmann
On Fri, 2010-09-03 at 16:15 +0900, Masayuki Ohtak wrote:
[]
> +#define pch_dbg(adap, fmt, arg...) \
> + dev_dbg(adap->pch_adapter.dev.parent, "%s :"fmt, __func__, ##arg)
> +
> +#define pch_err(adap, fmt, arg...) \
> + dev_err(adap->pch_adapter.dev.parent, "%s :"fmt, __func__, ##arg)
> +
> +#define pch_pci_err(pdev, fmt, arg...) \
> + dev_err(&pdev->dev, "%s :"fmt, __func__, ##arg)
> +#define pch_pci_dbg(pdev, fmt, arg...) \
> + dev_dbg(&pdev->dev, "%s :"fmt, __func__, ##arg)
OK, but it seems careless because the two types
are not uniformly indented, there's a blank line
between pch_dbg and pch_err, and the two pch_pci_<level>
defines are in the reverse order without a blank line
between them.
I think it's better to use separate multiple strings
that are concatentated by the preprocessor like:
"%s :" fmt
not
"%s :"fmt
Almost all code in kernel uses "%s: " to format __func__.
Some use "%s(): ". I think "%s :" is unique.
The rest of the logging messages look good.
Some other comments:
> + if ((pch_wait_for_xfer_complete(adap) == 0) &&
> + (pch_getack(adap) == 0)) {
This would look better as:
if ((pch_wait_for_xfer_complete(adap) == 0) &&
(pch_getack(adap) == 0)) {
> + if ((pch_wait_for_xfer_complete(adap) == 0)
> + && (pch_getack(adap) == 0)) {
Here too.
> + for (i = 0; i < PCH_MAX_CHN; i++) {
> + while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
> + /* Wait until all channel transfers are completed */
> + msleep(1);
> + }
> + /* Disable the i2c interrupts */
> + pch_disbl_int(&adap_info->pch_data[i]);
> + }
Would it be better to disable all possible interrupts first
or do you need to disable them in order?
Something like:
bool *disabled = kzalloc(PCH_MAX_CHN * sizeof(bool), GFP_KERNEL);
/*
* or a static with a memset, or check something
* like pch_is_int_enabled(&adap_info->pch_data[i])
* then remove the else because the kzalloc couldn't fail.
*/
if (disabled) {
bool alldone;
do {
alldone = true;
for (i = 0; i < PCH_MAX_CHN; i++) {
if (!adap_info->pch_data[i].pch_xfer_in_progress &&
!disabled[i])) {
pch_disbl_int(&adap_info->pch_data[i]);
disabled[i] = true;
} else
alldone = false;
}
if (!alldone) {
/* Wait until all channel transfers are completed */
msleep(1);
}
} while (!alldone);
kfree(disabled);
/* remove the else if there's a static etc */
} else {
for (i = 0; i < PCH_MAX_CHN; i++) {
while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
/* Wait until all channel transfers are completed */
msleep(1);
}
/* Disable the i2c interrupts */
pch_disbl_int(&adap_info->pch_data[i]);
}
}
cheers, Joe
^ permalink raw reply [flat|nested] 47+ messages in thread
* [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-03 7:15 ` Masayuki Ohtak
0 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtak @ 2010-09-03 7:15 UTC (permalink / raw)
To: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c, linux-kernel, joe
Cc: yong.y.wang, qi.wang, andrew.chih.howe.khor, arjan,
Tomoya MORINAGA, Arnd Bergmann, Masayuki Ohtake
Hi Joe,
We have updated for your comments.
Please confirm below.
Thanks, Ohtake(OKISemi)
---
I2C driver of Topcliff PCH
Topcliff PCH is the platform controller hub that is going to be used in
Intel's upcoming general embedded platform. All IO peripherals in
Topcliff PCH are actually devices sitting on AMBA bus.
Topcliff PCH has I2C I/F. Using this I/F, it is able to access system
devices connected to I2C.
Signed-off-by: Masayuki Ohtake <masa-korg@dsn.okisemi.com>
---
drivers/i2c/busses/Kconfig | 18 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-pch.c | 943 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 962 insertions(+), 0 deletions(-)
create mode 100644 drivers/i2c/busses/i2c-pch.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index bceafbf..c5db1e7 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -613,6 +613,24 @@ config I2C_XILINX
This driver can also be built as a module. If so, the module
will be called xilinx_i2c.
+config PCH_I2C
+ tristate "PCH I2C of Intel Topcliff"
+ depends on PCI
+ help
+ This driver is for PCH(Platform controller Hub) I2C of Topcliff which
+ is an IOH(Input/Output Hub) for x86 embedded processor.
+ This driver can access PCH I2C bus device.
+
+config PCH_I2C_CH_COUNT
+ int "PCH I2C the number of channel count"
+ range 1 2
+ depends on PCH_I2C
+ help
+ This driver is for PCH(Platform controller Hub) I2C of Topcliff which
+ is an IOH(Input/Output Hub) for x86 embedded processor.
+ The number of I2C buses/channels supported by the PCH I2C controller.
+ PCH I2C of Topcliff supports only one channel.
+
comment "External I2C/SMBus adapter drivers"
config I2C_PARPORT
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 936880b..aa04135 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
+obj-$(CONFIG_PCH_I2C) += i2c-pch.o
# External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o
diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c
new file mode 100644
index 0000000..f3840bd
--- /dev/null
+++ b/drivers/i2c/busses/i2c-pch.c
@@ -0,0 +1,943 @@
+/*
+ * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/pci.h>
+#include <linux/mutex.h>
+#include <linux/ktime.h>
+
+#define PCH_MAX_CHN CONFIG_PCH_I2C_CH_COUNT /* Maximum I2C channels
+ available */
+#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
+#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
+#define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
+#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
+#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
+
+#define PCH_I2CSADR 0x00 /* I2C slave address register */
+#define PCH_I2CCTL 0x04 /* I2C control register */
+#define PCH_I2CSR 0x08 /* I2C status register */
+#define PCH_I2CDR 0x0C /* I2C data register */
+#define PCH_I2CMON 0x10 /* I2C bus monitor register */
+#define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
+#define PCH_I2CMOD 0x18 /* I2C mode register */
+#define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
+#define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
+#define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
+#define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
+#define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
+#define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
+#define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
+#define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
+#define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
+#define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
+#define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
+#define PCH_I2CTMR 0x48 /* I2C timer register */
+#define PCH_I2CSRST 0xFC /* I2C reset register */
+#define PCH_I2CNF 0xF8 /* I2C noise filter register */
+
+#define BUS_IDLE_TIMEOUT 20
+#define PCH_I2CCTL_I2CMEN 0x0080
+#define TEN_BIT_ADDR_DEFAULT 0xF000
+#define TEN_BIT_ADDR_MASK 0xF0
+#define PCH_START 0x0020
+#define PCH_ESR_START 0x0001
+#define PCH_BUFF_START 0x1
+#define PCH_REPSTART 0x0004
+#define PCH_ACK 0x0008
+#define PCH_GETACK 0x0001
+#define CLR_REG 0x0
+#define I2C_RD 0x1
+#define I2CMCF_BIT 0x0080
+#define I2CMIF_BIT 0x0002
+#define I2CMAL_BIT 0x0010
+#define I2CBMFI_BIT 0x0001
+#define I2CBMAL_BIT 0x0002
+#define I2CBMNA_BIT 0x0004
+#define I2CBMTO_BIT 0x0008
+#define I2CBMIS_BIT 0x0010
+#define I2CESRFI_BIT 0X0001
+#define I2CESRTO_BIT 0x0002
+#define I2CESRFIIE_BIT 0x1
+#define I2CESRTOIE_BIT 0x2
+#define I2CBMDZ_BIT 0x0040
+#define I2CBMAG_BIT 0x0020
+#define I2CMBB_BIT 0x0020
+#define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
+ I2CBMTO_BIT | I2CBMIS_BIT)
+#define I2C_ADDR_MSK 0xFF
+#define I2C_MSB_2B_MSK 0x300
+#define FAST_MODE_CLK 400
+#define FAST_MODE_EN 0x0001
+#define SUB_ADDR_LEN_MAX 4
+#define BUF_LEN_MAX 32
+#define PCH_BUFFER_MODE 0x1
+#define EEPROM_SW_RST_MODE 0x0002
+#define NORMAL_INTR_ENBL 0x0300
+#define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
+#define EEPROM_RST_INTR_DISBL 0x0
+#define BUFFER_MODE_INTR_ENBL 0x001F
+#define BUFFER_MODE_INTR_DISBL 0x0
+#define NORMAL_MODE 0x0
+#define BUFFER_MODE 0x1
+#define EEPROM_SR_MODE 0x2
+#define I2C_TX_MODE 0x0010
+#define PCH_BUF_TX 0xFFF7
+#define PCH_BUF_RD 0x0008
+#define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
+ I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
+#define I2CMAL_EVENT 0x0001
+#define I2CMCF_EVENT 0x0002
+#define I2CBMFI_EVENT 0x0004
+#define I2CBMAL_EVENT 0x0008
+#define I2CBMNA_EVENT 0x0010
+#define I2CBMTO_EVENT 0x0020
+#define I2CBMIS_EVENT 0x0040
+#define I2CESRFI_EVENT 0x0080
+#define I2CESRTO_EVENT 0x0100
+#define PCI_DEVICE_ID_PCH_I2C 0x8817
+
+#define pch_dbg(adap, fmt, arg...) \
+ dev_dbg(adap->pch_adapter.dev.parent, "%s :"fmt, __func__, ##arg)
+
+#define pch_err(adap, fmt, arg...) \
+ dev_err(adap->pch_adapter.dev.parent, "%s :"fmt, __func__, ##arg)
+
+#define pch_pci_err(pdev, fmt, arg...) \
+ dev_err(&pdev->dev, "%s :"fmt, __func__, ##arg)
+#define pch_pci_dbg(pdev, fmt, arg...) \
+ dev_dbg(&pdev->dev, "%s :"fmt, __func__, ##arg)
+
+/**
+ * struct i2c_algo_pch_data - for I2C driver functionalities
+ * @p_adapter_info: stores the reference to adapter_info structure
+ * @pch_adapter: stores the reference to i2c_adapter structure
+ * @pch_base_address: specifies the remapped base address
+ * @pch_buff_mode_en: specifies if buffer mode is enabled
+ * @pch_event_flag: specifies occurrence of interrupt events
+ * @pch_xfer_in_progress: specifies whether the transfer is completed
+ */
+struct i2c_algo_pch_data {
+ struct adapter_info *p_adapter_info;
+ struct i2c_adapter pch_adapter;
+ void __iomem *pch_base_address;
+ int pch_buff_mode_en;
+ u32 pch_event_flag;
+ bool pch_xfer_in_progress;
+};
+
+/**
+ * struct adapter_info - This structure holds the adapter information for the
+ PCH i2c controller
+ * @pch_data: stores a list of i2c_algo_pch_data
+ * @pch_suspended: specifies whether the system is suspended or not
+ * perhaps with more lines and words.
+ *
+ * pch_data has as many elements as maximum I2C channels
+ */
+struct adapter_info {
+ struct i2c_algo_pch_data pch_data[PCH_MAX_CHN];
+ bool pch_suspended;
+};
+
+
+static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
+static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
+static wait_queue_head_t pch_event;
+static DEFINE_MUTEX(pch_mutex);
+
+static struct pci_device_id __devinitdata pch_pcidev_id[] = {
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_I2C)},
+ {0,}
+};
+
+static irqreturn_t pch_handler_ch0(int irq, void *pData);
+static irqreturn_t(*pch_handler_list[PCH_MAX_CHN]) (int irq, void *pData) = {
+ pch_handler_ch0,
+};
+
+static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ u32 val;
+ val = ioread32(addr + offset);
+ val |= bitmask;
+ iowrite32(val, addr + offset);
+}
+
+static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ u32 val;
+ val = ioread32(addr + offset);
+ val &= (~bitmask);
+ iowrite32(val, addr + offset);
+}
+
+/**
+ * pch_init() - hardware initialization of I2C module
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_init(struct i2c_algo_pch_data *adap)
+{
+ u32 pch_i2cbc;
+ u32 pch_i2ctmr;
+ u32 reg_value;
+ void __iomem *p = adap->pch_base_address;
+
+ /* reset I2C controller */
+ iowrite32(0x01, p + PCH_I2CSRST);
+ iowrite32(0x0, p + PCH_I2CSRST);
+ /* Initialize I2C registers */
+ iowrite32(CLR_REG, p + PCH_I2CCTL);
+ iowrite32(CLR_REG, p + PCH_I2CMOD);
+ iowrite32(CLR_REG, p + PCH_I2CBUFFOR);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSLV);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSUB);
+ iowrite32(CLR_REG, p + PCH_I2CBUFMSK);
+ iowrite32(CLR_REG, p + PCH_I2CESRFOR);
+ iowrite32(CLR_REG, p + PCH_I2CESRMSK);
+ iowrite32(0x21, p + PCH_I2CNF);
+
+ reg_value = PCH_I2CCTL_I2CMEN;
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL,
+ PCH_I2CCTL_I2CMEN);
+
+ if (pch_i2c_speed != 400)
+ pch_i2c_speed = 100;
+
+ if (pch_i2c_speed == FAST_MODE_CLK) {
+ reg_value |= FAST_MODE_EN;
+ pch_dbg(adap, "Fast mode enabled\n");
+ }
+
+ if (pch_clk <= 0 || pch_clk > PCH_MAX_CLK)
+ pch_clk = 62500;
+
+ pch_i2cbc = ((pch_clk) + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
+ /* Set transfer speed in I2CBC */
+ iowrite32(pch_i2cbc, p + PCH_I2CBC);
+
+ pch_i2ctmr = (pch_clk) / 8;
+ iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
+
+ reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
+ iowrite32(reg_value, p + PCH_I2CCTL);
+
+ pch_dbg(adap,
+ "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
+ ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
+
+ init_waitqueue_head(&pch_event);
+}
+
+static inline int ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
+{
+ return cmp1.tv64 < cmp2.tv64;
+}
+
+/**
+ * pch_wait_for_bus_idle() - check the status of bus.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ * @timeout: waiting time counter (us).
+ */
+static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
+ s32 timeout)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ /* MAX timeout value is timeout*1000*1000nsec */
+ ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
+ do {
+ if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
+ break;
+ msleep(1);
+ } while (ktime_lt(ktime_get(), ns_val));
+
+ pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
+
+ if (timeout == 0) {
+ pch_err(adap, "return%d\n", -ETIME);
+ return -ETIME;
+ }
+
+ return 0;
+}
+
+/**
+ * pch_start() - Generate I2C start condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ *
+ * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
+ */
+static void pch_start(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+}
+
+/**
+ * pch_wait_for_xfer_complete() - initiates a wait for the tx complete event
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
+{
+ s32 ret;
+ ret = wait_event_interruptible_timeout(pch_event,
+ (adap->pch_event_flag != 0), msecs_to_jiffies(50));
+ if (ret < 0) {
+ pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
+ return ret;
+ }
+
+ if (ret == 0) {
+ pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
+ return -ETIMEDOUT;
+ }
+
+ if (adap->pch_event_flag & I2C_ERROR_MASK) {
+ pch_err(adap, "error bits set: %x\n", adap->pch_event_flag);
+ return -EIO;
+ }
+
+ adap->pch_event_flag = 0;
+ ret = 0;
+
+ return ret;
+}
+
+/**
+ * pch_getack() - to confirm ACK/NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_getack(struct i2c_algo_pch_data *adap)
+{
+ u32 reg_val;
+ void __iomem *p = adap->pch_base_address;
+ reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
+
+ if (reg_val != 0) {
+ pch_err(adap, "return%d\n", -EPROTO);
+ return -EPROTO;
+ }
+
+ return 0;
+}
+
+/**
+ * pch_stop() - generate stop condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_stop(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ /* clear the start bit */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+}
+
+/**
+ * pch_repstart() - generate repeated start condition in normal mode
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_repstart(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_REPSTART);
+}
+
+/**
+ * pch_writebytes() - write data to I2C bus in normal mode
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @last: specifies whether last message or not.
+ * In the case of compound mode it will be 1 for last message,
+ * otherwise 0.
+ * @first: specifies whether first message or not.
+ * 1 for first message otherwise 0.
+ */
+static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+ u8 *buf;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ u32 addr_8_lsb;
+ s32 wrcount;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+ /* enable master tx */
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
+ length);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ addr_8_lsb = (addr & I2C_ADDR_MSK);
+ iowrite32(addr_8_lsb, p + PCH_I2CDR);
+ } else {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } else {
+ /* set 7 bit slave address and R/W bit as 0 */
+ iowrite32(addr << 1, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ }
+
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ for (wrcount = 0; wrcount < length; ++wrcount) {
+ /* write buffer value to I2C data register */
+ iowrite32(buf[wrcount], p + PCH_I2CDR);
+ pch_dbg(adap, "writing %x to Data register\n",
+ buf[wrcount]);
+
+ if (pch_wait_for_xfer_complete(adap) != 0)
+ return -ETIME;
+
+ if (pch_getack(adap))
+ return -ETIME;
+ }
+
+ /* check if this is the last message */
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+ } else {
+ pch_stop(adap);
+ return -EIO;
+ }
+
+ pch_dbg(adap, "return=%d\n", wrcount);
+
+ return wrcount;
+}
+
+/**
+ * pch_sendack() - send ACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+}
+
+/**
+ * pch_sendnack() - send NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendnack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+}
+
+/**
+ * pch_readbytes() - read data from I2C bus in normal mode.
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @last: specifies whether last message or not.
+ * @first: specifies whether first message or not.
+ */
+s32 pch_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ u8 *buf;
+ u32 count;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+
+ /* enable master reception */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+
+ } else {
+ /* 7 address bits + R/W bit */
+ addr = (((addr) << 1) | (I2C_RD));
+ iowrite32(addr, p + PCH_I2CDR);
+ }
+
+ /* check if it is the first message */
+ if (first)
+ pch_start(adap);
+
+ if ((pch_wait_for_xfer_complete(adap) == 0)
+ && (pch_getack(adap) == 0)) {
+ pch_dbg(adap, "return %d\n", 0);
+
+ if (length == 0) {
+ pch_stop(adap);
+ ioread32(p + PCH_I2CDR); /* Dummy read needs */
+
+ count = length;
+ } else {
+ int read_index;
+ int loop;
+ pch_sendack(adap);
+
+ /* Dummy read */
+ for (loop = 1, read_index = 0; loop < length; loop++) {
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (loop != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) != 0) {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } /* end for */
+
+ pch_sendnack(adap);
+
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (length != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) == 0) {
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+
+ buf[read_index++] = ioread32(p + PCH_I2CDR);
+ count = read_index;
+ } else {
+ count = -ETIME;
+ }
+
+ }
+ } else {
+ count = -ETIME;
+ pch_stop(adap);
+ }
+
+ return count;
+}
+
+/**
+ * pch_cb_ch0() - Interrupt handler Call back function
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_cb_ch0(struct i2c_algo_pch_data *adap)
+{
+ u32 sts;
+ void __iomem *p = adap->pch_base_address;
+
+ sts = ioread32(p + PCH_I2CSR);
+ sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
+ if (I2CMAL_BIT & sts)
+ adap->pch_event_flag |= I2CMAL_EVENT;
+
+ if (I2CMCF_BIT & sts)
+ adap->pch_event_flag |= I2CMCF_EVENT;
+
+ /* clear the applicable bits */
+ pch_clrbit((adap->pch_base_address), PCH_I2CSR, sts);
+
+ pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
+
+ wake_up_interruptible(&pch_event);
+}
+
+/**
+ * pch_handler_ch0() - interrupt handler for the PCH I2C controller
+ * @irq: irq number.
+ * @pData: cookie passed back to the handler function.
+ */
+static irqreturn_t pch_handler_ch0(int irq, void *pData)
+{
+ s32 reg_val;
+
+ struct i2c_algo_pch_data *adap_data = (struct i2c_algo_pch_data *)pData;
+ void __iomem *p = adap_data->pch_base_address;
+ u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE);
+
+ if (mode != NORMAL_MODE) {
+ pch_err(adap_data, "I2C mode is not supported\n");
+ return IRQ_NONE;
+ }
+
+ reg_val = ioread32(p + PCH_I2CSR);
+ if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
+ pch_cb_ch0(adap_data);
+ else
+ return IRQ_NONE;
+
+ return IRQ_HANDLED;
+}
+#if 0
+ if (mode == NORMAL_MODE) {
+ reg_val = ioread32(p + PCH_I2CSR);
+ if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
+ pch_cb_ch0(adap_data);
+ else
+ goto err_out;
+ } else {
+ pch_err(adap_data, "I2C mode is not supported\n");
+ goto err_out;
+ }
+ return IRQ_HANDLED;
+
+err_out:
+ return IRQ_NONE;
+}
+#endif
+/**
+ * pch_xfer() - Reading adnd writing data through I2C bus
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @num: number of messages.
+ */
+static s32 pch_xfer(struct i2c_adapter *i2c_adap,
+ struct i2c_msg *msgs, s32 num)
+{
+ struct i2c_msg *pmsg;
+ u32 i;
+ u32 status;
+ u32 msglen;
+ u32 subaddrlen;
+ s32 ret;
+
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ ret = mutex_lock_interruptible(&pch_mutex);
+ if (ret)
+ return -ERESTARTSYS;
+
+ if (adap->p_adapter_info->pch_suspended) {
+ mutex_unlock(&pch_mutex);
+ return -EBUSY;
+ }
+
+ pch_dbg(adap, "adap->p_adapter_info->pch_suspended is %d\n",
+ adap->p_adapter_info->pch_suspended);
+ /* transfer not completed */
+ adap->pch_xfer_in_progress = true;
+
+ for (i = 0; i < num; i++) {
+ pmsg = &msgs[i];
+ pmsg->flags |= adap->pch_buff_mode_en;
+ status = pmsg->flags;
+ pch_dbg(adap,
+ "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
+ /* calculate sub address length and message length */
+ /* these are applicable only for buffer mode */
+ subaddrlen = pmsg->buf[0];
+ /* calculate actual message length excluding
+ * the sub address fields */
+ msglen = (pmsg->len) - (subaddrlen + 1);
+ if (status & (I2C_M_RD)) {
+ pch_dbg(adap, "invoking pch_readbytes\n");
+ ret = pch_readbytes(i2c_adap, pmsg, (i + 1 == num),
+ (i == 0));
+ } else {
+ pch_dbg(adap, "invoking pch_writebytes\n");
+ ret = pch_writebytes(i2c_adap, pmsg, (i + 1 == num),
+ (i == 0));
+ }
+
+ }
+
+ adap->pch_xfer_in_progress = false; /* transfer completed */
+
+ mutex_unlock(&pch_mutex);
+
+ return ret;
+}
+
+/**
+ * pch_func() - return the functionality of the I2C driver
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static u32 pch_func(struct i2c_adapter *adap)
+{
+ u32 ret;
+ ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
+ return ret;
+}
+
+static struct i2c_algorithm pch_algorithm = {
+ .master_xfer = pch_xfer,
+ .functionality = pch_func
+};
+
+/**
+ * pch_disbl_int() - Disable PCH I2C interrupts
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_disbl_int(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL,
+ NORMAL_INTR_ENBL);
+
+ iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
+
+ iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
+}
+
+static int __devinit pch_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ int i;
+ void __iomem *base_addr;
+ s32 ret;
+ struct adapter_info *adap_info =
+ kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
+
+ pch_pci_dbg(pdev, "Entered.\n");
+
+ if (adap_info == NULL) {
+ pch_pci_err(pdev, "Memory allocation FAILED\n");
+ return -ENOMEM;
+ }
+
+ ret = pci_enable_device(pdev);
+ if (ret) {
+ pch_pci_err(pdev, "pci_enable_device FAILED\n");
+ goto err_pci_enable;
+ }
+
+ ret = pci_request_regions(pdev, KBUILD_MODNAME);
+ if (ret) {
+ pch_pci_err(pdev, "pci_request_regions FAILED\n");
+ goto err_pci_req;
+ }
+
+ base_addr = pci_iomap(pdev, 1, 0);
+
+ if (base_addr == 0) {
+ pch_pci_err(pdev, "pci_iomap FAILED\n");
+ ret = -ENOMEM;
+ goto err_pci_iomap;
+ }
+
+ adap_info->pch_suspended = false;
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ adap_info->pch_data[i].p_adapter_info = adap_info;
+
+ adap_info->pch_data[i].pch_adapter.owner = THIS_MODULE;
+ adap_info->pch_data[i].pch_adapter.class = I2C_CLASS_HWMON;
+ strcpy(adap_info->pch_data[i].pch_adapter.name, KBUILD_MODNAME);
+ adap_info->pch_data[i].pch_adapter.algo = &pch_algorithm;
+ adap_info->pch_data[i].pch_adapter.algo_data =
+ &adap_info->pch_data[i];
+
+ /* (i * 0x80) + base_addr; */
+ adap_info->pch_data[i].pch_base_address = base_addr;
+
+ adap_info->pch_data[i].pch_adapter.dev.parent = &pdev->dev;
+
+ ret = i2c_add_adapter(&(adap_info->pch_data[i].pch_adapter));
+
+ if (ret) {
+ pch_pci_err(pdev, "i2c_add_adapter FAILED\n");
+ goto err_i2c_add_adapter;
+ }
+
+ pch_init(&adap_info->pch_data[i]);
+ ret = request_irq(pdev->irq, pch_handler_list[i], IRQF_SHARED,
+ KBUILD_MODNAME, &adap_info->pch_data[i]);
+ if (ret) {
+ pch_pci_err(pdev, "request_irq FAILED\n");
+ goto err_request_irq;
+ }
+ }
+
+ pci_set_drvdata(pdev, adap_info);
+ pch_pci_dbg(pdev, "returns %d.\n", ret);
+ return 0;
+
+err_request_irq:
+ for (i = 0; i < PCH_MAX_CHN; i++)
+ i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
+err_i2c_add_adapter:
+ pci_iounmap(pdev, base_addr);
+err_pci_iomap:
+ pci_release_regions(pdev);
+err_pci_req:
+ pci_disable_device(pdev);
+err_pci_enable:
+ kfree(adap_info);
+ return ret;
+}
+
+static void __devexit pch_remove(struct pci_dev *pdev)
+{
+ int i;
+
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ pch_disbl_int(&adap_info->pch_data[i]);
+ free_irq(pdev->irq, &adap_info->pch_data[i]);
+ i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
+ }
+
+ if (adap_info->pch_data[0].pch_base_address) {
+ pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
+ adap_info->pch_data[0].pch_base_address = 0;
+ }
+
+ pci_set_drvdata(pdev, NULL);
+
+ pci_release_regions(pdev);
+
+ pci_disable_device(pdev);
+ kfree(adap_info);
+}
+
+#ifdef CONFIG_PM
+static int pch_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ int i;
+ int ret;
+
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+ void __iomem *p = adap_info->pch_data[0].pch_base_address;
+
+ adap_info->pch_suspended = true;
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
+ /* Wait until all channel transfers are completed */
+ msleep(1);
+ }
+ /* Disable the i2c interrupts */
+ pch_disbl_int(&adap_info->pch_data[i]);
+ }
+
+ pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
+ "invoked function pch_disbl_int successfully\n",
+ ioread32(p + 0x08), ioread32(p + 0x30), ioread32(p + 0x44));
+
+ ret = pci_save_state(pdev);
+
+ if (ret) {
+ pch_pci_err(pdev, "pci_save_state\n");
+ return ret;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+ pci_disable_device(pdev);
+ pci_set_power_state(pdev, pci_choose_state(pdev, state));
+
+ return 0;
+}
+
+static int pch_resume(struct pci_dev *pdev)
+{
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+ int i;
+
+ pci_set_power_state(pdev, PCI_D0);
+ pci_restore_state(pdev);
+
+ if (pci_enable_device(pdev) < 0) {
+ pch_pci_err(pdev, "pci_enable_device FAILED in pch_resume\n");
+ return -EIO;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+
+ for (i = 0; i < PCH_MAX_CHN; i++)
+ pch_init(&adap_info->pch_data[i]);
+
+ adap_info->pch_suspended = false;
+
+ return 0;
+}
+#else
+#define pch_suspend NULL
+#define pch_resume NULL
+#endif
+
+static struct pci_driver pch_pcidriver = {
+ .name = KBUILD_MODNAME,
+ .id_table = pch_pcidev_id,
+ .probe = pch_probe,
+ .remove = __devexit_p(pch_remove),
+ .suspend = pch_suspend,
+ .resume = pch_resume
+};
+
+static int __init pch_pci_init(void)
+{
+ return pci_register_driver(&pch_pcidriver);
+}
+
+static void __exit pch_pci_exit(void)
+{
+ pci_unregister_driver(&pch_pcidriver);
+}
+
+MODULE_DESCRIPTION("PCH I2C PCI Driver");
+MODULE_LICENSE("GPL");
+module_init(pch_pci_init);
+module_exit(pch_pci_exit);
+module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
+module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
--
1.6.0.6
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-03 7:15 ` Masayuki Ohtak
0 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtak @ 2010-09-03 7:15 UTC (permalink / raw)
To: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz
Cc: yong.y.wang-ral2JQCrhuEAvxtiuMwx3w,
qi.wang-ral2JQCrhuEAvxtiuMwx3w,
andrew.chih.howe.khor-ral2JQCrhuEAvxtiuMwx3w,
arjan-VuQAYsv1563Yd54FQh9/CA, Tomoya MORINAGA, Arnd Bergmann,
Masayuki Ohtake
Hi Joe,
We have updated for your comments.
Please confirm below.
Thanks, Ohtake(OKISemi)
---
I2C driver of Topcliff PCH
Topcliff PCH is the platform controller hub that is going to be used in
Intel's upcoming general embedded platform. All IO peripherals in
Topcliff PCH are actually devices sitting on AMBA bus.
Topcliff PCH has I2C I/F. Using this I/F, it is able to access system
devices connected to I2C.
Signed-off-by: Masayuki Ohtake <masa-korg-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>
---
drivers/i2c/busses/Kconfig | 18 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-pch.c | 943 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 962 insertions(+), 0 deletions(-)
create mode 100644 drivers/i2c/busses/i2c-pch.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index bceafbf..c5db1e7 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -613,6 +613,24 @@ config I2C_XILINX
This driver can also be built as a module. If so, the module
will be called xilinx_i2c.
+config PCH_I2C
+ tristate "PCH I2C of Intel Topcliff"
+ depends on PCI
+ help
+ This driver is for PCH(Platform controller Hub) I2C of Topcliff which
+ is an IOH(Input/Output Hub) for x86 embedded processor.
+ This driver can access PCH I2C bus device.
+
+config PCH_I2C_CH_COUNT
+ int "PCH I2C the number of channel count"
+ range 1 2
+ depends on PCH_I2C
+ help
+ This driver is for PCH(Platform controller Hub) I2C of Topcliff which
+ is an IOH(Input/Output Hub) for x86 embedded processor.
+ The number of I2C buses/channels supported by the PCH I2C controller.
+ PCH I2C of Topcliff supports only one channel.
+
comment "External I2C/SMBus adapter drivers"
config I2C_PARPORT
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 936880b..aa04135 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
+obj-$(CONFIG_PCH_I2C) += i2c-pch.o
# External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o
diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c
new file mode 100644
index 0000000..f3840bd
--- /dev/null
+++ b/drivers/i2c/busses/i2c-pch.c
@@ -0,0 +1,943 @@
+/*
+ * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/pci.h>
+#include <linux/mutex.h>
+#include <linux/ktime.h>
+
+#define PCH_MAX_CHN CONFIG_PCH_I2C_CH_COUNT /* Maximum I2C channels
+ available */
+#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
+#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
+#define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
+#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
+#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
+
+#define PCH_I2CSADR 0x00 /* I2C slave address register */
+#define PCH_I2CCTL 0x04 /* I2C control register */
+#define PCH_I2CSR 0x08 /* I2C status register */
+#define PCH_I2CDR 0x0C /* I2C data register */
+#define PCH_I2CMON 0x10 /* I2C bus monitor register */
+#define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
+#define PCH_I2CMOD 0x18 /* I2C mode register */
+#define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
+#define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
+#define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
+#define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
+#define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
+#define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
+#define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
+#define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
+#define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
+#define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
+#define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
+#define PCH_I2CTMR 0x48 /* I2C timer register */
+#define PCH_I2CSRST 0xFC /* I2C reset register */
+#define PCH_I2CNF 0xF8 /* I2C noise filter register */
+
+#define BUS_IDLE_TIMEOUT 20
+#define PCH_I2CCTL_I2CMEN 0x0080
+#define TEN_BIT_ADDR_DEFAULT 0xF000
+#define TEN_BIT_ADDR_MASK 0xF0
+#define PCH_START 0x0020
+#define PCH_ESR_START 0x0001
+#define PCH_BUFF_START 0x1
+#define PCH_REPSTART 0x0004
+#define PCH_ACK 0x0008
+#define PCH_GETACK 0x0001
+#define CLR_REG 0x0
+#define I2C_RD 0x1
+#define I2CMCF_BIT 0x0080
+#define I2CMIF_BIT 0x0002
+#define I2CMAL_BIT 0x0010
+#define I2CBMFI_BIT 0x0001
+#define I2CBMAL_BIT 0x0002
+#define I2CBMNA_BIT 0x0004
+#define I2CBMTO_BIT 0x0008
+#define I2CBMIS_BIT 0x0010
+#define I2CESRFI_BIT 0X0001
+#define I2CESRTO_BIT 0x0002
+#define I2CESRFIIE_BIT 0x1
+#define I2CESRTOIE_BIT 0x2
+#define I2CBMDZ_BIT 0x0040
+#define I2CBMAG_BIT 0x0020
+#define I2CMBB_BIT 0x0020
+#define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
+ I2CBMTO_BIT | I2CBMIS_BIT)
+#define I2C_ADDR_MSK 0xFF
+#define I2C_MSB_2B_MSK 0x300
+#define FAST_MODE_CLK 400
+#define FAST_MODE_EN 0x0001
+#define SUB_ADDR_LEN_MAX 4
+#define BUF_LEN_MAX 32
+#define PCH_BUFFER_MODE 0x1
+#define EEPROM_SW_RST_MODE 0x0002
+#define NORMAL_INTR_ENBL 0x0300
+#define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
+#define EEPROM_RST_INTR_DISBL 0x0
+#define BUFFER_MODE_INTR_ENBL 0x001F
+#define BUFFER_MODE_INTR_DISBL 0x0
+#define NORMAL_MODE 0x0
+#define BUFFER_MODE 0x1
+#define EEPROM_SR_MODE 0x2
+#define I2C_TX_MODE 0x0010
+#define PCH_BUF_TX 0xFFF7
+#define PCH_BUF_RD 0x0008
+#define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
+ I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
+#define I2CMAL_EVENT 0x0001
+#define I2CMCF_EVENT 0x0002
+#define I2CBMFI_EVENT 0x0004
+#define I2CBMAL_EVENT 0x0008
+#define I2CBMNA_EVENT 0x0010
+#define I2CBMTO_EVENT 0x0020
+#define I2CBMIS_EVENT 0x0040
+#define I2CESRFI_EVENT 0x0080
+#define I2CESRTO_EVENT 0x0100
+#define PCI_DEVICE_ID_PCH_I2C 0x8817
+
+#define pch_dbg(adap, fmt, arg...) \
+ dev_dbg(adap->pch_adapter.dev.parent, "%s :"fmt, __func__, ##arg)
+
+#define pch_err(adap, fmt, arg...) \
+ dev_err(adap->pch_adapter.dev.parent, "%s :"fmt, __func__, ##arg)
+
+#define pch_pci_err(pdev, fmt, arg...) \
+ dev_err(&pdev->dev, "%s :"fmt, __func__, ##arg)
+#define pch_pci_dbg(pdev, fmt, arg...) \
+ dev_dbg(&pdev->dev, "%s :"fmt, __func__, ##arg)
+
+/**
+ * struct i2c_algo_pch_data - for I2C driver functionalities
+ * @p_adapter_info: stores the reference to adapter_info structure
+ * @pch_adapter: stores the reference to i2c_adapter structure
+ * @pch_base_address: specifies the remapped base address
+ * @pch_buff_mode_en: specifies if buffer mode is enabled
+ * @pch_event_flag: specifies occurrence of interrupt events
+ * @pch_xfer_in_progress: specifies whether the transfer is completed
+ */
+struct i2c_algo_pch_data {
+ struct adapter_info *p_adapter_info;
+ struct i2c_adapter pch_adapter;
+ void __iomem *pch_base_address;
+ int pch_buff_mode_en;
+ u32 pch_event_flag;
+ bool pch_xfer_in_progress;
+};
+
+/**
+ * struct adapter_info - This structure holds the adapter information for the
+ PCH i2c controller
+ * @pch_data: stores a list of i2c_algo_pch_data
+ * @pch_suspended: specifies whether the system is suspended or not
+ * perhaps with more lines and words.
+ *
+ * pch_data has as many elements as maximum I2C channels
+ */
+struct adapter_info {
+ struct i2c_algo_pch_data pch_data[PCH_MAX_CHN];
+ bool pch_suspended;
+};
+
+
+static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
+static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
+static wait_queue_head_t pch_event;
+static DEFINE_MUTEX(pch_mutex);
+
+static struct pci_device_id __devinitdata pch_pcidev_id[] = {
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_I2C)},
+ {0,}
+};
+
+static irqreturn_t pch_handler_ch0(int irq, void *pData);
+static irqreturn_t(*pch_handler_list[PCH_MAX_CHN]) (int irq, void *pData) = {
+ pch_handler_ch0,
+};
+
+static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ u32 val;
+ val = ioread32(addr + offset);
+ val |= bitmask;
+ iowrite32(val, addr + offset);
+}
+
+static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ u32 val;
+ val = ioread32(addr + offset);
+ val &= (~bitmask);
+ iowrite32(val, addr + offset);
+}
+
+/**
+ * pch_init() - hardware initialization of I2C module
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_init(struct i2c_algo_pch_data *adap)
+{
+ u32 pch_i2cbc;
+ u32 pch_i2ctmr;
+ u32 reg_value;
+ void __iomem *p = adap->pch_base_address;
+
+ /* reset I2C controller */
+ iowrite32(0x01, p + PCH_I2CSRST);
+ iowrite32(0x0, p + PCH_I2CSRST);
+ /* Initialize I2C registers */
+ iowrite32(CLR_REG, p + PCH_I2CCTL);
+ iowrite32(CLR_REG, p + PCH_I2CMOD);
+ iowrite32(CLR_REG, p + PCH_I2CBUFFOR);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSLV);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSUB);
+ iowrite32(CLR_REG, p + PCH_I2CBUFMSK);
+ iowrite32(CLR_REG, p + PCH_I2CESRFOR);
+ iowrite32(CLR_REG, p + PCH_I2CESRMSK);
+ iowrite32(0x21, p + PCH_I2CNF);
+
+ reg_value = PCH_I2CCTL_I2CMEN;
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL,
+ PCH_I2CCTL_I2CMEN);
+
+ if (pch_i2c_speed != 400)
+ pch_i2c_speed = 100;
+
+ if (pch_i2c_speed == FAST_MODE_CLK) {
+ reg_value |= FAST_MODE_EN;
+ pch_dbg(adap, "Fast mode enabled\n");
+ }
+
+ if (pch_clk <= 0 || pch_clk > PCH_MAX_CLK)
+ pch_clk = 62500;
+
+ pch_i2cbc = ((pch_clk) + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
+ /* Set transfer speed in I2CBC */
+ iowrite32(pch_i2cbc, p + PCH_I2CBC);
+
+ pch_i2ctmr = (pch_clk) / 8;
+ iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
+
+ reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
+ iowrite32(reg_value, p + PCH_I2CCTL);
+
+ pch_dbg(adap,
+ "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
+ ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
+
+ init_waitqueue_head(&pch_event);
+}
+
+static inline int ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
+{
+ return cmp1.tv64 < cmp2.tv64;
+}
+
+/**
+ * pch_wait_for_bus_idle() - check the status of bus.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ * @timeout: waiting time counter (us).
+ */
+static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
+ s32 timeout)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ /* MAX timeout value is timeout*1000*1000nsec */
+ ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
+ do {
+ if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
+ break;
+ msleep(1);
+ } while (ktime_lt(ktime_get(), ns_val));
+
+ pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
+
+ if (timeout == 0) {
+ pch_err(adap, "return%d\n", -ETIME);
+ return -ETIME;
+ }
+
+ return 0;
+}
+
+/**
+ * pch_start() - Generate I2C start condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ *
+ * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
+ */
+static void pch_start(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+}
+
+/**
+ * pch_wait_for_xfer_complete() - initiates a wait for the tx complete event
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
+{
+ s32 ret;
+ ret = wait_event_interruptible_timeout(pch_event,
+ (adap->pch_event_flag != 0), msecs_to_jiffies(50));
+ if (ret < 0) {
+ pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
+ return ret;
+ }
+
+ if (ret == 0) {
+ pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
+ return -ETIMEDOUT;
+ }
+
+ if (adap->pch_event_flag & I2C_ERROR_MASK) {
+ pch_err(adap, "error bits set: %x\n", adap->pch_event_flag);
+ return -EIO;
+ }
+
+ adap->pch_event_flag = 0;
+ ret = 0;
+
+ return ret;
+}
+
+/**
+ * pch_getack() - to confirm ACK/NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_getack(struct i2c_algo_pch_data *adap)
+{
+ u32 reg_val;
+ void __iomem *p = adap->pch_base_address;
+ reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
+
+ if (reg_val != 0) {
+ pch_err(adap, "return%d\n", -EPROTO);
+ return -EPROTO;
+ }
+
+ return 0;
+}
+
+/**
+ * pch_stop() - generate stop condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_stop(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ /* clear the start bit */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+}
+
+/**
+ * pch_repstart() - generate repeated start condition in normal mode
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_repstart(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_REPSTART);
+}
+
+/**
+ * pch_writebytes() - write data to I2C bus in normal mode
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @last: specifies whether last message or not.
+ * In the case of compound mode it will be 1 for last message,
+ * otherwise 0.
+ * @first: specifies whether first message or not.
+ * 1 for first message otherwise 0.
+ */
+static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+ u8 *buf;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ u32 addr_8_lsb;
+ s32 wrcount;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+ /* enable master tx */
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
+ length);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ addr_8_lsb = (addr & I2C_ADDR_MSK);
+ iowrite32(addr_8_lsb, p + PCH_I2CDR);
+ } else {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } else {
+ /* set 7 bit slave address and R/W bit as 0 */
+ iowrite32(addr << 1, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ }
+
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ for (wrcount = 0; wrcount < length; ++wrcount) {
+ /* write buffer value to I2C data register */
+ iowrite32(buf[wrcount], p + PCH_I2CDR);
+ pch_dbg(adap, "writing %x to Data register\n",
+ buf[wrcount]);
+
+ if (pch_wait_for_xfer_complete(adap) != 0)
+ return -ETIME;
+
+ if (pch_getack(adap))
+ return -ETIME;
+ }
+
+ /* check if this is the last message */
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+ } else {
+ pch_stop(adap);
+ return -EIO;
+ }
+
+ pch_dbg(adap, "return=%d\n", wrcount);
+
+ return wrcount;
+}
+
+/**
+ * pch_sendack() - send ACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+}
+
+/**
+ * pch_sendnack() - send NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendnack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+}
+
+/**
+ * pch_readbytes() - read data from I2C bus in normal mode.
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @last: specifies whether last message or not.
+ * @first: specifies whether first message or not.
+ */
+s32 pch_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ u8 *buf;
+ u32 count;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+
+ /* enable master reception */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+
+ } else {
+ /* 7 address bits + R/W bit */
+ addr = (((addr) << 1) | (I2C_RD));
+ iowrite32(addr, p + PCH_I2CDR);
+ }
+
+ /* check if it is the first message */
+ if (first)
+ pch_start(adap);
+
+ if ((pch_wait_for_xfer_complete(adap) == 0)
+ && (pch_getack(adap) == 0)) {
+ pch_dbg(adap, "return %d\n", 0);
+
+ if (length == 0) {
+ pch_stop(adap);
+ ioread32(p + PCH_I2CDR); /* Dummy read needs */
+
+ count = length;
+ } else {
+ int read_index;
+ int loop;
+ pch_sendack(adap);
+
+ /* Dummy read */
+ for (loop = 1, read_index = 0; loop < length; loop++) {
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (loop != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) != 0) {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } /* end for */
+
+ pch_sendnack(adap);
+
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (length != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) == 0) {
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+
+ buf[read_index++] = ioread32(p + PCH_I2CDR);
+ count = read_index;
+ } else {
+ count = -ETIME;
+ }
+
+ }
+ } else {
+ count = -ETIME;
+ pch_stop(adap);
+ }
+
+ return count;
+}
+
+/**
+ * pch_cb_ch0() - Interrupt handler Call back function
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_cb_ch0(struct i2c_algo_pch_data *adap)
+{
+ u32 sts;
+ void __iomem *p = adap->pch_base_address;
+
+ sts = ioread32(p + PCH_I2CSR);
+ sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
+ if (I2CMAL_BIT & sts)
+ adap->pch_event_flag |= I2CMAL_EVENT;
+
+ if (I2CMCF_BIT & sts)
+ adap->pch_event_flag |= I2CMCF_EVENT;
+
+ /* clear the applicable bits */
+ pch_clrbit((adap->pch_base_address), PCH_I2CSR, sts);
+
+ pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
+
+ wake_up_interruptible(&pch_event);
+}
+
+/**
+ * pch_handler_ch0() - interrupt handler for the PCH I2C controller
+ * @irq: irq number.
+ * @pData: cookie passed back to the handler function.
+ */
+static irqreturn_t pch_handler_ch0(int irq, void *pData)
+{
+ s32 reg_val;
+
+ struct i2c_algo_pch_data *adap_data = (struct i2c_algo_pch_data *)pData;
+ void __iomem *p = adap_data->pch_base_address;
+ u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE);
+
+ if (mode != NORMAL_MODE) {
+ pch_err(adap_data, "I2C mode is not supported\n");
+ return IRQ_NONE;
+ }
+
+ reg_val = ioread32(p + PCH_I2CSR);
+ if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
+ pch_cb_ch0(adap_data);
+ else
+ return IRQ_NONE;
+
+ return IRQ_HANDLED;
+}
+#if 0
+ if (mode == NORMAL_MODE) {
+ reg_val = ioread32(p + PCH_I2CSR);
+ if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
+ pch_cb_ch0(adap_data);
+ else
+ goto err_out;
+ } else {
+ pch_err(adap_data, "I2C mode is not supported\n");
+ goto err_out;
+ }
+ return IRQ_HANDLED;
+
+err_out:
+ return IRQ_NONE;
+}
+#endif
+/**
+ * pch_xfer() - Reading adnd writing data through I2C bus
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @num: number of messages.
+ */
+static s32 pch_xfer(struct i2c_adapter *i2c_adap,
+ struct i2c_msg *msgs, s32 num)
+{
+ struct i2c_msg *pmsg;
+ u32 i;
+ u32 status;
+ u32 msglen;
+ u32 subaddrlen;
+ s32 ret;
+
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ ret = mutex_lock_interruptible(&pch_mutex);
+ if (ret)
+ return -ERESTARTSYS;
+
+ if (adap->p_adapter_info->pch_suspended) {
+ mutex_unlock(&pch_mutex);
+ return -EBUSY;
+ }
+
+ pch_dbg(adap, "adap->p_adapter_info->pch_suspended is %d\n",
+ adap->p_adapter_info->pch_suspended);
+ /* transfer not completed */
+ adap->pch_xfer_in_progress = true;
+
+ for (i = 0; i < num; i++) {
+ pmsg = &msgs[i];
+ pmsg->flags |= adap->pch_buff_mode_en;
+ status = pmsg->flags;
+ pch_dbg(adap,
+ "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
+ /* calculate sub address length and message length */
+ /* these are applicable only for buffer mode */
+ subaddrlen = pmsg->buf[0];
+ /* calculate actual message length excluding
+ * the sub address fields */
+ msglen = (pmsg->len) - (subaddrlen + 1);
+ if (status & (I2C_M_RD)) {
+ pch_dbg(adap, "invoking pch_readbytes\n");
+ ret = pch_readbytes(i2c_adap, pmsg, (i + 1 == num),
+ (i == 0));
+ } else {
+ pch_dbg(adap, "invoking pch_writebytes\n");
+ ret = pch_writebytes(i2c_adap, pmsg, (i + 1 == num),
+ (i == 0));
+ }
+
+ }
+
+ adap->pch_xfer_in_progress = false; /* transfer completed */
+
+ mutex_unlock(&pch_mutex);
+
+ return ret;
+}
+
+/**
+ * pch_func() - return the functionality of the I2C driver
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static u32 pch_func(struct i2c_adapter *adap)
+{
+ u32 ret;
+ ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
+ return ret;
+}
+
+static struct i2c_algorithm pch_algorithm = {
+ .master_xfer = pch_xfer,
+ .functionality = pch_func
+};
+
+/**
+ * pch_disbl_int() - Disable PCH I2C interrupts
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_disbl_int(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL,
+ NORMAL_INTR_ENBL);
+
+ iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
+
+ iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
+}
+
+static int __devinit pch_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ int i;
+ void __iomem *base_addr;
+ s32 ret;
+ struct adapter_info *adap_info =
+ kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
+
+ pch_pci_dbg(pdev, "Entered.\n");
+
+ if (adap_info == NULL) {
+ pch_pci_err(pdev, "Memory allocation FAILED\n");
+ return -ENOMEM;
+ }
+
+ ret = pci_enable_device(pdev);
+ if (ret) {
+ pch_pci_err(pdev, "pci_enable_device FAILED\n");
+ goto err_pci_enable;
+ }
+
+ ret = pci_request_regions(pdev, KBUILD_MODNAME);
+ if (ret) {
+ pch_pci_err(pdev, "pci_request_regions FAILED\n");
+ goto err_pci_req;
+ }
+
+ base_addr = pci_iomap(pdev, 1, 0);
+
+ if (base_addr == 0) {
+ pch_pci_err(pdev, "pci_iomap FAILED\n");
+ ret = -ENOMEM;
+ goto err_pci_iomap;
+ }
+
+ adap_info->pch_suspended = false;
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ adap_info->pch_data[i].p_adapter_info = adap_info;
+
+ adap_info->pch_data[i].pch_adapter.owner = THIS_MODULE;
+ adap_info->pch_data[i].pch_adapter.class = I2C_CLASS_HWMON;
+ strcpy(adap_info->pch_data[i].pch_adapter.name, KBUILD_MODNAME);
+ adap_info->pch_data[i].pch_adapter.algo = &pch_algorithm;
+ adap_info->pch_data[i].pch_adapter.algo_data =
+ &adap_info->pch_data[i];
+
+ /* (i * 0x80) + base_addr; */
+ adap_info->pch_data[i].pch_base_address = base_addr;
+
+ adap_info->pch_data[i].pch_adapter.dev.parent = &pdev->dev;
+
+ ret = i2c_add_adapter(&(adap_info->pch_data[i].pch_adapter));
+
+ if (ret) {
+ pch_pci_err(pdev, "i2c_add_adapter FAILED\n");
+ goto err_i2c_add_adapter;
+ }
+
+ pch_init(&adap_info->pch_data[i]);
+ ret = request_irq(pdev->irq, pch_handler_list[i], IRQF_SHARED,
+ KBUILD_MODNAME, &adap_info->pch_data[i]);
+ if (ret) {
+ pch_pci_err(pdev, "request_irq FAILED\n");
+ goto err_request_irq;
+ }
+ }
+
+ pci_set_drvdata(pdev, adap_info);
+ pch_pci_dbg(pdev, "returns %d.\n", ret);
+ return 0;
+
+err_request_irq:
+ for (i = 0; i < PCH_MAX_CHN; i++)
+ i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
+err_i2c_add_adapter:
+ pci_iounmap(pdev, base_addr);
+err_pci_iomap:
+ pci_release_regions(pdev);
+err_pci_req:
+ pci_disable_device(pdev);
+err_pci_enable:
+ kfree(adap_info);
+ return ret;
+}
+
+static void __devexit pch_remove(struct pci_dev *pdev)
+{
+ int i;
+
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ pch_disbl_int(&adap_info->pch_data[i]);
+ free_irq(pdev->irq, &adap_info->pch_data[i]);
+ i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
+ }
+
+ if (adap_info->pch_data[0].pch_base_address) {
+ pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
+ adap_info->pch_data[0].pch_base_address = 0;
+ }
+
+ pci_set_drvdata(pdev, NULL);
+
+ pci_release_regions(pdev);
+
+ pci_disable_device(pdev);
+ kfree(adap_info);
+}
+
+#ifdef CONFIG_PM
+static int pch_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ int i;
+ int ret;
+
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+ void __iomem *p = adap_info->pch_data[0].pch_base_address;
+
+ adap_info->pch_suspended = true;
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
+ /* Wait until all channel transfers are completed */
+ msleep(1);
+ }
+ /* Disable the i2c interrupts */
+ pch_disbl_int(&adap_info->pch_data[i]);
+ }
+
+ pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
+ "invoked function pch_disbl_int successfully\n",
+ ioread32(p + 0x08), ioread32(p + 0x30), ioread32(p + 0x44));
+
+ ret = pci_save_state(pdev);
+
+ if (ret) {
+ pch_pci_err(pdev, "pci_save_state\n");
+ return ret;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+ pci_disable_device(pdev);
+ pci_set_power_state(pdev, pci_choose_state(pdev, state));
+
+ return 0;
+}
+
+static int pch_resume(struct pci_dev *pdev)
+{
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+ int i;
+
+ pci_set_power_state(pdev, PCI_D0);
+ pci_restore_state(pdev);
+
+ if (pci_enable_device(pdev) < 0) {
+ pch_pci_err(pdev, "pci_enable_device FAILED in pch_resume\n");
+ return -EIO;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+
+ for (i = 0; i < PCH_MAX_CHN; i++)
+ pch_init(&adap_info->pch_data[i]);
+
+ adap_info->pch_suspended = false;
+
+ return 0;
+}
+#else
+#define pch_suspend NULL
+#define pch_resume NULL
+#endif
+
+static struct pci_driver pch_pcidriver = {
+ .name = KBUILD_MODNAME,
+ .id_table = pch_pcidev_id,
+ .probe = pch_probe,
+ .remove = __devexit_p(pch_remove),
+ .suspend = pch_suspend,
+ .resume = pch_resume
+};
+
+static int __init pch_pci_init(void)
+{
+ return pci_register_driver(&pch_pcidriver);
+}
+
+static void __exit pch_pci_exit(void)
+{
+ pci_unregister_driver(&pch_pcidriver);
+}
+
+MODULE_DESCRIPTION("PCH I2C PCI Driver");
+MODULE_LICENSE("GPL");
+module_init(pch_pci_init);
+module_exit(pch_pci_exit);
+module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
+module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
--
1.6.0.6
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
[not found] ` <4C80692E.80004-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>
@ 2010-09-03 4:38 ` Joe Perches
0 siblings, 0 replies; 47+ messages in thread
From: Joe Perches @ 2010-09-03 4:38 UTC (permalink / raw)
To: Masayuki Ohtak
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c, linux-kernel, yong.y.wang, qi.wang,
andrew.chih.howe.khor, arjan, Tomoya MORINAGA, Arnd Bergmann
I suggest these logging message changes and bug fixes:
Add pch_pci_dbg.
Rename 1st argument to pch_pci_dbg to pdev.
Add trailing "\n" to formats missing them.
Add "%s:" fmt, __func__, args to pch_<level> and pch_pci_<level>
logging macros.
Remove __func__ and inconsistent use of "%s : " and "%s:" prefix
from logging macro uses.
Fix misspelling of Enterred to Entered.
Use "FAILED" consistently.
There's an odd use that is still questionable:
pch_pci_dbg(pdev, "request_irq returns %d pch_probe returns\n", ret);
Signed-off-by: Joe Perches <joe@perches.com>
---
drivers/i2c/busses/i2c-pch.c | 103 ++++++++++++++++++++----------------------
1 files changed, 49 insertions(+), 54 deletions(-)
diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c
index 0933e63..f5bb140 100644
--- a/drivers/i2c/busses/i2c-pch.c
+++ b/drivers/i2c/busses/i2c-pch.c
@@ -121,13 +121,15 @@
#define I2CESRTO_EVENT 0x0100
#define PCI_DEVICE_ID_PCH_I2C 0x8817
-#define pch_dbg(adap, fmt, arg...) \
- dev_dbg(adap->pch_adapter.dev.parent, fmt, ##arg)
+#define pch_dbg(adap, fmt, arg...) \
+ dev_dbg(adap->pch_adapter.dev.parent, "%s: " fmt, __func__, ##arg)
+#define pch_err(adap, fmt, arg...) \
+ dev_err(adap->pch_adapter.dev.parent, "%s: " fmt, __func__, ##arg)
-#define pch_err(adap, fmt, arg...) \
- dev_err(adap->pch_adapter.dev.parent, fmt, ##arg)
-
-#define pch_pci_err(adap, fmt, arg...) dev_err(&adap->dev, fmt, ##arg)
+#define pch_pci_dbg(pdev, fmt, arg...) \
+ dev_dbg(&pdev->dev, "%s: " fmt, __func__, ##arg)
+#define pch_pci_err(pdev, fmt, arg...) \
+ dev_err(&pdev->dev, "%s: " fmt, __func__, ##arg)
/**
* struct i2c_algo_pch_data - for I2C driver functionalities
@@ -243,9 +245,8 @@ static void pch_init(struct i2c_algo_pch_data *adap)
reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
iowrite32(reg_value, p + PCH_I2CCTL);
- pch_dbg(adap,
- "%s: I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
- __func__, ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
+ pch_dbg(adap, "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
+ ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
init_waitqueue_head(&pch_event);
}
@@ -273,10 +274,10 @@ static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
msleep(1);
} while (ktime_lt(ktime_get(), ns_val));
- pch_dbg(adap, "%s : I2CSR = %x\n", __func__, ioread32(p + PCH_I2CSR));
+ pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
if (timeout == 0) {
- pch_err(adap, "%s :return%d\n", __func__, -ETIME);
+ pch_err(adap, "return: %d\n", -ETIME);
return -ETIME;
}
@@ -292,8 +293,7 @@ static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
static void pch_start(struct i2c_algo_pch_data *adap)
{
void __iomem *p = adap->pch_base_address;
- pch_dbg(adap, "In %s : I2CCTL = %x\n",
- __func__, ioread32(p + PCH_I2CCTL));
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
}
@@ -307,20 +307,17 @@ static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
ret = wait_event_interruptible_timeout(pch_event,
(adap->pch_event_flag != 0), msecs_to_jiffies(50));
if (ret < 0) {
- pch_err(adap, "%s :timeout: %x\n",
- __func__, adap->pch_event_flag);
+ pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
return ret;
}
if (ret == 0) {
- pch_err(adap, "%s :timeout: %x\n",
- __func__, adap->pch_event_flag);
+ pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
return -ETIMEDOUT;
}
if (adap->pch_event_flag & I2C_ERROR_MASK) {
- pch_err(adap, "%s :error bits set: %x\n",
- __func__, adap->pch_event_flag);
+ pch_err(adap, "error bits set: %x\n", adap->pch_event_flag);
return -EIO;
}
@@ -341,7 +338,7 @@ static s32 pch_getack(struct i2c_algo_pch_data *adap)
reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
if (reg_val != 0) {
- pch_err(adap, "%s : return%d\n", __func__, -EPROTO);
+ pch_err(adap, "return: %d\n", -EPROTO);
return -EPROTO;
}
@@ -355,7 +352,7 @@ static s32 pch_getack(struct i2c_algo_pch_data *adap)
static void pch_stop(struct i2c_algo_pch_data *adap)
{
void __iomem *p = adap->pch_base_address;
- pch_dbg(adap, "%s : I2CCTL = %x\n", __func__, ioread32(p + PCH_I2CCTL));
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
/* clear the start bit */
pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
}
@@ -367,8 +364,7 @@ static void pch_stop(struct i2c_algo_pch_data *adap)
static void pch_repstart(struct i2c_algo_pch_data *adap)
{
void __iomem *p = adap->pch_base_address;
- pch_dbg(adap, "In %s : I2CCTL = %x\n",
- __func__, ioread32(p + PCH_I2CCTL));
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_REPSTART);
}
@@ -398,7 +394,7 @@ static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
/* enable master tx */
pch_setbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
- pch_dbg(adap, "%s : I2CCTL = %x msgs->len = %d\n", __func__,
+ pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n",
ioread32(p + PCH_I2CCTL), length);
if (first) {
@@ -431,13 +427,13 @@ static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
for (wrcount = 0; wrcount < length; ++wrcount) {
/* write buffer value to I2C data register */
iowrite32(buf[wrcount], p + PCH_I2CDR);
- pch_dbg(adap, "%s : writing %x to Data register\n",
- __func__, buf[wrcount]);
+ pch_dbg(adap, "writing %x to Data register\n",
+ buf[wrcount]);
if (pch_wait_for_xfer_complete(adap) != 0)
return -ETIME;
- pch_dbg(adap, "%s return %d", __func__, 0);
+ pch_dbg(adap, "return %d", 0);
if (pch_getack(adap))
return -ETIME;
@@ -453,7 +449,7 @@ static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
return -EIO;
}
- pch_dbg(adap, "%s return=%d\n", __func__, wrcount);
+ pch_dbg(adap, "return=%d\n", wrcount);
return wrcount;
}
@@ -465,7 +461,7 @@ static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
static void pch_sendack(struct i2c_algo_pch_data *adap)
{
void __iomem *p = adap->pch_base_address;
- pch_dbg(adap, "%s : I2CCTL = %x\n", __func__, ioread32(p + PCH_I2CCTL));
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
}
@@ -476,7 +472,7 @@ static void pch_sendack(struct i2c_algo_pch_data *adap)
static void pch_sendnack(struct i2c_algo_pch_data *adap)
{
void __iomem *p = adap->pch_base_address;
- pch_dbg(adap, "%s : I2CCTL = %x\n", __func__, ioread32(p + PCH_I2CCTL));
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
}
@@ -526,7 +522,7 @@ s32 pch_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
if ((pch_wait_for_xfer_complete(adap) == 0)
&& (pch_getack(adap) == 0)) {
- pch_dbg(adap, "%s return %d", __func__, 0);
+ pch_dbg(adap, "return %d", 0);
if (length == 0) {
pch_stop(adap);
@@ -599,8 +595,7 @@ static void pch_cb_ch0(struct i2c_algo_pch_data *adap)
/* clear the applicable bits */
pch_clrbit((adap->pch_base_address), PCH_I2CSR, sts);
- pch_dbg(adap, "%s : PCH_I2CSR = %x\n",
- __func__, ioread32(p + PCH_I2CSR));
+ pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
wake_up_interruptible(&pch_event);
}
@@ -619,7 +614,7 @@ static irqreturn_t pch_handler_ch0(int irq, void *pData)
u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE);
if (mode != NORMAL_MODE) {
- pch_err(adap_data, "%s I2C mode is not supported\n", __func__);
+ pch_err(adap_data, "I2C mode is not supported\n");
return IRQ_NONE;
}
@@ -639,7 +634,7 @@ static irqreturn_t pch_handler_ch0(int irq, void *pData)
else
goto err_out;
} else {
- pch_err(adap_data, "%s I2C mode is not supported\n", __func__);
+ pch_err(adap_data, "I2C mode is not supported\n");
goto err_out;
}
return IRQ_HANDLED;
@@ -675,8 +670,8 @@ static s32 pch_xfer(struct i2c_adapter *i2c_adap,
return -EBUSY;
}
- pch_dbg(adap, "%s adap->p_adapter_info->pch_suspended is %d\n",
- __func__, adap->p_adapter_info->pch_suspended);
+ pch_dbg(adap, "adap->p_adapter_info->pch_suspended is %d\n",
+ adap->p_adapter_info->pch_suspended);
/* transfer not completed */
adap->pch_xfer_in_progress = true;
@@ -685,7 +680,7 @@ static s32 pch_xfer(struct i2c_adapter *i2c_adap,
pmsg->flags |= adap->pch_buff_mode_en;
status = pmsg->flags;
pch_dbg(adap,
- "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
+ "After invoking I2C_MODE_SEL: flag=0x%x\n", status);
/* calculate sub address length and message length */
/* these are applicable only for buffer mode */
subaddrlen = pmsg->buf[0];
@@ -693,11 +688,11 @@ static s32 pch_xfer(struct i2c_adapter *i2c_adap,
* the sub address fields */
msglen = (pmsg->len) - (subaddrlen + 1);
if (status & (I2C_M_RD)) {
- pch_dbg(adap, "%s invoking pch_readbytes\n", __func__);
+ pch_dbg(adap, "invoking pch_readbytes\n");
ret = pch_readbytes(i2c_adap, pmsg, (i + 1 == num),
(i == 0));
} else {
- pch_dbg(adap, "%s invoking pch_writebytes\n", __func__);
+ pch_dbg(adap, "invoking pch_writebytes\n");
ret = pch_writebytes(i2c_adap, pmsg, (i + 1 == num),
(i == 0));
}
@@ -752,29 +747,29 @@ static int __devinit pch_probe(struct pci_dev *pdev,
struct adapter_info *adap_info =
kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
- dev_dbg(&pdev->dev, "Enterred in %s\n", __func__);
+ pch_pci_dbg(pdev, "Entered\n");
if (adap_info == NULL) {
- pch_pci_err(pdev, "Memory allocation failed FAILED");
+ pch_pci_err(pdev, "Memory allocation failed FAILED\n");
return -ENOMEM;
}
ret = pci_enable_device(pdev);
if (ret) {
- pch_pci_err(pdev, "%s : pci_enable_device FAILED", __func__);
+ pch_pci_err(pdev, "pci_enable_device FAILED\n");
goto err_pci_enable;
}
ret = pci_request_regions(pdev, KBUILD_MODNAME);
if (ret) {
- pch_pci_err(pdev, "pci_request_regions FAILED");
+ pch_pci_err(pdev, "pci_request_regions FAILED\n");
goto err_pci_req;
}
base_addr = pci_iomap(pdev, 1, 0);
if (base_addr == 0) {
- pch_pci_err(pdev, "pci_iomap FAILED");
+ pch_pci_err(pdev, "pci_iomap FAILED\n");
ret = -ENOMEM;
goto err_pci_iomap;
}
@@ -799,7 +794,7 @@ static int __devinit pch_probe(struct pci_dev *pdev,
ret = i2c_add_adapter(&(adap_info->pch_data[i].pch_adapter));
if (ret) {
- pch_pci_err(pdev, "i2c_add_adapter FAILED");
+ pch_pci_err(pdev, "i2c_add_adapter FAILED\n");
goto err_i2c_add_adapter;
}
@@ -807,12 +802,12 @@ static int __devinit pch_probe(struct pci_dev *pdev,
ret = request_irq(pdev->irq, pch_handler_list[i], IRQF_SHARED,
KBUILD_MODNAME, &adap_info->pch_data[i]);
if (ret) {
- pch_pci_err(pdev, "request_irq Failed\n");
+ pch_pci_err(pdev, "request_irq FAILED\n");
goto err_request_irq;
}
}
- dev_dbg(&pdev->dev, "request_irq returns %d pch_probe returns.\n", ret);
+ pch_pci_dbg(pdev, "request_irq returns %d pch_probe returns\n", ret);
pci_set_drvdata(pdev, adap_info);
return 0;
@@ -876,12 +871,12 @@ static int pch_suspend(struct pci_dev *pdev, pm_message_t state)
pch_disbl_int(&adap_info->pch_data[i]);
}
- dev_dbg(&pdev->dev,
- "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
- "invoked function pch_disbl_int successfully\n",
- ioread32(p + 0x08),
- ioread32(p + 0x30),
- ioread32(p + 0x44));
+ pch_pci_dbg(pdev,
+ "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
+ "invoked function pch_disbl_int successfully\n",
+ ioread32(p + 0x08),
+ ioread32(p + 0x30),
+ ioread32(p + 0x44));
ret = pci_save_state(pdev);
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-03 4:38 ` Joe Perches
0 siblings, 0 replies; 47+ messages in thread
From: Joe Perches @ 2010-09-03 4:38 UTC (permalink / raw)
To: Masayuki Ohtak
Cc: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
yong.y.wang-ral2JQCrhuEAvxtiuMwx3w,
qi.wang-ral2JQCrhuEAvxtiuMwx3w,
andrew.chih.howe.khor-ral2JQCrhuEAvxtiuMwx3w,
arjan-VuQAYsv1563Yd54FQh9/CA, Tomoya MORINAGA, Arnd Bergmann
I suggest these logging message changes and bug fixes:
Add pch_pci_dbg.
Rename 1st argument to pch_pci_dbg to pdev.
Add trailing "\n" to formats missing them.
Add "%s:" fmt, __func__, args to pch_<level> and pch_pci_<level>
logging macros.
Remove __func__ and inconsistent use of "%s : " and "%s:" prefix
from logging macro uses.
Fix misspelling of Enterred to Entered.
Use "FAILED" consistently.
There's an odd use that is still questionable:
pch_pci_dbg(pdev, "request_irq returns %d pch_probe returns\n", ret);
Signed-off-by: Joe Perches <joe-6d6DIl74uiNBDgjK7y7TUQ@public.gmane.org>
---
drivers/i2c/busses/i2c-pch.c | 103 ++++++++++++++++++++----------------------
1 files changed, 49 insertions(+), 54 deletions(-)
diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c
index 0933e63..f5bb140 100644
--- a/drivers/i2c/busses/i2c-pch.c
+++ b/drivers/i2c/busses/i2c-pch.c
@@ -121,13 +121,15 @@
#define I2CESRTO_EVENT 0x0100
#define PCI_DEVICE_ID_PCH_I2C 0x8817
-#define pch_dbg(adap, fmt, arg...) \
- dev_dbg(adap->pch_adapter.dev.parent, fmt, ##arg)
+#define pch_dbg(adap, fmt, arg...) \
+ dev_dbg(adap->pch_adapter.dev.parent, "%s: " fmt, __func__, ##arg)
+#define pch_err(adap, fmt, arg...) \
+ dev_err(adap->pch_adapter.dev.parent, "%s: " fmt, __func__, ##arg)
-#define pch_err(adap, fmt, arg...) \
- dev_err(adap->pch_adapter.dev.parent, fmt, ##arg)
-
-#define pch_pci_err(adap, fmt, arg...) dev_err(&adap->dev, fmt, ##arg)
+#define pch_pci_dbg(pdev, fmt, arg...) \
+ dev_dbg(&pdev->dev, "%s: " fmt, __func__, ##arg)
+#define pch_pci_err(pdev, fmt, arg...) \
+ dev_err(&pdev->dev, "%s: " fmt, __func__, ##arg)
/**
* struct i2c_algo_pch_data - for I2C driver functionalities
@@ -243,9 +245,8 @@ static void pch_init(struct i2c_algo_pch_data *adap)
reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
iowrite32(reg_value, p + PCH_I2CCTL);
- pch_dbg(adap,
- "%s: I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
- __func__, ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
+ pch_dbg(adap, "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
+ ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
init_waitqueue_head(&pch_event);
}
@@ -273,10 +274,10 @@ static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
msleep(1);
} while (ktime_lt(ktime_get(), ns_val));
- pch_dbg(adap, "%s : I2CSR = %x\n", __func__, ioread32(p + PCH_I2CSR));
+ pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
if (timeout == 0) {
- pch_err(adap, "%s :return%d\n", __func__, -ETIME);
+ pch_err(adap, "return: %d\n", -ETIME);
return -ETIME;
}
@@ -292,8 +293,7 @@ static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
static void pch_start(struct i2c_algo_pch_data *adap)
{
void __iomem *p = adap->pch_base_address;
- pch_dbg(adap, "In %s : I2CCTL = %x\n",
- __func__, ioread32(p + PCH_I2CCTL));
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
}
@@ -307,20 +307,17 @@ static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
ret = wait_event_interruptible_timeout(pch_event,
(adap->pch_event_flag != 0), msecs_to_jiffies(50));
if (ret < 0) {
- pch_err(adap, "%s :timeout: %x\n",
- __func__, adap->pch_event_flag);
+ pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
return ret;
}
if (ret == 0) {
- pch_err(adap, "%s :timeout: %x\n",
- __func__, adap->pch_event_flag);
+ pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
return -ETIMEDOUT;
}
if (adap->pch_event_flag & I2C_ERROR_MASK) {
- pch_err(adap, "%s :error bits set: %x\n",
- __func__, adap->pch_event_flag);
+ pch_err(adap, "error bits set: %x\n", adap->pch_event_flag);
return -EIO;
}
@@ -341,7 +338,7 @@ static s32 pch_getack(struct i2c_algo_pch_data *adap)
reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
if (reg_val != 0) {
- pch_err(adap, "%s : return%d\n", __func__, -EPROTO);
+ pch_err(adap, "return: %d\n", -EPROTO);
return -EPROTO;
}
@@ -355,7 +352,7 @@ static s32 pch_getack(struct i2c_algo_pch_data *adap)
static void pch_stop(struct i2c_algo_pch_data *adap)
{
void __iomem *p = adap->pch_base_address;
- pch_dbg(adap, "%s : I2CCTL = %x\n", __func__, ioread32(p + PCH_I2CCTL));
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
/* clear the start bit */
pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
}
@@ -367,8 +364,7 @@ static void pch_stop(struct i2c_algo_pch_data *adap)
static void pch_repstart(struct i2c_algo_pch_data *adap)
{
void __iomem *p = adap->pch_base_address;
- pch_dbg(adap, "In %s : I2CCTL = %x\n",
- __func__, ioread32(p + PCH_I2CCTL));
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_REPSTART);
}
@@ -398,7 +394,7 @@ static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
/* enable master tx */
pch_setbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
- pch_dbg(adap, "%s : I2CCTL = %x msgs->len = %d\n", __func__,
+ pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n",
ioread32(p + PCH_I2CCTL), length);
if (first) {
@@ -431,13 +427,13 @@ static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
for (wrcount = 0; wrcount < length; ++wrcount) {
/* write buffer value to I2C data register */
iowrite32(buf[wrcount], p + PCH_I2CDR);
- pch_dbg(adap, "%s : writing %x to Data register\n",
- __func__, buf[wrcount]);
+ pch_dbg(adap, "writing %x to Data register\n",
+ buf[wrcount]);
if (pch_wait_for_xfer_complete(adap) != 0)
return -ETIME;
- pch_dbg(adap, "%s return %d", __func__, 0);
+ pch_dbg(adap, "return %d", 0);
if (pch_getack(adap))
return -ETIME;
@@ -453,7 +449,7 @@ static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
return -EIO;
}
- pch_dbg(adap, "%s return=%d\n", __func__, wrcount);
+ pch_dbg(adap, "return=%d\n", wrcount);
return wrcount;
}
@@ -465,7 +461,7 @@ static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
static void pch_sendack(struct i2c_algo_pch_data *adap)
{
void __iomem *p = adap->pch_base_address;
- pch_dbg(adap, "%s : I2CCTL = %x\n", __func__, ioread32(p + PCH_I2CCTL));
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
}
@@ -476,7 +472,7 @@ static void pch_sendack(struct i2c_algo_pch_data *adap)
static void pch_sendnack(struct i2c_algo_pch_data *adap)
{
void __iomem *p = adap->pch_base_address;
- pch_dbg(adap, "%s : I2CCTL = %x\n", __func__, ioread32(p + PCH_I2CCTL));
+ pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
}
@@ -526,7 +522,7 @@ s32 pch_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
if ((pch_wait_for_xfer_complete(adap) == 0)
&& (pch_getack(adap) == 0)) {
- pch_dbg(adap, "%s return %d", __func__, 0);
+ pch_dbg(adap, "return %d", 0);
if (length == 0) {
pch_stop(adap);
@@ -599,8 +595,7 @@ static void pch_cb_ch0(struct i2c_algo_pch_data *adap)
/* clear the applicable bits */
pch_clrbit((adap->pch_base_address), PCH_I2CSR, sts);
- pch_dbg(adap, "%s : PCH_I2CSR = %x\n",
- __func__, ioread32(p + PCH_I2CSR));
+ pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
wake_up_interruptible(&pch_event);
}
@@ -619,7 +614,7 @@ static irqreturn_t pch_handler_ch0(int irq, void *pData)
u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE);
if (mode != NORMAL_MODE) {
- pch_err(adap_data, "%s I2C mode is not supported\n", __func__);
+ pch_err(adap_data, "I2C mode is not supported\n");
return IRQ_NONE;
}
@@ -639,7 +634,7 @@ static irqreturn_t pch_handler_ch0(int irq, void *pData)
else
goto err_out;
} else {
- pch_err(adap_data, "%s I2C mode is not supported\n", __func__);
+ pch_err(adap_data, "I2C mode is not supported\n");
goto err_out;
}
return IRQ_HANDLED;
@@ -675,8 +670,8 @@ static s32 pch_xfer(struct i2c_adapter *i2c_adap,
return -EBUSY;
}
- pch_dbg(adap, "%s adap->p_adapter_info->pch_suspended is %d\n",
- __func__, adap->p_adapter_info->pch_suspended);
+ pch_dbg(adap, "adap->p_adapter_info->pch_suspended is %d\n",
+ adap->p_adapter_info->pch_suspended);
/* transfer not completed */
adap->pch_xfer_in_progress = true;
@@ -685,7 +680,7 @@ static s32 pch_xfer(struct i2c_adapter *i2c_adap,
pmsg->flags |= adap->pch_buff_mode_en;
status = pmsg->flags;
pch_dbg(adap,
- "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
+ "After invoking I2C_MODE_SEL: flag=0x%x\n", status);
/* calculate sub address length and message length */
/* these are applicable only for buffer mode */
subaddrlen = pmsg->buf[0];
@@ -693,11 +688,11 @@ static s32 pch_xfer(struct i2c_adapter *i2c_adap,
* the sub address fields */
msglen = (pmsg->len) - (subaddrlen + 1);
if (status & (I2C_M_RD)) {
- pch_dbg(adap, "%s invoking pch_readbytes\n", __func__);
+ pch_dbg(adap, "invoking pch_readbytes\n");
ret = pch_readbytes(i2c_adap, pmsg, (i + 1 == num),
(i == 0));
} else {
- pch_dbg(adap, "%s invoking pch_writebytes\n", __func__);
+ pch_dbg(adap, "invoking pch_writebytes\n");
ret = pch_writebytes(i2c_adap, pmsg, (i + 1 == num),
(i == 0));
}
@@ -752,29 +747,29 @@ static int __devinit pch_probe(struct pci_dev *pdev,
struct adapter_info *adap_info =
kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
- dev_dbg(&pdev->dev, "Enterred in %s\n", __func__);
+ pch_pci_dbg(pdev, "Entered\n");
if (adap_info == NULL) {
- pch_pci_err(pdev, "Memory allocation failed FAILED");
+ pch_pci_err(pdev, "Memory allocation failed FAILED\n");
return -ENOMEM;
}
ret = pci_enable_device(pdev);
if (ret) {
- pch_pci_err(pdev, "%s : pci_enable_device FAILED", __func__);
+ pch_pci_err(pdev, "pci_enable_device FAILED\n");
goto err_pci_enable;
}
ret = pci_request_regions(pdev, KBUILD_MODNAME);
if (ret) {
- pch_pci_err(pdev, "pci_request_regions FAILED");
+ pch_pci_err(pdev, "pci_request_regions FAILED\n");
goto err_pci_req;
}
base_addr = pci_iomap(pdev, 1, 0);
if (base_addr == 0) {
- pch_pci_err(pdev, "pci_iomap FAILED");
+ pch_pci_err(pdev, "pci_iomap FAILED\n");
ret = -ENOMEM;
goto err_pci_iomap;
}
@@ -799,7 +794,7 @@ static int __devinit pch_probe(struct pci_dev *pdev,
ret = i2c_add_adapter(&(adap_info->pch_data[i].pch_adapter));
if (ret) {
- pch_pci_err(pdev, "i2c_add_adapter FAILED");
+ pch_pci_err(pdev, "i2c_add_adapter FAILED\n");
goto err_i2c_add_adapter;
}
@@ -807,12 +802,12 @@ static int __devinit pch_probe(struct pci_dev *pdev,
ret = request_irq(pdev->irq, pch_handler_list[i], IRQF_SHARED,
KBUILD_MODNAME, &adap_info->pch_data[i]);
if (ret) {
- pch_pci_err(pdev, "request_irq Failed\n");
+ pch_pci_err(pdev, "request_irq FAILED\n");
goto err_request_irq;
}
}
- dev_dbg(&pdev->dev, "request_irq returns %d pch_probe returns.\n", ret);
+ pch_pci_dbg(pdev, "request_irq returns %d pch_probe returns\n", ret);
pci_set_drvdata(pdev, adap_info);
return 0;
@@ -876,12 +871,12 @@ static int pch_suspend(struct pci_dev *pdev, pm_message_t state)
pch_disbl_int(&adap_info->pch_data[i]);
}
- dev_dbg(&pdev->dev,
- "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
- "invoked function pch_disbl_int successfully\n",
- ioread32(p + 0x08),
- ioread32(p + 0x30),
- ioread32(p + 0x44));
+ pch_pci_dbg(pdev,
+ "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
+ "invoked function pch_disbl_int successfully\n",
+ ioread32(p + 0x08),
+ ioread32(p + 0x30),
+ ioread32(p + 0x44));
ret = pci_save_state(pdev);
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-03 3:19 ` Masayuki Ohtak
0 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtak @ 2010-09-03 3:19 UTC (permalink / raw)
To: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz, Linus Walleij, Ralf Baechle,
srinidhi kasagar, linux-i2c, linux-kernel
Cc: yong.y.wang, qi.wang, andrew.chih.howe.khor, arjan,
Tomoya MORINAGA, Arnd Bergmann
Hi Linus Walleij
We have updated for your comments.
Please confirm below.
---
I2C driver of Topcliff PCH
Topcliff PCH is the platform controller hub that is going to be used in
Intel's upcoming general embedded platform. All IO peripherals in
Topcliff PCH are actually devices sitting on AMBA bus.
Topcliff PCH has I2C I/F. Using this I/F, it is able to access system
devices connected to I2C.
Signed-off-by: Masayuki Ohtake <masa-korg@dsn.okisemi.com>
---
drivers/i2c/busses/Kconfig | 18 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-pch.c | 951 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 970 insertions(+), 0 deletions(-)
create mode 100644 drivers/i2c/busses/i2c-pch.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index bceafbf..c5db1e7 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -613,6 +613,24 @@ config I2C_XILINX
This driver can also be built as a module. If so, the module
will be called xilinx_i2c.
+config PCH_I2C
+ tristate "PCH I2C of Intel Topcliff"
+ depends on PCI
+ help
+ This driver is for PCH(Platform controller Hub) I2C of Topcliff which
+ is an IOH(Input/Output Hub) for x86 embedded processor.
+ This driver can access PCH I2C bus device.
+
+config PCH_I2C_CH_COUNT
+ int "PCH I2C the number of channel count"
+ range 1 2
+ depends on PCH_I2C
+ help
+ This driver is for PCH(Platform controller Hub) I2C of Topcliff which
+ is an IOH(Input/Output Hub) for x86 embedded processor.
+ The number of I2C buses/channels supported by the PCH I2C controller.
+ PCH I2C of Topcliff supports only one channel.
+
comment "External I2C/SMBus adapter drivers"
config I2C_PARPORT
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 936880b..aa04135 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
+obj-$(CONFIG_PCH_I2C) += i2c-pch.o
# External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o
diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c
new file mode 100644
index 0000000..0933e63
--- /dev/null
+++ b/drivers/i2c/busses/i2c-pch.c
@@ -0,0 +1,951 @@
+/*
+ * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/pci.h>
+#include <linux/mutex.h>
+#include <linux/ktime.h>
+
+#define PCH_MAX_CHN CONFIG_PCH_I2C_CH_COUNT /* Maximum I2C channels
+ available */
+#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
+#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
+#define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
+#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
+#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
+
+#define PCH_I2CSADR 0x00 /* I2C slave address register */
+#define PCH_I2CCTL 0x04 /* I2C control register */
+#define PCH_I2CSR 0x08 /* I2C status register */
+#define PCH_I2CDR 0x0C /* I2C data register */
+#define PCH_I2CMON 0x10 /* I2C bus monitor register */
+#define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
+#define PCH_I2CMOD 0x18 /* I2C mode register */
+#define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
+#define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
+#define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
+#define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
+#define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
+#define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
+#define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
+#define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
+#define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
+#define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
+#define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
+#define PCH_I2CTMR 0x48 /* I2C timer register */
+#define PCH_I2CSRST 0xFC /* I2C reset register */
+#define PCH_I2CNF 0xF8 /* I2C noise filter register */
+
+#define BUS_IDLE_TIMEOUT 20
+#define PCH_I2CCTL_I2CMEN 0x0080
+#define TEN_BIT_ADDR_DEFAULT 0xF000
+#define TEN_BIT_ADDR_MASK 0xF0
+#define PCH_START 0x0020
+#define PCH_ESR_START 0x0001
+#define PCH_BUFF_START 0x1
+#define PCH_REPSTART 0x0004
+#define PCH_ACK 0x0008
+#define PCH_GETACK 0x0001
+#define CLR_REG 0x0
+#define I2C_RD 0x1
+#define I2CMCF_BIT 0x0080
+#define I2CMIF_BIT 0x0002
+#define I2CMAL_BIT 0x0010
+#define I2CBMFI_BIT 0x0001
+#define I2CBMAL_BIT 0x0002
+#define I2CBMNA_BIT 0x0004
+#define I2CBMTO_BIT 0x0008
+#define I2CBMIS_BIT 0x0010
+#define I2CESRFI_BIT 0X0001
+#define I2CESRTO_BIT 0x0002
+#define I2CESRFIIE_BIT 0x1
+#define I2CESRTOIE_BIT 0x2
+#define I2CBMDZ_BIT 0x0040
+#define I2CBMAG_BIT 0x0020
+#define I2CMBB_BIT 0x0020
+#define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
+ I2CBMTO_BIT | I2CBMIS_BIT)
+#define I2C_ADDR_MSK 0xFF
+#define I2C_MSB_2B_MSK 0x300
+#define FAST_MODE_CLK 400
+#define FAST_MODE_EN 0x0001
+#define SUB_ADDR_LEN_MAX 4
+#define BUF_LEN_MAX 32
+#define PCH_BUFFER_MODE 0x1
+#define EEPROM_SW_RST_MODE 0x0002
+#define NORMAL_INTR_ENBL 0x0300
+#define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
+#define EEPROM_RST_INTR_DISBL 0x0
+#define BUFFER_MODE_INTR_ENBL 0x001F
+#define BUFFER_MODE_INTR_DISBL 0x0
+#define NORMAL_MODE 0x0
+#define BUFFER_MODE 0x1
+#define EEPROM_SR_MODE 0x2
+#define I2C_TX_MODE 0x0010
+#define PCH_BUF_TX 0xFFF7
+#define PCH_BUF_RD 0x0008
+#define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
+ I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
+#define I2CMAL_EVENT 0x0001
+#define I2CMCF_EVENT 0x0002
+#define I2CBMFI_EVENT 0x0004
+#define I2CBMAL_EVENT 0x0008
+#define I2CBMNA_EVENT 0x0010
+#define I2CBMTO_EVENT 0x0020
+#define I2CBMIS_EVENT 0x0040
+#define I2CESRFI_EVENT 0x0080
+#define I2CESRTO_EVENT 0x0100
+#define PCI_DEVICE_ID_PCH_I2C 0x8817
+
+#define pch_dbg(adap, fmt, arg...) \
+ dev_dbg(adap->pch_adapter.dev.parent, fmt, ##arg)
+
+#define pch_err(adap, fmt, arg...) \
+ dev_err(adap->pch_adapter.dev.parent, fmt, ##arg)
+
+#define pch_pci_err(adap, fmt, arg...) dev_err(&adap->dev, fmt, ##arg)
+
+/**
+ * struct i2c_algo_pch_data - for I2C driver functionalities
+ * @p_adapter_info: stores the reference to adapter_info structure
+ * @pch_adapter: stores the reference to i2c_adapter structure
+ * @pch_base_address: specifies the remapped base address
+ * @pch_buff_mode_en: specifies if buffer mode is enabled
+ * @pch_event_flag: specifies occurrence of interrupt events
+ * @pch_xfer_in_progress: specifies whether the transfer is completed
+ */
+struct i2c_algo_pch_data {
+ struct adapter_info *p_adapter_info;
+ struct i2c_adapter pch_adapter;
+ void __iomem *pch_base_address;
+ int pch_buff_mode_en;
+ u32 pch_event_flag;
+ bool pch_xfer_in_progress;
+};
+
+/**
+ * struct adapter_info - This structure holds the adapter information for the
+ PCH i2c controller
+ * @pch_data: stores a list of i2c_algo_pch_data
+ * @pch_suspended: specifies whether the system is suspended or not
+ * perhaps with more lines and words.
+ *
+ * pch_data has as many elements as maximum I2C channels
+ */
+struct adapter_info {
+ struct i2c_algo_pch_data pch_data[PCH_MAX_CHN];
+ bool pch_suspended;
+};
+
+
+static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
+static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
+static wait_queue_head_t pch_event;
+static DEFINE_MUTEX(pch_mutex);
+
+static struct pci_device_id __devinitdata pch_pcidev_id[] = {
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_I2C)},
+ {0,}
+};
+
+static irqreturn_t pch_handler_ch0(int irq, void *pData);
+static irqreturn_t(*pch_handler_list[PCH_MAX_CHN]) (int irq, void *pData) = {
+ pch_handler_ch0,
+};
+
+static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ u32 val;
+ val = ioread32(addr + offset);
+ val |= bitmask;
+ iowrite32(val, addr + offset);
+}
+
+static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ u32 val;
+ val = ioread32(addr + offset);
+ val &= (~bitmask);
+ iowrite32(val, addr + offset);
+}
+
+/**
+ * pch_init() - hardware initialization of I2C module
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_init(struct i2c_algo_pch_data *adap)
+{
+ u32 pch_i2cbc;
+ u32 pch_i2ctmr;
+ u32 reg_value;
+ void __iomem *p = adap->pch_base_address;
+
+ /* reset I2C controller */
+ iowrite32(0x01, p + PCH_I2CSRST);
+ iowrite32(0x0, p + PCH_I2CSRST);
+ /* Initialize I2C registers */
+ iowrite32(CLR_REG, p + PCH_I2CCTL);
+ iowrite32(CLR_REG, p + PCH_I2CMOD);
+ iowrite32(CLR_REG, p + PCH_I2CBUFFOR);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSLV);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSUB);
+ iowrite32(CLR_REG, p + PCH_I2CBUFMSK);
+ iowrite32(CLR_REG, p + PCH_I2CESRFOR);
+ iowrite32(CLR_REG, p + PCH_I2CESRMSK);
+ iowrite32(0x21, p + PCH_I2CNF);
+
+ reg_value = PCH_I2CCTL_I2CMEN;
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL,
+ PCH_I2CCTL_I2CMEN);
+
+ if (pch_i2c_speed != 400)
+ pch_i2c_speed = 100;
+
+ if (pch_i2c_speed == FAST_MODE_CLK) {
+ reg_value |= FAST_MODE_EN;
+ pch_dbg(adap, "Fast mode enabled\n");
+ }
+
+ if (pch_clk <= 0 || pch_clk > PCH_MAX_CLK)
+ pch_clk = 62500;
+
+ pch_i2cbc = ((pch_clk) + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
+ /* Set transfer speed in I2CBC */
+ iowrite32(pch_i2cbc, p + PCH_I2CBC);
+
+ pch_i2ctmr = (pch_clk) / 8;
+ iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
+
+ reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
+ iowrite32(reg_value, p + PCH_I2CCTL);
+
+ pch_dbg(adap,
+ "%s: I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
+ __func__, ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
+
+ init_waitqueue_head(&pch_event);
+}
+
+static inline int ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
+{
+ return cmp1.tv64 < cmp2.tv64;
+}
+
+/**
+ * pch_wait_for_bus_idle() - check the status of bus.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ * @timeout: waiting time counter (us).
+ */
+static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
+ s32 timeout)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ /* MAX timeout value is timeout*1000*1000nsec */
+ ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
+ do {
+ if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
+ break;
+ msleep(1);
+ } while (ktime_lt(ktime_get(), ns_val));
+
+ pch_dbg(adap, "%s : I2CSR = %x\n", __func__, ioread32(p + PCH_I2CSR));
+
+ if (timeout == 0) {
+ pch_err(adap, "%s :return%d\n", __func__, -ETIME);
+ return -ETIME;
+ }
+
+ return 0;
+}
+
+/**
+ * pch_start() - Generate I2C start condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ *
+ * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
+ */
+static void pch_start(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "In %s : I2CCTL = %x\n",
+ __func__, ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+}
+
+/**
+ * pch_wait_for_xfer_complete() - initiates a wait for the tx complete event
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
+{
+ s32 ret;
+ ret = wait_event_interruptible_timeout(pch_event,
+ (adap->pch_event_flag != 0), msecs_to_jiffies(50));
+ if (ret < 0) {
+ pch_err(adap, "%s :timeout: %x\n",
+ __func__, adap->pch_event_flag);
+ return ret;
+ }
+
+ if (ret == 0) {
+ pch_err(adap, "%s :timeout: %x\n",
+ __func__, adap->pch_event_flag);
+ return -ETIMEDOUT;
+ }
+
+ if (adap->pch_event_flag & I2C_ERROR_MASK) {
+ pch_err(adap, "%s :error bits set: %x\n",
+ __func__, adap->pch_event_flag);
+ return -EIO;
+ }
+
+ adap->pch_event_flag = 0;
+ ret = 0;
+
+ return ret;
+}
+
+/**
+ * pch_getack() - to confirm ACK/NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_getack(struct i2c_algo_pch_data *adap)
+{
+ u32 reg_val;
+ void __iomem *p = adap->pch_base_address;
+ reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
+
+ if (reg_val != 0) {
+ pch_err(adap, "%s : return%d\n", __func__, -EPROTO);
+ return -EPROTO;
+ }
+
+ return 0;
+}
+
+/**
+ * pch_stop() - generate stop condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_stop(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "%s : I2CCTL = %x\n", __func__, ioread32(p + PCH_I2CCTL));
+ /* clear the start bit */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+}
+
+/**
+ * pch_repstart() - generate repeated start condition in normal mode
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_repstart(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "In %s : I2CCTL = %x\n",
+ __func__, ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_REPSTART);
+}
+
+/**
+ * pch_writebytes() - write data to I2C bus in normal mode
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @last: specifies whether last message or not.
+ * In the case of compound mode it will be 1 for last message,
+ * otherwise 0.
+ * @first: specifies whether first message or not.
+ * 1 for first message otherwise 0.
+ */
+static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+ u8 *buf;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ u32 addr_8_lsb;
+ s32 wrcount;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+ /* enable master tx */
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ pch_dbg(adap, "%s : I2CCTL = %x msgs->len = %d\n", __func__,
+ ioread32(p + PCH_I2CCTL), length);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ addr_8_lsb = (addr & I2C_ADDR_MSK);
+ iowrite32(addr_8_lsb, p + PCH_I2CDR);
+ } else {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } else {
+ /* set 7 bit slave address and R/W bit as 0 */
+ iowrite32(addr << 1, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ }
+
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ for (wrcount = 0; wrcount < length; ++wrcount) {
+ /* write buffer value to I2C data register */
+ iowrite32(buf[wrcount], p + PCH_I2CDR);
+ pch_dbg(adap, "%s : writing %x to Data register\n",
+ __func__, buf[wrcount]);
+
+ if (pch_wait_for_xfer_complete(adap) != 0)
+ return -ETIME;
+
+ pch_dbg(adap, "%s return %d", __func__, 0);
+
+ if (pch_getack(adap))
+ return -ETIME;
+ }
+
+ /* check if this is the last message */
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+ } else {
+ pch_stop(adap);
+ return -EIO;
+ }
+
+ pch_dbg(adap, "%s return=%d\n", __func__, wrcount);
+
+ return wrcount;
+}
+
+/**
+ * pch_sendack() - send ACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "%s : I2CCTL = %x\n", __func__, ioread32(p + PCH_I2CCTL));
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+}
+
+/**
+ * pch_sendnack() - send NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendnack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "%s : I2CCTL = %x\n", __func__, ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+}
+
+/**
+ * pch_readbytes() - read data from I2C bus in normal mode.
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @last: specifies whether last message or not.
+ * @first: specifies whether first message or not.
+ */
+s32 pch_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ u8 *buf;
+ u32 count;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+
+ /* enable master reception */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+
+ } else {
+ /* 7 address bits + R/W bit */
+ addr = (((addr) << 1) | (I2C_RD));
+ iowrite32(addr, p + PCH_I2CDR);
+ }
+
+ /* check if it is the first message */
+ if (first)
+ pch_start(adap);
+
+ if ((pch_wait_for_xfer_complete(adap) == 0)
+ && (pch_getack(adap) == 0)) {
+ pch_dbg(adap, "%s return %d", __func__, 0);
+
+ if (length == 0) {
+ pch_stop(adap);
+ ioread32(p + PCH_I2CDR); /* Dummy read needs */
+
+ count = length;
+ } else {
+ int read_index;
+ int loop;
+ pch_sendack(adap);
+
+ /* Dummy read */
+ for (loop = 1, read_index = 0; loop < length; loop++) {
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (loop != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) != 0) {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } /* end for */
+
+ pch_sendnack(adap);
+
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (length != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) == 0) {
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+
+ buf[read_index++] = ioread32(p + PCH_I2CDR);
+ count = read_index;
+ } else {
+ count = -ETIME;
+ }
+
+ }
+ } else {
+ count = -ETIME;
+ pch_stop(adap);
+ }
+
+ return count;
+}
+
+/**
+ * pch_cb_ch0() - Interrupt handler Call back function
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_cb_ch0(struct i2c_algo_pch_data *adap)
+{
+ u32 sts;
+ void __iomem *p = adap->pch_base_address;
+
+ sts = ioread32(p + PCH_I2CSR);
+ sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
+ if (I2CMAL_BIT & sts)
+ adap->pch_event_flag |= I2CMAL_EVENT;
+
+ if (I2CMCF_BIT & sts)
+ adap->pch_event_flag |= I2CMCF_EVENT;
+
+ /* clear the applicable bits */
+ pch_clrbit((adap->pch_base_address), PCH_I2CSR, sts);
+
+ pch_dbg(adap, "%s : PCH_I2CSR = %x\n",
+ __func__, ioread32(p + PCH_I2CSR));
+
+ wake_up_interruptible(&pch_event);
+}
+
+/**
+ * pch_handler_ch0() - interrupt handler for the PCH I2C controller
+ * @irq: irq number.
+ * @pData: cookie passed back to the handler function.
+ */
+static irqreturn_t pch_handler_ch0(int irq, void *pData)
+{
+ s32 reg_val;
+
+ struct i2c_algo_pch_data *adap_data = (struct i2c_algo_pch_data *)pData;
+ void __iomem *p = adap_data->pch_base_address;
+ u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE);
+
+ if (mode != NORMAL_MODE) {
+ pch_err(adap_data, "%s I2C mode is not supported\n", __func__);
+ return IRQ_NONE;
+ }
+
+ reg_val = ioread32(p + PCH_I2CSR);
+ if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
+ pch_cb_ch0(adap_data);
+ else
+ return IRQ_NONE;
+
+ return IRQ_HANDLED;
+}
+#if 0
+ if (mode == NORMAL_MODE) {
+ reg_val = ioread32(p + PCH_I2CSR);
+ if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
+ pch_cb_ch0(adap_data);
+ else
+ goto err_out;
+ } else {
+ pch_err(adap_data, "%s I2C mode is not supported\n", __func__);
+ goto err_out;
+ }
+ return IRQ_HANDLED;
+
+err_out:
+ return IRQ_NONE;
+}
+#endif
+/**
+ * pch_xfer() - Reading adnd writing data through I2C bus
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @num: number of messages.
+ */
+static s32 pch_xfer(struct i2c_adapter *i2c_adap,
+ struct i2c_msg *msgs, s32 num)
+{
+ struct i2c_msg *pmsg;
+ u32 i;
+ u32 status;
+ u32 msglen;
+ u32 subaddrlen;
+ s32 ret;
+
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ ret = mutex_lock_interruptible(&pch_mutex);
+ if (ret) {
+ return -ERESTARTSYS;
+ }
+ if (adap->p_adapter_info->pch_suspended) {
+ mutex_unlock(&pch_mutex);
+ return -EBUSY;
+ }
+
+ pch_dbg(adap, "%s adap->p_adapter_info->pch_suspended is %d\n",
+ __func__, adap->p_adapter_info->pch_suspended);
+ /* transfer not completed */
+ adap->pch_xfer_in_progress = true;
+
+ for (i = 0; i < num; i++) {
+ pmsg = &msgs[i];
+ pmsg->flags |= adap->pch_buff_mode_en;
+ status = pmsg->flags;
+ pch_dbg(adap,
+ "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
+ /* calculate sub address length and message length */
+ /* these are applicable only for buffer mode */
+ subaddrlen = pmsg->buf[0];
+ /* calculate actual message length excluding
+ * the sub address fields */
+ msglen = (pmsg->len) - (subaddrlen + 1);
+ if (status & (I2C_M_RD)) {
+ pch_dbg(adap, "%s invoking pch_readbytes\n", __func__);
+ ret = pch_readbytes(i2c_adap, pmsg, (i + 1 == num),
+ (i == 0));
+ } else {
+ pch_dbg(adap, "%s invoking pch_writebytes\n", __func__);
+ ret = pch_writebytes(i2c_adap, pmsg, (i + 1 == num),
+ (i == 0));
+ }
+
+ }
+
+ adap->pch_xfer_in_progress = false; /* transfer completed */
+
+ mutex_unlock(&pch_mutex);
+
+ return ret;
+}
+
+/**
+ * pch_func() - return the functionality of the I2C driver
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static u32 pch_func(struct i2c_adapter *adap)
+{
+ u32 ret;
+ ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
+ return ret;
+}
+
+static struct i2c_algorithm pch_algorithm = {
+ .master_xfer = pch_xfer,
+ .functionality = pch_func
+};
+
+/**
+ * pch_disbl_int() - Disable PCH I2C interrupts
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_disbl_int(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL,
+ NORMAL_INTR_ENBL);
+
+ iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
+
+ iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
+}
+
+static int __devinit pch_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ int i;
+ void __iomem *base_addr;
+ s32 ret;
+ struct adapter_info *adap_info =
+ kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
+
+ dev_dbg(&pdev->dev, "Enterred in %s\n", __func__);
+
+ if (adap_info == NULL) {
+ pch_pci_err(pdev, "Memory allocation failed FAILED");
+ return -ENOMEM;
+ }
+
+ ret = pci_enable_device(pdev);
+ if (ret) {
+ pch_pci_err(pdev, "%s : pci_enable_device FAILED", __func__);
+ goto err_pci_enable;
+ }
+
+ ret = pci_request_regions(pdev, KBUILD_MODNAME);
+ if (ret) {
+ pch_pci_err(pdev, "pci_request_regions FAILED");
+ goto err_pci_req;
+ }
+
+ base_addr = pci_iomap(pdev, 1, 0);
+
+ if (base_addr == 0) {
+ pch_pci_err(pdev, "pci_iomap FAILED");
+ ret = -ENOMEM;
+ goto err_pci_iomap;
+ }
+
+ adap_info->pch_suspended = false;
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ adap_info->pch_data[i].p_adapter_info = adap_info;
+
+ adap_info->pch_data[i].pch_adapter.owner = THIS_MODULE;
+ adap_info->pch_data[i].pch_adapter.class = I2C_CLASS_HWMON;
+ strcpy(adap_info->pch_data[i].pch_adapter.name, "pch_i2c");
+ adap_info->pch_data[i].pch_adapter.algo = &pch_algorithm;
+ adap_info->pch_data[i].pch_adapter.algo_data =
+ &adap_info->pch_data[i];
+
+ /* (i * 0x80) + base_addr; */
+ adap_info->pch_data[i].pch_base_address = base_addr;
+
+ adap_info->pch_data[i].pch_adapter.dev.parent = &pdev->dev;
+
+ ret = i2c_add_adapter(&(adap_info->pch_data[i].pch_adapter));
+
+ if (ret) {
+ pch_pci_err(pdev, "i2c_add_adapter FAILED");
+ goto err_i2c_add_adapter;
+ }
+
+ pch_init(&adap_info->pch_data[i]);
+ ret = request_irq(pdev->irq, pch_handler_list[i], IRQF_SHARED,
+ KBUILD_MODNAME, &adap_info->pch_data[i]);
+ if (ret) {
+ pch_pci_err(pdev, "request_irq Failed\n");
+ goto err_request_irq;
+ }
+ }
+
+ dev_dbg(&pdev->dev, "request_irq returns %d pch_probe returns.\n", ret);
+ pci_set_drvdata(pdev, adap_info);
+ return 0;
+
+err_request_irq:
+ for (i = 0; i < PCH_MAX_CHN; i++)
+ i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
+err_i2c_add_adapter:
+ pci_iounmap(pdev, base_addr);
+err_pci_iomap:
+ pci_release_regions(pdev);
+err_pci_req:
+ pci_disable_device(pdev);
+err_pci_enable:
+ kfree(adap_info);
+ return ret;
+}
+
+static void __devexit pch_remove(struct pci_dev *pdev)
+{
+ int i;
+
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ pch_disbl_int(&adap_info->pch_data[i]);
+ free_irq(pdev->irq, &adap_info->pch_data[i]);
+ i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
+ }
+
+ if (adap_info->pch_data[0].pch_base_address) {
+ pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
+ adap_info->pch_data[0].pch_base_address = 0;
+ }
+
+ pci_set_drvdata(pdev, NULL);
+
+ pci_release_regions(pdev);
+
+ pci_disable_device(pdev);
+ kfree(adap_info);
+}
+
+#ifdef CONFIG_PM
+static int pch_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ int i;
+ int ret;
+
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+ void __iomem *p = adap_info->pch_data[0].pch_base_address;
+
+ adap_info->pch_suspended = true;
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
+ /* Wait until all channel transfers are completed */
+ msleep(1);
+ }
+ /* Disable the i2c interrupts */
+ pch_disbl_int(&adap_info->pch_data[i]);
+ }
+
+ dev_dbg(&pdev->dev,
+ "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
+ "invoked function pch_disbl_int successfully\n",
+ ioread32(p + 0x08),
+ ioread32(p + 0x30),
+ ioread32(p + 0x44));
+
+ ret = pci_save_state(pdev);
+
+ if (ret) {
+ pch_pci_err(pdev, "pci_save_state failed\n");
+ return ret;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+ pci_disable_device(pdev);
+ pci_set_power_state(pdev, pci_choose_state(pdev, state));
+
+ return 0;
+}
+
+static int pch_resume(struct pci_dev *pdev)
+{
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+ int i;
+
+ pci_set_power_state(pdev, PCI_D0);
+ pci_restore_state(pdev);
+
+ if (pci_enable_device(pdev) < 0) {
+ pch_pci_err(pdev, "pci_enable_device failed in pch_resume\n");
+ return -EIO;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+
+ for (i = 0; i < PCH_MAX_CHN; i++)
+ pch_init(&adap_info->pch_data[i]);
+
+ adap_info->pch_suspended = false;
+
+ return 0;
+}
+#else
+#define pch_suspend NULL
+#define pch_resume NULL
+#endif
+
+static struct pci_driver pch_pcidriver = {
+ .name = KBUILD_MODNAME,
+ .id_table = pch_pcidev_id,
+ .probe = pch_probe,
+ .remove = __devexit_p(pch_remove),
+ .suspend = pch_suspend,
+ .resume = pch_resume
+};
+
+static int __init pch_pci_init(void)
+{
+ return pci_register_driver(&pch_pcidriver);
+}
+
+static void __exit pch_pci_exit(void)
+{
+ pci_unregister_driver(&pch_pcidriver);
+}
+
+MODULE_DESCRIPTION("PCH I2C PCI Driver");
+MODULE_LICENSE("GPL");
+module_init(pch_pci_init);
+module_exit(pch_pci_exit);
+module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
+module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
--
1.6.0.6
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-03 3:19 ` Masayuki Ohtak
0 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtak @ 2010-09-03 3:19 UTC (permalink / raw)
To: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz
Cc: yong.y.wang-ral2JQCrhuEAvxtiuMwx3w,
qi.wang-ral2JQCrhuEAvxtiuMwx3w,
andrew.chih.howe.khor-ral2JQCrhuEAvxtiuMwx3w,
arjan-VuQAYsv1563Yd54FQh9/CA, Tomoya MORINAGA, Arnd Bergmann
Hi Linus Walleij
We have updated for your comments.
Please confirm below.
---
I2C driver of Topcliff PCH
Topcliff PCH is the platform controller hub that is going to be used in
Intel's upcoming general embedded platform. All IO peripherals in
Topcliff PCH are actually devices sitting on AMBA bus.
Topcliff PCH has I2C I/F. Using this I/F, it is able to access system
devices connected to I2C.
Signed-off-by: Masayuki Ohtake <masa-korg-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>
---
drivers/i2c/busses/Kconfig | 18 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-pch.c | 951 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 970 insertions(+), 0 deletions(-)
create mode 100644 drivers/i2c/busses/i2c-pch.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index bceafbf..c5db1e7 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -613,6 +613,24 @@ config I2C_XILINX
This driver can also be built as a module. If so, the module
will be called xilinx_i2c.
+config PCH_I2C
+ tristate "PCH I2C of Intel Topcliff"
+ depends on PCI
+ help
+ This driver is for PCH(Platform controller Hub) I2C of Topcliff which
+ is an IOH(Input/Output Hub) for x86 embedded processor.
+ This driver can access PCH I2C bus device.
+
+config PCH_I2C_CH_COUNT
+ int "PCH I2C the number of channel count"
+ range 1 2
+ depends on PCH_I2C
+ help
+ This driver is for PCH(Platform controller Hub) I2C of Topcliff which
+ is an IOH(Input/Output Hub) for x86 embedded processor.
+ The number of I2C buses/channels supported by the PCH I2C controller.
+ PCH I2C of Topcliff supports only one channel.
+
comment "External I2C/SMBus adapter drivers"
config I2C_PARPORT
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 936880b..aa04135 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
+obj-$(CONFIG_PCH_I2C) += i2c-pch.o
# External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o
diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c
new file mode 100644
index 0000000..0933e63
--- /dev/null
+++ b/drivers/i2c/busses/i2c-pch.c
@@ -0,0 +1,951 @@
+/*
+ * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/pci.h>
+#include <linux/mutex.h>
+#include <linux/ktime.h>
+
+#define PCH_MAX_CHN CONFIG_PCH_I2C_CH_COUNT /* Maximum I2C channels
+ available */
+#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
+#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
+#define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
+#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
+#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
+
+#define PCH_I2CSADR 0x00 /* I2C slave address register */
+#define PCH_I2CCTL 0x04 /* I2C control register */
+#define PCH_I2CSR 0x08 /* I2C status register */
+#define PCH_I2CDR 0x0C /* I2C data register */
+#define PCH_I2CMON 0x10 /* I2C bus monitor register */
+#define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
+#define PCH_I2CMOD 0x18 /* I2C mode register */
+#define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
+#define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
+#define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
+#define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
+#define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
+#define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
+#define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
+#define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
+#define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
+#define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
+#define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
+#define PCH_I2CTMR 0x48 /* I2C timer register */
+#define PCH_I2CSRST 0xFC /* I2C reset register */
+#define PCH_I2CNF 0xF8 /* I2C noise filter register */
+
+#define BUS_IDLE_TIMEOUT 20
+#define PCH_I2CCTL_I2CMEN 0x0080
+#define TEN_BIT_ADDR_DEFAULT 0xF000
+#define TEN_BIT_ADDR_MASK 0xF0
+#define PCH_START 0x0020
+#define PCH_ESR_START 0x0001
+#define PCH_BUFF_START 0x1
+#define PCH_REPSTART 0x0004
+#define PCH_ACK 0x0008
+#define PCH_GETACK 0x0001
+#define CLR_REG 0x0
+#define I2C_RD 0x1
+#define I2CMCF_BIT 0x0080
+#define I2CMIF_BIT 0x0002
+#define I2CMAL_BIT 0x0010
+#define I2CBMFI_BIT 0x0001
+#define I2CBMAL_BIT 0x0002
+#define I2CBMNA_BIT 0x0004
+#define I2CBMTO_BIT 0x0008
+#define I2CBMIS_BIT 0x0010
+#define I2CESRFI_BIT 0X0001
+#define I2CESRTO_BIT 0x0002
+#define I2CESRFIIE_BIT 0x1
+#define I2CESRTOIE_BIT 0x2
+#define I2CBMDZ_BIT 0x0040
+#define I2CBMAG_BIT 0x0020
+#define I2CMBB_BIT 0x0020
+#define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
+ I2CBMTO_BIT | I2CBMIS_BIT)
+#define I2C_ADDR_MSK 0xFF
+#define I2C_MSB_2B_MSK 0x300
+#define FAST_MODE_CLK 400
+#define FAST_MODE_EN 0x0001
+#define SUB_ADDR_LEN_MAX 4
+#define BUF_LEN_MAX 32
+#define PCH_BUFFER_MODE 0x1
+#define EEPROM_SW_RST_MODE 0x0002
+#define NORMAL_INTR_ENBL 0x0300
+#define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
+#define EEPROM_RST_INTR_DISBL 0x0
+#define BUFFER_MODE_INTR_ENBL 0x001F
+#define BUFFER_MODE_INTR_DISBL 0x0
+#define NORMAL_MODE 0x0
+#define BUFFER_MODE 0x1
+#define EEPROM_SR_MODE 0x2
+#define I2C_TX_MODE 0x0010
+#define PCH_BUF_TX 0xFFF7
+#define PCH_BUF_RD 0x0008
+#define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
+ I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
+#define I2CMAL_EVENT 0x0001
+#define I2CMCF_EVENT 0x0002
+#define I2CBMFI_EVENT 0x0004
+#define I2CBMAL_EVENT 0x0008
+#define I2CBMNA_EVENT 0x0010
+#define I2CBMTO_EVENT 0x0020
+#define I2CBMIS_EVENT 0x0040
+#define I2CESRFI_EVENT 0x0080
+#define I2CESRTO_EVENT 0x0100
+#define PCI_DEVICE_ID_PCH_I2C 0x8817
+
+#define pch_dbg(adap, fmt, arg...) \
+ dev_dbg(adap->pch_adapter.dev.parent, fmt, ##arg)
+
+#define pch_err(adap, fmt, arg...) \
+ dev_err(adap->pch_adapter.dev.parent, fmt, ##arg)
+
+#define pch_pci_err(adap, fmt, arg...) dev_err(&adap->dev, fmt, ##arg)
+
+/**
+ * struct i2c_algo_pch_data - for I2C driver functionalities
+ * @p_adapter_info: stores the reference to adapter_info structure
+ * @pch_adapter: stores the reference to i2c_adapter structure
+ * @pch_base_address: specifies the remapped base address
+ * @pch_buff_mode_en: specifies if buffer mode is enabled
+ * @pch_event_flag: specifies occurrence of interrupt events
+ * @pch_xfer_in_progress: specifies whether the transfer is completed
+ */
+struct i2c_algo_pch_data {
+ struct adapter_info *p_adapter_info;
+ struct i2c_adapter pch_adapter;
+ void __iomem *pch_base_address;
+ int pch_buff_mode_en;
+ u32 pch_event_flag;
+ bool pch_xfer_in_progress;
+};
+
+/**
+ * struct adapter_info - This structure holds the adapter information for the
+ PCH i2c controller
+ * @pch_data: stores a list of i2c_algo_pch_data
+ * @pch_suspended: specifies whether the system is suspended or not
+ * perhaps with more lines and words.
+ *
+ * pch_data has as many elements as maximum I2C channels
+ */
+struct adapter_info {
+ struct i2c_algo_pch_data pch_data[PCH_MAX_CHN];
+ bool pch_suspended;
+};
+
+
+static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
+static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
+static wait_queue_head_t pch_event;
+static DEFINE_MUTEX(pch_mutex);
+
+static struct pci_device_id __devinitdata pch_pcidev_id[] = {
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_I2C)},
+ {0,}
+};
+
+static irqreturn_t pch_handler_ch0(int irq, void *pData);
+static irqreturn_t(*pch_handler_list[PCH_MAX_CHN]) (int irq, void *pData) = {
+ pch_handler_ch0,
+};
+
+static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ u32 val;
+ val = ioread32(addr + offset);
+ val |= bitmask;
+ iowrite32(val, addr + offset);
+}
+
+static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ u32 val;
+ val = ioread32(addr + offset);
+ val &= (~bitmask);
+ iowrite32(val, addr + offset);
+}
+
+/**
+ * pch_init() - hardware initialization of I2C module
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_init(struct i2c_algo_pch_data *adap)
+{
+ u32 pch_i2cbc;
+ u32 pch_i2ctmr;
+ u32 reg_value;
+ void __iomem *p = adap->pch_base_address;
+
+ /* reset I2C controller */
+ iowrite32(0x01, p + PCH_I2CSRST);
+ iowrite32(0x0, p + PCH_I2CSRST);
+ /* Initialize I2C registers */
+ iowrite32(CLR_REG, p + PCH_I2CCTL);
+ iowrite32(CLR_REG, p + PCH_I2CMOD);
+ iowrite32(CLR_REG, p + PCH_I2CBUFFOR);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSLV);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSUB);
+ iowrite32(CLR_REG, p + PCH_I2CBUFMSK);
+ iowrite32(CLR_REG, p + PCH_I2CESRFOR);
+ iowrite32(CLR_REG, p + PCH_I2CESRMSK);
+ iowrite32(0x21, p + PCH_I2CNF);
+
+ reg_value = PCH_I2CCTL_I2CMEN;
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL,
+ PCH_I2CCTL_I2CMEN);
+
+ if (pch_i2c_speed != 400)
+ pch_i2c_speed = 100;
+
+ if (pch_i2c_speed == FAST_MODE_CLK) {
+ reg_value |= FAST_MODE_EN;
+ pch_dbg(adap, "Fast mode enabled\n");
+ }
+
+ if (pch_clk <= 0 || pch_clk > PCH_MAX_CLK)
+ pch_clk = 62500;
+
+ pch_i2cbc = ((pch_clk) + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
+ /* Set transfer speed in I2CBC */
+ iowrite32(pch_i2cbc, p + PCH_I2CBC);
+
+ pch_i2ctmr = (pch_clk) / 8;
+ iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
+
+ reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
+ iowrite32(reg_value, p + PCH_I2CCTL);
+
+ pch_dbg(adap,
+ "%s: I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
+ __func__, ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
+
+ init_waitqueue_head(&pch_event);
+}
+
+static inline int ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
+{
+ return cmp1.tv64 < cmp2.tv64;
+}
+
+/**
+ * pch_wait_for_bus_idle() - check the status of bus.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ * @timeout: waiting time counter (us).
+ */
+static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
+ s32 timeout)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ /* MAX timeout value is timeout*1000*1000nsec */
+ ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
+ do {
+ if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
+ break;
+ msleep(1);
+ } while (ktime_lt(ktime_get(), ns_val));
+
+ pch_dbg(adap, "%s : I2CSR = %x\n", __func__, ioread32(p + PCH_I2CSR));
+
+ if (timeout == 0) {
+ pch_err(adap, "%s :return%d\n", __func__, -ETIME);
+ return -ETIME;
+ }
+
+ return 0;
+}
+
+/**
+ * pch_start() - Generate I2C start condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ *
+ * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
+ */
+static void pch_start(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "In %s : I2CCTL = %x\n",
+ __func__, ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+}
+
+/**
+ * pch_wait_for_xfer_complete() - initiates a wait for the tx complete event
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
+{
+ s32 ret;
+ ret = wait_event_interruptible_timeout(pch_event,
+ (adap->pch_event_flag != 0), msecs_to_jiffies(50));
+ if (ret < 0) {
+ pch_err(adap, "%s :timeout: %x\n",
+ __func__, adap->pch_event_flag);
+ return ret;
+ }
+
+ if (ret == 0) {
+ pch_err(adap, "%s :timeout: %x\n",
+ __func__, adap->pch_event_flag);
+ return -ETIMEDOUT;
+ }
+
+ if (adap->pch_event_flag & I2C_ERROR_MASK) {
+ pch_err(adap, "%s :error bits set: %x\n",
+ __func__, adap->pch_event_flag);
+ return -EIO;
+ }
+
+ adap->pch_event_flag = 0;
+ ret = 0;
+
+ return ret;
+}
+
+/**
+ * pch_getack() - to confirm ACK/NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_getack(struct i2c_algo_pch_data *adap)
+{
+ u32 reg_val;
+ void __iomem *p = adap->pch_base_address;
+ reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
+
+ if (reg_val != 0) {
+ pch_err(adap, "%s : return%d\n", __func__, -EPROTO);
+ return -EPROTO;
+ }
+
+ return 0;
+}
+
+/**
+ * pch_stop() - generate stop condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_stop(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "%s : I2CCTL = %x\n", __func__, ioread32(p + PCH_I2CCTL));
+ /* clear the start bit */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+}
+
+/**
+ * pch_repstart() - generate repeated start condition in normal mode
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_repstart(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "In %s : I2CCTL = %x\n",
+ __func__, ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_REPSTART);
+}
+
+/**
+ * pch_writebytes() - write data to I2C bus in normal mode
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @last: specifies whether last message or not.
+ * In the case of compound mode it will be 1 for last message,
+ * otherwise 0.
+ * @first: specifies whether first message or not.
+ * 1 for first message otherwise 0.
+ */
+static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+ u8 *buf;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ u32 addr_8_lsb;
+ s32 wrcount;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+ /* enable master tx */
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ pch_dbg(adap, "%s : I2CCTL = %x msgs->len = %d\n", __func__,
+ ioread32(p + PCH_I2CCTL), length);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ addr_8_lsb = (addr & I2C_ADDR_MSK);
+ iowrite32(addr_8_lsb, p + PCH_I2CDR);
+ } else {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } else {
+ /* set 7 bit slave address and R/W bit as 0 */
+ iowrite32(addr << 1, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ }
+
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ for (wrcount = 0; wrcount < length; ++wrcount) {
+ /* write buffer value to I2C data register */
+ iowrite32(buf[wrcount], p + PCH_I2CDR);
+ pch_dbg(adap, "%s : writing %x to Data register\n",
+ __func__, buf[wrcount]);
+
+ if (pch_wait_for_xfer_complete(adap) != 0)
+ return -ETIME;
+
+ pch_dbg(adap, "%s return %d", __func__, 0);
+
+ if (pch_getack(adap))
+ return -ETIME;
+ }
+
+ /* check if this is the last message */
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+ } else {
+ pch_stop(adap);
+ return -EIO;
+ }
+
+ pch_dbg(adap, "%s return=%d\n", __func__, wrcount);
+
+ return wrcount;
+}
+
+/**
+ * pch_sendack() - send ACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "%s : I2CCTL = %x\n", __func__, ioread32(p + PCH_I2CCTL));
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+}
+
+/**
+ * pch_sendnack() - send NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendnack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ pch_dbg(adap, "%s : I2CCTL = %x\n", __func__, ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+}
+
+/**
+ * pch_readbytes() - read data from I2C bus in normal mode.
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @last: specifies whether last message or not.
+ * @first: specifies whether first message or not.
+ */
+s32 pch_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ u8 *buf;
+ u32 count;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+
+ /* enable master reception */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+
+ } else {
+ /* 7 address bits + R/W bit */
+ addr = (((addr) << 1) | (I2C_RD));
+ iowrite32(addr, p + PCH_I2CDR);
+ }
+
+ /* check if it is the first message */
+ if (first)
+ pch_start(adap);
+
+ if ((pch_wait_for_xfer_complete(adap) == 0)
+ && (pch_getack(adap) == 0)) {
+ pch_dbg(adap, "%s return %d", __func__, 0);
+
+ if (length == 0) {
+ pch_stop(adap);
+ ioread32(p + PCH_I2CDR); /* Dummy read needs */
+
+ count = length;
+ } else {
+ int read_index;
+ int loop;
+ pch_sendack(adap);
+
+ /* Dummy read */
+ for (loop = 1, read_index = 0; loop < length; loop++) {
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (loop != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) != 0) {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } /* end for */
+
+ pch_sendnack(adap);
+
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (length != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) == 0) {
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+
+ buf[read_index++] = ioread32(p + PCH_I2CDR);
+ count = read_index;
+ } else {
+ count = -ETIME;
+ }
+
+ }
+ } else {
+ count = -ETIME;
+ pch_stop(adap);
+ }
+
+ return count;
+}
+
+/**
+ * pch_cb_ch0() - Interrupt handler Call back function
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_cb_ch0(struct i2c_algo_pch_data *adap)
+{
+ u32 sts;
+ void __iomem *p = adap->pch_base_address;
+
+ sts = ioread32(p + PCH_I2CSR);
+ sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
+ if (I2CMAL_BIT & sts)
+ adap->pch_event_flag |= I2CMAL_EVENT;
+
+ if (I2CMCF_BIT & sts)
+ adap->pch_event_flag |= I2CMCF_EVENT;
+
+ /* clear the applicable bits */
+ pch_clrbit((adap->pch_base_address), PCH_I2CSR, sts);
+
+ pch_dbg(adap, "%s : PCH_I2CSR = %x\n",
+ __func__, ioread32(p + PCH_I2CSR));
+
+ wake_up_interruptible(&pch_event);
+}
+
+/**
+ * pch_handler_ch0() - interrupt handler for the PCH I2C controller
+ * @irq: irq number.
+ * @pData: cookie passed back to the handler function.
+ */
+static irqreturn_t pch_handler_ch0(int irq, void *pData)
+{
+ s32 reg_val;
+
+ struct i2c_algo_pch_data *adap_data = (struct i2c_algo_pch_data *)pData;
+ void __iomem *p = adap_data->pch_base_address;
+ u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE);
+
+ if (mode != NORMAL_MODE) {
+ pch_err(adap_data, "%s I2C mode is not supported\n", __func__);
+ return IRQ_NONE;
+ }
+
+ reg_val = ioread32(p + PCH_I2CSR);
+ if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
+ pch_cb_ch0(adap_data);
+ else
+ return IRQ_NONE;
+
+ return IRQ_HANDLED;
+}
+#if 0
+ if (mode == NORMAL_MODE) {
+ reg_val = ioread32(p + PCH_I2CSR);
+ if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
+ pch_cb_ch0(adap_data);
+ else
+ goto err_out;
+ } else {
+ pch_err(adap_data, "%s I2C mode is not supported\n", __func__);
+ goto err_out;
+ }
+ return IRQ_HANDLED;
+
+err_out:
+ return IRQ_NONE;
+}
+#endif
+/**
+ * pch_xfer() - Reading adnd writing data through I2C bus
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @num: number of messages.
+ */
+static s32 pch_xfer(struct i2c_adapter *i2c_adap,
+ struct i2c_msg *msgs, s32 num)
+{
+ struct i2c_msg *pmsg;
+ u32 i;
+ u32 status;
+ u32 msglen;
+ u32 subaddrlen;
+ s32 ret;
+
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ ret = mutex_lock_interruptible(&pch_mutex);
+ if (ret) {
+ return -ERESTARTSYS;
+ }
+ if (adap->p_adapter_info->pch_suspended) {
+ mutex_unlock(&pch_mutex);
+ return -EBUSY;
+ }
+
+ pch_dbg(adap, "%s adap->p_adapter_info->pch_suspended is %d\n",
+ __func__, adap->p_adapter_info->pch_suspended);
+ /* transfer not completed */
+ adap->pch_xfer_in_progress = true;
+
+ for (i = 0; i < num; i++) {
+ pmsg = &msgs[i];
+ pmsg->flags |= adap->pch_buff_mode_en;
+ status = pmsg->flags;
+ pch_dbg(adap,
+ "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
+ /* calculate sub address length and message length */
+ /* these are applicable only for buffer mode */
+ subaddrlen = pmsg->buf[0];
+ /* calculate actual message length excluding
+ * the sub address fields */
+ msglen = (pmsg->len) - (subaddrlen + 1);
+ if (status & (I2C_M_RD)) {
+ pch_dbg(adap, "%s invoking pch_readbytes\n", __func__);
+ ret = pch_readbytes(i2c_adap, pmsg, (i + 1 == num),
+ (i == 0));
+ } else {
+ pch_dbg(adap, "%s invoking pch_writebytes\n", __func__);
+ ret = pch_writebytes(i2c_adap, pmsg, (i + 1 == num),
+ (i == 0));
+ }
+
+ }
+
+ adap->pch_xfer_in_progress = false; /* transfer completed */
+
+ mutex_unlock(&pch_mutex);
+
+ return ret;
+}
+
+/**
+ * pch_func() - return the functionality of the I2C driver
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static u32 pch_func(struct i2c_adapter *adap)
+{
+ u32 ret;
+ ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
+ return ret;
+}
+
+static struct i2c_algorithm pch_algorithm = {
+ .master_xfer = pch_xfer,
+ .functionality = pch_func
+};
+
+/**
+ * pch_disbl_int() - Disable PCH I2C interrupts
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_disbl_int(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL,
+ NORMAL_INTR_ENBL);
+
+ iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
+
+ iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
+}
+
+static int __devinit pch_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ int i;
+ void __iomem *base_addr;
+ s32 ret;
+ struct adapter_info *adap_info =
+ kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
+
+ dev_dbg(&pdev->dev, "Enterred in %s\n", __func__);
+
+ if (adap_info == NULL) {
+ pch_pci_err(pdev, "Memory allocation failed FAILED");
+ return -ENOMEM;
+ }
+
+ ret = pci_enable_device(pdev);
+ if (ret) {
+ pch_pci_err(pdev, "%s : pci_enable_device FAILED", __func__);
+ goto err_pci_enable;
+ }
+
+ ret = pci_request_regions(pdev, KBUILD_MODNAME);
+ if (ret) {
+ pch_pci_err(pdev, "pci_request_regions FAILED");
+ goto err_pci_req;
+ }
+
+ base_addr = pci_iomap(pdev, 1, 0);
+
+ if (base_addr == 0) {
+ pch_pci_err(pdev, "pci_iomap FAILED");
+ ret = -ENOMEM;
+ goto err_pci_iomap;
+ }
+
+ adap_info->pch_suspended = false;
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ adap_info->pch_data[i].p_adapter_info = adap_info;
+
+ adap_info->pch_data[i].pch_adapter.owner = THIS_MODULE;
+ adap_info->pch_data[i].pch_adapter.class = I2C_CLASS_HWMON;
+ strcpy(adap_info->pch_data[i].pch_adapter.name, "pch_i2c");
+ adap_info->pch_data[i].pch_adapter.algo = &pch_algorithm;
+ adap_info->pch_data[i].pch_adapter.algo_data =
+ &adap_info->pch_data[i];
+
+ /* (i * 0x80) + base_addr; */
+ adap_info->pch_data[i].pch_base_address = base_addr;
+
+ adap_info->pch_data[i].pch_adapter.dev.parent = &pdev->dev;
+
+ ret = i2c_add_adapter(&(adap_info->pch_data[i].pch_adapter));
+
+ if (ret) {
+ pch_pci_err(pdev, "i2c_add_adapter FAILED");
+ goto err_i2c_add_adapter;
+ }
+
+ pch_init(&adap_info->pch_data[i]);
+ ret = request_irq(pdev->irq, pch_handler_list[i], IRQF_SHARED,
+ KBUILD_MODNAME, &adap_info->pch_data[i]);
+ if (ret) {
+ pch_pci_err(pdev, "request_irq Failed\n");
+ goto err_request_irq;
+ }
+ }
+
+ dev_dbg(&pdev->dev, "request_irq returns %d pch_probe returns.\n", ret);
+ pci_set_drvdata(pdev, adap_info);
+ return 0;
+
+err_request_irq:
+ for (i = 0; i < PCH_MAX_CHN; i++)
+ i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
+err_i2c_add_adapter:
+ pci_iounmap(pdev, base_addr);
+err_pci_iomap:
+ pci_release_regions(pdev);
+err_pci_req:
+ pci_disable_device(pdev);
+err_pci_enable:
+ kfree(adap_info);
+ return ret;
+}
+
+static void __devexit pch_remove(struct pci_dev *pdev)
+{
+ int i;
+
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ pch_disbl_int(&adap_info->pch_data[i]);
+ free_irq(pdev->irq, &adap_info->pch_data[i]);
+ i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
+ }
+
+ if (adap_info->pch_data[0].pch_base_address) {
+ pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
+ adap_info->pch_data[0].pch_base_address = 0;
+ }
+
+ pci_set_drvdata(pdev, NULL);
+
+ pci_release_regions(pdev);
+
+ pci_disable_device(pdev);
+ kfree(adap_info);
+}
+
+#ifdef CONFIG_PM
+static int pch_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ int i;
+ int ret;
+
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+ void __iomem *p = adap_info->pch_data[0].pch_base_address;
+
+ adap_info->pch_suspended = true;
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
+ /* Wait until all channel transfers are completed */
+ msleep(1);
+ }
+ /* Disable the i2c interrupts */
+ pch_disbl_int(&adap_info->pch_data[i]);
+ }
+
+ dev_dbg(&pdev->dev,
+ "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
+ "invoked function pch_disbl_int successfully\n",
+ ioread32(p + 0x08),
+ ioread32(p + 0x30),
+ ioread32(p + 0x44));
+
+ ret = pci_save_state(pdev);
+
+ if (ret) {
+ pch_pci_err(pdev, "pci_save_state failed\n");
+ return ret;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+ pci_disable_device(pdev);
+ pci_set_power_state(pdev, pci_choose_state(pdev, state));
+
+ return 0;
+}
+
+static int pch_resume(struct pci_dev *pdev)
+{
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+ int i;
+
+ pci_set_power_state(pdev, PCI_D0);
+ pci_restore_state(pdev);
+
+ if (pci_enable_device(pdev) < 0) {
+ pch_pci_err(pdev, "pci_enable_device failed in pch_resume\n");
+ return -EIO;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+
+ for (i = 0; i < PCH_MAX_CHN; i++)
+ pch_init(&adap_info->pch_data[i]);
+
+ adap_info->pch_suspended = false;
+
+ return 0;
+}
+#else
+#define pch_suspend NULL
+#define pch_resume NULL
+#endif
+
+static struct pci_driver pch_pcidriver = {
+ .name = KBUILD_MODNAME,
+ .id_table = pch_pcidev_id,
+ .probe = pch_probe,
+ .remove = __devexit_p(pch_remove),
+ .suspend = pch_suspend,
+ .resume = pch_resume
+};
+
+static int __init pch_pci_init(void)
+{
+ return pci_register_driver(&pch_pcidriver);
+}
+
+static void __exit pch_pci_exit(void)
+{
+ pci_unregister_driver(&pch_pcidriver);
+}
+
+MODULE_DESCRIPTION("PCH I2C PCI Driver");
+MODULE_LICENSE("GPL");
+module_init(pch_pci_init);
+module_exit(pch_pci_exit);
+module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
+module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
--
1.6.0.6
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
@ 2010-09-01 2:26 Masayuki Ohtak
0 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtak @ 2010-09-01 2:26 UTC (permalink / raw)
To: Jean Delvare (PC drivers, core), Ben Dooks (embedded platforms),
Crane Cai, Samuel Ortiz
Cc: Wang Yong Y", Wang Qi", Andrew",
arjan-VuQAYsv1563Yd54FQh9/CA, Tomoya MORINAGA, Arnd Bergmann
I2C driver of Topcliff PCH
Topcliff PCH is the platform controller hub that is going to be used in
Intel's upcoming general embedded platform. All IO peripherals in
Topcliff PCH are actually devices sitting on AMBA bus.
Topcliff PCH has I2C I/F. Using this I/F, it is able to access system
devices connected to I2C.
Signed-off-by: Masayuki Ohtake <masa-korg-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>
---
drivers/i2c/busses/Kconfig | 18 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-pch.c | 966 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 985 insertions(+), 0 deletions(-)
create mode 100644 drivers/i2c/busses/i2c-pch.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index bceafbf..c5db1e7 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -613,6 +613,24 @@ config I2C_XILINX
This driver can also be built as a module. If so, the module
will be called xilinx_i2c.
+config PCH_I2C
+ tristate "PCH I2C of Intel Topcliff"
+ depends on PCI
+ help
+ This driver is for PCH(Platform controller Hub) I2C of Topcliff which
+ is an IOH(Input/Output Hub) for x86 embedded processor.
+ This driver can access PCH I2C bus device.
+
+config PCH_I2C_CH_COUNT
+ int "PCH I2C the number of channel count"
+ range 1 2
+ depends on PCH_I2C
+ help
+ This driver is for PCH(Platform controller Hub) I2C of Topcliff which
+ is an IOH(Input/Output Hub) for x86 embedded processor.
+ The number of I2C buses/channels supported by the PCH I2C controller.
+ PCH I2C of Topcliff supports only one channel.
+
comment "External I2C/SMBus adapter drivers"
config I2C_PARPORT
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 936880b..aa04135 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
+obj-$(CONFIG_PCH_I2C) += i2c-pch.o
# External I2C/SMBus adapter drivers
obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o
diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c
new file mode 100644
index 0000000..fc1b6a0
--- /dev/null
+++ b/drivers/i2c/busses/i2c-pch.c
@@ -0,0 +1,966 @@
+/*
+ * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/pci.h>
+#include <linux/mutex.h>
+#include <linux/ktime.h>
+
+#define PCH_MAX_CHN CONFIG_PCH_I2C_CH_COUNT /* Maximum I2C channels
+ available */
+#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
+#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
+#define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
+#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
+#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
+
+#define PCH_I2CSADR 0x00 /* I2C slave address register */
+#define PCH_I2CCTL 0x04 /* I2C control register */
+#define PCH_I2CSR 0x08 /* I2C status register */
+#define PCH_I2CDR 0x0C /* I2C data register */
+#define PCH_I2CMON 0x10 /* I2C bus monitor register */
+#define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
+#define PCH_I2CMOD 0x18 /* I2C mode register */
+#define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
+#define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
+#define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
+#define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
+#define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
+#define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
+#define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
+#define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
+#define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
+#define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
+#define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
+#define PCH_I2CTMR 0x48 /* I2C timer register */
+#define PCH_I2CSRST 0xFC /* I2C reset register */
+#define PCH_I2CNF 0xF8 /* I2C noise filter register */
+
+#define BUS_IDLE_TIMEOUT 20
+#define PCH_I2CCTL_I2CMEN 0x0080
+#define TEN_BIT_ADDR_DEFAULT 0xF000
+#define TEN_BIT_ADDR_MASK 0xF0
+#define PCH_START 0x0020
+#define PCH_ESR_START 0x0001
+#define PCH_BUFF_START 0x1
+#define PCH_REPSTART 0x0004
+#define PCH_ACK 0x0008
+#define PCH_GETACK 0x0001
+#define CLR_REG 0x0
+#define I2C_RD 0x1
+#define I2CMCF_BIT 0x0080
+#define I2CMIF_BIT 0x0002
+#define I2CMAL_BIT 0x0010
+#define I2CBMFI_BIT 0x0001
+#define I2CBMAL_BIT 0x0002
+#define I2CBMNA_BIT 0x0004
+#define I2CBMTO_BIT 0x0008
+#define I2CBMIS_BIT 0x0010
+#define I2CESRFI_BIT 0X0001
+#define I2CESRTO_BIT 0x0002
+#define I2CESRFIIE_BIT 0x1
+#define I2CESRTOIE_BIT 0x2
+#define I2CBMDZ_BIT 0x0040
+#define I2CBMAG_BIT 0x0020
+#define I2CMBB_BIT 0x0020
+#define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
+ I2CBMTO_BIT | I2CBMIS_BIT)
+#define I2C_ADDR_MSK 0xFF
+#define I2C_MSB_2B_MSK 0x300
+#define FAST_MODE_CLK 400
+#define FAST_MODE_EN 0x0001
+#define SUB_ADDR_LEN_MAX 4
+#define BUF_LEN_MAX 32
+#define PCH_BUFFER_MODE 0x1
+#define EEPROM_SW_RST_MODE 0x0002
+#define NORMAL_INTR_ENBL 0x0300
+#define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
+#define EEPROM_RST_INTR_DISBL 0x0
+#define BUFFER_MODE_INTR_ENBL 0x001F
+#define BUFFER_MODE_INTR_DISBL 0x0
+#define NORMAL_MODE 0x0
+#define BUFFER_MODE 0x1
+#define EEPROM_SR_MODE 0x2
+#define I2C_TX_MODE 0x0010
+#define PCH_BUF_TX 0xFFF7
+#define PCH_BUF_RD 0x0008
+#define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
+ I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
+#define I2CMAL_EVENT 0x0001
+#define I2CMCF_EVENT 0x0002
+#define I2CBMFI_EVENT 0x0004
+#define I2CBMAL_EVENT 0x0008
+#define I2CBMNA_EVENT 0x0010
+#define I2CBMTO_EVENT 0x0020
+#define I2CBMIS_EVENT 0x0040
+#define I2CESRFI_EVENT 0x0080
+#define I2CESRTO_EVENT 0x0100
+
+#define MODULE_NAME "pch_i2c"
+#define PCI_DEVICE_ID_PCH_I2C 0x8817
+
+/**
+ * struct i2c_algo_pch_data - for I2C driver functionalities
+ * @p_adapter_info: stores the reference to adapter_info structure
+ * @pch_adapter: stores the reference to i2c_adapter structure
+ * @pch_base_address: specifies the remapped base address
+ * @pch_buff_mode_en: specifies if buffer mode is enabled
+ * @pch_event_flag: specifies occurrence of interrupt events
+ * @pch_xfer_in_progress: specifies whether the transfer is completed
+ */
+struct i2c_algo_pch_data {
+ struct adapter_info *p_adapter_info;
+ struct i2c_adapter pch_adapter;
+ void __iomem *pch_base_address;
+ int pch_buff_mode_en;
+ u32 pch_event_flag;
+ bool pch_xfer_in_progress;
+};
+
+/**
+ * struct adapter_info - This structure holds the adapter information for the
+ PCH i2c controller
+ * @pch_data: stores a list of i2c_algo_pch_data
+ * @pch_suspended: specifies whether the system is suspended or not
+ * perhaps with more lines and words.
+ *
+ * pch_data has as many elements as maximum I2C channels
+ */
+struct adapter_info {
+ struct i2c_algo_pch_data pch_data[PCH_MAX_CHN];
+ bool pch_suspended;
+};
+
+
+static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
+static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
+static wait_queue_head_t pch_event;
+static DEFINE_MUTEX(pch_mutex);
+
+static struct pci_device_id __devinitdata pch_pcidev_id[] = {
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PCH_I2C)},
+ {0,}
+};
+
+static irqreturn_t pch_handler_ch0(int irq, void *pData);
+static irqreturn_t(*pch_handler_list[PCH_MAX_CHN]) (int irq, void *pData) = {
+ pch_handler_ch0,
+};
+
+static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ u32 val;
+ val = ioread32(addr + offset);
+ val |= bitmask;
+ iowrite32(val, addr + offset);
+}
+
+static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
+{
+ u32 val;
+ val = ioread32(addr + offset);
+ val &= (~bitmask);
+ iowrite32(val, addr + offset);
+}
+
+/**
+ * pch_init() - hardware initialization of I2C module
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_init(struct i2c_algo_pch_data *adap)
+{
+ u32 pch_i2cbc;
+ u32 pch_i2ctmr;
+ u32 reg_value;
+ void __iomem *p = adap->pch_base_address;
+
+ /* reset I2C controller */
+ iowrite32(0x01, p + PCH_I2CSRST);
+ iowrite32(0x0, p + PCH_I2CSRST);
+ /* Initialize I2C registers */
+ iowrite32(CLR_REG, p + PCH_I2CCTL);
+ iowrite32(CLR_REG, p + PCH_I2CMOD);
+ iowrite32(CLR_REG, p + PCH_I2CBUFFOR);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSLV);
+ iowrite32(CLR_REG, p + PCH_I2CBUFSUB);
+ iowrite32(CLR_REG, p + PCH_I2CBUFMSK);
+ iowrite32(CLR_REG, p + PCH_I2CESRFOR);
+ iowrite32(CLR_REG, p + PCH_I2CESRMSK);
+ iowrite32(0x21, p + PCH_I2CNF);
+
+ reg_value = PCH_I2CCTL_I2CMEN;
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL,
+ PCH_I2CCTL_I2CMEN);
+
+ if (pch_i2c_speed != 400)
+ pch_i2c_speed = 100;
+
+ if (pch_i2c_speed == FAST_MODE_CLK) {
+ reg_value |= FAST_MODE_EN;
+ dev_dbg(adap->pch_adapter.dev.parent, "Fast mode enabled\n");
+ }
+
+ if (pch_clk <= 0 || pch_clk > PCH_MAX_CLK)
+ pch_clk = 62500;
+
+ pch_i2cbc = ((pch_clk) + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
+ /* Set transfer speed in I2CBC */
+ iowrite32(pch_i2cbc, p + PCH_I2CBC);
+
+ pch_i2ctmr = (pch_clk) / 8;
+ iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
+
+ reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
+ iowrite32(reg_value, p + PCH_I2CCTL);
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s: I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
+ __func__, ioread32(p + PCH_I2CCTL),
+ pch_i2cbc, pch_i2ctmr);
+
+ init_waitqueue_head(&pch_event);
+}
+
+static inline int ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
+{
+ return cmp1.tv64 < cmp2.tv64;
+}
+
+/**
+ * pch_wait_for_bus_idle() - check the status of bus.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ * @timeout: waiting time counter (us).
+ */
+static s32 pch_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
+ s32 timeout)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ /* MAX timeout value is timeout*1000*1000nsec */
+ ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
+ do {
+ if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
+ break;
+ msleep(1);
+ } while (ktime_lt(ktime_get(), ns_val));
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s : I2CSR = %x\n", __func__, ioread32(p + PCH_I2CSR));
+
+ if (timeout == 0) {
+ dev_err(adap->pch_adapter.dev.parent,
+ "%s :return%d\n", __func__, -ETIME);
+ } else {
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s : return %d\n", __func__, 0);
+ }
+
+ return ((timeout <= 0) ? (-ETIME) : (0));
+}
+
+/**
+ * pch_start() - Generate I2C start condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ *
+ * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
+ */
+static void pch_start(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ dev_dbg(adap->pch_adapter.dev.parent, "In %s : I2CCTL = %x\n",
+ __func__, ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+}
+
+/**
+ * pch_wait_for_xfer_complete() - initiates a wait for the tx complete event
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
+{
+ s32 ret;
+ ret = wait_event_interruptible_timeout(pch_event,
+ (adap->pch_event_flag != 0), msecs_to_jiffies(50));
+ if (ret < 0)
+ goto out;
+
+ if (ret == 0) {
+ ret = -ETIMEDOUT;
+ goto out;
+ }
+
+ if (adap->pch_event_flag & I2C_ERROR_MASK) {
+ ret = -EIO;
+ dev_err(adap->pch_adapter.dev.parent,
+ "error bits set: %x\n", adap->pch_event_flag);
+ goto out;
+ }
+
+ adap->pch_event_flag = 0;
+ ret = 0;
+out:
+ return ret;
+}
+
+/**
+ * pch_getack() - to confirm ACK/NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static s32 pch_getack(struct i2c_algo_pch_data *adap)
+{
+ u32 reg_val;
+ void __iomem *p = adap->pch_base_address;
+ reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
+
+ if (reg_val == 0)
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : return 0\n",
+ __func__);
+ else
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : return%d\n",
+ __func__, -EPROTO);
+
+ return (((reg_val) == 0) ? (0) : (-EPROTO));
+}
+
+/**
+ * pch_stop() - generate stop condition in normal mode.
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_stop(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : I2CCTL = %x\n", __func__,
+ ioread32(p + PCH_I2CCTL));
+ /* clear the start bit */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_START);
+}
+
+/**
+ * pch_repstart() - generate repeated start condition in normal mode
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_repstart(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ dev_dbg(adap->pch_adapter.dev.parent, "In %s : I2CCTL = %x\n",
+ __func__, ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_REPSTART);
+}
+
+/**
+ * pch_writebytes() - write data to I2C bus in normal mode
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @last: specifies whether last message or not.
+ * In the case of compound mode it will be 1 for last message,
+ * otherwise 0.
+ * @first: specifies whether first message or not.
+ * 1 for first message otherwise 0.
+ */
+static s32 pch_writebytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+ u8 *buf;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ u32 addr_8_lsb;
+ s32 wrcount;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+ /* enable master tx */
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s : I2CCTL = %x msgs->len = %d\n", __func__,
+ ioread32(p + PCH_I2CCTL), length);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ addr_8_lsb = (addr & I2C_ADDR_MSK);
+ iowrite32(addr_8_lsb, p + PCH_I2CDR);
+ } else {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } else {
+ /* set 7 bit slave address and R/W bit as 0 */
+ iowrite32(addr << 1, p + PCH_I2CDR);
+ if (first)
+ pch_start(adap);
+ }
+
+ if ((pch_wait_for_xfer_complete(adap) == 0) &&
+ (pch_getack(adap) == 0)) {
+ for (wrcount = 0; wrcount < length; ++wrcount) {
+ /* write buffer value to I2C data register */
+ iowrite32(buf[wrcount], p + PCH_I2CDR);
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s : writing %x to Data register\n",
+ __func__, buf[wrcount]);
+
+ if (pch_wait_for_xfer_complete(adap) != 0) {
+ wrcount = -ETIME;
+ break;
+ }
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s return %d", __func__, 0);
+
+ if (pch_getack(adap)) {
+ wrcount = -ETIME;
+ break;
+ }
+ }
+
+ /* check if this is the last message */
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+ } else {
+ pch_stop(adap);
+ }
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s return=%d\n", __func__, wrcount);
+
+ return wrcount;
+}
+
+/**
+ * pch_sendack() - send ACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : I2CCTL = %x\n", __func__,
+ ioread32(p + PCH_I2CCTL));
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+}
+
+/**
+ * pch_sendnack() - send NACK
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_sendnack(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : I2CCTL = %x\n", __func__,
+ ioread32(p + PCH_I2CCTL));
+ pch_setbit((adap->pch_base_address), PCH_I2CCTL, PCH_ACK);
+}
+
+/**
+ * pch_readbytes() - read data from I2C bus in normal mode.
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @last: specifies whether last message or not.
+ * @first: specifies whether first message or not.
+ */
+s32 pch_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+ u32 last, u32 first)
+{
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ u8 *buf;
+ u32 count;
+ u32 length;
+ u32 addr;
+ u32 addr_2_msb;
+ void __iomem *p = adap->pch_base_address;
+ length = msgs->len;
+ buf = msgs->buf;
+ addr = msgs->addr;
+
+ /* enable master reception */
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL, I2C_TX_MODE);
+
+ if (first) {
+ if (pch_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
+ return -ETIME;
+ }
+
+ if (msgs->flags & I2C_M_TEN) {
+ addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD));
+ iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
+
+ } else {
+ /* 7 address bits + R/W bit */
+ addr = (((addr) << 1) | (I2C_RD));
+ iowrite32(addr, p + PCH_I2CDR);
+ }
+
+ /* check if it is the first message */
+ if (first)
+ pch_start(adap);
+
+ if ((pch_wait_for_xfer_complete(adap) == 0)
+ && (pch_getack(adap) == 0)) {
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s return %d", __func__, 0);
+
+ if (length == 0) {
+ pch_stop(adap);
+ ioread32(p + PCH_I2CDR); /* Dummy read needs */
+
+ count = length;
+ } else {
+ int read_index;
+ int loop;
+ pch_sendack(adap);
+
+ /* Dummy read */
+ for (loop = 1, read_index = 0; loop < length; loop++) {
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (loop != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) != 0) {
+ pch_stop(adap);
+ return -ETIME;
+ }
+ } /* end for */
+
+ pch_sendnack(adap);
+
+ buf[read_index] = ioread32(p + PCH_I2CDR);
+
+ if (length != 1)
+ read_index++;
+
+ if (pch_wait_for_xfer_complete(adap) == 0) {
+ if (last)
+ pch_stop(adap);
+ else
+ pch_repstart(adap);
+
+ buf[read_index++] = ioread32(p + PCH_I2CDR);
+ count = read_index;
+ } else {
+ count = -ETIME;
+ }
+
+ }
+ } else {
+ count = -ETIME;
+ pch_stop(adap);
+ }
+
+ return count;
+}
+
+/**
+ * pch_cb_ch0() - Interrupt handler Call back function
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_cb_ch0(struct i2c_algo_pch_data *adap)
+{
+ u32 sts;
+ void __iomem *p = adap->pch_base_address;
+
+ sts = ioread32(p + PCH_I2CSR);
+ sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
+ if (I2CMAL_BIT & sts)
+ adap->pch_event_flag |= I2CMAL_EVENT;
+
+ if (I2CMCF_BIT & sts)
+ adap->pch_event_flag |= I2CMCF_EVENT;
+
+ /* clear the applicable bits */
+ pch_clrbit((adap->pch_base_address), PCH_I2CSR, sts);
+
+ dev_dbg(adap->pch_adapter.dev.parent, "%s : PCH_I2CSR = %x\n",
+ __func__, ioread32(p + PCH_I2CSR));
+
+ wake_up_interruptible(&pch_event);
+}
+
+/**
+ * pch_handler_ch0() - interrupt handler for the PCH I2C controller
+ * @irq: irq number.
+ * @pData: cookie passed back to the handler function.
+ */
+static irqreturn_t pch_handler_ch0(int irq, void *pData)
+{
+ s32 reg_val;
+
+ struct i2c_algo_pch_data *adap_data = (struct i2c_algo_pch_data *)pData;
+ void __iomem *p = adap_data->pch_base_address;
+ u32 mode = ioread32(p + PCH_I2CMOD) & (BUFFER_MODE | EEPROM_SR_MODE);
+
+ if (mode == NORMAL_MODE) {
+ reg_val = ioread32(p + PCH_I2CSR);
+ if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT))
+ pch_cb_ch0(adap_data);
+ else
+ goto err_out;
+ } else {
+ dev_err(adap_data->pch_adapter.dev.parent,
+ "%s I2C mode is not supported\n", __func__);
+ goto err_out;
+ }
+ return IRQ_HANDLED;
+
+err_out:
+ return IRQ_NONE;
+}
+
+/**
+ * pch_xfer() - Reading adnd writing data through I2C bus
+ * @i2c_adap: Pointer to the struct i2c_adapter.
+ * @msgs: Pointer to i2c_msg structure.
+ * @num: number of messages.
+ */
+static s32 pch_xfer(struct i2c_adapter *i2c_adap,
+ struct i2c_msg *msgs, s32 num)
+{
+ struct i2c_msg *pmsg;
+ u32 i;
+ u32 status;
+ u32 msglen;
+ u32 subaddrlen;
+ s32 ret;
+
+ struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
+
+ ret = mutex_lock_interruptible(&pch_mutex);
+ if (ret) {
+ ret = -ERESTARTSYS;
+ goto return_err_nomutex;
+ }
+ if (adap->p_adapter_info->pch_suspended == false) {
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s adap->p_adapter_info->pch_suspended is %d\n",
+ __func__, adap->p_adapter_info->pch_suspended);
+ /* transfer not completed */
+ adap->pch_xfer_in_progress = true;
+
+ ret = -EBUSY;
+ for (i = 0; i < num; i++) {
+ pmsg = &msgs[i];
+ pmsg->flags |= adap->pch_buff_mode_en;
+ status = pmsg->flags;
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "After invoking I2C_MODE_SEL :flag= 0x%x\n",
+ status);
+ /* calculate sub address length and message length */
+ /* these are applicable only for buffer mode */
+ subaddrlen = pmsg->buf[0];
+ /* calculate actual message length excluding
+ * the sub address fields */
+ msglen = (pmsg->len) - (subaddrlen + 1);
+ if (status & (I2C_M_RD)) {
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s invoking pch_readbytes\n",
+ __func__);
+ ret = pch_readbytes(i2c_adap, pmsg,
+ (i + 1 == num),
+ (i == 0));
+ } else {
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "%s invoking pch_writebytes\n",
+ __func__);
+ ret = pch_writebytes(i2c_adap, pmsg,
+ (i + 1 == num),
+ (i == 0));
+ }
+
+ }
+
+ adap->pch_xfer_in_progress = false; /* transfer completed */
+
+ dev_dbg(adap->pch_adapter.dev.parent,
+ "adap->pch_xfer_in_progress is %d\n",
+ adap->pch_xfer_in_progress);
+ } else {
+ ret = -EBUSY;
+ }
+
+ mutex_unlock(&pch_mutex);
+return_err_nomutex:
+ dev_dbg(adap->pch_adapter.dev.parent, "%s return:%d\n\n\n\n",
+ __func__, ret);
+ return ret;
+}
+
+/**
+ * pch_func() - return the functionality of the I2C driver
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static u32 pch_func(struct i2c_adapter *adap)
+{
+ u32 ret;
+ ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
+ return ret;
+}
+
+static struct i2c_algorithm pch_algorithm = {
+ .master_xfer = pch_xfer,
+ .functionality = pch_func
+};
+
+/**
+ * pch_disbl_int() - Disable PCH I2C interrupts
+ * @adap: Pointer to struct i2c_algo_pch_data.
+ */
+static void pch_disbl_int(struct i2c_algo_pch_data *adap)
+{
+ void __iomem *p = adap->pch_base_address;
+
+ pch_clrbit((adap->pch_base_address), PCH_I2CCTL,
+ NORMAL_INTR_ENBL);
+
+ iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
+
+ iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
+}
+
+static int __devinit pch_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ int i;
+ void __iomem *base_addr;
+ s32 ret;
+ struct adapter_info *adap_info =
+ kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
+
+ dev_dbg(&pdev->dev, "Enterred in %s\n", __func__);
+
+ if (adap_info == NULL) {
+ dev_err(&pdev->dev, "Memory allocation failed FAILED");
+ ret = -ENOMEM;
+ goto return_err;
+ }
+
+ ret = pci_enable_device(pdev);
+ if (ret) {
+ dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__);
+ goto err_pci_enable;
+ }
+
+ ret = pci_request_regions(pdev, MODULE_NAME);
+ if (ret) {
+ dev_err(&pdev->dev, "pci_request_regions FAILED");
+ goto err_pci_req;
+ }
+
+ base_addr = pci_iomap(pdev, 1, 0);
+
+ if (base_addr == 0) {
+ dev_err(&pdev->dev, "pci_iomap FAILED");
+ ret = -ENOMEM;
+ goto err_pci_iomap;
+ }
+
+ adap_info->pch_suspended = false;
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ adap_info->pch_data[i].p_adapter_info = adap_info;
+
+ adap_info->pch_data[i].pch_adapter.owner = THIS_MODULE;
+ adap_info->pch_data[i].pch_adapter.class = I2C_CLASS_HWMON;
+ strcpy(adap_info->pch_data[i].pch_adapter.name, "pch_i2c");
+ adap_info->pch_data[i].pch_adapter.algo = &pch_algorithm;
+ adap_info->pch_data[i].pch_adapter.algo_data =
+ &adap_info->pch_data[i];
+
+ /* (i * 0x80) + base_addr; */
+ adap_info->pch_data[i].pch_base_address = base_addr;
+
+ adap_info->pch_data[i].pch_adapter.dev.parent = &pdev->dev;
+
+ ret = i2c_add_adapter(&(adap_info->pch_data[i].pch_adapter));
+
+ if (ret) {
+ dev_err(&pdev->dev, "i2c_add_adapter FAILED");
+ goto err_i2c_add_adapter;
+ }
+
+ pch_init(&adap_info->pch_data[i]);
+ ret = request_irq(pdev->irq, pch_handler_list[i], IRQF_SHARED,
+ MODULE_NAME, &adap_info->pch_data[i]);
+ if (ret) {
+ dev_err(&pdev->dev, "request_irq Failed\n");
+ goto err_request_irq;
+ }
+ }
+
+ dev_dbg(&pdev->dev, "request_irq returns %d pch_probe returns.\n", ret);
+ pci_set_drvdata(pdev, adap_info);
+ return 0;
+
+err_request_irq:
+ for (i = 0; i < PCH_MAX_CHN; i++)
+ i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
+err_i2c_add_adapter:
+ pci_iounmap(pdev, base_addr);
+err_pci_iomap:
+ pci_release_regions(pdev);
+err_pci_req:
+ pci_disable_device(pdev);
+err_pci_enable:
+ kfree(adap_info);
+return_err:
+ return ret;
+}
+
+static void __devexit pch_remove(struct pci_dev *pdev)
+{
+ int i;
+
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ pch_disbl_int(&adap_info->pch_data[i]);
+ free_irq(pdev->irq, &adap_info->pch_data[i]);
+ i2c_del_adapter(&(adap_info->pch_data[i].pch_adapter));
+ }
+
+ if (adap_info->pch_data[0].pch_base_address) {
+ pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
+ adap_info->pch_data[0].pch_base_address = 0;
+ }
+
+ pci_set_drvdata(pdev, NULL);
+
+ pci_release_regions(pdev);
+
+ pci_disable_device(pdev);
+ kfree(adap_info);
+}
+
+#ifdef CONFIG_PM
+static int pch_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ int i;
+ int ret;
+
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+ void __iomem *p = adap_info->pch_data[0].pch_base_address;
+
+ adap_info->pch_suspended = true;
+
+ for (i = 0; i < PCH_MAX_CHN; i++) {
+ while ((adap_info->pch_data[i].pch_xfer_in_progress)) {
+ /* It is assumed that any pending transfer will
+ * be completed after the delay
+ */
+ msleep(1);
+ }
+ /* Disable the i2c interrupts */
+ pch_disbl_int(&adap_info->pch_data[i]);
+ }
+
+ dev_dbg(&pdev->dev,
+ "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
+ "invoked function pch_disbl_int successfully\n",
+ ioread32(p + 0x08),
+ ioread32(p + 0x30),
+ ioread32(p + 0x44));
+
+ ret = pci_save_state(pdev);
+
+ if (ret) {
+ dev_err(&pdev->dev, "pci_save_state failed\n");
+ return ret;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+ pci_disable_device(pdev);
+ pci_set_power_state(pdev, pci_choose_state(pdev, state));
+
+ return 0;
+}
+
+static int pch_resume(struct pci_dev *pdev)
+{
+ struct adapter_info *adap_info = pci_get_drvdata(pdev);
+ int i;
+
+ pci_set_power_state(pdev, PCI_D0);
+ pci_restore_state(pdev);
+
+ if (pci_enable_device(pdev) < 0) {
+ dev_err(&pdev->dev, "pci_enable_device failed in pch_resume\n");
+ return -EIO;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+
+ for (i = 0; i < PCH_MAX_CHN; i++)
+ pch_init(&adap_info->pch_data[i]);
+
+ adap_info->pch_suspended = false;
+
+ return 0;
+}
+#else
+#define pch_suspend NULL
+#define pch_resume NULL
+#endif
+
+static struct pci_driver pch_pcidriver = {
+ .name = "pch_i2c",
+ .id_table = pch_pcidev_id,
+ .probe = pch_probe,
+ .remove = __devexit_p(pch_remove),
+ .suspend = pch_suspend,
+ .resume = pch_resume
+};
+
+static int __init pch_pci_init(void)
+{
+ return pci_register_driver(&pch_pcidriver);
+}
+
+static void __exit pch_pci_exit(void)
+{
+ pci_unregister_driver(&pch_pcidriver);
+}
+
+MODULE_DESCRIPTION("PCH I2C PCI Driver");
+MODULE_LICENSE("GPL");
+module_init(pch_pci_init);
+module_exit(pch_pci_exit);
+module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
+module_param(pch_clk, int, (S_IRUSR | S_IWUSR));
--
1.6.0.6
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
[not found] ` <20100806142418.GA4921@suse.de>
@ 2010-09-01 1:57 ` Masayuki Ohtake
0 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtake @ 2010-09-01 1:57 UTC (permalink / raw)
To: Greg KH
Cc: ML linux-kernel, margie.foster, alan, arjan, Andrew, Wang Qi,
Wang Yong Y, meego-dev
Hi, Greg
Sorry for late response.
Thanks, Ohtake(OKISemi)
----- Original Message -----
From: "Greg KH" <gregkh@suse.de>
To: "Masayuki Ohtak" <masa-korg@dsn.okisemi.com>
Cc: <meego-dev@meego.com>; "Wang Yong Y" <yong.y.wang@intel.com>; "Wang Qi" <qi.wang@intel.com>; "Andrew"
<andrew.chih.howe.khor@intel.com>; <arjan@linux.intel.com>; <alan@linux.intel.com>; <margie.foster@intel.com>
Sent: Friday, August 06, 2010 11:24 PM
Subject: Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
> On Fri, Aug 06, 2010 at 01:33:24PM +0900, Masayuki Ohtak wrote:
> > I2C driver of Topcliff PCH
> >
> > Topcliff PCH is the platform controller hub that is going to be used in
> > Intel's upcoming general embedded platform. All IO peripherals in
> > Topcliff PCH are actually devices sitting on AMBA bus.
> > Topcliff PCH has I2C I/F. Using this I/F, it is able to access system
> > devices connected to I2C.
> >
> > Signed-off-by: Masayuki Ohtake <masa-korg@dsn.okisemi.com>
>
>
> Why not run this by the i2c maintainer and developers as well?
I will add i2c maintainer and developers next submission.
>
> You do know about the scripts/get_maintainer.pl program to tell you who
> to copy when sending a patch, right? Please use that.
>
> >
> > ---
> > drivers/i2c/busses/Kconfig | 8 +
> > drivers/i2c/busses/Makefile | 3 +
> > drivers/i2c/busses/i2c-pch.c | 910 ++++++++++++++++++++++++++++++++++++++++++
> > drivers/i2c/busses/i2c-pch.h | 147 +++++++
> > drivers/i2c/i2c-dev.c | 21 +
> > 5 files changed, 1089 insertions(+), 0 deletions(-)
> > create mode 100644 drivers/i2c/busses/i2c-pch.c
> > create mode 100644 drivers/i2c/busses/i2c-pch.h
> >
> > diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> > index 5f318ce..98e7201 100644
> > --- a/drivers/i2c/busses/Kconfig
> > +++ b/drivers/i2c/busses/Kconfig
> > @@ -7,6 +7,14 @@ menu "I2C Hardware Bus support"
> > comment "PC SMBus host controller drivers"
> > depends on PCI
> >
> > +config PCH_I2C
> > + tristate "PCH I2C"
> > + depends on PCI
> > + help
> > + This driver is for PCH I2C of Topcliff which is an IOH for x86
> > + embedded processor.
> > + This driver can access PCH I2C bus device.
> > +
> > config I2C_ALI1535
> > tristate "ALI 1535"
> > depends on PCI
> > diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
> > index 302c551..3e6b8d6 100644
> > --- a/drivers/i2c/busses/Makefile
> > +++ b/drivers/i2c/busses/Makefile
> > @@ -75,3 +75,6 @@ obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o
> > ifeq ($(CONFIG_I2C_DEBUG_BUS),y)
> > EXTRA_CFLAGS += -DDEBUG
> > endif
> > +
> > +obj-$(CONFIG_PCH_I2C) += pch_i2c.o
> > +pch_i2c-objs := i2c-pch.o
>
> Why not just name your file i2c-pci.c and then you don't need this
> two-step Makefile mess?
>
> > diff --git a/drivers/i2c/busses/i2c-pch.c b/drivers/i2c/busses/i2c-pch.c
> > new file mode 100644
> > index 0000000..7939781
> > --- /dev/null
> > +++ b/drivers/i2c/busses/i2c-pch.c
> > @@ -0,0 +1,910 @@
> > +/*
> > + * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; version 2 of the License.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
> > + */
> > +
> > +#include <linux/module.h>
> > +#include <linux/kernel.h>
> > +#include <linux/delay.h>
> > +#include <linux/init.h>
> > +#include <linux/errno.h>
> > +#include <linux/i2c.h>
> > +#include <linux/fs.h>
> > +#include <linux/io.h>
> > +#include <linux/types.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/jiffies.h>
> > +#include <linux/pci.h>
> > +#include <linux/mutex.h>
> > +#include <linux/ktime.h>
> > +
> > +#include "i2c-pch.h"
>
> Why do you need a .h file for this driver?
I will delete.
>
> <snip>
>
> > diff --git a/drivers/i2c/i2c-dev.c b/drivers/i2c/i2c-dev.c
> > index f4110aa..53e13de 100644
> > --- a/drivers/i2c/i2c-dev.c
> > +++ b/drivers/i2c/i2c-dev.c
> > @@ -36,6 +36,7 @@
> > #include <linux/i2c-dev.h>
> > #include <linux/jiffies.h>
> > #include <linux/uaccess.h>
> > +#include "busses/i2c-pch.h"
>
> Note how no other i2c driver needs to be included here...
I will delete.
>
> > static struct i2c_driver i2cdev_driver;
> >
> > @@ -372,6 +373,12 @@ static long i2cdev_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
> > struct i2c_client *client = file->private_data;
> > unsigned long funcs;
> >
> > + unsigned long pch_mode;
> > + int ret;
> > +
> > + struct i2c_msg msg;
> > + unsigned char msgbuf[1];
> > +
> > dev_dbg(&client->adapter->dev, "ioctl, cmd=0x%02x, arg=0x%02lx\n",
> > cmd, arg);
> >
> > @@ -427,6 +434,20 @@ static long i2cdev_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
> > */
> > client->adapter->timeout = msecs_to_jiffies(arg * 10);
> > break;
> > + case I2C_MODE_SEL:
> > + pch_mode = arg;
> > +
> > + if (pch_mode <= 4) {
> > + msgbuf[0] = pch_mode;
> > + msg.buf = msgbuf;
> > + msg.len = 1;
> > + msg.flags = 0;
> > + ret = i2c_transfer(client->adapter, &msg, 1);
> > + } else {
> > + printk(KERN_ERR "I2C mode sel:Invalid mode\n");
> > + ret = -EINVAL;
> > + }
> > + return ret;
>
> I really doubt you are allowed to add a new ioctl to the core i2c layer.
> You will have to run this by the i2c maintainer to get it accepted.
>
I will revert i2c core module.
I will submit modified patch soon.
Thanks, Ohtake(OKISemi)
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
[not found] ` <4C5B9229.1040403@linux.intel.com>
@ 2010-09-01 1:50 ` Masayuki Ohtake
0 siblings, 0 replies; 47+ messages in thread
From: Masayuki Ohtake @ 2010-09-01 1:50 UTC (permalink / raw)
To: Arjan van de Ven
Cc: ML linux-kernel, margie.foster, alan, gregkh,
andrew.chih.howe.khor, qi.wang, yong.y.wang, meego-dev
Hi Arjan,
Sorry, for late response.
----- Original Message -----
From: "Arjan van de Ven" <arjan@linux.intel.com>
To: "Masayuki Ohtak" <masa-korg@dsn.okisemi.com>
Cc: <meego-dev@meego.com>; <yong.y.wang@intel.com>; <qi.wang@intel.com>; <andrew.chih.howe.khor@intel.com>;
<gregkh@suse.de>; <alan@linux.intel.com>; <margie.foster@intel.com>
Sent: Friday, August 06, 2010 1:40 PM
Subject: Re: [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35
> On 8/5/2010 9:33 PM, Masayuki Ohtak wrote:
> >
> > +config PCH_I2C
> > + tristate "PCH I2C"
> >
>
> this is really not very descriptive. Can you make it "OKI Semi PCH I2C
> controller" or something
We will modify.
>
> if you has human get asked "PCH I2C"... almost nobody will know what
> that means.+static irqreturn_t pch_handler_ch0(int irq, void *pData);
>
>
> > +static irqreturn_t(*pch_handler_list[PCH_MAX_CHN]) (int irq, void *pData) = {
> > + pch_handler_ch0,
> > +};
> >
>
> hummmmmm what is this for??
This is callback function list for mulit-cahnnel I2C device.
>
>
> > +
> > +static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
> > +{
> > + iowrite32(((ioread32(addr + offset)) | (bitmask)), (addr + offset));
> > +}
> >
>
> this might be more readble if it's made 3 lines with a local variable...
> + "Cleared the registers PCH_I2CCTL,PCH_I2CMOD,PCH_I2CBUFFOR\n,"
>
>
> > + "PCH_I2CBUFSLV,PCH_I2CBUFSUB,PCH_I2CBUFMSK,\n"
> >
I will divide to 3 lines.
>
> what's that weird character ?diff --git a/drivers/i2c/i2c-dev.c
> b/drivers/i2c/i2c-dev.c
> + case I2C_MODE_SEL:
>
>
> > + pch_mode = arg;
> > +
> > + if (pch_mode <= 4) {
> > + msgbuf[0] = pch_mode;
> > + msg.buf = msgbuf;
> > + msg.len = 1;
> > + msg.flags = 0;
> > + ret = i2c_transfer(client->adapter, &msg, 1);
> >
>
> in generic code??
>
>
I will revert i2c-dev.c.
I will submit modified patch soon.
Thanks, Ohtake(OKISemi)
^ permalink raw reply [flat|nested] 47+ messages in thread
end of thread, other threads:[~2010-09-08 12:06 UTC | newest]
Thread overview: 47+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2010-09-01 2:26 [MeeGo-Dev][PATCH] Topcliff: Update PCH_I2C driver to 2.6.35 Masayuki Ohtak
2010-09-01 2:43 ` Joe Perches
2010-09-01 2:43 ` Joe Perches
2010-09-01 4:16 ` Masayuki Ohtake
2010-09-01 4:16 ` Masayuki Ohtake
2010-09-01 5:08 ` Masayuki Ohtake
2010-09-01 5:08 ` Masayuki Ohtake
2010-09-01 5:24 ` Joe Perches
2010-09-01 5:44 ` Masayuki Ohtake
2010-09-01 5:44 ` Masayuki Ohtake
2010-09-01 19:44 ` Linus Walleij
2010-09-01 19:44 ` Linus Walleij
2010-09-03 3:12 ` Masayuki Ohtake
2010-09-03 3:12 ` Masayuki Ohtake
-- strict thread matches above, loose matches on Subject: below --
2010-09-06 1:31 Masayuki Ohtak
2010-09-06 1:31 ` Masayuki Ohtak
2010-09-06 1:10 Masayuki Ohtak
2010-09-06 1:10 ` Masayuki Ohtak
2010-09-03 10:19 Masayuki Ohtak
2010-09-03 10:19 ` Masayuki Ohtak
2010-09-03 12:36 ` Alan Cox
2010-09-03 12:36 ` Alan Cox
2010-09-03 12:26 ` Wolfram Sang
2010-09-03 12:26 ` Wolfram Sang
2010-09-06 0:44 ` Masayuki Ohtake
2010-09-06 0:44 ` Masayuki Ohtake
2010-09-06 0:43 ` Masayuki Ohtake
2010-09-06 0:43 ` Masayuki Ohtake
2010-09-07 23:55 ` Ben Dooks
2010-09-07 23:55 ` Ben Dooks
2010-09-08 12:06 ` Masayuki Ohtake
2010-09-08 12:06 ` Masayuki Ohtake
2010-09-03 7:15 Masayuki Ohtak
2010-09-03 7:15 ` Masayuki Ohtak
2010-09-03 8:10 ` Joe Perches
2010-09-03 8:10 ` Joe Perches
2010-09-03 10:01 ` Masayuki Ohtake
2010-09-03 10:01 ` Masayuki Ohtake
2010-09-03 3:19 Masayuki Ohtak
2010-09-03 3:19 ` Masayuki Ohtak
2010-09-03 4:38 ` Joe Perches
2010-09-03 4:38 ` Joe Perches
2010-09-03 8:39 ` Linus WALLEIJ
[not found] ` <4C80692E.80004-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>
2010-09-03 8:39 ` Linus WALLEIJ
2010-09-01 2:26 Masayuki Ohtak
[not found] <4C5B9094.5090205@dsn.okisemi.com>
[not found] ` <4C5B9229.1040403@linux.intel.com>
2010-09-01 1:50 ` Masayuki Ohtake
[not found] ` <20100806142418.GA4921@suse.de>
2010-09-01 1:57 ` Masayuki Ohtake
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