All of lore.kernel.org
 help / color / mirror / Atom feed
From: "A.s. Dong" <aisheng.dong@nxp.com>
To: "A.s. Dong" <aisheng.dong@nxp.com>,
	"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"sboyd@codeaurora.org" <sboyd@codeaurora.org>,
	"mturquette@baylibre.com" <mturquette@baylibre.com>,
	"dongas86@gmail.com" <dongas86@gmail.com>,
	"shawnguo@kernel.org" <shawnguo@kernel.org>,
	Anson Huang <anson.huang@nxp.com>, Jacky Bai <ping.bai@nxp.com>
Subject: RE: [PATCH V2 00/10] clk: add imx7ulp clk support
Date: Wed, 26 Jul 2017 02:57:32 +0000	[thread overview]
Message-ID: <AM3PR04MB306D2D23526F1737DA4249B80B90@AM3PR04MB306.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <1499946435-7177-1-git-send-email-aisheng.dong@nxp.com>

Ping...

> -----Original Message-----
> From: Dong Aisheng [mailto:aisheng.dong@nxp.com]
> Sent: Thursday, July 13, 2017 7:47 PM
> To: linux-clk@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> sboyd@codeaurora.org; mturquette@baylibre.com; A.s. Dong;
> dongas86@gmail.com; shawnguo@kernel.org; Anson Huang; Jacky Bai
> Subject: [PATCH V2 00/10] clk: add imx7ulp clk support
> 
> This patch series intends to add imx7ulp clk support.
> 
> i.MX7ULP Clock functions are under joint control of the System Clock
> Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core
> Mode Controller (CMC)1 blocks
> 
> The clocking scheme provides clear separation between M4 domain and A7
> domain. Except for a few clock sources shared between two domains, such as
> the System Oscillator clock, the Slow IRC (SIRC), and and the Fast IRC
> clock (FIRCLK), clock sources and clock management are separated and
> contained within each domain.
> 
> M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
> A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
> 
> Note: this series only adds A7 clock domain support as M4 clock domain
> will be handled by M4 seperately.
> 
> Change Log:
> v1->v2:
>  * add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers
>  * use clk_hw apis to register clocks
>  * use of_clk_add_hw_provider
>  * split the clocks register process into two parts: early part for
> possible
>    timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part
> for
>    the left normal peripheral clocks registered by a platform driver.
> 
> Dong Aisheng (10):
>   clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support
>   clk: reparent orphans after critical clocks enabled
>   clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support
>   clk: imx: add pllv4 support
>   clk: imx: add pfdv2 support
>   clk: imx: add composite clk support
>   dt-bindings: clock: add imx7ulp clock binding doc
>   clk: imx: make mux parent strings const
>   clk: imx: implement new clk_hw based APIs
>   clk: imx: add imx7ulp clk driver
> 
>  .../devicetree/bindings/clock/imx7ulp-clock.txt    |  62 ++++++
>  drivers/clk/clk-divider.c                          | 100 ++++++++-
>  drivers/clk/clk-fractional-divider.c               |  10 +
>  drivers/clk/clk.c                                  |  39 ++--
>  drivers/clk/imx/Makefile                           |   6 +-
>  drivers/clk/imx/clk-busy.c                         |   2 +-
>  drivers/clk/imx/clk-composite.c                    |  90 ++++++++
>  drivers/clk/imx/clk-fixup-mux.c                    |   2 +-
>  drivers/clk/imx/clk-imx7ulp.c                      | 245
> +++++++++++++++++++++
>  drivers/clk/imx/clk-pfdv2.c                        | 207
> +++++++++++++++++
>  drivers/clk/imx/clk-pllv4.c                        | 188 ++++++++++++++++
>  drivers/clk/imx/clk.c                              |  22 ++
>  drivers/clk/imx/clk.h                              |  92 +++++++-
>  include/dt-bindings/clock/imx7ulp-clock.h          | 108 +++++++++
>  include/linux/clk-provider.h                       |  17 ++
>  15 files changed, 1159 insertions(+), 31 deletions(-)  create mode 100644
> Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
>  create mode 100644 drivers/clk/imx/clk-composite.c  create mode 100644
> drivers/clk/imx/clk-imx7ulp.c  create mode 100644 drivers/clk/imx/clk-
> pfdv2.c  create mode 100644 drivers/clk/imx/clk-pllv4.c  create mode
> 100644 include/dt-bindings/clock/imx7ulp-clock.h
> 
> --
> 2.7.4

WARNING: multiple messages have this Message-ID (diff)
From: "A.s. Dong" <aisheng.dong@nxp.com>
To: "A.s. Dong" <aisheng.dong@nxp.com>,
	"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"sboyd@codeaurora.org" <sboyd@codeaurora.org>,
	"mturquette@baylibre.com" <mturquette@baylibre.com>,
	"dongas86@gmail.com" <dongas86@gmail.com>,
	"shawnguo@kernel.org" <shawnguo@kernel.org>,
	Anson Huang <anson.huang@nxp.com>, Jacky Bai <ping.bai@nxp.com>
Subject: RE: [PATCH V2 00/10] clk: add imx7ulp clk support
Date: Wed, 26 Jul 2017 02:57:32 +0000	[thread overview]
Message-ID: <AM3PR04MB306D2D23526F1737DA4249B80B90@AM3PR04MB306.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <1499946435-7177-1-git-send-email-aisheng.dong@nxp.com>

Ping...

> -----Original Message-----
> From: Dong Aisheng [mailto:aisheng.dong@nxp.com]
> Sent: Thursday, July 13, 2017 7:47 PM
> To: linux-clk@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> sboyd@codeaurora.org; mturquette@baylibre.com; A.s. Dong;
> dongas86@gmail.com; shawnguo@kernel.org; Anson Huang; Jacky Bai
> Subject: [PATCH V2 00/10] clk: add imx7ulp clk support
>=20
> This patch series intends to add imx7ulp clk support.
>=20
> i.MX7ULP Clock functions are under joint control of the System Clock
> Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Cor=
e
> Mode Controller (CMC)1 blocks
>=20
> The clocking scheme provides clear separation between M4 domain and A7
> domain. Except for a few clock sources shared between two domains, such a=
s
> the System Oscillator clock, the Slow IRC (SIRC), and and the Fast IRC
> clock (FIRCLK), clock sources and clock management are separated and
> contained within each domain.
>=20
> M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
> A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
>=20
> Note: this series only adds A7 clock domain support as M4 clock domain
> will be handled by M4 seperately.
>=20
> Change Log:
> v1->v2:
>  * add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers
>  * use clk_hw apis to register clocks
>  * use of_clk_add_hw_provider
>  * split the clocks register process into two parts: early part for
> possible
>    timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part
> for
>    the left normal peripheral clocks registered by a platform driver.
>=20
> Dong Aisheng (10):
>   clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support
>   clk: reparent orphans after critical clocks enabled
>   clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support
>   clk: imx: add pllv4 support
>   clk: imx: add pfdv2 support
>   clk: imx: add composite clk support
>   dt-bindings: clock: add imx7ulp clock binding doc
>   clk: imx: make mux parent strings const
>   clk: imx: implement new clk_hw based APIs
>   clk: imx: add imx7ulp clk driver
>=20
>  .../devicetree/bindings/clock/imx7ulp-clock.txt    |  62 ++++++
>  drivers/clk/clk-divider.c                          | 100 ++++++++-
>  drivers/clk/clk-fractional-divider.c               |  10 +
>  drivers/clk/clk.c                                  |  39 ++--
>  drivers/clk/imx/Makefile                           |   6 +-
>  drivers/clk/imx/clk-busy.c                         |   2 +-
>  drivers/clk/imx/clk-composite.c                    |  90 ++++++++
>  drivers/clk/imx/clk-fixup-mux.c                    |   2 +-
>  drivers/clk/imx/clk-imx7ulp.c                      | 245
> +++++++++++++++++++++
>  drivers/clk/imx/clk-pfdv2.c                        | 207
> +++++++++++++++++
>  drivers/clk/imx/clk-pllv4.c                        | 188 +++++++++++++++=
+
>  drivers/clk/imx/clk.c                              |  22 ++
>  drivers/clk/imx/clk.h                              |  92 +++++++-
>  include/dt-bindings/clock/imx7ulp-clock.h          | 108 +++++++++
>  include/linux/clk-provider.h                       |  17 ++
>  15 files changed, 1159 insertions(+), 31 deletions(-)  create mode 10064=
4
> Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
>  create mode 100644 drivers/clk/imx/clk-composite.c  create mode 100644
> drivers/clk/imx/clk-imx7ulp.c  create mode 100644 drivers/clk/imx/clk-
> pfdv2.c  create mode 100644 drivers/clk/imx/clk-pllv4.c  create mode
> 100644 include/dt-bindings/clock/imx7ulp-clock.h
>=20
> --
> 2.7.4

WARNING: multiple messages have this Message-ID (diff)
From: aisheng.dong@nxp.com (A.s. Dong)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH V2 00/10] clk: add imx7ulp clk support
Date: Wed, 26 Jul 2017 02:57:32 +0000	[thread overview]
Message-ID: <AM3PR04MB306D2D23526F1737DA4249B80B90@AM3PR04MB306.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <1499946435-7177-1-git-send-email-aisheng.dong@nxp.com>

Ping...

> -----Original Message-----
> From: Dong Aisheng [mailto:aisheng.dong at nxp.com]
> Sent: Thursday, July 13, 2017 7:47 PM
> To: linux-clk at vger.kernel.org
> Cc: linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> sboyd at codeaurora.org; mturquette at baylibre.com; A.s. Dong;
> dongas86 at gmail.com; shawnguo at kernel.org; Anson Huang; Jacky Bai
> Subject: [PATCH V2 00/10] clk: add imx7ulp clk support
> 
> This patch series intends to add imx7ulp clk support.
> 
> i.MX7ULP Clock functions are under joint control of the System Clock
> Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core
> Mode Controller (CMC)1 blocks
> 
> The clocking scheme provides clear separation between M4 domain and A7
> domain. Except for a few clock sources shared between two domains, such as
> the System Oscillator clock, the Slow IRC (SIRC), and and the Fast IRC
> clock (FIRCLK), clock sources and clock management are separated and
> contained within each domain.
> 
> M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
> A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
> 
> Note: this series only adds A7 clock domain support as M4 clock domain
> will be handled by M4 seperately.
> 
> Change Log:
> v1->v2:
>  * add enable/disable for the type of CLK_DIVIDER_ZERO_GATE dividers
>  * use clk_hw apis to register clocks
>  * use of_clk_add_hw_provider
>  * split the clocks register process into two parts: early part for
> possible
>    timers clocks registered by CLK_OF_DECLARE_DRIVER and the later part
> for
>    the left normal peripheral clocks registered by a platform driver.
> 
> Dong Aisheng (10):
>   clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support
>   clk: reparent orphans after critical clocks enabled
>   clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support
>   clk: imx: add pllv4 support
>   clk: imx: add pfdv2 support
>   clk: imx: add composite clk support
>   dt-bindings: clock: add imx7ulp clock binding doc
>   clk: imx: make mux parent strings const
>   clk: imx: implement new clk_hw based APIs
>   clk: imx: add imx7ulp clk driver
> 
>  .../devicetree/bindings/clock/imx7ulp-clock.txt    |  62 ++++++
>  drivers/clk/clk-divider.c                          | 100 ++++++++-
>  drivers/clk/clk-fractional-divider.c               |  10 +
>  drivers/clk/clk.c                                  |  39 ++--
>  drivers/clk/imx/Makefile                           |   6 +-
>  drivers/clk/imx/clk-busy.c                         |   2 +-
>  drivers/clk/imx/clk-composite.c                    |  90 ++++++++
>  drivers/clk/imx/clk-fixup-mux.c                    |   2 +-
>  drivers/clk/imx/clk-imx7ulp.c                      | 245
> +++++++++++++++++++++
>  drivers/clk/imx/clk-pfdv2.c                        | 207
> +++++++++++++++++
>  drivers/clk/imx/clk-pllv4.c                        | 188 ++++++++++++++++
>  drivers/clk/imx/clk.c                              |  22 ++
>  drivers/clk/imx/clk.h                              |  92 +++++++-
>  include/dt-bindings/clock/imx7ulp-clock.h          | 108 +++++++++
>  include/linux/clk-provider.h                       |  17 ++
>  15 files changed, 1159 insertions(+), 31 deletions(-)  create mode 100644
> Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
>  create mode 100644 drivers/clk/imx/clk-composite.c  create mode 100644
> drivers/clk/imx/clk-imx7ulp.c  create mode 100644 drivers/clk/imx/clk-
> pfdv2.c  create mode 100644 drivers/clk/imx/clk-pllv4.c  create mode
> 100644 include/dt-bindings/clock/imx7ulp-clock.h
> 
> --
> 2.7.4

  parent reply	other threads:[~2017-07-26  2:57 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-13 11:47 [PATCH V2 00/10] clk: add imx7ulp clk support Dong Aisheng
2017-07-13 11:47 ` Dong Aisheng
2017-07-13 11:47 ` [PATCH V2 01/10] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE " Dong Aisheng
2017-07-13 11:47   ` Dong Aisheng
2017-11-02  7:50   ` Stephen Boyd
2017-11-02  7:50     ` Stephen Boyd
2017-12-20 14:27     ` Dong Aisheng
2017-12-20 14:27       ` Dong Aisheng
2017-12-22  1:24       ` Stephen Boyd
2017-12-22  1:24         ` Stephen Boyd
2017-12-22  3:42         ` Dong Aisheng
2017-12-22  3:42           ` Dong Aisheng
2018-01-17  3:00         ` Dong Aisheng
2018-01-17  3:00           ` Dong Aisheng
2017-07-13 11:47 ` [PATCH V2 02/10] clk: reparent orphans after critical clocks enabled Dong Aisheng
2017-07-13 11:47   ` Dong Aisheng
2017-11-02  7:36   ` Stephen Boyd
2017-11-02  7:36     ` Stephen Boyd
2017-12-20 14:33     ` Dong Aisheng
2017-12-20 14:33       ` Dong Aisheng
2017-12-21 18:32       ` Stephen Boyd
2017-12-21 18:32         ` Stephen Boyd
2017-12-22  1:55         ` Stephen Boyd
2017-12-22  1:55           ` Stephen Boyd
2017-12-22  2:54           ` Dong Aisheng
2017-12-22  2:54             ` Dong Aisheng
2017-07-13 11:47 ` [PATCH V2 03/10] clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support Dong Aisheng
2017-07-13 11:47   ` Dong Aisheng
2017-07-13 11:47 ` [PATCH V2 04/10] clk: imx: add pllv4 support Dong Aisheng
2017-07-13 11:47   ` Dong Aisheng
2017-07-13 11:47 ` [PATCH V2 05/10] clk: imx: add pfdv2 support Dong Aisheng
2017-07-13 11:47   ` Dong Aisheng
2017-07-13 11:47 ` [PATCH V2 06/10] clk: imx: add composite clk support Dong Aisheng
2017-07-13 11:47   ` Dong Aisheng
2017-07-13 11:47 ` [PATCH V2 07/10] dt-bindings: clock: add imx7ulp clock binding doc Dong Aisheng
2017-07-13 11:47   ` Dong Aisheng
2017-07-13 11:47 ` [PATCH V2 08/10] clk: imx: make mux parent strings const Dong Aisheng
2017-07-13 11:47   ` Dong Aisheng
2017-07-13 11:47 ` [PATCH V2 09/10] clk: imx: implement new clk_hw based APIs Dong Aisheng
2017-07-13 11:47   ` Dong Aisheng
2017-07-13 11:47 ` [PATCH V2 10/10] clk: imx: add imx7ulp clk driver Dong Aisheng
2017-07-13 11:47   ` Dong Aisheng
2017-07-26  2:57 ` A.s. Dong [this message]
2017-07-26  2:57   ` [PATCH V2 00/10] clk: add imx7ulp clk support A.s. Dong
2017-07-26  2:57   ` A.s. Dong
2017-08-24  7:05 ` A.s. Dong
2017-08-24  7:05   ` A.s. Dong
2017-08-24  7:05   ` A.s. Dong
2017-09-11  7:25 ` Dong Aisheng
2017-09-11  7:25   ` Dong Aisheng

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=AM3PR04MB306D2D23526F1737DA4249B80B90@AM3PR04MB306.eurprd04.prod.outlook.com \
    --to=aisheng.dong@nxp.com \
    --cc=anson.huang@nxp.com \
    --cc=dongas86@gmail.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-clk@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mturquette@baylibre.com \
    --cc=ping.bai@nxp.com \
    --cc=sboyd@codeaurora.org \
    --cc=shawnguo@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.