* [U-Boot] T2080 l2-cache-controller compatible string overwritten by ft_fixup_l2cache @ 2016-11-23 9:43 Chris Packham 2016-11-23 17:41 ` york sun 0 siblings, 1 reply; 10+ messages in thread From: Chris Packham @ 2016-11-23 9:43 UTC (permalink / raw) To: u-boot Hi, I was just looking at what it would take to add the T2080 L2 cache to the mpc85xx_edac driver in Linux. At a cursory glance all the registers appear to be there so I figured I'd just add the appropriate entry to the of match table. To my surprise I found that the compatible string in my device tree was overwritten with "cache". I've tracked this down to the CONFIG_SYS_FSL_QORIQ_CHASSIS2 implementation of ft_fixup_l2cache in u-boot. The CONFIG_L2_CACHE version seems to take care to update the device tree node to compatible = "fsl,t2080-l2-cache-controller", "cache"; but the CONFIG_SYS_FSL_QORIQ_CHASSIS2 version just sets this to compatible = "cache"; Is this an over-site or is it intentional? Thanks, Chris ^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] T2080 l2-cache-controller compatible string overwritten by ft_fixup_l2cache 2016-11-23 9:43 [U-Boot] T2080 l2-cache-controller compatible string overwritten by ft_fixup_l2cache Chris Packham @ 2016-11-23 17:41 ` york sun 2016-11-28 23:52 ` [U-Boot] [PATCH] arch: powerpc: Retain compatible property for L2 cache Chris Packham 2016-11-29 3:10 ` [U-Boot] [PATCH] " Chris Packham 0 siblings, 2 replies; 10+ messages in thread From: york sun @ 2016-11-23 17:41 UTC (permalink / raw) To: u-boot On 11/23/2016 01:43 AM, Chris Packham wrote: > Hi, > > I was just looking at what it would take to add the T2080 L2 cache to > the mpc85xx_edac driver in Linux. At a cursory glance all the > registers appear to be there so I figured I'd just add the appropriate > entry to the of match table. > > To my surprise I found that the compatible string in my device tree > was overwritten with "cache". I've tracked this down to the > CONFIG_SYS_FSL_QORIQ_CHASSIS2 implementation of ft_fixup_l2cache in > u-boot. > > The CONFIG_L2_CACHE version seems to take care to update the device tree node to > > compatible = "fsl,t2080-l2-cache-controller", "cache"; > > but the CONFIG_SYS_FSL_QORIQ_CHASSIS2 version just sets this to > > compatible = "cache"; > > Is this an over-site or is it intentional? > I don't have any record of this discussion. Kumar wrote and committed this change. I hope he remembers. York ^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] arch: powerpc: Retain compatible property for L2 cache 2016-11-23 17:41 ` york sun @ 2016-11-28 23:52 ` Chris Packham 2016-11-29 3:10 ` [U-Boot] [PATCH] " Chris Packham 1 sibling, 0 replies; 10+ messages in thread From: Chris Packham @ 2016-11-28 23:52 UTC (permalink / raw) To: u-boot Instead of setting the compatible property to "cache", append the desired value retaining what may already be set in the current property. Signed-off-by: Chris Packham <judge.packham@gmail.com> --- On Thu, Nov 24, 2016 at 6:41 AM, york sun <york.sun@nxp.com> wrote: > On 11/23/2016 01:43 AM, Chris Packham wrote: >> Hi, >> >> I was just looking at what it would take to add the T2080 L2 cache to >> the mpc85xx_edac driver in Linux. At a cursory glance all the >> registers appear to be there so I figured I'd just add the >> appropriate >> entry to the of match table. >> >> To my surprise I found that the compatible string in my device tree >> was overwritten with "cache". I've tracked this down to the >> CONFIG_SYS_FSL_QORIQ_CHASSIS2 implementation of ft_fixup_l2cache in >> u-boot. >> >> The CONFIG_L2_CACHE version seems to take care to update the device >> tree node to >> >> compatible = "fsl,t2080-l2-cache-controller", "cache"; >> >> but the CONFIG_SYS_FSL_QORIQ_CHASSIS2 version just sets this to >> >> compatible = "cache"; >> >> Is this an over-site or is it intentional? >> > > I don't have any record of this discussion. Kumar wrote and committed > this change. I hope he remembers. > Here's a patch that retains the compatible property from the original dtb and adds the "cache" value if required. This gets the value I need through to the kernel. arch/powerpc/cpu/mpc85xx/fdt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 047c972ac78e..f31df41836d5 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -337,7 +337,8 @@ static inline void ft_fixup_l2cache(void *blob) fdt_setprop_cell(blob, l2_off, "cache-size", size); fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); fdt_setprop_cell(blob, l2_off, "cache-level", 2); - fdt_setprop(blob, l2_off, "compatible", "cache", 6); + if (fdt_node_check_compatible(blob, l2_off, "cache") == 1) + fdt_appendprop_string(blob, l2_off, "compatible", "cache"); } if (l3_off < 0) { -- 2.10.2 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] powerpc: Retain compatible property for L2 cache 2016-11-23 17:41 ` york sun 2016-11-28 23:52 ` [U-Boot] [PATCH] arch: powerpc: Retain compatible property for L2 cache Chris Packham @ 2016-11-29 3:10 ` Chris Packham 2016-11-30 17:18 ` york sun 1 sibling, 1 reply; 10+ messages in thread From: Chris Packham @ 2016-11-29 3:10 UTC (permalink / raw) To: u-boot Instead of setting the compatible property to "cache", append the desired value retaining what may already be set in the current property. Signed-off-by: Chris Packham <judge.packham@gmail.com> --- On Thu, Nov 24, 2016 at 6:41 AM, york sun <york.sun@nxp.com> wrote: > On 11/23/2016 01:43 AM, Chris Packham wrote: >> Hi, >> >> I was just looking at what it would take to add the T2080 L2 cache to >> the mpc85xx_edac driver in Linux. At a cursory glance all the >> registers appear to be there so I figured I'd just add the >> appropriate >> entry to the of match table. >> >> To my surprise I found that the compatible string in my device tree >> was overwritten with "cache". I've tracked this down to the >> CONFIG_SYS_FSL_QORIQ_CHASSIS2 implementation of ft_fixup_l2cache in >> u-boot. >> >> The CONFIG_L2_CACHE version seems to take care to update the device >> tree node to >> >> compatible = "fsl,t2080-l2-cache-controller", "cache"; >> >> but the CONFIG_SYS_FSL_QORIQ_CHASSIS2 version just sets this to >> >> compatible = "cache"; >> >> Is this an over-site or is it intentional? >> > > I don't have any record of this discussion. Kumar wrote and committed > this change. I hope he remembers. > (re-sent because I flubbed the subject line and got bounced for Ccing all arch mainatiners, sorry for the spam) Here's a patch that retains the compatible property from the original dtb and adds the "cache" value if required. This gets the value I need through to the kernel. If it helps this is also consistent with the Linux documentation for this binding[1] which states that the compatible property should have both "<chip>-l2-cache-controller" and "cache" as values [1] - Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt arch/powerpc/cpu/mpc85xx/fdt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 047c972ac78e..f31df41836d5 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -337,7 +337,8 @@ static inline void ft_fixup_l2cache(void *blob) fdt_setprop_cell(blob, l2_off, "cache-size", size); fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); fdt_setprop_cell(blob, l2_off, "cache-level", 2); - fdt_setprop(blob, l2_off, "compatible", "cache", 6); + if (fdt_node_check_compatible(blob, l2_off, "cache") == 1) + fdt_appendprop_string(blob, l2_off, "compatible", "cache"); } if (l3_off < 0) { -- 2.10.2 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] powerpc: Retain compatible property for L2 cache 2016-11-29 3:10 ` [U-Boot] [PATCH] " Chris Packham @ 2016-11-30 17:18 ` york sun 2016-12-01 7:47 ` Chris Packham 0 siblings, 1 reply; 10+ messages in thread From: york sun @ 2016-11-30 17:18 UTC (permalink / raw) To: u-boot On 11/28/2016 07:10 PM, Chris Packham wrote: > Instead of setting the compatible property to "cache", append the > desired value retaining what may already be set in the current property. > > Signed-off-by: Chris Packham <judge.packham@gmail.com> > --- <snip> > > arch/powerpc/cpu/mpc85xx/fdt.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c > index 047c972ac78e..f31df41836d5 100644 > --- a/arch/powerpc/cpu/mpc85xx/fdt.c > +++ b/arch/powerpc/cpu/mpc85xx/fdt.c > @@ -337,7 +337,8 @@ static inline void ft_fixup_l2cache(void *blob) > fdt_setprop_cell(blob, l2_off, "cache-size", size); > fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); > fdt_setprop_cell(blob, l2_off, "cache-level", 2); > - fdt_setprop(blob, l2_off, "compatible", "cache", 6); > + if (fdt_node_check_compatible(blob, l2_off, "cache") == 1) > + fdt_appendprop_string(blob, l2_off, "compatible", "cache"); > } > > if (l3_off < 0) { > You drop fdt_setprop, check the compatible "cache" and append it with "cache" again? I thought you wanted compatible = "fsl,t2080-l2-cache-controller", "cache"; York ^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] powerpc: Retain compatible property for L2 cache 2016-11-30 17:18 ` york sun @ 2016-12-01 7:47 ` Chris Packham 2016-12-01 17:34 ` york sun 0 siblings, 1 reply; 10+ messages in thread From: Chris Packham @ 2016-12-01 7:47 UTC (permalink / raw) To: u-boot On Thu, Dec 1, 2016 at 6:18 AM, york sun <york.sun@nxp.com> wrote: > On 11/28/2016 07:10 PM, Chris Packham wrote: >> Instead of setting the compatible property to "cache", append the >> desired value retaining what may already be set in the current property. >> >> Signed-off-by: Chris Packham <judge.packham@gmail.com> >> --- > > <snip> > >> >> arch/powerpc/cpu/mpc85xx/fdt.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c >> index 047c972ac78e..f31df41836d5 100644 >> --- a/arch/powerpc/cpu/mpc85xx/fdt.c >> +++ b/arch/powerpc/cpu/mpc85xx/fdt.c >> @@ -337,7 +337,8 @@ static inline void ft_fixup_l2cache(void *blob) >> fdt_setprop_cell(blob, l2_off, "cache-size", size); >> fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); >> fdt_setprop_cell(blob, l2_off, "cache-level", 2); >> - fdt_setprop(blob, l2_off, "compatible", "cache", 6); >> + if (fdt_node_check_compatible(blob, l2_off, "cache") == 1) >> + fdt_appendprop_string(blob, l2_off, "compatible", "cache"); >> } >> >> if (l3_off < 0) { >> > > You drop fdt_setprop, check the compatible "cache" and append it with > "cache" again? I thought you wanted > > compatible = "fsl,t2080-l2-cache-controller", "cache"; I already have "fsl,t2080-l2-cache-controller" in my dts. Really I just want fdt_appendprop_string(blob, l2_off, "compatible", "cache"); But the check is necessary because we run through this block multiple times (once per CPU). My initial version was struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr())); int len; char buf[40]; len = sprintf(buf, "fsl,%c%s-l2-cache-controller",tolower(cpu->name[0]), cpu->name + 1) + 1; len += sprintf(buf + len, "cache") + 1; fdt_setprop(blob, l2_off, "compatible", buf, len); But that's more code. > > York ^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH] powerpc: Retain compatible property for L2 cache 2016-12-01 7:47 ` Chris Packham @ 2016-12-01 17:34 ` york sun [not found] ` <CAFOYHZA7ycTE3rTQJiAgBBVBUFW9_QemAcCra33VnfGiWn0Arg@mail.gmail.com> 0 siblings, 1 reply; 10+ messages in thread From: york sun @ 2016-12-01 17:34 UTC (permalink / raw) To: u-boot On 11/30/2016 11:47 PM, Chris Packham wrote: > On Thu, Dec 1, 2016 at 6:18 AM, york sun <york.sun@nxp.com> wrote: >> On 11/28/2016 07:10 PM, Chris Packham wrote: >>> Instead of setting the compatible property to "cache", append the >>> desired value retaining what may already be set in the current property. >>> >>> Signed-off-by: Chris Packham <judge.packham@gmail.com> >>> --- >> >> <snip> >> >>> >>> arch/powerpc/cpu/mpc85xx/fdt.c | 3 ++- >>> 1 file changed, 2 insertions(+), 1 deletion(-) >>> >>> diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c >>> index 047c972ac78e..f31df41836d5 100644 >>> --- a/arch/powerpc/cpu/mpc85xx/fdt.c >>> +++ b/arch/powerpc/cpu/mpc85xx/fdt.c >>> @@ -337,7 +337,8 @@ static inline void ft_fixup_l2cache(void *blob) >>> fdt_setprop_cell(blob, l2_off, "cache-size", size); >>> fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); >>> fdt_setprop_cell(blob, l2_off, "cache-level", 2); >>> - fdt_setprop(blob, l2_off, "compatible", "cache", 6); >>> + if (fdt_node_check_compatible(blob, l2_off, "cache") == 1) >>> + fdt_appendprop_string(blob, l2_off, "compatible", "cache"); >>> } >>> >>> if (l3_off < 0) { >>> >> >> You drop fdt_setprop, check the compatible "cache" and append it with >> "cache" again? I thought you wanted >> >> compatible = "fsl,t2080-l2-cache-controller", "cache"; > > I already have "fsl,t2080-l2-cache-controller" in my dts. Really I just want > > fdt_appendprop_string(blob, l2_off, "compatible", "cache"); I see. > > But the check is necessary because we run through this block multiple > times (once per CPU). My initial version was > > struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr())); > int len; > char buf[40]; > > len = sprintf(buf, > "fsl,%c%s-l2-cache-controller",tolower(cpu->name[0]), cpu->name + 1) + > 1; > len += sprintf(buf + len, "cache") + 1; > > fdt_setprop(blob, l2_off, "compatible", buf, len); > > But that's more code. > Ideally we don't have to fix up dts. Since if we have to do it, I like the long version better. If the dts doesn't have correct compatible, the kernel won't take it, right? York ^ permalink raw reply [flat|nested] 10+ messages in thread
[parent not found: <CAFOYHZA7ycTE3rTQJiAgBBVBUFW9_QemAcCra33VnfGiWn0Arg@mail.gmail.com>]
[parent not found: <CAFOYHZD5JrrC=d9-kZd6tLiZHynJFjS3AtbkaPS9b9Pfy-s5hQ@mail.gmail.com>]
* [U-Boot] [PATCH] powerpc: Retain compatible property for L2 cache [not found] ` <CAFOYHZD5JrrC=d9-kZd6tLiZHynJFjS3AtbkaPS9b9Pfy-s5hQ@mail.gmail.com> @ 2016-12-02 7:35 ` Chris Packham 2016-12-02 8:22 ` [U-Boot] [PATCH v2] " Chris Packham 0 siblings, 1 reply; 10+ messages in thread From: Chris Packham @ 2016-12-02 7:35 UTC (permalink / raw) To: u-boot On 2/12/2016 6:34 AM, "york sun" <york.sun@nxp.com> wrote: > > On 11/30/2016 11:47 PM, Chris Packham wrote: > > On Thu, Dec 1, 2016 at 6:18 AM, york sun <york.sun@nxp.com> wrote: > >> On 11/28/2016 07:10 PM, Chris Packham wrote: > >>> Instead of setting the compatible property to "cache", append the > >>> desired value retaining what may already be set in the current property. > >>> > >>> Signed-off-by: Chris Packham <judge.packham@gmail.com> > >>> --- > >> > >> <snip> > >> > >>> > >>> arch/powerpc/cpu/mpc85xx/fdt.c | 3 ++- > >>> 1 file changed, 2 insertions(+), 1 deletion(-) > >>> > >>> diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c > >>> index 047c972ac78e..f31df41836d5 100644 > >>> --- a/arch/powerpc/cpu/mpc85xx/fdt.c > >>> +++ b/arch/powerpc/cpu/mpc85xx/fdt.c > >>> @@ -337,7 +337,8 @@ static inline void ft_fixup_l2cache(void *blob) > >>> fdt_setprop_cell(blob, l2_off, "cache-size", size); > >>> fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); > >>> fdt_setprop_cell(blob, l2_off, "cache-level", 2); > >>> - fdt_setprop(blob, l2_off, "compatible", "cache", 6); > >>> + if (fdt_node_check_compatible(blob, l2_off, "cache") == 1) > >>> + fdt_appendprop_string(blob, l2_off, "compatible", "cache"); > >>> } > >>> > >>> if (l3_off < 0) { > >>> > >> > >> You drop fdt_setprop, check the compatible "cache" and append it with > >> "cache" again? I thought you wanted > >> > >> compatible = "fsl,t2080-l2-cache-controller", "cache"; > > > > I already have "fsl,t2080-l2-cache-controller" in my dts. Really I just want > > > > fdt_appendprop_string(blob, l2_off, "compatible", "cache"); > > I see. > > > > > But the check is necessary because we run through this block multiple > > times (once per CPU). My initial version was > > > > struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr())); > > int len; > > char buf[40]; > > > > len = sprintf(buf, > > "fsl,%c%s-l2-cache-controller",tolower(cpu->name[0]), cpu->name + 1) + > > 1; > > len += sprintf(buf + len, "cache") + 1; > > > > fdt_setprop(blob, l2_off, "compatible", buf, len); > > > > But that's more code. > > > > Ideally we don't have to fix up dts. Since if we have to do it, I like > the long version better. If the dts doesn't have correct compatible, the > kernel won't take it, right? > Ok. I'll post a v2 based on the long version. As it's a repeat of code in another block I'll see if i can extract it to a helper function. ^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2] powerpc: Retain compatible property for L2 cache 2016-12-02 7:35 ` Chris Packham @ 2016-12-02 8:22 ` Chris Packham 2016-12-20 17:16 ` york sun 0 siblings, 1 reply; 10+ messages in thread From: Chris Packham @ 2016-12-02 8:22 UTC (permalink / raw) To: u-boot When setting the compatible property for the L2 cache ensure that we follow the documented binding by setting both "<chip>-l2-cache-controller" and "cache" as values. Signed-off-by: Chris Packham <judge.packham@gmail.com> --- Changes in v2: - extract a helper function to set the compatible property and use it in both the CONFIG_L2_CACHE and CONFIG_BACKSIDE_L2_CACHE cases. arch/powerpc/cpu/mpc85xx/fdt.c | 61 +++++++++++++++++++++++++----------------- 1 file changed, 36 insertions(+), 25 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 047c972ac78e..8aaf53a65458 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -180,6 +180,39 @@ static inline void ft_fixup_l3cache(void *blob, int off) #define ft_fixup_l3cache(x, y) #endif +#if defined(CONFIG_L2_CACHE) || \ + defined(CONFIG_BACKSIDE_L2_CACHE) || \ + defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) +static inline void ft_fixup_l2cache_compatible(void *blob, int off) +{ + int len; + struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr())); + + if (cpu) { + char buf[40]; + + if (isdigit(cpu->name[0])) { + /* MPCxxxx, where xxxx == 4-digit number */ + len = sprintf(buf, "fsl,mpc%s-l2-cache-controller", + cpu->name) + 1; + } else { + /* Pxxxx or Txxxx, where xxxx == 4-digit number */ + len = sprintf(buf, "fsl,%c%s-l2-cache-controller", + tolower(cpu->name[0]), cpu->name + 1) + 1; + } + + /* + * append "cache" after the NULL character that the previous + * sprintf wrote. This is how a device tree stores multiple + * strings in a property. + */ + len += sprintf(buf + len, "cache") + 1; + + fdt_setprop(blob, off, "compatible", buf, len); + } +} +#endif + #if defined(CONFIG_L2_CACHE) /* return size in kilobytes */ static inline u32 l2cache_size(void) @@ -215,9 +248,8 @@ static inline u32 l2cache_size(void) static inline void ft_fixup_l2cache(void *blob) { - int len, off; + int off; u32 *ph; - struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr())); const u32 line_size = 32; const u32 num_ways = 8; @@ -243,28 +275,7 @@ static inline void ft_fixup_l2cache(void *blob) return ; } - if (cpu) { - char buf[40]; - - if (isdigit(cpu->name[0])) { - /* MPCxxxx, where xxxx == 4-digit number */ - len = sprintf(buf, "fsl,mpc%s-l2-cache-controller", - cpu->name) + 1; - } else { - /* Pxxxx or Txxxx, where xxxx == 4-digit number */ - len = sprintf(buf, "fsl,%c%s-l2-cache-controller", - tolower(cpu->name[0]), cpu->name + 1) + 1; - } - - /* - * append "cache" after the NULL character that the previous - * sprintf wrote. This is how a device tree stores multiple - * strings in a property. - */ - len += sprintf(buf + len, "cache") + 1; - - fdt_setprop(blob, off, "compatible", buf, len); - } + ft_fixup_l2cache_compatible(blob, off); fdt_setprop(blob, off, "cache-unified", NULL, 0); fdt_setprop_cell(blob, off, "cache-block-size", line_size); fdt_setprop_cell(blob, off, "cache-size", size); @@ -337,7 +348,7 @@ static inline void ft_fixup_l2cache(void *blob) fdt_setprop_cell(blob, l2_off, "cache-size", size); fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); fdt_setprop_cell(blob, l2_off, "cache-level", 2); - fdt_setprop(blob, l2_off, "compatible", "cache", 6); + ft_fixup_l2cache_compatible(blob, l2_off); } if (l3_off < 0) { -- 2.10.2 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v2] powerpc: Retain compatible property for L2 cache 2016-12-02 8:22 ` [U-Boot] [PATCH v2] " Chris Packham @ 2016-12-20 17:16 ` york sun 0 siblings, 0 replies; 10+ messages in thread From: york sun @ 2016-12-20 17:16 UTC (permalink / raw) To: u-boot On 12/02/2016 12:22 AM, Chris Packham wrote: > When setting the compatible property for the L2 cache ensure that we > follow the documented binding by setting both > "<chip>-l2-cache-controller" and "cache" as values. > > Signed-off-by: Chris Packham <judge.packham@gmail.com> > --- > > Changes in v2: > - extract a helper function to set the compatible property and use it in > both the CONFIG_L2_CACHE and CONFIG_BACKSIDE_L2_CACHE cases. > > arch/powerpc/cpu/mpc85xx/fdt.c | 61 +++++++++++++++++++++++++----------------- > 1 file changed, 36 insertions(+), 25 deletions(-) > Applied to u-boot-mpc85xx master, awaiting upstream. Thanks. York ^ permalink raw reply [flat|nested] 10+ messages in thread
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2016-11-23 9:43 [U-Boot] T2080 l2-cache-controller compatible string overwritten by ft_fixup_l2cache Chris Packham
2016-11-23 17:41 ` york sun
2016-11-28 23:52 ` [U-Boot] [PATCH] arch: powerpc: Retain compatible property for L2 cache Chris Packham
2016-11-29 3:10 ` [U-Boot] [PATCH] " Chris Packham
2016-11-30 17:18 ` york sun
2016-12-01 7:47 ` Chris Packham
2016-12-01 17:34 ` york sun
[not found] ` <CAFOYHZA7ycTE3rTQJiAgBBVBUFW9_QemAcCra33VnfGiWn0Arg@mail.gmail.com>
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2016-12-02 7:35 ` Chris Packham
2016-12-02 8:22 ` [U-Boot] [PATCH v2] " Chris Packham
2016-12-20 17:16 ` york sun
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