From: Aisheng Dong <aisheng.dong@nxp.com>
To: Peng Fan <peng.fan@nxp.com>,
"shawnguo@kernel.org" <shawnguo@kernel.org>,
"s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
Leonard Crestez <leonard.crestez@nxp.com>,
"sboyd@kernel.org" <sboyd@kernel.org>,
Abel Vesa <abel.vesa@nxp.com>
Cc: "kernel@pengutronix.de" <kernel@pengutronix.de>,
"festevam@gmail.com" <festevam@gmail.com>,
dl-linux-imx <linux-imx@nxp.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Anson Huang <anson.huang@nxp.com>,
Daniel Baluta <daniel.baluta@nxp.com>,
"aford173@gmail.com" <aford173@gmail.com>,
Jacky Bai <ping.bai@nxp.com>, Jun Li <jun.li@nxp.com>,
"l.stach@pengutronix.de" <l.stach@pengutronix.de>,
"andrew.smirnov@gmail.com" <andrew.smirnov@gmail.com>,
"agx@sigxcpu.org" <agx@sigxcpu.org>,
"angus@akkea.ca" <angus@akkea.ca>,
"heiko@sntech.de" <heiko@sntech.de>,
Andy Duan <fugang.duan@nxp.com>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>
Subject: RE: [PATCH V2 05/10] clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code
Date: Sun, 26 Apr 2020 04:38:45 +0000 [thread overview]
Message-ID: <AM6PR04MB49662BE2A6456DD9B62F28D980AE0@AM6PR04MB4966.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <1584008384-11578-6-git-send-email-peng.fan@nxp.com>
> From: Peng Fan <peng.fan@nxp.com>
> Sent: Thursday, March 12, 2020 6:20 PM
>
> Use imx8m_clk_hw_composite_core to simpliy clks that belong to core clk slice.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Should we also deprecated the old clock ids which will not be supported by driver anymore?
Otherwise:
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Regards
Aisheng
> ---
> drivers/clk/imx/clk-imx8mp.c | 47
> +++++++++++---------------------
> include/dt-bindings/clock/imx8mp-clock.h | 11 +++++++-
> 2 files changed, 26 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index
> a7613c7355c8..998e9e63f831 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -546,33 +546,18 @@ static int imx8mp_clocks_probe(struct
> platform_device *pdev)
> hws[IMX8MP_SYS_PLL2_500M] =
> imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
> hws[IMX8MP_SYS_PLL2_1000M] =
> imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
>
> - hws[IMX8MP_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src",
> ccm_base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels));
> - hws[IMX8MP_CLK_M7_SRC] = imx_clk_hw_mux2("arm_m7_src",
> ccm_base + 0x8080, 24, 3, imx8mp_m7_sels, ARRAY_SIZE(imx8mp_m7_sels));
> - hws[IMX8MP_CLK_ML_SRC] = imx_clk_hw_mux2("ml_src", ccm_base +
> 0x8100, 24, 3, imx8mp_ml_sels, ARRAY_SIZE(imx8mp_ml_sels));
> - hws[IMX8MP_CLK_GPU3D_CORE_SRC] =
> imx_clk_hw_mux2("gpu3d_core_src", ccm_base + 0x8180, 24, 3,
> imx8mp_gpu3d_core_sels, ARRAY_SIZE(imx8mp_gpu3d_core_sels));
> - hws[IMX8MP_CLK_GPU3D_SHADER_SRC] =
> imx_clk_hw_mux2("gpu3d_shader_src", ccm_base + 0x8200, 24, 3,
> imx8mp_gpu3d_shader_sels, ARRAY_SIZE(imx8mp_gpu3d_shader_sels));
> - hws[IMX8MP_CLK_GPU2D_SRC] = imx_clk_hw_mux2("gpu2d_src",
> ccm_base + 0x8280, 24, 3, imx8mp_gpu2d_sels,
> ARRAY_SIZE(imx8mp_gpu2d_sels));
> - hws[IMX8MP_CLK_AUDIO_AXI_SRC] = imx_clk_hw_mux2("audio_axi_src",
> ccm_base + 0x8300, 24, 3, imx8mp_audio_axi_sels,
> ARRAY_SIZE(imx8mp_audio_axi_sels));
> - hws[IMX8MP_CLK_HSIO_AXI_SRC] = imx_clk_hw_mux2("hsio_axi_src",
> ccm_base + 0x8380, 24, 3, imx8mp_hsio_axi_sels,
> ARRAY_SIZE(imx8mp_hsio_axi_sels));
> - hws[IMX8MP_CLK_MEDIA_ISP_SRC] = imx_clk_hw_mux2("media_isp_src",
> ccm_base + 0x8400, 24, 3, imx8mp_media_isp_sels,
> ARRAY_SIZE(imx8mp_media_isp_sels));
> - hws[IMX8MP_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg",
> "arm_a53_src", ccm_base + 0x8000, 28);
> - hws[IMX8MP_CLK_M4_CG] = imx_clk_hw_gate3("arm_m7_cg",
> "arm_m7_src", ccm_base + 0x8080, 28);
> - hws[IMX8MP_CLK_ML_CG] = imx_clk_hw_gate3("ml_cg", "ml_src",
> ccm_base + 0x8100, 28);
> - hws[IMX8MP_CLK_GPU3D_CORE_CG] =
> imx_clk_hw_gate3("gpu3d_core_cg", "gpu3d_core_src", ccm_base + 0x8180,
> 28);
> - hws[IMX8MP_CLK_GPU3D_SHADER_CG] =
> imx_clk_hw_gate3("gpu3d_shader_cg", "gpu3d_shader_src", ccm_base +
> 0x8200, 28);
> - hws[IMX8MP_CLK_GPU2D_CG] = imx_clk_hw_gate3("gpu2d_cg",
> "gpu2d_src", ccm_base + 0x8280, 28);
> - hws[IMX8MP_CLK_AUDIO_AXI_CG] = imx_clk_hw_gate3("audio_axi_cg",
> "audio_axi_src", ccm_base + 0x8300, 28);
> - hws[IMX8MP_CLK_HSIO_AXI_CG] = imx_clk_hw_gate3("hsio_axi_cg",
> "hsio_axi_src", ccm_base + 0x8380, 28);
> - hws[IMX8MP_CLK_MEDIA_ISP_CG] = imx_clk_hw_gate3("media_isp_cg",
> "media_isp_src", ccm_base + 0x8400, 28);
> - hws[IMX8MP_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div",
> "arm_a53_cg", ccm_base + 0x8000, 0, 3);
> - hws[IMX8MP_CLK_M7_DIV] = imx_clk_hw_divider2("arm_m7_div",
> "arm_m7_cg", ccm_base + 0x8080, 0, 3);
> - hws[IMX8MP_CLK_ML_DIV] = imx_clk_hw_divider2("ml_div", "ml_cg",
> ccm_base + 0x8100, 0, 3);
> - hws[IMX8MP_CLK_GPU3D_CORE_DIV] =
> imx_clk_hw_divider2("gpu3d_core_div", "gpu3d_core_cg", ccm_base + 0x8180,
> 0, 3);
> - hws[IMX8MP_CLK_GPU3D_SHADER_DIV] =
> imx_clk_hw_divider2("gpu3d_shader_div", "gpu3d_shader_cg", ccm_base +
> 0x8200, 0, 3);
> - hws[IMX8MP_CLK_GPU2D_DIV] = imx_clk_hw_divider2("gpu2d_div",
> "gpu2d_cg", ccm_base + 0x8280, 0, 3);
> - hws[IMX8MP_CLK_AUDIO_AXI_DIV] =
> imx_clk_hw_divider2("audio_axi_div", "audio_axi_cg", ccm_base + 0x8300, 0,
> 3);
> - hws[IMX8MP_CLK_HSIO_AXI_DIV] = imx_clk_hw_divider2("hsio_axi_div",
> "hsio_axi_cg", ccm_base + 0x8380, 0, 3);
> - hws[IMX8MP_CLK_MEDIA_ISP_DIV] =
> imx_clk_hw_divider2("media_isp_div", "media_isp_cg", ccm_base + 0x8400, 0,
> 3);
> + hws[IMX8MP_CLK_A53_DIV] =
> imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base
> + 0x8000);
> + hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV];
> + hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV];
> + hws[IMX8MP_CLK_M7_CORE] =
> imx8m_clk_hw_composite_core("m7_core", imx8mp_m7_sels, ccm_base +
> 0x8080);
> + hws[IMX8MP_CLK_ML_CORE] =
> imx8m_clk_hw_composite_core("ml_core", imx8mp_ml_sels, ccm_base +
> 0x8100);
> + hws[IMX8MP_CLK_GPU3D_CORE] =
> imx8m_clk_hw_composite_core("gpu3d_core", imx8mp_gpu3d_core_sels,
> ccm_base + 0x8180);
> + hws[IMX8MP_CLK_GPU3D_SHADER_CORE] =
> imx8m_clk_hw_composite("gpu3d_shader_core", imx8mp_gpu3d_shader_sels,
> ccm_base + 0x8200);
> + hws[IMX8MP_CLK_GPU2D_CORE] =
> imx8m_clk_hw_composite("gpu2d_core", imx8mp_gpu2d_sels, ccm_base +
> 0x8280);
> + hws[IMX8MP_CLK_AUDIO_AXI] = imx8m_clk_hw_composite("audio_axi",
> imx8mp_audio_axi_sels, ccm_base + 0x8300);
> + hws[IMX8MP_CLK_AUDIO_AXI_SRC] = hws[IMX8MP_CLK_AUDIO_AXI];
> + hws[IMX8MP_CLK_HSIO_AXI] = imx8m_clk_hw_composite("hsio_axi",
> imx8mp_hsio_axi_sels, ccm_base + 0x8380);
> + hws[IMX8MP_CLK_MEDIA_ISP] = imx8m_clk_hw_composite("media_isp",
> +imx8mp_media_isp_sels, ccm_base + 0x8400);
>
> /* CORE SEL */
> hws[IMX8MP_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core",
> ccm_base + 0x9880, 24, 1, imx8mp_a53_core_sels,
> ARRAY_SIZE(imx8mp_a53_core_sels));
> @@ -713,8 +698,8 @@ static int imx8mp_clocks_probe(struct platform_device
> *pdev)
> hws[IMX8MP_CLK_SDMA1_ROOT] = imx_clk_hw_gate4("sdma1_root_clk",
> "ipg_root", ccm_base + 0x43a0, 0);
> hws[IMX8MP_CLK_ENET_QOS_ROOT] =
> imx_clk_hw_gate4("enet_qos_root_clk", "sim_enet_root_clk", ccm_base +
> 0x43b0, 0);
> hws[IMX8MP_CLK_SIM_ENET_ROOT] =
> imx_clk_hw_gate4("sim_enet_root_clk", "enet_axi", ccm_base + 0x4400, 0);
> - hws[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk",
> "gpu2d_div", ccm_base + 0x4450, 0);
> - hws[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk",
> "gpu3d_core_div", ccm_base + 0x4460, 0);
> + hws[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk",
> "gpu2d_core", ccm_base + 0x4450, 0);
> + hws[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk",
> +"gpu3d_core", ccm_base + 0x4460, 0);
> hws[IMX8MP_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk",
> "ipg_root", ccm_base + 0x4470, 0);
> hws[IMX8MP_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk",
> "uart1", ccm_base + 0x4490, 0);
> hws[IMX8MP_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk",
> "uart2", ccm_base + 0x44a0, 0); @@ -731,7 +716,7 @@ static int
> imx8mp_clocks_probe(struct platform_device *pdev)
> hws[IMX8MP_CLK_GPU_ROOT] = imx_clk_hw_gate4("gpu_root_clk",
> "gpu_axi", ccm_base + 0x4570, 0);
> hws[IMX8MP_CLK_VPU_VC8KE_ROOT] =
> imx_clk_hw_gate4("vpu_vc8ke_root_clk", "vpu_vc8000e", ccm_base + 0x4590,
> 0);
> hws[IMX8MP_CLK_VPU_G2_ROOT] =
> imx_clk_hw_gate4("vpu_g2_root_clk", "vpu_g2", ccm_base + 0x45a0, 0);
> - hws[IMX8MP_CLK_NPU_ROOT] = imx_clk_hw_gate4("npu_root_clk",
> "ml_div", ccm_base + 0x45b0, 0);
> + hws[IMX8MP_CLK_NPU_ROOT] = imx_clk_hw_gate4("npu_root_clk",
> "ml_core",
> +ccm_base + 0x45b0, 0);
> hws[IMX8MP_CLK_HSIO_ROOT] = imx_clk_hw_gate4("hsio_root_clk",
> "ipg_root", ccm_base + 0x45c0, 0);
> hws[IMX8MP_CLK_MEDIA_APB_ROOT] =
> imx_clk_hw_gate2_shared2("media_apb_root_clk", "media_apb", ccm_base +
> 0x45d0, 0, &share_count_media);
> hws[IMX8MP_CLK_MEDIA_AXI_ROOT] =
> imx_clk_hw_gate2_shared2("media_axi_root_clk", "media_axi", ccm_base +
> 0x45d0, 0, &share_count_media); @@ -739,7 +724,7 @@ static int
> imx8mp_clocks_probe(struct platform_device *pdev)
> hws[IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT] =
> imx_clk_hw_gate2_shared2("media_cam2_pix_root_clk", "media_cam2_pix",
> ccm_base + 0x45d0, 0, &share_count_media);
> hws[IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT] =
> imx_clk_hw_gate2_shared2("media_disp1_pix_root_clk", "media_disp1_pix",
> ccm_base + 0x45d0, 0, &share_count_media);
> hws[IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT] =
> imx_clk_hw_gate2_shared2("media_disp2_pix_root_clk", "media_disp2_pix",
> ccm_base + 0x45d0, 0, &share_count_media);
> - hws[IMX8MP_CLK_MEDIA_ISP_ROOT] =
> imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp_div", ccm_base
> + 0x45d0, 0, &share_count_media);
> + hws[IMX8MP_CLK_MEDIA_ISP_ROOT] =
> +imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp", ccm_base +
> +0x45d0, 0, &share_count_media);
>
> hws[IMX8MP_CLK_USDHC3_ROOT] =
> imx_clk_hw_gate4("usdhc3_root_clk", "usdhc3", ccm_base + 0x45e0, 0);
> hws[IMX8MP_CLK_HDMI_ROOT] = imx_clk_hw_gate4("hdmi_root_clk",
> "hdmi_axi", ccm_base + 0x45f0, 0); diff --git
> a/include/dt-bindings/clock/imx8mp-clock.h
> b/include/dt-bindings/clock/imx8mp-clock.h
> index 46c69cd66c62..8430bc4fd182 100644
> --- a/include/dt-bindings/clock/imx8mp-clock.h
> +++ b/include/dt-bindings/clock/imx8mp-clock.h
> @@ -313,6 +313,15 @@
> #define IMX8MP_SYS_PLL2_333M_CG 303
> #define IMX8MP_SYS_PLL2_500M_CG 304
>
> -#define IMX8MP_CLK_END 305
> +#define IMX8MP_CLK_M7_CORE 305
> +#define IMX8MP_CLK_ML_CORE 306
> +#define IMX8MP_CLK_GPU3D_CORE 307
> +#define IMX8MP_CLK_GPU3D_SHADER_CORE 308
> +#define IMX8MP_CLK_GPU2D_CORE 309
> +#define IMX8MP_CLK_AUDIO_AXI 310
> +#define IMX8MP_CLK_HSIO_AXI 311
> +#define IMX8MP_CLK_MEDIA_ISP 312
> +
> +#define IMX8MP_CLK_END 313
>
> #endif
> --
> 2.16.4
WARNING: multiple messages have this Message-ID (diff)
From: Aisheng Dong <aisheng.dong@nxp.com>
To: Peng Fan <peng.fan@nxp.com>,
"shawnguo@kernel.org" <shawnguo@kernel.org>,
"s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
Leonard Crestez <leonard.crestez@nxp.com>,
"sboyd@kernel.org" <sboyd@kernel.org>,
Abel Vesa <abel.vesa@nxp.com>
Cc: Andy Duan <fugang.duan@nxp.com>, Jacky Bai <ping.bai@nxp.com>,
Anson Huang <anson.huang@nxp.com>,
"andrew.smirnov@gmail.com" <andrew.smirnov@gmail.com>,
Daniel Baluta <daniel.baluta@nxp.com>,
"agx@sigxcpu.org" <agx@sigxcpu.org>,
"angus@akkea.ca" <angus@akkea.ca>,
"heiko@sntech.de" <heiko@sntech.de>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
dl-linux-imx <linux-imx@nxp.com>,
"kernel@pengutronix.de" <kernel@pengutronix.de>,
"aford173@gmail.com" <aford173@gmail.com>,
"l.stach@pengutronix.de" <l.stach@pengutronix.de>,
"festevam@gmail.com" <festevam@gmail.com>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>, Jun Li <jun.li@nxp.com>
Subject: RE: [PATCH V2 05/10] clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code
Date: Sun, 26 Apr 2020 04:38:45 +0000 [thread overview]
Message-ID: <AM6PR04MB49662BE2A6456DD9B62F28D980AE0@AM6PR04MB4966.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <1584008384-11578-6-git-send-email-peng.fan@nxp.com>
> From: Peng Fan <peng.fan@nxp.com>
> Sent: Thursday, March 12, 2020 6:20 PM
>
> Use imx8m_clk_hw_composite_core to simpliy clks that belong to core clk slice.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Should we also deprecated the old clock ids which will not be supported by driver anymore?
Otherwise:
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Regards
Aisheng
> ---
> drivers/clk/imx/clk-imx8mp.c | 47
> +++++++++++---------------------
> include/dt-bindings/clock/imx8mp-clock.h | 11 +++++++-
> 2 files changed, 26 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index
> a7613c7355c8..998e9e63f831 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -546,33 +546,18 @@ static int imx8mp_clocks_probe(struct
> platform_device *pdev)
> hws[IMX8MP_SYS_PLL2_500M] =
> imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
> hws[IMX8MP_SYS_PLL2_1000M] =
> imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
>
> - hws[IMX8MP_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src",
> ccm_base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels));
> - hws[IMX8MP_CLK_M7_SRC] = imx_clk_hw_mux2("arm_m7_src",
> ccm_base + 0x8080, 24, 3, imx8mp_m7_sels, ARRAY_SIZE(imx8mp_m7_sels));
> - hws[IMX8MP_CLK_ML_SRC] = imx_clk_hw_mux2("ml_src", ccm_base +
> 0x8100, 24, 3, imx8mp_ml_sels, ARRAY_SIZE(imx8mp_ml_sels));
> - hws[IMX8MP_CLK_GPU3D_CORE_SRC] =
> imx_clk_hw_mux2("gpu3d_core_src", ccm_base + 0x8180, 24, 3,
> imx8mp_gpu3d_core_sels, ARRAY_SIZE(imx8mp_gpu3d_core_sels));
> - hws[IMX8MP_CLK_GPU3D_SHADER_SRC] =
> imx_clk_hw_mux2("gpu3d_shader_src", ccm_base + 0x8200, 24, 3,
> imx8mp_gpu3d_shader_sels, ARRAY_SIZE(imx8mp_gpu3d_shader_sels));
> - hws[IMX8MP_CLK_GPU2D_SRC] = imx_clk_hw_mux2("gpu2d_src",
> ccm_base + 0x8280, 24, 3, imx8mp_gpu2d_sels,
> ARRAY_SIZE(imx8mp_gpu2d_sels));
> - hws[IMX8MP_CLK_AUDIO_AXI_SRC] = imx_clk_hw_mux2("audio_axi_src",
> ccm_base + 0x8300, 24, 3, imx8mp_audio_axi_sels,
> ARRAY_SIZE(imx8mp_audio_axi_sels));
> - hws[IMX8MP_CLK_HSIO_AXI_SRC] = imx_clk_hw_mux2("hsio_axi_src",
> ccm_base + 0x8380, 24, 3, imx8mp_hsio_axi_sels,
> ARRAY_SIZE(imx8mp_hsio_axi_sels));
> - hws[IMX8MP_CLK_MEDIA_ISP_SRC] = imx_clk_hw_mux2("media_isp_src",
> ccm_base + 0x8400, 24, 3, imx8mp_media_isp_sels,
> ARRAY_SIZE(imx8mp_media_isp_sels));
> - hws[IMX8MP_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg",
> "arm_a53_src", ccm_base + 0x8000, 28);
> - hws[IMX8MP_CLK_M4_CG] = imx_clk_hw_gate3("arm_m7_cg",
> "arm_m7_src", ccm_base + 0x8080, 28);
> - hws[IMX8MP_CLK_ML_CG] = imx_clk_hw_gate3("ml_cg", "ml_src",
> ccm_base + 0x8100, 28);
> - hws[IMX8MP_CLK_GPU3D_CORE_CG] =
> imx_clk_hw_gate3("gpu3d_core_cg", "gpu3d_core_src", ccm_base + 0x8180,
> 28);
> - hws[IMX8MP_CLK_GPU3D_SHADER_CG] =
> imx_clk_hw_gate3("gpu3d_shader_cg", "gpu3d_shader_src", ccm_base +
> 0x8200, 28);
> - hws[IMX8MP_CLK_GPU2D_CG] = imx_clk_hw_gate3("gpu2d_cg",
> "gpu2d_src", ccm_base + 0x8280, 28);
> - hws[IMX8MP_CLK_AUDIO_AXI_CG] = imx_clk_hw_gate3("audio_axi_cg",
> "audio_axi_src", ccm_base + 0x8300, 28);
> - hws[IMX8MP_CLK_HSIO_AXI_CG] = imx_clk_hw_gate3("hsio_axi_cg",
> "hsio_axi_src", ccm_base + 0x8380, 28);
> - hws[IMX8MP_CLK_MEDIA_ISP_CG] = imx_clk_hw_gate3("media_isp_cg",
> "media_isp_src", ccm_base + 0x8400, 28);
> - hws[IMX8MP_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div",
> "arm_a53_cg", ccm_base + 0x8000, 0, 3);
> - hws[IMX8MP_CLK_M7_DIV] = imx_clk_hw_divider2("arm_m7_div",
> "arm_m7_cg", ccm_base + 0x8080, 0, 3);
> - hws[IMX8MP_CLK_ML_DIV] = imx_clk_hw_divider2("ml_div", "ml_cg",
> ccm_base + 0x8100, 0, 3);
> - hws[IMX8MP_CLK_GPU3D_CORE_DIV] =
> imx_clk_hw_divider2("gpu3d_core_div", "gpu3d_core_cg", ccm_base + 0x8180,
> 0, 3);
> - hws[IMX8MP_CLK_GPU3D_SHADER_DIV] =
> imx_clk_hw_divider2("gpu3d_shader_div", "gpu3d_shader_cg", ccm_base +
> 0x8200, 0, 3);
> - hws[IMX8MP_CLK_GPU2D_DIV] = imx_clk_hw_divider2("gpu2d_div",
> "gpu2d_cg", ccm_base + 0x8280, 0, 3);
> - hws[IMX8MP_CLK_AUDIO_AXI_DIV] =
> imx_clk_hw_divider2("audio_axi_div", "audio_axi_cg", ccm_base + 0x8300, 0,
> 3);
> - hws[IMX8MP_CLK_HSIO_AXI_DIV] = imx_clk_hw_divider2("hsio_axi_div",
> "hsio_axi_cg", ccm_base + 0x8380, 0, 3);
> - hws[IMX8MP_CLK_MEDIA_ISP_DIV] =
> imx_clk_hw_divider2("media_isp_div", "media_isp_cg", ccm_base + 0x8400, 0,
> 3);
> + hws[IMX8MP_CLK_A53_DIV] =
> imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base
> + 0x8000);
> + hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV];
> + hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV];
> + hws[IMX8MP_CLK_M7_CORE] =
> imx8m_clk_hw_composite_core("m7_core", imx8mp_m7_sels, ccm_base +
> 0x8080);
> + hws[IMX8MP_CLK_ML_CORE] =
> imx8m_clk_hw_composite_core("ml_core", imx8mp_ml_sels, ccm_base +
> 0x8100);
> + hws[IMX8MP_CLK_GPU3D_CORE] =
> imx8m_clk_hw_composite_core("gpu3d_core", imx8mp_gpu3d_core_sels,
> ccm_base + 0x8180);
> + hws[IMX8MP_CLK_GPU3D_SHADER_CORE] =
> imx8m_clk_hw_composite("gpu3d_shader_core", imx8mp_gpu3d_shader_sels,
> ccm_base + 0x8200);
> + hws[IMX8MP_CLK_GPU2D_CORE] =
> imx8m_clk_hw_composite("gpu2d_core", imx8mp_gpu2d_sels, ccm_base +
> 0x8280);
> + hws[IMX8MP_CLK_AUDIO_AXI] = imx8m_clk_hw_composite("audio_axi",
> imx8mp_audio_axi_sels, ccm_base + 0x8300);
> + hws[IMX8MP_CLK_AUDIO_AXI_SRC] = hws[IMX8MP_CLK_AUDIO_AXI];
> + hws[IMX8MP_CLK_HSIO_AXI] = imx8m_clk_hw_composite("hsio_axi",
> imx8mp_hsio_axi_sels, ccm_base + 0x8380);
> + hws[IMX8MP_CLK_MEDIA_ISP] = imx8m_clk_hw_composite("media_isp",
> +imx8mp_media_isp_sels, ccm_base + 0x8400);
>
> /* CORE SEL */
> hws[IMX8MP_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core",
> ccm_base + 0x9880, 24, 1, imx8mp_a53_core_sels,
> ARRAY_SIZE(imx8mp_a53_core_sels));
> @@ -713,8 +698,8 @@ static int imx8mp_clocks_probe(struct platform_device
> *pdev)
> hws[IMX8MP_CLK_SDMA1_ROOT] = imx_clk_hw_gate4("sdma1_root_clk",
> "ipg_root", ccm_base + 0x43a0, 0);
> hws[IMX8MP_CLK_ENET_QOS_ROOT] =
> imx_clk_hw_gate4("enet_qos_root_clk", "sim_enet_root_clk", ccm_base +
> 0x43b0, 0);
> hws[IMX8MP_CLK_SIM_ENET_ROOT] =
> imx_clk_hw_gate4("sim_enet_root_clk", "enet_axi", ccm_base + 0x4400, 0);
> - hws[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk",
> "gpu2d_div", ccm_base + 0x4450, 0);
> - hws[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk",
> "gpu3d_core_div", ccm_base + 0x4460, 0);
> + hws[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk",
> "gpu2d_core", ccm_base + 0x4450, 0);
> + hws[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk",
> +"gpu3d_core", ccm_base + 0x4460, 0);
> hws[IMX8MP_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk",
> "ipg_root", ccm_base + 0x4470, 0);
> hws[IMX8MP_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk",
> "uart1", ccm_base + 0x4490, 0);
> hws[IMX8MP_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk",
> "uart2", ccm_base + 0x44a0, 0); @@ -731,7 +716,7 @@ static int
> imx8mp_clocks_probe(struct platform_device *pdev)
> hws[IMX8MP_CLK_GPU_ROOT] = imx_clk_hw_gate4("gpu_root_clk",
> "gpu_axi", ccm_base + 0x4570, 0);
> hws[IMX8MP_CLK_VPU_VC8KE_ROOT] =
> imx_clk_hw_gate4("vpu_vc8ke_root_clk", "vpu_vc8000e", ccm_base + 0x4590,
> 0);
> hws[IMX8MP_CLK_VPU_G2_ROOT] =
> imx_clk_hw_gate4("vpu_g2_root_clk", "vpu_g2", ccm_base + 0x45a0, 0);
> - hws[IMX8MP_CLK_NPU_ROOT] = imx_clk_hw_gate4("npu_root_clk",
> "ml_div", ccm_base + 0x45b0, 0);
> + hws[IMX8MP_CLK_NPU_ROOT] = imx_clk_hw_gate4("npu_root_clk",
> "ml_core",
> +ccm_base + 0x45b0, 0);
> hws[IMX8MP_CLK_HSIO_ROOT] = imx_clk_hw_gate4("hsio_root_clk",
> "ipg_root", ccm_base + 0x45c0, 0);
> hws[IMX8MP_CLK_MEDIA_APB_ROOT] =
> imx_clk_hw_gate2_shared2("media_apb_root_clk", "media_apb", ccm_base +
> 0x45d0, 0, &share_count_media);
> hws[IMX8MP_CLK_MEDIA_AXI_ROOT] =
> imx_clk_hw_gate2_shared2("media_axi_root_clk", "media_axi", ccm_base +
> 0x45d0, 0, &share_count_media); @@ -739,7 +724,7 @@ static int
> imx8mp_clocks_probe(struct platform_device *pdev)
> hws[IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT] =
> imx_clk_hw_gate2_shared2("media_cam2_pix_root_clk", "media_cam2_pix",
> ccm_base + 0x45d0, 0, &share_count_media);
> hws[IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT] =
> imx_clk_hw_gate2_shared2("media_disp1_pix_root_clk", "media_disp1_pix",
> ccm_base + 0x45d0, 0, &share_count_media);
> hws[IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT] =
> imx_clk_hw_gate2_shared2("media_disp2_pix_root_clk", "media_disp2_pix",
> ccm_base + 0x45d0, 0, &share_count_media);
> - hws[IMX8MP_CLK_MEDIA_ISP_ROOT] =
> imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp_div", ccm_base
> + 0x45d0, 0, &share_count_media);
> + hws[IMX8MP_CLK_MEDIA_ISP_ROOT] =
> +imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp", ccm_base +
> +0x45d0, 0, &share_count_media);
>
> hws[IMX8MP_CLK_USDHC3_ROOT] =
> imx_clk_hw_gate4("usdhc3_root_clk", "usdhc3", ccm_base + 0x45e0, 0);
> hws[IMX8MP_CLK_HDMI_ROOT] = imx_clk_hw_gate4("hdmi_root_clk",
> "hdmi_axi", ccm_base + 0x45f0, 0); diff --git
> a/include/dt-bindings/clock/imx8mp-clock.h
> b/include/dt-bindings/clock/imx8mp-clock.h
> index 46c69cd66c62..8430bc4fd182 100644
> --- a/include/dt-bindings/clock/imx8mp-clock.h
> +++ b/include/dt-bindings/clock/imx8mp-clock.h
> @@ -313,6 +313,15 @@
> #define IMX8MP_SYS_PLL2_333M_CG 303
> #define IMX8MP_SYS_PLL2_500M_CG 304
>
> -#define IMX8MP_CLK_END 305
> +#define IMX8MP_CLK_M7_CORE 305
> +#define IMX8MP_CLK_ML_CORE 306
> +#define IMX8MP_CLK_GPU3D_CORE 307
> +#define IMX8MP_CLK_GPU3D_SHADER_CORE 308
> +#define IMX8MP_CLK_GPU2D_CORE 309
> +#define IMX8MP_CLK_AUDIO_AXI 310
> +#define IMX8MP_CLK_HSIO_AXI 311
> +#define IMX8MP_CLK_MEDIA_ISP 312
> +
> +#define IMX8MP_CLK_END 313
>
> #endif
> --
> 2.16.4
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next prev parent reply other threads:[~2020-04-26 4:38 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-12 10:19 [PATCH V2 00/10] clk: imx: fixes and improve for i.MX8M peng.fan
2020-03-12 10:19 ` peng.fan
2020-03-12 10:19 ` [PATCH V2 01/10] arm64: dts: imx8m: assign clocks for A53 peng.fan
2020-03-12 10:19 ` peng.fan
2020-04-26 3:51 ` Aisheng Dong
2020-04-26 3:51 ` Aisheng Dong
2020-03-12 10:19 ` [PATCH V2 02/10] clk: imx8m: drop clk_hw_set_parent " peng.fan
2020-03-12 10:19 ` peng.fan
2020-04-26 3:54 ` Aisheng Dong
2020-04-26 3:54 ` Aisheng Dong
2020-03-12 10:19 ` [PATCH V2 03/10] clk: imx: imx8mp: fix pll mux bit peng.fan
2020-03-12 10:19 ` peng.fan
2020-04-26 4:23 ` Aisheng Dong
2020-04-26 4:23 ` Aisheng Dong
2020-03-12 10:19 ` [PATCH V2 04/10] clk: imx8mp: Define gates for pll1/2 fixed dividers peng.fan
2020-03-12 10:19 ` peng.fan
2020-04-26 4:29 ` Aisheng Dong
2020-04-26 4:29 ` Aisheng Dong
2020-03-12 10:19 ` [PATCH V2 05/10] clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code peng.fan
2020-03-12 10:19 ` peng.fan
2020-04-26 4:38 ` Aisheng Dong [this message]
2020-04-26 4:38 ` Aisheng Dong
2020-04-27 8:57 ` Peng Fan
2020-04-27 8:57 ` Peng Fan
2020-03-12 10:19 ` [PATCH V2 06/10] clk: imx8m: migrate A53 clk root to use composite core peng.fan
2020-03-12 10:19 ` peng.fan
2020-04-26 4:43 ` Aisheng Dong
2020-04-26 4:43 ` Aisheng Dong
2020-04-27 8:58 ` Peng Fan
2020-04-27 8:58 ` Peng Fan
2020-03-12 10:19 ` [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk peng.fan
2020-03-12 10:19 ` peng.fan
2020-04-24 19:29 ` Leonard Crestez
2020-04-24 19:29 ` Leonard Crestez
2020-04-27 9:15 ` Peng Fan
2020-04-27 9:15 ` Peng Fan
2020-04-27 19:34 ` Leonard Crestez
2020-04-27 19:34 ` Leonard Crestez
2020-04-28 1:08 ` Peng Fan
2020-04-28 1:08 ` Peng Fan
2020-04-26 5:08 ` Aisheng Dong
2020-04-26 5:08 ` Aisheng Dong
2020-04-27 9:11 ` Peng Fan
2020-04-27 9:11 ` Peng Fan
2020-04-30 10:00 ` Abel Vesa
2020-04-30 10:00 ` Abel Vesa
2020-04-30 12:56 ` Peng Fan
2020-04-30 12:56 ` Peng Fan
2020-03-12 10:19 ` [PATCH V2 08/10] clk: imx: add imx8m_clk_hw_composite_bus peng.fan
2020-03-12 10:19 ` peng.fan
2020-03-12 10:19 ` [PATCH V2 09/10] clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice peng.fan
2020-03-12 10:19 ` peng.fan
2020-03-12 10:19 ` [PATCH V2 10/10] clk: imx8mp: mark memrepair clock as critical peng.fan
2020-03-12 10:19 ` peng.fan
2020-03-19 10:04 ` [PATCH V2 00/10] clk: imx: fixes and improve for i.MX8M Peng Fan
2020-03-19 10:04 ` Peng Fan
2020-04-18 13:45 ` Peng Fan
2020-04-18 13:45 ` Peng Fan
2020-04-24 19:30 ` Leonard Crestez
2020-04-24 19:30 ` Leonard Crestez
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