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* [PATCH] drm/amdgpu: Fix channel_index table layout for Aldebaran
@ 2021-07-29 15:37 Mukul Joshi
  2021-07-29 15:50 ` Clements, John
  2021-08-02  3:50 ` Chen, Guchun
  0 siblings, 2 replies; 3+ messages in thread
From: Mukul Joshi @ 2021-07-29 15:37 UTC (permalink / raw)
  To: amd-gfx; +Cc: Mukul Joshi, john.clements, Hawking.Zhang

Fix the channel_index table layout to fetch the correct
channel_index when calculating physical address from
normalized address during page retirement.
Also, fix the number of UMC instances and number of channels
within each UMC instance for Aldebaran.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |  4 ++--
 drivers/gpu/drm/amd/amdgpu/umc_v6_7.c | 16 ++++++++--------
 drivers/gpu/drm/amd/amdgpu/umc_v6_7.h |  4 ++--
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 7cf653f9e9a7..097230b5e946 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1171,8 +1171,8 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
 		break;
 	case CHIP_ALDEBARAN:
 		adev->umc.max_ras_err_cnt_per_query = UMC_V6_7_TOTAL_CHANNEL_NUM;
-		adev->umc.channel_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;
-		adev->umc.umc_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;
+		adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;
+		adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;
 		adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET;
 		if (!adev->gmc.xgmi.connected_to_cpu)
 			adev->umc.ras_funcs = &umc_v6_7_ras_funcs;
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
index 7da12110425c..bb30336b1e8d 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
@@ -30,17 +30,17 @@
 
 const uint32_t
 	umc_v6_7_channel_idx_tbl_second[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM] = {
-		{28, 12, 6, 22},	{19, 3, 9, 25},
-		{20, 4, 30, 14},	{11, 27, 1, 17},
-		{24, 8, 2, 18},		{15, 31, 5, 21},
-		{16, 0, 26, 10},	{7, 23, 29, 13}
+		{28, 20, 24, 16, 12, 4, 8, 0},
+		{6, 30, 2, 26, 22, 14, 18, 10},
+		{19, 11, 15, 7, 3, 27, 31, 23},
+		{9, 1, 5, 29, 25, 17, 21, 13}
 };
 const uint32_t
 	umc_v6_7_channel_idx_tbl_first[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM] = {
-		{19, 3, 9, 25},		{28, 12, 6, 22},
-		{11, 27, 1, 17},	{20, 4, 30, 14},
-		{15, 31, 5, 21},	{24, 8, 2, 18},
-		{7, 23, 29, 13},	{16, 0, 26, 10}
+		{19, 11, 15, 7,	3, 27, 31, 23},
+		{9, 1, 5, 29, 25, 17, 21, 13},
+		{28, 20, 24, 16, 12, 4, 8, 0},
+		{6, 30, 2, 26, 22, 14, 18, 10},
 };
 
 static inline uint32_t get_umc_v6_7_reg_offset(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h
index 81b8f1844091..57f2557e7aca 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h
@@ -36,9 +36,9 @@
 #define UMC_V6_7_INST_DIST	0x40000
 
 /* number of umc channel instance with memory map register access */
-#define UMC_V6_7_CHANNEL_INSTANCE_NUM		4
+#define UMC_V6_7_UMC_INSTANCE_NUM		4
 /* number of umc instance with memory map register access */
-#define UMC_V6_7_UMC_INSTANCE_NUM		8
+#define UMC_V6_7_CHANNEL_INSTANCE_NUM		8
 /* total channel instances in one umc block */
 #define UMC_V6_7_TOTAL_CHANNEL_NUM	(UMC_V6_7_CHANNEL_INSTANCE_NUM * UMC_V6_7_UMC_INSTANCE_NUM)
 /* UMC regiser per channel offset */
-- 
2.17.1

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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 3+ messages in thread
* Re: [PATCH] drm/amdgpu: Fix channel_index table layout for Aldebaran
  2021-07-29 15:37 [PATCH] drm/amdgpu: Fix channel_index table layout for Aldebaran Mukul Joshi
@ 2021-07-29 15:50 ` Clements, John
  2021-08-02  3:50 ` Chen, Guchun
  1 sibling, 0 replies; 3+ messages in thread
From: Clements, John @ 2021-07-29 15:50 UTC (permalink / raw)
  To: Joshi, Mukul, amd-gfx; +Cc: Zhang, Hawking


[-- Attachment #1.1: Type: text/plain, Size: 4182 bytes --]

[AMD Official Use Only]

Reviewed-By: John Clements <john.clements@amd.com>

________________________________
From: Joshi, Mukul <Mukul.Joshi@amd.com>
Sent: Thursday, July 29, 2021 11:37 PM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Cc: Clements, John <John.Clements@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Joshi, Mukul <Mukul.Joshi@amd.com>
Subject: [PATCH] drm/amdgpu: Fix channel_index table layout for Aldebaran

Fix the channel_index table layout to fetch the correct
channel_index when calculating physical address from
normalized address during page retirement.
Also, fix the number of UMC instances and number of channels
within each UMC instance for Aldebaran.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |  4 ++--
 drivers/gpu/drm/amd/amdgpu/umc_v6_7.c | 16 ++++++++--------
 drivers/gpu/drm/amd/amdgpu/umc_v6_7.h |  4 ++--
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 7cf653f9e9a7..097230b5e946 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1171,8 +1171,8 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
                 break;
         case CHIP_ALDEBARAN:
                 adev->umc.max_ras_err_cnt_per_query = UMC_V6_7_TOTAL_CHANNEL_NUM;
-               adev->umc.channel_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;
-               adev->umc.umc_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;
+               adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;
+               adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;
                 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET;
                 if (!adev->gmc.xgmi.connected_to_cpu)
                         adev->umc.ras_funcs = &umc_v6_7_ras_funcs;
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
index 7da12110425c..bb30336b1e8d 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
@@ -30,17 +30,17 @@

 const uint32_t
         umc_v6_7_channel_idx_tbl_second[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM] = {
-               {28, 12, 6, 22},        {19, 3, 9, 25},
-               {20, 4, 30, 14},        {11, 27, 1, 17},
-               {24, 8, 2, 18},         {15, 31, 5, 21},
-               {16, 0, 26, 10},        {7, 23, 29, 13}
+               {28, 20, 24, 16, 12, 4, 8, 0},
+               {6, 30, 2, 26, 22, 14, 18, 10},
+               {19, 11, 15, 7, 3, 27, 31, 23},
+               {9, 1, 5, 29, 25, 17, 21, 13}
 };
 const uint32_t
         umc_v6_7_channel_idx_tbl_first[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM] = {
-               {19, 3, 9, 25},         {28, 12, 6, 22},
-               {11, 27, 1, 17},        {20, 4, 30, 14},
-               {15, 31, 5, 21},        {24, 8, 2, 18},
-               {7, 23, 29, 13},        {16, 0, 26, 10}
+               {19, 11, 15, 7, 3, 27, 31, 23},
+               {9, 1, 5, 29, 25, 17, 21, 13},
+               {28, 20, 24, 16, 12, 4, 8, 0},
+               {6, 30, 2, 26, 22, 14, 18, 10},
 };

 static inline uint32_t get_umc_v6_7_reg_offset(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h
index 81b8f1844091..57f2557e7aca 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h
@@ -36,9 +36,9 @@
 #define UMC_V6_7_INST_DIST      0x40000

 /* number of umc channel instance with memory map register access */
-#define UMC_V6_7_CHANNEL_INSTANCE_NUM          4
+#define UMC_V6_7_UMC_INSTANCE_NUM              4
 /* number of umc instance with memory map register access */
-#define UMC_V6_7_UMC_INSTANCE_NUM              8
+#define UMC_V6_7_CHANNEL_INSTANCE_NUM          8
 /* total channel instances in one umc block */
 #define UMC_V6_7_TOTAL_CHANNEL_NUM      (UMC_V6_7_CHANNEL_INSTANCE_NUM * UMC_V6_7_UMC_INSTANCE_NUM)
 /* UMC regiser per channel offset */
--
2.17.1


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[-- Attachment #2: Type: text/plain, Size: 154 bytes --]

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 3+ messages in thread
* RE: [PATCH] drm/amdgpu: Fix channel_index table layout for Aldebaran
  2021-07-29 15:37 [PATCH] drm/amdgpu: Fix channel_index table layout for Aldebaran Mukul Joshi
  2021-07-29 15:50 ` Clements, John
@ 2021-08-02  3:50 ` Chen, Guchun
  1 sibling, 0 replies; 3+ messages in thread
From: Chen, Guchun @ 2021-08-02  3:50 UTC (permalink / raw)
  To: Joshi, Mukul, amd-gfx; +Cc: Joshi, Mukul, Clements, John, Zhang, Hawking

[Public]

/* number of umc channel instance with memory map register access */
-#define UMC_V6_7_CHANNEL_INSTANCE_NUM		4
+#define UMC_V6_7_UMC_INSTANCE_NUM		4
 /* number of umc instance with memory map register access */
-#define UMC_V6_7_UMC_INSTANCE_NUM		8
+#define UMC_V6_7_CHANNEL_INSTANCE_NUM		8

Please update the comments accordingly as well.

Regards,
Guchun

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Mukul Joshi
Sent: Thursday, July 29, 2021 11:38 PM
To: amd-gfx@lists.freedesktop.org
Cc: Joshi, Mukul <Mukul.Joshi@amd.com>; Clements, John <John.Clements@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>
Subject: [PATCH] drm/amdgpu: Fix channel_index table layout for Aldebaran

Fix the channel_index table layout to fetch the correct channel_index when calculating physical address from normalized address during page retirement.
Also, fix the number of UMC instances and number of channels within each UMC instance for Aldebaran.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |  4 ++--  drivers/gpu/drm/amd/amdgpu/umc_v6_7.c | 16 ++++++++--------  drivers/gpu/drm/amd/amdgpu/umc_v6_7.h |  4 ++--
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 7cf653f9e9a7..097230b5e946 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1171,8 +1171,8 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
 		break;
 	case CHIP_ALDEBARAN:
 		adev->umc.max_ras_err_cnt_per_query = UMC_V6_7_TOTAL_CHANNEL_NUM;
-		adev->umc.channel_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;
-		adev->umc.umc_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;
+		adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;
+		adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;
 		adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET;
 		if (!adev->gmc.xgmi.connected_to_cpu)
 			adev->umc.ras_funcs = &umc_v6_7_ras_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
index 7da12110425c..bb30336b1e8d 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
@@ -30,17 +30,17 @@
 
 const uint32_t
 	umc_v6_7_channel_idx_tbl_second[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM] = {
-		{28, 12, 6, 22},	{19, 3, 9, 25},
-		{20, 4, 30, 14},	{11, 27, 1, 17},
-		{24, 8, 2, 18},		{15, 31, 5, 21},
-		{16, 0, 26, 10},	{7, 23, 29, 13}
+		{28, 20, 24, 16, 12, 4, 8, 0},
+		{6, 30, 2, 26, 22, 14, 18, 10},
+		{19, 11, 15, 7, 3, 27, 31, 23},
+		{9, 1, 5, 29, 25, 17, 21, 13}
 };
 const uint32_t
 	umc_v6_7_channel_idx_tbl_first[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM] = {
-		{19, 3, 9, 25},		{28, 12, 6, 22},
-		{11, 27, 1, 17},	{20, 4, 30, 14},
-		{15, 31, 5, 21},	{24, 8, 2, 18},
-		{7, 23, 29, 13},	{16, 0, 26, 10}
+		{19, 11, 15, 7,	3, 27, 31, 23},
+		{9, 1, 5, 29, 25, 17, 21, 13},
+		{28, 20, 24, 16, 12, 4, 8, 0},
+		{6, 30, 2, 26, 22, 14, 18, 10},
 };
 
 static inline uint32_t get_umc_v6_7_reg_offset(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h
index 81b8f1844091..57f2557e7aca 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h
@@ -36,9 +36,9 @@
 #define UMC_V6_7_INST_DIST	0x40000
 
 /* number of umc channel instance with memory map register access */
-#define UMC_V6_7_CHANNEL_INSTANCE_NUM		4
+#define UMC_V6_7_UMC_INSTANCE_NUM		4
 /* number of umc instance with memory map register access */
-#define UMC_V6_7_UMC_INSTANCE_NUM		8
+#define UMC_V6_7_CHANNEL_INSTANCE_NUM		8
 /* total channel instances in one umc block */
 #define UMC_V6_7_TOTAL_CHANNEL_NUM	(UMC_V6_7_CHANNEL_INSTANCE_NUM * UMC_V6_7_UMC_INSTANCE_NUM)
 /* UMC regiser per channel offset */
--
2.17.1

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^ permalink raw reply related	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2021-08-02  3:50 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2021-07-29 15:37 [PATCH] drm/amdgpu: Fix channel_index table layout for Aldebaran Mukul Joshi
2021-07-29 15:50 ` Clements, John
2021-08-02  3:50 ` Chen, Guchun

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