[Intel-gfx] [PATCH V3 0/8] drm/i915/gt: Initialize unused MOCS entries to L3_WB

[Intel-gfx] [PATCH V3 0/8] drm/i915/gt: Initialize unused MOCS entries to L3_WB

[Ayaz A Siddiqui]

Gen >= 12 onwards MOCS table doesn't have a setting for PTE
so I915_MOCS_PTE is not a valid index and it will have different
MOCS values are based on the platform.

To detect these kinds of misprogramming, all the unspecified and
reserved MOCS indexes are set to WB_L3. TGL/RKL unspecified MOCS
indexes are pointing to L3 UC are kept intact to avoid API break.

This series also contains patches to program BLIT_CCTL and
CMD_CCTL registers to UC.
Since we are quite late to update MOCS table for TGL so added
a new MOCS table for ADL family.

V2:
  1. Added CMD_CCTL to GUC regset list so that it can be restored
     after engine reset.
  2. Checkpatch warning removal.

V3:
 1. Changed implementation to have a framework only.
 2. Added register type for proper application.
 3. moved CMD_CCTL programming to a separate patch.
 4. Added L3CC initialization during gt reset so that MOCS indexes are
    set before GuC initialization. 
 5. Removed Renderer check for L3CC verification in selftest.

Apoorva Singh (1):
  drm/i915/gt: Set BLIT_CCTL reg to un-cached

Ayaz A Siddiqui (5):
  drm/i915/gt: Add support of mocs propagation
  drm/i915/gt: Set CMD_CCTL to UC for Gen12 Onward
  drm/i915/gt: Initialize unused MOCS entries with device specific
    values
  drm/i95/adl: Define MOCS table for Alderlake
  drm/i915/selftest: Remove Renderer class check for l3cc table read

Sreedhar Telukuntla (1):
  drm/i915/gt: Initialize L3CC table in mocs init

Srinivasan Shanmugam (1):
  drm/i915/gt: Add support of mocs auxiliary registers programming

 drivers/gpu/drm/i915/gt/intel_gt.c         |   5 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h   |   4 +
 drivers/gpu/drm/i915/gt/intel_mocs.c       | 314 +++++++++++++++++++--
 drivers/gpu/drm/i915/gt/intel_mocs.h       |   5 +
 drivers/gpu/drm/i915/gt/selftest_mocs.c    |  53 +++-
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c |  17 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h |  15 +
 drivers/gpu/drm/i915/i915_reg.h            |  23 ++
 8 files changed, 399 insertions(+), 37 deletions(-)

-- 
2.26.2

[Intel-gfx] [PATCH V3 1/8] drm/i915/gt: Add support of mocs propagation

[Ayaz A Siddiqui]

Now there are lots of Command and registers that require mocs index
programming.
So propagating mocs_index from mocs to gt so that it can be
used directly without having platform-specific checks.

Cc: CQ Tang<cq.tang@intel.com>
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_types.h |  4 ++++
 drivers/gpu/drm/i915/gt/intel_mocs.c     | 10 ++++++++++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index a81e21bf1bd1a..88601a2d2c229 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -192,6 +192,10 @@ struct intel_gt {
 
 		unsigned long mslice_mask;
 	} info;
+
+	struct i915_mocs_index_gt {
+		u8 uc_index;
+	} mocs;
 };
 
 enum intel_gt_scratch_field {
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 582c4423b95d6..10cc508c1a4f6 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -22,6 +22,7 @@ struct drm_i915_mocs_table {
 	unsigned int size;
 	unsigned int n_entries;
 	const struct drm_i915_mocs_entry *table;
+	u8 uc_index;
 };
 
 /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
@@ -340,6 +341,8 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
 {
 	unsigned int flags;
 
+	memset(table, 0, sizeof(struct drm_i915_mocs_table));
+
 	if (IS_DG1(i915)) {
 		table->size = ARRAY_SIZE(dg1_mocs_table);
 		table->table = dg1_mocs_table;
@@ -504,6 +507,12 @@ static u32 global_mocs_offset(void)
 	return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0));
 }
 
+static void set_mocs_index(struct intel_gt *gt,
+			   struct drm_i915_mocs_table *table)
+{
+	gt->mocs.uc_index = table->uc_index;
+}
+
 void intel_mocs_init(struct intel_gt *gt)
 {
 	struct drm_i915_mocs_table table;
@@ -515,6 +524,7 @@ void intel_mocs_init(struct intel_gt *gt)
 	flags = get_mocs_settings(gt->i915, &table);
 	if (flags & HAS_GLOBAL_MOCS)
 		__init_mocs_table(gt->uncore, &table, global_mocs_offset());
+	set_mocs_index(gt, &table);
 }
 
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
-- 
2.26.2

Re: [Intel-gfx] [PATCH V3 1/8] drm/i915/gt: Add support of mocs propagation

[Matt Roper]

On Mon, Aug 30, 2021 at 09:52:33PM +0530, Ayaz A Siddiqui wrote:
> Now there are lots of Command and registers that require mocs index
> programming.
> So propagating mocs_index from mocs to gt so that it can be
> used directly without having platform-specific checks.
> 
> Cc: CQ Tang<cq.tang@intel.com>
> Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_types.h |  4 ++++
>  drivers/gpu/drm/i915/gt/intel_mocs.c     | 10 ++++++++++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index a81e21bf1bd1a..88601a2d2c229 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -192,6 +192,10 @@ struct intel_gt {
>  
>  		unsigned long mslice_mask;
>  	} info;
> +
> +	struct i915_mocs_index_gt {

Do we actually plan to use the name 'i915_mocs_index_gt' anywhere else
in the code?  If not, an anonymous struct is probably fine.

> +		u8 uc_index;
> +	} mocs;
>  };
>  
>  enum intel_gt_scratch_field {
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 582c4423b95d6..10cc508c1a4f6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -22,6 +22,7 @@ struct drm_i915_mocs_table {
>  	unsigned int size;
>  	unsigned int n_entries;
>  	const struct drm_i915_mocs_entry *table;
> +	u8 uc_index;
>  };
>  
>  /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
> @@ -340,6 +341,8 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
>  {
>  	unsigned int flags;
>  
> +	memset(table, 0, sizeof(struct drm_i915_mocs_table));
> +
>  	if (IS_DG1(i915)) {
>  		table->size = ARRAY_SIZE(dg1_mocs_table);
>  		table->table = dg1_mocs_table;
> @@ -504,6 +507,12 @@ static u32 global_mocs_offset(void)
>  	return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0));
>  }
>  
> +static void set_mocs_index(struct intel_gt *gt,
> +			   struct drm_i915_mocs_table *table)
> +{
> +	gt->mocs.uc_index = table->uc_index;
> +}
> +
>  void intel_mocs_init(struct intel_gt *gt)
>  {
>  	struct drm_i915_mocs_table table;
> @@ -515,6 +524,7 @@ void intel_mocs_init(struct intel_gt *gt)
>  	flags = get_mocs_settings(gt->i915, &table);
>  	if (flags & HAS_GLOBAL_MOCS)
>  		__init_mocs_table(gt->uncore, &table, global_mocs_offset());
> +	set_mocs_index(gt, &table);

We could probably just inline the 

        gt->mocs.uc_index = table->uc_index;

rather than creating a separate function; it doesn't look like
set_mocs_index() gets used anywhere else.

Aside from the two minor cleanups,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

>  }
>  
>  #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> -- 
> 2.26.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

[Intel-gfx] [PATCH V3 2/8] drm/i915/gt: Add support of mocs auxiliary registers programming

[Ayaz A Siddiqui]

From: Srinivasan Shanmugam <srinivasan.s@intel.com>

Few registers need to be programmed with
appropriate MOCS indexes for proper functioning.
As of now, there are two categories of registers that
need to be programmed, these are engine power domains
register and engine state context register.

A framework is being added to handle programming and
verification of those registers.

To add a register in the future we just need to add it
in build_aux_regs(), the rest will be taken care of by
the framework.

V2: (Ayaz)
 Added CMD_CCTL in guc_mmio_regset_init(), so that this
 register can restored after engine reset.

V3: (Ayaz)
 1. Changed implementation to have a framework only.
 2. Added register type for proper application.
 3. Removed CMD_CCTL programming.

Cc: Chris Wilson <chris.p.wilson@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.s@intel.com>
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt.c         |   5 +
 drivers/gpu/drm/i915/gt/intel_mocs.c       | 184 +++++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_mocs.h       |   5 +
 drivers/gpu/drm/i915/gt/selftest_mocs.c    |  49 ++++++
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c |  17 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h |  15 ++
 6 files changed, 263 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 62d40c9866427..ccb257d5282f4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -21,6 +21,7 @@
 #include "intel_uncore.h"
 #include "intel_pm.h"
 #include "shmem_utils.h"
+#include "intel_mocs.h"
 
 void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
 {
@@ -530,6 +531,10 @@ static int __engines_record_defaults(struct intel_gt *gt)
 		if (err)
 			goto err_rq;
 
+		err  = apply_mocs_aux_regs_ctx(rq);
+		if (err)
+			goto err_rq;
+
 		err = intel_renderstate_emit(&so, rq);
 		if (err)
 			goto err_rq;
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 10cc508c1a4f6..c52640523c218 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -10,6 +10,8 @@
 #include "intel_lrc_reg.h"
 #include "intel_mocs.h"
 #include "intel_ring.h"
+#include "intel_gpu_commands.h"
+#include "uc/intel_guc_ads.h"
 
 /* structures required */
 struct drm_i915_mocs_entry {
@@ -25,6 +27,28 @@ struct drm_i915_mocs_table {
 	u8 uc_index;
 };
 
+enum register_type {
+	/*
+	 * REG_GT: General register - Need to  be re-plied after GT/GPU reset
+	 * REG_ENGINE: Domain register - needs to be re-applied after
+	 *	       engine reset
+	 * REG_ENGINE_CONTEXT: Engine state context register - need to stored
+	 *		       as part of Golden context.
+	 */
+	REG_GT = 0,
+	REG_ENGINE,
+	REG_ENGINE_CONTEXT
+};
+
+struct drm_i915_aux_table {
+	enum register_type type;
+	const char *name;
+	i915_reg_t offset;
+	u32 value;
+	u32 readmask;
+	struct drm_i915_aux_table *next;
+};
+
 /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
 #define _LE_CACHEABILITY(value)	((value) << 0)
 #define _LE_TGT_CACHE(value)	((value) << 2)
@@ -336,6 +360,78 @@ static bool has_mocs(const struct drm_i915_private *i915)
 	return !IS_DGFX(i915);
 }
 
+static struct drm_i915_aux_table *
+add_aux_reg(struct drm_i915_aux_table *aux,
+	    enum register_type type,
+	    const char *name,
+	    i915_reg_t offset,
+	    u32 value,
+	    u32 read)
+{
+	struct drm_i915_aux_table *x;
+
+	x = kmalloc(sizeof(*x), GFP_ATOMIC);
+	if (!x) {
+		DRM_ERROR("Failed to allocate aux reg '%s'\n", name);
+		return aux;
+	}
+
+	x->type = type;
+	x->name = name;
+	x->offset = offset;
+	x->value = value;
+	x->readmask = read;
+
+	x->next = aux;
+	return x;
+}
+
+static const struct drm_i915_aux_table *
+build_aux_regs(const struct intel_engine_cs *engine,
+	       const struct drm_i915_mocs_table *mocs)
+{
+	struct drm_i915_aux_table *aux = NULL;
+
+	if (GRAPHICS_VER(engine->i915) >= 12 &&
+	    !drm_WARN_ONCE(&engine->i915->drm, !mocs->uc_index,
+	    "Platform that should have UC index defined and does not\n")) {
+		/*
+		 * Add Auxiliary register which needs to be programmed with
+		 * UC MOCS index. We need to call add_aux_reg() to add
+		 * a entry in drm_i915_aux_table link list.
+		 */
+	}
+	return aux;
+}
+
+static void
+free_aux_regs(const struct drm_i915_aux_table *aux)
+{
+	while (aux) {
+		struct drm_i915_aux_table *next = aux->next;
+
+		kfree(aux);
+		aux = next;
+	}
+}
+
+static void apply_aux_regs_engine(struct intel_engine_cs *engine,
+				  const struct drm_i915_aux_table *aux)
+{
+	u32 mmio_reg_offset;
+
+	while (aux) {
+		if (aux->type == REG_ENGINE) {
+			mmio_reg_offset = i915_mmio_reg_offset(aux->offset);
+			intel_uncore_write_fw(engine->uncore,
+					      _MMIO(engine->mmio_base +
+					      mmio_reg_offset),
+					      aux->value);
+		}
+		aux = aux->next;
+	}
+}
+
 static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
 				      struct drm_i915_mocs_table *table)
 {
@@ -347,10 +443,12 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
 		table->size = ARRAY_SIZE(dg1_mocs_table);
 		table->table = dg1_mocs_table;
 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
+		table->uc_index = 1;
 	} else if (GRAPHICS_VER(i915) >= 12) {
 		table->size  = ARRAY_SIZE(tgl_mocs_table);
 		table->table = tgl_mocs_table;
 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
+		table->uc_index = 3;
 	} else if (GRAPHICS_VER(i915) == 11) {
 		table->size  = ARRAY_SIZE(icl_mocs_table);
 		table->table = icl_mocs_table;
@@ -395,6 +493,87 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
 	return flags;
 }
 
+int get_ctx_reg_count(const struct drm_i915_aux_table *aux)
+{
+	int count = 0;
+
+	while (aux) {
+		if (aux->type == REG_ENGINE_CONTEXT)
+			count++;
+		aux = aux->next;
+	}
+	return count;
+}
+
+void add_aux_mocs_guc_mmio_regset(struct temp_regset *regset,
+				  struct intel_engine_cs *engine)
+{
+	const struct drm_i915_aux_table *aux;
+	struct drm_i915_mocs_table table;
+	int ret;
+
+	ret = get_mocs_settings(engine->i915, &table);
+	if (!ret)
+		return;
+
+	aux = build_aux_regs(engine, &table);
+	if (!aux)
+		return;
+
+	while (aux) {
+		if (aux->type == REG_ENGINE)
+			GUC_MMIO_REG_ADD(regset,
+					 _MMIO(engine->mmio_base
+					 + i915_mmio_reg_offset(aux->offset)),
+					 true);
+		aux = aux->next;
+	}
+	free_aux_regs(aux);
+}
+
+int apply_mocs_aux_regs_ctx(struct i915_request *rq)
+{
+	const struct drm_i915_aux_table *aux;
+	struct drm_i915_mocs_table table;
+	u32 *cs;
+	int ret, count;
+
+	ret = get_mocs_settings(rq->engine->i915, &table);
+	if (!ret)
+		return 0;
+
+	aux = build_aux_regs(rq->engine, &table);
+
+	count = get_ctx_reg_count(aux);
+	if (!count)
+		return 0;
+	ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
+	if (ret)
+		return ret;
+
+	cs = intel_ring_begin(rq, (count * 2 + 2));
+	if (IS_ERR(cs))
+		return PTR_ERR(cs);
+
+	*cs++ = MI_LOAD_REGISTER_IMM(count);
+	while (aux) {
+		if (aux->type == REG_ENGINE_CONTEXT) {
+			*cs++ = i915_mmio_reg_offset(aux->offset);
+			*cs++ = aux->value;
+		}
+		aux = aux->next;
+	}
+	*cs++ = MI_NOOP;
+
+	intel_ring_advance(rq, cs);
+	free_aux_regs(aux);
+	ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
 /*
  * Get control_value from MOCS entry taking into account when it's not used:
  * I915_MOCS_PTE's value is returned in this case.
@@ -484,6 +663,7 @@ static void init_l3cc_table(struct intel_engine_cs *engine,
 
 void intel_mocs_init_engine(struct intel_engine_cs *engine)
 {
+	const struct drm_i915_aux_table *aux;
 	struct drm_i915_mocs_table table;
 	unsigned int flags;
 
@@ -500,6 +680,10 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
 
 	if (flags & HAS_RENDER_L3CC && engine->class == RENDER_CLASS)
 		init_l3cc_table(engine, &table);
+
+	aux = build_aux_regs(engine, &table);
+	apply_aux_regs_engine(engine, aux);
+	free_aux_regs(aux);
 }
 
 static u32 global_mocs_offset(void)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h b/drivers/gpu/drm/i915/gt/intel_mocs.h
index d83274f5163bd..0f362a0acc3a3 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.h
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
@@ -33,8 +33,13 @@
 
 struct intel_engine_cs;
 struct intel_gt;
+struct i915_request;
+struct temp_regset;
 
 void intel_mocs_init(struct intel_gt *gt);
 void intel_mocs_init_engine(struct intel_engine_cs *engine);
+int apply_mocs_aux_regs_ctx(struct i915_request *rq);
+void add_aux_mocs_guc_mmio_regset(struct temp_regset *regset,
+				  struct intel_engine_cs *engine);
 
 #endif
diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
index 13d25bf2a94aa..2b0207dfbf21c 100644
--- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
@@ -155,6 +155,47 @@ static int read_l3cc_table(struct i915_request *rq,
 	return read_regs(rq, addr, (table->n_entries + 1) / 2, offset);
 }
 
+static int read_aux_regs(struct i915_request *rq,
+			 const struct drm_i915_aux_table *r,
+			 u32 *offset)
+{
+	int err;
+
+	while (r) {
+		err = read_regs(rq,
+				rq->engine->mmio_base + i915_mmio_reg_offset(r->offset), 1,
+				offset);
+		if (err)
+			return err;
+
+		r = r->next;
+	}
+
+	return 0;
+}
+
+static int check_aux_regs(struct intel_engine_cs *engine,
+			  const struct drm_i915_aux_table *r,
+			  u32 **vaddr)
+{
+	while (r) {
+		u32 expect = r->value & r->readmask;
+		u32 masked_value = **vaddr & r->readmask;
+
+		if (masked_value != expect) {
+			pr_err("%s: Invalid entry %s[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x\n",
+			       engine->name, r->name,
+			       i915_mmio_reg_offset(r->offset), **vaddr,
+			       masked_value, expect);
+			return -EINVAL;
+		}
+		++*vaddr;
+		r = r->next;
+	}
+
+	return 0;
+}
+
 static int check_mocs_table(struct intel_engine_cs *engine,
 			    const struct drm_i915_mocs_table *table,
 			    u32 **vaddr)
@@ -216,6 +257,7 @@ static int check_mocs_engine(struct live_mocs *arg,
 			     struct intel_context *ce)
 {
 	struct i915_vma *vma = arg->scratch;
+	const struct drm_i915_aux_table *aux;
 	struct i915_request *rq;
 	u32 offset;
 	u32 *vaddr;
@@ -223,6 +265,8 @@ static int check_mocs_engine(struct live_mocs *arg,
 
 	memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE / sizeof(u32));
 
+	aux = build_aux_regs(ce->engine, &arg->table);
+
 	rq = intel_context_create_request(ce);
 	if (IS_ERR(rq))
 		return PTR_ERR(rq);
@@ -239,6 +283,8 @@ static int check_mocs_engine(struct live_mocs *arg,
 		err = read_mocs_table(rq, arg->mocs, &offset);
 	if (!err && ce->engine->class == RENDER_CLASS)
 		err = read_l3cc_table(rq, arg->l3cc, &offset);
+	if (!err)
+		err = read_aux_regs(rq, aux, &offset);
 	offset -= i915_ggtt_offset(vma);
 	GEM_BUG_ON(offset > PAGE_SIZE);
 
@@ -252,10 +298,13 @@ static int check_mocs_engine(struct live_mocs *arg,
 		err = check_mocs_table(ce->engine, arg->mocs, &vaddr);
 	if (!err && ce->engine->class == RENDER_CLASS)
 		err = check_l3cc_table(ce->engine, arg->l3cc, &vaddr);
+	if (!err)
+		err = check_aux_regs(ce->engine, aux, &vaddr);
 	if (err)
 		return err;
 
 	GEM_BUG_ON(arg->vaddr + offset != vaddr);
+	free_aux_regs(aux);
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 6926919bcac6b..be4cca49abced 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -12,6 +12,7 @@
 #include "intel_guc_fwif.h"
 #include "intel_uc.h"
 #include "i915_drv.h"
+#include "gt/intel_mocs.h"
 
 /*
  * The Additional Data Struct (ADS) has pointers for different buffers used by
@@ -187,11 +188,6 @@ static void guc_mapping_table_init(struct intel_gt *gt,
  * inside the ADS.
  */
 #define MAX_MMIO_REGS	128	/* Arbitrary size, increase as needed */
-struct temp_regset {
-	struct guc_mmio_reg *registers;
-	u32 used;
-	u32 size;
-};
 
 static int guc_mmio_reg_cmp(const void *a, const void *b)
 {
@@ -201,8 +197,8 @@ static int guc_mmio_reg_cmp(const void *a, const void *b)
 	return (int)ra->offset - (int)rb->offset;
 }
 
-static void guc_mmio_reg_add(struct temp_regset *regset,
-			     u32 offset, u32 flags)
+void guc_mmio_reg_add(struct temp_regset *regset,
+		      u32 offset, u32 flags)
 {
 	u32 count = regset->used;
 	struct guc_mmio_reg reg = {
@@ -236,11 +232,6 @@ static void guc_mmio_reg_add(struct temp_regset *regset,
 	}
 }
 
-#define GUC_MMIO_REG_ADD(regset, reg, masked) \
-	guc_mmio_reg_add(regset, \
-			 i915_mmio_reg_offset((reg)), \
-			 (masked) ? GUC_REGSET_MASKED : 0)
-
 static void guc_mmio_regset_init(struct temp_regset *regset,
 				 struct intel_engine_cs *engine)
 {
@@ -258,6 +249,8 @@ static void guc_mmio_regset_init(struct temp_regset *regset,
 	for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
 		GUC_MMIO_REG_ADD(regset, wa->reg, wa->masked_reg);
 
+	add_aux_mocs_guc_mmio_regset(regset, engine);
+
 	/* Be extra paranoid and include all whitelist registers. */
 	for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++)
 		GUC_MMIO_REG_ADD(regset,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
index 3d85051d57e45..75736c56fa187 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
@@ -6,9 +6,24 @@
 #ifndef _INTEL_GUC_ADS_H_
 #define _INTEL_GUC_ADS_H_
 
+#include <linux/types.h>
+
+struct temp_regset {
+	struct guc_mmio_reg *registers;
+	u32 used;
+	u32 size;
+};
+
 struct intel_guc;
 struct drm_printer;
 
+void guc_mmio_reg_add(struct temp_regset *regset,
+		      u32 offset, u32 flags);
+#define GUC_MMIO_REG_ADD(regset, reg, masked) \
+	guc_mmio_reg_add(regset, \
+			 i915_mmio_reg_offset((reg)), \
+			 (masked) ? GUC_REGSET_MASKED : 0)
+
 int intel_guc_ads_create(struct intel_guc *guc);
 void intel_guc_ads_destroy(struct intel_guc *guc);
 void intel_guc_ads_init_late(struct intel_guc *guc);
-- 
2.26.2

Re: [Intel-gfx] [PATCH V3 2/8] drm/i915/gt: Add support of mocs auxiliary registers programming

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 2184 bytes --]

Hi Ayaz,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20210830]
[cannot apply to v5.14]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Ayaz-A-Siddiqui/drm-i915-gt-Initialize-unused-MOCS-entries-to-L3_WB/20210831-002827
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a014-20210830 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
        # https://github.com/0day-ci/linux/commit/449e390824ff0b89a08669d97f456bec3c0f8f74
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Ayaz-A-Siddiqui/drm-i915-gt-Initialize-unused-MOCS-entries-to-L3_WB/20210831-002827
        git checkout 449e390824ff0b89a08669d97f456bec3c0f8f74
        # save the attached .config to linux build tree
        make W=1 ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/gt/intel_mocs.c:496:5: warning: no previous prototype for 'get_ctx_reg_count' [-Wmissing-prototypes]
     496 | int get_ctx_reg_count(const struct drm_i915_aux_table *aux)
         |     ^~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/gt/intel_mocs.c:364:1: warning: 'add_aux_reg' defined but not used [-Wunused-function]
     364 | add_aux_reg(struct drm_i915_aux_table *aux,
         | ^~~~~~~~~~~


vim +/get_ctx_reg_count +496 drivers/gpu/drm/i915/gt/intel_mocs.c

   495	
 > 496	int get_ctx_reg_count(const struct drm_i915_aux_table *aux)
   497	{
   498		int count = 0;
   499	
   500		while (aux) {
   501			if (aux->type == REG_ENGINE_CONTEXT)
   502				count++;
   503			aux = aux->next;
   504		}
   505		return count;
   506	}
   507	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 42892 bytes --]

Re: [Intel-gfx] [PATCH V3 2/8] drm/i915/gt: Add support of mocs auxiliary registers programming

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 2241 bytes --]

Hi Ayaz,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20210830]
[cannot apply to v5.14]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Ayaz-A-Siddiqui/drm-i915-gt-Initialize-unused-MOCS-entries-to-L3_WB/20210831-002827
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a014-20210830 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
        # https://github.com/0day-ci/linux/commit/449e390824ff0b89a08669d97f456bec3c0f8f74
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Ayaz-A-Siddiqui/drm-i915-gt-Initialize-unused-MOCS-entries-to-L3_WB/20210831-002827
        git checkout 449e390824ff0b89a08669d97f456bec3c0f8f74
        # save the attached .config to linux build tree
        make W=1 ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/gt/intel_mocs.c:496:5: warning: no previous prototype for 'get_ctx_reg_count' [-Wmissing-prototypes]
     496 | int get_ctx_reg_count(const struct drm_i915_aux_table *aux)
         |     ^~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/gt/intel_mocs.c:364:1: warning: 'add_aux_reg' defined but not used [-Wunused-function]
     364 | add_aux_reg(struct drm_i915_aux_table *aux,
         | ^~~~~~~~~~~


vim +/get_ctx_reg_count +496 drivers/gpu/drm/i915/gt/intel_mocs.c

   495	
 > 496	int get_ctx_reg_count(const struct drm_i915_aux_table *aux)
   497	{
   498		int count = 0;
   499	
   500		while (aux) {
   501			if (aux->type == REG_ENGINE_CONTEXT)
   502				count++;
   503			aux = aux->next;
   504		}
   505		return count;
   506	}
   507	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 42892 bytes --]

Re: [Intel-gfx] [PATCH V3 2/8] drm/i915/gt: Add support of mocs auxiliary registers programming

[-- Attachment #1: Type: text/plain, Size: 2641 bytes --]

Hi Ayaz,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20210830]
[cannot apply to v5.14]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Ayaz-A-Siddiqui/drm-i915-gt-Initialize-unused-MOCS-entries-to-L3_WB/20210831-002827
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a004-20210830 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 4b1fde8a2b681dad2ce0c082a5d6422caa06b0bc)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/449e390824ff0b89a08669d97f456bec3c0f8f74
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Ayaz-A-Siddiqui/drm-i915-gt-Initialize-unused-MOCS-entries-to-L3_WB/20210831-002827
        git checkout 449e390824ff0b89a08669d97f456bec3c0f8f74
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/gt/intel_mocs.c:496:5: warning: no previous prototype for function 'get_ctx_reg_count' [-Wmissing-prototypes]
   int get_ctx_reg_count(const struct drm_i915_aux_table *aux)
       ^
   drivers/gpu/drm/i915/gt/intel_mocs.c:496:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
   int get_ctx_reg_count(const struct drm_i915_aux_table *aux)
   ^
   static 
   drivers/gpu/drm/i915/gt/intel_mocs.c:364:1: warning: unused function 'add_aux_reg' [-Wunused-function]
   add_aux_reg(struct drm_i915_aux_table *aux,
   ^
   2 warnings generated.


vim +/get_ctx_reg_count +496 drivers/gpu/drm/i915/gt/intel_mocs.c

   495	
 > 496	int get_ctx_reg_count(const struct drm_i915_aux_table *aux)
   497	{
   498		int count = 0;
   499	
   500		while (aux) {
   501			if (aux->type == REG_ENGINE_CONTEXT)
   502				count++;
   503			aux = aux->next;
   504		}
   505		return count;
   506	}
   507	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 34241 bytes --]

Re: [Intel-gfx] [PATCH V3 2/8] drm/i915/gt: Add support of mocs auxiliary registers programming

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 2705 bytes --]

Hi Ayaz,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20210830]
[cannot apply to v5.14]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Ayaz-A-Siddiqui/drm-i915-gt-Initialize-unused-MOCS-entries-to-L3_WB/20210831-002827
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-a004-20210830 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 4b1fde8a2b681dad2ce0c082a5d6422caa06b0bc)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/449e390824ff0b89a08669d97f456bec3c0f8f74
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Ayaz-A-Siddiqui/drm-i915-gt-Initialize-unused-MOCS-entries-to-L3_WB/20210831-002827
        git checkout 449e390824ff0b89a08669d97f456bec3c0f8f74
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/gt/intel_mocs.c:496:5: warning: no previous prototype for function 'get_ctx_reg_count' [-Wmissing-prototypes]
   int get_ctx_reg_count(const struct drm_i915_aux_table *aux)
       ^
   drivers/gpu/drm/i915/gt/intel_mocs.c:496:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
   int get_ctx_reg_count(const struct drm_i915_aux_table *aux)
   ^
   static 
   drivers/gpu/drm/i915/gt/intel_mocs.c:364:1: warning: unused function 'add_aux_reg' [-Wunused-function]
   add_aux_reg(struct drm_i915_aux_table *aux,
   ^
   2 warnings generated.


vim +/get_ctx_reg_count +496 drivers/gpu/drm/i915/gt/intel_mocs.c

   495	
 > 496	int get_ctx_reg_count(const struct drm_i915_aux_table *aux)
   497	{
   498		int count = 0;
   499	
   500		while (aux) {
   501			if (aux->type == REG_ENGINE_CONTEXT)
   502				count++;
   503			aux = aux->next;
   504		}
   505		return count;
   506	}
   507	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 34241 bytes --]

Re: [Intel-gfx] [PATCH V3 2/8] drm/i915/gt: Add support of mocs auxiliary registers programming

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 2223 bytes --]

Hi Ayaz,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip next-20210830]
[cannot apply to v5.14]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Ayaz-A-Siddiqui/drm-i915-gt-Initialize-unused-MOCS-entries-to-L3_WB/20210831-002827
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-a016-20210830 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
        # https://github.com/0day-ci/linux/commit/449e390824ff0b89a08669d97f456bec3c0f8f74
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Ayaz-A-Siddiqui/drm-i915-gt-Initialize-unused-MOCS-entries-to-L3_WB/20210831-002827
        git checkout 449e390824ff0b89a08669d97f456bec3c0f8f74
        # save the attached .config to linux build tree
        make W=1 ARCH=i386 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> drivers/gpu/drm/i915/gt/intel_mocs.c:496:5: error: no previous prototype for 'get_ctx_reg_count' [-Werror=missing-prototypes]
     496 | int get_ctx_reg_count(const struct drm_i915_aux_table *aux)
         |     ^~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/gt/intel_mocs.c:364:1: error: 'add_aux_reg' defined but not used [-Werror=unused-function]
     364 | add_aux_reg(struct drm_i915_aux_table *aux,
         | ^~~~~~~~~~~
   cc1: all warnings being treated as errors


vim +/get_ctx_reg_count +496 drivers/gpu/drm/i915/gt/intel_mocs.c

   495	
 > 496	int get_ctx_reg_count(const struct drm_i915_aux_table *aux)
   497	{
   498		int count = 0;
   499	
   500		while (aux) {
   501			if (aux->type == REG_ENGINE_CONTEXT)
   502				count++;
   503			aux = aux->next;
   504		}
   505		return count;
   506	}
   507	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 39847 bytes --]

Re: [Intel-gfx] [PATCH V3 2/8] drm/i915/gt: Add support of mocs auxiliary registers programming

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 2281 bytes --]

Hi Ayaz,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip next-20210830]
[cannot apply to v5.14]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Ayaz-A-Siddiqui/drm-i915-gt-Initialize-unused-MOCS-entries-to-L3_WB/20210831-002827
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-a016-20210830 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
        # https://github.com/0day-ci/linux/commit/449e390824ff0b89a08669d97f456bec3c0f8f74
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Ayaz-A-Siddiqui/drm-i915-gt-Initialize-unused-MOCS-entries-to-L3_WB/20210831-002827
        git checkout 449e390824ff0b89a08669d97f456bec3c0f8f74
        # save the attached .config to linux build tree
        make W=1 ARCH=i386 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> drivers/gpu/drm/i915/gt/intel_mocs.c:496:5: error: no previous prototype for 'get_ctx_reg_count' [-Werror=missing-prototypes]
     496 | int get_ctx_reg_count(const struct drm_i915_aux_table *aux)
         |     ^~~~~~~~~~~~~~~~~
   drivers/gpu/drm/i915/gt/intel_mocs.c:364:1: error: 'add_aux_reg' defined but not used [-Werror=unused-function]
     364 | add_aux_reg(struct drm_i915_aux_table *aux,
         | ^~~~~~~~~~~
   cc1: all warnings being treated as errors


vim +/get_ctx_reg_count +496 drivers/gpu/drm/i915/gt/intel_mocs.c

   495	
 > 496	int get_ctx_reg_count(const struct drm_i915_aux_table *aux)
   497	{
   498		int count = 0;
   499	
   500		while (aux) {
   501			if (aux->type == REG_ENGINE_CONTEXT)
   502				count++;
   503			aux = aux->next;
   504		}
   505		return count;
   506	}
   507	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 39847 bytes --]

Re: [Intel-gfx] [PATCH V3 2/8] drm/i915/gt: Add support of mocs auxiliary registers programming

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 1762 bytes --]

Hi Ayaz,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20210830]
[cannot apply to v5.14]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Ayaz-A-Siddiqui/drm-i915-gt-Initialize-unused-MOCS-entries-to-L3_WB/20210831-002827
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-s001-20210830 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce:
        # apt-get install sparse
        # sparse version: v0.6.3-348-gf0e6938b-dirty
        # https://github.com/0day-ci/linux/commit/449e390824ff0b89a08669d97f456bec3c0f8f74
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Ayaz-A-Siddiqui/drm-i915-gt-Initialize-unused-MOCS-entries-to-L3_WB/20210831-002827
        git checkout 449e390824ff0b89a08669d97f456bec3c0f8f74
        # save the attached .config to linux build tree
        make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>


sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/i915/gt/intel_mocs.c:496:5: sparse: sparse: symbol 'get_ctx_reg_count' was not declared. Should it be static?

Please review and possibly fold the followup patch.

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 36426 bytes --]

Re: [Intel-gfx] [PATCH V3 2/8] drm/i915/gt: Add support of mocs auxiliary registers programming

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 1801 bytes --]

Hi Ayaz,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20210830]
[cannot apply to v5.14]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Ayaz-A-Siddiqui/drm-i915-gt-Initialize-unused-MOCS-entries-to-L3_WB/20210831-002827
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-s001-20210830 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce:
        # apt-get install sparse
        # sparse version: v0.6.3-348-gf0e6938b-dirty
        # https://github.com/0day-ci/linux/commit/449e390824ff0b89a08669d97f456bec3c0f8f74
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Ayaz-A-Siddiqui/drm-i915-gt-Initialize-unused-MOCS-entries-to-L3_WB/20210831-002827
        git checkout 449e390824ff0b89a08669d97f456bec3c0f8f74
        # save the attached .config to linux build tree
        make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>


sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/i915/gt/intel_mocs.c:496:5: sparse: sparse: symbol 'get_ctx_reg_count' was not declared. Should it be static?

Please review and possibly fold the followup patch.

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 36426 bytes --]

[Intel-gfx] [RFC PATCH] drm/i915/gt: get_ctx_reg_count() can be static

[kernel test robot]

drivers/gpu/drm/i915/gt/intel_mocs.c:496:5: warning: symbol 'get_ctx_reg_count' was not declared. Should it be static?

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: kernel test robot <lkp@intel.com>
---
 intel_mocs.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index c52640523c218..728d0340cc622 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -493,7 +493,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
 	return flags;
 }
 
-int get_ctx_reg_count(const struct drm_i915_aux_table *aux)
+static int get_ctx_reg_count(const struct drm_i915_aux_table *aux)
 {
 	int count = 0;
 

[RFC PATCH] drm/i915/gt: get_ctx_reg_count() can be static

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 795 bytes --]

drivers/gpu/drm/i915/gt/intel_mocs.c:496:5: warning: symbol 'get_ctx_reg_count' was not declared. Should it be static?

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: kernel test robot <lkp@intel.com>
---
 intel_mocs.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index c52640523c218..728d0340cc622 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -493,7 +493,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
 	return flags;
 }
 
-int get_ctx_reg_count(const struct drm_i915_aux_table *aux)
+static int get_ctx_reg_count(const struct drm_i915_aux_table *aux)
 {
 	int count = 0;
 

Re: [Intel-gfx] [PATCH V3 2/8] drm/i915/gt: Add support of mocs auxiliary registers programming

[kernel test robot]

Hi Ayaz,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20210901]
[cannot apply to v5.14]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Ayaz-A-Siddiqui/drm-i915-gt-Initialize-unused-MOCS-entries-to-L3_WB/20210831-002827
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>


includecheck warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/i915/gt/intel_gt.c: intel_mocs.h is included more than once.

Please review and possibly fold the followup patch.

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

Re: [Intel-gfx] [PATCH V3 2/8] drm/i915/gt: Add support of mocs auxiliary registers programming

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 1061 bytes --]

Hi Ayaz,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20210901]
[cannot apply to v5.14]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Ayaz-A-Siddiqui/drm-i915-gt-Initialize-unused-MOCS-entries-to-L3_WB/20210831-002827
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>


includecheck warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/i915/gt/intel_gt.c: intel_mocs.h is included more than once.

Please review and possibly fold the followup patch.

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

[Intel-gfx] [RFC PATCH] drm/i915/gt: fix duplicated inclusion

[kernel test robot]

Generated by: scripts/checkincludes.pl

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: kernel test robot <lkp@intel.com>
---
 intel_gt.c |    1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index ccb257d5282f4..4643fbf753455 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -14,7 +14,6 @@
 #include "intel_gt_pm.h"
 #include "intel_gt_requests.h"
 #include "intel_migrate.h"
-#include "intel_mocs.h"
 #include "intel_rc6.h"
 #include "intel_renderstate.h"
 #include "intel_rps.h"

[RFC PATCH] drm/i915/gt: fix duplicated inclusion

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 629 bytes --]

Generated by: scripts/checkincludes.pl

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: kernel test robot <lkp@intel.com>
---
 intel_gt.c |    1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index ccb257d5282f4..4643fbf753455 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -14,7 +14,6 @@
 #include "intel_gt_pm.h"
 #include "intel_gt_requests.h"
 #include "intel_migrate.h"
-#include "intel_mocs.h"
 #include "intel_rc6.h"
 #include "intel_renderstate.h"
 #include "intel_rps.h"

Re: [Intel-gfx] [PATCH V3 2/8] drm/i915/gt: Add support of mocs auxiliary registers programming

[Matt Roper]

On Mon, Aug 30, 2021 at 09:52:34PM +0530, Ayaz A Siddiqui wrote:
> From: Srinivasan Shanmugam <srinivasan.s@intel.com>
> 
> Few registers need to be programmed with
> appropriate MOCS indexes for proper functioning.
> As of now, there are two categories of registers that
> need to be programmed, these are engine power domains
> register and engine state context register.

Minor nitpick:  MOCS-related registers are the initial user of this
framework, but isn't the longer-term goal to move other types of
registers over to this as well (e.g., some of the "fake" workarounds we
have today for uapi compatibility)?  I'd avoid mentioning MOCS
specifically in this patch since this is just a general
register-initializing framework.

> 
> A framework is being added to handle programming and
> verification of those registers.
> 
> To add a register in the future we just need to add it
> in build_aux_regs(), the rest will be taken care of by
> the framework.
> 
> V2: (Ayaz)
>  Added CMD_CCTL in guc_mmio_regset_init(), so that this
>  register can restored after engine reset.
> 
> V3: (Ayaz)
>  1. Changed implementation to have a framework only.
>  2. Added register type for proper application.
>  3. Removed CMD_CCTL programming.
> 
> Cc: Chris Wilson <chris.p.wilson@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Srinivasan Shanmugam <srinivasan.s@intel.com>
> Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt.c         |   5 +
>  drivers/gpu/drm/i915/gt/intel_mocs.c       | 184 +++++++++++++++++++++
>  drivers/gpu/drm/i915/gt/intel_mocs.h       |   5 +
>  drivers/gpu/drm/i915/gt/selftest_mocs.c    |  49 ++++++
>  drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c |  17 +-
>  drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h |  15 ++
>  6 files changed, 263 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 62d40c9866427..ccb257d5282f4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -21,6 +21,7 @@
>  #include "intel_uncore.h"
>  #include "intel_pm.h"
>  #include "shmem_utils.h"
> +#include "intel_mocs.h"
>  
>  void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
>  {
> @@ -530,6 +531,10 @@ static int __engines_record_defaults(struct intel_gt *gt)
>  		if (err)
>  			goto err_rq;
>  
> +		err  = apply_mocs_aux_regs_ctx(rq);
> +		if (err)
> +			goto err_rq;
> +
>  		err = intel_renderstate_emit(&so, rq);
>  		if (err)
>  			goto err_rq;
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 10cc508c1a4f6..c52640523c218 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c

The main framework here probably shouldn't be in intel_mocs if we want
to make this generic and usable for multiple purposes.  It would be best
to have most of this infrastructure in its own file.  Then other parts
of the code (e.g., mocs) can call the new functions here to add their
own sets of registers to the aux table.

> @@ -10,6 +10,8 @@
>  #include "intel_lrc_reg.h"
>  #include "intel_mocs.h"
>  #include "intel_ring.h"
> +#include "intel_gpu_commands.h"
> +#include "uc/intel_guc_ads.h"
>  
>  /* structures required */
>  struct drm_i915_mocs_entry {
> @@ -25,6 +27,28 @@ struct drm_i915_mocs_table {
>  	u8 uc_index;
>  };
>  
> +enum register_type {
> +	/*
> +	 * REG_GT: General register - Need to  be re-plied after GT/GPU reset
> +	 * REG_ENGINE: Domain register - needs to be re-applied after
> +	 *	       engine reset
> +	 * REG_ENGINE_CONTEXT: Engine state context register - need to stored
> +	 *		       as part of Golden context.
> +	 */
> +	REG_GT = 0,
> +	REG_ENGINE,
> +	REG_ENGINE_CONTEXT
> +};
> +
> +struct drm_i915_aux_table {
> +	enum register_type type;
> +	const char *name;
> +	i915_reg_t offset;
> +	u32 value;
> +	u32 readmask;
> +	struct drm_i915_aux_table *next;
> +};
> +
>  /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
>  #define _LE_CACHEABILITY(value)	((value) << 0)
>  #define _LE_TGT_CACHE(value)	((value) << 2)
> @@ -336,6 +360,78 @@ static bool has_mocs(const struct drm_i915_private *i915)
>  	return !IS_DGFX(i915);
>  }
>  
> +static struct drm_i915_aux_table *
> +add_aux_reg(struct drm_i915_aux_table *aux,
> +	    enum register_type type,
> +	    const char *name,
> +	    i915_reg_t offset,
> +	    u32 value,
> +	    u32 read)
> +{
> +	struct drm_i915_aux_table *x;
> +
> +	x = kmalloc(sizeof(*x), GFP_ATOMIC);
> +	if (!x) {
> +		DRM_ERROR("Failed to allocate aux reg '%s'\n", name);
> +		return aux;
> +	}
> +
> +	x->type = type;
> +	x->name = name;
> +	x->offset = offset;
> +	x->value = value;
> +	x->readmask = read;
> +
> +	x->next = aux;
> +	return x;
> +}
> +
> +static const struct drm_i915_aux_table *
> +build_aux_regs(const struct intel_engine_cs *engine,
> +	       const struct drm_i915_mocs_table *mocs)

It seems like the design you have here at the moment is going to
allocate and fill a new AUX list any time the code needs the list of
registers, and then frees it immediately afterward.  That seems a bit
inefficient to do multiple times at runtime (e.g., in execlist mode
every engine reset would trigger an additional allocation/build/free).

Can we just build the list once at initialization time (with different
parts of the code adding their own sets of registers to the table) and
then free it later when the GT is destroyed?  That's sort of the
approach that our workaround code takes --- decide which registers are
important to deal with a single time during device init, then use that
pre-built list whenever necessary during runtime, and finally free it at
GT teardown.

Also, the function that adds the MOCS-specific registers to the table
can be kept here in intel_mocs.c, but should probably be added in the
next patch that deals with MOCS-specific registers.  This patch should
focus the interfaces to add new registers to the table, and the
application of the table's registers at different parts of the code.


> +{
> +	struct drm_i915_aux_table *aux = NULL;
> +
> +	if (GRAPHICS_VER(engine->i915) >= 12 &&
> +	    !drm_WARN_ONCE(&engine->i915->drm, !mocs->uc_index,
> +	    "Platform that should have UC index defined and does not\n")) {
> +		/*
> +		 * Add Auxiliary register which needs to be programmed with
> +		 * UC MOCS index. We need to call add_aux_reg() to add
> +		 * a entry in drm_i915_aux_table link list.
> +		 */
> +	}
> +	return aux;
> +}
> +
> +static void
> +free_aux_regs(const struct drm_i915_aux_table *aux)
> +{
> +	while (aux) {
> +		struct drm_i915_aux_table *next = aux->next;
> +
> +		kfree(aux);
> +		aux = next;
> +	}
> +}
> +
> +static void apply_aux_regs_engine(struct intel_engine_cs *engine,
> +				  const struct drm_i915_aux_table *aux)
> +{
> +	u32 mmio_reg_offset;
> +
> +	while (aux) {
> +		if (aux->type == REG_ENGINE) {
> +			mmio_reg_offset = i915_mmio_reg_offset(aux->offset);
> +			intel_uncore_write_fw(engine->uncore,
> +					      _MMIO(engine->mmio_base +
> +					      mmio_reg_offset),
> +					      aux->value);
> +		}
> +		aux = aux->next;
> +	}
> +}
> +
>  static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
>  				      struct drm_i915_mocs_table *table)
>  {
> @@ -347,10 +443,12 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
>  		table->size = ARRAY_SIZE(dg1_mocs_table);
>  		table->table = dg1_mocs_table;
>  		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> +		table->uc_index = 1;
>  	} else if (GRAPHICS_VER(i915) >= 12) {
>  		table->size  = ARRAY_SIZE(tgl_mocs_table);
>  		table->table = tgl_mocs_table;
>  		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> +		table->uc_index = 3;
>  	} else if (GRAPHICS_VER(i915) == 11) {
>  		table->size  = ARRAY_SIZE(icl_mocs_table);
>  		table->table = icl_mocs_table;
> @@ -395,6 +493,87 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
>  	return flags;
>  }
>  
> +int get_ctx_reg_count(const struct drm_i915_aux_table *aux)

Should this be static?

If we keep the aux table around during runtime, we could probably just
tally up the count as registers are getting added during init, so that
we don't need to re-walk the list to count them later.

> +{
> +	int count = 0;
> +
> +	while (aux) {
> +		if (aux->type == REG_ENGINE_CONTEXT)
> +			count++;
> +		aux = aux->next;
> +	}
> +	return count;
> +}
> +
> +void add_aux_mocs_guc_mmio_regset(struct temp_regset *regset,
> +				  struct intel_engine_cs *engine)

If we're making this framework general, we should probably remove 'mocs'
from the name since it will eventually have other non-mocs registers
included too once we start using it for other things.


> +{
> +	const struct drm_i915_aux_table *aux;
> +	struct drm_i915_mocs_table table;
> +	int ret;
> +
> +	ret = get_mocs_settings(engine->i915, &table);
> +	if (!ret)
> +		return;
> +
> +	aux = build_aux_regs(engine, &table);
> +	if (!aux)
> +		return;
> +
> +	while (aux) {
> +		if (aux->type == REG_ENGINE)
> +			GUC_MMIO_REG_ADD(regset,
> +					 _MMIO(engine->mmio_base
> +					 + i915_mmio_reg_offset(aux->offset)),
> +					 true);
> +		aux = aux->next;
> +	}
> +	free_aux_regs(aux);
> +}
> +
> +int apply_mocs_aux_regs_ctx(struct i915_request *rq)
> +{
> +	const struct drm_i915_aux_table *aux;
> +	struct drm_i915_mocs_table table;
> +	u32 *cs;
> +	int ret, count;
> +
> +	ret = get_mocs_settings(rq->engine->i915, &table);
> +	if (!ret)
> +		return 0;
> +
> +	aux = build_aux_regs(rq->engine, &table);
> +
> +	count = get_ctx_reg_count(aux);
> +	if (!count)
> +		return 0;

With the current init/build/free design, aren't you leaking the table
here?  There might be zero context registers, but there still could have
been some non-context registers on the list we got back.

> +	ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
> +	if (ret)
> +		return ret;
> +
> +	cs = intel_ring_begin(rq, (count * 2 + 2));
> +	if (IS_ERR(cs))
> +		return PTR_ERR(cs);
> +
> +	*cs++ = MI_LOAD_REGISTER_IMM(count);
> +	while (aux) {
> +		if (aux->type == REG_ENGINE_CONTEXT) {
> +			*cs++ = i915_mmio_reg_offset(aux->offset);
> +			*cs++ = aux->value;
> +		}
> +		aux = aux->next;
> +	}
> +	*cs++ = MI_NOOP;
> +
> +	intel_ring_advance(rq, cs);
> +	free_aux_regs(aux);
> +	ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
>  /*
>   * Get control_value from MOCS entry taking into account when it's not used:
>   * I915_MOCS_PTE's value is returned in this case.
> @@ -484,6 +663,7 @@ static void init_l3cc_table(struct intel_engine_cs *engine,
>  
>  void intel_mocs_init_engine(struct intel_engine_cs *engine)
>  {
> +	const struct drm_i915_aux_table *aux;
>  	struct drm_i915_mocs_table table;
>  	unsigned int flags;
>  
> @@ -500,6 +680,10 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
>  
>  	if (flags & HAS_RENDER_L3CC && engine->class == RENDER_CLASS)
>  		init_l3cc_table(engine, &table);
> +
> +	aux = build_aux_regs(engine, &table);
> +	apply_aux_regs_engine(engine, aux);
> +	free_aux_regs(aux);
>  }
>  
>  static u32 global_mocs_offset(void)
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h b/drivers/gpu/drm/i915/gt/intel_mocs.h
> index d83274f5163bd..0f362a0acc3a3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
> @@ -33,8 +33,13 @@
>  
>  struct intel_engine_cs;
>  struct intel_gt;
> +struct i915_request;
> +struct temp_regset;
>  
>  void intel_mocs_init(struct intel_gt *gt);
>  void intel_mocs_init_engine(struct intel_engine_cs *engine);
> +int apply_mocs_aux_regs_ctx(struct i915_request *rq);
> +void add_aux_mocs_guc_mmio_regset(struct temp_regset *regset,
> +				  struct intel_engine_cs *engine);
>  
>  #endif
> diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> index 13d25bf2a94aa..2b0207dfbf21c 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c

If we still want to have selftests that operate on specific subsets of
the aux table after we make it more generic, we could potentially add a
'aux source' field to 'struct drm_i915_aux_table' that represents what
part of the code added the register (MOCS, uapi compat, etc.).  Then we
can easily ignore the registers on the table that aren't relevant to the
specific selftest.

> @@ -155,6 +155,47 @@ static int read_l3cc_table(struct i915_request *rq,
>  	return read_regs(rq, addr, (table->n_entries + 1) / 2, offset);
>  }
>  
> +static int read_aux_regs(struct i915_request *rq,
> +			 const struct drm_i915_aux_table *r,
> +			 u32 *offset)
> +{
> +	int err;
> +
> +	while (r) {
> +		err = read_regs(rq,
> +				rq->engine->mmio_base + i915_mmio_reg_offset(r->offset), 1,
> +				offset);
> +		if (err)
> +			return err;
> +
> +		r = r->next;
> +	}
> +
> +	return 0;
> +}
> +
> +static int check_aux_regs(struct intel_engine_cs *engine,
> +			  const struct drm_i915_aux_table *r,
> +			  u32 **vaddr)

One other concern (which is part of why I didn't really want to see this
framework handled separately from workarounds) is that the aux table
might tell us to program a register with a specific value, but we may
also have a hardware workaround for a platform/stepping that overrides
that with an alternate value.  Our workaround framework is smart enough
to combine multiple entries for the same register into a single
operation (if the set of bits being updated are different), or will warn
if there's two conflicting sets of programming requested for certain
bits.  Right now it's not clear who wins if the aux table wants to
program a register to value 'X' but the workaround lists want to program
the same register to value 'Y.'  In theory the workaround should
overrule the regular programming, but at the moment these selftests
aren't checking to see if that's the case.  We may not have any such
conflicts today (especially since we have so few registers that are
going to be on the aux table initially), but it may come up eventually.


Matt

> +{
> +	while (r) {
> +		u32 expect = r->value & r->readmask;
> +		u32 masked_value = **vaddr & r->readmask;
> +
> +		if (masked_value != expect) {
> +			pr_err("%s: Invalid entry %s[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x\n",
> +			       engine->name, r->name,
> +			       i915_mmio_reg_offset(r->offset), **vaddr,
> +			       masked_value, expect);
> +			return -EINVAL;
> +		}
> +		++*vaddr;
> +		r = r->next;
> +	}
> +
> +	return 0;
> +}
> +
>  static int check_mocs_table(struct intel_engine_cs *engine,
>  			    const struct drm_i915_mocs_table *table,
>  			    u32 **vaddr)
> @@ -216,6 +257,7 @@ static int check_mocs_engine(struct live_mocs *arg,
>  			     struct intel_context *ce)
>  {
>  	struct i915_vma *vma = arg->scratch;
> +	const struct drm_i915_aux_table *aux;
>  	struct i915_request *rq;
>  	u32 offset;
>  	u32 *vaddr;
> @@ -223,6 +265,8 @@ static int check_mocs_engine(struct live_mocs *arg,
>  
>  	memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE / sizeof(u32));
>  
> +	aux = build_aux_regs(ce->engine, &arg->table);
> +
>  	rq = intel_context_create_request(ce);
>  	if (IS_ERR(rq))
>  		return PTR_ERR(rq);
> @@ -239,6 +283,8 @@ static int check_mocs_engine(struct live_mocs *arg,
>  		err = read_mocs_table(rq, arg->mocs, &offset);
>  	if (!err && ce->engine->class == RENDER_CLASS)
>  		err = read_l3cc_table(rq, arg->l3cc, &offset);
> +	if (!err)
> +		err = read_aux_regs(rq, aux, &offset);
>  	offset -= i915_ggtt_offset(vma);
>  	GEM_BUG_ON(offset > PAGE_SIZE);
>  
> @@ -252,10 +298,13 @@ static int check_mocs_engine(struct live_mocs *arg,
>  		err = check_mocs_table(ce->engine, arg->mocs, &vaddr);
>  	if (!err && ce->engine->class == RENDER_CLASS)
>  		err = check_l3cc_table(ce->engine, arg->l3cc, &vaddr);
> +	if (!err)
> +		err = check_aux_regs(ce->engine, aux, &vaddr);
>  	if (err)
>  		return err;
>  
>  	GEM_BUG_ON(arg->vaddr + offset != vaddr);
> +	free_aux_regs(aux);
>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index 6926919bcac6b..be4cca49abced 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -12,6 +12,7 @@
>  #include "intel_guc_fwif.h"
>  #include "intel_uc.h"
>  #include "i915_drv.h"
> +#include "gt/intel_mocs.h"
>  
>  /*
>   * The Additional Data Struct (ADS) has pointers for different buffers used by
> @@ -187,11 +188,6 @@ static void guc_mapping_table_init(struct intel_gt *gt,
>   * inside the ADS.
>   */
>  #define MAX_MMIO_REGS	128	/* Arbitrary size, increase as needed */
> -struct temp_regset {
> -	struct guc_mmio_reg *registers;
> -	u32 used;
> -	u32 size;
> -};
>  
>  static int guc_mmio_reg_cmp(const void *a, const void *b)
>  {
> @@ -201,8 +197,8 @@ static int guc_mmio_reg_cmp(const void *a, const void *b)
>  	return (int)ra->offset - (int)rb->offset;
>  }
>  
> -static void guc_mmio_reg_add(struct temp_regset *regset,
> -			     u32 offset, u32 flags)
> +void guc_mmio_reg_add(struct temp_regset *regset,
> +		      u32 offset, u32 flags)
>  {
>  	u32 count = regset->used;
>  	struct guc_mmio_reg reg = {
> @@ -236,11 +232,6 @@ static void guc_mmio_reg_add(struct temp_regset *regset,
>  	}
>  }
>  
> -#define GUC_MMIO_REG_ADD(regset, reg, masked) \
> -	guc_mmio_reg_add(regset, \
> -			 i915_mmio_reg_offset((reg)), \
> -			 (masked) ? GUC_REGSET_MASKED : 0)
> -
>  static void guc_mmio_regset_init(struct temp_regset *regset,
>  				 struct intel_engine_cs *engine)
>  {
> @@ -258,6 +249,8 @@ static void guc_mmio_regset_init(struct temp_regset *regset,
>  	for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
>  		GUC_MMIO_REG_ADD(regset, wa->reg, wa->masked_reg);
>  
> +	add_aux_mocs_guc_mmio_regset(regset, engine);
> +
>  	/* Be extra paranoid and include all whitelist registers. */
>  	for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++)
>  		GUC_MMIO_REG_ADD(regset,
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
> index 3d85051d57e45..75736c56fa187 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
> @@ -6,9 +6,24 @@
>  #ifndef _INTEL_GUC_ADS_H_
>  #define _INTEL_GUC_ADS_H_
>  
> +#include <linux/types.h>
> +
> +struct temp_regset {
> +	struct guc_mmio_reg *registers;
> +	u32 used;
> +	u32 size;
> +};
> +
>  struct intel_guc;
>  struct drm_printer;
>  
> +void guc_mmio_reg_add(struct temp_regset *regset,
> +		      u32 offset, u32 flags);
> +#define GUC_MMIO_REG_ADD(regset, reg, masked) \
> +	guc_mmio_reg_add(regset, \
> +			 i915_mmio_reg_offset((reg)), \
> +			 (masked) ? GUC_REGSET_MASKED : 0)
> +
>  int intel_guc_ads_create(struct intel_guc *guc);
>  void intel_guc_ads_destroy(struct intel_guc *guc);
>  void intel_guc_ads_init_late(struct intel_guc *guc);
> -- 
> 2.26.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

Re: [Intel-gfx] [PATCH V3 2/8] drm/i915/gt: Add support of mocs auxiliary registers programming

[Siddiqui, Ayaz A]

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Thursday, September 2, 2021 2:55 AM
> To: Siddiqui, Ayaz A <ayaz.siddiqui@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; S, Srinivasan <srinivasan.s@intel.com>;
> Wilson, Chris P <chris.p.wilson@intel.com>
> Subject: Re: [PATCH V3 2/8] drm/i915/gt: Add support of mocs auxiliary
> registers programming
> 
> On Mon, Aug 30, 2021 at 09:52:34PM +0530, Ayaz A Siddiqui wrote:
> > From: Srinivasan Shanmugam <srinivasan.s@intel.com>
> >
> > Few registers need to be programmed with appropriate MOCS indexes for
> > proper functioning.
> > As of now, there are two categories of registers that need to be
> > programmed, these are engine power domains register and engine state
> > context register.
> 
> Minor nitpick:  MOCS-related registers are the initial user of this framework,
> but isn't the longer-term goal to move other types of registers over to this as
> well (e.g., some of the "fake" workarounds we have today for uapi
> compatibility)?  I'd avoid mentioning MOCS specifically in this patch since this
> is just a general register-initializing framework.
Sure we should remove MOCS from here.
> 
> >
> > A framework is being added to handle programming and verification of
> > those registers.
> >
> > To add a register in the future we just need to add it in
> > build_aux_regs(), the rest will be taken care of by the framework.
> >
> > V2: (Ayaz)
> >  Added CMD_CCTL in guc_mmio_regset_init(), so that this  register can
> > restored after engine reset.
> >
> > V3: (Ayaz)
> >  1. Changed implementation to have a framework only.
> >  2. Added register type for proper application.
> >  3. Removed CMD_CCTL programming.
> >
> > Cc: Chris Wilson <chris.p.wilson@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Srinivasan Shanmugam <srinivasan.s@intel.com>
> > Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_gt.c         |   5 +
> >  drivers/gpu/drm/i915/gt/intel_mocs.c       | 184 +++++++++++++++++++++
> >  drivers/gpu/drm/i915/gt/intel_mocs.h       |   5 +
> >  drivers/gpu/drm/i915/gt/selftest_mocs.c    |  49 ++++++
> >  drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c |  17 +-
> > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h |  15 ++
> >  6 files changed, 263 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> > b/drivers/gpu/drm/i915/gt/intel_gt.c
> > index 62d40c9866427..ccb257d5282f4 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > @@ -21,6 +21,7 @@
> >  #include "intel_uncore.h"
> >  #include "intel_pm.h"
> >  #include "shmem_utils.h"
> > +#include "intel_mocs.h"
> >
> >  void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private
> > *i915)  { @@ -530,6 +531,10 @@ static int
> > __engines_record_defaults(struct intel_gt *gt)
> >  		if (err)
> >  			goto err_rq;
> >
> > +		err  = apply_mocs_aux_regs_ctx(rq);
> > +		if (err)
> > +			goto err_rq;
> > +
> >  		err = intel_renderstate_emit(&so, rq);
> >  		if (err)
> >  			goto err_rq;
> > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
> > b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > index 10cc508c1a4f6..c52640523c218 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> 
> The main framework here probably shouldn't be in intel_mocs if we want to
> make this generic and usable for multiple purposes.  It would be best to have
> most of this infrastructure in its own file.  Then other parts of the code (e.g.,
> mocs) can call the new functions here to add their own sets of registers to
> the aux table.
Yes make sense.
 
> > @@ -10,6 +10,8 @@
> >  #include "intel_lrc_reg.h"
> >  #include "intel_mocs.h"
> >  #include "intel_ring.h"
> > +#include "intel_gpu_commands.h"
> > +#include "uc/intel_guc_ads.h"
> >
> >  /* structures required */
> >  struct drm_i915_mocs_entry {
> > @@ -25,6 +27,28 @@ struct drm_i915_mocs_table {
> >  	u8 uc_index;
> >  };
> >
> > +enum register_type {
> > +	/*
> > +	 * REG_GT: General register - Need to  be re-plied after GT/GPU
> reset
> > +	 * REG_ENGINE: Domain register - needs to be re-applied after
> > +	 *	       engine reset
> > +	 * REG_ENGINE_CONTEXT: Engine state context register - need to
> stored
> > +	 *		       as part of Golden context.
> > +	 */
> > +	REG_GT = 0,
> > +	REG_ENGINE,
> > +	REG_ENGINE_CONTEXT
> > +};
> > +
> > +struct drm_i915_aux_table {
> > +	enum register_type type;
> > +	const char *name;
> > +	i915_reg_t offset;
> > +	u32 value;
> > +	u32 readmask;
> > +	struct drm_i915_aux_table *next;
> > +};
> > +
> >  /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
> >  #define _LE_CACHEABILITY(value)	((value) << 0)
> >  #define _LE_TGT_CACHE(value)	((value) << 2)
> > @@ -336,6 +360,78 @@ static bool has_mocs(const struct
> drm_i915_private *i915)
> >  	return !IS_DGFX(i915);
> >  }
> >
> > +static struct drm_i915_aux_table *
> > +add_aux_reg(struct drm_i915_aux_table *aux,
> > +	    enum register_type type,
> > +	    const char *name,
> > +	    i915_reg_t offset,
> > +	    u32 value,
> > +	    u32 read)
> > +{
> > +	struct drm_i915_aux_table *x;
> > +
> > +	x = kmalloc(sizeof(*x), GFP_ATOMIC);
> > +	if (!x) {
> > +		DRM_ERROR("Failed to allocate aux reg '%s'\n", name);
> > +		return aux;
> > +	}
> > +
> > +	x->type = type;
> > +	x->name = name;
> > +	x->offset = offset;
> > +	x->value = value;
> > +	x->readmask = read;
> > +
> > +	x->next = aux;
> > +	return x;
> > +}
> > +
> > +static const struct drm_i915_aux_table * build_aux_regs(const struct
> > +intel_engine_cs *engine,
> > +	       const struct drm_i915_mocs_table *mocs)
> 
> It seems like the design you have here at the moment is going to allocate and
> fill a new AUX list any time the code needs the list of registers, and then
> frees it immediately afterward.  That seems a bit inefficient to do multiple
> times at runtime (e.g., in execlist mode every engine reset would trigger an
> additional allocation/build/free).
> 
> Can we just build the list once at initialization time (with different parts of the
> code adding their own sets of registers to the table) and then free it later
> when the GT is destroyed?  That's sort of the approach that our workaround
> code takes --- decide which registers are important to deal with a single time
> during device init, then use that pre-built list whenever necessary during
> runtime, and finally free it at GT teardown.
> 
> Also, the function that adds the MOCS-specific registers to the table can be
> kept here in intel_mocs.c, but should probably be added in the next patch
> that deals with MOCS-specific registers.  This patch should focus the
> interfaces to add new registers to the table, and the application of the table's
> registers at different parts of the code.
As I see following works here it will take some time to implement and test.
1. During GT init --> create the aux table.
2. Add the all the register as per respective  need.
3. Apply all the register at one place instead of category 
4. In case if these register need to be programmed different places based on need then
we need add a category identifier. eg. AUX_MOCS. , e.g. intel_mocs_init_engine()
static void apply_aux_regs_engine(struct intel_engine_cs *engine,
			  const struct drm_i915_aux_table *aux) {
	u32 mmio_reg_offset;

	while (aux) {
		if (aux->type == REG_ENGINE  && aux->category == AUX_MOCS ) {
			mmio_reg_offset = i915_mmio_reg_offset(aux->offset);
			intel_uncore_write_fw(engine->uncore,
					      _MMIO(engine->mmio_base +
					      mmio_reg_offset),
					      aux->value);
		}
		aux = aux->next;
	}
}	

5. free the table during gt reset.

 
> 
> 
> > +{
> > +	struct drm_i915_aux_table *aux = NULL;
> > +
> > +	if (GRAPHICS_VER(engine->i915) >= 12 &&
> > +	    !drm_WARN_ONCE(&engine->i915->drm, !mocs->uc_index,
> > +	    "Platform that should have UC index defined and does not\n")) {
> > +		/*
> > +		 * Add Auxiliary register which needs to be programmed with
> > +		 * UC MOCS index. We need to call add_aux_reg() to add
> > +		 * a entry in drm_i915_aux_table link list.
> > +		 */
> > +	}
> > +	return aux;
> > +}
> > +
> > +static void
> > +free_aux_regs(const struct drm_i915_aux_table *aux) {
> > +	while (aux) {
> > +		struct drm_i915_aux_table *next = aux->next;
> > +
> > +		kfree(aux);
> > +		aux = next;
> > +	}
> > +}
> > +
> > +static void apply_aux_regs_engine(struct intel_engine_cs *engine,
> > +				  const struct drm_i915_aux_table *aux) {
> > +	u32 mmio_reg_offset;
> > +
> > +	while (aux) {
> > +		if (aux->type == REG_ENGINE) {
> > +			mmio_reg_offset = i915_mmio_reg_offset(aux-
> >offset);
> > +			intel_uncore_write_fw(engine->uncore,
> > +					      _MMIO(engine->mmio_base +
> > +					      mmio_reg_offset),
> > +					      aux->value);
> > +		}
> > +		aux = aux->next;
> > +	}
> > +}
> > +
> >  static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
> >  				      struct drm_i915_mocs_table *table)  {
> @@ -347,10 +443,12 @@
> > static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
> >  		table->size = ARRAY_SIZE(dg1_mocs_table);
> >  		table->table = dg1_mocs_table;
> >  		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> > +		table->uc_index = 1;
> >  	} else if (GRAPHICS_VER(i915) >= 12) {
> >  		table->size  = ARRAY_SIZE(tgl_mocs_table);
> >  		table->table = tgl_mocs_table;
> >  		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> > +		table->uc_index = 3;
> >  	} else if (GRAPHICS_VER(i915) == 11) {
> >  		table->size  = ARRAY_SIZE(icl_mocs_table);
> >  		table->table = icl_mocs_table;
> > @@ -395,6 +493,87 @@ static unsigned int get_mocs_settings(const struct
> drm_i915_private *i915,
> >  	return flags;
> >  }
> >
> > +int get_ctx_reg_count(const struct drm_i915_aux_table *aux)
> 
> Should this be static?
Yes will take care
> 
> If we keep the aux table around during runtime, we could probably just tally
> up the count as registers are getting added during init, so that we don't need
> to re-walk the list to count them later.
Its only once when we are writing it in golden context. If we have to add a count as member
Then we need count for engine , ctx and global.
> 
> > +{
> > +	int count = 0;
> > +
> > +	while (aux) {
> > +		if (aux->type == REG_ENGINE_CONTEXT)
> > +			count++;
> > +		aux = aux->next;
> > +	}
> > +	return count;
> > +}
> > +
> > +void add_aux_mocs_guc_mmio_regset(struct temp_regset *regset,
> > +				  struct intel_engine_cs *engine)
> 
> If we're making this framework general, we should probably remove 'mocs'
> from the name since it will eventually have other non-mocs registers
> included too once we start using it for other things.
sure
> 
> 
> > +{
> > +	const struct drm_i915_aux_table *aux;
> > +	struct drm_i915_mocs_table table;
> > +	int ret;
> > +
> > +	ret = get_mocs_settings(engine->i915, &table);
> > +	if (!ret)
> > +		return;
> > +
> > +	aux = build_aux_regs(engine, &table);
> > +	if (!aux)
> > +		return;
> > +
> > +	while (aux) {
> > +		if (aux->type == REG_ENGINE)
> > +			GUC_MMIO_REG_ADD(regset,
> > +					 _MMIO(engine->mmio_base
> > +					 + i915_mmio_reg_offset(aux-
> >offset)),
> > +					 true);
> > +		aux = aux->next;
> > +	}
> > +	free_aux_regs(aux);
> > +}
> > +
> > +int apply_mocs_aux_regs_ctx(struct i915_request *rq) {
> > +	const struct drm_i915_aux_table *aux;
> > +	struct drm_i915_mocs_table table;
> > +	u32 *cs;
> > +	int ret, count;
> > +
> > +	ret = get_mocs_settings(rq->engine->i915, &table);
> > +	if (!ret)
> > +		return 0;
> > +
> > +	aux = build_aux_regs(rq->engine, &table);
> > +
> > +	count = get_ctx_reg_count(aux);
> > +	if (!count)
> > +		return 0;
> 

> > +	count = get_ctx_reg_count(aux);
	if (!count)
		return 0;

> With the current init/build/free design, aren't you leaking the table here?
> There might be zero context registers, but there still could have been some
> non-context registers on the list we got back.
Thanks it should be something like that. 
ret = get_mocs_settings(rq->engine->i915, &table);
	if (!ret) {
		free_aux_regs(aux);
		return 0;
 	}
But if we modify the framework for single allocate /remove then its ok 
> 
> > +	ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
> > +	if (ret)
> > +		return ret;
> > +
> > +	cs = intel_ring_begin(rq, (count * 2 + 2));
> > +	if (IS_ERR(cs))
> > +		return PTR_ERR(cs);
> > +
> > +	*cs++ = MI_LOAD_REGISTER_IMM(count);
> > +	while (aux) {
> > +		if (aux->type == REG_ENGINE_CONTEXT) {
> > +			*cs++ = i915_mmio_reg_offset(aux->offset);
> > +			*cs++ = aux->value;
> > +		}
> > +		aux = aux->next;
> > +	}
> > +	*cs++ = MI_NOOP;
> > +
> > +	intel_ring_advance(rq, cs);
> > +	free_aux_regs(aux);
> > +	ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
> > +	if (ret)
> > +		return ret;
> > +
> > +	return 0;
> > +}
> > +
> >  /*
> >   * Get control_value from MOCS entry taking into account when it's not
> used:
> >   * I915_MOCS_PTE's value is returned in this case.
> > @@ -484,6 +663,7 @@ static void init_l3cc_table(struct intel_engine_cs
> > *engine,
> >
> >  void intel_mocs_init_engine(struct intel_engine_cs *engine)  {
> > +	const struct drm_i915_aux_table *aux;
> >  	struct drm_i915_mocs_table table;
> >  	unsigned int flags;
> >
> > @@ -500,6 +680,10 @@ void intel_mocs_init_engine(struct
> > intel_engine_cs *engine)
> >
> >  	if (flags & HAS_RENDER_L3CC && engine->class == RENDER_CLASS)
> >  		init_l3cc_table(engine, &table);
> > +
> > +	aux = build_aux_regs(engine, &table);
> > +	apply_aux_regs_engine(engine, aux);
> > +	free_aux_regs(aux);
> >  }
> >
> >  static u32 global_mocs_offset(void)
> > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h
> > b/drivers/gpu/drm/i915/gt/intel_mocs.h
> > index d83274f5163bd..0f362a0acc3a3 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_mocs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
> > @@ -33,8 +33,13 @@
> >
> >  struct intel_engine_cs;
> >  struct intel_gt;
> > +struct i915_request;
> > +struct temp_regset;
> >
> >  void intel_mocs_init(struct intel_gt *gt);  void
> > intel_mocs_init_engine(struct intel_engine_cs *engine);
> > +int apply_mocs_aux_regs_ctx(struct i915_request *rq); void
> > +add_aux_mocs_guc_mmio_regset(struct temp_regset *regset,
> > +				  struct intel_engine_cs *engine);
> >
> >  #endif
> > diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c
> > b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> > index 13d25bf2a94aa..2b0207dfbf21c 100644
> > --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
> > +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> 
> If we still want to have selftests that operate on specific subsets of the aux
> table after we make it more generic, we could potentially add a 'aux source'
> field to 'struct drm_i915_aux_table' that represents what part of the code
> added the register (MOCS, uapi compat, etc.).  Then we can easily ignore the
> registers on the table that aren't relevant to the specific selftest.
Yes we need to add Source/category as mentioned above.
> 
> > @@ -155,6 +155,47 @@ static int read_l3cc_table(struct i915_request *rq,
> >  	return read_regs(rq, addr, (table->n_entries + 1) / 2, offset);  }
> >
> > +static int read_aux_regs(struct i915_request *rq,
> > +			 const struct drm_i915_aux_table *r,
> > +			 u32 *offset)
> > +{
> > +	int err;
> > +
> > +	while (r) {
> > +		err = read_regs(rq,
> > +				rq->engine->mmio_base +
> i915_mmio_reg_offset(r->offset), 1,
> > +				offset);
> > +		if (err)
> > +			return err;
> > +
> > +		r = r->next;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +static int check_aux_regs(struct intel_engine_cs *engine,
> > +			  const struct drm_i915_aux_table *r,
> > +			  u32 **vaddr)
> 
> One other concern (which is part of why I didn't really want to see this
> framework handled separately from workarounds) is that the aux table
> might tell us to program a register with a specific value, but we may also have
> a hardware workaround for a platform/stepping that overrides that with an
> alternate value.  Our workaround framework is smart enough to combine
> multiple entries for the same register into a single operation (if the set of bits
> being updated are different), or will warn if there's two conflicting sets of
> programming requested for certain bits. Right now it's not clear who wins if
> the aux table wants to program a register to value 'X' but the workaround
> lists want to program the same register to value 'Y.'  In theory the
> workaround should overrule the regular programming, but at the moment
> these selftests aren't checking to see if that's the case.  We may not have any
> such conflicts today (especially since we have so few registers that are going
> to be on the aux table initially), but it may come up eventually.
Yes its valid point, I did not thought about it. Do you think that moving to
workaround will be better option here?

-Ayaz

> 
> 
> Matt

> 
> > +{
> > +	while (r) {
> > +		u32 expect = r->value & r->readmask;
> > +		u32 masked_value = **vaddr & r->readmask;
> > +
> > +		if (masked_value != expect) {
> > +			pr_err("%s: Invalid entry %s[%x]=0x%x, relevant bits
> were 0x%x vs expected 0x%x\n",
> > +			       engine->name, r->name,
> > +			       i915_mmio_reg_offset(r->offset), **vaddr,
> > +			       masked_value, expect);
> > +			return -EINVAL;
> > +		}
> > +		++*vaddr;
> > +		r = r->next;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> >  static int check_mocs_table(struct intel_engine_cs *engine,
> >  			    const struct drm_i915_mocs_table *table,
> >  			    u32 **vaddr)
> > @@ -216,6 +257,7 @@ static int check_mocs_engine(struct live_mocs *arg,
> >  			     struct intel_context *ce)
> >  {
> >  	struct i915_vma *vma = arg->scratch;
> > +	const struct drm_i915_aux_table *aux;
> >  	struct i915_request *rq;
> >  	u32 offset;
> >  	u32 *vaddr;
> > @@ -223,6 +265,8 @@ static int check_mocs_engine(struct live_mocs
> > *arg,
> >
> >  	memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE / sizeof(u32));
> >
> > +	aux = build_aux_regs(ce->engine, &arg->table);
> > +
> >  	rq = intel_context_create_request(ce);
> >  	if (IS_ERR(rq))
> >  		return PTR_ERR(rq);
> > @@ -239,6 +283,8 @@ static int check_mocs_engine(struct live_mocs *arg,
> >  		err = read_mocs_table(rq, arg->mocs, &offset);
> >  	if (!err && ce->engine->class == RENDER_CLASS)
> >  		err = read_l3cc_table(rq, arg->l3cc, &offset);
> > +	if (!err)
> > +		err = read_aux_regs(rq, aux, &offset);
> >  	offset -= i915_ggtt_offset(vma);
> >  	GEM_BUG_ON(offset > PAGE_SIZE);
> >
> > @@ -252,10 +298,13 @@ static int check_mocs_engine(struct live_mocs
> *arg,
> >  		err = check_mocs_table(ce->engine, arg->mocs, &vaddr);
> >  	if (!err && ce->engine->class == RENDER_CLASS)
> >  		err = check_l3cc_table(ce->engine, arg->l3cc, &vaddr);
> > +	if (!err)
> > +		err = check_aux_regs(ce->engine, aux, &vaddr);
> >  	if (err)
> >  		return err;
> >
> >  	GEM_BUG_ON(arg->vaddr + offset != vaddr);
> > +	free_aux_regs(aux);
> >  	return 0;
> >  }
> >
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> > index 6926919bcac6b..be4cca49abced 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> > @@ -12,6 +12,7 @@
> >  #include "intel_guc_fwif.h"
> >  #include "intel_uc.h"
> >  #include "i915_drv.h"
> > +#include "gt/intel_mocs.h"
> >
> >  /*
> >   * The Additional Data Struct (ADS) has pointers for different
> > buffers used by @@ -187,11 +188,6 @@ static void
> guc_mapping_table_init(struct intel_gt *gt,
> >   * inside the ADS.
> >   */
> >  #define MAX_MMIO_REGS	128	/* Arbitrary size, increase as needed
> */
> > -struct temp_regset {
> > -	struct guc_mmio_reg *registers;
> > -	u32 used;
> > -	u32 size;
> > -};
> >
> >  static int guc_mmio_reg_cmp(const void *a, const void *b)  { @@
> > -201,8 +197,8 @@ static int guc_mmio_reg_cmp(const void *a, const void
> *b)
> >  	return (int)ra->offset - (int)rb->offset;  }
> >
> > -static void guc_mmio_reg_add(struct temp_regset *regset,
> > -			     u32 offset, u32 flags)
> > +void guc_mmio_reg_add(struct temp_regset *regset,
> > +		      u32 offset, u32 flags)
> >  {
> >  	u32 count = regset->used;
> >  	struct guc_mmio_reg reg = {
> > @@ -236,11 +232,6 @@ static void guc_mmio_reg_add(struct temp_regset
> *regset,
> >  	}
> >  }
> >
> > -#define GUC_MMIO_REG_ADD(regset, reg, masked) \
> > -	guc_mmio_reg_add(regset, \
> > -			 i915_mmio_reg_offset((reg)), \
> > -			 (masked) ? GUC_REGSET_MASKED : 0)
> > -
> >  static void guc_mmio_regset_init(struct temp_regset *regset,
> >  				 struct intel_engine_cs *engine)
> >  {
> > @@ -258,6 +249,8 @@ static void guc_mmio_regset_init(struct
> temp_regset *regset,
> >  	for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
> >  		GUC_MMIO_REG_ADD(regset, wa->reg, wa->masked_reg);
> >
> > +	add_aux_mocs_guc_mmio_regset(regset, engine);
> > +
> >  	/* Be extra paranoid and include all whitelist registers. */
> >  	for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++)
> >  		GUC_MMIO_REG_ADD(regset,
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
> > b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
> > index 3d85051d57e45..75736c56fa187 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
> > @@ -6,9 +6,24 @@
> >  #ifndef _INTEL_GUC_ADS_H_
> >  #define _INTEL_GUC_ADS_H_
> >
> > +#include <linux/types.h>
> > +
> > +struct temp_regset {
> > +	struct guc_mmio_reg *registers;
> > +	u32 used;
> > +	u32 size;
> > +};
> > +
> >  struct intel_guc;
> >  struct drm_printer;
> >
> > +void guc_mmio_reg_add(struct temp_regset *regset,
> > +		      u32 offset, u32 flags);
> > +#define GUC_MMIO_REG_ADD(regset, reg, masked) \
> > +	guc_mmio_reg_add(regset, \
> > +			 i915_mmio_reg_offset((reg)), \
> > +			 (masked) ? GUC_REGSET_MASKED : 0)
> > +
> >  int intel_guc_ads_create(struct intel_guc *guc);  void
> > intel_guc_ads_destroy(struct intel_guc *guc);  void
> > intel_guc_ads_init_late(struct intel_guc *guc);
> > --
> > 2.26.2
> >
> 
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795

Re: [Intel-gfx] [PATCH V3 2/8] drm/i915/gt: Add support of mocs auxiliary registers programming

[Matt Roper]

On Thu, Sep 02, 2021 at 04:56:18AM -0700, Siddiqui, Ayaz A wrote:
...
> > > +static int check_aux_regs(struct intel_engine_cs *engine,
> > > +                     const struct drm_i915_aux_table *r,
> > > +                     u32 **vaddr)
> >
> > One other concern (which is part of why I didn't really want to see this
> > framework handled separately from workarounds) is that the aux table
> > might tell us to program a register with a specific value, but we may also have
> > a hardware workaround for a platform/stepping that overrides that with an
> > alternate value.  Our workaround framework is smart enough to combine
> > multiple entries for the same register into a single operation (if the set of bits
> > being updated are different), or will warn if there's two conflicting sets of
> > programming requested for certain bits. Right now it's not clear who wins if
> > the aux table wants to program a register to value 'X' but the workaround
> > lists want to program the same register to value 'Y.'  In theory the
> > workaround should overrule the regular programming, but at the moment
> > these selftests aren't checking to see if that's the case.  We may not have any
> > such conflicts today (especially since we have so few registers that are going
> > to be on the aux table initially), but it may come up eventually.
> Yes its valid point, I did not thought about it. Do you think that moving to
> workaround will be better option here?

I think there's a short-term and a long-term aspect here.  My opinion is
that in the immediate short term we should add these two MOCS-related
registers (one of which is a context register, one of which is an engine
register) as additional fake workarounds.  Despite calling them
"workarounds" that part of the code is already more of a generic "GT
register override" framework, and we already have a number of things
programmed there that aren't actually workarounds.  Trying to spin up a
completely new framework ("aux table") for GT register overrides is
going to take a bit more time to get right, and I'm not sure we want to
hold up the proper MOCS programming while that happens (especially since
ADL is about to leave "force probe required" state and we really don't
want to miss the boat on getting MOCS programmed correctly before that
happens).

Longer term I do think we want to rework how we handle both formal
workarounds and non-workaround register overrides in the driver.  That's
been something I've been meaning to work on for quite a while now, but
it just keeps getting preempted by higher priority tasks that show up;
hopefully I can get back to it soon.  But such rework is going to take a
bit of time, both to get widespread agreement on the redesign, and to do
some extensive testing to make sure we don't mishandle any corner cases
around reset handling, execlist vs GuC, etc.  It will also probably
happen in multiple steps rather than jumping from our current design
straight to the final form; I don't think it makes sense to make the
MOCS programming dependent on completion of that long, multi-step
process.

I think one of Chris' concerns about re-using the workaround framework
for setting these two MOCS-related registers is that the programming
would wind up getting verified by the workarounds selftest rather than
the mocs selftest (and thus failures on these specific registers may not
get the attention they need).  That's true, but if the concern is great
enough, I think we could make the gt_mocs selftest:
 - scan the workaround lists and ensure that the two MOCS-related
   registers truly are present on the appropriate list (if not, error)
 - check that the register programming still matches the value defined
   in the workaround (if not, error); this would duplicate the check
   also done in the workaround selftest, but that's probably fine to
   have both tests fail if there's a programming problem
 - lookup the programmed MOCS values in the platform's MOCS table and
   make sure that they really have the expected characteristics (L3 on
   platforms going forward, UC on the older platforms that we can't
   change now for abi compat reasons)


Matt


> 
> -Ayaz
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

Re: [Intel-gfx] [PATCH V3 2/8] drm/i915/gt: Add support of mocs auxiliary registers programming

[Siddiqui, Ayaz A]

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Thursday, September 2, 2021 9:36 PM
> To: Siddiqui, Ayaz A <ayaz.siddiqui@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; S, Srinivasan <srinivasan.s@intel.com>;
> Wilson, Chris P <chris.p.wilson@intel.com>
> Subject: Re: [PATCH V3 2/8] drm/i915/gt: Add support of mocs auxiliary
> registers programming
> 
> On Thu, Sep 02, 2021 at 04:56:18AM -0700, Siddiqui, Ayaz A wrote:
> ...
> > > > +static int check_aux_regs(struct intel_engine_cs *engine,
> > > > +                     const struct drm_i915_aux_table *r,
> > > > +                     u32 **vaddr)
> > >
> > > One other concern (which is part of why I didn't really want to see
> > > this framework handled separately from workarounds) is that the aux
> > > table might tell us to program a register with a specific value, but
> > > we may also have a hardware workaround for a platform/stepping that
> > > overrides that with an alternate value.  Our workaround framework is
> > > smart enough to combine multiple entries for the same register into
> > > a single operation (if the set of bits being updated are different),
> > > or will warn if there's two conflicting sets of programming
> > > requested for certain bits. Right now it's not clear who wins if the
> > > aux table wants to program a register to value 'X' but the
> > > workaround lists want to program the same register to value 'Y.'  In
> > > theory the workaround should overrule the regular programming, but
> > > at the moment these selftests aren't checking to see if that's the
> > > case.  We may not have any such conflicts today (especially since we have
> so few registers that are going to be on the aux table initially), but it may
> come up eventually.
> > Yes its valid point, I did not thought about it. Do you think that
> > moving to workaround will be better option here?
> 
> I think there's a short-term and a long-term aspect here.  My opinion is that
> in the immediate short term we should add these two MOCS-related
> registers (one of which is a context register, one of which is an engine
> register) as additional fake workarounds.  Despite calling them
> "workarounds" that part of the code is already more of a generic "GT register
> override" framework, and we already have a number of things programmed
> there that aren't actually workarounds.  Trying to spin up a completely new
> framework ("aux table") for GT register overrides is going to take a bit more
> time to get right, and I'm not sure we want to hold up the proper MOCS
> programming while that happens (especially since ADL is about to leave
> "force probe required" state and we really don't want to miss the boat on
> getting MOCS programmed correctly before that happens).
> 
> Longer term I do think we want to rework how we handle both formal
> workarounds and non-workaround register overrides in the driver.  That's
> been something I've been meaning to work on for quite a while now, but it
> just keeps getting preempted by higher priority tasks that show up;
> hopefully I can get back to it soon.  But such rework is going to take a bit of
> time, both to get widespread agreement on the redesign, and to do some
> extensive testing to make sure we don't mishandle any corner cases around
> reset handling, execlist vs GuC, etc.  It will also probably happen in multiple
> steps rather than jumping from our current design straight to the final form; I
> don't think it makes sense to make the MOCS programming dependent on
> completion of that long, multi-step process.
> 
> I think one of Chris' concerns about re-using the workaround framework for
> setting these two MOCS-related registers is that the programming would
> wind up getting verified by the workarounds selftest rather than the mocs
> selftest (and thus failures on these specific registers may not get the
> attention they need).  That's true, but if the concern is great enough, I think
> we could make the gt_mocs selftest:
>  - scan the workaround lists and ensure that the two MOCS-related
>    registers truly are present on the appropriate list (if not, error)
>  - check that the register programming still matches the value defined
>    in the workaround (if not, error); this would duplicate the check
>    also done in the workaround selftest, but that's probably fine to
>    have both tests fail if there's a programming problem
>  - lookup the programmed MOCS values in the platform's MOCS table and
>    make sure that they really have the expected characteristics (L3 on
>    platforms going forward, UC on the older platforms that we can't
>    change now for abi compat reasons)
> 
> 
> Matt
Thanks Matt, I have modified that register programming using workaround framework.
I'll share the new series soon.
Since we have already planned to rework on framework so let add category specific
verification in scope of that planned activity instead of adding a temporary
verification in mocs selftest.
Meanwhile programming of values are already verified in workaround.

Regards
-Ayaz


> 
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795

[Intel-gfx] [PATCH V3 3/8] drm/i915/gt: Set CMD_CCTL to UC for Gen12 Onward

[Ayaz A Siddiqui]

Cache-control registers for Command Stream(CMD_CCTL) are used
to set catchability for memory writes and reads outputted by
Command Streamers on Gen12 onward platforms.

These registers need to point un-cached(UC) MOCS index.

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_mocs.c | 12 ++++++++++++
 drivers/gpu/drm/i915/i915_reg.h      | 16 ++++++++++++++++
 2 files changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index c52640523c218..403bd48362b19 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -386,6 +386,17 @@ add_aux_reg(struct drm_i915_aux_table *aux,
 	return x;
 }
 
+static struct drm_i915_aux_table *
+add_cmd_cctl_override(struct drm_i915_aux_table *aux, u8 idx)
+{
+	return add_aux_reg(aux,
+			   REG_ENGINE,
+			   "CMD_CCTL",
+			   RING_CMD_CCTL(0),
+			   CMD_CCTL_MOCS_OVERRIDE(idx, idx),
+			   CMD_CCTL_WRITE_OVERRIDE_MASK | CMD_CCTL_READ_OVERRIDE_MASK);
+}
+
 static const struct drm_i915_aux_table *
 build_aux_regs(const struct intel_engine_cs *engine,
 	       const struct drm_i915_mocs_table *mocs)
@@ -400,6 +411,7 @@ build_aux_regs(const struct intel_engine_cs *engine,
 		 * UC MOCS index. We need to call add_aux_reg() to add
 		 * a entry in drm_i915_aux_table link list.
 		 */
+		aux = add_cmd_cctl_override(aux, mocs->uc_index);
 	}
 	return aux;
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8d4cf1e203ab7..df7a4550fb50f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2551,6 +2551,22 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define RING_HWS_PGA(base)	_MMIO((base) + 0x80)
 #define RING_ID(base)		_MMIO((base) + 0x8c)
 #define RING_HWS_PGA_GEN6(base)	_MMIO((base) + 0x2080)
+
+#define RING_CMD_CCTL(base)	_MMIO((base) + 0xc4)
+/*
+ * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
+ * The lsb of each can be considered a separate enabling bit for encryption.
+ * 6:0 == default MOCS value for reads  =>  6:1 == table index for reads.
+ * 13:7 == default MOCS value for writes => 13:8 == table index for writes.
+ * 15:14 == Reserved => 31:30 are set to 0.
+ */
+#define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7)
+#define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0)
+#define CMD_CCTL_MOCS_OVERRIDE(write, read)					\
+	_MASKED_FIELD(CMD_CCTL_WRITE_OVERRIDE_MASK | CMD_CCTL_READ_OVERRIDE_MASK, \
+		      REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
+		      REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
+
 #define RING_RESET_CTL(base)	_MMIO((base) + 0xd0)
 #define   RESET_CTL_CAT_ERROR	   REG_BIT(2)
 #define   RESET_CTL_READY_TO_RESET REG_BIT(1)
-- 
2.26.2

[Intel-gfx] [PATCH V3 4/8] drm/i915/gt: Set BLIT_CCTL reg to un-cached

[Ayaz A Siddiqui]

From: Apoorva Singh <apoorva1.singh@intel.com>

Blitter commands which do not have MOCS fields rely on
cacheability of BlitterCacheControlRegister which was mapped
to index 0 by default.Once we changed the MOCS value of
index 0 to L3 WB, tests like gem_linear_blits started failing
due to a change in cacheability from UC to WB.

Program and place the BlitterCacheControlRegister in
build_aux_regs().

Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_mocs.c | 13 +++++++++++++
 drivers/gpu/drm/i915/i915_reg.h      |  7 +++++++
 2 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 403bd48362b19..82eafa8d22453 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -386,6 +386,17 @@ add_aux_reg(struct drm_i915_aux_table *aux,
 	return x;
 }
 
+static struct drm_i915_aux_table *
+add_blit_cctl_override(struct drm_i915_aux_table *aux, u8 idx)
+{
+	return add_aux_reg(aux,
+			   REG_ENGINE_CONTEXT,
+			   "BLIT_CCTL",
+			   BLIT_CCTL(0),
+			   BLIT_CCTL_MOCS(idx, idx),
+			   0);
+}
+
 static struct drm_i915_aux_table *
 add_cmd_cctl_override(struct drm_i915_aux_table *aux, u8 idx)
 {
@@ -412,6 +423,8 @@ build_aux_regs(const struct intel_engine_cs *engine,
 		 * a entry in drm_i915_aux_table link list.
 		 */
 		aux = add_cmd_cctl_override(aux, mocs->uc_index);
+		if (engine->class == COPY_ENGINE_CLASS)
+			aux = add_blit_cctl_override(aux, mocs->uc_index);
 	}
 	return aux;
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index df7a4550fb50f..207e0ada179b2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2567,6 +2567,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 		      REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
 		      REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
 
+#define BLIT_CCTL(base)	_MMIO((base) + 0x204)
+#define   BLIT_CCTL_DST_MOCS_MASK	REG_GENMASK(14, 8)
+#define   BLIT_CCTL_SRC_MOCS_MASK	REG_GENMASK(6, 0)
+#define   BLIT_CCTL_DST_MOCS_SHIFT	8
+#define   BLIT_CCTL_MOCS(dst, src)							\
+	((((dst) << 1) << BLIT_CCTL_DST_MOCS_SHIFT) | ((src) << 1))
+
 #define RING_RESET_CTL(base)	_MMIO((base) + 0xd0)
 #define   RESET_CTL_CAT_ERROR	   REG_BIT(2)
 #define   RESET_CTL_READY_TO_RESET REG_BIT(1)
-- 
2.26.2

Re: [Intel-gfx] [PATCH V3 4/8] drm/i915/gt: Set BLIT_CCTL reg to un-cached

[Matt Roper]

On Mon, Aug 30, 2021 at 09:52:36PM +0530, Ayaz A Siddiqui wrote:
> From: Apoorva Singh <apoorva1.singh@intel.com>
> 
> Blitter commands which do not have MOCS fields rely on
> cacheability of BlitterCacheControlRegister which was mapped
> to index 0 by default.Once we changed the MOCS value of
> index 0 to L3 WB, tests like gem_linear_blits started failing
> due to a change in cacheability from UC to WB.
> 
> Program and place the BlitterCacheControlRegister in
> build_aux_regs().
> 
> Signed-off-by: Apoorva Singh <apoorva1.singh@intel.com>
> Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_mocs.c | 13 +++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h      |  7 +++++++
>  2 files changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 403bd48362b19..82eafa8d22453 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -386,6 +386,17 @@ add_aux_reg(struct drm_i915_aux_table *aux,
>  	return x;
>  }
>  
> +static struct drm_i915_aux_table *
> +add_blit_cctl_override(struct drm_i915_aux_table *aux, u8 idx)
> +{
> +	return add_aux_reg(aux,
> +			   REG_ENGINE_CONTEXT,
> +			   "BLIT_CCTL",
> +			   BLIT_CCTL(0),
> +			   BLIT_CCTL_MOCS(idx, idx),
> +			   0);
> +}
> +
>  static struct drm_i915_aux_table *
>  add_cmd_cctl_override(struct drm_i915_aux_table *aux, u8 idx)
>  {
> @@ -412,6 +423,8 @@ build_aux_regs(const struct intel_engine_cs *engine,
>  		 * a entry in drm_i915_aux_table link list.
>  		 */
>  		aux = add_cmd_cctl_override(aux, mocs->uc_index);
> +		if (engine->class == COPY_ENGINE_CLASS)
> +			aux = add_blit_cctl_override(aux, mocs->uc_index);
>  	}
>  	return aux;
>  }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index df7a4550fb50f..207e0ada179b2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2567,6 +2567,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  		      REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
>  		      REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
>  
> +#define BLIT_CCTL(base)	_MMIO((base) + 0x204)
> +#define   BLIT_CCTL_DST_MOCS_MASK	REG_GENMASK(14, 8)
> +#define   BLIT_CCTL_SRC_MOCS_MASK	REG_GENMASK(6, 0)
> +#define   BLIT_CCTL_DST_MOCS_SHIFT	8
> +#define   BLIT_CCTL_MOCS(dst, src)							\
> +	((((dst) << 1) << BLIT_CCTL_DST_MOCS_SHIFT) | ((src) << 1))

It would be preferable to write this as

        #define   BLIT_CCTL_MOCS(dst, src) (\
                REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst << 1)) | \
                REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src << 1)) \
        )

You can drop BLIT_CCTL_DST_MOCS_SHIFT too then.


In general the changes in this patch and patch #3 look okay, but they
may need to be reworked slightly if we change the general design of the
aux table framework based on the review feedback there.


Matt

> +
>  #define RING_RESET_CTL(base)	_MMIO((base) + 0xd0)
>  #define   RESET_CTL_CAT_ERROR	   REG_BIT(2)
>  #define   RESET_CTL_READY_TO_RESET REG_BIT(1)
> -- 
> 2.26.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

[Intel-gfx] [PATCH V3 5/8] drm/i915/gt: Initialize unused MOCS entries with device specific values

[Ayaz A Siddiqui]

Historically we've initialized all undefined/reserved entries in
a platform's MOCS table to the contents of table entry #1 (i.e.,
I915_MOCS_PTE).
Going forward, we can't assume that table entry #1 will always
contain suitable values to use for undefined/reserved table
indices. We'll allow a platform-specific table index to be
selected at table initialization time in these cases.

This new mechanism to select L3 WB entry will be applicable for
all the Gen12+ platforms except TGL and RKL.

Since TGL and RLK are already in production so their mocs settings
are intact to avoid ABI break.

Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_mocs.c | 41 +++++++++++++++-------------
 1 file changed, 22 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 82eafa8d22453..a97cc08e5a395 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -25,6 +25,7 @@ struct drm_i915_mocs_table {
 	unsigned int n_entries;
 	const struct drm_i915_mocs_entry *table;
 	u8 uc_index;
+	u8 unused_entries_index;
 };
 
 enum register_type {
@@ -113,18 +114,25 @@ struct drm_i915_aux_table {
  *
  * Entries not part of the following tables are undefined as far as
  * userspace is concerned and shouldn't be relied upon.  For Gen < 12
- * they will be initialized to PTE. Gen >= 12 onwards don't have a setting for
- * PTE and will be initialized to an invalid value.
+ * they will be initialized to PTE. Gen >= 12 don't have a setting for
+ * PTE and those platforms except TGL/RKL will be initialized L3 WB to
+ * catch accidental use of reserved and unused mocs indexes.
  *
  * The last few entries are reserved by the hardware. For ICL+ they
  * should be initialized according to bspec and never used, for older
  * platforms they should never be written to.
  *
- * NOTE: These tables are part of bspec and defined as part of hardware
+ * NOTE1: These tables are part of bspec and defined as part of hardware
  *       interface for ICL+. For older platforms, they are part of kernel
  *       ABI. It is expected that, for specific hardware platform, existing
  *       entries will remain constant and the table will only be updated by
  *       adding new entries, filling unused positions.
+ *
+ * NOTE2: For GEN >= 12 except TGL and RKL, reserved and unspecified MOCS
+ *       indices have been set to L3 WB. These reserved entries should never
+ *       be used, they may be changed to low performant variants with better
+ *       coherency in the future if more entries are needed.
+ *       For TGL/RKL, all the unspecified MOCS indexes are mapped to L3 UC.
  */
 #define GEN9_MOCS_ENTRIES \
 	MOCS_ENTRY(I915_MOCS_UNCACHED, \
@@ -307,17 +315,9 @@ static const struct drm_i915_mocs_entry icl_mocs_table[] = {
 };
 
 static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
-	/* Error */
-	MOCS_ENTRY(0, 0, L3_0_DIRECT),
 
 	/* UC */
 	MOCS_ENTRY(1, 0, L3_1_UC),
-
-	/* Reserved */
-	MOCS_ENTRY(2, 0, L3_0_DIRECT),
-	MOCS_ENTRY(3, 0, L3_0_DIRECT),
-	MOCS_ENTRY(4, 0, L3_0_DIRECT),
-
 	/* WB - L3 */
 	MOCS_ENTRY(5, 0, L3_3_WB),
 	/* WB - L3 50% */
@@ -469,6 +469,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
 		table->table = dg1_mocs_table;
 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
 		table->uc_index = 1;
+		table->unused_entries_index = 5;
 	} else if (GRAPHICS_VER(i915) >= 12) {
 		table->size  = ARRAY_SIZE(tgl_mocs_table);
 		table->table = tgl_mocs_table;
@@ -600,16 +601,17 @@ int apply_mocs_aux_regs_ctx(struct i915_request *rq)
 }
 
 /*
- * Get control_value from MOCS entry taking into account when it's not used:
- * I915_MOCS_PTE's value is returned in this case.
+ * Get control_value from MOCS entry taking into account when it's not used
+ * then if unused_entries_index is non-zero then its value will be returned
+ * otherwise I915_MOCS_PTE's value is returned in this case.
  */
 static u32 get_entry_control(const struct drm_i915_mocs_table *table,
 			     unsigned int index)
 {
 	if (index < table->size && table->table[index].used)
 		return table->table[index].control_value;
-
-	return table->table[I915_MOCS_PTE].control_value;
+	index = table->unused_entries_index ? : I915_MOCS_PTE;
+	return table->table[index].control_value;
 }
 
 #define for_each_mocs(mocs, t, i) \
@@ -650,16 +652,17 @@ static void init_mocs_table(struct intel_engine_cs *engine,
 }
 
 /*
- * Get l3cc_value from MOCS entry taking into account when it's not used:
- * I915_MOCS_PTE's value is returned in this case.
+ * Get l3cc_value from MOCS entry taking into account when it's not used
+ * then if unused_entries_index is not zero then its value will be returned
+ * otherwise I915_MOCS_PTE's value is returned in this case.
  */
 static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table,
 			  unsigned int index)
 {
 	if (index < table->size && table->table[index].used)
 		return table->table[index].l3cc_value;
-
-	return table->table[I915_MOCS_PTE].l3cc_value;
+	index = table->unused_entries_index ? : I915_MOCS_PTE;
+	return table->table[index].l3cc_value;
 }
 
 static u32 l3cc_combine(u16 low, u16 high)
-- 
2.26.2

Re: [Intel-gfx] [PATCH V3 5/8] drm/i915/gt: Initialize unused MOCS entries with device specific values

[Matt Roper]

On Mon, Aug 30, 2021 at 09:52:37PM +0530, Ayaz A Siddiqui wrote:
> Historically we've initialized all undefined/reserved entries in
> a platform's MOCS table to the contents of table entry #1 (i.e.,
> I915_MOCS_PTE).
> Going forward, we can't assume that table entry #1 will always
> contain suitable values to use for undefined/reserved table
> indices. We'll allow a platform-specific table index to be
> selected at table initialization time in these cases.
> 
> This new mechanism to select L3 WB entry will be applicable for
> all the Gen12+ platforms except TGL and RKL.
> 
> Since TGL and RLK are already in production so their mocs settings
> are intact to avoid ABI break.
> 
> Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_mocs.c | 41 +++++++++++++++-------------
>  1 file changed, 22 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 82eafa8d22453..a97cc08e5a395 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -25,6 +25,7 @@ struct drm_i915_mocs_table {
>  	unsigned int n_entries;
>  	const struct drm_i915_mocs_entry *table;
>  	u8 uc_index;
> +	u8 unused_entries_index;
>  };
>  
>  enum register_type {
> @@ -113,18 +114,25 @@ struct drm_i915_aux_table {
>   *
>   * Entries not part of the following tables are undefined as far as
>   * userspace is concerned and shouldn't be relied upon.  For Gen < 12
> - * they will be initialized to PTE. Gen >= 12 onwards don't have a setting for
> - * PTE and will be initialized to an invalid value.
> + * they will be initialized to PTE. Gen >= 12 don't have a setting for
> + * PTE and those platforms except TGL/RKL will be initialized L3 WB to
> + * catch accidental use of reserved and unused mocs indexes.
>   *
>   * The last few entries are reserved by the hardware. For ICL+ they
>   * should be initialized according to bspec and never used, for older
>   * platforms they should never be written to.
>   *
> - * NOTE: These tables are part of bspec and defined as part of hardware
> + * NOTE1: These tables are part of bspec and defined as part of hardware
>   *       interface for ICL+. For older platforms, they are part of kernel
>   *       ABI. It is expected that, for specific hardware platform, existing
>   *       entries will remain constant and the table will only be updated by
>   *       adding new entries, filling unused positions.
> + *
> + * NOTE2: For GEN >= 12 except TGL and RKL, reserved and unspecified MOCS
> + *       indices have been set to L3 WB. These reserved entries should never
> + *       be used, they may be changed to low performant variants with better
> + *       coherency in the future if more entries are needed.
> + *       For TGL/RKL, all the unspecified MOCS indexes are mapped to L3 UC.
>   */
>  #define GEN9_MOCS_ENTRIES \
>  	MOCS_ENTRY(I915_MOCS_UNCACHED, \
> @@ -307,17 +315,9 @@ static const struct drm_i915_mocs_entry icl_mocs_table[] = {
>  };
>  
>  static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
> -	/* Error */
> -	MOCS_ENTRY(0, 0, L3_0_DIRECT),
>  
>  	/* UC */
>  	MOCS_ENTRY(1, 0, L3_1_UC),
> -
> -	/* Reserved */
> -	MOCS_ENTRY(2, 0, L3_0_DIRECT),
> -	MOCS_ENTRY(3, 0, L3_0_DIRECT),
> -	MOCS_ENTRY(4, 0, L3_0_DIRECT),
> -
>  	/* WB - L3 */
>  	MOCS_ENTRY(5, 0, L3_3_WB),
>  	/* WB - L3 50% */
> @@ -469,6 +469,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
>  		table->table = dg1_mocs_table;
>  		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
>  		table->uc_index = 1;
> +		table->unused_entries_index = 5;
>  	} else if (GRAPHICS_VER(i915) >= 12) {
>  		table->size  = ARRAY_SIZE(tgl_mocs_table);
>  		table->table = tgl_mocs_table;

Should we add

        table->unused_entries_index = 1;

to the rest of the platforms here since that's what we're doing in
get_entry_l3cc() anyway?

Also I think we can rely on that to avoid the need to add a new MOCS
table for ADL in the next patch; we can just use the same table but set
a different unused_entries_index.  E.g.,

        } else if (IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) {
                ...
                /* UC: Can't be changed now for ABI reasons */
                table->unused_entries_index = 1;
        } else if (GRAPHICS_VER(i915) >= 12) {
                ...
                /* L3 */
                table->unused_entries_index = 2;
        } else if (GRAPHICS_VER(i915) == 11) {
                ...
                table->unused_entries_index = 1;
        ...


> @@ -600,16 +601,17 @@ int apply_mocs_aux_regs_ctx(struct i915_request *rq)
>  }
>  
>  /*
> - * Get control_value from MOCS entry taking into account when it's not used:
> - * I915_MOCS_PTE's value is returned in this case.
> + * Get control_value from MOCS entry taking into account when it's not used
> + * then if unused_entries_index is non-zero then its value will be returned
> + * otherwise I915_MOCS_PTE's value is returned in this case.
>   */
>  static u32 get_entry_control(const struct drm_i915_mocs_table *table,
>  			     unsigned int index)
>  {
>  	if (index < table->size && table->table[index].used)
>  		return table->table[index].control_value;
> -
> -	return table->table[I915_MOCS_PTE].control_value;
> +	index = table->unused_entries_index ? : I915_MOCS_PTE;

As noted above, I'd rather see us do this right in the MOCS settings
setup.  Then we'd probably just want a
drm_WARN_ON(!table->unused_entries_index) to make sure we don't forget
to explicitly set it for any platforms.

> +	return table->table[index].control_value;
>  }
>  
>  #define for_each_mocs(mocs, t, i) \
> @@ -650,16 +652,17 @@ static void init_mocs_table(struct intel_engine_cs *engine,
>  }
>  
>  /*
> - * Get l3cc_value from MOCS entry taking into account when it's not used:
> - * I915_MOCS_PTE's value is returned in this case.
> + * Get l3cc_value from MOCS entry taking into account when it's not used
> + * then if unused_entries_index is not zero then its value will be returned
> + * otherwise I915_MOCS_PTE's value is returned in this case.
>   */
>  static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table,
>  			  unsigned int index)
>  {
>  	if (index < table->size && table->table[index].used)
>  		return table->table[index].l3cc_value;
> -
> -	return table->table[I915_MOCS_PTE].l3cc_value;
> +	index = table->unused_entries_index ? : I915_MOCS_PTE;

Ditto.



Matt

> +	return table->table[index].l3cc_value;
>  }
>  
>  static u32 l3cc_combine(u16 low, u16 high)
> -- 
> 2.26.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

Re: [Intel-gfx] [PATCH V3 5/8] drm/i915/gt: Initialize unused MOCS entries with device specific values

[Siddiqui, Ayaz A]

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Thursday, September 2, 2021 5:15 AM
> To: Siddiqui, Ayaz A <ayaz.siddiqui@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH V3 5/8] drm/i915/gt: Initialize unused MOCS
> entries with device specific values
> 
> On Mon, Aug 30, 2021 at 09:52:37PM +0530, Ayaz A Siddiqui wrote:
> > Historically we've initialized all undefined/reserved entries in a
> > platform's MOCS table to the contents of table entry #1 (i.e.,
> > I915_MOCS_PTE).
> > Going forward, we can't assume that table entry #1 will always contain
> > suitable values to use for undefined/reserved table indices. We'll
> > allow a platform-specific table index to be selected at table
> > initialization time in these cases.
> >
> > This new mechanism to select L3 WB entry will be applicable for all
> > the Gen12+ platforms except TGL and RKL.
> >
> > Since TGL and RLK are already in production so their mocs settings are
> > intact to avoid ABI break.
> >
> > Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_mocs.c | 41
> > +++++++++++++++-------------
> >  1 file changed, 22 insertions(+), 19 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
> > b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > index 82eafa8d22453..a97cc08e5a395 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > @@ -25,6 +25,7 @@ struct drm_i915_mocs_table {
> >  	unsigned int n_entries;
> >  	const struct drm_i915_mocs_entry *table;
> >  	u8 uc_index;
> > +	u8 unused_entries_index;
> >  };
> >
> >  enum register_type {
> > @@ -113,18 +114,25 @@ struct drm_i915_aux_table {
> >   *
> >   * Entries not part of the following tables are undefined as far as
> >   * userspace is concerned and shouldn't be relied upon.  For Gen < 12
> > - * they will be initialized to PTE. Gen >= 12 onwards don't have a
> > setting for
> > - * PTE and will be initialized to an invalid value.
> > + * they will be initialized to PTE. Gen >= 12 don't have a setting
> > + for
> > + * PTE and those platforms except TGL/RKL will be initialized L3 WB
> > + to
> > + * catch accidental use of reserved and unused mocs indexes.
> >   *
> >   * The last few entries are reserved by the hardware. For ICL+ they
> >   * should be initialized according to bspec and never used, for older
> >   * platforms they should never be written to.
> >   *
> > - * NOTE: These tables are part of bspec and defined as part of
> > hardware
> > + * NOTE1: These tables are part of bspec and defined as part of
> > + hardware
> >   *       interface for ICL+. For older platforms, they are part of kernel
> >   *       ABI. It is expected that, for specific hardware platform, existing
> >   *       entries will remain constant and the table will only be updated by
> >   *       adding new entries, filling unused positions.
> > + *
> > + * NOTE2: For GEN >= 12 except TGL and RKL, reserved and unspecified
> MOCS
> > + *       indices have been set to L3 WB. These reserved entries should never
> > + *       be used, they may be changed to low performant variants with
> better
> > + *       coherency in the future if more entries are needed.
> > + *       For TGL/RKL, all the unspecified MOCS indexes are mapped to L3 UC.
> >   */
> >  #define GEN9_MOCS_ENTRIES \
> >  	MOCS_ENTRY(I915_MOCS_UNCACHED, \
> > @@ -307,17 +315,9 @@ static const struct drm_i915_mocs_entry
> > icl_mocs_table[] = {  };
> >
> >  static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
> > -	/* Error */
> > -	MOCS_ENTRY(0, 0, L3_0_DIRECT),
> >
> >  	/* UC */
> >  	MOCS_ENTRY(1, 0, L3_1_UC),
> > -
> > -	/* Reserved */
> > -	MOCS_ENTRY(2, 0, L3_0_DIRECT),
> > -	MOCS_ENTRY(3, 0, L3_0_DIRECT),
> > -	MOCS_ENTRY(4, 0, L3_0_DIRECT),
> > -
> >  	/* WB - L3 */
> >  	MOCS_ENTRY(5, 0, L3_3_WB),
> >  	/* WB - L3 50% */
> > @@ -469,6 +469,7 @@ static unsigned int get_mocs_settings(const struct
> drm_i915_private *i915,
> >  		table->table = dg1_mocs_table;
> >  		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> >  		table->uc_index = 1;
> > +		table->unused_entries_index = 5;
> >  	} else if (GRAPHICS_VER(i915) >= 12) {
> >  		table->size  = ARRAY_SIZE(tgl_mocs_table);
> >  		table->table = tgl_mocs_table;
> 
> Should we add
> 
>         table->unused_entries_index = 1;
> 
> to the rest of the platforms here since that's what we're doing in
> get_entry_l3cc() anyway?
> 
> Also I think we can rely on that to avoid the need to add a new MOCS table
> for ADL in the next patch; we can just use the same table but set a different
> unused_entries_index.  E.g.,
> 
>         } else if (IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) {
>                 ...
>                 /* UC: Can't be changed now for ABI reasons */
>                 table->unused_entries_index = 1;
>         } else if (GRAPHICS_VER(i915) >= 12) {
>                 ...
>                 /* L3 */
>                 table->unused_entries_index = 2;
>         } else if (GRAPHICS_VER(i915) == 11) {
>                 ...
>                 table->unused_entries_index = 1;
>         ...
> 
	} else if (GRAPHICS_VER(i915) >= 12) {
		table->size  = ARRAY_SIZE(tgl_mocs_table);
		table->table = tgl_mocs_table;
		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
		table->uc_index = 3;
		if (!IS_TIGERLAKE(i915) || !IS_ROCKETLAKE(i915))
			table->unused_entries_index = 2;
	}
I 'm thinking to add like this so that there is no change for gen11/Gen9  and TGL/RKL flow.
> 
> > @@ -600,16 +601,17 @@ int apply_mocs_aux_regs_ctx(struct
> i915_request
> > *rq)  }
> >
> >  /*
> > - * Get control_value from MOCS entry taking into account when it's not
> used:
> > - * I915_MOCS_PTE's value is returned in this case.
> > + * Get control_value from MOCS entry taking into account when it's
> > + not used
> > + * then if unused_entries_index is non-zero then its value will be
> > + returned
> > + * otherwise I915_MOCS_PTE's value is returned in this case.
> >   */
> >  static u32 get_entry_control(const struct drm_i915_mocs_table *table,
> >  			     unsigned int index)
> >  {
> >  	if (index < table->size && table->table[index].used)
> >  		return table->table[index].control_value;
> > -
> > -	return table->table[I915_MOCS_PTE].control_value;
> > +	index = table->unused_entries_index ? : I915_MOCS_PTE;
> 
> As noted above, I'd rather see us do this right in the MOCS settings setup.
> Then we'd probably just want a
> drm_WARN_ON(!table->unused_entries_index) to make sure we don't
> forget to explicitly set it for any platforms.
If we have to add a warn on for table->unused_entries_index,
The we should add unused_entries_index when we should add this for all table
and change code like this 
-	return table->table[I915_MOCS_PTE].control_value;
+	return table->table[table->unused_entries_index].control_value;

What ever you suggest I'll take care
-Ayaz

> >  }
> >
> >  #define for_each_mocs(mocs, t, i) \
> > @@ -650,16 +652,17 @@ static void init_mocs_table(struct
> > intel_engine_cs *engine,  }
> >
> >  /*
> > - * Get l3cc_value from MOCS entry taking into account when it's not used:
> > - * I915_MOCS_PTE's value is returned in this case.
> > + * Get l3cc_value from MOCS entry taking into account when it's not
> > + used
> > + * then if unused_entries_index is not zero then its value will be
> > + returned
> > + * otherwise I915_MOCS_PTE's value is returned in this case.
> >   */
> >  static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table,
> >  			  unsigned int index)
> >  {
> >  	if (index < table->size && table->table[index].used)
> >  		return table->table[index].l3cc_value;
> > -
> > -	return table->table[I915_MOCS_PTE].l3cc_value;
> > +	index = table->unused_entries_index ? : I915_MOCS_PTE;
> 
> Ditto.
> 
> 
> 
> Matt
> 
> > +	return table->table[index].l3cc_value;
> >  }
> >
> >  static u32 l3cc_combine(u16 low, u16 high)
> > --
> > 2.26.2
> >
> 
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795

[Intel-gfx] [PATCH V3 6/8] drm/i95/adl: Define MOCS table for Alderlake

[Ayaz A Siddiqui]

In order to program unused and reserved mocs entries to L3_WB,
we need to create a separate mocs table for alderlake.

This patch will also covers wa_1608975824.

Cc: Chris P Wilson <chris.p.wilson@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_mocs.c | 41 +++++++++++++++++++++++++++-
 1 file changed, 40 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index a97cc08e5a395..577a78dfedf99 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -339,6 +339,39 @@ static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
 	MOCS_ENTRY(63, 0, L3_1_UC),
 };
 
+static const struct drm_i915_mocs_entry adl_mocs_table[] = {
+	/* wa_1608975824 */
+	MOCS_ENTRY(0,
+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+		   L3_3_WB),
+
+	GEN11_MOCS_ENTRIES,
+	/* Implicitly enable L1 - HDC:L1 + L3 + LLC */
+	MOCS_ENTRY(48,
+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+		   L3_3_WB),
+	/* Implicitly enable L1 - HDC:L1 + L3 */
+	MOCS_ENTRY(49,
+		   LE_1_UC | LE_TC_1_LLC,
+		   L3_3_WB),
+	/* Implicitly enable L1 - HDC:L1 + LLC */
+	MOCS_ENTRY(50,
+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+		   L3_1_UC),
+	/* Implicitly enable L1 - HDC:L1 */
+	MOCS_ENTRY(51,
+		   LE_1_UC | LE_TC_1_LLC,
+		   L3_1_UC),
+	/* HW Special Case (CCS) */
+	MOCS_ENTRY(60,
+		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
+		   L3_1_UC),
+	/* HW Special Case (Displayable) */
+	MOCS_ENTRY(61,
+		   LE_1_UC | LE_TC_1_LLC,
+		   L3_3_WB),
+};
+
 enum {
 	HAS_GLOBAL_MOCS = BIT(0),
 	HAS_ENGINE_MOCS = BIT(1),
@@ -464,7 +497,13 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
 
 	memset(table, 0, sizeof(struct drm_i915_mocs_table));
 
-	if (IS_DG1(i915)) {
+	if (IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) {
+		table->size = ARRAY_SIZE(adl_mocs_table);
+		table->table = adl_mocs_table;
+		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
+		table->uc_index = 3;
+		table->unused_entries_index = 2;
+	} else if (IS_DG1(i915)) {
 		table->size = ARRAY_SIZE(dg1_mocs_table);
 		table->table = dg1_mocs_table;
 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
-- 
2.26.2

Re: [Intel-gfx] [PATCH V3 6/8] drm/i95/adl: Define MOCS table for Alderlake

[Matt Roper]

On Mon, Aug 30, 2021 at 09:52:38PM +0530, Ayaz A Siddiqui wrote:
> In order to program unused and reserved mocs entries to L3_WB,
> we need to create a separate mocs table for alderlake.

As noted on the previous patch, I don't think we need a separate table
if we just make sure we initialize unused_entries_index differently for
TGL/RKL vs other gen12 platforms (entry 2 vs entry 1).

> 
> This patch will also covers wa_1608975824.
> 
> Cc: Chris P Wilson <chris.p.wilson@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> 
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_mocs.c | 41 +++++++++++++++++++++++++++-
>  1 file changed, 40 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index a97cc08e5a395..577a78dfedf99 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -339,6 +339,39 @@ static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
>  	MOCS_ENTRY(63, 0, L3_1_UC),
>  };
>  
> +static const struct drm_i915_mocs_entry adl_mocs_table[] = {
> +	/* wa_1608975824 */
> +	MOCS_ENTRY(0,
> +		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
> +		   L3_3_WB),

Even if we want to keep the separate table for some reason, I believe
this is the same as entry 2, right (which is defined inside
GEN11_MOCS_ENTRIES)?  So if we just omit it, it will be handled just
like any other undefined entry.


Matt

> +
> +	GEN11_MOCS_ENTRIES,
> +	/* Implicitly enable L1 - HDC:L1 + L3 + LLC */
> +	MOCS_ENTRY(48,
> +		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
> +		   L3_3_WB),
> +	/* Implicitly enable L1 - HDC:L1 + L3 */
> +	MOCS_ENTRY(49,
> +		   LE_1_UC | LE_TC_1_LLC,
> +		   L3_3_WB),
> +	/* Implicitly enable L1 - HDC:L1 + LLC */
> +	MOCS_ENTRY(50,
> +		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
> +		   L3_1_UC),
> +	/* Implicitly enable L1 - HDC:L1 */
> +	MOCS_ENTRY(51,
> +		   LE_1_UC | LE_TC_1_LLC,
> +		   L3_1_UC),
> +	/* HW Special Case (CCS) */
> +	MOCS_ENTRY(60,
> +		   LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
> +		   L3_1_UC),
> +	/* HW Special Case (Displayable) */
> +	MOCS_ENTRY(61,
> +		   LE_1_UC | LE_TC_1_LLC,
> +		   L3_3_WB),
> +};
> +
>  enum {
>  	HAS_GLOBAL_MOCS = BIT(0),
>  	HAS_ENGINE_MOCS = BIT(1),
> @@ -464,7 +497,13 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
>  
>  	memset(table, 0, sizeof(struct drm_i915_mocs_table));
>  
> -	if (IS_DG1(i915)) {
> +	if (IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) {
> +		table->size = ARRAY_SIZE(adl_mocs_table);
> +		table->table = adl_mocs_table;
> +		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> +		table->uc_index = 3;
> +		table->unused_entries_index = 2;
> +	} else if (IS_DG1(i915)) {
>  		table->size = ARRAY_SIZE(dg1_mocs_table);
>  		table->table = dg1_mocs_table;
>  		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> -- 
> 2.26.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

[Intel-gfx] [PATCH V3 7/8] drm/i915/gt: Initialize L3CC table in mocs init

[Ayaz A Siddiqui]

From: Sreedhar Telukuntla <sreedhar.telukuntla@intel.com>

Initialize the L3CC table as part of mocs initalization to program
LNCFCMOCSx registers, so that the mocs settings are available for
selection for subsequent memory transactions in driver load path.

Signed-off-by: Sreedhar Telukuntla <sreedhar.telukuntla@intel.com>
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_mocs.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 577a78dfedf99..405374f1d8ed2 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -717,10 +717,9 @@ static u32 l3cc_combine(u16 low, u16 high)
 	     0; \
 	     i++)
 
-static void init_l3cc_table(struct intel_engine_cs *engine,
+static void init_l3cc_table(struct intel_uncore *uncore,
 			    const struct drm_i915_mocs_table *table)
 {
-	struct intel_uncore *uncore = engine->uncore;
 	unsigned int i;
 	u32 l3cc;
 
@@ -746,7 +745,7 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
 		init_mocs_table(engine, &table);
 
 	if (flags & HAS_RENDER_L3CC && engine->class == RENDER_CLASS)
-		init_l3cc_table(engine, &table);
+		init_l3cc_table(engine->uncore, &table);
 
 	aux = build_aux_regs(engine, &table);
 	apply_aux_regs_engine(engine, aux);
@@ -776,6 +775,14 @@ void intel_mocs_init(struct intel_gt *gt)
 	if (flags & HAS_GLOBAL_MOCS)
 		__init_mocs_table(gt->uncore, &table, global_mocs_offset());
 	set_mocs_index(gt, &table);
+
+	/*
+	 * Initialize the L3CC table as part of mocs initalization to make
+	 * sure the LNCFCMOCSx registers are programmed for the subsequent
+	 * memory transactions including guc transactions
+	 */
+	if (flags & HAS_RENDER_L3CC)
+		init_l3cc_table(gt->uncore, &table);
 }
 
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
-- 
2.26.2

Re: [Intel-gfx] [PATCH V3 7/8] drm/i915/gt: Initialize L3CC table in mocs init

[Matt Roper]

On Mon, Aug 30, 2021 at 09:52:39PM +0530, Ayaz A Siddiqui wrote:
> From: Sreedhar Telukuntla <sreedhar.telukuntla@intel.com>
> 
> Initialize the L3CC table as part of mocs initalization to program
> LNCFCMOCSx registers, so that the mocs settings are available for
> selection for subsequent memory transactions in driver load path.
> 
> Signed-off-by: Sreedhar Telukuntla <sreedhar.telukuntla@intel.com>
> Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_mocs.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 577a78dfedf99..405374f1d8ed2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -717,10 +717,9 @@ static u32 l3cc_combine(u16 low, u16 high)
>  	     0; \
>  	     i++)
>  
> -static void init_l3cc_table(struct intel_engine_cs *engine,
> +static void init_l3cc_table(struct intel_uncore *uncore,
>  			    const struct drm_i915_mocs_table *table)
>  {
> -	struct intel_uncore *uncore = engine->uncore;
>  	unsigned int i;
>  	u32 l3cc;
>  
> @@ -746,7 +745,7 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
>  		init_mocs_table(engine, &table);
>  
>  	if (flags & HAS_RENDER_L3CC && engine->class == RENDER_CLASS)
> -		init_l3cc_table(engine, &table);
> +		init_l3cc_table(engine->uncore, &table);

Can you clarify in the commit message why we still need to re-call this
in intel_mocs_init_engine() if we've already done it in
intel_mocs_init()?  I'm assuming it's because we lose these register
values on engine resets, so in the execlist path we need to make sure
they get re-applied after the reset?


Matt

>  
>  	aux = build_aux_regs(engine, &table);
>  	apply_aux_regs_engine(engine, aux);
> @@ -776,6 +775,14 @@ void intel_mocs_init(struct intel_gt *gt)
>  	if (flags & HAS_GLOBAL_MOCS)
>  		__init_mocs_table(gt->uncore, &table, global_mocs_offset());
>  	set_mocs_index(gt, &table);
> +
> +	/*
> +	 * Initialize the L3CC table as part of mocs initalization to make
> +	 * sure the LNCFCMOCSx registers are programmed for the subsequent
> +	 * memory transactions including guc transactions
> +	 */
> +	if (flags & HAS_RENDER_L3CC)
> +		init_l3cc_table(gt->uncore, &table);
>  }
>  
>  #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> -- 
> 2.26.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

Re: [Intel-gfx] [PATCH V3 7/8] drm/i915/gt: Initialize L3CC table in mocs init

[Siddiqui, Ayaz A]

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Thursday, September 2, 2021 5:47 AM
> To: Siddiqui, Ayaz A <ayaz.siddiqui@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Telukuntla, Sreedhar
> <sreedhar.telukuntla@intel.com>
> Subject: Re: [Intel-gfx] [PATCH V3 7/8] drm/i915/gt: Initialize L3CC table in
> mocs init
> 
> On Mon, Aug 30, 2021 at 09:52:39PM +0530, Ayaz A Siddiqui wrote:
> > From: Sreedhar Telukuntla <sreedhar.telukuntla@intel.com>
> >
> > Initialize the L3CC table as part of mocs initalization to program
> > LNCFCMOCSx registers, so that the mocs settings are available for
> > selection for subsequent memory transactions in driver load path.


> >
> > Signed-off-by: Sreedhar Telukuntla <sreedhar.telukuntla@intel.com>
> > Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_mocs.c | 13 ++++++++++---
> >  1 file changed, 10 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
> > b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > index 577a78dfedf99..405374f1d8ed2 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > @@ -717,10 +717,9 @@ static u32 l3cc_combine(u16 low, u16 high)
> >  	     0; \
> >  	     i++)
> >
> > -static void init_l3cc_table(struct intel_engine_cs *engine,
> > +static void init_l3cc_table(struct intel_uncore *uncore,
> >  			    const struct drm_i915_mocs_table *table)  {
> > -	struct intel_uncore *uncore = engine->uncore;
> >  	unsigned int i;
> >  	u32 l3cc;
> >
> > @@ -746,7 +745,7 @@ void intel_mocs_init_engine(struct intel_engine_cs
> *engine)
> >  		init_mocs_table(engine, &table);
> >
> >  	if (flags & HAS_RENDER_L3CC && engine->class == RENDER_CLASS)
> > -		init_l3cc_table(engine, &table);
> > +		init_l3cc_table(engine->uncore, &table);
> 
> Can you clarify in the commit message why we still need to re-call this in
> intel_mocs_init_engine() if we've already done it in intel_mocs_init()?  I'm
> assuming it's because we lose these register values on engine resets, so in
> the execlist path we need to make sure they get re-applied after the reset?
> 
> 
> Matt
Yes for platform like DG1/TGL we are loosing the MOCS programming during engine reset.
While on XEHP-SDV , Programming of L3CC are retain during engine reset also since
There is no Renderer engine in XEHP-SVD so MOCS will not be programmed, that why we need to add
This patch, We have not tested on stickiness DG2 yet, but I do not see any harm if we program it again
This patch will be required for XEHP-SVD.  If there are any other concern then we may ignore this patch
as of now and continue with other patches of series.  I'll modify commit message with   more information.
-Ayaz
 
 
> 
> >
> >  	aux = build_aux_regs(engine, &table);
> >  	apply_aux_regs_engine(engine, aux);
> > @@ -776,6 +775,14 @@ void intel_mocs_init(struct intel_gt *gt)
> >  	if (flags & HAS_GLOBAL_MOCS)
> >  		__init_mocs_table(gt->uncore, &table,
> global_mocs_offset());
> >  	set_mocs_index(gt, &table);
> > +
> > +	/*
> > +	 * Initialize the L3CC table as part of mocs initalization to make
> > +	 * sure the LNCFCMOCSx registers are programmed for the
> subsequent
> > +	 * memory transactions including guc transactions
> > +	 */
> > +	if (flags & HAS_RENDER_L3CC)
> > +		init_l3cc_table(gt->uncore, &table);
> >  }
> >
> >  #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> > --
> > 2.26.2
> >
> 
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795

[Intel-gfx] [PATCH V3 8/8] drm/i915/selftest: Remove Renderer class check for l3cc table read

[Ayaz A Siddiqui]

Some platform like XEHPSVD does not have Renderer engines. since
read_l3cc_table() is guarded by renderer class due to that check
of L3CC table was not being performed on those platforms.

Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
---
 drivers/gpu/drm/i915/gt/selftest_mocs.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
index 2b0207dfbf21c..05f5c57f82699 100644
--- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
@@ -281,7 +281,7 @@ static int check_mocs_engine(struct live_mocs *arg,
 	offset = i915_ggtt_offset(vma);
 	if (!err)
 		err = read_mocs_table(rq, arg->mocs, &offset);
-	if (!err && ce->engine->class == RENDER_CLASS)
+	if (!err)
 		err = read_l3cc_table(rq, arg->l3cc, &offset);
 	if (!err)
 		err = read_aux_regs(rq, aux, &offset);
@@ -296,7 +296,7 @@ static int check_mocs_engine(struct live_mocs *arg,
 	vaddr = arg->vaddr;
 	if (!err)
 		err = check_mocs_table(ce->engine, arg->mocs, &vaddr);
-	if (!err && ce->engine->class == RENDER_CLASS)
+	if (!err)
 		err = check_l3cc_table(ce->engine, arg->l3cc, &vaddr);
 	if (!err)
 		err = check_aux_regs(ce->engine, aux, &vaddr);
-- 
2.26.2

Re: [Intel-gfx] [PATCH V3 8/8] drm/i915/selftest: Remove Renderer class check for l3cc table read

[Matt Roper]

On Mon, Aug 30, 2021 at 09:52:40PM +0530, Ayaz A Siddiqui wrote:
> Some platform like XEHPSVD does not have Renderer engines. since
> read_l3cc_table() is guarded by renderer class due to that check
> of L3CC table was not being performed on those platforms.
> 
> Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/selftest_mocs.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> index 2b0207dfbf21c..05f5c57f82699 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> @@ -281,7 +281,7 @@ static int check_mocs_engine(struct live_mocs *arg,
>  	offset = i915_ggtt_offset(vma);
>  	if (!err)
>  		err = read_mocs_table(rq, arg->mocs, &offset);
> -	if (!err && ce->engine->class == RENDER_CLASS)
> +	if (!err)

This is going to make us read & verify the same values several times
(once per engine) which doesn't seem to provide much benefit.  But I
guess we do the same thing for global MOCS and nobody seems to care
about the duplicated effort there either.

I guess it doesn't really matter.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>


Matt

>  		err = read_l3cc_table(rq, arg->l3cc, &offset);
>  	if (!err)
>  		err = read_aux_regs(rq, aux, &offset);
> @@ -296,7 +296,7 @@ static int check_mocs_engine(struct live_mocs *arg,
>  	vaddr = arg->vaddr;
>  	if (!err)
>  		err = check_mocs_table(ce->engine, arg->mocs, &vaddr);
> -	if (!err && ce->engine->class == RENDER_CLASS)
> +	if (!err)
>  		err = check_l3cc_table(ce->engine, arg->l3cc, &vaddr);
>  	if (!err)
>  		err = check_aux_regs(ce->engine, aux, &vaddr);
> -- 
> 2.26.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/gt: Initialize unused MOCS entries to L3_WB

[Patchwork]

== Series Details ==

Series: drm/i915/gt: Initialize unused MOCS entries to L3_WB
URL   : https://patchwork.freedesktop.org/series/94168/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1374:34:    expected struct i915_address_space *vm
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1374:34:    got struct i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1374:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:    expected struct i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:    got struct i915_address_space *
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:    expected struct i915_address_space *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:    got struct i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_mocs.c:561:5: warning: symbol 'get_ctx_reg_count' was not declared. Should it be static?
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+./include/linux/stddef.h:17:9: this was the original definition
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined
+/usr/lib/gcc/x86_64-linux-gnu/8/include/stddef.h:417:9: warning: preprocessor token offsetof redefined

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Initialize unused MOCS entries to L3_WB

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 6006 bytes --]

== Series Details ==

Series: drm/i915/gt: Initialize unused MOCS entries to L3_WB
URL   : https://patchwork.freedesktop.org/series/94168/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10537 -> Patchwork_20920
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/index.html

Known issues
------------

  Here are the changes found in Patchwork_20920 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@cs-gfx:
    - fi-rkl-guc:         NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/fi-rkl-guc/igt@amdgpu/amd_basic@cs-gfx.html

  * igt@amdgpu/amd_cs_nop@sync-fork-compute0:
    - fi-snb-2600:        NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html

  * igt@gem_huc_copy@huc-copy:
    - fi-skl-6700k2:      NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/fi-skl-6700k2/igt@gem_huc_copy@huc-copy.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-rkl-guc:         [PASS][4] -> [SKIP][5] ([fdo#109308])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/fi-rkl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/fi-rkl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@kms_chamelium@dp-hpd-fast:
    - fi-skl-6700k2:      NOTRUN -> [SKIP][6] ([fdo#109271]) +5 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/fi-skl-6700k2/igt@kms_chamelium@dp-hpd-fast.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-skl-6700k2:      NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#533])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/fi-skl-6700k2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-skl-6700k2:      NOTRUN -> [INCOMPLETE][8] ([i915#146] / [i915#198])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/fi-skl-6700k2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s0:
    - fi-skl-6700k2:      [DMESG-WARN][9] ([i915#1602]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/fi-skl-6700k2/igt@gem_exec_suspend@basic-s0.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/fi-skl-6700k2/igt@gem_exec_suspend@basic-s0.html

  * igt@i915_selftest@live@gt_heartbeat:
    - {fi-tgl-dsi}:       [DMESG-FAIL][11] ([i915#541]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@hangcheck:
    - fi-snb-2600:        [INCOMPLETE][13] ([i915#3921]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/fi-snb-2600/igt@i915_selftest@live@hangcheck.html

  
#### Warnings ####

  * igt@i915_selftest@live@workarounds:
    - fi-rkl-guc:         [DMESG-FAIL][15] ([i915#3928]) -> [DMESG-WARN][16] ([i915#3967])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/fi-rkl-guc/igt@i915_selftest@live@workarounds.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/fi-rkl-guc/igt@i915_selftest@live@workarounds.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
  [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#3928]: https://gitlab.freedesktop.org/drm/intel/issues/3928
  [i915#3967]: https://gitlab.freedesktop.org/drm/intel/issues/3967
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541


Participating hosts (44 -> 36)
------------------------------

  Missing    (8): fi-ilk-m540 bat-adls-5 bat-dg1-6 bat-dg1-5 fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus bat-jsl-1 


Build changes
-------------

  * Linux: CI_DRM_10537 -> Patchwork_20920

  CI-20190529: 20190529
  CI_DRM_10537: 81c643b64b3cb96bcfb72ae1a151c5cb728781c9 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6191: e9292b533691784f46eeb9bae522ca7a8710c920 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20920: 10702a29bc71f98b930ac13551dd19a844c0e453 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

10702a29bc71 drm/i915/selftest: Remove Renderer class check for l3cc table read
aa2861a635ae drm/i915/gt: Initialize L3CC table in mocs init
ed5842025e29 drm/i95/adl: Define MOCS table for Alderlake
90238e2e5d65 drm/i915/gt: Initialize unused MOCS entries with device specific values
14301d392964 drm/i915/gt: Set BLIT_CCTL reg to un-cached
4f46aa839de7 drm/i915/gt: Set CMD_CCTL to UC for Gen12 Onward
dd57a362b68f drm/i915/gt: Add support of mocs auxiliary registers programming
44e8eac78355 drm/i915/gt: Add support of mocs propagation

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/index.html

[-- Attachment #2: Type: text/html, Size: 7122 bytes --]

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Initialize unused MOCS entries to L3_WB

[Patchwork]

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== Series Details ==

Series: drm/i915/gt: Initialize unused MOCS entries to L3_WB
URL   : https://patchwork.freedesktop.org/series/94168/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10537_full -> Patchwork_20920_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_20920_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@drm_import_export@flink:
    - shard-kbl:          [PASS][1] -> [INCOMPLETE][2] ([i915#2369])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-kbl1/igt@drm_import_export@flink.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-kbl3/igt@drm_import_export@flink.html

  * igt@gem_create@create-massive:
    - shard-snb:          NOTRUN -> [DMESG-WARN][3] ([i915#3002])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-snb7/igt@gem_create@create-massive.html

  * igt@gem_ctx_persistence@engines-queued:
    - shard-snb:          NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099]) +3 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-snb6/igt@gem_ctx_persistence@engines-queued.html

  * igt@gem_eio@unwedge-stress:
    - shard-tglb:         [PASS][5] -> [TIMEOUT][6] ([i915#2369] / [i915#3063] / [i915#3648])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-tglb8/igt@gem_eio@unwedge-stress.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-tglb6/igt@gem_eio@unwedge-stress.html
    - shard-snb:          NOTRUN -> [FAIL][7] ([i915#3354])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-snb7/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-kbl:          [PASS][8] -> [FAIL][9] ([i915#2846])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-kbl7/igt@gem_exec_fair@basic-deadline.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-kbl7/igt@gem_exec_fair@basic-deadline.html
    - shard-apl:          NOTRUN -> [FAIL][10] ([i915#2846])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-apl2/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
    - shard-tglb:         [PASS][11] -> [FAIL][12] ([i915#2842]) +2 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-tglb6/igt@gem_exec_fair@basic-none-vip@rcs0.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-tglb1/igt@gem_exec_fair@basic-none-vip@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
    - shard-kbl:          [PASS][13] -> [FAIL][14] ([i915#2842])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-kbl2/igt@gem_exec_fair@basic-pace@vcs0.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-iclb:         NOTRUN -> [FAIL][15] ([i915#2842])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-iclb:         [PASS][16] -> [FAIL][17] ([i915#2842])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-iclb8/igt@gem_exec_fair@basic-pace@vecs0.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-iclb2/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-glk:          [PASS][18] -> [FAIL][19] ([i915#2842]) +1 similar issue
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-glk3/igt@gem_exec_fair@basic-throttle@rcs0.html
    - shard-iclb:         [PASS][20] -> [FAIL][21] ([i915#2849])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-iclb4/igt@gem_exec_fair@basic-throttle@rcs0.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs:
    - shard-iclb:         NOTRUN -> [SKIP][22] ([i915#768])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-iclb4/igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs.html

  * igt@gem_userptr_blits@input-checking:
    - shard-apl:          NOTRUN -> [DMESG-WARN][23] ([i915#3002])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-apl7/igt@gem_userptr_blits@input-checking.html

  * igt@i915_pm_rpm@gem-mmap-type@fixed:
    - shard-iclb:         NOTRUN -> [SKIP][24] ([i915#3976])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-iclb4/igt@i915_pm_rpm@gem-mmap-type@fixed.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-90:
    - shard-iclb:         NOTRUN -> [SKIP][25] ([fdo#110725] / [fdo#111614])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-iclb4/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-skl:          NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3777])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-skl7/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-skl:          NOTRUN -> [FAIL][27] ([i915#3722])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-skl3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-0:
    - shard-glk:          [PASS][28] -> [DMESG-WARN][29] ([i915#118] / [i915#95])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-glk6/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-glk5/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-apl:          NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3777])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-apl6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-apl:          NOTRUN -> [SKIP][31] ([fdo#109271]) +170 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-apl6/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
    - shard-kbl:          NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3886]) +1 similar issue
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-kbl2/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3886]) +4 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-apl8/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
    - shard-iclb:         NOTRUN -> [SKIP][34] ([fdo#109278] / [i915#3886])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-iclb4/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-crc-primary-rotation-180-yf_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][35] ([i915#3689]) +1 similar issue
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-tglb6/igt@kms_ccs@pipe-b-crc-primary-rotation-180-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][36] ([i915#3689] / [i915#3886])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-tglb7/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
    - shard-skl:          NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3886]) +3 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-skl7/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium@dp-mode-timings:
    - shard-apl:          NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) +10 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-apl6/igt@kms_chamelium@dp-mode-timings.html

  * igt@kms_chamelium@hdmi-hpd-storm:
    - shard-kbl:          NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +6 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-kbl4/igt@kms_chamelium@hdmi-hpd-storm.html

  * igt@kms_chamelium@vga-hpd-for-each-pipe:
    - shard-skl:          NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +9 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-skl7/igt@kms_chamelium@vga-hpd-for-each-pipe.html

  * igt@kms_color_chamelium@pipe-b-ctm-max:
    - shard-snb:          NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +16 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-snb5/igt@kms_color_chamelium@pipe-b-ctm-max.html

  * igt@kms_color_chamelium@pipe-c-degamma:
    - shard-tglb:         NOTRUN -> [SKIP][42] ([fdo#109284] / [fdo#111827])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-tglb7/igt@kms_color_chamelium@pipe-c-degamma.html

  * igt@kms_content_protection@content_type_change:
    - shard-tglb:         NOTRUN -> [SKIP][43] ([fdo#111828])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-tglb6/igt@kms_content_protection@content_type_change.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-iclb:         NOTRUN -> [SKIP][44] ([i915#3116])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-iclb4/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@uevent:
    - shard-apl:          NOTRUN -> [FAIL][45] ([i915#2105])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-apl6/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@pipe-b-cursor-suspend:
    - shard-apl:          [PASS][46] -> [DMESG-WARN][47] ([i915#180])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-apl8/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-apl6/igt@kms_cursor_crc@pipe-b-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-c-cursor-512x170-random:
    - shard-iclb:         NOTRUN -> [SKIP][48] ([fdo#109278] / [fdo#109279])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-iclb4/igt@kms_cursor_crc@pipe-c-cursor-512x170-random.html

  * igt@kms_cursor_crc@pipe-d-cursor-256x85-random:
    - shard-iclb:         NOTRUN -> [SKIP][49] ([fdo#109278]) +4 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-iclb4/igt@kms_cursor_crc@pipe-d-cursor-256x85-random.html

  * igt@kms_cursor_legacy@pipe-d-single-bo:
    - shard-skl:          NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#533])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-skl3/igt@kms_cursor_legacy@pipe-d-single-bo.html

  * igt@kms_dsc@basic-dsc-enable:
    - shard-iclb:         NOTRUN -> [SKIP][51] ([i915#3840])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-iclb4/igt@kms_dsc@basic-dsc-enable.html

  * igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
    - shard-iclb:         NOTRUN -> [SKIP][52] ([fdo#109274])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-iclb4/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
    - shard-skl:          [PASS][53] -> [FAIL][54] ([i915#79])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
    - shard-skl:          [PASS][55] -> [FAIL][56] ([i915#2122]) +1 similar issue
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt:
    - shard-skl:          NOTRUN -> [SKIP][57] ([fdo#109271]) +88 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-skl3/igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt:
    - shard-snb:          NOTRUN -> [SKIP][58] ([fdo#109271]) +296 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-kbl:          [PASS][59] -> [DMESG-WARN][60] ([i915#180]) +2 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-pwrite:
    - shard-iclb:         NOTRUN -> [SKIP][61] ([fdo#109280]) +1 similar issue
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-onoff:
    - shard-tglb:         NOTRUN -> [SKIP][62] ([fdo#111825]) +2 similar issues
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-tglb7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-onoff.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [PASS][63] -> [FAIL][64] ([i915#1188])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-skl5/igt@kms_hdr@bpc-switch-dpms.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - shard-apl:          NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#533]) +1 similar issue
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-apl2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
    - shard-kbl:          NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#533])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-kbl2/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
    - shard-apl:          NOTRUN -> [FAIL][67] ([fdo#108145] / [i915#265]) +2 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-apl6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
    - shard-skl:          NOTRUN -> [FAIL][68] ([i915#265]) +1 similar issue
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html

  * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
    - shard-kbl:          NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#2733])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-kbl2/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3:
    - shard-tglb:         NOTRUN -> [SKIP][70] ([i915#2920])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-tglb6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
    - shard-apl:          NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#658]) +2 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-apl7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1:
    - shard-skl:          NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#658]) +2 similar issues
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-skl7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html

  * igt@kms_psr2_su@page_flip:
    - shard-kbl:          NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#658])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-kbl4/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@psr2_primary_mmap_gtt:
    - shard-iclb:         [PASS][74] -> [SKIP][75] ([fdo#109441]) +1 similar issue
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-iclb5/igt@kms_psr@psr2_primary_mmap_gtt.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [PASS][76] -> [DMESG-WARN][77] ([i915#180] / [i915#295])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@kms_writeback@writeback-invalid-parameters:
    - shard-skl:          NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#2437])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-skl3/igt@kms_writeback@writeback-invalid-parameters.html

  * igt@perf@blocking:
    - shard-skl:          [PASS][79] -> [FAIL][80] ([i915#1542])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-skl7/igt@perf@blocking.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-skl10/igt@perf@blocking.html

  * igt@prime_nv_api@i915_nv_double_import:
    - shard-tglb:         NOTRUN -> [SKIP][81] ([fdo#109291])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-tglb6/igt@prime_nv_api@i915_nv_double_import.html

  * igt@prime_nv_pcopy@test1_micro:
    - shard-kbl:          NOTRUN -> [SKIP][82] ([fdo#109271]) +44 similar issues
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-kbl1/igt@prime_nv_pcopy@test1_micro.html

  * igt@sysfs_clients@create:
    - shard-skl:          NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#2994])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-skl3/igt@sysfs_clients@create.html

  * igt@sysfs_clients@fair-7:
    - shard-apl:          NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#2994]) +2 similar issues
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-apl6/igt@sysfs_clients@fair-7.html

  * igt@sysfs_clients@recycle:
    - shard-kbl:          NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#2994])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-kbl2/igt@sysfs_clients@recycle.html

  
#### Possible fixes ####

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         [FAIL][86] ([i915#2842]) -> [PASS][87] +1 similar issue
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [SKIP][88] ([i915#2190]) -> [PASS][89]
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-tglb6/igt@gem_huc_copy@huc-copy.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-tglb7/igt@gem_huc_copy@huc-copy.html

  * igt@gem_mmap_gtt@cpuset-big-copy-xy:
    - shard-iclb:         [FAIL][90] ([i915#307]) -> [PASS][91]
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-iclb7/igt@gem_mmap_gtt@cpuset-big-copy-xy.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-iclb4/igt@gem_mmap_gtt@cpuset-big-copy-xy.html

  * igt@gem_mmap_gtt@cpuset-medium-copy-odd:
    - shard-iclb:         [FAIL][92] ([i915#2428]) -> [PASS][93] +1 similar issue
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-iclb3/igt@gem_mmap_gtt@cpuset-medium-copy-odd.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-iclb8/igt@gem_mmap_gtt@cpuset-medium-copy-odd.html

  * igt@i915_pm_rpm@gem-mmap-type@gtt:
    - shard-iclb:         [INCOMPLETE][94] -> [PASS][95]
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-iclb7/igt@i915_pm_rpm@gem-mmap-type@gtt.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-iclb4/igt@i915_pm_rpm@gem-mmap-type@gtt.html

  * igt@i915_suspend@forcewake:
    - shard-apl:          [DMESG-WARN][96] ([i915#180]) -> [PASS][97]
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-apl3/igt@i915_suspend@forcewake.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-apl8/igt@i915_suspend@forcewake.html

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-glk:          [FAIL][98] ([i915#2521]) -> [PASS][99]
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-glk4/igt@kms_async_flips@alternate-sync-async-flip.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-glk6/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_big_fb@linear-32bpp-rotate-0:
    - shard-glk:          [DMESG-WARN][100] ([i915#118] / [i915#95]) -> [PASS][101] +1 similar issue
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-glk1/igt@kms_big_fb@linear-32bpp-rotate-0.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-glk9/igt@kms_big_fb@linear-32bpp-rotate-0.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][102] ([i915#79]) -> [PASS][103]
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][104] ([i915#2122]) -> [PASS][105]
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-glk4/igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-glk6/igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-skl:          [FAIL][106] ([i915#79]) -> [PASS][107] +2 similar issues
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-skl:          [FAIL][108] ([i915#2122]) -> [PASS][109] +1 similar issue
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-skl8/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-skl2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-kbl:          [DMESG-WARN][110] ([i915#180]) -> [PASS][111] +2 similar issues
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_flip@flip-vs-suspend@c-dp1:
    - shard-kbl:          [INCOMPLETE][112] ([i915#636]) -> [PASS][113]
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-kbl2/igt@kms_flip@flip-vs-suspend@c-dp1.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-kbl4/igt@kms_flip@flip-vs-suspend@c-dp1.html

  * igt@sysfs_timeslice_duration@timeout@vecs0:
    - shard-iclb:         [FAIL][114] ([i915#1755]) -> [PASS][115]
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-iclb4/igt@sysfs_timeslice_duration@timeout@vecs0.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-iclb1/igt@sysfs_timeslice_duration@timeout@vecs0.html
    - shard-tglb:         [FAIL][116] ([i915#1755]) -> [PASS][117]
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-tglb6/igt@sysfs_timeslice_duration@timeout@vecs0.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-tglb1/igt@sysfs_timeslice_duration@timeout@vecs0.html

  
#### Warnings ####

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-iclb:         [WARN][118] ([i915#2684]) -> [WARN][119] ([i915#1804] / [i915#2684])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
    - shard-kbl:          [DMESG-WARN][120] ([i915#180]) -> [INCOMPLETE][121] ([i915#636])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3:
    - shard-iclb:         [SKIP][122] ([i915#658]) -> [SKIP][123] ([i915#2920])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-iclb8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
    - shard-iclb:         [SKIP][124] ([i915#2920]) -> [SKIP][125] ([i915#658]) +1 similar issue
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-iclb5/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129]) ([i915#180] / [i915#3002] / [i915#3363]) -> ([FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#2722] / [i915#3002] / [i915#3363] / [i915#602])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-kbl7/igt@runner@aborted.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-kbl3/igt@runner@aborted.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-kbl7/igt@runner@aborted.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-kbl7/igt@runner@aborted.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-kbl7/igt@runner@aborted.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-kbl7/igt@runner@aborted.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-kbl4/igt@runner@aborted.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-kbl3/igt@runner@aborted.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-kbl7/igt@runner@aborted.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-kbl7/igt@runner@aborted.html
    - shard-apl:          ([FAIL][136], [FAIL][137], [FAIL][138]) ([i915#180] / [i915#3002] / [i915#3363]) -> ([FAIL][139], [FAIL][140]) ([i915#1814] / [i915#3002] / [i915#3363])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-apl3/igt@runner@aborted.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-apl8/igt@runner@aborted.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10537/shard-apl6/igt@runner@aborted.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-apl7/igt@runner@aborted.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/shard-apl6/igt@runner@aborted.html

  
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#111828]: https://bugs.freedesktop.org/show_bug.cgi?id=111828
  [i915#1099]: https://gitlab.freedesktop.org/drm/inte

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20920/index.html

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