* [PATCH 00/14] Display Stream Compression (DSC) for AMD Navi
@ 2019-08-19 15:50 David Francis
2019-08-19 15:50 ` [PATCH 02/14] Revert "drm/amd/display: navi10 bring up skip dsc encoder config" David Francis
[not found] ` <20190819155038.1771-1-David.Francis-5C7GfCeVMHo@public.gmane.org>
0 siblings, 2 replies; 21+ messages in thread
From: David Francis @ 2019-08-19 15:50 UTC (permalink / raw)
To: dri-devel, amd-gfx; +Cc: David Francis
This patchset enables Display Stream Compression (DSC) on DP
connectors on Navi ASICs, both SST and DSC.
8k60 and 4k144 support requires ODM combine, an AMD internal
feature that may be a bit buggy right now.
Patches 1 through 5 enable DSC for SST. Most of the work was
already done in the Navi promotion patches; this just hooks
it up to the atomic interface. The first two reverts are of temporary
changes to block off DSC. The third is of a commit that was
accidentally promoted twice. The fourth and last revert fixes a
potential issue with ODM combine.
Patches 6 and 7 are fixes for bugs that would be exposed by
MST DSC. One fix is with the MST code and the other in the DSC code.
Patches 8, 9, and 10 are small DRM changes required for DSC MST:
FEC, a new bit in the standard; some export definitions; and
a previously uninitialized variable.
Patches 11 through 14 are the DSC MST policy itself. This includes
the code for detecting and validating DSC capabilities, enabling
DSC over a link, computing the fair DSC configurations for
multiple DSC displays, and adding to atomic state crtcs that might
need reprogramming due to DSC.
David Francis (14):
Revert "drm/amd/display: skip dsc config for navi10 bring up"
Revert "drm/amd/display: navi10 bring up skip dsc encoder config"
Revert "drm/amd/display: add global master update lock for DCN2"
Revert "drm/amd/display: Fix underscan not using proper scaling"
drm/amd/display: Enable SST DSC in DM
drm/amd/display: Use dc helpers to compute timeslot distribution
drm/amd/display: Initialize DSC PPS variables to 0
drm/dp-mst: Parse FEC capability on MST ports
drm/dp-mst: Export symbols for dpcd read/write
drm/dp-mst: Fill branch->num_ports
drm/amd/display: Validate DSC caps on MST endpoints
drm/amd/display: Write DSC enable to MST DPCD
drm/amd/display: MST DSC compute fair share
drm/amd/display: Trigger modesets on MST DSC connectors
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 116 +++-
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 71 +--
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 498 +++++++++++++++++-
.../display/amdgpu_dm/amdgpu_dm_mst_types.h | 5 +
drivers/gpu/drm/amd/display/dc/core/dc.c | 12 +-
.../drm/amd/display/dc/core/dc_link_hwss.c | 3 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 3 +
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 -
.../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 72 +--
.../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h | 3 -
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 7 +-
.../drm/amd/display/dc/dcn20/dcn20_resource.h | 1 +
.../display/dc/dcn20/dcn20_stream_encoder.c | 8 -
.../amd/display/dc/inc/hw/timing_generator.h | 2 -
drivers/gpu/drm/drm_dp_mst_topology.c | 6 +
include/drm/drm_dp_mst_helper.h | 3 +
16 files changed, 668 insertions(+), 146 deletions(-)
--
2.17.1
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^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 01/14] Revert "drm/amd/display: skip dsc config for navi10 bring up"
[not found] ` <20190819155038.1771-1-David.Francis-5C7GfCeVMHo@public.gmane.org>
@ 2019-08-19 15:50 ` David Francis
2019-08-19 15:50 ` [PATCH 03/14] Revert "drm/amd/display: add global master update lock for DCN2" David Francis
` (11 subsequent siblings)
12 siblings, 0 replies; 21+ messages in thread
From: David Francis @ 2019-08-19 15:50 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: David Francis
This reverts commit 55ad81f3510ec1a1c19e6a4d8a6319812d07d256.
optc dsc config was causing warnings due to missing register
definitions. With the registers restored, the function can
be re-enabled
The reverted commit also disabled sanity checks and dsc
power gating. The sanity check warnings are not associated
with dsc, and power gating on dsc still has an issue on
non-dsc monitors where the dsc hardware block is never init
and so cannot respond to power gating requests. Therefore,
those are left as is
Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index aedf9de1c947..99070e93020b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -191,15 +191,6 @@ void optc2_set_dsc_config(struct timing_generator *optc,
uint32_t dsc_slice_width)
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
- uint32_t data_format = 0;
- /* skip if dsc mode is not changed */
- data_format = dm_read_reg(CTX, REG(OPTC_DATA_FORMAT_CONTROL));
-
- data_format = data_format & 0x30; /* bit5:4 */
- data_format = data_format >> 4;
-
- if (data_format == dsc_mode)
- return;
REG_UPDATE(OPTC_DATA_FORMAT_CONTROL,
OPTC_DSC_MODE, dsc_mode);
--
2.17.1
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 02/14] Revert "drm/amd/display: navi10 bring up skip dsc encoder config"
2019-08-19 15:50 [PATCH 00/14] Display Stream Compression (DSC) for AMD Navi David Francis
@ 2019-08-19 15:50 ` David Francis
[not found] ` <20190819155038.1771-1-David.Francis-5C7GfCeVMHo@public.gmane.org>
1 sibling, 0 replies; 21+ messages in thread
From: David Francis @ 2019-08-19 15:50 UTC (permalink / raw)
To: dri-devel, amd-gfx; +Cc: David Francis
This reverts commit 5f2fd347eeff7d4ce271920efd47baaa18fe968c.
Re-enable enc2_dp_set_dsc_config. This function caused warnings
due to missing register definitions. With the registers added,
this now works
Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c | 8 --------
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
index 6d54942ab98b..a4e67286cdad 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
@@ -277,14 +277,6 @@ static void enc2_dp_set_dsc_config(struct stream_encoder *enc,
uint32_t dsc_slice_width)
{
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
- uint32_t dsc_value = 0;
-
- dsc_value = REG_READ(DP_DSC_CNTL);
-
- /* dsc disable skip */
- if ((dsc_value & 0x3) == 0x0)
- return;
-
REG_UPDATE_2(DP_DSC_CNTL,
DP_DSC_MODE, dsc_mode,
--
2.17.1
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 03/14] Revert "drm/amd/display: add global master update lock for DCN2"
[not found] ` <20190819155038.1771-1-David.Francis-5C7GfCeVMHo@public.gmane.org>
2019-08-19 15:50 ` [PATCH 01/14] Revert "drm/amd/display: skip dsc config for navi10 bring up" David Francis
@ 2019-08-19 15:50 ` David Francis
2019-08-19 15:50 ` [PATCH 04/14] Revert "drm/amd/display: Fix underscan not using proper scaling" David Francis
` (10 subsequent siblings)
12 siblings, 0 replies; 21+ messages in thread
From: David Francis @ 2019-08-19 15:50 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: David Francis
This reverts commit 55a6f5bbcf00a49565946c0a9b8c716313dc6c05.
This commit was accidentally promoted twice
Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 --
.../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 63 +------------------
.../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h | 3 -
.../amd/display/dc/inc/hw/timing_generator.h | 2 -
4 files changed, 1 insertion(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index fa8a73f6c8e3..e146d1d8d45e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -575,10 +575,6 @@ enum dc_status dcn20_enable_stream_timing(
pipe_ctx->stream->signal,
true);
- if (pipe_ctx->stream_res.tg->funcs->setup_global_lock)
- pipe_ctx->stream_res.tg->funcs->setup_global_lock(
- pipe_ctx->stream_res.tg);
-
if (odm_pipe)
odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
odm_pipe->stream_res.opp,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index 99070e93020b..2137e2be2140 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -333,65 +333,6 @@ void optc2_triplebuffer_unlock(struct timing_generator *optc)
}
-
-void optc2_setup_global_lock(struct timing_generator *optc)
-{
- struct optc *optc1 = DCN10TG_FROM_TG(optc);
- uint32_t v_blank_start = 0;
- uint32_t h_blank_start = 0, h_total = 0;
-
- REG_SET(OTG_GLOBAL_CONTROL1, 0, MASTER_UPDATE_LOCK_DB_EN, 1);
-
- REG_SET(OTG_GLOBAL_CONTROL2, 0, DIG_UPDATE_LOCATION, 20);
-
- REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start);
-
- REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start);
-
- REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &h_total);
- REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
- MASTER_UPDATE_LOCK_DB_X,
- h_blank_start - 200 - 1,
- MASTER_UPDATE_LOCK_DB_Y,
- v_blank_start - 1);
-}
-
-void optc2_lock_global(struct timing_generator *optc)
-{
- struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
- REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1);
-
- REG_SET(OTG_GLOBAL_CONTROL0, 0,
- OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
- REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
- OTG_MASTER_UPDATE_LOCK, 1);
-
- /* Should be fast, status does not update on maximus */
- if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
- REG_WAIT(OTG_MASTER_UPDATE_LOCK,
- UPDATE_LOCK_STATUS, 1,
- 1, 10);
-}
-
-void optc2_lock(struct timing_generator *optc)
-{
- struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
- REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0);
-
- REG_SET(OTG_GLOBAL_CONTROL0, 0,
- OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
- REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
- OTG_MASTER_UPDATE_LOCK, 1);
-
- /* Should be fast, status does not update on maximus */
- if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
- REG_WAIT(OTG_MASTER_UPDATE_LOCK,
- UPDATE_LOCK_STATUS, 1,
- 1, 10);
-}
-
void optc2_lock_doublebuffer_enable(struct timing_generator *optc)
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
@@ -486,10 +427,8 @@ static struct timing_generator_funcs dcn20_tg_funcs = {
.triplebuffer_lock = optc2_triplebuffer_lock,
.triplebuffer_unlock = optc2_triplebuffer_unlock,
.disable_reset_trigger = optc1_disable_reset_trigger,
- .lock = optc2_lock,
+ .lock = optc1_lock,
.unlock = optc1_unlock,
- .lock_global = optc2_lock_global,
- .setup_global_lock = optc2_setup_global_lock,
.lock_doublebuffer_enable = optc2_lock_doublebuffer_enable,
.lock_doublebuffer_disable = optc2_lock_doublebuffer_disable,
.enable_optc_clock = optc1_enable_optc_clock,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
index 47cb4de1564c..32a58431fd09 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
@@ -106,9 +106,6 @@ void optc2_get_optc_source(struct timing_generator *optc,
void optc2_triplebuffer_lock(struct timing_generator *optc);
void optc2_triplebuffer_unlock(struct timing_generator *optc);
-void optc2_lock(struct timing_generator *optc);
-void optc2_lock_global(struct timing_generator *optc);
-void optc2_setup_global_lock(struct timing_generator *optc);
void optc2_lock_doublebuffer_disable(struct timing_generator *optc);
void optc2_lock_doublebuffer_enable(struct timing_generator *optc);
void optc2_program_manual_trigger(struct timing_generator *optc);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index f607ef24c766..e0713d6d6c8d 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -189,10 +189,8 @@ struct timing_generator_funcs {
bool (*did_triggered_reset_occur)(struct timing_generator *tg);
void (*setup_global_swap_lock)(struct timing_generator *tg,
const struct dcp_gsl_params *gsl_params);
- void (*setup_global_lock)(struct timing_generator *tg);
void (*unlock)(struct timing_generator *tg);
void (*lock)(struct timing_generator *tg);
- void (*lock_global)(struct timing_generator *tg);
void (*lock_doublebuffer_disable)(struct timing_generator *tg);
void (*lock_doublebuffer_enable)(struct timing_generator *tg);
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
--
2.17.1
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 04/14] Revert "drm/amd/display: Fix underscan not using proper scaling"
[not found] ` <20190819155038.1771-1-David.Francis-5C7GfCeVMHo@public.gmane.org>
2019-08-19 15:50 ` [PATCH 01/14] Revert "drm/amd/display: skip dsc config for navi10 bring up" David Francis
2019-08-19 15:50 ` [PATCH 03/14] Revert "drm/amd/display: add global master update lock for DCN2" David Francis
@ 2019-08-19 15:50 ` David Francis
2019-08-19 15:50 ` [PATCH 05/14] drm/amd/display: Enable SST DSC in DM David Francis
` (9 subsequent siblings)
12 siblings, 0 replies; 21+ messages in thread
From: David Francis @ 2019-08-19 15:50 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: David Francis
This reverts commit 80e80ec817f161560b4159608fb41bd289abede3.
This commit fixed an issue with underscan commits not updating all
needed timing values, but through various refactors it is no longer
necessary. It causes corruption on odm combine by
overwriting the halved h_active in the stream timing
Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 77ac7f707ec5..1189e320062b 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2127,7 +2127,7 @@ void dc_commit_updates_for_stream(struct dc *dc,
enum surface_update_type update_type;
struct dc_state *context;
struct dc_context *dc_ctx = dc->ctx;
- int i, j;
+ int i;
stream_status = dc_stream_get_status(stream);
context = dc->current_state;
@@ -2165,16 +2165,6 @@ void dc_commit_updates_for_stream(struct dc *dc,
copy_surface_update_to_plane(surface, &srf_updates[i]);
- if (update_type >= UPDATE_TYPE_MED) {
- for (j = 0; j < dc->res_pool->pipe_count; j++) {
- struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
-
- if (pipe_ctx->plane_state != surface)
- continue;
-
- resource_build_scaling_params(pipe_ctx);
- }
- }
}
copy_stream_update_to_stream(dc, context, stream, stream_update);
--
2.17.1
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 05/14] drm/amd/display: Enable SST DSC in DM
[not found] ` <20190819155038.1771-1-David.Francis-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2019-08-19 15:50 ` [PATCH 04/14] Revert "drm/amd/display: Fix underscan not using proper scaling" David Francis
@ 2019-08-19 15:50 ` David Francis
[not found] ` <20190819155038.1771-6-David.Francis-5C7GfCeVMHo@public.gmane.org>
2019-08-19 15:50 ` [PATCH 06/14] drm/amd/display: Use dc helpers to compute timeslot distribution David Francis
` (8 subsequent siblings)
12 siblings, 1 reply; 21+ messages in thread
From: David Francis @ 2019-08-19 15:50 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: David Francis, Mikita Lipski
In create_stream_for_sink, check for SST DP connectors
Parse DSC caps to DC format, then, if DSC is supported,
compute the config
DSC hardware will be programmed by dc_commit_state
Cc: Mikita Lipski <Mikita.Lipski@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 32 ++++++++++++-------
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 4 ++-
2 files changed, 24 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 911fe78b47c1..84249057e181 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3576,6 +3576,10 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
int mode_refresh;
int preferred_refresh = 0;
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ struct dsc_dec_dpcd_caps dsc_caps;
+ uint32_t link_bandwidth_kbps;
+#endif
struct dc_sink *sink = NULL;
if (aconnector == NULL) {
@@ -3648,17 +3652,23 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
&mode, &aconnector->base, con_state, old_stream);
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
- /* stream->timing.flags.DSC = 0; */
- /* */
- /* if (aconnector->dc_link && */
- /* aconnector->dc_link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT #<{(|&& */
- /* aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.is_dsc_supported|)}>#) */
- /* if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc, */
- /* &aconnector->dc_link->dpcd_caps.dsc_caps, */
- /* dc_link_bandwidth_kbps(aconnector->dc_link, dc_link_get_link_cap(aconnector->dc_link)), */
- /* &stream->timing, */
- /* &stream->timing.dsc_cfg)) */
- /* stream->timing.flags.DSC = 1; */
+ stream->timing.flags.DSC = 0;
+
+ if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
+ dc_dsc_parse_dsc_dpcd(aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
+ aconnector->dc_link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
+ &dsc_caps);
+ link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
+ dc_link_get_link_cap(aconnector->dc_link));
+
+ if (dsc_caps.is_dsc_supported)
+ if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc,
+ &dsc_caps,
+ link_bandwidth_kbps,
+ &stream->timing,
+ &stream->timing.dsc_cfg))
+ stream->timing.flags.DSC = 1;
+ }
#endif
update_stream_scaling_settings(&mode, dm_state, stream);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 7cf0573ab25f..5f2c315b18ba 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -549,7 +549,9 @@ bool dm_helpers_dp_write_dsc_enable(
bool enable
)
{
- return false;
+ uint8_t enable_dsc = enable ? 1 : 0;
+
+ return dm_helpers_dp_write_dpcd(ctx, stream->sink->link, DP_DSC_ENABLE, &enable_dsc, 1);
}
#endif
--
2.17.1
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 06/14] drm/amd/display: Use dc helpers to compute timeslot distribution
[not found] ` <20190819155038.1771-1-David.Francis-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2019-08-19 15:50 ` [PATCH 05/14] drm/amd/display: Enable SST DSC in DM David Francis
@ 2019-08-19 15:50 ` David Francis
[not found] ` <20190819155038.1771-7-David.Francis-5C7GfCeVMHo@public.gmane.org>
2019-08-19 15:50 ` [PATCH 07/14] drm/amd/display: Initialize DSC PPS variables to 0 David Francis
` (7 subsequent siblings)
12 siblings, 1 reply; 21+ messages in thread
From: David Francis @ 2019-08-19 15:50 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: David Francis, Jerry Zuo
We were using drm helpers to convert a timing into its
bandwidth, its bandwidth into pbn, and its pbn into timeslots
These helpers
-Did not take DSC timings into account
-Used the link rate and lane count of the link's aux device,
which are not the same as the link's current cap
-Did not take FEC into account (FEC reduces the PBN per timeslot)
Use the DC helpers (dc_bandwidth_in_kbps_from_timing,
dc_link_bandwidth_kbps) instead
Cc: Jerry Zuo <Jerry.Zuo@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 41 ++++---------------
1 file changed, 8 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 5f2c315b18ba..b32c0790399a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -189,8 +189,8 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
int slots = 0;
bool ret;
int clock;
- int bpp = 0;
int pbn = 0;
+ int pbn_per_timeslot;
aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
@@ -205,40 +205,15 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
mst_port = aconnector->port;
if (enable) {
- clock = stream->timing.pix_clk_100hz / 10;
-
- switch (stream->timing.display_color_depth) {
-
- case COLOR_DEPTH_666:
- bpp = 6;
- break;
- case COLOR_DEPTH_888:
- bpp = 8;
- break;
- case COLOR_DEPTH_101010:
- bpp = 10;
- break;
- case COLOR_DEPTH_121212:
- bpp = 12;
- break;
- case COLOR_DEPTH_141414:
- bpp = 14;
- break;
- case COLOR_DEPTH_161616:
- bpp = 16;
- break;
- default:
- ASSERT(bpp != 0);
- break;
- }
-
- bpp = bpp * 3;
-
- /* TODO need to know link rate */
+ clock = dc_bandwidth_in_kbps_from_timing(&stream->timing);
- pbn = drm_dp_calc_pbn_mode(clock, bpp);
+ /* dc_bandwidth_in_kbps_from_timing already takes bpp into account */
+ pbn = drm_dp_calc_pbn_mode(clock, 1);
- slots = drm_dp_find_vcpi_slots(mst_mgr, pbn);
+ /* Convert kilobits per second / 64 (for 64 timeslots) to pbn (54/64 megabytes per second) */
+ pbn_per_timeslot = dc_link_bandwidth_kbps(
+ stream->link, dc_link_get_link_cap(stream->link)) / (8 * 1000 * 54);
+ slots = DIV_ROUND_UP(pbn, pbn_per_timeslot);
ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, slots);
if (!ret)
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 07/14] drm/amd/display: Initialize DSC PPS variables to 0
[not found] ` <20190819155038.1771-1-David.Francis-5C7GfCeVMHo@public.gmane.org>
` (4 preceding siblings ...)
2019-08-19 15:50 ` [PATCH 06/14] drm/amd/display: Use dc helpers to compute timeslot distribution David Francis
@ 2019-08-19 15:50 ` David Francis
2019-08-19 19:36 ` Kazlauskas, Nicholas
2019-08-19 15:50 ` [PATCH 08/14] drm/dp-mst: Parse FEC capability on MST ports David Francis
` (6 subsequent siblings)
12 siblings, 1 reply; 21+ messages in thread
From: David Francis @ 2019-08-19 15:50 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: David Francis
For DSC MST, sometimes monitors would break out
in full-screen static. The issue traced back to the
PPS generation code, where these variables were being used
uninitialized and were picking up garbage.
memset to 0 to avoid this
Signed-off-by: David Francis <David.Francis@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 3 +++
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 35c5467e60e8..619ac48edd05 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -491,6 +491,9 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
struct dsc_config dsc_cfg;
uint8_t dsc_packed_pps[128];
+ memset(&dsc_cfg, 0, sizeof(dsc_cfg));
+ memset(dsc_packed_pps, 0, 128);
+
/* Enable DSC hw block */
dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
index 379c9e4ac63b..16debe6d89f2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
@@ -207,6 +207,9 @@ static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const str
struct dsc_reg_values dsc_reg_vals;
struct dsc_optc_config dsc_optc_cfg;
+ memset(&dsc_reg_vals, 0, sizeof(dsc_reg_vals));
+ memset(&dsc_optc_cfg, 0, sizeof(dsc_optc_cfg));
+
DC_LOG_DSC("Getting packed DSC PPS for DSC Config:");
dsc_config_log(dsc, dsc_cfg);
DC_LOG_DSC("DSC Picture Parameter Set (PPS):");
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 08/14] drm/dp-mst: Parse FEC capability on MST ports
[not found] ` <20190819155038.1771-1-David.Francis-5C7GfCeVMHo@public.gmane.org>
` (5 preceding siblings ...)
2019-08-19 15:50 ` [PATCH 07/14] drm/amd/display: Initialize DSC PPS variables to 0 David Francis
@ 2019-08-19 15:50 ` David Francis
2019-08-19 15:50 ` [PATCH 09/14] drm/dp-mst: Export symbols for dpcd read/write David Francis
` (5 subsequent siblings)
12 siblings, 0 replies; 21+ messages in thread
From: David Francis @ 2019-08-19 15:50 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: David Francis
As of DP1.4, ENUM_PATH_RESOURCES returns a bit indicating
if FEC can be supported up to that point in the MST network.
The bit is the first byte of the ENUM_PATH_RESOURCES ack reply,
bottom-most bit (refer to section 2.11.9.4 of DP standard,
v1.4)
That value is needed for FEC and DSC support
Store it on drm_dp_mst_port
Signed-off-by: David Francis <David.Francis@amd.com>
---
drivers/gpu/drm/drm_dp_mst_topology.c | 2 ++
include/drm/drm_dp_mst_helper.h | 3 +++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
index 398e7314ea8b..53a0ad16e37b 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -552,6 +552,7 @@ static bool drm_dp_sideband_parse_enum_path_resources_ack(struct drm_dp_sideband
{
int idx = 1;
repmsg->u.path_resources.port_number = (raw->msg[idx] >> 4) & 0xf;
+ repmsg->u.path_resources.fec_capable = raw->msg[idx] & 0x1;
idx++;
if (idx > raw->curlen)
goto fail_len;
@@ -2180,6 +2181,7 @@ static int drm_dp_send_enum_path_resources(struct drm_dp_mst_topology_mgr *mgr,
DRM_DEBUG_KMS("enum path resources %d: %d %d\n", txmsg->reply.u.path_resources.port_number, txmsg->reply.u.path_resources.full_payload_bw_number,
txmsg->reply.u.path_resources.avail_payload_bw_number);
port->available_pbn = txmsg->reply.u.path_resources.avail_payload_bw_number;
+ port->fec_capable = txmsg->reply.u.path_resources.fec_capable;
}
}
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index 2ba6253ea6d3..e1801781fff5 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -108,6 +108,8 @@ struct drm_dp_mst_port {
* audio-capable.
*/
bool has_audio;
+
+ bool fec_capable;
};
/**
@@ -312,6 +314,7 @@ struct drm_dp_port_number_req {
struct drm_dp_enum_path_resources_ack_reply {
u8 port_number;
+ bool fec_capable;
u16 full_payload_bw_number;
u16 avail_payload_bw_number;
};
--
2.17.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 09/14] drm/dp-mst: Export symbols for dpcd read/write
[not found] ` <20190819155038.1771-1-David.Francis-5C7GfCeVMHo@public.gmane.org>
` (6 preceding siblings ...)
2019-08-19 15:50 ` [PATCH 08/14] drm/dp-mst: Parse FEC capability on MST ports David Francis
@ 2019-08-19 15:50 ` David Francis
2019-08-19 15:50 ` [PATCH 10/14] drm/dp-mst: Fill branch->num_ports David Francis
` (4 subsequent siblings)
12 siblings, 0 replies; 21+ messages in thread
From: David Francis @ 2019-08-19 15:50 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: David Francis
To use these functions in drm driver directories, they must be
exported
Signed-off-by: David Francis <David.Francis@amd.com>
---
drivers/gpu/drm/drm_dp_mst_topology.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
index 53a0ad16e37b..5a072571cb44 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -1512,6 +1512,7 @@ ssize_t drm_dp_mst_dpcd_read(struct drm_dp_aux *aux,
return drm_dp_send_dpcd_read(port->mgr, port,
offset, size, buffer);
}
+EXPORT_SYMBOL(drm_dp_mst_dpcd_read);
/**
* drm_dp_mst_dpcd_write() - write a series of bytes to the DPCD via sideband
@@ -1535,6 +1536,7 @@ ssize_t drm_dp_mst_dpcd_write(struct drm_dp_aux *aux,
return drm_dp_send_dpcd_write(port->mgr, port,
offset, size, buffer);
}
+EXPORT_SYMBOL(drm_dp_mst_dpcd_write);
static void drm_dp_check_mstb_guid(struct drm_dp_mst_branch *mstb, u8 *guid)
{
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 10/14] drm/dp-mst: Fill branch->num_ports
[not found] ` <20190819155038.1771-1-David.Francis-5C7GfCeVMHo@public.gmane.org>
` (7 preceding siblings ...)
2019-08-19 15:50 ` [PATCH 09/14] drm/dp-mst: Export symbols for dpcd read/write David Francis
@ 2019-08-19 15:50 ` David Francis
2019-08-19 15:50 ` [PATCH 11/14] drm/amd/display: Validate DSC caps on MST endpoints David Francis
` (3 subsequent siblings)
12 siblings, 0 replies; 21+ messages in thread
From: David Francis @ 2019-08-19 15:50 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: David Francis
This field on drm_dp_mst_branch was never filled
Initialize it to zero when the list of ports is created.
When a port is added to the list, increment num_ports
Signed-off-by: David Francis <David.Francis@amd.com>
---
drivers/gpu/drm/drm_dp_mst_topology.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
index 5a072571cb44..31b7213b6036 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -918,6 +918,7 @@ static struct drm_dp_mst_branch *drm_dp_add_mst_branch_device(u8 lct, u8 *rad)
INIT_LIST_HEAD(&mstb->ports);
kref_init(&mstb->topology_kref);
kref_init(&mstb->malloc_kref);
+ mstb->num_ports = 0;
return mstb;
}
@@ -1672,6 +1673,7 @@ static void drm_dp_add_port(struct drm_dp_mst_branch *mstb,
mutex_lock(&mstb->mgr->lock);
drm_dp_mst_topology_get_port(port);
list_add(&port->next, &mstb->ports);
+ mstb->num_ports++;
mutex_unlock(&mstb->mgr->lock);
}
--
2.17.1
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 11/14] drm/amd/display: Validate DSC caps on MST endpoints
[not found] ` <20190819155038.1771-1-David.Francis-5C7GfCeVMHo@public.gmane.org>
` (8 preceding siblings ...)
2019-08-19 15:50 ` [PATCH 10/14] drm/dp-mst: Fill branch->num_ports David Francis
@ 2019-08-19 15:50 ` David Francis
2019-08-19 15:50 ` [PATCH 12/14] drm/amd/display: Write DSC enable to MST DPCD David Francis
` (2 subsequent siblings)
12 siblings, 0 replies; 21+ messages in thread
From: David Francis @ 2019-08-19 15:50 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: David Francis, Wenjing Liu, Nikola Cornij
The first step in MST DSC is checking MST endpoints
to see how DSC can be enabled
Case 1: DP-to-DP peer device
if the branch immediately upstream has
- PDT = DP_PEER_DEVICE_DP_MST_BRANCHING (2)
- DPCD rev. >= DP 1.4
- Exactly one input and one output
- The output has PDT = DP_PEER_DEVICE_SST_SINK (3)
In this case, DSC could be possible either on the endpoint
or the peer device. Prefer the endpoint, which is possible if
- The endpoint has DP_DSC_DECOMPRESSION_IS_SUPPORTED bit set
- The endpoint has DP_FEC_CAPABLE bit set
- The peer device has DSC_PASSTHROUGH_CAPABILITY bit set (from DP v2.0)
Otherwise, use the peer device
Case 2: DP-to-HDMI peer device
If the output port has
- PDT = DP_PEER_DEVICE_DP_LEGACY_CONV (4)
- DPCD rev. >= DP 1.4
- LDPS = true
- MCS = false
In this case, DSC can only be attempted on the peer device
(the output port)
Case 3: Virtual DP Sink (Internal Display Panel)
If the output port has
- DPCD rev. >= DP 1.4
- port_num >= 8
In this case, DSC can only be attempted on the peer device
(the output port)
Case 4: Synaptix Workaround
If the output has
- link DPCD rev. >= DP 1.4
- link branch_dev_id = 0x90CC24 (Synaptix)
- There is exactly one branch device between the link and output
In this case, DSC can be attempted, but only using the *link*
aux device's caps. This is a quirk.
Test for these cases as modes are enumerated for an MST endpoint.
We cannot do this during link attach because the dc_sink object
will not have been created yet
If no DSC is attempted, zero the DSC caps
Cc: Wenjing Liu <Wenjing.Liu@amd.com>
Cc: Nikola Cornij <Nikola.Cornij@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
---
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 123 +++++++++++++++++-
.../display/amdgpu_dm/amdgpu_dm_mst_types.h | 3 +
2 files changed, 125 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 16218a202b59..58571844f6d5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -25,6 +25,7 @@
#include <linux/version.h>
#include <drm/drm_atomic_helper.h>
+#include <drm/drm_dp_mst_helper.h>
#include "dm_services.h"
#include "amdgpu.h"
#include "amdgpu_dm.h"
@@ -189,6 +190,120 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
.early_unregister = amdgpu_dm_mst_connector_early_unregister,
};
+bool is_virtual_dpcd(struct drm_dp_mst_port *port)
+{
+ struct drm_dp_mst_port *downstream_port;
+
+ if (!port)
+ return false;
+
+ if (port->port_num >= 8 &&
+ port->dpcd_rev >= DP_DPCD_REV_14) {
+ /* Virtual DP Sink (Internal Display Panel) */
+ return true;
+ } else if (port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV &&
+ !port->mcs &&
+ port->ldps &&
+ port->dpcd_rev >= DP_DPCD_REV_14) {
+ /* DP-to-HDMI Protocol Converter */
+ return true;
+ } else if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING &&
+ port->mstb &&
+ port->dpcd_rev >= DP_DPCD_REV_14) {
+ /* DP-to-DP */
+ if (port->mstb->num_ports == 2) {
+ list_for_each_entry(downstream_port, &port->mstb->ports, next) {
+ if (!downstream_port->input &&
+ downstream_port->pdt == DP_PEER_DEVICE_SST_SINK)
+ return true;
+ }
+ }
+ }
+ return false;
+}
+
+bool synaptix_workaround(struct amdgpu_dm_connector *aconnector)
+{
+ struct drm_dp_mst_port *port = aconnector->port;
+ struct dc_link *link = aconnector->dc_sink->link;
+ u8 down_stream_port_data;
+
+ if (port->mgr->mst_primary == port->parent &&
+ link->dpcd_caps.branch_dev_id == 0x90CC24 &&
+ link->dpcd_caps.dpcd_rev.raw >= DP_DPCD_REV_14) {
+ drm_dp_mst_dpcd_read(&port->aux, DP_DOWNSTREAMPORT_PRESENT, &down_stream_port_data, 1);
+ if ((down_stream_port_data & 7) != 3)
+ return true;
+ }
+ return false;
+}
+
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
+{
+ u8 upstream_dsc_caps[16] = { 0 };
+ u8 endpoint_dsc_caps[16] = { 0 };
+ u8 endpoint_fec_caps = 0;
+ struct dc_sink *dc_sink = aconnector->dc_sink;
+ struct drm_dp_mst_port *output_port = aconnector->port;
+ struct drm_dp_mst_port *immediate_upstream_port;
+ struct drm_dp_mst_port *fec_port;
+
+ if (aconnector->port && aconnector->port->parent)
+ immediate_upstream_port = aconnector->port->parent->port_parent;
+ else
+ immediate_upstream_port = NULL;
+
+ fec_port = immediate_upstream_port;
+ while (fec_port) {
+ if (!fec_port->fec_capable)
+ return false;
+
+ fec_port = fec_port->parent->port_parent;
+ }
+
+ if (immediate_upstream_port)
+ drm_dp_mst_dpcd_read(&immediate_upstream_port->aux, DP_DSC_SUPPORT, upstream_dsc_caps, 16);
+ drm_dp_mst_dpcd_read(&output_port->aux, DP_DSC_SUPPORT, endpoint_dsc_caps, 16);
+ drm_dp_mst_dpcd_read(&output_port->aux, DP_FEC_CAPABILITY, &endpoint_fec_caps, 1);
+
+ if (is_virtual_dpcd(immediate_upstream_port)
+ && (upstream_dsc_caps[0] & 0x2) /* DSC passthrough capability */
+ && (endpoint_fec_caps & DP_FEC_CAPABLE)
+ && (endpoint_dsc_caps[0] & DP_DSC_DECOMPRESSION_IS_SUPPORTED)) {
+ /* Enpoint decompression with DP-to-DP peer device */
+ if (!dc_dsc_parse_dsc_dpcd(endpoint_dsc_caps, NULL, &dc_sink->sink_dsc_caps.dsc_dec_caps))
+ return false;
+
+ dc_sink->sink_dsc_caps.is_virtual_dpcd_dsc = false;
+ } else if (is_virtual_dpcd(immediate_upstream_port)) {
+ /* Virtual DPCD decompression with DP-to-DP peer device */
+ if (!dc_dsc_parse_dsc_dpcd(upstream_dsc_caps, NULL, &dc_sink->sink_dsc_caps.dsc_dec_caps))
+ return false;
+
+ dc_sink->sink_dsc_caps.is_virtual_dpcd_dsc = true;
+ } else if (is_virtual_dpcd(output_port)) {
+ /* Virtual DPCD decompression with DP-to-HDMI or Virtual DP Sink */
+ if (!dc_dsc_parse_dsc_dpcd(endpoint_dsc_caps, NULL, &dc_sink->sink_dsc_caps.dsc_dec_caps))
+ return false;
+
+ dc_sink->sink_dsc_caps.is_virtual_dpcd_dsc = true;
+ } else if (synaptix_workaround(aconnector)) {
+ /* Synaptix workaround */
+ aconnector = dc_sink->link->priv;
+ drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, DP_DSC_SUPPORT, upstream_dsc_caps, 16);
+ if (!dc_dsc_parse_dsc_dpcd(upstream_dsc_caps, NULL, &dc_sink->sink_dsc_caps.dsc_dec_caps))
+ return false;
+
+ dc_sink->sink_dsc_caps.is_virtual_dpcd_dsc = true;
+ } else {
+ return false;
+ }
+
+ return true;
+}
+#endif
+
static int dm_dp_mst_get_modes(struct drm_connector *connector)
{
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
@@ -231,10 +346,16 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)
/* dc_link_add_remote_sink returns a new reference */
aconnector->dc_sink = dc_sink;
- if (aconnector->dc_sink)
+ if (aconnector->dc_sink) {
amdgpu_dm_update_freesync_caps(
connector, aconnector->edid);
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ if (!validate_dsc_caps_on_connector(aconnector))
+ memset(&aconnector->dc_sink->sink_dsc_caps,
+ 0, sizeof(aconnector->dc_sink->sink_dsc_caps));
+#endif
+ }
}
drm_connector_update_edid_property(
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
index 2da851b40042..8de3d8c30f8d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
@@ -32,4 +32,7 @@ struct amdgpu_dm_connector;
void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
struct amdgpu_dm_connector *aconnector);
+bool is_virtual_dpcd(struct drm_dp_mst_port *port);
+bool synaptix_workaround(struct amdgpu_dm_connector *aconnector);
+
#endif
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 12/14] drm/amd/display: Write DSC enable to MST DPCD
[not found] ` <20190819155038.1771-1-David.Francis-5C7GfCeVMHo@public.gmane.org>
` (9 preceding siblings ...)
2019-08-19 15:50 ` [PATCH 11/14] drm/amd/display: Validate DSC caps on MST endpoints David Francis
@ 2019-08-19 15:50 ` David Francis
2019-08-19 15:50 ` [PATCH 13/14] drm/amd/display: MST DSC compute fair share David Francis
2019-08-19 15:50 ` [PATCH 14/14] drm/amd/display: Trigger modesets on MST DSC connectors David Francis
12 siblings, 0 replies; 21+ messages in thread
From: David Francis @ 2019-08-19 15:50 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: David Francis, Wenjing Liu, Nikola Cornij
Rework the dm_helpers_write_dsc_enable callback to
handle the MST case
Depending on how DSC is done, the DP_DSC_ENABLE bit
needs to be set on a different point
For SST, use the link aux
For endpoint DSC over DP-to-DP peer devices,
use the output port
For peer device DSC over DP-to-DP peer devices,
use the upstream (peer) device
For DP-to-HDMI or virtual DP peer devices,
use the output port
For the Synaptix workaround, use the link aux
Cc: Wenjing Liu <Wenjing.Liu@amd.com>
Cc: Nikola Cornij <Nikola.Cornij@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 30 ++++++++++++++++++-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index b32c0790399a..3d5deeed8367 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -38,6 +38,7 @@
#include "dc.h"
#include "amdgpu_dm.h"
#include "amdgpu_dm_irq.h"
+#include "amdgpu_dm_mst_types.h"
#include "dm_helpers.h"
@@ -525,8 +526,35 @@ bool dm_helpers_dp_write_dsc_enable(
)
{
uint8_t enable_dsc = enable ? 1 : 0;
+ struct amdgpu_dm_connector *aconnector;
+
+ if (!stream)
+ return false;
+
+ if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
+ aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
+
+ if (!aconnector || !aconnector->dc_sink)
+ return false;
+
+ if (!aconnector->dc_sink->sink_dsc_caps.is_virtual_dpcd_dsc)
+ return drm_dp_mst_dpcd_write(&aconnector->port->aux,
+ DP_DSC_ENABLE, &enable_dsc, 1) >= 0;
+ else if (is_virtual_dpcd(aconnector->port->parent->port_parent))
+ return drm_dp_mst_dpcd_write(&aconnector->port->parent->port_parent->aux,
+ DP_DSC_ENABLE, &enable_dsc, 1) >= 0;
+ else if (is_virtual_dpcd(aconnector->port))
+ return drm_dp_mst_dpcd_write(&aconnector->port->aux,
+ DP_DSC_ENABLE, &enable_dsc, 1) >= 0;
+ else if (synaptix_workaround(aconnector))
+ return dm_helpers_dp_write_dpcd(ctx, stream->link,
+ DP_DSC_ENABLE, &enable_dsc, 1);
+ }
+
+ if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT)
+ return dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
- return dm_helpers_dp_write_dpcd(ctx, stream->sink->link, DP_DSC_ENABLE, &enable_dsc, 1);
+ return false;
}
#endif
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 13/14] drm/amd/display: MST DSC compute fair share
[not found] ` <20190819155038.1771-1-David.Francis-5C7GfCeVMHo@public.gmane.org>
` (10 preceding siblings ...)
2019-08-19 15:50 ` [PATCH 12/14] drm/amd/display: Write DSC enable to MST DPCD David Francis
@ 2019-08-19 15:50 ` David Francis
2019-08-19 15:50 ` [PATCH 14/14] drm/amd/display: Trigger modesets on MST DSC connectors David Francis
12 siblings, 0 replies; 21+ messages in thread
From: David Francis @ 2019-08-19 15:50 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: David Francis, Wenjing Liu, Nikola Cornij
If there is limited link bandwidth on a MST network,
it must be divided fairly between the streams on that network
Implement an algorithm to determine the correct DSC config
for each stream
The algorithm:
This
[ ] ( )
represents the range of bandwidths possible for a given stream.
The [] area represents the range of DSC configs, and the ()
represents no DSC. The bandwidth used increases from left to right.
First, try disabling DSC on all streams
[ ] (|)
[ ] (|)
Check this against the bandwidth limits of the link and each branch
(including each endpoint). If it passes, the job is done
Second, try maximum DSC compression on all streams
that support DSC
[| ] ( )
[| ] ( )
If this does not pass, then enabling this combination of streams
is impossible
Otherwise, divide the remaining bandwidth evenly amongst the streams
[ | ] ( )
[ | ] ( )
If one or more of the streams reach minimum compression, evenly
divide the reamining bandwidth amongst the remaining streams
[ |] ( )
[ |] ( )
[ | ] ( )
[ | ] ( )
If all streams can reach minimum compression, disable compression
greedily
[ |] ( )
[ |] ( )
[ ] (|)
Perform this algorithm on each full update, on each MST link
with at least one DSC stream on it
After the configs are computed, call
dcn20_add_dsc_to_stream_resource on each stream with DSC enabled.
It is only after all streams are created that we can know which
of them will need DSC.
Do all of this at the end of amdgpu atomic check. If it fails,
fail check; This combination of timings cannot be supported.
Cc: Wenjing Liu <Wenjing.Liu@amd.com>
Cc: Nikola Cornij <Nikola.Cornij@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 375 ++++++++++++++++++
.../display/amdgpu_dm/amdgpu_dm_mst_types.h | 4 +-
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 7 +-
.../drm/amd/display/dc/dcn20/dcn20_resource.h | 1 +
5 files changed, 388 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 84249057e181..145fd73025dc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7331,6 +7331,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ if (!compute_mst_dsc_configs_for_state(dm_state->context))
+ goto fail;
+#endif
if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) {
ret = -EINVAL;
goto fail;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 58571844f6d5..0b6bfa093e83 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -38,6 +38,8 @@
#include "i2caux_interface.h"
+#include "dc/dcn20/dcn20_resource.h"
+
/* #define TRACE_DPCD */
#ifdef TRACE_DPCD
@@ -548,3 +550,376 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
aconnector->connector_id);
}
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+struct dsc_mst_fairness_params {
+ struct dc_crtc_timing *timing;
+ struct dc_sink *sink;
+ struct dc_dsc_bw_range bw_range;
+ bool compression_possible;
+ struct drm_dp_mst_port *port;
+};
+
+struct dsc_mst_fairness_vars {
+ int pbn;
+ bool dsc_enabled;
+ int bpp_x16;
+};
+
+static bool port_downstream_of_branch(struct drm_dp_mst_port *port,
+ struct drm_dp_mst_branch *branch)
+{
+ while (port->parent) {
+ if (port->parent == branch)
+ return true;
+
+ if (port->parent->port_parent)
+ port = port->parent->port_parent;
+ else
+ break;
+ }
+ return false;
+}
+
+static bool check_pbn_limit_on_branch(struct drm_dp_mst_branch *branch,
+ struct dsc_mst_fairness_params *params,
+ struct dsc_mst_fairness_vars *vars, int count)
+{
+ struct drm_dp_mst_port *port;
+ int i;
+ int pbn_limit = 0;
+ int pbn_used = 0;
+
+ list_for_each_entry(port, &branch->ports, next) {
+ if (port->mstb)
+ if (!check_pbn_limit_on_branch(port->mstb, params, vars, count))
+ return false;
+
+ if (port->available_pbn > 0)
+ pbn_limit = port->available_pbn;
+ }
+
+ for (i = 0; i < count; i++) {
+ if (port_downstream_of_branch(params[i].port, branch))
+ pbn_used += vars[i].pbn;
+ }
+
+ if (pbn_used > pbn_limit)
+ return false;
+
+ return true;
+}
+
+static bool check_bandwidth_limits(struct dc_link *dc_link,
+ struct dsc_mst_fairness_params *params,
+ struct dsc_mst_fairness_vars *vars,
+ int count)
+{
+ int link_timeslot_limit = 63;
+ int link_timeslots_used = 0;
+ int pbn_per_timeslot;
+ int i;
+ struct drm_dp_mst_topology_mgr *mst_mgr;
+
+ /* kbits to pbn, dividing by 64 */
+ pbn_per_timeslot = dc_link_bandwidth_kbps(dc_link,
+ dc_link_get_link_cap(dc_link)) / (8 * 1000 * 54);
+
+ /* Check link bandwidth limit */
+ for (i = 0; i < count; i++)
+ link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot);
+
+ if (link_timeslots_used > link_timeslot_limit)
+ return false;
+
+ /* Check branch bandwidth limit for each port on each branch */
+ mst_mgr = params[0].port->mgr;
+ if (!check_pbn_limit_on_branch(mst_mgr->mst_primary, params, vars, count))
+ return false;
+
+ return true;
+}
+
+static int kbps_to_peak_pbn(int kbps)
+{
+ u64 peak_kbps = kbps;
+
+ peak_kbps *= 1006;
+ peak_kbps /= 1000;
+ return (int) DIV_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
+}
+
+static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
+ struct dsc_mst_fairness_vars *vars,
+ int count)
+{
+ int i;
+
+ for (i = 0; i < count; i++) {
+ memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
+ if (vars[i].dsc_enabled && dc_dsc_compute_config(params[i].sink->ctx->dc,
+ ¶ms[i].sink->sink_dsc_caps.dsc_dec_caps,
+ 0,
+ params[i].timing,
+ ¶ms[i].timing->dsc_cfg)) {
+ params[i].timing->flags.DSC = 1;
+ params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;
+ } else {
+ params[i].timing->flags.DSC = 0;
+ }
+
+ }
+
+}
+
+static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
+{
+ struct dc_dsc_config dsc_config;
+ u64 kbps;
+
+ kbps = (u64)pbn * 994 * 8 * 54 / 64;
+ dc_dsc_compute_config(param.sink->ctx->dc,
+ ¶m.sink->sink_dsc_caps.dsc_dec_caps,
+ (int) kbps, param.timing, &dsc_config);
+
+ return dsc_config.bits_per_pixel;
+}
+
+static void increase_dsc_bpp(struct dc_link *dc_link,
+ struct dsc_mst_fairness_params *params,
+ struct dsc_mst_fairness_vars *vars,
+ int count)
+{
+ int i;
+ bool bpp_increased[MAX_PIPES];
+ int initial_slack[MAX_PIPES];
+ int min_initial_slack;
+ int next_index;
+ int remaining_to_increase = 0;
+ int pbn_per_timeslot;
+ int link_timeslots_used;
+ int fair_pbn_alloc;
+
+ for (i = 0; i < count; i++) {
+ if (vars[i].dsc_enabled) {
+ initial_slack[i] = kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i].pbn;
+ bpp_increased[i] = false;
+ remaining_to_increase += 1;
+ } else {
+ initial_slack[i] = 0;
+ bpp_increased[i] = true;
+ }
+ }
+
+ pbn_per_timeslot = dc_link_bandwidth_kbps(dc_link,
+ dc_link_get_link_cap(dc_link)) / (8 * 1000 * 54);
+
+ while (remaining_to_increase) {
+ next_index = -1;
+ min_initial_slack = -1;
+ for (i = 0; i < count; i++) {
+ if (!bpp_increased[i]) {
+ if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
+ min_initial_slack = initial_slack[i];
+ next_index = i;
+ }
+ }
+ }
+
+ if (next_index == -1)
+ break;
+
+ link_timeslots_used = 0;
+
+ for (i = 0; i < count; i++)
+ link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot);
+
+ fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * pbn_per_timeslot;
+
+ if (initial_slack[next_index] > fair_pbn_alloc) {
+ vars[next_index].pbn += fair_pbn_alloc;
+ if (check_bandwidth_limits(dc_link, params, vars, count))
+ vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
+ else
+ vars[next_index].pbn -= fair_pbn_alloc;
+ } else {
+ vars[next_index].pbn += initial_slack[next_index];
+ if (check_bandwidth_limits(dc_link, params, vars, count))
+ vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
+ else
+ vars[next_index].pbn -= initial_slack[next_index];
+ }
+
+ bpp_increased[next_index] = true;
+ remaining_to_increase--;
+ }
+}
+
+static void try_disable_dsc(struct dc_link *dc_link,
+ struct dsc_mst_fairness_params *params,
+ struct dsc_mst_fairness_vars *vars,
+ int count)
+{
+ int i;
+ bool tried[MAX_PIPES];
+ int kbps_increase[MAX_PIPES];
+ int max_kbps_increase;
+ int next_index;
+ int remaining_to_try = 0;
+
+ for (i = 0; i < count; i++) {
+ if (vars[i].dsc_enabled && vars[i].bpp_x16 == params[i].bw_range.max_target_bpp_x16) {
+ kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
+ tried[i] = false;
+ remaining_to_try += 1;
+ } else {
+ kbps_increase[i] = 0;
+ tried[i] = true;
+ }
+ }
+
+ while (remaining_to_try) {
+ next_index = -1;
+ max_kbps_increase = -1;
+ for (i = 0; i < count; i++) {
+ if (!tried[i]) {
+ if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
+ max_kbps_increase = kbps_increase[i];
+ next_index = i;
+ }
+ }
+ }
+
+ if (next_index == -1)
+ break;
+
+ vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
+
+ if (check_bandwidth_limits(dc_link, params, vars, count)) {
+ vars[next_index].dsc_enabled = false;
+ vars[next_index].bpp_x16 = 0;
+ } else {
+ vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps);
+ }
+
+ tried[next_index] = true;
+ remaining_to_try--;
+ }
+}
+
+static bool compute_mst_dsc_configs_for_link(struct dc_state *dc_state, struct dc_link *dc_link)
+{
+ int i;
+ struct dc_stream_state *stream;
+ struct dsc_mst_fairness_params params[MAX_PIPES];
+ struct dsc_mst_fairness_vars vars[MAX_PIPES];
+ struct amdgpu_dm_connector *aconnector;
+ int count = 0;
+
+ memset(params, 0, sizeof(params));
+
+ /* Set up params */
+ for (i = 0; i < dc_state->stream_count; i++) {
+ stream = dc_state->streams[i];
+
+ if (stream->link != dc_link)
+ continue;
+
+ stream->timing.flags.DSC = 0;
+
+ params[count].timing = &stream->timing;
+ params[count].sink = stream->sink;
+ aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
+ params[count].port = aconnector->port;
+ params[count].compression_possible = stream->sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported;
+ if (!dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc, 8, 16,
+ &stream->sink->sink_dsc_caps.dsc_dec_caps,
+ &stream->timing, ¶ms[count].bw_range))
+ params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
+
+ count++;
+ }
+
+ /* Try no compression */
+ for (i = 0; i < count; i++) {
+ vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
+ vars[i].dsc_enabled = false;
+ vars[i].bpp_x16 = 0;
+ }
+
+ if (check_bandwidth_limits(dc_link, params, vars, count)) {
+ set_dsc_configs_from_fairness_vars(params, vars, count);
+ return true;
+ }
+
+ /* Try max compression */
+ for (i = 0; i < count; i++) {
+ if (params[i].compression_possible) {
+ vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps);
+ vars[i].dsc_enabled = true;
+ vars[i].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
+ } else {
+ vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
+ vars[i].dsc_enabled = false;
+ vars[i].bpp_x16 = 0;
+ }
+ }
+
+ if (!check_bandwidth_limits(dc_link, params, vars, count))
+ return false;
+
+ /* Optimize degree of compression */
+ increase_dsc_bpp(dc_link, params, vars, count);
+
+ try_disable_dsc(dc_link, params, vars, count);
+
+ set_dsc_configs_from_fairness_vars(params, vars, count);
+
+ return true;
+}
+
+bool compute_mst_dsc_configs_for_state(struct dc_state *dc_state)
+{
+ int i, j;
+ struct dc_stream_state *stream;
+ bool computed_streams[MAX_PIPES];
+ struct amdgpu_dm_connector *aconnector;
+
+ for (i = 0; i < dc_state->stream_count; i++)
+ computed_streams[i] = false;
+
+ for (i = 0; i < dc_state->stream_count; i++) {
+ stream = dc_state->streams[i];
+
+ if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
+ continue;
+
+ aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
+
+ if (!aconnector || !aconnector->dc_sink)
+ continue;
+
+ if (!aconnector->dc_sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported)
+ continue;
+
+ if (computed_streams[i])
+ continue;
+
+ if (!compute_mst_dsc_configs_for_link(dc_state, stream->link))
+ return false;
+
+ for (j = 0; j < dc_state->stream_count; j++) {
+ if (dc_state->streams[j]->link == stream->link)
+ computed_streams[j] = true;
+ }
+ }
+
+ for (i = 0; i < dc_state->stream_count; i++) {
+ stream = dc_state->streams[i];
+
+ if (stream->timing.flags.DSC == 1)
+ dcn20_add_dsc_to_stream_resource(stream->ctx->dc, dc_state, stream);
+ }
+
+ return true;
+}
+#endif
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
index 8de3d8c30f8d..b7d2e4e70185 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
@@ -34,5 +34,7 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
bool is_virtual_dpcd(struct drm_dp_mst_port *port);
bool synaptix_workaround(struct amdgpu_dm_connector *aconnector);
-
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+bool compute_mst_dsc_configs_for_state(struct dc_state *dc_state);
+#endif
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index c59f31dcdc0d..22511b047837 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1439,7 +1439,7 @@ static void release_dsc(struct resource_context *res_ctx,
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
-static enum dc_status add_dsc_to_stream_resource(struct dc *dc,
+enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc,
struct dc_state *dc_ctx,
struct dc_stream_state *dc_stream)
{
@@ -1454,6 +1454,9 @@ static enum dc_status add_dsc_to_stream_resource(struct dc *dc,
if (pipe_ctx->stream != dc_stream)
continue;
+ if (pipe_ctx->stream_res.dsc)
+ continue;
+
acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc);
/* The number of DSCs can be less than the number of pipes */
@@ -1511,7 +1514,7 @@ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx,
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
/* Get a DSC if required and available */
if (result == DC_OK && dc_stream->timing.flags.DSC)
- result = add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
+ result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
#endif
if (result == DC_OK)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
index 44f95aa0d61e..2209ebda6ef6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
@@ -131,6 +131,7 @@ void dcn20_calculate_dlg_params(
enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);
enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
+enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_state *dc_ctx, struct dc_stream_state *dc_stream);
enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state);
--
2.17.1
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 14/14] drm/amd/display: Trigger modesets on MST DSC connectors
[not found] ` <20190819155038.1771-1-David.Francis-5C7GfCeVMHo@public.gmane.org>
` (11 preceding siblings ...)
2019-08-19 15:50 ` [PATCH 13/14] drm/amd/display: MST DSC compute fair share David Francis
@ 2019-08-19 15:50 ` David Francis
[not found] ` <20190819155038.1771-15-David.Francis-5C7GfCeVMHo@public.gmane.org>
12 siblings, 1 reply; 21+ messages in thread
From: David Francis @ 2019-08-19 15:50 UTC (permalink / raw)
To: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Leo Li, David Francis, Nicholas Kazlauskas
Whenever a connector on an MST network is attached, detached, or
undergoes a modeset, the DSC configs for each stream on that
topology will be recalculated. This can change their required
bandwidth, requiring a full reprogramming, as though a modeset
was performed, even if that stream did not change timing.
Therefore, whenever a crtc has drm_atomic_crtc_needs_modeset,
for each crtc that shares a MST topology with that stream and
supports DSC, add that crtc (and all affected connectors and
planes) to the atomic state and set mode_changed on its state
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 80 +++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 145fd73025dc..8d5357aec5e8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6475,7 +6475,78 @@ static int do_aquire_global_lock(struct drm_device *dev,
return ret < 0 ? ret : 0;
}
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
+{
+ struct drm_connector *connector;
+ struct drm_connector_state *conn_state;
+ struct drm_connector_list_iter conn_iter;
+ struct drm_crtc_state *new_crtc_state;
+ struct amdgpu_dm_connector *aconnector = NULL, *aconnector_to_add;
+ int i, j, ret;
+ struct drm_crtc *crtcs_affected[MAX_PIPES] = { 0 };
+
+ for_each_new_connector_in_state(state, connector, conn_state, i) {
+ if (conn_state->crtc != crtc)
+ continue;
+
+ aconnector = to_amdgpu_dm_connector(connector);
+ if (!aconnector->port)
+ aconnector = NULL;
+ else
+ break;
+ }
+
+ if (!aconnector)
+ return 0;
+
+ i = 0;
+ drm_connector_list_iter_begin(state->dev, &conn_iter);
+ drm_for_each_connector_iter(connector, &conn_iter) {
+ if (!connector->state || !connector->state->crtc)
+ continue;
+
+ aconnector_to_add = to_amdgpu_dm_connector(connector);
+ if (!aconnector_to_add->port)
+ continue;
+
+ if (aconnector_to_add->port->mgr != aconnector->port->mgr)
+ continue;
+
+ if (!aconnector_to_add->dc_sink)
+ continue;
+
+ if (!aconnector_to_add->dc_sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported)
+ continue;
+ if (i >= MAX_PIPES)
+ continue;
+
+ crtcs_affected[i] = connector->state->crtc;
+ i++;
+ }
+ drm_connector_list_iter_end(&conn_iter);
+
+ for (j = 0; j < i; j++) {
+ new_crtc_state = drm_atomic_get_crtc_state(state, crtcs_affected[j]);
+ if (IS_ERR(new_crtc_state))
+ return PTR_ERR(new_crtc_state);
+
+ new_crtc_state->mode_changed = true;
+
+ ret = drm_atomic_add_affected_connectors(state, crtcs_affected[j]);
+ if (ret)
+ return ret;
+
+ ret = drm_atomic_add_affected_planes(state, crtcs_affected[j]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+
+}
+#endif
static void get_freesync_config_for_crtc(
struct dm_crtc_state *new_crtc_state,
struct dm_connector_state *new_con_state)
@@ -7178,6 +7249,15 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
goto fail;
}
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+ if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
+ ret = add_affected_mst_dsc_crtcs(state, crtc);
+ if (ret)
+ goto fail;
+ }
+ }
+#endif
/*
* Add all primary and overlay planes on the CRTC to the state
* whenever a plane is enabled to maintain correct z-ordering
--
2.17.1
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 05/14] drm/amd/display: Enable SST DSC in DM
[not found] ` <20190819155038.1771-6-David.Francis-5C7GfCeVMHo@public.gmane.org>
@ 2019-08-19 18:46 ` Mikita Lipski
0 siblings, 0 replies; 21+ messages in thread
From: Mikita Lipski @ 2019-08-19 18:46 UTC (permalink / raw)
To: Francis, David, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Lipski, Mikita
Tested-by: Mikita Lipski <Mikita.Lipski@amd.com>
Mikita Lipski
On 2019-08-19 11:50 a.m., David Francis wrote:
> In create_stream_for_sink, check for SST DP connectors
>
> Parse DSC caps to DC format, then, if DSC is supported,
> compute the config
>
> DSC hardware will be programmed by dc_commit_state
>
> Cc: Mikita Lipski <Mikita.Lipski@amd.com>
> Signed-off-by: David Francis <David.Francis@amd.com>
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 32 ++++++++++++-------
> .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 4 ++-
> 2 files changed, 24 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 911fe78b47c1..84249057e181 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -3576,6 +3576,10 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
> bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
> int mode_refresh;
> int preferred_refresh = 0;
> +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> + struct dsc_dec_dpcd_caps dsc_caps;
> + uint32_t link_bandwidth_kbps;
> +#endif
>
> struct dc_sink *sink = NULL;
> if (aconnector == NULL) {
> @@ -3648,17 +3652,23 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
> &mode, &aconnector->base, con_state, old_stream);
>
> #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> - /* stream->timing.flags.DSC = 0; */
> - /* */
> - /* if (aconnector->dc_link && */
> - /* aconnector->dc_link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT #<{(|&& */
> - /* aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.is_dsc_supported|)}>#) */
> - /* if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc, */
> - /* &aconnector->dc_link->dpcd_caps.dsc_caps, */
> - /* dc_link_bandwidth_kbps(aconnector->dc_link, dc_link_get_link_cap(aconnector->dc_link)), */
> - /* &stream->timing, */
> - /* &stream->timing.dsc_cfg)) */
> - /* stream->timing.flags.DSC = 1; */
> + stream->timing.flags.DSC = 0;
> +
> + if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
> + dc_dsc_parse_dsc_dpcd(aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
> + aconnector->dc_link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
> + &dsc_caps);
> + link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
> + dc_link_get_link_cap(aconnector->dc_link));
> +
> + if (dsc_caps.is_dsc_supported)
> + if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc,
> + &dsc_caps,
> + link_bandwidth_kbps,
> + &stream->timing,
> + &stream->timing.dsc_cfg))
> + stream->timing.flags.DSC = 1;
> + }
> #endif
>
> update_stream_scaling_settings(&mode, dm_state, stream);
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> index 7cf0573ab25f..5f2c315b18ba 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> @@ -549,7 +549,9 @@ bool dm_helpers_dp_write_dsc_enable(
> bool enable
> )
> {
> - return false;
> + uint8_t enable_dsc = enable ? 1 : 0;
> +
> + return dm_helpers_dp_write_dpcd(ctx, stream->sink->link, DP_DSC_ENABLE, &enable_dsc, 1);
> }
> #endif
>
>
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 06/14] drm/amd/display: Use dc helpers to compute timeslot distribution
[not found] ` <20190819155038.1771-7-David.Francis-5C7GfCeVMHo@public.gmane.org>
@ 2019-08-19 19:21 ` Kazlauskas, Nicholas
2019-08-19 19:35 ` Francis, David
0 siblings, 1 reply; 21+ messages in thread
From: Kazlauskas, Nicholas @ 2019-08-19 19:21 UTC (permalink / raw)
To: Francis, David, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Zuo, Jerry
On 8/19/19 11:50 AM, David Francis wrote:
> We were using drm helpers to convert a timing into its
> bandwidth, its bandwidth into pbn, and its pbn into timeslots
>
> These helpers
> -Did not take DSC timings into account
> -Used the link rate and lane count of the link's aux device,
> which are not the same as the link's current cap
> -Did not take FEC into account (FEC reduces the PBN per timeslot)
>
> Use the DC helpers (dc_bandwidth_in_kbps_from_timing,
> dc_link_bandwidth_kbps) instead
>
> Cc: Jerry Zuo <Jerry.Zuo@amd.com>
> Signed-off-by: David Francis <David.Francis@amd.com>
Wouldn't this be a good candidate for shared DRM helpers or to modify
the existing ones to support this usecase?
Seems like this would be shared across drivers.
Nicholas Kazlauskas
> ---
> .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 41 ++++---------------
> 1 file changed, 8 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> index 5f2c315b18ba..b32c0790399a 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> @@ -189,8 +189,8 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
> int slots = 0;
> bool ret;
> int clock;
> - int bpp = 0;
> int pbn = 0;
> + int pbn_per_timeslot;
>
> aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
>
> @@ -205,40 +205,15 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
> mst_port = aconnector->port;
>
> if (enable) {
> - clock = stream->timing.pix_clk_100hz / 10;
> -
> - switch (stream->timing.display_color_depth) {
> -
> - case COLOR_DEPTH_666:
> - bpp = 6;
> - break;
> - case COLOR_DEPTH_888:
> - bpp = 8;
> - break;
> - case COLOR_DEPTH_101010:
> - bpp = 10;
> - break;
> - case COLOR_DEPTH_121212:
> - bpp = 12;
> - break;
> - case COLOR_DEPTH_141414:
> - bpp = 14;
> - break;
> - case COLOR_DEPTH_161616:
> - bpp = 16;
> - break;
> - default:
> - ASSERT(bpp != 0);
> - break;
> - }
> -
> - bpp = bpp * 3;
> -
> - /* TODO need to know link rate */
> + clock = dc_bandwidth_in_kbps_from_timing(&stream->timing);
>
> - pbn = drm_dp_calc_pbn_mode(clock, bpp);
> + /* dc_bandwidth_in_kbps_from_timing already takes bpp into account */
> + pbn = drm_dp_calc_pbn_mode(clock, 1);
>
> - slots = drm_dp_find_vcpi_slots(mst_mgr, pbn);
> + /* Convert kilobits per second / 64 (for 64 timeslots) to pbn (54/64 megabytes per second) */
> + pbn_per_timeslot = dc_link_bandwidth_kbps(
> + stream->link, dc_link_get_link_cap(stream->link)) / (8 * 1000 * 54);
> + slots = DIV_ROUND_UP(pbn, pbn_per_timeslot);
> ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, slots);
>
> if (!ret)
>
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 14/14] drm/amd/display: Trigger modesets on MST DSC connectors
[not found] ` <20190819155038.1771-15-David.Francis-5C7GfCeVMHo@public.gmane.org>
@ 2019-08-19 19:34 ` Kazlauskas, Nicholas
2019-08-19 19:40 ` Francis, David
0 siblings, 1 reply; 21+ messages in thread
From: Kazlauskas, Nicholas @ 2019-08-19 19:34 UTC (permalink / raw)
To: Francis, David, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Li, Sun peng (Leo)
On 8/19/19 11:50 AM, David Francis wrote:
> Whenever a connector on an MST network is attached, detached, or
> undergoes a modeset, the DSC configs for each stream on that
> topology will be recalculated. This can change their required
> bandwidth, requiring a full reprogramming, as though a modeset
> was performed, even if that stream did not change timing.
>
> Therefore, whenever a crtc has drm_atomic_crtc_needs_modeset,
> for each crtc that shares a MST topology with that stream and
> supports DSC, add that crtc (and all affected connectors and
> planes) to the atomic state and set mode_changed on its state
>
> Cc: Leo Li <sunpeng.li@amd.com>
> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
> Signed-off-by: David Francis <David.Francis@amd.com>
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 80 +++++++++++++++++++
> 1 file changed, 80 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 145fd73025dc..8d5357aec5e8 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -6475,7 +6475,78 @@ static int do_aquire_global_lock(struct drm_device *dev,
>
> return ret < 0 ? ret : 0;
> }
> +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> +static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
> +{
> + struct drm_connector *connector;
> + struct drm_connector_state *conn_state;
> + struct drm_connector_list_iter conn_iter;
> + struct drm_crtc_state *new_crtc_state;
> + struct amdgpu_dm_connector *aconnector = NULL, *aconnector_to_add;
> + int i, j, ret;
> + struct drm_crtc *crtcs_affected[MAX_PIPES] = { 0 }; > +
> + for_each_new_connector_in_state(state, connector, conn_state, i) {
> + if (conn_state->crtc != crtc)
> + continue;
> +
> + aconnector = to_amdgpu_dm_connector(connector);
> + if (!aconnector->port)
> + aconnector = NULL;
> + else
> + break;
> + }
> +
> + if (!aconnector)
> + return 0;
> +
> + i = 0;
> + drm_connector_list_iter_begin(state->dev, &conn_iter);
I don't like that we're grabbing the global connector lock every single
time any CRTC undergoes a modeset even for ASICs that don't support DSC.
We do lock everything below in atomic check anyway for FULL updates but
I'd like to avoid adding more code that does this if possible. Maybe a
check at the start that only does this if the ASIC has DSC support would
be OK.
> + drm_for_each_connector_iter(connector, &conn_iter) {
> + if (!connector->state || !connector->state->crtc)
> + continue;
> +
> + aconnector_to_add = to_amdgpu_dm_connector(connector);
> + if (!aconnector_to_add->port)
> + continue;
> +
> + if (aconnector_to_add->port->mgr != aconnector->port->mgr)
> + continue;
> +
> + if (!aconnector_to_add->dc_sink)
> + continue;
> +
> + if (!aconnector_to_add->dc_sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported)
> + continue;
>
> + if (i >= MAX_PIPES)
> + continue;
> +
> + crtcs_affected[i] = connector->state->crtc;
Drop this crtcs_affected array and just perform the logic below right
here. We don't really need two loops here, redundant calls to
drm_atomic_get_crtc_state and the other helpers are fine.
> + i++;
> + }
> + drm_connector_list_iter_end(&conn_iter);
> +
> + for (j = 0; j < i; j++) {
> + new_crtc_state = drm_atomic_get_crtc_state(state, crtcs_affected[j]);
> + if (IS_ERR(new_crtc_state))
> + return PTR_ERR(new_crtc_state);
> +
> + new_crtc_state->mode_changed = true;
> +
> + ret = drm_atomic_add_affected_connectors(state, crtcs_affected[j]);
> + if (ret)
> + return ret;
> +
> + ret = drm_atomic_add_affected_planes(state, crtcs_affected[j]);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +
> +}
> +#endif
> static void get_freesync_config_for_crtc(
> struct dm_crtc_state *new_crtc_state,
> struct dm_connector_state *new_con_state)
> @@ -7178,6 +7249,15 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
> goto fail;
> }
>
> +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> + if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
> + ret = add_affected_mst_dsc_crtcs(state, crtc);
> + if (ret)
> + goto fail;
> + }
> + }
> +#endif
> /*
> * Add all primary and overlay planes on the CRTC to the state
> * whenever a plane is enabled to maintain correct z-ordering
>
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 06/14] drm/amd/display: Use dc helpers to compute timeslot distribution
2019-08-19 19:21 ` Kazlauskas, Nicholas
@ 2019-08-19 19:35 ` Francis, David
0 siblings, 0 replies; 21+ messages in thread
From: Francis, David @ 2019-08-19 19:35 UTC (permalink / raw)
To: Kazlauskas, Nicholas, dri-devel, amd-gfx; +Cc: Zuo, Jerry
On 8/19/19 11:50 AM, David Francis wrote:
>> We were using drm helpers to convert a timing into its
>> bandwidth, its bandwidth into pbn, and its pbn into timeslots
>>
>> These helpers
>> -Did not take DSC timings into account
>> -Used the link rate and lane count of the link's aux device,
>> which are not the same as the link's current cap
>> -Did not take FEC into account (FEC reduces the PBN per timeslot)
>>
>> Use the DC helpers (dc_bandwidth_in_kbps_from_timing,
>> dc_link_bandwidth_kbps) instead
>>
>> Cc: Jerry Zuo <Jerry.Zuo@amd.com>
>> Signed-off-by: David Francis <David.Francis@amd.com>
>
>Wouldn't this be a good candidate for shared DRM helpers or to modify
>the existing ones to support this usecase?
>
>Seems like this would be shared across drivers.
>
>Nicholas Kazlauskas
>
These functions use information which is not stored in drm structs but tracked in
a driver-specific way
- Whether or not FEC is enabled
- Whether or not DSC is enabled, and with what config
- The current link setting
This could be shifted into drm helpers, but it would require functions with signatures like
drm_dp_calc_pbn_mode(clock, bpp, dsc_bpp)
and
drm_dp_find_vcpi_slots(mst_mgr, pbn, fec_enabled, lane_count, link_rate)
and each driver would need to convert their own structs into those fields
before calling these helpers.
Is that worth it?
>> ---
>> .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 41 ++++---------------
>> 1 file changed, 8 insertions(+), 33 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
>> index 5f2c315b18ba..b32c0790399a 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
>> @@ -189,8 +189,8 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
>> int slots = 0;
>> bool ret;
>> int clock;
>> - int bpp = 0;
>> int pbn = 0;
>> + int pbn_per_timeslot;
>>
>> aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
>>
>> @@ -205,40 +205,15 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
>> mst_port = aconnector->port;
>>
>> if (enable) {
>> - clock = stream->timing.pix_clk_100hz / 10;
>> -
>> - switch (stream->timing.display_color_depth) {
>> -
>> - case COLOR_DEPTH_666:
>> - bpp = 6;
>> - break;
>> - case COLOR_DEPTH_888:
>> - bpp = 8;
>> - break;
>> - case COLOR_DEPTH_101010:
>> - bpp = 10;
>> - break;
>> - case COLOR_DEPTH_121212:
>> - bpp = 12;
>> - break;
>> - case COLOR_DEPTH_141414:
>> - bpp = 14;
>> - break;
>> - case COLOR_DEPTH_161616:
>> - bpp = 16;
>> - break;
>> - default:
>> - ASSERT(bpp != 0);
>> - break;
>> - }
>> -
>> - bpp = bpp * 3;
>> -
>> - /* TODO need to know link rate */
>> + clock = dc_bandwidth_in_kbps_from_timing(&stream->timing);
>>
>> - pbn = drm_dp_calc_pbn_mode(clock, bpp);
>> + /* dc_bandwidth_in_kbps_from_timing already takes bpp into account */
>> + pbn = drm_dp_calc_pbn_mode(clock, 1);
>>
>> - slots = drm_dp_find_vcpi_slots(mst_mgr, pbn);
>> + /* Convert kilobits per second / 64 (for 64 timeslots) to pbn (54/64 megabytes per second) */
>> + pbn_per_timeslot = dc_link_bandwidth_kbps(
>> + stream->link, dc_link_get_link_cap(stream->link)) / (8 * 1000 * 54);
>> + slots = DIV_ROUND_UP(pbn, pbn_per_timeslot);
>> ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, slots);
>>
>> if (!ret)
________________________________________
From: Kazlauskas, Nicholas <Nicholas.Kazlauskas@amd.com>
Sent: August 19, 2019 3:21 PM
To: Francis, David; dri-devel@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
Cc: Zuo, Jerry
Subject: Re: [PATCH 06/14] drm/amd/display: Use dc helpers to compute timeslot distribution
On 8/19/19 11:50 AM, David Francis wrote:
> We were using drm helpers to convert a timing into its
> bandwidth, its bandwidth into pbn, and its pbn into timeslots
>
> These helpers
> -Did not take DSC timings into account
> -Used the link rate and lane count of the link's aux device,
> which are not the same as the link's current cap
> -Did not take FEC into account (FEC reduces the PBN per timeslot)
>
> Use the DC helpers (dc_bandwidth_in_kbps_from_timing,
> dc_link_bandwidth_kbps) instead
>
> Cc: Jerry Zuo <Jerry.Zuo@amd.com>
> Signed-off-by: David Francis <David.Francis@amd.com>
Wouldn't this be a good candidate for shared DRM helpers or to modify
the existing ones to support this usecase?
Seems like this would be shared across drivers.
Nicholas Kazlauskas
> ---
> .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 41 ++++---------------
> 1 file changed, 8 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> index 5f2c315b18ba..b32c0790399a 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> @@ -189,8 +189,8 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
> int slots = 0;
> bool ret;
> int clock;
> - int bpp = 0;
> int pbn = 0;
> + int pbn_per_timeslot;
>
> aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
>
> @@ -205,40 +205,15 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
> mst_port = aconnector->port;
>
> if (enable) {
> - clock = stream->timing.pix_clk_100hz / 10;
> -
> - switch (stream->timing.display_color_depth) {
> -
> - case COLOR_DEPTH_666:
> - bpp = 6;
> - break;
> - case COLOR_DEPTH_888:
> - bpp = 8;
> - break;
> - case COLOR_DEPTH_101010:
> - bpp = 10;
> - break;
> - case COLOR_DEPTH_121212:
> - bpp = 12;
> - break;
> - case COLOR_DEPTH_141414:
> - bpp = 14;
> - break;
> - case COLOR_DEPTH_161616:
> - bpp = 16;
> - break;
> - default:
> - ASSERT(bpp != 0);
> - break;
> - }
> -
> - bpp = bpp * 3;
> -
> - /* TODO need to know link rate */
> + clock = dc_bandwidth_in_kbps_from_timing(&stream->timing);
>
> - pbn = drm_dp_calc_pbn_mode(clock, bpp);
> + /* dc_bandwidth_in_kbps_from_timing already takes bpp into account */
> + pbn = drm_dp_calc_pbn_mode(clock, 1);
>
> - slots = drm_dp_find_vcpi_slots(mst_mgr, pbn);
> + /* Convert kilobits per second / 64 (for 64 timeslots) to pbn (54/64 megabytes per second) */
> + pbn_per_timeslot = dc_link_bandwidth_kbps(
> + stream->link, dc_link_get_link_cap(stream->link)) / (8 * 1000 * 54);
> + slots = DIV_ROUND_UP(pbn, pbn_per_timeslot);
> ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, slots);
>
> if (!ret)
>
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 07/14] drm/amd/display: Initialize DSC PPS variables to 0
2019-08-19 15:50 ` [PATCH 07/14] drm/amd/display: Initialize DSC PPS variables to 0 David Francis
@ 2019-08-19 19:36 ` Kazlauskas, Nicholas
0 siblings, 0 replies; 21+ messages in thread
From: Kazlauskas, Nicholas @ 2019-08-19 19:36 UTC (permalink / raw)
To: Francis, David, dri-devel, amd-gfx
On 8/19/19 11:50 AM, David Francis wrote:
> For DSC MST, sometimes monitors would break out
> in full-screen static. The issue traced back to the
> PPS generation code, where these variables were being used
> uninitialized and were picking up garbage.
>
> memset to 0 to avoid this
>
> Signed-off-by: David Francis <David.Francis@amd.com>
Patches 1-5 and 7 are:
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
> ---
> drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 3 +++
> drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 3 +++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
> index 35c5467e60e8..619ac48edd05 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
> @@ -491,6 +491,9 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
> struct dsc_config dsc_cfg;
> uint8_t dsc_packed_pps[128];
>
> + memset(&dsc_cfg, 0, sizeof(dsc_cfg));
> + memset(dsc_packed_pps, 0, 128);
> +
> /* Enable DSC hw block */
> dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
> dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
> index 379c9e4ac63b..16debe6d89f2 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
> @@ -207,6 +207,9 @@ static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const str
> struct dsc_reg_values dsc_reg_vals;
> struct dsc_optc_config dsc_optc_cfg;
>
> + memset(&dsc_reg_vals, 0, sizeof(dsc_reg_vals));
> + memset(&dsc_optc_cfg, 0, sizeof(dsc_optc_cfg));
> +
> DC_LOG_DSC("Getting packed DSC PPS for DSC Config:");
> dsc_config_log(dsc, dsc_cfg);
> DC_LOG_DSC("DSC Picture Parameter Set (PPS):");
>
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 14/14] drm/amd/display: Trigger modesets on MST DSC connectors
2019-08-19 19:34 ` Kazlauskas, Nicholas
@ 2019-08-19 19:40 ` Francis, David
0 siblings, 0 replies; 21+ messages in thread
From: Francis, David @ 2019-08-19 19:40 UTC (permalink / raw)
To: Kazlauskas, Nicholas, dri-devel, amd-gfx; +Cc: Li, Sun peng (Leo)
>> Whenever a connector on an MST network is attached, detached, or
>> undergoes a modeset, the DSC configs for each stream on that
>> topology will be recalculated. This can change their required
>> bandwidth, requiring a full reprogramming, as though a modeset
>> was performed, even if that stream did not change timing.
>>
>> Therefore, whenever a crtc has drm_atomic_crtc_needs_modeset,
>> for each crtc that shares a MST topology with that stream and
>> supports DSC, add that crtc (and all affected connectors and
>> planes) to the atomic state and set mode_changed on its state
>>
>> Cc: Leo Li <sunpeng.li@amd.com>
>> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
>> Signed-off-by: David Francis <David.Francis@amd.com>
>> ---
>> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 80 +++++++++++++++++++
>> 1 file changed, 80 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> index 145fd73025dc..8d5357aec5e8 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> @@ -6475,7 +6475,78 @@ static int do_aquire_global_lock(struct drm_device *dev,
>>
>> return ret < 0 ? ret : 0;
>> }
>> +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>> +static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
>> +{
>> + struct drm_connector *connector;
>> + struct drm_connector_state *conn_state;
>> + struct drm_connector_list_iter conn_iter;
>> + struct drm_crtc_state *new_crtc_state;
>> + struct amdgpu_dm_connector *aconnector = NULL, *aconnector_to_add;
>> + int i, j, ret;
>> + struct drm_crtc *crtcs_affected[MAX_PIPES] = { 0 }; > +
>> + for_each_new_connector_in_state(state, connector, conn_state, i) {
>> + if (conn_state->crtc != crtc)
>> + continue;
>> +
>> + aconnector = to_amdgpu_dm_connector(connector);
>> + if (!aconnector->port)
>> + aconnector = NULL;
>> + else
>> + break;
>> + }
>> +
>> + if (!aconnector)
>> + return 0;
>> +
>> + i = 0;
>> + drm_connector_list_iter_begin(state->dev, &conn_iter);
>
>I don't like that we're grabbing the global connector lock every single
>time any CRTC undergoes a modeset even for ASICs that don't support DSC.
>
>We do lock everything below in atomic check anyway for FULL updates but
>I'd like to avoid adding more code that does this if possible. Maybe a
>check at the start that only does this if the ASIC has DSC support would
>be OK.
>
Will do
>> + drm_for_each_connector_iter(connector, &conn_iter) {
>> + if (!connector->state || !connector->state->crtc)
>> + continue;
>> +
>> + aconnector_to_add = to_amdgpu_dm_connector(connector);
>> + if (!aconnector_to_add->port)
>> + continue;
>> +
>> + if (aconnector_to_add->port->mgr != aconnector->port->mgr)
>> + continue;
>> +
>> + if (!aconnector_to_add->dc_sink)
>> + continue;
>> +
>> + if (!aconnector_to_add->dc_sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported)
>> + continue;
>>
>> + if (i >= MAX_PIPES)
>> + continue;
>> +
>> + crtcs_affected[i] = connector->state->crtc;
>
>Drop this crtcs_affected array and just perform the logic below right
>here. We don't really need two loops here, redundant calls to
>drm_atomic_get_crtc_state and the other helpers are fine.
>
Unfortunately, calling drm_atomic_get_crtc_state inside
drm_for_each_connector_iter causes a lockdep warning
>> + i++;
>> + }
>> + drm_connector_list_iter_end(&conn_iter);
>> +
>> + for (j = 0; j < i; j++) {
>> + new_crtc_state = drm_atomic_get_crtc_state(state, crtcs_affected[j]);
>> + if (IS_ERR(new_crtc_state))
>> + return PTR_ERR(new_crtc_state);
>> +
>> + new_crtc_state->mode_changed = true;
>> +
>> + ret = drm_atomic_add_affected_connectors(state, crtcs_affected[j]);
>> + if (ret)
>> + return ret;
>> +
>> + ret = drm_atomic_add_affected_planes(state, crtcs_affected[j]);
>> + if (ret)
>> + return ret;
>> + }
>> +
>> + return 0;
>> +
>> +}
>> +#endif
>> static void get_freesync_config_for_crtc(
>> struct dm_crtc_state *new_crtc_state,
>> struct dm_connector_state *new_con_state)
>> @@ -7178,6 +7249,15 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
>> goto fail;
>> }
>>
>> +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>> + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
>> + if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
>> + ret = add_affected_mst_dsc_crtcs(state, crtc);
>> + if (ret)
>> + goto fail;
>> + }
>> + }
>> +#endif
>> /*
>> * Add all primary and overlay planes on the CRTC to the state
>> * whenever a plane is enabled to maintain correct z-ordering
________________________________________
From: Kazlauskas, Nicholas <Nicholas.Kazlauskas@amd.com>
Sent: August 19, 2019 3:34 PM
To: Francis, David; dri-devel@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
Cc: Li, Sun peng (Leo)
Subject: Re: [PATCH 14/14] drm/amd/display: Trigger modesets on MST DSC connectors
On 8/19/19 11:50 AM, David Francis wrote:
> Whenever a connector on an MST network is attached, detached, or
> undergoes a modeset, the DSC configs for each stream on that
> topology will be recalculated. This can change their required
> bandwidth, requiring a full reprogramming, as though a modeset
> was performed, even if that stream did not change timing.
>
> Therefore, whenever a crtc has drm_atomic_crtc_needs_modeset,
> for each crtc that shares a MST topology with that stream and
> supports DSC, add that crtc (and all affected connectors and
> planes) to the atomic state and set mode_changed on its state
>
> Cc: Leo Li <sunpeng.li@amd.com>
> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
> Signed-off-by: David Francis <David.Francis@amd.com>
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 80 +++++++++++++++++++
> 1 file changed, 80 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 145fd73025dc..8d5357aec5e8 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -6475,7 +6475,78 @@ static int do_aquire_global_lock(struct drm_device *dev,
>
> return ret < 0 ? ret : 0;
> }
> +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> +static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
> +{
> + struct drm_connector *connector;
> + struct drm_connector_state *conn_state;
> + struct drm_connector_list_iter conn_iter;
> + struct drm_crtc_state *new_crtc_state;
> + struct amdgpu_dm_connector *aconnector = NULL, *aconnector_to_add;
> + int i, j, ret;
> + struct drm_crtc *crtcs_affected[MAX_PIPES] = { 0 }; > +
> + for_each_new_connector_in_state(state, connector, conn_state, i) {
> + if (conn_state->crtc != crtc)
> + continue;
> +
> + aconnector = to_amdgpu_dm_connector(connector);
> + if (!aconnector->port)
> + aconnector = NULL;
> + else
> + break;
> + }
> +
> + if (!aconnector)
> + return 0;
> +
> + i = 0;
> + drm_connector_list_iter_begin(state->dev, &conn_iter);
I don't like that we're grabbing the global connector lock every single
time any CRTC undergoes a modeset even for ASICs that don't support DSC.
We do lock everything below in atomic check anyway for FULL updates but
I'd like to avoid adding more code that does this if possible. Maybe a
check at the start that only does this if the ASIC has DSC support would
be OK.
> + drm_for_each_connector_iter(connector, &conn_iter) {
> + if (!connector->state || !connector->state->crtc)
> + continue;
> +
> + aconnector_to_add = to_amdgpu_dm_connector(connector);
> + if (!aconnector_to_add->port)
> + continue;
> +
> + if (aconnector_to_add->port->mgr != aconnector->port->mgr)
> + continue;
> +
> + if (!aconnector_to_add->dc_sink)
> + continue;
> +
> + if (!aconnector_to_add->dc_sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported)
> + continue;
>
> + if (i >= MAX_PIPES)
> + continue;
> +
> + crtcs_affected[i] = connector->state->crtc;
Drop this crtcs_affected array and just perform the logic below right
here. We don't really need two loops here, redundant calls to
drm_atomic_get_crtc_state and the other helpers are fine.
> + i++;
> + }
> + drm_connector_list_iter_end(&conn_iter);
> +
> + for (j = 0; j < i; j++) {
> + new_crtc_state = drm_atomic_get_crtc_state(state, crtcs_affected[j]);
> + if (IS_ERR(new_crtc_state))
> + return PTR_ERR(new_crtc_state);
> +
> + new_crtc_state->mode_changed = true;
> +
> + ret = drm_atomic_add_affected_connectors(state, crtcs_affected[j]);
> + if (ret)
> + return ret;
> +
> + ret = drm_atomic_add_affected_planes(state, crtcs_affected[j]);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +
> +}
> +#endif
> static void get_freesync_config_for_crtc(
> struct dm_crtc_state *new_crtc_state,
> struct dm_connector_state *new_con_state)
> @@ -7178,6 +7249,15 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
> goto fail;
> }
>
> +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> + if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
> + ret = add_affected_mst_dsc_crtcs(state, crtc);
> + if (ret)
> + goto fail;
> + }
> + }
> +#endif
> /*
> * Add all primary and overlay planes on the CRTC to the state
> * whenever a plane is enabled to maintain correct z-ordering
>
_______________________________________________
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dri-devel@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2019-08-19 19:40 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-19 15:50 [PATCH 00/14] Display Stream Compression (DSC) for AMD Navi David Francis
2019-08-19 15:50 ` [PATCH 02/14] Revert "drm/amd/display: navi10 bring up skip dsc encoder config" David Francis
[not found] ` <20190819155038.1771-1-David.Francis-5C7GfCeVMHo@public.gmane.org>
2019-08-19 15:50 ` [PATCH 01/14] Revert "drm/amd/display: skip dsc config for navi10 bring up" David Francis
2019-08-19 15:50 ` [PATCH 03/14] Revert "drm/amd/display: add global master update lock for DCN2" David Francis
2019-08-19 15:50 ` [PATCH 04/14] Revert "drm/amd/display: Fix underscan not using proper scaling" David Francis
2019-08-19 15:50 ` [PATCH 05/14] drm/amd/display: Enable SST DSC in DM David Francis
[not found] ` <20190819155038.1771-6-David.Francis-5C7GfCeVMHo@public.gmane.org>
2019-08-19 18:46 ` Mikita Lipski
2019-08-19 15:50 ` [PATCH 06/14] drm/amd/display: Use dc helpers to compute timeslot distribution David Francis
[not found] ` <20190819155038.1771-7-David.Francis-5C7GfCeVMHo@public.gmane.org>
2019-08-19 19:21 ` Kazlauskas, Nicholas
2019-08-19 19:35 ` Francis, David
2019-08-19 15:50 ` [PATCH 07/14] drm/amd/display: Initialize DSC PPS variables to 0 David Francis
2019-08-19 19:36 ` Kazlauskas, Nicholas
2019-08-19 15:50 ` [PATCH 08/14] drm/dp-mst: Parse FEC capability on MST ports David Francis
2019-08-19 15:50 ` [PATCH 09/14] drm/dp-mst: Export symbols for dpcd read/write David Francis
2019-08-19 15:50 ` [PATCH 10/14] drm/dp-mst: Fill branch->num_ports David Francis
2019-08-19 15:50 ` [PATCH 11/14] drm/amd/display: Validate DSC caps on MST endpoints David Francis
2019-08-19 15:50 ` [PATCH 12/14] drm/amd/display: Write DSC enable to MST DPCD David Francis
2019-08-19 15:50 ` [PATCH 13/14] drm/amd/display: MST DSC compute fair share David Francis
2019-08-19 15:50 ` [PATCH 14/14] drm/amd/display: Trigger modesets on MST DSC connectors David Francis
[not found] ` <20190819155038.1771-15-David.Francis-5C7GfCeVMHo@public.gmane.org>
2019-08-19 19:34 ` Kazlauskas, Nicholas
2019-08-19 19:40 ` Francis, David
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