* [v2 0/2] Store QSPI reference clock in kHz for SOCFPGA SOC64
@ 2021-03-24 6:19 Siew Chin Lim
2021-03-24 6:19 ` [v2 1/2] arm: socfpga: Move Stratix10 and Agilex clock manager common code Siew Chin Lim
2021-03-24 6:19 ` [v2 2/2] arm: socfpga: Changed to store QSPI reference clock in kHz Siew Chin Lim
0 siblings, 2 replies; 4+ messages in thread
From: Siew Chin Lim @ 2021-03-24 6:19 UTC (permalink / raw)
To: u-boot
This is the 2cd version of patchset to clean up clock manager code
and store QSPI reference clock in kHz for SOCFPGA SOC64.
This patchset is extracted from "Add Intel Diamond Mesa SoC support" series.
We are in preparation to support new Intel N5X (Diamond Mesa) SOC64 device
and we would like to clean up some code before enable N5X device.
Patch status:
Have changes: Patch 2
Other patches unchanged.
Detail changelog can find in commit message.
v1->v2:
--------
Patch 2:
- Rename mbox_qspi_set_controller_clk_hz function to
cm_set_qspi_controller_clk_hz function and move to clock_manager.c.
- Remove CLOCK_1K macro from socfpga_soc64_common.h
- Sort include file list by alphabetical order in mailbox_s10.c
History:
--------
[v1] https://patchwork.ozlabs.org/project/uboot/cover/20210315143643.33102-1-elly.siew.chin.lim at intel.com/
The first version of this patchset is extracted from "Add Intel Diamond Mesa SoC support" series.
https://patchwork.ozlabs.org/project/uboot/cover/20201110064439.9683-1-elly.siew.chin.lim at intel.com/
This patchset has dependency on:
--------
1. arm: socfpga: Move Stratix10 and Agilex SPL common code
https://patchwork.ozlabs.org/project/uboot/patch/20210315075916.26336-1-elly.siew.chin.lim at intel.com/
2. Restructure Stratix10 and Agilex handoff code
https://patchwork.ozlabs.org/project/uboot/cover/20210315094329.30282-1-elly.siew.chin.lim at intel.com/
Siew Chin Lim (2):
arm: socfpga: Move Stratix10 and Agilex clock manager common code
arm: socfpga: Changed to store QSPI reference clock in kHz
arch/arm/mach-socfpga/clock_manager.c | 43 ++++++++++++++++++++--
arch/arm/mach-socfpga/clock_manager_agilex.c | 6 ---
arch/arm/mach-socfpga/clock_manager_s10.c | 6 ---
arch/arm/mach-socfpga/include/mach/clock_manager.h | 5 +++
.../mach-socfpga/include/mach/clock_manager_s10.h | 1 -
.../include/mach/system_manager_soc64.h | 16 +++++++-
arch/arm/mach-socfpga/mailbox_s10.c | 17 +++++----
7 files changed, 69 insertions(+), 25 deletions(-)
--
2.13.0
^ permalink raw reply [flat|nested] 4+ messages in thread
* [v2 1/2] arm: socfpga: Move Stratix10 and Agilex clock manager common code
2021-03-24 6:19 [v2 0/2] Store QSPI reference clock in kHz for SOCFPGA SOC64 Siew Chin Lim
@ 2021-03-24 6:19 ` Siew Chin Lim
2021-03-24 6:19 ` [v2 2/2] arm: socfpga: Changed to store QSPI reference clock in kHz Siew Chin Lim
1 sibling, 0 replies; 4+ messages in thread
From: Siew Chin Lim @ 2021-03-24 6:19 UTC (permalink / raw)
To: u-boot
Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
arch/arm/mach-socfpga/clock_manager.c | 15 ++++++++++++---
arch/arm/mach-socfpga/clock_manager_agilex.c | 6 ------
arch/arm/mach-socfpga/clock_manager_s10.c | 6 ------
arch/arm/mach-socfpga/include/mach/clock_manager.h | 4 ++++
arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 1 -
5 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index f0b15f770c..be426a5cfb 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -4,12 +4,13 @@
*/
#include <common.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
#include <command.h>
#include <init.h>
#include <wait_bit.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/arch/clock_manager.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -63,6 +64,14 @@ int set_cpu_clk_info(void)
return 0;
}
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64)
+unsigned int cm_get_qspi_controller_clk_hz(void)
+{
+ return readl(socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+}
+#endif
+
#ifndef CONFIG_SPL_BUILD
static int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-socfpga/clock_manager_agilex.c
index 6377f2ce3b..e035c09aae 100644
--- a/arch/arm/mach-socfpga/clock_manager_agilex.c
+++ b/arch/arm/mach-socfpga/clock_manager_agilex.c
@@ -65,12 +65,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void)
return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
}
-u32 cm_get_qspi_controller_clk_hz(void)
-{
- return readl(socfpga_get_sysmgr_addr() +
- SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
-}
-
void cm_print_clock_quick_summary(void)
{
printf("MPU %10d kHz\n",
diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c
index e060e5754e..4b4f0749db 100644
--- a/arch/arm/mach-socfpga/clock_manager_s10.c
+++ b/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -384,12 +384,6 @@ unsigned int cm_get_l4_sp_clk_hz(void)
return clock;
}
-unsigned int cm_get_qspi_controller_clk_hz(void)
-{
- return readl(socfpga_get_sysmgr_addr() +
- SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
-}
-
unsigned int cm_get_spi_controller_clk_hz(void)
{
u32 clock = cm_get_l3_main_clk_hz();
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index 1f734bcd65..0f0cb230fa 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -12,6 +12,10 @@ phys_addr_t socfpga_get_clkmgr_addr(void);
void cm_wait_for_lock(u32 mask);
int cm_wait_for_fsm(void);
void cm_print_clock_quick_summary(void);
+
+#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
+unsigned int cm_get_qspi_controller_clk_hz(void);
+#endif
#endif
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
index cb7923baef..98c3bf1b03 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -15,7 +15,6 @@ unsigned long cm_get_mpu_clk_hz(void);
unsigned long cm_get_sdram_clk_hz(void);
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
-unsigned int cm_get_qspi_controller_clk_hz(void);
unsigned int cm_get_spi_controller_clk_hz(void);
struct cm_config {
--
2.13.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [v2 2/2] arm: socfpga: Changed to store QSPI reference clock in kHz
2021-03-24 6:19 [v2 0/2] Store QSPI reference clock in kHz for SOCFPGA SOC64 Siew Chin Lim
2021-03-24 6:19 ` [v2 1/2] arm: socfpga: Move Stratix10 and Agilex clock manager common code Siew Chin Lim
@ 2021-03-24 6:19 ` Siew Chin Lim
2021-03-24 8:23 ` Tan, Ley Foon
1 sibling, 1 reply; 4+ messages in thread
From: Siew Chin Lim @ 2021-03-24 6:19 UTC (permalink / raw)
To: u-boot
Changed to store QSPI reference clock in kHz instead of Hz in
boot scratch cold0 register for Stratix10 and Agilex.
This patch is in preparation for Intel N5X SDRAM driver
support. Reserved 4 bits for Intel N5X SDRAM driver,
and there will be 28 bits to store QSPI reference clock.
Due to limited bits, QSPI reference clock frequency is
converted to kHz from Hz.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
v2:
- Rename mbox_qspi_set_controller_clk_hz function to
cm_set_qspi_controller_clk_hz function and move to clock_manager.c.
- Remove CLOCK_1K macro from socfpga_soc64_common.h
- Sort include file list by alphabetical order in mailbox_s10.c
---
arch/arm/mach-socfpga/clock_manager.c | 32 ++++++++++++++++++++--
arch/arm/mach-socfpga/include/mach/clock_manager.h | 1 +
.../include/mach/system_manager_soc64.h | 16 ++++++++++-
arch/arm/mach-socfpga/mailbox_s10.c | 17 ++++++------
4 files changed, 55 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index be426a5cfb..9e645a4253 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -65,10 +65,38 @@ int set_cpu_clk_info(void)
}
#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64)
+int cm_set_qspi_controller_clk_hz(u32 clk_hz)
+{
+ u32 reg;
+ u32 clk_khz;
+
+ /*
+ * Store QSPI ref clock and set into sysmgr boot register.
+ * Only clock freq in kHz degree is accepted due to limited bits[27:0]
+ * is reserved for storing the QSPI clock freq into boot scratch cold0
+ * register.
+ */
+ if (clk_hz < 1000)
+ return -EINVAL;
+
+ clk_khz = clk_hz / 1000;
+ printf("QSPI: Reference clock@%d kHz\n", clk_khz);
+
+ reg = (readl(socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_BOOT_SCRATCH_COLD0)) &
+ ~(SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK);
+
+ writel((clk_khz & SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) | reg,
+ socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+
+ return 0;
+}
+
unsigned int cm_get_qspi_controller_clk_hz(void)
{
- return readl(socfpga_get_sysmgr_addr() +
- SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+ return (readl(socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_BOOT_SCRATCH_COLD0) &
+ SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK) * 1000;
}
#endif
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index 0f0cb230fa..df7449b80b 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -14,6 +14,7 @@ int cm_wait_for_fsm(void);
void cm_print_clock_quick_summary(void);
#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
+int cm_set_qspi_controller_clk_hz(u32 clk_hz);
unsigned int cm_get_qspi_controller_clk_hz(void);
#endif
#endif
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index 1eb8e7a904..fc4e17821b 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -42,7 +42,10 @@ void populate_sysmgr_pinmux(void);
#define SYSMGR_SOC64_GPO 0xe4
#define SYSMGR_SOC64_GPI 0xe8
#define SYSMGR_SOC64_MPU 0xf0
-/* store qspi ref clock */
+/*
+ * Bits[31:28] reserved for N5X DDR retention, bits[27:0] reserved for SOC 64-bit
+ * storing qspi ref clock (kHz)
+ */
#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200
/* store osc1 clock freq */
#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204
@@ -85,6 +88,17 @@ void populate_sysmgr_pinmux(void);
#define SYSMGR_SOC64_HPS_OSC_CLK 0x1358
#define SYSMGR_SOC64_IODELAY0 0x1400
+/*
+ * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD0
+ * Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for SOC 64-bit
+ * storing qspi ref clock (kHz)
+ */
+#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0)
+#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK BIT(31)
+#define ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK BIT(30)
+#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28))
+#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28
+
#define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
index 7dcdae8136..101af23855 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -5,14 +5,15 @@
*/
#include <common.h>
-#include <hang.h>
-#include <wait_bit.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
+#include <asm/arch/clock_manager.h>
#include <asm/arch/mailbox_s10.h>
#include <asm/arch/system_manager.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
#include <asm/secure.h>
#include <asm/system.h>
+#include <hang.h>
+#include <wait_bit.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -384,10 +385,10 @@ int mbox_qspi_open(void)
if (ret)
goto error;
- /* We are getting QSPI ref clock and set into sysmgr boot register */
- printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]);
- writel(resp_buf[0],
- socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+ /* Store QSPI controller ref clock frequency */
+ ret = cm_set_qspi_controller_clk_hz(resp_buf[0]);
+ if (ret)
+ goto error;
return 0;
--
2.13.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [v2 2/2] arm: socfpga: Changed to store QSPI reference clock in kHz
2021-03-24 6:19 ` [v2 2/2] arm: socfpga: Changed to store QSPI reference clock in kHz Siew Chin Lim
@ 2021-03-24 8:23 ` Tan, Ley Foon
0 siblings, 0 replies; 4+ messages in thread
From: Tan, Ley Foon @ 2021-03-24 8:23 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> Sent: Wednesday, March 24, 2021 2:20 PM
> To: u-boot at lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Tan, Ley Foon
> <ley.foon.tan@intel.com>; See, Chin Liang <chin.liang.see@intel.com>;
> Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@intel.com>; Westergreen, Dalon
> <dalon.westergreen@intel.com>; Simon Glass <sjg@chromium.org>; Gan,
> Yau Wai <yau.wai.gan@intel.com>; Lim, Elly Siew Chin
> <elly.siew.chin.lim@intel.com>
> Subject: [v2 2/2] arm: socfpga: Changed to store QSPI reference clock in kHz
>
> Changed to store QSPI reference clock in kHz instead of Hz in boot scratch
> cold0 register for Stratix10 and Agilex.
>
> This patch is in preparation for Intel N5X SDRAM driver support. Reserved 4
> bits for Intel N5X SDRAM driver, and there will be 28 bits to store QSPI
> reference clock.
> Due to limited bits, QSPI reference clock frequency is converted to kHz from
> Hz.
>
> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>
> ---
> v2:
> - Rename mbox_qspi_set_controller_clk_hz function to
> cm_set_qspi_controller_clk_hz function and move to clock_manager.c.
> - Remove CLOCK_1K macro from socfpga_soc64_common.h
> - Sort include file list by alphabetical order in mailbox_s10.c
> ---
>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
^ permalink raw reply [flat|nested] 4+ messages in thread
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