Re: [PATCH v4 2/2] soc: mediatek: add mtk-devapc driver

[Chun-Kuang Hu <chunkuang.hu@kernel.org>]

Hi, Neal:

Neal Liu <neal.liu@mediatek.com> 於 2020年7月31日 週五 上午10:52寫道：
>
> Hi Chun-Kuang,
>
> On Fri, 2020-07-31 at 00:14 +0800, Chun-Kuang Hu wrote:
> > Hi, Neal:
> >
> > Neal Liu <neal.liu@mediatek.com> 於 2020年7月29日 週三 下午4:29寫道：
> > >
> > > MediaTek bus fabric provides TrustZone security support and data
> > > protection to prevent slaves from being accessed by unexpected
> > > masters.
> > > The security violation is logged and sent to the processor for
> > > further analysis or countermeasures.
> > >
> > > Any occurrence of security violation would raise an interrupt, and
> > > it will be handled by mtk-devapc driver. The violation
> > > information is printed in order to find the murderer.
> > >
> > > Signed-off-by: Neal Liu <neal.liu@mediatek.com>
> > > ---
> >
> > [snip]
> >
> > > +
> > > +/*
> > > + * devapc_extract_vio_dbg - extract full violation information after doing
> > > + *                          shift mechanism.
> > > + */
> > > +static void devapc_extract_vio_dbg(struct mtk_devapc_context *ctx)
> > > +{
> > > +       const struct mtk_devapc_vio_dbgs *vio_dbgs;
> > > +       struct mtk_devapc_vio_info *vio_info;
> > > +       void __iomem *vio_dbg0_reg;
> > > +       void __iomem *vio_dbg1_reg;
> > > +       u32 dbg0;
> > > +
> > > +       vio_dbg0_reg = ctx->devapc_pd_base + ctx->offset->vio_dbg0;
> > > +       vio_dbg1_reg = ctx->devapc_pd_base + ctx->offset->vio_dbg1;
> > > +
> > > +       vio_dbgs = ctx->vio_dbgs;
> > > +       vio_info = ctx->vio_info;
> > > +
> > > +       /* Starts to extract violation information */
> > > +       dbg0 = readl(vio_dbg0_reg);
> > > +       vio_info->vio_addr = readl(vio_dbg1_reg);
> > > +
> > > +       vio_info->master_id = (dbg0 & vio_dbgs->mstid.mask) >>
> > > +                             vio_dbgs->mstid.start;
> > > +       vio_info->domain_id = (dbg0 & vio_dbgs->dmnid.mask) >>
> > > +                             vio_dbgs->dmnid.start;
> > > +       vio_info->write = ((dbg0 & vio_dbgs->vio_w.mask) >>
> > > +                           vio_dbgs->vio_w.start) == 1;
> > > +       vio_info->read = ((dbg0 & vio_dbgs->vio_r.mask) >>
> > > +                         vio_dbgs->vio_r.start) == 1;
> > > +       vio_info->vio_addr_high = (dbg0 & vio_dbgs->addr_h.mask) >>
> > > +                                 vio_dbgs->addr_h.start;
> >
> >
> > I would like to define the type of ctx->vio_info to be
> >
> > struct mtk_devapc_vio_dbgs {
> >     u32 mstid:16;
> >     u32 dmnid:6;
> >     u32 vio_w:1;
> >     u32 vio_r:1;
> >     u32 addr_h:4;
> >     u32 resv:4;
> > };
> >
> > so the code would like the simple way
> >
> > ctx->vio_info = (struct mtk_devapc_vio_dbgs)readl(vio_dbg1_reg);
> >
>
> This idea looks great! Is there any possible to pass the bit layout by
> DT data, and still make this operation simple?
> Why am I asking this question is because this bit layout is platform
> dependent.

I doubt these info would be in a single 32-bits register for all
future SoC. If they are not in single 32-bits register, you may create
a vio_dbgs_type in DT data, and the code may be

if (ctx->vio_dbgs_type == VIO_DBGS_TYPE_MTxxxx) {
    ctx->vio_info = (struct mtk_devapc_vio_dbgs)readl(vio_dbg1_reg);
} else if (ctx->vio_dbgs_type == VIO_DBGS_TYPE_MTyyyy) {
    ctx->vio_info->mstid = readl(vio_mstid_reg);
    ctx->vio_info->dmnid = readl(vio_dmnid_reg);
    ctx->vio_info->vio_w = readl(vio_vio_w_reg);
    ctx->vio_info->vio_r = readl(vio_vio_r_reg);
}

I think we need not to consider how the future would be. Once the
second SoC driver is upstreaming, we could find out the best solution
for it.

Regards,
Chun-Kuang.

>
> > Regards,
> > Chun-Kuang.
> >
> > > +
> > > +       devapc_vio_info_print(ctx);
> > > +}
> > > +
>