From: Anup Patel <anup@brainfault.org>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: Alistair Francis <alistair.francis@wdc.com>,
Anup Patel <anup.patel@wdc.com>,
Atish Patra <atish.patra@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
Bin Meng <bin.meng@windriver.com>
Subject: Re: [PATCH] riscv: Add SiFive drivers to rv32_defconfig
Date: Thu, 16 Jul 2020 18:43:03 +0530 [thread overview]
Message-ID: <CAAhSdy0==OEUUs6-+0g=kogqm2J=64XFiacNL7HdgZwyS-3hWA@mail.gmail.com> (raw)
In-Reply-To: <1594874393-23620-1-git-send-email-bmeng.cn@gmail.com>
On Thu, Jul 16, 2020 at 10:10 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This adds SiFive drivers to rv32_defconfig, to keep in sync with the
> 64-bit config. This is useful when testing 32-bit kernel with QEMU
> 'sifive_u' 32-bit machine.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
> arch/riscv/configs/rv32_defconfig | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig
> index 05bbf52..8759501 100644
> --- a/arch/riscv/configs/rv32_defconfig
> +++ b/arch/riscv/configs/rv32_defconfig
> @@ -14,6 +14,7 @@ CONFIG_CHECKPOINT_RESTORE=y
> CONFIG_BLK_DEV_INITRD=y
> CONFIG_EXPERT=y
> CONFIG_BPF_SYSCALL=y
> +CONFIG_SOC_SIFIVE=y
> CONFIG_SOC_VIRT=y
> CONFIG_ARCH_RV32I=y
> CONFIG_SMP=y
> @@ -61,6 +62,8 @@ CONFIG_HVC_RISCV_SBI=y
> CONFIG_VIRTIO_CONSOLE=y
> CONFIG_HW_RANDOM=y
> CONFIG_HW_RANDOM_VIRTIO=y
> +CONFIG_SPI=y
> +CONFIG_SPI_SIFIVE=y
> # CONFIG_PTP_1588_CLOCK is not set
> CONFIG_POWER_RESET=y
> CONFIG_DRM=y
> @@ -76,6 +79,8 @@ CONFIG_USB_OHCI_HCD=y
> CONFIG_USB_OHCI_HCD_PLATFORM=y
> CONFIG_USB_STORAGE=y
> CONFIG_USB_UAS=y
> +CONFIG_MMC=y
> +CONFIG_MMC_SPI=y
> CONFIG_RTC_CLASS=y
> CONFIG_VIRTIO_PCI=y
> CONFIG_VIRTIO_BALLOON=y
> --
> 2.7.4
>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup@brainfault.org>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: Bin Meng <bin.meng@windriver.com>,
Anup Patel <anup.patel@wdc.com>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>, Atish Patra <atish.patra@wdc.com>,
Alistair Francis <alistair.francis@wdc.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
linux-riscv <linux-riscv@lists.infradead.org>
Subject: Re: [PATCH] riscv: Add SiFive drivers to rv32_defconfig
Date: Thu, 16 Jul 2020 18:43:03 +0530 [thread overview]
Message-ID: <CAAhSdy0==OEUUs6-+0g=kogqm2J=64XFiacNL7HdgZwyS-3hWA@mail.gmail.com> (raw)
In-Reply-To: <1594874393-23620-1-git-send-email-bmeng.cn@gmail.com>
On Thu, Jul 16, 2020 at 10:10 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This adds SiFive drivers to rv32_defconfig, to keep in sync with the
> 64-bit config. This is useful when testing 32-bit kernel with QEMU
> 'sifive_u' 32-bit machine.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
> arch/riscv/configs/rv32_defconfig | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig
> index 05bbf52..8759501 100644
> --- a/arch/riscv/configs/rv32_defconfig
> +++ b/arch/riscv/configs/rv32_defconfig
> @@ -14,6 +14,7 @@ CONFIG_CHECKPOINT_RESTORE=y
> CONFIG_BLK_DEV_INITRD=y
> CONFIG_EXPERT=y
> CONFIG_BPF_SYSCALL=y
> +CONFIG_SOC_SIFIVE=y
> CONFIG_SOC_VIRT=y
> CONFIG_ARCH_RV32I=y
> CONFIG_SMP=y
> @@ -61,6 +62,8 @@ CONFIG_HVC_RISCV_SBI=y
> CONFIG_VIRTIO_CONSOLE=y
> CONFIG_HW_RANDOM=y
> CONFIG_HW_RANDOM_VIRTIO=y
> +CONFIG_SPI=y
> +CONFIG_SPI_SIFIVE=y
> # CONFIG_PTP_1588_CLOCK is not set
> CONFIG_POWER_RESET=y
> CONFIG_DRM=y
> @@ -76,6 +79,8 @@ CONFIG_USB_OHCI_HCD=y
> CONFIG_USB_OHCI_HCD_PLATFORM=y
> CONFIG_USB_STORAGE=y
> CONFIG_USB_UAS=y
> +CONFIG_MMC=y
> +CONFIG_MMC_SPI=y
> CONFIG_RTC_CLASS=y
> CONFIG_VIRTIO_PCI=y
> CONFIG_VIRTIO_BALLOON=y
> --
> 2.7.4
>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2020-07-16 13:13 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-16 4:39 [PATCH] riscv: Add SiFive drivers to rv32_defconfig Bin Meng
2020-07-16 4:39 ` Bin Meng
2020-07-16 13:13 ` Anup Patel [this message]
2020-07-16 13:13 ` Anup Patel
2020-07-16 16:39 ` Alistair Francis
2020-07-16 16:39 ` Alistair Francis
2020-08-18 9:29 ` Bin Meng
2020-08-18 9:29 ` Bin Meng
2020-08-20 18:00 ` Palmer Dabbelt
2020-08-20 18:00 ` Palmer Dabbelt
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